TSV6390, TSV6390A, TSV6391, TSV6391A - Farnell Element 14 - Revenir à l'accueil
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Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:35 5.9M
Farnell-RASPBERRY-PI..> 22-Jul-2014 12:35 5.9M
Farnell-Dremel-Exper..> 22-Jul-2014 12:34 1.6M
Farnell-STM32F103x8-..> 22-Jul-2014 12:33 1.6M
Farnell-BD6xxx-PDF.htm 22-Jul-2014 12:33 1.6M
Farnell-L78S-STMicro..> 22-Jul-2014 12:32 1.6M
Farnell-RaspiCam-Doc..> 22-Jul-2014 12:32 1.6M
Farnell-SB520-SB5100..> 22-Jul-2014 12:32 1.6M
Farnell-iServer-Micr..> 22-Jul-2014 12:32 1.6M
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Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:31 2.4M
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Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30 4.7M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:29 4.8M
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Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27 5.9M
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Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47 837K
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Farnell-Silica-Gel-M..> 07-Jul-2014 19:46 1.2M
Farnell-TKC2-Dusters..> 07-Jul-2014 19:46 1.2M
Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46 1.2M
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Farnell-Araldite-Fus..> 07-Jul-2014 19:45 1.2M
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Farnell-safety-data-..> 07-Jul-2014 19:44 1.4M
Farnell-A-4-Hardener..> 07-Jul-2014 19:44 1.4M
Farnell-CC-Debugger-..> 07-Jul-2014 19:44 1.5M
Farnell-MSP430-Hardw..> 07-Jul-2014 19:43 1.8M
Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43 1.6M
Farnell-CC2531-USB-H..> 07-Jul-2014 19:43 1.8M
Farnell-Alimentation..> 07-Jul-2014 19:43 1.8M
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Farnell-LPC3220-30-4..> 16-Jul-2014 09:02 2.2M
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Farnell-Encodeur-USB..> 08-Jul-2014 18:56 2.0M
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Farnell-2020-Manuel-..> 08-Jul-2014 18:55 2.1M
Farnell-Synchronous-..> 08-Jul-2014 18:54 2.1M
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Farnell-L293d-Texas-..> 08-Jul-2014 18:53 2.2M
Farnell-SN54HC244-SN..> 08-Jul-2014 18:52 2.3M
Farnell-MAX232-MAX23..> 08-Jul-2014 18:52 2.3M
Farnell-High-precisi..> 08-Jul-2014 18:51 2.3M
Farnell-SMU-Instrume..> 08-Jul-2014 18:51 2.3M
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Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
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Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
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Farnell-24AA024-24LC..> 23-Jun-2014 10:26 3.1M
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Farnell-Alimentation..> 14-Jun-2014 18:24 2.5M
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Farnell-DC-Fan-type-..> 14-Jun-2014 09:48 2.5M
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Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27 2.4M
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Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464KTSV6390, TSV6390A, TSV6391, TSV6391A Micropower (60 μA), wide bandwidth (2.4 MHz) CMOS op-amps Features ■ Low offset voltage: 500 μV max (A version) ■ Low power consumption: 60 μA typ at 5 V ■ Low supply voltage: 1.5 V – 5.5 V ■ Gain bandwidth product: 2.4 MHz typical ■ Stable in gain configuration (-3 or +4) ■ Low power shutdown mode: 5 nA typical ■ High output current: 63 mA at VCC= 5 V ■ Low input bias current: 1 pA typical ■ Rail-to-rail input and output ■ Extended temperature range: -40°C to +125°C ■ 4 kV human body model Applications ■ Battery-powered applications ■ Portable devices ■ Signal conditioning ■ Active filtering ■ Medical instrumentation Description The TSV6390 and TSV6391 devices are single operational amplifiers offering low voltage, low power operation and rail-to-rail input and output. With a very low input bias current and low offset voltage (500 μV maximum for the A version), the TSV6390 and TSV6391 are ideal for applications requiring precision. The devices can operate at power supplies ranging from 1.5 to 5.5 V, and are therefore ideal for battery-powered devices, extending battery life. When used with a gain (above -3 or +4), these products feature an excellent speed/power consumption ratio, offering a 2.4 MHz gain bandwidth product while consuming only 60 μA at a 5 V supply voltage. The TSV6390 comes with a shutdown function. Both the TSV6390 and TSV6391 have a high tolerance to ESD, sustaining 4 kV for the human body model. Additionally, they are offered in micropackages, SC70-6 and SOT23-6 for the TSV6390 and SC70-5 and SOT23-5 for the TSV6391. They are guaranteed for industrial temperature ranges from -40° C to +125° C. All these features combined make the TSV6390 and TSV6391 ideal for sensor interfaces, battery-supplied and portable applications, as well as active filtering. TSV6390ICT/ILT TSV6391ICT/ILT SC70-6/SOT23-6 SC70-5/SOT23-5 VCCIn+ In- Out 1 2 3 6 4 +_ 5 SHDN VCC+ VCCIn+ In- Out 1 2 3 5 4 +_ VCC+ www.st.com Contents TSV6390, TSV6390A, TSV6391, TSV6391A 2/22 Doc ID 17118 Rev 1 Contents 1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Shutdown function (TSV6390) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 Optimization of DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Driving resistive and capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8 Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 SOT23-6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 SC70-5 (or SOT323-5) package mechanical data . . . . . . . . . . . . . . . . . . 17 4.4 SC70-6 (or SOT323-6) package mechanical data . . . . . . . . . . . . . . . . . . 18 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TSV6390, TSV6390A, TSV6391, TSV6391A Absolute maximum ratings and operating conditions Doc ID 17118 Rev 1 3/22 1 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol Parameter Value Unit VCC Supply voltage(1) 1. All voltage values, except differential voltages, are with respect to network ground terminal. 6 V Vid Differential input voltage (2) 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. ±VCC V Vin Input voltage (3) 3. VCC-Vin must not exceed 6 V, Vin must not exceed 6 V. VCC- -0.2 to VCC+ +0.2 V Iin Input current (4) 4. Input current must be limited by a resistor in series with the inputs. 10 mA SHDN Shutdown voltage(3) VCC- -0.2 to VCC+ +0.2 V Tstg Storage temperature -65 to +150 °C Rthja Thermal resistance junction to ambient(5)(6) SC70-5 SOT23-5 SOT23-6 SC70-6 5. Short-circuits can cause excessive heating and destructive dissipation. 6. Rth are typical values. 205 250 240 232 °C/W Tj Maximum junction temperature 150 °C ESD HBM: human body model(7) 7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 4 kV MM: machine model(8) 8. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating. 300 V CDM: charged device model(9) 9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to the ground. 1.5 kV Latch-up immunity 200 mA Table 2. Operating conditions Symbol Parameter Value Unit VCC Supply voltage 1.5 to 5.5 V Vicm Common mode input voltage range VCC- -0.1 to VCC+ +0.1 V Toper Operating free air temperature range -40 to +125 °C Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 4/22 Doc ID 17118 Rev 1 2 Electrical characteristics Table 3. Electrical characteristics at VCC+ = +1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV6390-TSV6391 TSV6390A-TSV6391A 3 0.5 mV Tmin < Top < Tmax TSV6390-TSV6391 TSV6390A-TSV6391A 4.5 2 DVio Input offset voltage drift 2 μV/°C Iio Input offset current (1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 Iib Input bias current(1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 CMR Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 1.8 V, Vout = 0.9 V 53 74 dB Tmin < Top < Tmax 51 Avd Large signal voltage gain RL= 10 kΩ, Vout = 0.5 V to 1.3 V 85 95 dB Tmin < Top < Tmax 80 VOH High level output voltage RL = 10 kΩ 35 5 mV Tmin < Top < Tmax 50 VOL Low level output voltage RL = 10 kΩ 4 35 mV Tmin < Top < Tmax 50 Iout Isink Vout = 1.8 V 6 12 mA Tmin < Top < Tmax 4 Isource Vout = 0 V 6 10 mA Tmin < Top < Tmax 4 ICC Supply current SHDN = VCC No load, Vout = VCC/2 40 50 60 μA Tmin < Top < Tmax 62 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2 MHz Gain Minimum gain for stability Phase margin = 60°, Rf = 10 kΩ, RL = 10 kΩ, CL = 20 pF +4 -3 V/V SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to 1.3 V 0.7 V/μs en Equivalent input noise voltage f = 1 kHz f = 10 kHz 60 33 1. Guaranteed by design. nV Hz ----------- TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics Doc ID 17118 Rev 1 5/22 Table 4. Shutdown characteristics VCC = 1.8 V (TSV6390) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance ICC Supply current in shutdown mode (all operators) SHDN = VCC- 2.5 50 nA Tmin < Top < 85° C 200 nA Tmin < Top < 125° C 1.5 μA ton Amplifier turn-on time RL = 2 kΩ, Vout = VCC- to VCC - + 0.2 V 300 ns toff Amplifier turn-off time RL = 2 kΩ, Vout = VCC+ - 0.5 V to VCC+ - 0.7 V 20 ns VIH SHDN logic high 1.3 V VIL SHDN logic low 0.5 V IIH SHDN current high SHDN = VCC+ 10 pA IIL SHDN current low SHDN = VCC- 10 pA IOLeak Output leakage in shutdown mode SHDN = VCC- 50 pA Tmin < Top < Tmax 1 nA Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 6/22 Doc ID 17118 Rev 1 Table 5. VCC+ = +3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV6390-TSV6391 TSV6390A-TSV6391A 3 0.5 mV Tmin < Top < Tmax TSV6390-TSV6391 TSV6390A-TSV6391A 4.5 2 DVio Input offset voltage drift 2 μV/°C Iio Input offset current(1) 1 10 pA Tmin < Top < Tmax 1 100 Iib Input bias current(1) 1 10 pA Tmin < Top < Tmax 1 100 CMR Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 3.3 V, Vout = 1.65 V 57 79 dB Tmin < Top < Tmax 53 Avd Large signal voltage gain RL = 10 kΩ, Vout = 0.5 V to 2.8 V 88 98 dB Tmin < Top < Tmax 83 VOH High level output voltage RL = 10 kΩ 35 6 mV Tmin. < Top < Tmax 50 VOL Low level output voltage RL = 10 kΩ 7 35 mV Tmin < Top < Tmax 50 Iout Isink Vout = 3.3 V 23 45 mA Tmin < Top < Tmax 20 42 Isource Vout = 0 V 23 38 mA Tmin < Top < Tmax 20 ICC Supply current SHDN = VCC No load, Vout= VCC/2 43 55 64 μA Tmin < Top < Tmax 66 μA AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2.2 MHz Gain Minimum gain for stability Phase margin = 60°, Rf = 10 kΩ, RL = 10 kΩ, CL = 20 pF, +4 -3 V/V SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to 2.8 V 0.9 V/μs en Equivalent input noise voltage f = 1 kHz 65 1. Guaranteed by design. nV Hz ----------- TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics Doc ID 17118 Rev 1 7/22 Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV6390-TSV6391 TSV6390A-TSV6391A 3 0.5 mV Tmin < Top < Tmax TSV6390-TSV6391 TSV6390A-TSV6391A 4.5 2 mV DVio Input offset voltage drift 2 μV/°C Iio Input offset current(1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 Iib Input bias current(1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 CMR Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 5 V, Vout = 2.5 V 60 80 dB Tmin < Top < Tmax 55 SVR Supply voltage rejection ratio 20 log (ΔVCC/ΔVio) VCC = 1.8 to 5 V 75 93 dB Tmin < Top < Tmax 73 Avd Large signal voltage gain RL= 10 kΩ, Vout= 0.5 V to 4.5 V 89 98 dB Tmin < Top < Tmax 84 VOH High level output voltage RL = 10 kΩ 35 7 mV Tmin < Top < Tmax 50 VOL Low level output voltage RL = 10 kΩ 6 35 mV Tmin < Top < Tmax 50 Iout Isink Vout = 5 V 40 65 mA Tmin < Top < Tmax 35 Isource Vout = 0 V 40 72 mA Tmin < Top < Tmax 35 ICC Supply current SHDN = VCC No load, Vout=VCC/2 50 60 69 μA Tmin < Top < Tmax 72 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2.4 MHz Gain Minimum gain for stability Phase margin = 60°, Rf = 10 kΩ, RL = 10 kΩ, CL = 20 pF, +4 -3 V/V SR Slew rate RL = 10 kΩ, CL = 100 pF 1.1 V/μs Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 8/22 Doc ID 17118 Rev 1 en Equivalent input noise voltage f = 1 kHz f = 10 kHz 60 33 THD+N Total harmonic distortion + noise Av = -10, fin = 1 kHz, R= 100 kΩ, Vicm = Vcc/2, Vin = 40 mVpp 0.11 % 1. Guaranteed by design. Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and RL connected to VCC/2 (unless otherwise specified) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit nV Hz ----------- Table 7. Shutdown characteristics VCC = 5 V (TSV6390) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance ICC Supply current in shutdown mode (all operators) SHDN = VCC- 5 50 nA Tmin < Top < 85° C 200 nA Tmin < Top < 125° C 1.5 μA ton Amplifier turn-on time RL = 2 kΩ, Vout = VCC- to VCC - + 0.2 V 300 ns toff Amplifier turn-off time RL = 2 Ω, Vout = VCC+ - 0.5 V to VCC+ - 0.7 V 30 ns VIH SHDN logic high 4.5 V VIL SHDN logic low 0.5 V IIH SHDN current high SHDN = VCC+ 10 pA IIL SHDN current low SHDN = VCC- 10 pA IOLeak Output leakage in shutdown mode SHDN = VCC- 50 pA Tmin < Top < Tmax 1 nA TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics Doc ID 17118 Rev 1 9/22 Figure 1. Supply current vs. supply voltage at Vicm = VCC/2 Figure 2. Output current vs. output voltage at VCC = 1.5 V Figure 3. Output current vs. output voltage at VCC = 5 V Figure 4. Peaking at closed loop gain = -10 10000 100000 1000000 0 5 10 15 20 VCC=5V VCC=1.5V Closed loop gain = -10 T=25 C,CLoad=100pF, Vicm=VCC/2, RLoad=2.2kΩ for Iout giving minimum stability on a typical part Gain (dB) Frequency (Hz) Figure 5. Peaking at closed loop gain = -3 at VCC = 1.5 V Figure 6. Peaking at closed loop gain = -3 at VCC = 5 V 10000 100000 1000000 0 2 4 6 8 10 12 14 RLoad=100kΩ RLoad T=25 C, V =2.2kΩ icm=VCC/2 ACL=-3, VCC=1.5V CLoad=33pF RLoad= 100kΩ connected to VCC/2 RLoad= 2.2kΩ for Iout giving minimum stability on a typical part Gain (dB) Frequency (Hz) 10000 100000 1000000 0 2 4 6 8 10 12 14 RLoad=2.2kΩ T=25 C, Vicm=VCC/2 ACL=-3, VCC=5V CLoad=33pF RLoad=100kΩ RLoad= 100kΩ connected to VCC/2 RLoad= 2.2kΩ for Iout giving minimum stability on a typical part Gain (dB) Frequency (Hz) Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 10/22 Doc ID 17118 Rev 1 Figure 7. Positive slew rate vs. supply voltage Figure 8. Negative slew rate vs. supply voltage Figure 9. Distortion + noise vs. output voltage at VCC = 1.8 V Figure 10. Distortion + noise vs. output voltage at VCC = 5 V RLoad=2kΩ, CLoad=100pF, ACL=−10 Vin: from 0.5V to VCC+− 0.5V SR calculated from 10% to 90% Vicm=VCC/2 T=25°C T=125°C T=−40°C Slew rate (V/ s) Supply voltage (V) T=25°C RLoad=2kΩ, CLoad=100pF, ACL=−10 Vin: from VCC+−0.5V to 0.5V SR calculated from 10% to 90% Vicm=VCC/2 T=125°C T=−40°C Slew rate (V/ s) Supply voltage (V) Ω Ω THD + N (%) Output voltage (Vrms) Ω Ω THD + N (%) Ouput voltage (Vrms) Figure 11. Slew rate timing Figure 12. Noise vs. frequency at VCC = 5 V Vin Vout RLoad=2kΩ, CLoad=100pF, Vicm=VCC/2, ACL=−10 T=25°C, VCC=5V Amplitude (V) Time (μs) 10 100 1000 10000 10 100 Equivalent Input Voltage Noise (nV/VHz) Vcc=5V Tamb=25 C Vicm=4.5V Vicm=2.5V TSV6390, TSV6390A, TSV6391, TSV6391A Application information Doc ID 17118 Rev 1 11/22 3 Application information 3.1 Operating voltages The TSV6390 and TSV6391 can operate from 1.5 to 5.5 V. Their parameters are fully specified for 1.8, 3.3 and 5 V power supplies. However, the parameters are very stable in the full VCC range and several characterization curves show the TSV639x characteristics at 1.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40° C to +125° C. 3.2 Rail-to-rail input The TSV6390 and TSV6391 are built with two complementary PMOS and NMOS input differential pairs. The devices have a rail-to-rail input, and the input common mode range is extended from VCC- -0.1 V to VCC+ +0.1 V. The transition between the two pairs appears at VCC+ -0.7 V. In the transition region, the performance of CMRR, PSRR, Vio and THD is slightly degraded (as shown in Figure 13 and Figure 14 for Vio vs. Vicm). The devices are guaranteed without phase reversal. 3.3 Rail-to-rail output The operational amplifiers’ output levels can go close to the rails: 35 mV maximum above and below the rail when connected to a 10 kΩ resistive load to VCC/2. 3.4 Shutdown function (TSV6390) The operational amplifier is enabled when the SHDN pin is pulled high. To disable the amplifier, the SHDN must be pulled down to VCC-. When in shutdown mode, the amplifier’s output is in a high impedance state. The SHDN pin must never be left floating, but tied to VCC+ or VCC-. Figure 13. Input offset voltage vs input common mode at VCC = 1.5 V Figure 14. Input offset voltage vs input common mode at VCC = 5 V -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 Input Offset Voltage (mV) Input Common Mode Voltage (V) 0.0 1.0 2.0 3.0 4.0 5.0 -0.4 -0.2 0.0 0.2 0.4 Input Offset Voltage (mV) Input Common Mode Voltage (V) Application information TSV6390, TSV6390A, TSV6391, TSV6391A 12/22 Doc ID 17118 Rev 1 The turn-on and turn-off times are calculated for an output variation of ±200 mV (Figure 15 and Figure 16 show the test configurations). Figure 15. Test configuration for turn-on time (Vout pulled down) Figure 16. Test configuration for turn-off time (Vout pulled down) + VCC GND 2 KΩ + - DUT GND VCC - 0.5 V + VCC GND 2 KΩ + - DUT GND VCC - 0.5 V Figure 17. Turn-on time, VCC = 5 V, Vout pulled down, T = 25° C Figure 18. Turn-off time, VCC= 5 V, Vout pulled down, T = 25° C Shutdown pulse Vout Vcc = 5V T = 25°C Voltage (V) Time( s) Shutdown pulse Vout Vcc = 5V T = 25°C Output voltage (V) Time( s) TSV6390, TSV6390A, TSV6391, TSV6391A Application information Doc ID 17118 Rev 1 13/22 3.5 Optimization of DC and AC parameters These devices use an innovative approach to reduce the spread of the main DC and AC parameters. An internal adjustment achieves a very narrow spread of the current consumption (60 μA typical, min/max at ±17 %). Parameters linked to the current consumption value, such as GBP, SR and AVd, benefit from this narrow dispersion. 3.6 Driving resistive and capacitive loads These products are micropower, low-voltage operational amplifiers optimized to drive rather large resistive loads, above 2 kΩ. For lower resistive loads, the THD level may significantly increase. These operational amplifiers have a relatively low internal compensation capacitor, making them very fast while consuming very little. They are ideal when used in a non-inverting configuration or in an inverting configuration in the following conditions. ● IGainI ≥ 3 in an inverting configuration (CL = 20 pF, RL = 100 kΩ) or IgainI ≥ 10 (CL = 100 pF, RL = 100 kΩ) ● Gain ≥ +4 in a non-inverting configuration (CL = 20 pF, RL = 100 kΩ) or gain ≥ +11 (CL = 100 pF, RL= 100 kΩ) As these operational amplifiers are not unity gain stable, for a low closed-loop gain it is recommended to use the TSV62x (29 μA, 420 kHz) or TSV63x (60 μA, 880 kHz) which are unity gain stable. 3.7 PCB layouts For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins. 3.8 Macromodel An accurate macromodel of the TSV6390 and TSV6391 is available on STMicroelectronics’ web site at www.st.com. This model is a trade-off between accuracy and complexity (that is, time simulation) of the TSV639x operational amplifiers. It emulates the nominal performances of a typical device within the specified operating conditions mentioned in the datasheet. It also helps to validate a design approach and to select the right operational amplifier, but it does not replace on-board measurements. Table 8. Related products Part # Icc (μA) at 5 V GBP (MHz) SR (V/μs) Minimum gain for stability (CLoad = 100 pF) TSV620-1 29 0.42 0.14 1 TSV6290-1 29 1.3 0.5 +11 TSV630-1 60 0.88 0.34 1 TSV6390-1 60 2.4 1.1 +11 Package information TSV6390, TSV6390A, TSV6391, TSV6391A 14/22 Doc ID 17118 Rev 1 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. TSV6390, TSV6390A, TSV6391, TSV6391A Package information Doc ID 17118 Rev 1 15/22 4.1 SOT23-5 package mechanical data Figure 19. SOT23-5L package mechanical drawing Table 9. SOT23-5L package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.20 1.45 0.035 0.047 0.057 A1 0.15 0.006 A2 0.90 1.05 1.30 0.035 0.041 0.051 B 0.35 0.40 0.50 0.013 0.015 0.019 C 0.09 0.15 0.20 0.003 0.006 0.008 D 2.80 2.90 3.00 0.110 0.114 0.118 D1 1.90 0.075 e 0.95 0.037 E 2.60 2.80 3.00 0.102 0.110 0.118 F 1.50 1.60 1.75 0.059 0.063 0.069 L 0.10 0.35 0.60 0.004 0.013 0.023 K 0° 10° Package information TSV6390, TSV6390A, TSV6391, TSV6391A 16/22 Doc ID 17118 Rev 1 4.2 SOT23-6 package mechanical data Figure 20. SOT23-6L package mechanical drawing Table 10. SOT23-6L package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.45 0.035 0.057 A1 0.10 0.004 A2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.013 0.019 c 0.09 0.20 0.003 0.008 D 2.80 3.05 0.110 0.120 E 1.50 1.75 0.060 0.069 e 0.95 0.037 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 ° 0 10° TSV6390, TSV6390A, TSV6391, TSV6391A Package information Doc ID 17118 Rev 1 17/22 4.3 SC70-5 (or SOT323-5) package mechanical data Figure 21. SC70-5 (or SOT323-5) package mechanical drawing Table 11. SC70-5 (or SOT323-5) package mechanical data Ref Dimensions Millimeters Inches Min Typ Max Min Typ Max A 0.80 1.10 0.315 0.043 A1 0.10 0.004 A2 0.80 0.90 1.00 0.315 0.035 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 D 1.80 2.00 2.20 0.071 0.079 0.087 E 1.80 2.10 2.40 0.071 0.083 0.094 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 0.025 e1 1.30 0.051 L 0.26 0.36 0.46 0.010 0.014 0.018 < 0° 8° SEATING PLANE GAUGE PLANE DIMENSIONS IN MM SIDE VIEW TOP VIEW COPLANAR LEADS Package information TSV6390, TSV6390A, TSV6391, TSV6391A 18/22 Doc ID 17118 Rev 1 4.4 SC70-6 (or SOT323-6) package mechanical data Figure 22. SC70-6 (or SOT323-6) package mechanical drawing Table 12. SC70-6 (or SOT323-6) package mechanical data Ref Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.80 1.10 0.031 0.043 A1 0.10 0.004 A2 0.80 1.00 0.031 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.18 0.004 0.007 D 1.80 2.20 0.071 0.086 E 1.15 1.35 0.045 0.053 e 0.65 0.026 HE 1.80 2.40 0.071 0.094 L 0.10 0.40 0.004 0.016 Q1 0.10 0.40 0.004 0.016 TSV6390, TSV6390A, TSV6391, TSV6391A Package information Doc ID 17118 Rev 1 19/22 Figure 23. SC70-6 (or SOT323-6) package footprint Ordering information TSV6390, TSV6390A, TSV6391, TSV6391A 20/22 Doc ID 17118 Rev 1 5 Ordering information Table 13. Order codes Part number Temperature range Package Packing Marking TSV6390ILT -40°C to +125°C SOT23-6 Tape & reel K109 TSV6390ICT SC70-6 K19 TSV6390AILT SOT23-6 K142 TSV6390AICT SC70-6 K42 TSV6391ILT SOT23-5 K108 TSV6391ICT SC70-5 K20 TSV6391AILT SOT23-5 K141 TSV6391AICT SC70-5 K41 TSV6390, TSV6390A, TSV6391, TSV6391A Revision history Doc ID 17118 Rev 1 21/22 6 Revision history Table 14. Document revision history Date Revision Changes 09-Mar-2010 1 Initial release. TSV6390, TSV6390A, TSV6391, TSV6391A 22/22 Doc ID 17118 Rev 1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com General Description The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E +3.0V-powered EIA/TIA-232 and V.28/V.24 communications interface devices feature low power consumption, high data-rate capabilities, and enhanced electrostatic-discharge (ESD) protection. The enhanced ESD structure protects all transmitter outputs and receiver inputs to ±15kV using IEC 1000-4-2 Air-Gap Discharge, ±8kV using IEC 1000-4-2 Contact Discharge (±9kV for MAX3246E), and ±15kV using the Human Body Model. The logic and receiver I/O pins of the MAX3237E are protected to the above standards, while the transmitter output pins are protected to ±15kV using the Human Body Model. A proprietary low-dropout transmitter output stage delivers true RS-232 performance from a +3.0V to +5.5V power supply, using an internal dual charge pump. The charge pump requires only four small 0.1μF capacitors for operation from a +3.3V supply. Each device guarantees operation at data rates of 250kbps while maintaining RS-232 output levels. The MAX3237E guarantees operation at 250kbps in the normal operating mode and 1Mbps in the MegaBaud™ operating mode, while maintaining RS-232- compliant output levels. The MAX3222E/MAX3232E have two receivers and two transmitters. The MAX3222E features a 1μA shutdown mode that reduces power consumption in battery-powered portable systems. The MAX3222E receivers remain active in shutdown mode, allowing monitoring of external devices while consuming only 1μA of supply current. The MAX3222E and MAX3232E are pin, package, and functionally compatible with the industry-standard MAX242 and MAX232, respectively. The MAX3241E/MAX3246E are complete serial ports (three drivers/five receivers) designed for notebook and subnotebook computers. The MAX3237E (five drivers/ three receivers) is ideal for peripheral applications that require fast data transfer. These devices feature a shutdown mode in which all receivers remain active, while consuming only 1μA (MAX3241E/MAX3246E) or 10nA (MAX3237E). The MAX3222E, MAX3232E, and MAX3241E are available in space-saving SO, SSOP, TQFN and TSSOP packages. The MAX3237E is offered in an SSOP package. The MAX3246E is offered in the ultra-small 6 x 6 UCSP™ package. Applications Battery-Powered Equipment Printers Cell Phones Smart Phones Cell-Phone Data Cables xDSL Modems Notebook, Subnotebook, and Palmtop Computers Next-Generation Device Features ♦ For Space-Constrained Applications MAX3228E/MAX3229E: ±15kV ESD-Protected, +2.5V to +5.5V, RS-232 Transceivers in UCSP ♦ For Low-Voltage or Data Cable Applications MAX3380E/MAX3381E: +2.35V to +5.5V, 1μA, 2Tx/2Rx, RS-232 Transceivers with ±15kV ESD-Protected I/O and Logic Pins MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ________________________________________________________________ Maxim Integrated Products 1 19-1298; Rev 10; 1/06 _______________Ordering Information Ordering Information continued at end of data sheet. *Dice are tested at TA = +25°C, DC parameters only. **EP = Exposed paddle. Pin Configurations, Selector Guide, and Typical Operating Circuits appear at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PINPACKAGE PKG CODE MAX3222ECTP 0°C to +70°C 20 Thin QFNEP** (5mm x 5mm) T2055-5 MAX3222ECUP 0°C to +70°C 20 TSSOP — MAX3222ECAP 0°C to +70°C 20 SSOP — MAX3222ECWN 0°C to +70°C 18 Wide SO — MAX3222ECPN 0°C to +70°C 18 Plastic DIP — MAX3222EC/D 0°C to +70°C Dice* — MAX3222EETP -40°C to +85°C 20 Thin QFNEP** (5mm x 5mm) T2055-5 MAX3222EEUP -40°C to +85°C 20 TSSOP — MAX3222EEAP -40°C to +85°C 20 SSOP — MAX3222EEWN -40°C to +85°C 18 Wide SO — MAX3222EEPN -40°C to +85°C 18 Plastic DIP — MAX3232ECAE 0°C to +70°C 16 SSOP — MAX3232ECWE 0°C to +70°C 16 Wide SO — MAX3232ECPE 0°C to +70°C 16 Plastic DIP — MegaBaud and UCSP are trademarks of Maxim Integrated Products, Inc. †Covered by U.S. Patent numbers 4,636,930; 4,679,134; 4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and other patents pending. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VCC to GND..............................................................-0.3V to +6V V+ to GND (Note 1) ..................................................-0.3V to +7V V- to GND (Note 1) ...................................................+0.3V to -7V V+ + |V-| (Note 1).................................................................+13V Input Voltages T_IN, EN, SHDN, MBAUD to GND ........................-0.3V to +6V R_IN to GND .....................................................................±25V Output Voltages T_OUT to GND...............................................................±13.2V R_OUT, R_OUTB (MAX3241E)................-0.3V to (VCC + 0.3V) Short-Circuit Duration, T_OUT to GND.......................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin SSOP (derate 7.14mW/°C above +70°C) ..........571mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .......754.7mW 16-Pin TQFN (derate 20.8mW/°C above +70°C) .....1666.7mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW 18-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW 18-Pin PDIP (derate 11.11mW/°C above +70°C)..........889mW 20-Pin TQFN (derate 21.3mW/°C above +70°C) ........1702mW 20-Pin TSSOP (derate 10.9mW/°C above +70°C) ........879mW 20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW 28-Pin Wide SO (derate 12.50mW/°C above +70°C).............1W 28-Pin TSSOP (derate 12.8mW/°C above +70°C) ......1026mW 32-Lead Thin QFN (derate 33.3mW/°C above +70°C)..2666mW 6 x 6 UCSP (derate 12.6mW/°C above +70°C).............1010mW Operating Temperature Ranges MAX32_ _EC_ _ ...................................................0°C to +70°C MAX32_ _EE_ _.................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Bump Reflow Temperature (Note 2) Infrared, 15s..................................................................+200°C Vapor Phase, 20s..........................................................+215°C Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed. PARAMETER CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS (VCC = +3.3V or +5V, TA = +25°C) MAX3222E, MAX3232E, MAX3241E, MAX3246E 0.3 1 Supply Current SHDN = VCC, no load MAX3237E 0.5 2.0 mA SHDN = GND 1 10 μA Shutdown Supply Current SHDN = R_IN = GND, T_IN = GND or VCC (MAX3237E) 10 300 nA LOGIC INPUTS Input Logic Low T_IN, EN, SHDN, MBAUD 0.8 V VCC = +3.3V 2.0 Input Logic High T_IN, EN, SHDN, MBAUD VCC = +5.0V 2.4 V Transmitter Input Hysteresis 0.5 V T_IN, EN, SHDN MAX3222E, MAX3232E, MAX3241E, MAX3246E ±0.01 ±1 Input Leakage Current T_IN, SHDN, MBAUD MAX3237E (Note 5) 9 18 μA RECEIVER OUTPUTS Output Leakage Current R_OUT (MAX3222E/MAX3237E/MAX3241E/ MAX3246E), EN = VCC, receivers disabled ±0.05 ±10 μA Output-Voltage Low IOUT = 1.6mA (MAX3222E/MAX3232E/MAX3241E/ MAX3246E), IOUT = 1.0mA (MAX3237E) 0.4 V MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Output-Voltage High IOUT = -1.0mA VCC - 0.6 VCC - 0.1 V RECEIVER INPUTS Input Voltage Range -25 +25 V VCC = +3.3V 0.6 1.1 Input Threshold Low TA = +25°C VCC = +5.0V 0.8 1.5 V VCC = +3.3V 1.5 2.4 Input Threshold High TA = +25°C VCC = +5.0V 2.0 2.4 V Input Hysteresis 0.5 V Input Resistance TA = +25°C 3 5 7 kΩ TRANSMITTER OUTPUTS Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground (Note 6) ±5 ±5.4 V Output Resistance VCC = 0, transmitter output = ±2V 300 50k Ω Output Short-Circuit Current ±60 mA Output Leakage Current V C C = 0 or + 3.0V to + 5.5V , V OU T = ± 12V , tr ansm i tter s d i sab l ed ( M AX 3222E /M AX 3232E /M AX 3241E /M AX 3246E ) ±25 μA MOUSE DRIVABILITY (MAX3241E) Transmitter Output Voltage T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with 3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA each ±5 V ESD PROTECTION Human Body Model ±15 IEC 1000-4-2 Air-Gap Discharge (except MAX3237E) ±15 IEC 1000-4-2 Contact Discharge (except MAX3237E) ±8 R_IN, T_OUT IEC 1000-4-2 Contact Discharge (MAX3246E only) ±9 kV Human Body Model ±15 IEC1000-4-2 Air-Gap Discharge ±15 T_IN, R_IN, R_OUT, EN, SHDN, MBAUD MAX3237E IEC1000-4-2 Contact Discharge ±8 kV MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 4 _______________________________________________________________________________________ TIMING CHARACTERISTICS—MAX3237E (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) Note 3:MAX3222E/MAX3232E/MAX3241E: C1–C4 = 0.1μF tested at +3.3V ±10%; C1 = 0.047μF, C2, C3, C4 = 0.33μF tested at +5.0V ±10%. MAX3237E: C1–C4 = 0.1μF tested at +3.3V ±5%, C1–C4 = 0.22μF tested at +3.3V ±10%; C1 = 0.047μF, C2, C3, C4 = 0.33μF tested at +5.0V ±10%. MAX3246E; C1-C4 = 0.22μF tested at +3.3V ±10%; C1 = 0.22μF, C2, C3, C4 = 0.54μF tested at 5.0V ±10%. Note 4: MAX3246E devices are production tested at +25°C. All limits are guaranteed by design over the operating temperature range. Note 5: The MAX3237E logic inputs have an active positive feedback resistor. The input current goes to zero when the inputs are at the supply rails. Note 6: MAX3241EEUI is specified at TA = +25°C. Note 7: Transmitter skew is measured at the transmitter zero crosspoints. PARAMETER CONDITIONS MIN TYP MAX UNITS RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = GND 250 VCC = +3.0V to +4.5V, RL = 3kΩ, CL = 250pF, one transmitter switching, MBAUD = VCC Maximum Data Rate 1000 VCC = +4.5V to +5.5V, RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = VCC 1000 kbps tPHL 0.15 Receiver Propagation Delay R_IN to R_OUT, CL = 150pF tPLH 0.15 μs Receiver Output Enable Time Normal operation 2.6 μs Receiver Output Disable Time Normal operation 2.4 μs | tPHL - tPLH |, MBAUD = GND Transmitter Skew (Note 7) | tPHL - tPLH |, MBAUD = VCC 100 ns Receiver Skew | tPHL - tPLH | 50 ns CL = 150pF MBAUD = GND 6 30 to 1000pF MBAUD = VCC 24 150 VCC = +3.3V, RL = 3kΩ to 7kΩ, +3.0V to -3.0V or -3.0V to +3.0V, TA = +25°C CL = 150pF to 2500pF, MBAUD = GND 4 30 Transition-Region Slew Rate V/μs TIMING CHARACTERISTICS—MAX3222E/MAX3232E/MAX3241E/MAX3246E (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TA = TMIN to TMAX (MAX3222E/MAX3232E/ MAX3241E) (Note 6) 250 Maximum Data Rate RL = 3kΩ, CL = 1000pF, one transmitter switching TA = + 25°C ( M AX 3246E ) 250 kbps tPHL 0.15 Receiver Propagation Delay tPLH Receiver input to receiver output, CL = 150pF 0.15 μs Receiver Output Enable Time Normal operation (except MAX3232E) 200 ns Receiver Output Disable Time Normal operation (except MAX3232E) 200 ns Transmitter Skew |tPHL - tPLH| (Note 7) 100 ns Receiver Skew |tPHL - tPLH| 50 ns Transition-Region Slew Rate V C C = + 3.3V , TA = + 25°C , RL = 3kΩ to 7kΩ , m easur ed fr om + 3.0V to - 3.0V or - 3.0V to + 3.0V , one tr ansm i tter sw i tchi ng CL = 150pF to 1000pF 6 30 V/μs MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 5 -6 -4 -2 0 2 4 6 0 MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3237E toc07 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 2500 3000 FOR DATA RATES UP TO 250kbps 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL 5 3 1 -1 -3 -5 VOUT+ VOUT- -6 -2 -4 2 0 4 6 -5 -3 1 -1 3 5 0 500 1000 1500 2000 2500 3000 MAX3246E toc07A LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) VOUTVOUT+ FOR DATA RATES UP TO 250kbps 1 TRANSMITTER 250kbps 4 TRANSMITTERS 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3237E toc08 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD, EACH OUTPUT 2Mbps 1.5Mbps 1Mbps 2Mbps 1Mbps 1.5Mbps __________________________________________Typical Operating Characteristics (VCC = +3.3V, 250kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ and CL, TA = +25°C, unless otherwise noted.) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1000 2000 3000 4000 5000 MAX3241E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3237E to04 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps VOUT+ VOUT- 0 30 20 10 40 50 60 0 1000 2000 3000 4000 5000 MAX3241E OPERATING SUPPLY CURRENT vs. LOAD CAPACITANCE MAX3237E toc06 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 250kbps 120kbps 20kbps 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps 0 4 2 8 6 12 10 14 0 1000 2000 3000 4000 5000 MAX3241E SLEW RATE vs. LOAD CAPACITANCE MAX3237E toc05 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1000 2000 3000 4000 5000 MAX3222E/MAX3232E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3237E toc01 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) T1 TRANSMITTING AT 250kbps T2 TRANSMITTING AT 15.6kbps VOUT+ VOUT- 0 6 2 4 10 8 14 12 16 0 1000 2000 3000 4000 5000 MAX3222E/MAX3232E SLEW RATE vs. LOAD CAPACITANCE MAX3237E toc02 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) +SLEW FOR DATA RATES UP TO 250kbps -SLEW 0 25 20 15 5 10 35 30 40 45 0 1000 2000 3000 4000 5000 MAX3222E/MAX3232E OPERATING SUPPLY CURRENT vs. LOAD CAPACITANCE MAX3237E toc03 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 250kbps 120kbps 20kbps T1 TRANSMITTING AT 250kbps T2 TRANSMITTING AT 15.6kbps MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 6 _______________________________________________________________________________________ Typical Operating Characteristics (continued) (VCC = +3.3V, 250kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ and CL, TA = +25°C, unless otherwise noted.) 0 20 60 40 80 100 0 MAX3237E TRANSMITTER SKEW vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3237E toc12 LOAD CAPACITANCE (pF) 500 1000 1500 2000 TRANSMITTER SKEW (ns) |tPLH - tPHL| 1 TRANSMITTER AT 500kbps 4 TRANSMITTERS AT 1/16 DATA RATE ALL TRANSMITTERS LOADED WITH 3kΩ + CL -6 -2 -4 2 0 4 6 -3 -5 1 -1 3 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 MAX3237E toc13 SUPPLY VOLTAGE (V) TRANSMITTER OUTPUT VOLTAGE (V) VOUTVOUT+ 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ +1000pF MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (MBAUD = GND) 0 10 20 30 40 50 2.0 MAX3237E SUPPLY CURRENT vs. SUPPLY VOLTAGE (MBAUD = GND) MAX3237E toc14 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 2.5 3.0 3.5 4.0 4.5 5.0 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ AND 1000pF MAX3246E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3237E toc15 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 -6 0 5000 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps VOUTVOUT+ 4 6 8 10 12 14 16 0 MAX3246E SLEW RATE vs. LOAD CAPACITANCE MAX3237E toc16 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 SR+ SR- 0 10 20 30 40 50 60 0 MAX3246E OPERATING SUPPLY CURRENT vs. LOAD CAPACITANCE MAX3237E toc17 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps 55 45 35 25 15 5 250kbps 120kbps 20kbps 0 2 4 6 8 10 12 0 MAX3237E SLEW RATE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3237E toc09 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 2500 3000 SR+ SR- 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL 0 10 20 30 50 40 60 70 0 MAX3237E SLEW RATE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3237E toc10 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 -SLEW, 1Mbps +SLEW, 1Mbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD EACH OUTPUT -SLEW, 2Mbps +SLEW, 2Mbps 0 10 20 30 40 50 0 MAX3237E SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA (MBAUD = GND) MAX3237E toc11 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 500 1000 1500 2000 2500 3000 250kbps 120kbps 20kbps 1 TRANSMITTER AT 20kbps, 120kbps, 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 7 *These pins have an active positive feedback resistor internal to the MAX3237E, allowing unused inputs to be left unconnected. Pin Description PIN MAX3222E MAX3232E MAX3241E TQFN SO/ DIP TSSOP/ SSOP TQFN SO/DIP/ SSOP/ 16-PIN TSSOP 20-PIN TSSOP MAX3237E SSOP/ SO QFN MAX3246E NAME FUNCTION 19 1 1 — — — 13* 23 22 B3 EN Receiver Enable. Active low. 1 2 2 16 1 2 28 28 28 F3 C1+ Positive Terminal of Voltage-Doubler Charge- Pump Capacitor 20 3 3 15 2 3 27 27 27 F1 V+ +5.5V Generated by the Charge Pump 2 4 4 1 3 4 25 24 23 F4 C1- Negative Terminal of Voltage-Doubler Charge- Pump Capacitor 3 5 5 2 4 5 1 1 29 E1 C2+ Positive Terminal of Inverting Charge-Pump Capacitor 4 6 6 3 5 6 3 2 30 D1 C2- Negative Terminal of Inverting Charge-Pump Capacitor 5 7 7 4 6 7 4 3 31 C1 V- -5.5V Generated by the Charge Pump 6, 15 8, 15 8, 17 5, 12 7, 14 8, 17 5, 6, 7, 10, 12 9, 10, 11 6, 7, 8 F6, E6, D6 T_OUT RS-232 Transmitter Outputs 7, 14 9, 14 9, 16 6, 11 8, 13 9, 16 8, 9, 11 4–8 1–5 A4, A5, A6, B6, C6 R_IN RS-232 Receiver Inputs 8, 13 10, 13 10, 15 7, 10 9, 12 12, 15 18, 20, 21 15–19 13, 14, 15, 17, 18 C2, B1, A1, A2, A3 R_OUT TTL/CMOS Receiver Outputs 10, 11 11, 12 12, 13 8, 9 10, 11 13, 14 17*, 19*, 22*, 23*, 24* 12, 13, 14 10, 11, 12 E3, E2, D2 T_IN TTL/CMOS Transmitter Inputs MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 8 _______________________________________________________________________________________ Pin Description (continued) PIN MAX3222E MAX3232E MAX3241E TQFN SO/ DIP TSSOP/ SSOP TQFN SO/DIP/ SSOP/ 16-PIN TSSOP 20-PIN TSSOP MAX3237E SSOP/ SO/ TSSOP QFN MAX3246E NAME FUNCTION 16 16 18 13 15 18 2 25 24 F5 GND Ground 17 17 19 14 16 19 26 26 26 F2 VCC +3.0V to +5.5V Supply Voltage 18 18 20 — — — 14* 22 21 B2 SHDN Shutdown Control. Active low. 9, 12 — 11, 14 — — 1, 10, 11, 20 — — 9, 16, 25, 32 C3, D3, B4, C4, D4, E4, B5, C5, D5, E5 N.C. No Connection. For MAX3246E, these locations are not populated with solder bumps. — — — — — — 15* — — — MBAUD MegaBaud Control Input. Connect to GND for normal operation; connect to VCC for 1Mbps transmission rates. — — — — — — 16 20, 21 19, 20 — R_OUTB Noninverting Complementary Receiver Outputs. Always active. EP — — EP — — — — EP — GND Exposed Paddle. Solder the exposed paddle to the ground alone or leave unconnected. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 9 Detailed Description Dual Charge-Pump Voltage Converter The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246Es’ internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump) over the +3.0V to +5.5V VCC range. The charge pump operates in discontinuous mode; if the output voltages are less than 5.5V, the charge pump is enabled, and if the output voltages exceed 5.5V, the charge pump is disabled. Each charge pump requires a flying capacitor (C1, C2) and a reservoir capacitor (C3, C4) to generate the V+ and V- supplies (Figure 1). RS-232 Transmitters The transmitters are inverting level translators that convert TTL/CMOS-logic levels to ±5V EIA/TIA-232-compliant levels. The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E transmitters guarantee a 250kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF, providing compatibility with PC-to-PC communication software (such as LapLink™). Transmitters can be paralleled to drive multiple receivers or mice. The MAX3222E/MAX3237E/MAX3241E/MAX3246E transmitters are disabled and the outputs are forced into a high-impedance state when the device is in shutdown mode (SHDN = GND). The MAX3222E/ MAX3232E/MAX3237E/MAX3241E/MAX3246E permit the outputs to be driven up to ±12V in shutdown. The MAX3222E/MAX3232E/MAX3241E/MAX3246E transmitter inputs do not have pullup resistors. Connect unused inputs to GND or VCC. The MAX3237E’s transmitter inputs have a 400kΩ active positive-feedback resistor, allowing unused inputs to be left unconnected. MAX3237E MegaBaud Operation For higher-speed serial communications, the MAX3237E features MegaBaud operation. In MegaBaud operating mode (MBAUD = VCC), the MAX3237E transmitters guarantee a 1Mbps data rate with worst-case loads of 3kΩ in parallel with 250pF for +3.0V < VCC < +4.5V. For +5V ±10% operation, the MAX3237E transmitters guarantee a 1Mbps data rate into worst-case loads of 3kΩ in parallel with 1000pF. RS-232 Receivers The receivers convert RS-232 signals to CMOS-logic output levels. The MAX3222E/MAX3237E/MAX3241E/ MAX3246E receivers have inverting three-state outputs. Drive EN high to place the receiver(s) into a highimpedance state. Receivers can be either active or inactive in shutdown (Table 1). MAX3222E MAX3232E MAX3237E MAX3241E MAX3246E 5kΩ R_ OUT R_ IN C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC T_ IN T_ OUT GND 7kΩ 150pF MAX3222E MAX3232E MAX3237E MAX3241E MAX3246E 5kΩ R_ OUT R_ IN C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC T_ IN T_ OUT GND 3kΩ 1000pF (2500pF, MAX3237E only) MINIMUM SLEW-RATE TEST CIRCUIT MAXIMUM SLEW-RATE TEST CIRCUIT Figure 1. Slew-Rate Test Circuits LapLink is a trademark of Traveling Software. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 10 ______________________________________________________________________________________ The complementary outputs on the MAX3237E/ MAX3241E (R_OUTB) are always active, regardless of the state of EN or SHDN. This allows the device to be used for ring indicator applications without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC drops to zero in shutdown to accommodate peripherals such as UARTs (Figure 2). MAX3222E/MAX3237E/MAX3241E/ MAX3246E Shutdown Mode Supply current falls to less than 1μA in shutdown mode (SHDN = low). The MAX3237E’s supply current falls to10nA (typ) when all receiver inputs are in the invalid range (-0.3V < R_IN < +0.3). When shut down, the device’s charge pumps are shut off, V+ is pulled down to VCC, V- is pulled to ground, and the transmitter outputs are disabled (high impedance). The time required to recover from shutdown is typically 100μs, as shown in Figure 3. Connect SHDN to VCC if shutdown mode is not used. SHDN has no effect on R_OUT or R_OUTB (MAX3237E/MAX3241E). ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX3222E/MAX3232E/MAX3237E/MAX3241E/MAX3246E have extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, Maxim’s E versions keep working without latchup, whereas competing RS-232 products can latch and must be powered down to remove latchup. Furthermore, the MAX3237E logic I/O pins also have ±15kV ESD protection. Protecting the logic I/O pins to ±15kV makes the MAX3237E ideal for data cable applications. T1OUT R1OUTB Tx 5kΩ UART VCC T1IN LOGIC TRANSITION DETECTOR R1OUT R1IN THREE-STATED EN = VCC SHDN = GND VCC TO μP Rx PREVIOUS RS-232 Tx UART PROTECTION DIODE PROTECTION DIODE SHDN = GND VCC VCC GND Rx 5kΩ a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM A ACTIVE RECEIVER OUTPUT IN SHUTDOWN. b) NEW MAX3237E/MAX3241E: EN SHUTS DOWN RECEIVER OUTPUTS B (EXCEPT FOR B OUTPUTS), SO NO CURRENT FLOWS TO UART IN SHUTDOWN. B B OUTPUTS INDICATE RECEIVER ACTIVITY DURING SHUTDOWN WITH EN HIGH. GND MAX3237E/MAX3241E Figure 2. Detection of RS-232 Activity when the UART and Interface are Shut Down; Comparison of MAX3237E/MAX3241E (b) with Previous Transceivers (a) 40μs/div SHDN T2OUT T1OUT 5V/div 0 2V/div 0 VCC = 3.3V C1–C4 = 0.1μF Figure 3. Transmitter Outputs Recovering from Shutdown or Powering Up MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 11 ESD protection can be tested in various ways; the transmitter outputs and receiver inputs for the MAX3222E/MAX3232E/MAX3241E/MAX3246E are characterized for protection to the following limits: • ±15kV using the Human Body Model • ±8kV using the Contact Discharge method specified in IEC 1000-4-2 • ±9kV (MAX3246E only) using the Contact Discharge method specified in IEC 1000-4-2 • ±15kV using the Air-Gap Discharge method specified in IEC 1000-4-2 CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Cs 100pF RC 1MΩ RD 1500Ω HIGHVOLTAGE DC SOURCE DEVICEUNDERTEST Figure 4a. Human Body ESD Test Model IP 100% 90% 36.8% tRL TIME tDL CURRENT WAVEFORM PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Ir 10% 0 0 AMPERES Figure 4b. Human Body Model Current Waveform CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Cs 150pF RC 50MΩ to 100MΩ RD 330Ω HIGHVOLTAGE DC SOURCE DEVICEUNDERTEST Figure 5a. IEC 1000-4-2 ESD Test Model tr = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% IPEAK I Figure 5b. IEC 1000-4-2 ESD Generator Current Waveform Table 1. MAX3222E/MAX3237E/MAX3241E/ MAX3246E Shutdown and Enable Control Truth Table SHDN EN T_OUT R_OUT R_OUTB (MAX3237E/ MAX3241E) 0 0 High impedance Active Active 0 1 High impedance High impedance Active 1 0 Active Active Active 1 1 Active High impedance Active MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 12 ______________________________________________________________________________________ For the MAX3237E, all logic and RS-232 I/O pins are characterized for protection to ±15kV per the Human Body Model. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 4a shows the Human Body Model, and Figure 4b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. IEC 1000-4-2 The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3222E/ MAX3232E/MAX3237E/MAX3241E/MAX3246E help you design equipment that meets level 4 (the highest level) of IEC 1000-4-2, without the need for additional ESDprotection components. The major difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD withstand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 5a shows the IEC 1000-4-2 model, and Figure 5b shows the current waveform for the ±8kV IEC 1000-4-2 level 4 ESD Contact Discharge test. The Air- Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. All pins require this protection during manufacturing, not just RS-232 inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. Table 2. Required Minimum Capacitor Values -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 MAX3222E-fig06a LOAD CURRENT PER TRANSMITTER (mA) TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ VOUTVOUT+ VCC VOUTVCC = 3.0V Figure 6a. MAX3241E Transmitter Output Voltage vs. Load Table 3. Logic-Family Compatibility with Current Per Transmitter Various Supply Voltages VCC (V) C1 (μF) C2, C3, C4 (μF) MAX3222E/MAX3232E/MAX3241E 3.0 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.1 0.47 MAX3237E/MAX3246E 3.0 to 3.6 0.22 0.22 3.15 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.22 1.0 SYSTEM POWER-SUPPLY VOLTAGE (V) VCC SUPPLY VOLTAGE (V) COMPATIBILITY 3.3 3.3 Compatible with all CMOS families 5 5 Compatible with all TTL and CMOS families 5 3.3 C om p ati b l e w i th AC T and H C T C M OS , and w i th AC , H C , or C D 4000 C M O S MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 13 Applications Information Capacitor Selection The capacitor type used for C1–C4 is not critical for proper operation; polarized or nonpolarized capacitors can be used. The charge pump requires 0.1μF capacitors for 3.3V operation. For other supply voltages, see Table 2 for required capacitor values. Do not use values smaller than those listed in Table 2. Increasing the capacitor values (e.g., by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without changing C1’s value. However, do not increase C1 without also increasing the values of C2, C3, C4, and CBYPASS to maintain the proper ratios (C1 to the other capacitors). When using the minimum required capacitor values, make sure the capacitor value does not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V-. Power-Supply Decoupling In most circumstances, a 0.1μF VCC bypass capacitor is adequate. In applications sensitive to power-supply noise, use a capacitor of the same value as chargepump capacitor C1. Connect bypass capacitors as close to the IC as possible. Operation Down to 2.7V Transmitter outputs meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V. MAX3241E 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 VCC R4IN 7 6 R2IN 5 R1IN 4 SHDN 22 GND 25 12 T3IN 13 T2IN 14 T1IN 2 C2- 1 C2+ 24 C1- 28 C1+ T3OUT 11 +V COMPUTER SERIAL PORT +V -V GND Tx T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 VCC C4 C1 C3 C2 CBYPASS VCC = +3.0V TO +5.5V 26 R3IN MOUSE Figure 6b. Mouse Driver Test Circuit MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 14 ______________________________________________________________________________________ Figure 7. Loopback Test Circuit 2μs/div T1IN T1OUT R1OUT 5V/div 5V/div V 5V/div CC = 3.3V C1–C4 = 0.1μF Figure 8. MAX3241E Loopback Test Result at 120kbps 2μs/div T1IN T1OUT R1OUT 5V/div 5V/div 5V/div VCC = 3.3V, C1–C4 = 0.1μF Figure 9. MAX3241E Loopback Test Result at 250kbps +5V 0 +5V 0 -5V +5V 0 T_IN T_OUT 5kΩ + 250pF R_OUT 400ns/div VCC = 3.3V C1–C4 = 0.1μF Figure 10. MAX3237E Loopback Test Result at 1000kbps (MBAUD = VCC) MAX3222E MAX3232E MAX3237E MAX3241E MAX3246E 5kΩ R_ OUT R_ IN C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC T_ IN T_ OUT GND 1000pF Transmitter Outputs Recovering from Shutdown Figure 3 shows two transmitter outputs recovering from shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels (one transmitter input is high; the other is low). Each transmitter is loaded with 3kΩ in parallel with 2500pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of V- exceeds approximately -3.0V. Mouse Drivability The MAX3241E is designed to power serial mice while operating from low-voltage power supplies. It has been tested with leading mouse brands from manufacturers such as Microsoft and Logitech. The MAX3241E successfully drove all serial mice tested and met their current and voltage requirements. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 15 Figure 6a shows the transmitter output voltages under increasing load current at +3.0V. Figure 6b shows a typical mouse connection using the MAX3241E. High Data Rates The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E maintain the RS-232 ±5V minimum transmitter output voltage even at high data rates. Figure 7 shows a transmitter loopback test circuit. Figure 8 shows a loopback test result at 120kbps, and Figure 9 shows the same test at 250kbps. For Figure 8, all transmitters were driven simultaneously at 120kbps into RS- 232 loads in parallel with 1000pF. For Figure 9, a single transmitter was driven at 250kbps, and all transmitters were loaded with an RS-232 receiver in parallel with 1000pF. The MAX3237E maintains the RS-232 ±5.0V minimum transmitter output voltage at data rates up to 1Mbps. Figure 10 shows a loopback test result at 1Mbps with MBAUD = VCC. For Figure 10, all transmitters were loaded with an RS-232 receiver in parallel with 250pF. Interconnection with 3V and 5V Logic The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E can directly interface with various 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections. UCSP Reliability The UCSP represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as the wafer-fabrication process primarily determines it. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Table 4 shows the testing done to characterize the UCSP reliability performance. In conclusion, the UCSP is capable of performing reliably through environmental stresses as indicated by the results in the table. Additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. Table 4. Reliability Test Data TEST CONDITIONS DURATION FAILURES PER SAMPLE SIZE Temperature Cycle TA = -35°C to +85°C, TA = -40°C to +100°C 150 cycles, 900 cycles 0/10, 0/200 Operating Life TA = +70°C 240 hours 0/10 Moisture Resistance TA = +20°C to +60°C, 90% RH 240 hours 0/10 Low-Temperature Storage TA = -20°C 240 hours 0/10 Low-Temperature Operational TA = -10°C 24 hours 0/10 Solderability 8-hour steam age — 0/15 ESD ±15kV, Human Body Model — 0/5 High-Temperature Operating Life TJ = +150°C 168 hours 0/45 MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 16 ______________________________________________________________________________________ __________________________________________________________Pin Configurations 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2IN T2OUT VC2- C2+ R2IN 9 R2OUT TSSOP/SSOP N.C. N.C. MAX3222E 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 N.C. VCC GND C1- T1OUT V+ C1+ N.C. R1IN R1OUT T2IN R2OUT T2OUT VC2- C2+ R2IN 9 N.C. TSSOP T1IN N.C. MAX3232E 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC GND T1OUT C2+ R1IN C1- V+ C1+ MAX3232E R1OUT T1IN T2IN R2IN R2OUT T2OUT VC2- SO/DIP/SSOP/TSSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC GND C1- EN R5OUT SHDN R1OUTB R2OUTB R1OUT R2OUT R3OUT R4OUT T1IN T2IN T3IN T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN R1IN VC2- C2+ SSOP/SO/TSSOP QFN MAX3241E TOP VIEW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC C1- T1IN T2IN MBAUD T3IN R1OUT R2OUT T4IN R3OUT T5IN R1OUTB SHDN EN T5OUT R3IN T4OUT R2IN R1IN T3OUT T2OUT T1OUT VC2- GND C2+ SSOP MAX3237E 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2OUT T2IN VC2- C2+ R2IN 9 10 R2OUT SO/DIP MAX3222E 32 31 30 29 28 27 26 N.C. VC2- C2+ C1+ V+ VCC 25 N.C. 9 10 11 12 13 14 15 N.C. T3IN T2IN T1IN R5OUT R4OUT R3OUT N.C. 16 17 18 19 20 21 22 23 R2OUT R1OUT R2OUTB R1OUTB SHDN EN C1- 8 7 6 5 4 3 2 T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN MAX3241E R1IN 1 24 GND TOP VIEW MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 17 Pin Configurations (continued) 19 20 18 17 7 6 8 C1- C2- V- 9 C1+ R1IN N.C. T1IN T1OUT 1 2 SHDN 4 5 15 14 12 11 EN V+ EXPOSED PADDLE EXPOSED PADDLE N.C. R2OUT R2IN T2OUT MAX3222E C2+ R1OUT 3 13 VCC GND 16 10 T2IN TQFN TOP VIEW 15 16 14 13 6 5 7 C2+ V- 8 C1- R1IN T1IN T1OUT 1 2 VCC 4 12 11 9 V+ C1+ T2IN R2OUT R2IN T2OUT MAX3232E C2- R1OUT 3 10 GND TQFN TOP VIEW UCSP F2 F3 F4 F5 F6 E3 E6 D6 C6 B3 B6 A2 A3 A4 A5 A6 TOP VIEW (BUMPS ON BOTTOM) T1OUT VCC C1+ C1- GND R3IN R4OUT R5OUT R1IN R2IN R4IN R5IN T3OUT T2OUT B2: SHDN C2: R1OUT D2: T3IN E2: T2IN B3: EN E3: T1IN BUMPS B4, B5, C3, C4, C5, D3, D4, D5, E4, AND E5 NOT POPULATED E2 D2 C2 B2 F1 E1 D1 C1 B1 A1 V+ R3OUT R2OUT VC2- C2+ MAX3246E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 18 ______________________________________________________________________________________ __________________________________________________Typical Operating Circuits 10 R2OUT 1 13 R1OUT R2IN 9 18 GND 16 RS-232 OUTPUTS TTL/CMOS INPUTS 11 T2IN 12 T1IN C2- 6 5 C2+ 4 C1- 2 C1+ R1IN 14 T2OUT 8 T1OUT 15 V- 7 V+ VCC 3 17 C1 0.1μF C2 0.1μF CBYPASS +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS 5kΩ EN 5kΩ SHDN C3* 0.1μF C4 0.1μF NOTE: PIN NUMBERS REFER TO SO/DIP PACKAGES. MAX3222E PINOUT REFERS TO SO/DIP PACKAGES. MAX3232E PINOUT REFERS TO TSSOP/SSOP/SO/DIP/ PACKAGES *C3 CAN BE RETURNED TO EITHER VCC OR GROUND. 9 R2OUT 12 R1OUT R2IN 8 GND 15 RS-232 OUTPUTS TTL/CMOS INPUTS 10 T2IN 11 T1IN C2- 5 4 C2+ 3 C1- 1 C1+ R1IN 13 T2OUT 7 T1OUT 14 V- 6 V+ VCC 2 C4 0.1μF 16 C1 0.1μF C2 0.1μF CBYPASS +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS C3* 0.1μF 5kΩ 5kΩ SEE TABLE 2 FOR CAPACITOR SELECTION. MAX3222E MAX3232E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 19 _____________________________________Typical Operating Circuits (continued) 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 *C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS SHDN 22 GND 25 RS-232 OUTPUTS TTL/CMOS INPUTS 12 T3IN 13 T2IN 14 T1IN C2- 2 1 C2+ 24 C1- 28 C1+ T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 C4 0.1μF C3* 0.1μF C1 0.1μF C2 0.1μF 26 +3.3V CBYPASS MAX3241E 13 EN 18 R3OUT 20 R2OUT 21 R1OUT 16 R1OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ R3IN 11 R2IN 9 R1IN 8 RS-232 INPUTS GND 2 RS-232 OUTPUTS LOGIC INPUTS 22 T3IN 23 T2IN 24 T1IN C2- 3 1 C2+ 25 C1- 28 C1+ T3OUT 7 T2OUT 6 T1OUT 5 T1 T2 T3 R1 R2 R3 V- 4 V+ VCC 27 0.1μF 0.1μF 0.1μF 0.1μF 26 MBAUD 15 17 T5IN 19 T4IN T5OUT 12 T4OUT 10 SHDN 14 T4 T5 C3* CBYPASS +3.3V MAX3237E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 20 ______________________________________________________________________________________ _____________________________________Typical Operating Circuits (continued) B3 EN A3 R5OUT A2 R4OUT A1 R3OUT B1 R2OUT C2 R1OUT TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN C6 *C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN B6 R3IN A6 R2IN A5 R1IN A4 RS-232 INPUTS SHDN B2 GND F5 RS-232 OUTPUTS TTL/CMOS INPUTS D2 T3IN E2 T2IN E3 T1IN C2- D1 E1 C2+ F4 C1- F3 C1+ T3OUT D6 T2OUT E6 T1OUT F6 VC1 V+ VCC F1 C4 0.1μF C3* 0.1μF C1 0.1μF C2 0.1μF F2 +3.3V CBYPASS MAX3246E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 21 Selector Guide PART NO. OF DRIVERS/ RECEIVERS LOW-POWER SHUTDOWN GUARANTEED DATA RATE (bps) MAX3222E 2/2 ✔ 250k MAX3232E 2/2 — 250k MAX3237E (Normal) 5/3 ✔ 250k MAX3237E (MegaBaud) 5/3 ✔ 1M MAX3241E 3/5 ✔ 250k MAX3246E 3/5 ✔ 250k ___________________Chip Information TRANSISTOR COUNT: MAX3222E/MAX3232E: 1129 MAX3237E: 2110 MAX3241E: 1335 MAX3246E: 842 PROCESS: BICMOS Ordering Information (continued) PART TEMP RANGE PINPACKAGE PKG CODE MAX3232ECTE 0°C to +70°C 16 Thin QFNEP** (5mm x 5mm) T1655-2 MAX3232ECUE 0°C to +70°C 16 TSSOP — MAX3232ECUP 0°C to +70°C 20 TSSOP — MAX3232EEAE -40°C to +85°C 16 SSOP — MAX3232EEWE -40°C to +85°C 16 Wide SO — MAX3232EEPE -40°C to +85°C 16 Plastic DIP — MAX3232EETE -40°C to +85°C 16 Thin QFNEP** (5mm x 5mm) T1655-2 MAX3232EEUE -40°C to +85°C 16 TSSOP — MAX3232EEUP -40°C to +85°C 20 TSSOP — MAX3237ECAI 0°C to +70°C 28 SSOP — MAX3237EEAI -40°C to +85°C 28 SSOP — MAX3241ECAI 0°C to +70°C 28 SSOP — MAX3241ECWI 0°C to +70°C 28 Wide SO — MAX3241ECUI 0°C to +70°C 28 TSSOP — MAX3241ECTJ 0°C to +70°C 32 Thin QFN — MAX3241EEAI -40°C to +85°C 28 SSOP — MAX3241EEWI -40°C to +85°C 28 Wide SO — MAX3241EEUI -40°C to +85°C 28 TSSOP — MAX3246ECBX-T 0°C to +70°C 6 x 6 UCSP† — MAX3246EEBX-T -40°C to +85°C 6 x 6 UCSP† — †Requires solder temperature profile described in the Absolute Maximum Ratings section. UCSP Reliability is integrally linked to the user’s assembly methods, circuit board material, and environment. Refer to the UCSP Reliability Notice in the UCSP Reliability section of this datasheet for more information. **EP = Exposed paddle. 24L QFN THIN.EPS PACKAGE OUTLINE, 21-0139 2 1 E 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm PACKAGE OUTLINE, 21-0139 2 2 E 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 22 ______________________________________________________________________________________ MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 23 TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 1 1 I Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 24 ______________________________________________________________________________________ 36L,UCSP.EPS 21-0082 1 1 K PACKAGE OUTLINE, 6x6 UCSP Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 25 SOICW.EPS PACKAGE OUTLINE, .300" SOIC 1 1 21-0042 B APPROVAL DOCUMENT CONTROL NO. REV. PROPRIETARY INFORMATION TITLE: TOP VIEW FRONT VIEW MAX 0.012 0.104 0.019 0.299 0.013 INCHES 0.291 0.009 E C DIM 0.014 0.004 B A1 MIN A 0.093 0.23 7.40 7.60 0.32 MILLIMETERS 0.10 0.35 2.35 MIN 0.49 0.30 MAX 2.65 L 0.016 0.050 0.40 1.27 D 0.496 0.512 D DIM MIN D INCHES MAX 12.60 13.00 MILLIMETERS MIN MAX 20 AC 0.447 0.463 11.35 11.75 18 AB 0.398 0.413 10.10 10.50 16 AA N MS013 SIDE VIEW H 0.394 0.419 10.00 10.65 e 0.050 1.27 D 0.598 0.614 15.20 15.60 24 AD D 0.697 0.713 17.70 18.10 28 AE E H N D e B A1 A 0∞-8∞ C L 1 VARIATIONS: Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SSOP.EPS PACKAGE OUTLINE, SSOP, 5.3 MM 1 1 21-0056 C APPROVAL DOCUMENT CONTROL NO. REV. PROPRIETARY INFORMATION TITLE: NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. H 7.90 L 0∞ 0.301 0.025 8∞ 0.311 0.037 0∞ 7.65 0.63 8∞ 0.95 MAX 5.38 MILLIMETERS B C D E e A1 DIM A SEE VARIATIONS 0.0256 BSC 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 INCHES MIN MAX 0.078 0.65 BSC 0.25 0.09 5.20 0.05 0.38 0.20 0.21 MIN 1.73 1.99 MILLIMETERS 6.07 6.07 10.07 8.07 7.07 INCHES D D D D D 0.239 0.239 0.397 0.317 0.278 MIN 0.249 0.249 0.407 0.328 0.289 MAX MIN 6.33 6.33 10.33 8.33 7.33 14L 16L 28L 24L 20L MAX N A D e A1 L C E H N 2 1 B 0.068 MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PDIPN.EPS Revision History Pages changed at Rev 10: 1–4, 9, 11, 21, 22, 26 PCB Keyswitches 4 - 23 4 RF RF short-travel keyswitches General data RF 15 (15 x 15 mm) and RF 19 (19 x 19 mm) with distinct key click, for use under an overlay or with RK 90 keycaps. Can be fully illuminated. Content RF 15 short-travel keyswitch 4 - 26 RF 15 short-travel keyswitch, non-illuminated 4 - 28 RF 15 short-travel keyswitch, fully illuminated with 2 LEDs 4 - 29 RF 15 short-travel keyswitch, 1 LED spot-illumination 4 - 30 RF 15 N short-travel keyswitch 4 - 32 RF 15 N short-travel keyswitch, non-illuminated 4 - 35 RF 15 R short-travel keyswitch 4 - 36 RF 15 R low short-travel keyswitch, non-illuminated 4 - 39 RF 15 R high short-travel keyswitch, non-illuminated 4 - 39 RF 15 R low short-travel keyswitch, 1 LED spot-illumination 4 - 40 RF 15 R high short-travel keyswitch, 1 LED spot-illumination 4 - 41 RF 15 H short-travel keyswitch 4 - 42 RF 15 H short-travel keyswitch, non-illuminated 4 - 44 RF 15 H short-travel keyswitch, fully illuminated 4 - 45 RF 15 signal indicator 4 - 46 RF 15 signal indicator, fully illuminated, 1 LED 4 - 48 RF 19 short-travel keyswitch 4 - 50 RF 19 short-travel keyswitch, non-illuminated 4 - 53 RF 19 short-travel keyswitch, fully illuminated with 2 LEDs 4 - 54 RF 19 short-travel keyswitch, 1 LED spot-illumination 4 - 55 RF 19 short-travel keyswitch, 1 NC + 1 NO 4 - 56 RF 19 short-travel keyswitch, non-illuminated 4 - 58 RF 19 H short-travel keyswitch 4 - 60 RF 19 H keyswitch, non-illuminated 4 - 62 RF 19 H short-travel keyswitch, fully illuminated 4 - 63 RF 19 signal indicator 4 - 64 RF 19 signal indicator, 1/2 x 1-module 4 - 66 RF 19 signal indicator, 1/2 x 2-module 4 - 66 RF 19 signal indicator, 1 x 1-module 4 - 67 RF 19 signal indicator, 1 x 2-module 4 - 67 4 - 24 PCB Keyswitches 4 RF RF short-travel keyswitches RF special accessories 4 - 68 Extension plunger for RF 15 N, round head 4 - 68 Extension plunger for RF 15 N, round head, with recess for LED 4 - 69 Keycap for RF 15, snap-on, for overall height 12.5 mm 4 - 69 Spacers, round 4 - 70 Spacers, triangular 4 - 71 LED spacer for RF 15 N 4 - 72 PCB Keyswitches 4 - 25 4 RF RF short-travel keyswitches Specifications LED 3 mm LED 2 mm LED Max. forward current lF: Current reduction from: T0 = 50 °C: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: (valid for 25 °C) 30 mA approx 0.5 mA/°C 635 nm 2 V/10 mA 5 V/100 μA min. - 20 °C . . . + 80 °C Red LED 30 mA approx 0.5 mA/°C 565 nm 2 V/10 mA 5 V/100 μA min. - 20 °C . . . + 80 °C Green LED 20 mA approx 0.2 mA/°C 586 nm 2 V/10 mA 5 V/100 μA min. - 20 °C . . . + 80 °C Yellow LED Max. forward current lF: Current reduction from: T0 = 50 °C: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: 20 mA approx 0.6 mA/°C 470 nm 2.7 V/10 mA 5V/100 μA min. - 20 °C . . . + 80 °C Blue LED 25 mA -- 3.6 V/20 mA - - 20 °C . . . + 80 °C White LED 30 mA - 510-545 nm 3.5 V/20 mA - -30 °C . . . + 100 °C Green LED superbright Max. forward current lF: Current reduction from: T0 = 50 °C: Light current fV/lF typ: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: (valid for 25 °C) 30 mA 0.5 mA/°C - 637 nm 1.8 V/20 mA 5 V/100 μA min. - 55 °C . . . + 100 °C Red LED 30 mA 0.5 mA/°C - 569 nm 2.1 V/10 mA 5 V/100 μA min. - 40 °C . . . + 100 °C Green LED 50 mA 0.8 mA/°C 250 mIm/20 mA 590 nm 1.9 V/20 mA 5 V/100 μA min. -40 °C . . . + 100 °C Yellow LED Max. forward current lF: Current reduction from: T0 = 50 °C: Light current fV/lF typ: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: 30 mA - - 464-485 nm 3.6 V/20 mA - 20 °C . . . + 80 °C Blue LED 30 mA approx 0.6 mA/°C - 635/565 nm 2 V/10 mA - - 20 °C . . . + 80 °C Multi-colour LED Rated power of series: PV = IF 2 x RV Calculating the series resistor: RV = Example for 5 Volt: RV = = 150 Ω (= standard value) UB - UF IF 5V - 2.0 V 0.02 A 4 - 26 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch General data Low-profile keyboards with RF 15 components should be designed with a 19.05 mm grid. With this grid, frame webs remain free between the individual keys. The overlay can be glued onto these frame webs; we recommend area embossing over the keys for the overlays. Technical data General information Colour of lens see order block Recommended key grid 19.05 mm Dimensions Length 15 mm Width 15 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot-/fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 27 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 View on component side, all hole diameters 1,1 +/- 0,1 mm Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, fully illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 15 Circuit Diagram – Keyswitch RF 15 Dimensional Drawing RF 15 Hole Pattern RF 15 Hole Pattern – Front Panel Stock items are marked by bold printed order numbers. 4 - 28 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch, non-illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Ag not illuminated transparent 3.14.100.006/0000 Au not illuminated transparent 3.14.100.001/0000 Technical data see page 4 - 26 Accessories: Keycap for RF 15, snap-on, for overall height 12.5 mm: 5.46.654.059/0227 For keycaps, refer to chapter accessories and system RK 90. If exchangeable legends are required, or if an overall height of 12.5 mm is required, a keycap can be mounted on the non-illuminated keys. The keycap legend is visible through a window in the overlay. You can change the legend by replacing the keycap. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 29 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch, fully illuminated with 2 LEDs Illuminated area 10.8 x 10.8 mm Housing Actuator Lens Pict.: red Contact materials Illumination Colour of lens LED colour LED type Order no. Ag fully illuminated 2 LEDs red red 2 mm 3.14.200.021/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.200.022/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.023/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.024/0000 Ag fully illuminated 2 LEDs blue blue 2 mm 3.14.200.025/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.200.012/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.013/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.014/0000 Au fully illuminated 2 LEDs blue blue 2 mm 3.14.200.015/0000 Technical data see page 4 - 26 For keycaps, refer to RK 90 system design. Technical data of LED see seperate page at the beginning of this chapter. Stock items are marked by bold printed order numbers. 4 - 30 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch, 1 LED spot-illumination Pict.: red Contact materials Illumination Colour of lens LED colour LED type Order no. Ag spot illumination 1 LED opaque white blue 3 mm 3.14.100.040/0000 Ag spot illumination 1 LED transparent red 3 mm 3.14.100.041/0000 Ag spot illumination 1 LED transparent green 3 mm 3.14.100.042/0000 Ag spot illumination 1 LED transparent yellow 3 mm 3.14.100.043/0000 Au spot illumination 1 LED opaque white blue 3 mm 3.14.100.030/0000 Au spot illumination 1 LED transparent red 3 mm 3.14.100.031/0000 Au spot illumination 1 LED transparent green 3 mm 3.14.100.032/0000 Au spot illumination 1 LED transparent yellow 3 mm 3.14.100.033/0000 Technical data see page 4 - 26 Double-spot LED illumination available on request Technical data of LED see seperate page at the beginning of this chapter. 4 - 32 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 N short-travel keyswitch General data The RF 15N keyswitch provides a minimum overall height of 6.2 mm. The overall height can be varied by extension plungers which are inserted into the cross-like notches on the actuator tops. LEDs can only be arranged separately next to the keyswitches up to an overall height of 10 mm (i.e. without plunger or with small plunger). Keyswitches with overall heights of 12 mm or more can be provided with a maximum of 2 LEDs which are inserted into the recesses of the keyswitch housing. LEDs of keyswitches with overall heights of 12.5 mm or more should be placed onto LED spacers in order to obtain satisfactory illumination. Technical data General information Colour of lens see order block Recommended key grid 19.05 mm Dimensions Length 15 mm Width 15 mm Overall height 6.2 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination external 3 mm LED possible if height ‹ 12 mm Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 33 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 Operation characteristic limits RF Keyswitch, non illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 15 N Circuit Diagram – Keyswitch RF 15 N Dimensional Drawings RF 15 N 4 - 34 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 N without plunger RF 15 N with plunger ø 10 mm, non-illuminated RF 15 N with plunger ø 10 mm, illuminated RF 15 N with plunger ø 15 mm, illuminated View on component side All hole diameters 1,1 +/- 0,1 mm PCB layout Keyswitch 1/400” grid Hole Pattern RF 15 N Hole Patterns – Front Panel RF 15 N Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 35 4 RF Description Photo Order no. Page Accessories RF 15 N short-travel keyswitch LED yellow, 3mm 1.90.690.103/0000 5 - 20 LED spacer for RF 15 N, Ø 5 mm, spacing length 2.2 mm, light grey, for use with overall height of 12.5 mm 5.30.109.010/0756 Extension plunger for RF 15 N, Ø 10 mm, overall height 22.5 mm 5.46.011.028/0710 Extension plunger for RF 15 N, Ø 15 mm, overall height 22.5 mm 5.46.017.028/0710 RF 15 N short-travel keyswitch, non-illuminated Contact materials Illumination Recommended key grid Overall height Order no. Au external 3 mm LED possible if height < 12 mm 19.05 mm 6.2 mm 3.14.100.601/0000 Ag external 3 mm LED possible if height < 12 mm 19.05 mm 6.2 mm 3.14.100.606/0000 Technical data see page 4 - 32 For keycaps, refer to RK 90 system design. Double-spot LED illumination available on request. 4 - 36 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 R short-travel keyswitch with 3 mm LED, green Pict.: with 2 mm LED, red General data The round actuator of the RF 15 R keyswitch requires round front panel cut-outs. These make it possible to use a narrow keyboard grid of only 15.24 mm with sufficiently large frame webs between the individual keys. We recommend area embossing over the actuators for the overlay. Technical data General information Recommended key grid 15.24 mm Dimensions Length 15 mm Width 15 mm Overall height 9,7/12,5 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot illumination LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 37 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 View on component side All hole diameters 1,1 +/- 0,1 mm PCB layout Keyswitch 1/400” grid Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 15 R Circuit Diagram – Keyswitch RF 15 R Dimensional Drawing RF 15 R Hole Pattern RF 15 R 4 - 38 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 R, non-illuminated RF 15 R, illuminated Hole Pattern – Front Panel RF 15 R Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 39 4 RF RF short-travel keyswitches RF 15 R low short-travel keyswitch, non-illuminated Contact materials Overall height Illumination LED type LED colour Order no. Au 9.7 mm not illuminated 3.14.100.501/0000 Ag 9.7 mm not illuminated 3.14.100.506/0000 Technical data see page 4 - 36 RF 15 R high short-travel keyswitch, non-illuminated Contact materials Overall height Illumination LED type LED colour Order no. Au 12.5 mm not illuminated 3.14.100.801/0000 Ag 12.5 mm not illuminated 3.14.100.806/0000 Technical data see page 4 - 36 Stock items are marked by bold printed order numbers. 4 - 40 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 R low short-travel keyswitch, 1 LED spot-illumination Pict.: with 2 mm LED, red Contact materials Overall height Illumination LED type LED colour Order no. Au 9.7 mm spot illumination 1 LED 2 mm red 3.14.100.531/0000 Au 9.7 mm spot illumination 1 LED 2 mm green 3.14.100.532/0000 Au 9.7 mm spot illumination 1 LED 2 mm yellow 3.14.100.533/0000 Ag 9.7 mm spot illumination 1 LED 2 mm red 3.14.100.541/0000 Ag 9.7 mm spot illumination 1 LED 2 mm green 3.14.100.542/0000 Ag 9.7 mm spot illumination 1 LED 2 mm yellow 3.14.100.543/0000 Technical data see page 4 - 36 Versions with 2 LEDs available on request. Technical data of LED see seperate page at the beginning of this chapter. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 41 4 RF RF short-travel keyswitches RF 15 R high short-travel keyswitch, 1 LED spot-illumination Pict.: with 3 mm LED, green Contact materials Overall height Illumination LED type LED colour Order no. Au 12.5 mm spot illumination 1 LED 3 mm blue 3.14.100.830/0000 Au 12.5 mm spot illumination 1 LED 3 mm red 3.14.100.831/0000 Au 12.5 mm spot illumination 1 LED 3 mm green 3.14.100.832/0000 Au 12.5 mm spot illumination 1 LED 3 mm yellow 3.14.100.833/0000 Ag 12.5 mm spot illumination 1 LED 3 mm blue 3.14.100.840/0000 Ag 12.5 mm spot illumination 1 LED 3 mm red 3.14.100.841/0000 Ag 12.5 mm spot illumination 1 LED 3 mm green 3.14.100.842/0000 Ag 12.5 mm spot illumination 1 LED 3 mm yellow 3.14.100.843/0000 Technical data see page 4 - 36 Versions with 2 LEDs available on request. Technical data of LED see seperate page at the beginning of the chapter. 4 - 42 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 H short-travel keyswitch yellow General data Application notes: The RF 15 H key has an overall height of 12.5 mm and can be fully illuminated. When designing membrane keyboards, we recommend using a key grid of at least 19.05 mm and a 0.13 mm overlay with area embossing over the keys. You can use the O-ring (accessory) to block the key and use it as an indicator field or blank spaceholder. Technical data General information Colour of lens see order block Recommended key grid 20 mm Dimensions Length 15 mm Width 15 mm Overall height 12.5 mm Mechanical design Mounting soldering into PCB Terminals see order block Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination not illuminated / fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 43 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 No metal webs with 15.24 mm. View on component side. All hole diameters 1,1 +/- 0,1 mm. PCB layout Keyswitch 1/400” grid. Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, fully illuminated Force/Travel Diagram – Keyswitch RF 15 H Circuit Diagram – Keyswitch RF 15 H Dimensional Drawing Hole Pattern Hole Pattern – Front Panel Stock items are marked by bold printed order numbers. 4 - 44 PCB Keyswitches 4 RF RF short-travel keyswitches Description Photo Order no. Page Accessories RF 15 H short-travel keyswitch O-ring, black, for blocking the operating stroke 5.30.120.009/0100 5 - 27 RF 15 H short-travel keyswitch, non-illuminated overall height housing actuator lens illuminated area Contact materials Illumination Colour of lens LED colour LED type Order no. Au not illuminated white 3.14.100.702/0000 Ag not illuminated white 3.14.100.707/0000 Technical data see page 4 - 42 Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 45 4 RF RF short-travel keyswitches RF 15 H short-travel keyswitch, fully illuminated overall height housing actuator lens illuminated area Pict.: yellow Contact materials Illumination Colour of lens LED colour LED type Order no. Au fully illuminated 2 LEDs red red 2 mm 3.14.200.731/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.200.732/0000 Au fully illuminated 1 LED green green super bright 3 mm 3.14.200.736/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.733/0000 Au fully illuminated 1 LED white white 3 mm 3.14.200.735/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.738/0000 Au fully illuminated 1 LED blue blue 3 mm 3.14.200.739/0000 Au fully illuminated 2 LEDs white multi colour 3 mm 3.14.100.734/0000 Ag fully illuminated 2 LEDs red red 2 mm 3.14.200.741/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.200.742/0000 Ag fully illuminated 1 LED green green super bright 3 mm 3.14.200.746/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.743/0000 Ag fully illuminated 1 LED white white 3 mm 3.14.200.745/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.748/0000 Ag fully illuminated 1 LED blue blue 3 mm 3.14.200.749/0000 Ag fully illuminated 2 LEDs white multi colour 3 mm 3.14.100.744/0000 Technical data see page 4 - 42 When using the keyswitches with multicolour LEDs the illumination colour can be varied from red to green by change of polarity. Due to the frequency of the polarity-changes the colours red, green, yellow as well as all secondary colours from these are possible. Technical data of LED see seperate page of the beginning of this chapter. 4 - 46 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 signal indicator Pict.: green Technical data General information Colour of lens see order block Recommended key grid 19.05 mm Dimensions Length 15 mm Width 15 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Illumination fully illuminated 1 LED LED colour see order block LED type 2 mm Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 47 4 RF Dimensional Drawing Signal Indicator RF 15 Hole Pattern Hole Pattern – Front Panel No metal webs with 15.24 mm. View on component side. All hole diameters 1,1 +/- 0,1 mm. RF short-travel keyswitches Stock items are marked by bold printed order numbers. 4 - 48 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 signal indicator, fully illuminated, 1 LED Pict.: green Overall height Illumination Colour of lens LED colour LED type Order no. 9.7 mm fully illuminated 1 LED red red 2 mm 3.14.200.051/0000 9.7 mm fully illuminated 1 LED green green 2 mm 3.14.200.052/0000 9.7 mm fully illuminated 1 LED yellow yellow 2 mm 3.14.200.053/0000 9.7 mm fully illuminated 1 LED orange yellow 2 mm 3.14.200.054/0000 9.7 mm fully illuminated 1 LED blue blue 2 mm 3.14.200.055/0000 Technical data see page 4 - 46 For more information, see LEDs. Technical data of LED see seperate page of the beginning of this chapter. 4 - 50 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch General data Application notes: RF 19 keys offer a large actuation area. When designing low-profile keyboards with a grid of >= 23 mm, frame webs remain free between the individual keys. The overlay can be glued onto these frame webs; we recommend area embossing over the keys for the overlay. Technical data General information Colour of lens see order block Recommended key grid 23 mm Dimensions Length 19.05 mm Width 19.05 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot-/fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 51 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, fully illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 19 Circuit Diagram – Keyswitch RF 19 Dimensional Drawing 4 - 52 PCB Keyswitches 4 RF RF short-travel keyswitches * The LED may be positioned either on the left-hand or right-hand side. Standard version: LED on left-hand side View on component side, all hole diameters 1,1 +/- 0,1 mm Hole Patterns RF 19 Hole Patterns – Front Panel RF 19 Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 53 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, non-illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Au not illuminated transparent 3.14.001.001/0000 Ag not illuminated transparent 3.14.001.006/0000 Technical data see page 4 - 50 Stock items are marked by bold printed order numbers. 4 - 54 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, fully illuminated with 2 LEDs Contact materials Illumination Colour of lens LED colour LED type Order no. Au fully illuminated 2 LEDs red red 2 mm 3.14.002.011/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.002.012/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.013/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.014/0000 Au fully illuminated 2 LEDs blue blue 2 mm 3.14.002.015/0000 Ag fully illuminated 2 LEDs red red 2 mm 3.14.002.021/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.002.022/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.023/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.024/0000 Ag fully illuminated 2 LEDs blue blue 2 mm 3.14.002.025/0000 Technical data see page 4 - 50 Technical data of LED see seperate page of the beginning of this chapter. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 55 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, 1 LED spot-illumination Pict.: red Contact materials Illumination Colour of lens LED colour LED type Order no. Au spot illumination 1 LED opaque white blue 3 mm 3.14.001.030/0000 Au spot illumination 1 LED transparent red 3 mm 3.14.001.031/0000 Au spot illumination 1 LED transparent green 3 mm 3.14.001.032/0000 Au spot illumination 1 LED transparent yellow 3 mm 3.14.001.033/0000 Ag spot illumination 1 LED opaque white blue 3 mm 3.14.001.040/0000 Ag spot illumination 1 LED transparent red 3 mm 3.14.001.041/0000 Ag spot illumination 1 LED transparent green 3 mm 3.14.001.042/0000 Ag spot illumination 1 LED transparent yellow 3 mm 3.14.001.043/0000 Technical data see page 4 - 50 Versions with 2 LEDs available on request. Technical data of LED see seperate page of the beginning of this chapter. 4 - 56 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, 1 NC + 1 NO Technical data General information Recommended key grid 23 mm Dimensions Length 19.05 mm Width 19.05 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system bridge contact Contact arrangement 1 NC + 1 NO Contact materials Au/Ag Illumination none Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0,02 V, Ag: 3 V V Rated voltage max. Au: 42 V, Ag: 50 V V Rated current min. Au: 0,01 mA, Ag: 0,1 mA mA Rated current max. Au: 100 mA, Ag: 250 mA mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 2 x 106 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 100000 Soldering time max. 5 sec. Soldering temperature max. 265 °C Flammability of materials UL 94 HB For keycaps, refer to RK 90. PCB Keyswitches 4 - 57 4 RF RF short-travel keyswitches Dimensional Drawing Hole Pattern Hole Pattern – Front Panel Circuit Diagram view on component side Stock items are marked by bold printed order numbers. 4 - 58 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, non-illuminated Contact materials Contact arrangement Illumination Colour of lens Order no. Au 1 NC + 1 NO not illuminated opaque white 1.16.000.991/0000 Ag 1 NC + 1 NO not illuminated opaque white 1.16.000.990/0000 Technical data see page 4 - 56 4 - 60 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 H short-travel keyswitch General data Application notes: The RF 19H key has an overall height of 12.5 mm and can be fully illuminated. When designing membrane keyboards, we recommend using a key grid of at least 23 mm and a 0.13 mm overlay with area embossing over the keys. You can use the O-ring (accessory) to block the key and use it as an indicator field or blank spaceholder. Technical data General information Colour of lens see order block Recommended key grid 24 mm Dimensions Length 19.05 mm Width 19.05 mm Overall height 12.5 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot-/fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 61 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 Operation characteristic limits RF Keyswitch, non illuminated Keyswitch, fully illuminated Force/Travel Diagram – Keyswitch RF 19 H Circuit Diagram – Keyswitch RF 19 H Dimensional Drawing 4 - 62 PCB Keyswitches 4 RF Stock items are marked by bold printed order numbers. RF short-travel keyswitches Description Photo Order no. Page Accessories RF 19 H short-travel keyswitch O-ring, black, 17.0 x 1.5, for blocking RF 19H keys 5.30.125.003/0100 5 - 27 RF 19 H keyswitch, non-illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Au not illuminated white 3.14.001.501/0000 Ag not illuminated white 3.14.001.506/0000 Technical data see page 4 - 60 * The LED may be positioned either on the left-hand or right-hand side. Standard version: LED on left-hand side View on component side, all hole diameters 1,1 +/- 0,1 mm Hole Pattern RF 19 H Hole Pattern – Front Panel RF 19 H LED Keyswitch not illuminated Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 63 4 RF RF short-travel keyswitches RF 19 H short-travel keyswitch, fully illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Au fully illuminated 2 LEDs red red 2 mm 3.14.002.613/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.002.632/0000 Au fully illuminated 1 LED green green super bright 3 mm 3.14.002.633/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.653/0000 Au fully illuminated 1 LED white white 3 mm 3.14.002.684/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.673/0000 Au fully illuminated 2 LEDs white multi colour 3 mm 3.14.001.672/0000 Au fully illuminated 1 LED blue blue 3 mm 3.14.002.683/0000 Ag fully illuminated 2 LEDs red red 2 mm 3.14.002.623/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.002.642/0000 Ag fully illuminated 1 LED green green super bright 3 mm 3.14.002.643/0000 Ag fully illuminated 1 LED blue blue super bright 3 mm 3.14.002.688/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.663/0000 Ag fully illuminated 1 LED white white 3 mm 3.14.002.689/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.678/0000 Ag fully illuminated 2 LEDs white multi colour 3 mm 3.14.001.682/0000 Technical data see page 4 - 60 When using the keyswitches with multicolour LEDs the illumination colour can be varied from red to green by change of polarity. Due to the frequency of the polarity-changes the colours red, green, yellow as well as all secondary colours from these are possible. Technical data of LED see seperate page of the beginning of this chapter. 4 - 64 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 signal indicator 1 x 2-module 0.5 x 2-module 1 x 1-module Pict.: 0.5 x 1-module Technical data General information Colour of lens see order block Recommended key grid 23/x mm Dimensions Length see order block Width see order block Overall height 9.15 mm Mechanical design Mounting soldering into PCB Illumination see order block LED colour see order block LED type see order block Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 65 4 RF RF short-travel keyswitches * The LED may be positioned either on the left-hand or right-hand side. Standard verstion: LED on left-hand side View on component side, all hole diameters 1,1 +/- 0,1 mm Front panel cut-out = outer keyswitch size + 1 mm Dimensional Drawing Signal Indicator RF 19 Hole Patterns RF 19 Stock items are marked by bold printed order numbers. 4 - 66 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 signal indicator, 1/2 x 1-module Housing Lens Illuminated area 16.4 x 7.8 mm Pict.: 0,5 x 1-module, yellow Illumination Colour of lens LED colour LED type Order no. fully illuminated 1 LED red red 2 mm 3.14.002.061/0000 fully illuminated 1 LED green green 2 mm 3.14.002.062/0000 fully illuminated 1 LED yellow yellow 2 mm 3.14.002.063/0000 fully illuminated 1 LED orange yellow 2 mm 3.14.002.064/0000 Technical data see page 4 - 64 For more information, see LEDs. RF 19 signal indicator, 1/2 x 2-module Pict.: 0,5 x 2-module, yellow Illumination Colour of lens LED colour LED type Order no. fully illuminated 3 LEDs red red 2 mm 3.14.002.908/0000 fully illuminated 3 LEDs green green 2 mm 3.14.002.909/0000 fully illuminated 3 LEDs yellow yellow 2 mm 3.14.002.910/0000 fully illuminated 3 LEDs orange yellow 2 mm 3.14.002.911/0000 Technical data see page 4 - 64 For more information, see LEDs. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 67 4 RF RF short-travel keyswitches RF 19 signal indicator, 1 x 1-module Pict.: 1 x 1-module, green Illumination Colour of lens LED colour LED type Order no. fully illuminated 2 LEDs red red 2 mm 3.14.002.051/0000 fully illuminated 2 LEDs green green 2 mm 3.14.002.052/0000 fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.053/0000 fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.054/0000 fully illuminated 2 LEDs blue blue 2 mm 3.14.001.659/0000 Technical data see page 4 - 64 For more information, see LEDs. Suitable for RK 90 system design, illuminated for 2-module keycap. RF 19 signal indicator, 1 x 2-module Pict.: 1 x 2-module, red Illumination Colour of lens LED colour LED type Order no. fully illuminated 5 LEDs red red 2 mm 3.14.002.071/0000 fully illuminated 5 LEDs green green 2 mm 3.14.002.072/0000 fully illuminated 5 LEDs yellow yellow 2 mm 3.14.002.073/0000 fully illuminated 5 LEDs orange yellow 2 mm 3.14.002.074/0000 Technical data see page 4 - 64 For more information, see LEDs. Stock items are marked by bold printed order numbers. 4 - 68 PCB Keyswitches 4 RF RF short-travel keyswitches RF special accessories Pict.: light grey round and triangular versions Extension plunger for RF 15 N, round head Pict.: light grey Length Width Overall height Diameter Colour Order no. 9 mm 10 mm 5.46.011.036/0710 9.7 mm 10 mm 5.46.011.030/0710 12.5 mm 10 mm 5.46.011.037/0710 13 mm 10 mm 5.46.011.038/0710 22.5 mm 10 mm 5.46.011.028/0710 Length of plunger = Overall height - 4.25 mm. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 69 4 RF RF short-travel keyswitches Extension plunger for RF 15 N, round head, with recess for LED Length Width Overall height Diameter Colour Order no. 9 mm 15 mm 5.46.017.036/0710 9.7 mm 15 mm 5.46.017.030/0710 12.5 mm 15 mm 5.46.017.037/0710 13 mm 15 mm 5.46.017.038/0710 22.5 mm 15 mm 5.46.017.028/0710 Keycap for RF 15, snap-on, for overall height 12.5 mm Length Width Overall height Diameter Colour Order no. 14.2 mm 14.2 mm 12.5 mm beige 5.46.654.059/0227 Stock items are marked by bold printed order numbers. 4 - 70 PCB Keyswitches 4 RF RF short-travel keyswitches Spacers, round Overlay Front panel Spacer PCB Length Width Overall height Diameter Colour Order no. 6.2 mm blue 5.30.759.251/0000 9.00 mm green 5.30.759.046/0000 3.50 mm blue transparent 5.30.759.023/0000 4 mm green 5.30.759.025/0000 4.25 mm blue 5.30.759.026/0000 4.50 mm red 5.30.759.027/0000 4.75 mm blue transparent 5.30.759.028/0000 5 mm black 5.30.759.029/0000 5.25 mm yellow orange transparent 5.30.759.030/0000 5.50 mm yellow 5.30.759.031/0000 5.75 mm green 5.30.759.032/0000 6 mm blue 5.30.759.033/0000 6.25 mm red 5.30.759.034/0000 6.50 mm blue transparent 5.30.759.035/0000 6.75 mm black 5.30.759.036/0000 7 mm yellow orange transparent 5.30.759.037/0000 7.25 mm yellow 5.30.759.038/0000 7.50 mm green 5.30.759.039/0000 7.75 mm blue 5.30.759.040/0000 8 mm red 5.30.759.041/0000 8.25 mm blue transparent 5.30.759.042/0000 10.00 mm black 5.30.759.043/0104 Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 71 4 RF RF short-travel keyswitches Spacers, triangular Countersink from height > 4 mm Overlay Front panel Spacer PCB Length Width Overall height Diameter Colour Order no. 6.2 mm blue 5.30.759.253/0000 2.50 mm blue 5.30.759.094/0000 2.75 mm red 5.30.759.095/0000 3 mm blue transparent 5.30.759.096/0000 3.25 mm black 5.30.759.097/0000 3.50 mm yellow orange transparent 5.30.759.098/0000 3.75 mm yellow 5.30.759.099/0000 4 mm green 5.30.759.100/0000 4.25 mm blue 5.30.759.101/0000 4.50 mm red 5.30.759.102/0000 4.75 mm blue transparent 5.30.759.103/0000 5 mm black 5.30.759.104/0000 5.25 mm yellow orange transparent 5.30.759.105/0000 5.50 mm yellow 5.30.759.106/0000 5.75 mm green 5.30.759.107/0000 6 mm blue 5.30.759.108/0000 6.25 mm red 5.30.759.109/0000 6.50 mm blue transparent 5.30.759.110/0000 6.75 mm black 5.30.759.111/0000 7 mm yellow orange transparent 5.30.759.112/0000 7.25 mm yellow 5.30.759.113/0000 7.50 mm green 5.30.759.114/0000 7.75 mm blue 5.30.759.115/0000 Stock items are marked by bold printed order numbers. 4 - 72 PCB Keyswitches 4 RF RF short-travel keyswitches Length Width Overall height Diameter Colour Order no. 8 mm red 5.30.759.116/0000 8.25 mm blue transparent 5.30.759.117/0000 10.00 mm black 5.30.759.124/0000 10.25 mm yellow orange transparent 5.30.759.125/0000 LED spacer for RF 15 N Pict.: light grey Length Characteristic 1 Width Overall height Order no. Characteristic 2 Diameter Colour 2.2 mm 12.5 mm 5 mm light grey 5.30.109.010/0756 12 mm 22.5 mm 5 mm black 5.30.109.019/0105 9 mm blue 5.30.759.254/0000 TL082 Wide Bandwidth Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage (BI-FET II™ technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The TL082 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and most LM358 designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Features n Internally trimmed offset voltage: 15 mV n Low input bias current: 50 pA n Low input noise voltage: 16nV/√Hz n Low input noise current: 0.01 pA/√Hz n Wide gain bandwidth: 4 MHz n High slew rate: 13 V/μs n Low supply current: 3.6 mA n High input impedance: 1012Ω n Low total harmonic distortion: ≤0.02% n Low 1/f noise corner: 50 Hz n Fast settling time to 0.01%: 2 μs Typical Connection 00835701 Connection Diagram DIP/SO Package (Top View) 00835703 Order Number TL082CM or TL082CP See NS Package Number M08A or N08E Simplified Schematic 00835702 BI-FET II™ is a trademark of National Semiconductor Corp. August 2000 TL082 Wide Bandwidth Dual JFET Input Operational Amplifier © 2004 National Semiconductor Corporation DS008357 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ±18V Power Dissipation (Note 2) Operating Temperature Range 0°C to +70°C Tj(MAX) 150°C Differential Input Voltage ±30V Input Voltage Range (Note 3) ±15V Output Short Circuit Duration Continuous Storage Temperature Range −65°C to +150°C Lead Temp. (Soldering, 10 seconds) 260°C ESD rating to be determined. Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. DC Electrical Characteristics (Note 5) Symbol Parameter Conditions TL082C Units Min Typ Max VOS Input Offset Voltage RS = 10 kΩ, TA = 25°C 5 15 mV Over Temperature 20 mV ΔVOS/ΔT Average TC of Input Offset RS = 10 kΩ 10 μV/°C Voltage IOS Input Offset Current Tj = 25°C, (Notes 5, 6) 25 200 pA Tj ≤ 70°C 4 nA IB Input Bias Current Tj = 25°C, (Notes 5, 6) 50 400 pA Tj ≤ 70°C 8 nA RIN Input Resistance Tj = 25°C 1012 Ω AVOL Large Signal Voltage Gain VS = ±15V, TA = 25°C 25 100 V/mV VO = ±10V, RL = 2 kΩ Over Temperature 15 V/mV VO Output Voltage Swing VS = ±15V, RL = 10 kΩ ±12 ±13.5 V VCM Input Common-Mode Voltage VS = ±15V ±11 +15 V Range −12 V CMRR Common-Mode Rejection Ratio RS ≤ 10 kΩ 70 100 dB PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB IS Supply Current 3.6 5.6 mA TL082 www.national.com 2 AC Electrical Characteristics (Note 5) Symbol Parameter Conditions TL082C Units Min Typ Max Amplifier to Amplifier Coupling TA = 25°C, f = 1Hz- −120 dB 20 kHz (Input Referred) SR Slew Rate VS = ±15V, TA = 25°C 8 13 V/μs GBW Gain Bandwidth Product VS = ±15V, TA = 25°C 4 MHz en Equivalent Input Noise Voltage TA = 25°C, RS = 100Ω, 25 nV/√Hz f = 1000 Hz in Equivalent Input Noise Current Tj = 25°C, f = 1000 Hz 0.01 pA/√Hz THD Total Harmonic Distortion AV = +10, RL = 10k, VO = 20 Vp − p, BW = 20 Hz−20 kHz <0.02 % Note 2: For operating at elevated temperature, the device must be derated based on a thermal resistance of 115°C/W junction to ambient for the N package. Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: The power dissipation limit, however, cannot be exceeded. Note 5: These specifications apply for VS = ±15V and 0°C ≤TA ≤ +70°C. VOS, IB and IOS are measured at VCM = 0. Note 6: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj = TA + θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V. Typical Performance Characteristics Input Bias Current Input Bias Current 00835718 00835719 TL082 3 www.national.com Typical Performance Characteristics (Continued) Supply Current Positive Common-Mode Input Voltage Limit 00835720 00835721 Negative Common-Mode Input Voltage Limit Positive Current Limit 00835722 00835723 Negative Current Limit Voltage Swing 00835724 00835725 TL082 www.national.com 4 Typical Performance Characteristics (Continued) Output Voltage Swing Gain Bandwidth 00835726 00835727 Bode Plot Slew Rate 00835728 00835729 Distortion vs Frequency Undistorted Output Voltage Swing 00835730 00835731 TL082 5 www.national.com Typical Performance Characteristics (Continued) Open Loop Frequency Response Common-Mode Rejection Ratio 00835732 00835733 Power Supply Rejection Ratio Equivalent Input Noise Voltage 00835734 00835735 Open Loop Voltage Gain (V/V) Output Impedance 00835736 00835737 TL082 www.national.com 6 Typical Performance Characteristics (Continued) Inverter Setting Time 00835738 Pulse Response Small Signal Inverting 00835706 Small Signal Non-Inverting 00835707 Large Signal Inverting 00835708 Large Signal Non-Inverting 00835709 TL082 7 www.national.com Pulse Response (Continued) Current Limit (RL = 100Ω) 00835710 Application Hints These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kΩ load resistance to ±10V over the full temperature range of 0°C to +70°C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. Because these amplifiers are JFET rather than MOSFET input op amps they do not require special handling. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. TL082 www.national.com 8 Detailed Schematic 00835711 Typical Applications Three-Band Active Tone Control 00835712 TL082 9 www.national.com Typical Applications (Continued) 00835713 • All potentiometers are linear taper • Use the LF347 Quad for stereo applications Note 8: All controls flat. Note 9: Bass and treble boost, mid flat. Note 10: Bass and treble cut, mid flat. Note 11: Mid boost, bass and treble flat. Note 12: Mid cut, bass and treble flat. Improved CMRR Instrumentation Amplifier 00835714 C and are separate isolated grounds Matching of R2’s, R4’s and R5’s control CMRR With AVT = 1400, resistor matching = 0.01%: CMRR = 136 dB • Very high input impedance • Super high CMRR TL082 www.national.com 10 Typical Applications (Continued) Fourth Order Low Pass Butterworth Filter 00835715 Fourth Order High Pass Butterworth Filter 00835716 TL082 11 www.national.com Typical Applications (Continued) Ohms to Volts Converter 00835717 TL082 www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted Order Number TL082CM NS Package M08A Order Number TL082CP NS Package N08E TL082 13 www.national.com Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com TL082 Wide Bandwidth Dual JFET Input Operational Amplifier UDG-02157 VIN VOUT 5 13 12 16 15 1 2 3 4 6 11 7 8 14 10 9 + - KFF RT BP5 SGND VIN BPN10 SW BP10 SYNC ILIM TPS40060PWP SS/SD VFB COMP HDRV LDRV PGND 8 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS40060, TPS40061 1FEATURES APPLICATIONS 2• Operating Input Voltage 10 V to 55 V • Networking Equipment • Input Voltage Feed-Forward Compensation • Telecom Equipment • < 1% Internal 0.7-V Reference • Base Stations • Programmable Fixed-Frequency, Up to 1-MHz • Servers Voltage Mode Controller • Internal Gate Drive Outputs for High-Side P- DESCRIPTION Channel and Synchronous N-Channel The TPS40060 and TPS40061 are high-voltage, wide MOSFETs input (10 V to 55 V) synchronous, step-down • 16-Pin PowerPAD™ Package (θ converters. JC = 2°C/W) • Thermal Shutdown This family of devices offers design flexibility with a variety of user programmable functions, including; • Externally Synchronizable soft-start, UVLO, operating frequency, voltage feed- • Programmable High-Side Sense Short Circuit forward, high-side current limit, and loop Protection compensation. These devices are also • Programmable Closed-Loop Soft-Start synchronizable to an external supply. • TPS40060 Source Only/TPS40061 Source/Sink The TPS40060 and TPS40061 incorporate MOSFET gate drivers for external P-channel high-side and Nchannel synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. SIMPLIFIED APPLICATION DIAGRAM 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. THERMAL PAD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 KFF RT BP5 SYNC SGND SS/SD VFB COMP ILIM VIN HDRV BPN10 SW BP10 LDRV PGND PWP PACKAGE (1)(2) (TOP VIEW) TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA LOAD CURRENT PACKAGE(1) PART NUMBER SOURCE(2) Plastic HTSSOP (PWP) TPS40060PWP –40°C to 85°C SOURCE/SIN(2) Plastic HTSSOP (PWP) TPS40061PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40060PWPR). See the Application Information of the data sheet for PowerPAD drawing and layout information. (2) See Application Information section. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS40060 TPS40061 VIN 60 V VFB, SS/SD, SYNC –0.3 V to 6 V VIN Input voltage range SW –0.3 V to 60 V or VIN+5 V (whichever is less) SW. transient < 50 ns –2.5 V VOUT Output voltage range COMP, RT, KFF, SS –0.3 V to 6 V IIN Input current KFF 5 mA IOUT Output current RT 200 μA TJ Operating junction temperature range –40°C to 125°C Tstg Storage temperature –55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VIN Input voltage 10 55 V TA Operating free-air temperature –40 85 °C (1) For more information on the PWP package, refer to TI Technical Brief (SLMA002). (2) PowerPAD™ heat slug must be connected to SGND (Pin 5), or electrically isolated from all other pins. 2 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 μA, fSW = 300 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN 10 55 V OPERATING CURRENT IDD Quiescent current Output drivers not switching 1.5 2.5 mA 5-V REFERENCE VBP5 Input voltage 4.5 5.0 5.5 V OSCILLATOR/RAMP GENERATOR(1) fOSC Frequency 270 300 330 kHz VRAMP PWM ramp voltage(2) 2 VIH High-level input voltage, SYNC 2 V VIL Low-level input voltage, SYNC 0.8 ISYNC Input current, SYNC 5 10 μA Pulse width, SYNC Pulse amplitude = 5 V 50 ns VRT RT voltage 2.32 2.50 2.68 V Maximum duty cycle VFB = 0 V, 100 kHz ≤ fSW≤ 1 MHz 85% 98% Minimum duty cycle VFB ≥ 0.75 V 0% VKFF Feed-forward voltage 3.35 3.50 3.65 V IKFF Feed-forward current operating range(2) 20 1100 μA SS/SD (SOFT START) ISS Soft-start source current 1.5 2.3 2.9 μA VSS Soft-start clamp voltage 3.1 3.7 4.0 V tDSCH Discharge time CSS = 220 pF 1.6 2.2 2.9 μs tSS Soft-start time CSS = 220 pF, 0 V ≤ VSS ≤ 1.6 V 120 155 235 SS/SD (SHUTDOWN) VSD Shutdown threshold voltage 90 130 160 VEN Device action threshold voltage 170 210 260 mV Hysteresis 80 10-V REFERENCE VBP10 Input voltage 9.0 9.7 10.7 V ERROR AMPLIFIER TA = 25°C 0.698 0.700 0.704 VFB Feedback regulation voltage 0°C ≤ TA ≤ 85°C 0.690 0.700 0.707 V 0.690 0.700 0.715 GBW Gain bandwidth 3 5 MHz AVOL Open loop gain 60 80 dB IOH High-level output source current VCOMP = 2.0 V, VFB = 0 V 1.5 4.0 mA IOL Low-level output sink current VCOMP = 2.0 V, VFB = 1 V 2.5 4.0 IBIAS Input bias current VFB = 0.7 V 100 300 nA VOH High-level output voltage IOH = 0.5 mA, VFB = 0 V 3.25 3.45 3.60 V VOL Low-level output voltage IOL = 0.5 mA, VFB = 1 V 0.050 0.215 0.350 (1) KFF current (IKFF) increases with SYNC frequency (fSYNC) and decreases with maximum duty cycle (DMAX). (2) Ensured by design. Not production tested. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 μA, fSW = 300 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT TA = 25°C 8.8 10.0 11.4 ISINK Current limit sink current 0°C ≤ TA ≤ 85°C 8.3 11.9 μA -40°C ≤ TA ≤ 0°C 7.5 11.5 VILIM = 23.7 V, VSW = (VILIM – 0.5 V) 330 500 tDELAY Propagation delay to output VILIM = 23.7 V, VSW = (VILIM – 2 V) 275 375 ns tON Switch leading-edge blanking pulse time(3) 100 tOFF Off time during a fault 7 cycles VOS Overcurrent comparator offset voltage -200 -60 50 mV OUTPUT DRIVER tHFALL High-side driver fall time(3) CHDRV = 2200 pF, (VIN – VBPN10) 48 96 tHRISE High-side driver rise time(3) CHDRV = 2200 pF, (VIN – VBPN10) 36 72 ns tLFALL Low-side driver fall time(3) CLDRV = 2200 pF, BP10 24 48 tLRISE Low-side driver rise time(3) CLDRV = 2200 pF, BP10 48 96 VOH High-level ouput voltage, HDRV IHDRV = 0.1 A , (VIN – VHDRV) 1.0 1.4 VOL Low-level ouput voltage, HDRV IHDRV = 0.1 A , (VHDRV – VBPN10) 0.75 V VOH High-level ouput voltage, LDRV ILDRV = 0.1 A, (VBP10 – VLDRV) 1.0 1.5 VOL Low-level ouput voltage, LDRV ILDRV = 0.1 A 0.5 Minimum controllable pulse width 100 150 ns BPN10 REGULATOR VBPN1 Output voltage Outputs off –7.5 –8.5 –9.5 V 0 RECTIFIER ZERO CURRENT COMPARATOR (TPS40060 ONLY) VSW Switch voltage LDRV output OFF –6 0 6 mV SW NODE ILEAK Leakage current(3) 1 μA THERMAL SHUTDOWN Shutdown temperature(3) 165 TSD °C Hysteresis(3) 25 UNDERVOLTAGE LOCKOUT VUVLO Undervoltage lockout threshold voltage, BP10 RKFF = 10 kΩ 6.25 6.5 7.5 Undervoltage lockout hysteresis 0.4 V VKFF KFF programmable threshold voltage RKFF = 82.5 kΩ 9 10 11 (3) Ensured by design. Not production tested. 4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. 5-V reference. BP5 3 O This pin should be bypassed to ground with a 0.1-μF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. BP10 11 O 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-μF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. BPN10 13 O Negative 8-V reference with respect to VIN. This voltage is used to provide gate drive for the high side P-channel MOSFET. This pin should be bypassed to VIN with a 0.1-μF capacitor Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the COMP 8 I VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large signal transient response. HDRV 14 O Floating gate drive for the high-side P-channel MOSFET. This pin switches from VIN (MOSFET off) to BPN10 (MOSFET on). Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a ILIM 16 I voltage drop across an external resistor connected from this pin to VIN. The voltage on this pin is compared to the voltage drop (VIN -SW) across the high side MOSFET during conduction. KFF 1 I A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into this pin is internally divided and used to control the slope of the PWM ramp. LDRV 10 I Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off). PGND 9 Power ground reference for the device. There should be a low-impedance connection from this point to the source of the power MOSFET. RT 2 I A resistor is connected from this pin to ground to set the internal oscillator ramp charging current and switching frequency. SGND 5 Signal ground reference for the device. Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 μA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is approximately SS/SD 6 I 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains active. SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing. This pin is used for zero current sensing in the TPS40060. SYNC 4 I Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. VFB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. VIN 15 I Supply voltage for the device. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS40060 TPS40061 1 2 7 + + 6 Ramp Generator Clock Oscillator 14 10 13 12 9 15 11 8 4 5 BP10 BP10 07VREF 7 7 16 3−bit up/down Fault Counter 7 7 7 07VREF 1V5REF 3V5REF Reference Voltages 7 Fault 7 Restart CLK 7 CLK BP5 7 3 BP5 7 7 Restart + 7 07VREF 7 7 Fault CL S Q R Q 7 CLK CL SW 7 SW S Q R Q 7 HDRV LDRV PGND BPN10 VIN BP10 SYNC RT KFF BP5 VFB SS/SD COMP ILIM SGND Zero Current Detector (TPS40060 Only) 10−V Regulator 7 1V5REF VIN 7 7 HDRV 7 HDRV 7 BPN10 7 + 0.85 V + N-Channel Driver P-Channel Driver UDG−02160 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com SIMPLIFIED BLOCK DIAGRAM 6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 UDG-02131 RAMP COMP SW VIN VIN SW COMP RAMP VPEAK VVALLEY T2 tON1 > tON2 and d1 > d2 t tON2 ON1 d tON T T1 RT 1 fSW17.8210623 k TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 APPLICATION INFORMATION The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application. The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It has two quadrant operation and will source or sink output current. This provides the best transient response. The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. This controller also emulates a standard buck converter at light loads where the inductor current goes discontinuous. At continuous output inductor currents the controller operates as a synchronous buck converter to optimize efficiency. SW NODE RESISTOR The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output current which flows during this dead time. This negative voltage could affect the operation of the controller, especially at low input voltages. Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as shown in Figure 14 as RSW. SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by Equation 1 and the relationship is charted in Figure 2. (1) PROGRAMMING THE RAMP GENERATOR CIRCUIT The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1). Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS40060 TPS40061 RKFF VIN (min)3.565.27RT1502 () 100 0 200 300 400 500 600 400 600 800 1000 700 200 800 FEED-FORWARD IMPEDANCE vs SWITCHING FREQUENCY RKFF - Feed-Forward Impedance - kW fSW - Switching Frequency - kHz VIN = 25 V VIN = 15 V VIN = 9 V RT - Timing Resistance - kW fSW - Switching Frequency - kHz TIMING RESISTANCE vs SWITCHING FREQUENCY 0 100 0 200 400 600 800 1000 200 300 400 500 600 RKFF VIN (min)3.565.27RT1502 () TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the minimum input voltage, VIN(min) through the following: where: • VIN is the desired start-up (UVLO) input voltage • RT is the timing resistor in kΩ (2) See the section on UVLO operation for further description. The curve showing the feedforward impedance required for a given switching frequency, fSW, at various input voltages is shown in Figure 3. For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltages. For more information on large duty cycle operation, refer to Application Note (SLUA310). Figure 2. Figure 3. UVLO OPERATION The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable undervoltage threshold. The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage condition exists if the device receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the oscillator frequency as described in Equation 3: 8 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 10 15 0.5 0 1.0 1.5 2.0 2.5 3.0 20 25 30 35 40 45 50 45 VUVLO - Output Voltage - V VUVLO - Undervoltage Lockout Threshold - V UNDERVOLTAGE LOCKOUT vs HYSTERESIS UDG-02132 Clock PWM RAMP PowerGood VIN UVLO Threshold 1 2 3 4 5 6 7 1 2 1 2 3 4 5 6 7 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 where: • VIN is the desired start-up (UVLO) input voltage • RT is the timing resistor in kΩ (3) The variable UVLO function utilizes a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter the clock cycle a powergood signal is asserted, a soft-start initiated, and the upper and lower MOSFETs are turned off. Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared (See Figure 4). Figure 4. Undervoltage Lockout Operation Figure 5. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS40060 TPS40061 CSS 2.3 A 0.7 V tSTART (Farads) tSTART 2LCO (seconds) TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com The impedance of the input voltage can cause the input voltage, at the TPS4006x, to sag when the converter starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to select the start-up voltage, the amount of hysteresis voltage is shown in Figure 5. PROGRAMMING SOFT START TPS4006x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on CSS minus 0.85 V, is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V VREF). The loop is closed on the lower of the (VCSS – 0.85 V) voltage or the internal reference voltage (0.7-V VREF). Once the (VCSS – 0.85 V) voltage rises above the internal reference voltage, regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-CO time constant as described in Equation 4. (4) There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit, which follows. The soft-start capacitance, CSS, is described in Equation 5. For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time should be longer than the time that the VINsupply transitions between 6 V and 7 V. (5) 10 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 RILIM IOCRDS(on)[max] ISINK VOS ISINK () ( ) ( ) O O LIM LOAD START C V I I A t é ´ ù = ê ú + ë û TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 PROGRAMMING CURRENT LIMIT This device uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven low. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 7 for typical overcurrent protection waveforms. The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at start-up (ILOAD). (6) The current limit programming resistor (RILIM) is calculated using Equation 7. Care must be taken in choosing the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. where: • ISINK is the current into the ILIM pin and is nominally 8.3 μA, minimum • IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current • VOS is the overcurrent comparator offset and is 50 mV maximum (7) BP5, BP10 AND BPN10 INTERNAL VOLTAGE REGULATOR Start-up characteristics of the BP5, BP10 and BPN10 regulators are shown in Figure 7. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BPN10 and BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS40060 TPS40061 VBPx - Output Voltage - V VIN - Input Voltage - V INTERNAL REGULATOR OUTPUT VOLTAGE vs INPUT VOLTAGE 2 4 6 8 10 12 6 8 10 12 2 4 0 BP10 BP5 BPN10 UDG-02136 HDRV CLOCK VVIN-VSW SS 7 CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES VILIM tBLANKING TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 6. Typical Current Limit Protection Waveforms Figure 7. CALCULATING THE BPN10 AND BP10V BYPASS CAPACITOR The BPN10 capacitance provides energy for the high-side driver. The BPN10 capacitor should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the high-side MOSFET and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance is described in Equation 8. 12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 L VINVOVO VINIfSW (H) KFF ( IN(min) ) ( T(dummy) ) R = V - 3.5V ´ 65.27 ´R +1502 W RT(dummy) 1 fSYNC17.8210623 k CBP10V QgSR V (F) CBPN10 Qg V (F) TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 (8) The 10-V reference pin, BP10V needs to provide energy for the synchronous MOSFET gate drive via the BP10V capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 9. (9) SYNCHRONIZING TO AN EXTERNAL SUPPLY The TPS4006x can be synchronized to an external clock through the SYNC pin. The SW node rises on the falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4006x to freely run at the frequency programmed by RT. Internally, the SYNC pin has a pull-down current between 5 μA and 10 μA. In order to synchronize the device to an external clock signal, the SYNC pin has to be overdriven from the external clock circuit. Normal logic gates or an external MOSFET with a pull-up resistor of 10 kΩ is adequate. Internally there is a delay of between approximately 50 ns and 100 ns from the time the SYNC pin is pulled low and the HDRV signal goes low to turn on the upper MOSFET. Additionally, there is some delay as the MOSFET gate charges to turn on the upper MOSFET, typically between 20 ns and 50 ns. The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a 'dummy' value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the design. where: • fSYNC is the synchronous frequency in kHz (10) Use the value of RT(dummy) to calculate the value for RKFF. where: • RT(dummy) is in kΩ (11) This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency. SELECTING THE INDUCTOR VALUE The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in Equation 12. where: • VO is the output voltage • ΔI is the peak-to-peak inductor current (12) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TPS40060 TPS40061 CO LIOH 2 IOL 2 Vf 2 Vi 2 (F) V2 Vf 2 Vi 2 Volts2 EC 12 CV2 (J) I2 IOH 2 IOL 2 (Amperes)2 EL 12 LI2 (J) V I ESR 1 8COfSW VPP TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com CALCULATING THE OUTPUT CAPACITANCE The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output ripple is described in Equation 13. (13) The output ripple voltage is typically between 90% and 95% due to the ESR component. The output capacitance requirement typically increases in the presence of a load transient requirement. During a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in Equation 14 and Equation 15. (14) where: where: • IOH is the output current under heavy load conditions • IOL is the output current under light load conditions (15) Energy in the capacitor is given by the following equation: (16) where: where: • Vf is the final peak capacitor voltage • Vi is the initial capacitor voltage (17) By substituting Equation 15 into Equation 14, substituting Equation 17 into Equation 16, setting Equation 14 equal to Equation 16 and solving for CO yields the following equation. (18) Loop Compensation Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40060 and TPS40061 use voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The generic modulator gain is described in Figure 8. 14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 fC fSW 4 (Hertz) BIAS O 0.7 R1 R V 0.7 ´ = W - fZ 1 2ESRCO (Hz) fLC 1 2LCO (Hz) ( ) ( ) IN min IN(min) MOD MOD dB RAMP RAMP V V A or A 20 log V V æ ö æ ö = ç ÷ = ´ ç ÷ ç ÷ ç ÷ è ø è ø D VO VIN VC VS or VO VC VIN VS TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 Duty cycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage, (19) With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore, the moderator DC gain is independent of the change of input voltage. For the TPS40060 and TPS40061 the modulator dc gain is shown in Equation 20, with VIN(min) as the minimum input voltage required to cause the ramp excursion to reach the maximum ramp amplitude of VRAMP. (20) Calculate the Poles and Zeros For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in Equation 21. (21) There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at the frequency calculated in Equation 22. (22) Calculate the value of RBIAS to set the output voltage, VO. (23) The maximum crossover frequency (0 dB loop gain) is set by Equation 24. (24) Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a –2 slope (-40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 9 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated. A Type III topology, shown in Figure 10, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 11. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to roll-off the overall gain at higher frequencies. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TPS40060 TPS40061 fC 1 2R1C2G (Hertz) fP1 1 2R2C2 (Hz) fP2 1 2R3C3 (Hz) fZ1 1 2R2C1 (Hz) fZ2 1 2R1C3 (Hz) RBIAS UDG−02189 + R1 R3 C3 C2 (optional) C1 R2 7 8 VREF COMP VFB VOUT GAIN 180° −90° −270° PHASE + 1 − 1 − 1 0 dB MODULATOR GAIN vs SWITCHING FREQUENCY ModulatorGain - dB fSW - Switching Frequency - Hz 100 1 k 10 k 100 k ESR Zero, + 1 LC Filter, - 2 AMOD = VIN(min) / VRAMP Resultant, - 1 VC PWM MODULATOR RELATIONSHIPS VS D = VC / VS TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 8. Figure 9. Figure 10. Type III Compensation of Configuration Figure 11. Type III Compensation Gain and Phase The poles and zeros for a type III network are described in Equation 25. (25) The value of R1 is somewhat arbitrary, but influences other component values. A value between 50kΩ and 100kΩ usually yields reasonable values. The unity gain frequency is described in Equation 26. where • G is the reciprocal of the modulator gain at fC (26) 16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 PSW(fsw) VINIOUTtSWfSW (Watts) IRMS IOd AmperesRMS PCOND IRMS 2 RDS(on)1TCRTJ25OC (W) R2(MIN) VC (max) ISOURCE (min) () 3.45 V 2.0 mA 1.725 k AMOD(f) AMODfLC fC 2 and G 1 AMOD(f) TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 The modulator gain as a function of frequency at fC, is described in Equation 27. (27) Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. (28) dv/dt INDUCED TURN-ON MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through currents. Therefore the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS capacitance. A 2-Ω to 5-Ω resistor in the upper MOSFET gate lead shapes the turn-on and dv/dt of the SW node and helps reduce the induced turn-on. HIGH-SIDE MOSFET POWER DISSIPATION The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by Equation 29. where: • TCR is the temperature coefficient of the MOSFET RDS(on) (29) The TCR varies depending on MOSFET technology and manufacturer but is typically ranges between 3500 ppm/°C and 1000 ppm/°C. The IRMS current for the high side MOSFET is described in Equation 30. (30) The switching losses for the high-side MOSFET are described in Equation 31. where: • IO is the DC output current • tSW is the switching rise time, typically < 20 ns • fSW is the switching frequency (31) Typical switching waveforms are shown in Figure 12. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TPS40060 TPS40061 PSR PDCPRRPCOND (W) PRR 0.5QRRVINfSW (W) PDC 2IOVFtDELAYfSW (W) IRMS IO1d ARMS PT PCONDPSW(fsw) (W) PT TJTA JA (W) UDG-02179 DI ANTI-CROSS CONDUCTION SYNCHRONOUS RECTIFIER ON BODY DIODE CONDUCTION BODY DIODE CONDUCTION HIGH SIDE ON ID1 ID2 IO SW 0 d 1-d TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 12. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by the following equation. (32) where: (33) and ΘJA is the package thermal impedance. SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using Equation 29 and the RMS current through the synchronous rectifier MOSFET is described in Equation 34. (34) The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross conduction delay time. The body diode conduction losses are described by Equation 35. where: • VF is the body diode forward voltage • tDELAY is the delay time just before the SW node rises (35) The 2-multiplier is used because the body-diode conducts twice during each cycle (once on the rising edge and once on the falling edge) The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 36. where: • QRR is the reverse recovery charge of the body diode (36) The total synchronous rectifier MOSFET power dissipation is described in Equation 37. (37) 18 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 ( ) ( ) ( ) ( ) J A Q JA IN SW g T T I V f Hz 2 Q æ é - ù ö ç ê ú - ÷ ç êë q ´ úû ÷ = è ø ´ PT 2QgfSWIQVIN (W) PT 2PD VDR IQVIN (W) PD = Qg ´ VDR ´ fSW (W / driver) TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 TPS40060/TPS40061 POWER DISSIPATION The power dissipation in the TPS40060 and TPS40061 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance, (refer to the second reference in the REFERENCES section) can be calculated from Equation 38. (38) And the total power dissipation in the device, assuming MOSFETs with similar gate charges for both the highside and synchronous rectifier is described in Equation 39. (39) or where: • IQ is the quiescent operating current (neglecting drivers) (40) The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. ΘJA = 36.51°C/W The maximum allowable package power dissipation is related to ambient temperature by Equation 36. Substituting Equation 32 into Equation 40 and solving for fSW yields the maximum operating frequency for the TPS40060 and TPS40061. The result is: (41) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com LAYOUT CONSIDERATIONS THE PowerPAD™ PACKAGE The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the dimensions of the circuit board pad are 5 mm x 3.4 mm. The dimensions of the package pad are shown in Figure 13. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package (see REFERENCES section) for more information on the PowerPAD package. Figure 13. PowerPAD Dimensions MOSFET PACKAGING MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on proper layout and thermal management. The θJAspecified in the MOSFET data sheet refers to a given copper area and thickness. In most cases, a thermal impedance of 40°C/W requires one square inch of 2-ounce copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer to the selected MOSFET's data sheet for more information regarding proper mounting. GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS The device provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor. Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. 20 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 Component placement should ensure that bypass capacitors (BP10, BP5, and BPN10) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BPN10, and the switch node (SW). Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TPS40060 TPS40061 PSW(fsw) VINIOtSWfSW 55 V5 A20 ns130 kHz 0.715 W PCOND 1.220.12(10.007(15025)) 0.324 W IRMS IOd 50.0588 1.2 A I IO20.2 520.2 2.0 A fSW 0.0588 400 ns 147 kHz 1 TSW fSW VO(min) VIN(max) TON VO(min) VIN(max) tON TSW or dMIN VO(min) VIN(max) 0.0588 dMAX VO(max) VIN(min) 0.187 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com DESIGN EXAMPLE • Input voltage: 18 VDC to 55 VDC • Output voltage: 3.3 V ±2% • Output current: 5 A (maximum, steady-state), 7 A (surge, 10-ms duration, 10% duty cycle maximum) • Output ripple: 33 mVP-P at 5 A • Output load response: 0.3 V => 10% to 90% step load change • Operating temperature: –40°C to 85°C • fSW = 130 kHz 1. Calculate maximum and minimum duty cycles (42) 2. Select switching frequency The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater than 330 ns (see Electrical Characteristics table). Therefore (43) (44) Using 400 ns to provide margin, (45) Since the oscillator can vary by 10%, decrease fSW, by 10% fSW = 0.9 × 147 kHz = 130 kHz and therefore choose a frequency of 130 kHz. 3. Select ΔI In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load. (46) 4. Calculate the high-side MOSFET power losses Power losses in the high-side MOSFET (Si9407AGY) at 55-VIN where switching losses dominate can be calculated from Equation 46 through Equation 49. (47) substituting Equation 47 into Equation 29 yields (48) and from Equation 31, the switching losses can be determined. (49) The MOSFET junction temperature can be found by substituting Equation 33 into Equation 32 22 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 RT 1 fSW17.82 E0623 k 408 k, use 412 k (55 3.3) 3.3 L 11.9 H 55 2 130 kHZ - ´ = = m ´ ´ J SR JA A ( ) T = P ´ q + T = 0.644 ´ 40 + 85 = 111°C SR RR COND DC P = P ´P ´P = 0.107 + 0.485 + 0.052 = 0.644 W PRR 0.5QRRVINfSW 0.530 nC55 V130 kHz 0.107 W DC O FD DELAY SW P = 2´I ´ V ´ t ´ f = 2´ 5 A ´ 0.8 V ´ 50 ns ´130 kHZ = 0.052 W ( ( )) 2 COND P = 4.85 ´ 0.011´ 1+ 0.007 150 - 25 = 0.485 W IRMS IO1d 510.0588 4.85 ARMS TJ PCONDPSWJATA (0.3240.715)4085 127OC TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 (50) 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two loss components, conduction, and diode reverse recovery losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from Equation 51 (51) The synchronous MOSFET conduction loss from Equation 29 is: (52) The body diode conduction loss from Equation 35 is: (53) The body diode reverse recovery loss from Equation 36 is: (54) The total power dissipated in the synchronous rectifier MOSFET from Equation 37 is: (55) The junction temperature of the synchronous rectifier at 85°C is: (56) In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. 6. Calculate the Inductor Value The inductor value is calculated from Equation 12. (57) A standard inductor value of 10-μH is chosen. A Coev DXM1306-10RO or Panasonic ETQPF102HFA could be used. 7. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be derived from following Equation 58, with fSW in kHz. (58) 8. Programming the Ramp Generator Circuit The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also controls the input UVLO voltage. For an undervoltage level of 14.4V (20% below the 18 VIN(min)), RKFF is calculated in Equation 59. RKFF = (80%xVIN(min) – 3.5)(65.27 ×RT + 1502) Ω = 309 kΩ, use 301 kΩ (59) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPS40060 TPS40061 fZ 1 20.012180 F 74 kHz fLC 1 2 10 H180 F 3.7 kHz AMOD(dB) = 20 ´log(9) = 19 dB MOD 18 A 9 2 = = RILIM 100.14 ISINK VOS ISINK 100.14 8.3 A (50 mV) 8.3 A 175 k 174 k ILIM 180 F3.3 1 m 7.0 7.6 A CSS 2.3 A 0.7 V 1 ms 3.28 nF 3300 pF 33 mV 2.0ESR 1 8180 F130 kHz 33 mV 2.0ESR 1 8127 F130 kHz CO 10 H5212 3.323.02 127 F TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com 9. Calculating the Output Capacitance (CO) In this example. the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1 A to 5 A step load. CO can be calculated using Equation 18. (60) Using Equation 13 calculate the ESR required to meet the output ripple requirements. (61) ESR = 8.9 mΩ In order to get the required ESR, the capacitance needs to be greater than the 127-μF calculated. For example, a single Panasonic SP capacitor, 180-μF with ESR of 12 mΩ can be used. Re-calculating the ESR required with the new value of 180-μF is shown in Equation 62. (62) ESR = 11.1 mΩ 10. Calculate the Soft-Start Capacitor (CSS) This design requires a soft-start time (tSTART) of 1 ms. CSS is calculated in Equation 63. (63) 11. Calculate the Current Limit Resistor (RILIM) The current limit set point depends on tSTART, VO, CO and ILOAD at start up as shown in Equation 7. (64) Set ILIM for 10.0 A minimum, then from Equation 7 (65) 12. Calculate Loop Compensation Values Calculate the DC modulator gain (AMOD) from Equation 20. (66) (67) Calculate the output poles and zeros from Equation 21 and Equation 22 of the L-C filter. (68) and (69) Select the close-loop 0 dB crossover frequency, fC. For this example fC = 10 kHz. Select the double zero location for the Type III compensation network at the output filter double pole at 3.7 kHz. Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7 kHz. 24 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 CBP10V QgSR V 57 nC 0.5 114 nF CBPN10 Qg V 30 nC 0.5 60 nF RBIAS 0.7 VR1 VO0.7 V 0.7 V100k 3.3 V0.7 V 26.9 k, choose 26.7 k Z1 1 1 f C1 4301pF, choose 3900 pF 2 R2 C1 2 10 k 3.7 kHz = \ = = p´ ´ p´ W´ P1 1 1 f R2 9.82 k , choose 10 k 2 R2 C2 2 220 pF 73.7 kHz = \ = = W W p´ ´ p´ ´ C 1 1 f C2 196 pF, choose 220 pF 2 R1 C2 G 2 100 k 0.81 10 kHz = \ = = p´ ´ ´ p´ W´ ´ P2 1 1 f R3 4.59 k , choose 4.64 k 2 R3 C3 2 470 pF 73.7 kHz = \ = = W W p´ ´ p´ ´ fZ2 1 2R1C3 C3 1 2100 k3.7 kHz 430 pF, choose 470 pF MOD(f ) 1 1 G 0.81 A 1.23 = = = 2 2 LC MOD(f ) MOD C f 3.7 kHz A A 9 1.23 f 10 kHz æ ö æ ö = ´ ç ÷ = ´ ç ÷ = è ø è ø TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain AMOD at the crossover frequency from Equation 27. (70) And also from Equation 27. (71) Choose R1 = 100 kΩ The poles and zeros for a Type III network are described in Equation 25 and Equation 26. (72) (73) (74) (75) (76) Calculate the value of RBIAS from Equation 23 with R1 = 100 kΩ. (77) CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin from Equation 8 is shown in Equation 78. (78) and the BP10V capacitance from Equation 9 is shown in Equation 79. (79) For this application, a 0.1-μF capacitor was used for the BPN10V and a 1.0-μF was used for the BP10V bypass capacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter specified in the design example. GATE DRIVE CONFIGURATION Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDS voltage and low gate threshold voltage of the Si4470, the design includes a 2-Ω in the gate lead of the upper MOSFET. The resistor can be used to shape the low-to-high transition of the Switch node and reduce the tendency of dv/dtinduced turn on. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: TPS40060 TPS40061 5 13 12 16 15 1 2 3 KFF RT BP5 SGND VIN BPN10 SW BP10 4 SYNC 11 ILIM TPS40060PWP 6 SS/SD 7 VFB 8 COMP HDRV 14 LDRV 10 PGND 9 + − + − PGND RILIM 174 kΩ 0.1 μF 2 Ω 10 μH Si4470 1.0 μF Si9407 CO 180 μF RT 412 kΩ RKFF 301 kΩ UDG−02161 0.1 μF CSS 3300 pF C1 3900 pF R2 10 kΩ R1 R3 100kΩ 4.64 kΩ C2 220 pF C3 470 pF RSW 10 Ω 30BQ060 RBIAS 26.7 kΩ VOUT VIN TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 14. Design Example, 48 V to 3.3 V at 5 A dc-to-dc Converter REFERENCES 1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2. 2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI Literature No. SLMA002 26 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 REVISION HISTORY Changes from Revision E (June 2006) to Revision F Page • Changed reference to Figure 13, PowerPad Dimensions, to Figure 14, Design Example, 48 V to 3.3 V at 5 A dc-todc Converter ......................................................................................................................................................................... 7 • Changed both (CSS – 0.85 V) voltages to (VCSS – 0.85 V) in Programming Soft Start ....................................................... 10 • Changed turn-on (IL) to start-up (ILOAD) in the third paragraph of Programming Current Limit section. ............................. 11 • Changed first instance of BPN10 to BP10 in respective section title. ................................................................................ 11 • Added high-side before MOSFET in the Calculating the BP10 and BP10V Bypass Capacitor section ............................. 12 • Changed HDRV signal goes high to ...goes low in the Synchronizing to an External Supply section ............................... 13 • Added equation definition for fSYNC to Equation 10 ............................................................................................................. 13 • Deleted k from KΩ at the end of equation Equation 11 ...................................................................................................... 13 • Added (dummy) to RT in Equation 11 definition ................................................................................................................. 13 • Changed sequence of equation substitutions from: Equation 14 into Equation 13, Equation 16 into Equation 15, Equation 13 equal to Equation 15, to: Equation 15 into Equation 14, Equation 17 into Equation 16, Equation 14 equal to Equation 16 ........................................................................................................................................................... 14 • Added generic before modulator gain in first paragraph of the Loop Compensation section ............................................ 14 • Deleted with VIN being the minimum input voltage required to cause the ramp excursion to cover the entire switching period. from first paragraph of the Loop Compensation section ........................................................................................ 14 • Deleted previous Equation 19, which was AMOD = VIN / VS or AMOD(db) = 20 × log (VIN / VS ) ............................................. 14 • Changed figure reference for modulator gain in the Loop Compensation from Figure 6 (Typical Current Limit Protection Waveforms) to Figure 8 (PWM MODULATOR RELATIONSHIPS) ................................................................... 14 • Added moderator DC gain and new Equation 20 to Loop Compensation section ............................................................. 15 • Changed VOUT to VOin sentence before and in Equation 23 .............................................................................................. 15 • Changed calculated in to set by in sentence before Equation 24 ...................................................................................... 15 • Changed VIN / VS to VIN(min) / VRAMP in the Modulator Gain vs Switching Frequency graph ............................................... 15 • Changed the TCR minimum value from 0.0035 to 3500 and the maximum from 0.010 to 10000 in the second paragraph of the High-Side MOSFET Power Dissipation section ...................................................................................... 17 • Changed VDD to VIN in Equation 41 .................................................................................................................................... 19 • Changed PowerPAD Dimensions to include x and y axis values ....................................................................................... 20 • Added high-side MOSFET to step four title ........................................................................................................................ 22 • Changed reference to substituting Equation 30 to Equation 47 ......................................................................................... 22 • Deleted IRMS 2 × RDS(ON) from synchronous MOSFET conduction equation ........................................................................ 23 • Changed synchronous MOSFET conduction equation equals value from 0.10 to 0.485 ................................................... 23 • Changed body diode conduction equation values: 100 ns to 50 ns and 0.104 W to 0.052 W ........................................... 23 • Changed power dissipation equation values: 0.1 to 0.485, 0.104 to 0.052, 0.311 W to 0.644 W ..................................... 23 • Changed junction temperature equation values: (0.311) to 0.644, 97°C to 111°C ............................................................ 23 • Changed Step 6 reference to Equation 11 to Equation 12 ................................................................................................. 23 • Changed inductor value equation in Step 6: replaced value of 48 with 55 and 11.8 with 11.9 .......................................... 23 • Changed RKFF equation values in Step 8:133.7 to 309 kΩ, 133 to 301 kΩ ........................................................................ 23 • Added 80%x before VIN(min) in RKFF equation in Step 8 ....................................................................................................... 23 • Changed first ESR value in Step 9 from 12.7 to 8.9 mΩ .................................................................................................... 24 • Changed second ESR value in Step 9 from 13.8 to 11.1 mΩ ............................................................................................ 24 • Changed DC modulator gain values in both equations: 10 to 18, 5 to 9; (5.0) to 9, 14 to 19 dB ...................................... 24 • Changed AMOD crossover frequency equation values: 5 to 9, 0.68 to 1.23 ..................................................................... 25 • Changed gain (G) equation values: 0.68 to 1.23, 1.46 to 0.81 .......................................................................................... 25 • Changed poles and zeros equation values: Equation 73, 73.3 to 73.7 kHZ, 4.62 to 4.59 kΩ; Equation 74, 3.29 to 0.81, 1.46 to 10 kHZ, 109 to 196 pF, 100 to 220 pF; Equation 75, 100 to 200 pF, 73.3 to 73.7 kHz, 21.7 to 9.82 kΩ, Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com 21.5 to 10 kΩ; Equation 76, 21.5 to 10 kΩ, 2000 to 4301 pF, 1800 to 3900 pF ................................................................ 25 • Changed Design Example graphic to include new values from equation: 133 to 301 kΩ, 1800 to 3900 pF, 21.5 to 10 kΩ, 100 to 220 pF. Si9470 to Si9407 ................................................................................................................................. 25 • Added link references to hard-coded references throughout document ............................................................................. 26 28 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TPS40060PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40060PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40060PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40060PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40061PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 TPS40061PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 TPS40061PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 TPS40061PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES025B January 2002–Revised May 2011 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Contents 1 Introduction ........................................................................................................................ 9 1.1 Features ...................................................................................................................... 9 1.2 Description ................................................................................................................. 10 1.3 Functional Block Diagram ................................................................................................ 11 1.4 Ordering Information ...................................................................................................... 11 1.5 Terminal Assignments—Normal Mode ................................................................................. 12 1.6 Terminal Assignments—External MCU Mode ......................................................................... 12 1.7 Terminal Functions ........................................................................................................ 13 1.8 Device Operation Modes ................................................................................................. 15 1.9 Terminal Assignments for Codec Port Interface Modes .............................................................. 15 2 Detailed Description .......................................................................................................... 16 2.1 Architectural Overview .................................................................................................... 16 2.1.1 Oscillator and PLL .............................................................................................. 16 2.1.2 Clock Generator and Sequencer Logic ...................................................................... 16 2.1.3 Adaptive Clock Generator (ACG) ............................................................................. 16 2.1.4 USB Transceiver ................................................................................................ 16 2.1.5 USB Serial Interface Engine (SIE) ........................................................................... 16 2.1.6 USB Buffer Manager (UBM) .................................................................................. 17 2.1.7 USB Frame Timer .............................................................................................. 17 2.1.8 USB Suspend and Resume Logic ............................................................................ 17 2.1.9 MCU Core ....................................................................................................... 17 2.1.10 MCU Memory ................................................................................................... 17 2.1.11 USB Endpoint Configuration Blocks and Buffer Space .................................................... 17 2.1.12 DMA Controller .................................................................................................. 17 2.1.13 Codec Port Interface ........................................................................................... 18 2.1.14 I2C Interface ..................................................................................................... 18 2.1.15 General-Purpose IO Ports (GPIO) ........................................................................... 18 2.1.16 Interrupt Logic ................................................................................................... 18 2.1.17 Reset Logic ...................................................................................................... 18 2.2 Device Operation .......................................................................................................... 19 2.2.1 Clock Generation ............................................................................................... 19 2.2.2 Boot Process .................................................................................................... 19 2.2.2.1 EEPROM Boot Process ........................................................................... 19 2.2.2.2 Host Boot Process ................................................................................. 19 2.2.2.3 EEPROM Data Organization ..................................................................... 20 2.2.2.4 I2C Serial EEPROM ................................................................................ 21 2.2.2.5 DFU Upgrade Process ............................................................................ 22 2.2.2.6 Download Error Recovery ........................................................................ 22 2.2.2.7 ROM Support Functions .......................................................................... 22 2.2.3 USB Enumeration .............................................................................................. 23 2.2.4 TAS1020B USB Reset Logic .................................................................................. 23 2.2.5 USB Suspend and Resume Modes .......................................................................... 24 2.2.5.1 USB Suspend Mode ............................................................................... 24 2.2.5.2 USB Resume Mode ................................................................................ 25 2.2.5.3 USB Remote Wake-Up Mode .................................................................... 25 2 Contents Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.6 Adaptive Clock Generator (ACG) ............................................................................. 26 2.2.6.1 Programmable Frequency Synthesizer ......................................................... 27 2.2.6.2 Capture Counter and Register ................................................................... 28 2.2.7 USB Transfers .................................................................................................. 29 2.2.7.1 Control Transfers ................................................................................... 29 2.2.7.2 Interrupt Transfers ................................................................................. 31 2.2.7.3 Bulk Transfers ...................................................................................... 32 2.2.7.4 Isochronous Transfers ............................................................................. 35 2.2.8 Microcontroller Unit ............................................................................................. 39 2.2.9 External MCU Mode Operation ............................................................................... 39 2.2.10 Interrupt Logic ................................................................................................... 39 2.2.11 General-Purpose I/O (GPIO) Ports ........................................................................... 45 2.2.11.1 Port 3 GPIO Bits ................................................................................... 47 2.2.11.2 Port 1 GPIO Bits ................................................................................... 48 2.2.11.3 Pullup Macro ........................................................................................ 48 2.2.12 DMA Controller .................................................................................................. 49 2.2.13 Codec Port Interface ........................................................................................... 49 2.2.13.1 General-Purpose Mode of Operation ............................................................ 50 2.2.13.2 Audio Codec (AC) '97 1.0 Mode of Operation ................................................. 57 2.2.13.3 Audio Codec (AC) '97 2.0 Mode of Operation ................................................. 58 2.2.13.4 Inter-IC Sound (I2S) Modes of Operation ....................................................... 59 2.2.13.5 AIC Mode of Operation ............................................................................ 61 2.2.13.6 Bulk Mode ........................................................................................... 61 2.2.14 I2C Interface ..................................................................................................... 62 2.2.14.1 Data Transfers ...................................................................................... 62 2.2.14.2 Single Byte Write ................................................................................... 63 2.2.14.3 Multiple Byte Write ................................................................................. 64 2.2.14.4 Single Byte Read ................................................................................... 64 2.2.14.5 Multiple Byte Read ................................................................................. 65 3 Electrical Specifications ..................................................................................................... 66 3.1 Absolute Maximum Ratings .............................................................................................. 66 3.2 Dissipation Ratings ........................................................................................................ 66 3.3 Recommended Operating Conditions .................................................................................. 66 3.4 Electrical Characteristics ................................................................................................. 66 3.5 Timing Characteristics .................................................................................................... 67 3.6 Clock and Control Signals ................................................................................................ 67 3.7 USB Signals When Sourced by TAS1020B ............................................................................ 67 3.8 Codec Port Interface Signals (AC ’97 Modes) ......................................................................... 68 3.9 Codec Port Interface Signals (I2S Modes) ............................................................................. 69 3.10 Codec Port Interface Signals (General-Purpose Mode) .............................................................. 69 3.11 I2C Interface Signals ...................................................................................................... 70 4 Application Information ...................................................................................................... 71 5 8K ROM ............................................................................................................................ 72 5.1 ROM Errata ................................................................................................................. 72 6 MCU Memory and Memory-Mapped Registers ....................................................................... 73 6.1 MCU Memory Space ...................................................................................................... 73 6.2 Internal Data Memory ..................................................................................................... 73 Copyright © 2002–2011, Texas Instruments Incorporated Contents 3 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.3 External MCU Mode Memory Space .................................................................................... 75 6.4 USB Endpoint Configuration Blocks and Data Buffer Space ........................................................ 76 6.4.1 USB Endpoint Configuration Blocks ......................................................................... 76 6.4.2 Data Buffer Space .............................................................................................. 76 6.4.3 USB OUT Endpoint Configuration Bytes .................................................................... 80 6.4.3.1 USB OUT Endpoint - Y Buffer Data Count Byte (OEPDCNTYx) ............................ 80 6.4.3.2 USB OUT Endpoint - Y Buffer Base Address Byte (OEPBBAYx) ........................... 80 6.4.3.3 USB OUT Endpoint - X Buffer Data Count Byte (OEPDCNTXx) ............................ 81 6.4.3.4 USB OUT Endpoint - X and Y Buffer Size Byte (OEPBSIZx) ................................ 81 6.4.3.5 USB OUT Endpoint - X Buffer Base Address Byte (OEPBBAXx) ........................... 81 6.4.3.6 USB OUT Endpoint - Configuration Byte (OEPCNFx) ........................................ 82 6.4.4 USB IN Endpoint Configuration Bytes ....................................................................... 83 6.4.4.1 USB IN Endpoint - Y Buffer Data Count Byte (IEPDCNTYx) ................................ 83 6.4.4.2 USB IN Endpoint - Y Buffer Base Address Byte (IEPBBAYx) ............................... 84 6.4.4.3 USB IN Endpoint - X Buffer Data Count Byte (IEPDCNTXx) ................................ 84 6.4.4.4 USB IN Endpoint - X and Y Buffer Size Byte (IEPBSIZx) .................................... 84 6.4.4.5 USB IN Endpoint - X Buffer Base Address Byte (IEPBBAXx) ............................... 85 6.4.4.6 USB IN Endpoint - Configuration Byte (IEPCNFx) ............................................ 85 6.4.5 USB Control Endpoint Setup Stage Data Packet Buffer .................................................. 86 6.5 Memory-Mapped Registers .............................................................................................. 87 6.5.1 USB Registers .................................................................................................. 89 6.5.1.1 USB Function Address Register (USBFADR - Address FFFFh) ............................ 89 6.5.1.2 USB Status Register (USBSTA - Address FFFEh) ............................................ 90 6.5.1.3 USB Interrupt Mask Register (USBIMSK - Address FFFDh) ................................. 91 6.5.1.4 USB Control Register (USBCTL - Address FFFCh) ........................................... 91 6.5.1.5 USB Frame Number Register (Low Byte) (USBFNL - Address FFFBh) .................... 92 6.5.1.6 USB Frame Number Register (High Byte) (USBFNH - Address FFFAh) ................... 92 6.5.2 DMA Registers .................................................................................................. 92 6.5.2.1 DMA Time Slot Assignment Register (Low Byte) (DMATSL1 - Address FFF0h) (DMATSL0 - Address FFEAh) .................................................................................. 92 6.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 - Address FFEFh) (DMATSH0 - Address FFE9h) ................................................................... 93 6.5.2.3 DMA Control Register (DMACTL1 - Address FFEEh) (DMACTL0 - Address FFE8h) .... 93 6.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L - Address FFF3h) (DMABCNT0L- Address FFEBh) ................................................................. 93 6.5.2.5 DMA Current Buffer Content Register (High Byte) (DMABCNT1H - Address FFF4h) (DMABCNT0H - Address FFECh) ............................................................... 94 6.5.2.6 DMA Bulk Packet Count Register (Low Byte) (DMABPCT0 - Address FFF2h) ........... 94 6.5.2.7 DMA Bulk Packet Count Register (High-byte) (DMABPCT1 - Address FFF1h) ........... 94 6.5.2.8 UBM Write Pointer (Low Byte) (Ch0WrPtrL - Address FFBCh) (Ch1WrPtrL - Address FFB8h) .............................................................................................. 94 6.5.2.9 UBM Write Pointer (High Byte) (Ch0WrPtrH - Address FFBBh) (Ch1WrPtrH - Address FFB7h) .............................................................................................. 95 6.5.2.10 DMA Read Pointer (Low Byte) (Ch0RdPtrL - Address FFBAh) (Ch1RdPtrL - Address FFB6h) .............................................................................................. 95 6.5.2.11 DMA Read Pointer (High Byte) (Ch0RdPtrH - Address FFB9h) (Ch1RdPtrH - Address FFB5h) .............................................................................................. 95 6.5.3 Adaptive Clock Generator Registers ......................................................................... 96 6.5.3.1 Adaptive Clock Generator1 Frequency Register (Byte 0) (ACG1FRQ0 - Address FFE7h) 4 Contents Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 ........................................................................................................ 96 6.5.3.2 Adaptive Clock Generator1 Frequency Register (Byte 1) (ACG1FRQ1 - Address FFE6h) ........................................................................................................ 96 6.5.3.3 Adaptive Clock Generator1 Frequency Register (Byte 2) (ACG1FRQ2 - Address FFE5h) ........................................................................................................ 96 6.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL - Address FFE4h) .............................................................................................. 97 6.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH - Address FFE3h) .............................................................................................. 97 6.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 - Address FFF9h) ........................................................................................................ 97 6.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 - Address FFF8h) ........................................................................................................ 97 6.5.3.8 Adaptive Clock Generator2 Frequency Register (Byte 2) (ACG2FRQ2 - Address FFF7h) ........................................................................................................ 98 6.5.3.9 Adaptive Clock Generator2 Divider Control Register (ACG2DCTL - Address FFF6h) ... 98 6.5.3.10 Adaptive Clock Generator1 Divider Control Register (ACG1DCTL - Address FFE2h) ... 98 6.5.3.11 Adaptive Clock Generator Control Register (ACGCTL - Address FFE1h) ................. 99 6.5.4 Codec Port Interface Registers .............................................................................. 100 6.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 - Address FFE0h) ........... 100 6.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 - Address FFDFh) .......... 101 6.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF3 - Address FFDEh) .......... 102 6.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 - Address FFDDh) .......... 103 6.5.4.5 Codec Port Interface Control and Status Register (CPTCTL - Address FFDCh) ........ 104 6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh) .................... 105 6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh) ......... 105 6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h) ......... 105 6.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL - Address FFD8h) ....................................................................................................... 106 6.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH - Address FFD7h) ....................................................................................................... 106 6.5.4.11 Codec Port Receive Interface Configuration Register 2 (CPTRXCNF2 - Address FFD6h) ....................................................................................................... 107 6.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 - Address FFD5h) ....................................................................................................... 108 6.5.4.13 Codec Port Receive Interface Configuration Register 4 (CPTRXCNF4 - Address FFD4h) ....................................................................................................... 109 6.5.5 P3 Mask Register ............................................................................................. 109 6.5.5.1 P3 Mask Register (P3MSK - Address FFCAh) ............................................... 109 6.5.6 I2C Interface Registers ....................................................................................... 110 6.5.6.1 I2C Interface Address Register (I2CADR - Address FFC3h) ............................... 110 6.5.6.2 I2C Interface Receive Data Register (I2CDATI - Address FFC2h) ......................... 110 6.5.6.3 I2C Interface Transmit Data Register (I2CDATO - Address FFC1h) ....................... 110 6.5.6.4 I2C Interface Control and Status Register (I2CCTL - Address FFC0h) ................... 111 6.5.7 Miscellaneous Registers ..................................................................................... 112 6.5.7.1 USB OUT endpoint Interrupt Register (OEPINT - Address FFB4h) ....................... 112 6.5.7.2 USB IN endpoint Interrupt Register (IEPINT - Address FFB3h) ........................... 112 6.5.7.3 Interrupt Vector Register (VECINT - Address FFB2h) ....................................... 113 6.5.7.4 Global Control Register (GLOBCTL - Address FFB1h) ..................................... 114 6.5.7.5 Memory Configuration Register (MEMCFG - Address FFB0h) ............................. 114 Copyright © 2002–2011, Texas Instruments Incorporated Contents 5 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com List of Figures 2-1 Adaptive Clock Generator Block Diagram .................................................................................... 27 2-2 TAS1020B Interrupt, Reset, Suspend, and Resume Logic ................................................................. 41 2-3 Activation of Setup Stage Transaction Overwrite Interrupt ................................................................. 43 2-4 GPIO Port 1 and Port 3 Functionality.......................................................................................... 46 2-5 Pull-Up Logic Symbol............................................................................................................ 48 2-6 Codec Port Interface Parameters − AC '97 1.0 .............................................................................. 53 2-7 Codec Port Interface Parameters − AIC ...................................................................................... 54 2-8 Codec Port Interface Parameters – I2S........................................................................................ 57 2-9 Byte Reversal Example ......................................................................................................... 57 2-10 Connection of the TAS1020B to an AC '97 Codec .......................................................................... 58 2-11 Connection of the TAS1020B to Multiple AC '97 Codecs................................................................... 59 2-12 Bit Transfer on the I2C Bus ..................................................................................................... 62 2-13 I2C START and STOP Conditions ............................................................................................. 63 2-14 TAS1020B Acknowledge on the I2C Bus...................................................................................... 63 2-15 Single Byte Write Transfer ...................................................................................................... 64 2-16 Multiple Byte Write Transfer .................................................................................................... 64 2-17 Single Byte Read Transfer ...................................................................................................... 64 2-18 Multiple Byte Read Transfer .................................................................................................... 65 3-1 External Interrupt Timing Waveform ........................................................................................... 67 3-2 USB Differential Driver Timing Waveform..................................................................................... 67 3-3 BIT_CLK and SYNC Timing Waveforms...................................................................................... 68 3-4 SYNC, SD_IN, and SD_OUT Timing Waveforms............................................................................ 68 3-5 I2S Mode Timing Waveforms ................................................................................................... 69 3-6 General-Purpose Mode Timing Waveforms .................................................................................. 69 3-7 SCL and SDA Timing Waveforms.............................................................................................. 70 3-8 Start and Stop Conditions Timing Waveforms................................................................................ 70 3-9 Acknowledge Timing Waveform................................................................................................ 70 4-1 Typical TAS1020B Device Connections....................................................................................... 71 6-1 Boot Loader Mode Memory Map............................................................................................... 75 6-2 Normal Operating Mode Memory Map ........................................................................................ 75 6-3 USB Endpoint Configuration Blocks and Buffer Space Memory Map..................................................... 77 6 List of Figures Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 List of Tables 1-1 Terminal Functions—Normal Mode ........................................................................................... 13 1-2 Terminal Functions—External MCU Mode ................................................................................... 14 1-3 Operating Mode After Reset .................................................................................................... 15 1-4 Terminal Assignments for Codec Port Interface Modes..................................................................... 15 2-1 EEPROM Header ................................................................................................................ 21 2-2 AGC Control Registers .......................................................................................................... 27 2-3 ACG Frequency Registers ...................................................................................................... 28 2-4 Electrical Characteristics of Pullup Resistors................................................................................. 48 2-5 Terminal Assignments for Codec Port Interface General-Purpose Mode................................................. 50 2-6 Terminal Assignments for Codec Port Interface AC '97 1.0 Mode 2 ...................................................... 57 2-7 Terminal Assignments for Codec Port Interface AC '97 2.0 Mode 3 ...................................................... 58 2-8 Terminal Assignments for Codec Port Interface I2S Mode 4 and Mode 5 ................................................ 59 2-9 SLOT Assignments for Codec Port Interface I2S Mode 4................................................................... 60 2-10 SLOT Assignments for Codec Port Interface I2S Mode 5................................................................... 60 2-11 Terminal Assignments for Codec Port Interface AIC Mode 1 .............................................................. 61 6-1 USB Endpoint Configuration Blocks Address Map .......................................................................... 77 6-2 USB Control Endpoint Setup Data Packet Buffer Address Map ........................................................... 86 6-3 Memory-Mapped Registers Address Map .................................................................................... 87 Copyright © 2002–2011, Texas Instruments Incorporated List of Tables 7 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 8 List of Tables Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 USB Streaming Controller Check for Samples: TAS1020B 1 Introduction 1.1 Features 1 • Universal Serial Bus (USB) • DMA Controller – USB specification version 1.1 compatible – Two DMA channels to support streaming – USB audio class specification 1.0 compatible USB audio data to/from the codec port – Integrated USB transceiver interface – Supports 12 Mb/s data rate (full speed) – Each channel can support a single USB – Supports suspend/resume and remote isochronous endpoint wake-up – In the I2S mode the device can support – Supports control, interrupt, bulk, and DAC/ADCs at different sampling frequencies isochronous data transfer type – A circular programmable FIFO used for – Supports up to a total of seven IN endpoints isochronous audio data streaming and seven OUT endpoints in addition to the • Codec Port Interface control endpoint – Configurable to support AC '97 1.x, AC '97 – Data transfer type, data buffer size, single or 2.x, AIC, or I2S serial interface formats double buffering is programmable for each – I2S modes can support a combination of one endpoint stereo DAC and/or two stereo ADCs – On-chip adaptive clock generator (ACG) – Can be configured as a general-purpose supports asynchronous, synchronous and serial interface adaptive synchronization modes for – Can support bulk data transfer using DMA isochronous endpoints for higher throughput – To support synchronization for streaming • I2C Interface USB audio data, the ACG can be used to – Master only interface generate the master clock for the codec – Does not support a multimaster bus • Micro-Controller Unit (MCU) environment – Standard 8052 8-bit core – Programmable to 100 kb/s or 400 kb/s data – 8K bytes of program memory ROM that transfer speeds contains a boot loader program and a library – Supports wait states to accommodate slow of commonly used USB functions slaves – 6016 bytes of program memory RAM which • General Characteristics is loaded by the boot loader program – High performance 48-pin TQFP Package – 256 bytes of internal data memory RAM – On-chip phase-locked loop (PLL) with – Two GPIO ports internal oscillator is used to generate – MCU handles all USB control, interrupt, and internal clocks from a 6 MHz crystal input bulk endpoint transfers – Reset output available which is asserted for both system and USB reset – External MCU mode supports application firmware development – 8K ROM with boot loader program and commonly used USB functions library – 3.3 V core and I/O buffers 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 1.2 Description The TAS1020B integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed specifically for applications that require isochronous data streaming. Applications include digital speakers, which require the streaming of digital audio data between the host PC and the speaker system via the USB connection. The TAS1020B device is fully compatible with the USB Specification Version 1.1 and the USB Audio Class 1.0 Specification. The TAS1020B uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization, the boot loader program downloads the application program code to a 6,016-byte RAM from either the host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk endpoint transactions. DMA channels are provided to handle isochronous endpoint transactions. The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition to the USB control endpoint, support is provided for up to seven IN endpoints and seven OUT endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint configuration blocks that reside in on-chip RAM. All USB data transfer types are supported. The TAS1020B device also includes a codec port interface (C-Port) that can be configured to support several industry standard serial interface protocols. These protocols include the audio codec (AC) '97 Revision 1.X, the AC '97 Revision 2.X and several inter-IC sound (I2S) modes. A direct memory access (DMA) controller with two channels is provided for streaming the USB isochronous data packets to/from the codec port interface. Each DMA channel can support one USB isochronous endpoint. An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization modes, which include asynchronous, synchronous and adaptive. Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit general-purpose input/output (GPIO) ports. The TAS1020B device is implemented in a 3.3-V 0.25 μm CMOS technology. 10 Introduction Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B 8052 Core I2C Control 8K ROM 6016 Byte RAM USB Serial OSC PLL ACG Suspend /Resume Logic I2C Bus C−Port Port−3 Port−1 USB SOF 6 MHz Interface Engine CODEC Interface 1520 Byte SRAM UBM DMA Global Control/Status Registers TQFP Texas Instruments Package Type Peripheral Device Audio Solutions 48 pins PFB T AS 1020B PFB TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 1.3 Functional Block Diagram 1.4 Ordering Information Copyright © 2002–2011, Texas Instruments Incorporated Introduction 11 Submit Documentation Feedback Product Folder Link(s): TAS1020B 2 3 P1.1 P1.0 NC DVDD NC P3.5 P3.4 P3.3 DVSS P3.2/XINT P3.1 P3.0 24 23 22 21 20 19 18 17 16 15 14 13 4 37 38 39 40 41 42 43 44 45 46 47 48 CSCLK CDATO MCLKO1 MCLKO2 RESET VREN SDA SCL AVSS XTALO XTALI PLLFILI 5 6 7 8 P1.5 P1.4 P1.3 36 35 34 33 32 31 30 CDATI CSYNC CRESET CSCHNE DV TEST EXTEN RSTO MCLKI PUR DP DM MRESET 29 28 27 26 9 10 11 12 25 1 P1.2 P1.7 P1.6 DD PLLFILO AV DVSS DVDD DD DVSS TAS1020B 2 3 MCUAD1 MCUAD0 MCURD DVDD MCUWR MCUINTO MCUALE MCUA10 DVSS XINT MCUA9 MCUA8 24 23 22 21 20 19 18 17 16 15 14 13 4 37 38 39 40 41 42 43 44 45 46 47 48 CSCLK CDATO MCLKO1 MCLKO2 RESET VREN SDA SCL AVSS XTALO XTALI PLLFILI 5 6 7 8 MCUAD4 MCUAD3 36 35 34 33 32 31 30 CDATI CSYNC CRESET DV TEST EXTEN RSTO MCLKI PUR DP DM MRESET 29 28 27 26 9 10 11 12 25 1 MCUAD2 DD PLLFILO AV DVSS DVDD DD DVSS TAS1020B MCUAD5 MCUAD6 MCUAD7 CSCHNE TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 1.5 Terminal Assignments—Normal Mode PFB PACKAGE (Normal Mode) (TOP VIEW) 1.6 Terminal Assignments—External MCU Mode PFB PACKAGE (External Mode) (TOP VIEW) 12 Introduction Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 1.7 Terminal Functions Table 1-1. Terminal Functions—Normal Mode TERMINAL I/O DESCRIPTION NAME PIN TYPE NO. AVDD Power 2 3.3-V analog supply voltage AVSS Power 45 Analog ground CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock the CSYNC, CDATO, CDATI, CRESET, AND CSCHNE signals. CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port interface. CDATO CMOS 38 O Codec port interface serial data out CDATI CMOS 36 I Codec port interface serial data in CRESET CMOS 34 O Codec port interface reset output (see Table 1-4 for alternate uses) CSCHNE CMOS 32 I/O Codec port interface secondary channel enable (see Table 1-4 for alternate uses) DP CMOS 6 I/O USB differential pair data signal plus. DP is the positive signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DVDD Power 8, 21, 33 3.3-V digital supply voltage DVSS Power 4, 16, 28 Digital ground EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU mode MCLKI CMOS 3 I Master clock input. An input that can be used as the master clock for the codec port interface or the source for MCLKO2. MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for the codec port interface and the codec. MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec port interface and the codec used in I2S modes for receive. This clock signal can also be used as a miscellaneous clock. MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state NC 20,22 Not used P1.[0:7] CMOS 23, 24, 25, I/O General-purpose I/O port [bits 0 through 7]: A bidirectional 8-bit I/O port with an internal 26, 27, 29, 100-μA active pullup 30, 31 P3.[0:5] CMOS 13, 14, 15, I/O General-purpose I/O port [bits 0 through 5]: A bidirectional I/O port with an internal 17, 18, 19 100-μA active pullup PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components PLLFILO CMOS 1 O PLL loop filter output: Output from on-chip PLL to external filter components PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup resistor on the DP signal from a high-impedance state to 3.3 V. When the DP signal is connected to 3.3-V the host PC detects the connection of the TAS1020B device to the universal serial bus. RESET CMOS 41 O General-purpose active-low output which is memory mapped RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is active SCL CMOS 44 O I2C interface serial clock SDA CMOS 43 I/O I2C interface serial data TEST CMOS 10 I Test mode enable: Factory test mode VREN CMOS 42 O General-purpose active-low output which is memory mapped XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal XTALO CMOS 46 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal Copyright © 2002–2011, Texas Instruments Incorporated Introduction 13 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 1-2. Terminal Functions—External MCU Mode TERMINAL I/O DESCRIPTION NAME PIN TYPE NO. AVDD Power 2 - 3.3-V Analog supply voltage AVSS Power 45 - Analog ground CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock the CSYNC, CDATO, CDATI, CRESET AND CSCHNE signals. CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port interface. CDATO CMOS 38 O Codec port interface serial data output CDATI CMOS 36 I Codec port interface serial data input CRESET CMOS 34 O Codec port interface reset output (see Table 1-4 for alternate uses) CSCHNE CMOS 32 I/O Codec port interface secondary channel enable (see Table 1-4 for alternate uses) DP CMOS 6 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DVDD Power 8, 21, 33 - 3.3-V Digital supply voltage DVSS Power 4, 16, 28 - Digital ground EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal uses a 3.3 V TTL/LVCMOS input buffer. MCLKI CMOS 3 I Master clock input: An input that can be used as the master clock for the codec port interface or the source for MCLKO2. MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for the codec port interface and the codec. MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec port interface and the codec. This clock signal can also be used as a miscellaneous clock. MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state. MCUAD [0:7] CMOS 23, 24, 25, I/O MCU multiplexed address/data: Multiplexed address bits[0:7]/data bits[0:7] for external 26, 27, 29, MCU access to the TAS1020B external data memory space. 30, 31 MCUA [8:10] CMOS 13, 14, 17 I/O MCU address bus: Multiplexed address bus bits[8:10] for external MCU access to the TAS1020B external data memory space. MCUALE CMOS 18 I MCU address latch enable: Address latch enable for external MCU access to the TAS1020B external data memory space. MCUINTO CMOS 19 O MCU interrupt output: Interrupt output to be used for external MCU INTO input signal. All internal TAS1020B interrupt sources are read together to generate this output signal. MCUWR CMOS 20 I MCU write strobe: Write strobe for external MCU write access to the TAS1020B external data memory space. MCURD CMOS 22 I MCU read strobe: Read strobe for external MCU read access to the TAS1020B external data memory space. PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components. PLLFILO CMOS 1 O PLL loop filter output: Output to on-chip PLL from external filter components. PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup resistor on the DP signal to 3.3V from a high-impedance state. When the DP signal is connected in a 3.3-V state, the host PC should detect the connection of the TAS1020B device to the universal serial bus. RESET CMOS 41 O General-purpose active-low output which is memory mapped RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is active. SCL CMOS 44 O I2C interface serial clock SDA CMOS 43 I/O I2C interface serial data input/output TEST CMOS 10 I Test mode enable: Factory text mode 14 Introduction Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Table 1-2. Terminal Functions—External MCU Mode (continued) TERMINAL I/O DESCRIPTION NAME PIN TYPE NO. VREN CMOS 42 O General-purpose active-low output which is memory mapped. XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal. XTALO CMOS 46 O Crystal output: Output from the on-chip oscillator to an external 6-MHz crystal. 1.8 Device Operation Modes The EXTEN and TEST pins define the mode that the TAS1020B is in after reset. Table 1-3. Operating Mode After Reset MODE EXTEN TEST Normal mode - internal MCU 0 0 External MCU mode 1 0 Factory test 0 1 Factory test 1 1 1.9 Terminal Assignments for Codec Port Interface Modes The codec port interface has five modes of operation that support AC '97, I2S, and AIC codecs. There is also a general-purpose mode that is not specific to a serial interface. The mode is programmed by writing to the mode select field of the codec port interface configuration register 1 (CPTCNF1). The codec port interface terminals CSYNC, CSCLK, CDATO, CDATI, CRESET, and CSCHNE take on functionality appropriate to the mode programmed as shown in the following table. Table 1-4. Terminal Assignments for Codec Port Interface Modes(1) (2) (3) TERMINAL GP AIC AC '97 v1.x AC '97 v2.x I2S I2S NO. NAME Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 35 CSYNC CSYNC I/O FS O SYNC O SYNC O LRCK O LRCK1 O 37 CSCLK CSCLK I/O SCLK O BIT_CLK I BIT_CLK I SCLK O SCLK1 O 38 CDATO CDATO O DOUT O SD_OUT O SD_OUT O SDOUT1 O SDOUT1 O 36 CDATI CDATI I DIN I SD_IN I SD_IN1 I SDIN1 I SDIN2 I 34 CRESET CRESET O RESET O RESET O RESET O CRESET O SCLK2 O 32 CSCHNE NC O FC O NC O SD_IN2 I SDIN2 I LRCK2 O (1) Signal names and I/O direction are with respect to the TAS1020B device. The signal names used for the TAS1020B terminals for the various codec port interface modes reflect the nomenclature used by the codec devices. (2) NC indicates no connection for the terminal in a particular mode. The TAS1020B device drives the signal as an output for these cases. (3) The CSYNC and CSCLK signals can be programmed as either an input or an output in the general-purpose mode. Copyright © 2002–2011, Texas Instruments Incorporated Introduction 15 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2 Detailed Description 2.1 Architectural Overview 2.1.1 Oscillator and PLL Using an external 6-MHz crystal, the TAS1020B derives the fundamental 48-MHz internal clock signal using an on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated by the clock generator and adaptive clock generator. 2.1.2 Clock Generator and Sequencer Logic Utilizing the 48-MHz output from the PLL, the clock generator logic generates all internal clock signals, except for the codec port interface master clock (MCLK) and serial clock (CSCLK) signals. The TAS1020B internal clocks include the 48-MHz clock, a 24-MHz clock, and a 12-MHz clock. A 12 MHz USB clock is also generated. The USB clock is the same as the internal 12-MHz clock when the TAS1020B is transmitting data, but is derived from the data when the TAS1020B is receiving data. To derive the USB clock when receiving USB data, the TAS1020B utilizes an internal digital PLL (DPLL) driven from the 48-MHz clock. The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and the USB endpoint buffer space. The SRAM can be accessed by the MCU, the USB buffer manager (UBM), or the DMA channels. The sequencer controls the access to the memory using a round-robin fixed priority arbitration scheme. This means that the sequencer logic generates grant signals for the MCU, UBM, and DMA channels at a predetermined fixed frequency. 2.1.3 Adaptive Clock Generator (ACG) The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the codec port interface and the codec device. To synchronize data sent to or received from the codec to the USB frame rate, the MCLKO signal generated by the adaptive clock generator must be used. The synchronization of the MCLKO signal to the USB frame rate is achieved by the ACG, which, in turn, is controlled by a soft PLL, implemented in the MCU. One of the tasks performed by the ACG is to maintain count of the number of MCLKO clocks between USB Start of Frame (SOF) events. This count is monitored by the soft PLL in the MCU. Based on this count, the soft PLL outputs corrections to the ACG to adjust MCLKO to obtain the correct number of MCLKO clocks between USB SOF events. MCLKI, the master clock input, can also be selected to source the clocks used by the codec port interface. When MCLKI is selected, it is used to derive the TAS1020B-sourced versions of the clocks CSCLK and CSYNC. In this scenario, the codec device would also use the same master clock signal (MCLKI). 2.1.4 USB Transceiver The TAS1020B provides an integrated transceiver for the USB port. The transceiver includes a differential output driver, a differential input receiver, and two single ended input buffers. The transceiver connects to the USB DP and DM signal terminals. 2.1.5 USB Serial Interface Engine (SIE) The serial interface engine logic manages the USB packet protocol for packets being received and transmitted by the TAS1020B. For packets being received, the SIE decodes the packet identifier field (PID) to determine the type of packet being received and to ensure the PID is valid. The SIE then calculates the cycle redundancy check (CRC) of the received token and data packets and compares the value to the CRC contained in the packet to verify that the packet was not corrupted during transmission. For transmitted token and data packets, the SIE generates the CRC that is transmitted with the packet. The SIE also generates the synchronization field (SYNC) and the correct PID for all transmitted packets. Another major function of the SIE is the serial-to-parallel conversion of received data packets and the parallel-to-serial conversion of transmitted data packets. 16 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.1.6 USB Buffer Manager (UBM) The USB buffer manager provides the control logic that interfaces the SIE to the USB endpoint buffers. One of the major functions of the UBM is to decode the USB function address to determine if the host PC is addressing the TAS1020B device USB peripheral function. In addition, the endpoint address field and direction signal are decoded to determine which particular USB endpoint is being addressed. Based on the direction of the USB transaction and the endpoint number, the UBM will either write or read the data packet to or from the appropriate USB endpoint data buffer. 2.1.7 USB Frame Timer The USB frame timer logic receives the start of frame (SOF) packet from the host PC each USB frame. Each frame, the logic stores the 11-bit frame number value from the SOF packet in a register and asserts the internal SOF signal. The frame number register can be read by the MCU and the value can be used as a time stamp. For USB frames in which the SOF packet is corrupted or not received, the frame timer logic will generate a pseudo start of frame (PSOF) signal and increment the frame number register. 2.1.8 USB Suspend and Resume Logic The USB suspend and resume logic detects suspend and resume conditions on the USB. This logic also provides the internal signals used to control the TAS1020B device when these conditions occur. The capability to resume operation from a suspend condition with a locally generated remote wake-up event is also provided. 2.1.9 MCU Core The TAS1020B uses an 8-bit microcontroller core that is based on the industry standard 8052. The MCU is software compatible with the 8052, 8032, 80C52, 80C53, and 87C52 MCUs. The 8052 MCU is the processing core of the TAS1020B and handles all USB control, interrupt and bulk endpoint transfers. Bulk out end-point transfers can also be handled by one of the two DMA channels. 2.1.10 MCU Memory In accordance with the industry standard 8052, the TAS1020B MCU memory is organized into program memory, external data memory and internal data memory. A boot ROM program is used to download the application code to a 6K byte RAM that is mapped to the program memory space. The external data memory includes the USB endpoint configuration blocks, USB data buffers, and memory mapped registers. The total external data memory space available is 1.5K bytes. A total of 256 bytes are provided for the internal data memory. 2.1.11 USB Endpoint Configuration Blocks and Buffer Space The USB endpoint configuration blocks are used by the MCU to configure and operate the required USB endpoints for a particular application. In addition to the control end-point, the TAS1020B supports a total of seven IN endpoints and seven OUT endpoints. A set of six bytes is provided for each endpoint to specify the endpoint type, buffer address, buffer size, and data packet byte count. The USB endpoint buffer configuration blocks and buffer space provided totals 1440 bytes. The buffer space to be used by a particular endpoint is fully configurable by the MCU for a particular application. Therefore, the MCU can configure each buffer based on the total number of endpoints to be used, the maximum packet size to be used for each endpoint, and the selection of single or double buffering. 2.1.12 DMA Controller Two DMA channels are provided to support the streaming of data for USB isochronous IN endpoints, Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 17 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com isochronous OUT endpoints, and bulk OUT endpoints. Each DMA channel can support one USB isochronous IN endpoint, or one isochronous OUT endpoint, or one bulk OUT endpoint. The DMA channels are used to stream data between the USB endpoint data buffers and the codec port interface. The USB endpoint number and direction can be programmed for each DMA channel. Also, the codec port interface time slots to be serviced by each DMA channel can be programmed. 2.1.13 Codec Port Interface The TAS1020B provides a configurable full duplex bidirectional serial interface that can be used to connect to a codec or other external device types for streaming USB isochronous data. The interface can be configured to support several different industry standard protocols, including AC '97 1.x, AC '97 2.x, AIC, and I2S. The TAS1020B also has a general-purpose mode to support other protocols. 2.1.14 I2C Interface The I2C interface logic provides a two-wire serial interface that the 8052 MCU can use to access other ICs. The TAS1020B is an I2C master device only and supports single byte or multiple byte read and write operations. The interface can be programmed to operate at either 100 kbps or 400 kbps. In addition, the protocol supports 8-bit or 16-bit addressing for accessing the I2C slave device memory locations. The TAS1020B supports I2C wait states. This means slaves can assert wait state on the I2C bus by pulling the SCL line low. 2.1.15 General-Purpose IO Ports (GPIO) The TAS1020B provides two general-purpose IO ports that are controlled by the internal 8052 MCU. The two ports are port 1 and port 3. Port 1 provides true GPIO capability. Each bit of port 1 can be independently used as either an input or output, and consists of an output buffer, an input buffer, and a pullup resistor(4). Some of the bits of port 3 also provide true GPIO capability, but, in addition, some of the bits of port 3 also provide alternate input and output uses. An example of this is P3.2, which is used as the external interrupt (XINT) input to the TAS1020B. A detailed description of the alternate uses of some of the port 3 bits is presented in Section 2.2.11. The pullup resistors for port 1 and port 3 can be disabled by bits P1PUDIS and P3PUDIS respectively in the on-chip register GLOBCTL. In addition, any port 3 pin can be used to wake up the host PC from a low-power suspend mode. 2.1.16 Interrupt Logic The interrupt logic monitors the various conditions that can cause an interrupt and asserts the interrupt 0 (INTO) input on the 8052 MCU core accordingly. All of the TAS1020B internal interrupt sources and the external interrupt (XINT) input are ORed together to generate the INT0 signal. An interrupt vector register is used by the MCU to identify the interrupt source. 2.1.17 Reset Logic An external master reset (MRESET) input signal that is asynchronous to the internal clocks can be used to reset the TAS1020B logic. In addition to this master reset, the TAS1020B logic can also be reset by a USB reset from the host PC if bit FRSTE in the on-chip register USBCTL is set to 1. The TAS1020B also provides a reset output (RSTO) signal that can be used by external devices. This signal is asserted when either a master reset occurs or when a USB reset occurs and FRSTE is set to 1. (4) The pullup resistors are not implemented as true resistors, but rather as switchable current sources (see Section 2.2.11.3). 18 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2 Device Operation The operation of the TAS1020B is explained in the following sections. For additional information on USB, refer to the Universal Serial Bus Specification, Version 1.1. 2.2.1 Clock Generation The TAS1020B requires an external 6-MHz crystal with load capacitors and PLL loop filter components to derive all the clocks needed for both USB and codec operation. Figure 4-1 shows the connection of these components to the TAS1020B. Figure 4-1 also shows a ground shield residing on the top layer of the PCB and underneath the crystal and its load capacitors and the PLL components. The PLL is an analog PLL, and noise pickup in these components can translate to phase jitter at the output of the PLL, which in turn can translate to distortion at the codec. A ground shield is recommended to attenuate the digital noise components on the board as seen at the PLL. The AVSS and AVDD pins on the TAS1020B are used exclusively to power the analog PLL. To maintain isolation from the digital noise residing on a board, AVSS should be a separate ground plane that connects to the primary ground plane (DGND) at a single point via a ferrite bead. The ferrite bead should exhibit around 9 Ω of impedance at 100 MHz. AVDD should also be distinct from DVDD. A recommended architecture is to generate DVDD and AVDD from the same regulator line, with each derived from a RC filter in series with the regulator output. It is finally recommended that the ground shield for the crystal and its load capacitors and the PLL loop filter components be connected to AVSS at a single point via a ferrite bead of the same type as above. Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internally in the TAS1020B is a major advantage with regard to EMI. 2.2.2 Boot Process The TAS1020B can boot from EEPROM or execute a host boot. Host boot will be used in the following circumstances: • No EEPROM is present. • An EEPROM is present, but does not contain a valid header. • An EEPROM is present, but is a device EEPROM (contains header information only). 2.2.2.1 EEPROM Boot Process If the target device has an application EEPROM (an EEPROM that contains both header and application data), and if the header portion of the EEPROM content is valid, the EEPROM application code is downloaded to on-chip RAM. During the download process, the RAM is mapped to data space, and the boot code that orchestrates the download is part of the on-chip firmware housed in on-chip ROM. Also, while the application code is being downloaded, the TAS1020B remains disconnected from the USB bus. When the download is complete, the firmware sets the ROM disable bit SDW. The setting of this bit maps the RAM from data space to program space, starting address 0x0000. Having set bit SDW, the firmware then branches to address 0x0000, which is the reset entry point for the application code. The application code is now running. The application code then switches on the PUR output. The PUR output pin is connected, through external circuitry (see Figure 4-1), to the positive (DP) line of the differential USB bus. Switching PUR on informs the host that a full speed (12 Mb/s) device is present on the bus. In the enumeration procedure that follows, the application code reports its run-time device descriptor set. Following enumeration, the device is actively running its application. 2.2.2.2 Host Boot Process The DFU code in the TAS1020B fully adheres to the USB Device Class Specification for DFU 1.0. In addition, the TAS1020B utilizes the communication protocols from the DFU specification to implement a host boot capability for those applications that do not have an EEPROM resource. In such cases, the Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 19 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com TAS1020B, at power-up, reports its DFU mode descriptor set rather than its run-time descriptor set and directly enters what the DFU specification terms the DFU Program Mode. The host processor must be cognizant of the fact that the device under enumeration does not have an EEPROM resource with valid code, and is already in the DFU mode awaiting a download per the DFU protocol. All of this capability is provided by the ROM-based code (firmware) that resides on the TAS1020B. Specifically, the host boot process addresses three cases—an EPROM is not present, an EEPROM is present but the data in the EEPROM is invalid, or an EEPROM is present but the EEPROM is a device EEPROM (contains only header data). In all three of these cases, the TAS1020B firmware comes up in the DFU Program Mode. A host boot ensues, but the final destination of the download depends on the status of the onboard EEPROM. a. If the firmware determines that no EEPROM is present (by noting, when addressing the EEPROM, the absence of an acknowledge from the EEPROM), a Vendor ID of 0xFFFF and a Product ID of 0xFFFE is reported during enumeration. The download that follows enumeration is written to the on-chip RAM. The download from the host must include a header (see Section 2.2.2.3.1), and the header overwrite bit in the header downloaded must be set to 0. (The header overwrite bit is used to instruct the TAS1020B firmware as to whether or not the header portion of the download is to be written into the EEPROM. Since, in this case, no EEPROM is present, this header overwrite bit must be set to 0). It is noted that the host must have prior knowledge that the target will initialize in the DFU program mode and will require a download of application code (and header) to RAM. b. If the firmware determines that an EEPROM is present (acknowledges are received from the EEPROM), but that the header data in the EEPROM is invalid, a Vendor ID of 0xFFFF and a Product ID of 0xFFFE is reported during enumeration. The download that follows enumeration is written to EEPROM. Since the EEPROM data was invalid, the host has to set the header overwrite bit in the header portion of the download to a 1 to ensure that the header is written to the EEPROM. It is noted that the host must have prior knowledge that the target does have an EEPROM, but that the data in the EEPROM is invalid. This could be a situation such as the initial download of the application on a production line. c. If the firmware determines that an EEPROM is present, that the header data in the EEPROM is valid, but that the header data in the EEPROM indicates that the EEPROM is a device EEPROM, the Vendor ID and Product ID settings in the EEPROM-resident header is reported during enumeration. In addition, the strings in the header, if applicable, are reported. The EEPROM download that follows enumeration will be written to the on-chip RAM facility. In addition to downloading the application code to RAM, an option also exists to download the header portion of the download image to the EEPROM. If the host does not wish to overwrite the valid header data in the EEPROM, it must set the header overwrite bit in its download header to a 0. It is noted that the host must have knowledge that the target contains an EEPROM, and that the EEPROM is a device EEPROM. 2.2.2.3 EEPROM Data Organization Two types of data can be stored in the EEPROM—header data, which contains USB device information, and application code. During boot, if no header or invalid header data is found in the EEPROM, paragraph (b) in Section 2.2.2.2 applies. During boot, if a valid header is found in the EEPROM, and the header indicates that the Data Type is an Application, then the application is loaded from the EEPROM and execution is passed to it. During boot, if a valid header is found in the EEPROM, and the header indicates that the Data Type is a Device, then paragraph (c) in Section 2.2.2.2 applies. 2.2.2.3.1 EEPROM Header Table 2-1 shows the format and information contained it the header data. As seen from Table 2-1, the header data begins at address 0x0000 in the EEPROM and precedes the application code. 20 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Table 2-1. EEPROM Header OFFSET TYPE SIZE VALUE 0 headerChksum 1 Header check sum—derived by adding the header data, excluding the header checksum, in bytes, and retaining the lower byte of the sum as the checksum. 1 HeaderSize 1 Size, in units of bytes, of the header including strings if applied 2 Signature 2 Signature: 0x1234 4 VendorID 2 USB Vendor ID 6 ProductID 2 USB Product ID 8 ProductVersion 1 Product version 9 FirmwareVersion 1 Firmware version USB attributes: Bit 0: If set to 1, the header includes all three strings: language, manufacture, and product strings, if set to 0, the header does not include any string. The strings, if present, must 10 UsbAttributes 1 conform to the USB string format per USB spec 1.0 or later. Bit 1 : Not used. Bit 2: If set to 1, the device can be self powered, if set to 0, cannot be self powered. Bit 3: If set to 1, the device can be bus powered, if set to 0, cannot be bus powered. Bits 4 through 7: Reserved 11 MaxPower 1 Maximum power the device needs in units of 2 mA. Device attributes: Bit 0: If set to 1, the CPU clock is 24 MHz, if set to 0, the CPU clock is 12 MHz. Bit 1: If set to 1, the download version of the header will be written into the EEPROM (download target has to be EEPROM). If the header is not to be overwritten, or if the target is 12 Attributes 1 RAM, this bit must be cleared to 0. Bit 2: Not used. Bit 3: If set to 1, the EEPROM can support a 400 kHz I2C bus, if set to 0, the EEPROM cannot support a 400-kHz I2C bus. Bits 4 through 7: Reserved 13 WPageSize 1 Maximum I2C write page size, in units of bytes This value defines if the device is an application EEPROM or a device EEPROM.0x01: 14 DataType 1 Application EEPROM—contains header and application code.0x02: Device EEPROM—contains only header. All other values are invalid. 15 RpageSize 1 Maximum I2C read page size, in units of bytes. If the value is zero, the whole payLoadSize is read in one I2C read setup. 16 payLoadSize 2 Size, in units of bytes, of the application, if using EEPROM as an application EEPROM, otherwise the value is 0. Language string in standard USB string format if applied. If this attribute is applied, the two xxxx Language string 4 attributes that follow must also be applied. If this attribute is not applied, the following two attributes cannot be applied. xxxx Manufacture ... Manufacture string in standard USB string format if applied. string xxxx Product string ... Product string in standard USB string format if applied. xxxx Application Code ... Application code if applied The header checksum is used by the firmware to detect the presence of a valid header in the EEPROM. The header size field supports future updates of the header. 2.2.2.3.2 Application Code Application code is stored as a binary image in the EEPROM following the header information. The binary image must always be mapped to MCU program space starting at address 0x0000, and must be stored in the EEPROM as a continuous linear block of data. 2.2.2.4 I2C Serial EEPROM The TAS1020B accesses the EEPROM via an I2C serial bus. Thus the EEPROM must be an I2C serial EEPROM. The ROM boot loader assumes the EEPROM device uses the full 7-bit I2C device address with the upper four bits of the address (control code) set to 1010 and the three least significant bits (chip select bits) set to 000. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 21 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2.2.2.5 DFU Upgrade Process DFU compliance provides a host the capability of upgrading application code currently residing in a target's onboard EEPROM memory. The DFU upgrade process provided by the TAS1020B fully conforms to the requirements specified in USB Device Class Specification For DFU 1.0. The download must consist of both header and application code. The destination of the download must be defined by the on-chip application code (as opposed to the application code being downloaded). Under normal circumstances, the download destination would be EEPROM, but it is possible for the application code to specify on-chip RAM as the download destination. If the download destination is to be EEPROM, bit 1 of the Attribute field in the header data being downloaded determines whether or not the header data in the download image is to be written to the EEPROM. A bit value of 1 results in the header in the EEPROM being overwritten by the header content in the download image. It is important to note that if the application code targets RAM as the download destination, bit 1 in the Attribute field of the download image must be 0. 2.2.2.6 Download Error Recovery Safeguards are incorporated on the TAS1020B ROM to allow recovery from a host download that does not complete due to a loss of power. Before downloading the application code, the TAS1020B saves the value of the Data Type field in the EEPROM header and modifies the Data Type field to indicate that a download is in progress (0x03: Updating). After successful completion of the download, the TAS1020B restores the saved value in the Data Type field. If the download is terminated prior to successful completion, the Data Type field still indicates that a download is in progress. In the case of an unsuccessful download the TAS1020B reboots as a DFU device in DFU Program mode and uses the Vendor and Product ID from the EEPROM header as the vendor and product ID in its USB device descriptor. The download process consists of the following task flow. 1. Header portion of download is written to EEPROM, if applicable. 2. Header Data Type is retrieved and stored in RAM. 3. Header Data Type is overwritten with a value indicating that a download is in progress. 4. Application portion of download is written to EEPROM (or to RAM). 5. Header Data Type is overwritten with the previously recorded legal value. If the download should terminate during the downloading of the header to EEPROM, the header checksum results in the EEPROM being declared invalid on the next boot of the TAS1020B. If the download should terminate during the downloading of the application code, the Data Type field indicates that a download was in progress and the TAS1020B enters the DFU program mode on the next boot. If the TAS1020B remains powered when a premature termination of a download occurs, the TAS1020B remains in the DFU program mode. In this case, the host can again attempt a download; the TAS1020B does not have to be rebooted. 2.2.2.7 ROM Support Functions To conserve RAM memory resources on the TAS1020B, several USB-specific routines have been included in the firmware resident in the on-chip ROM. The inclusion of these routines frees the application code from having to implement USB-specific code. The tasks provided by the ROM code include: • A USB engine for handling USB control endpoint data transactions and states • USB protocol handlers to support USB Chapter 9 • USB protocol handlers to support USB HID Class • USB protocol handlers to support USB DFU Class 22 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 • USB protocol handlers to support the common features of USB Audio Class commands – Feature Unit: • Set/get volume control • Set/get mute control • Set/get bass control • Set/get treble control – Mixer unit: set/get input/output gain control – End point: set/get the audio streaming endpoint sampling frequency – For unsupported case, the ROM code passes the requests to the application code for processing (). See also Section 5. 2.2.3 USB Enumeration USB enumeration is accomplished by interaction between the host PC and the TAS1020B. As described in Section 2.2.2, the TAS1020B can identify itself as an application device by reporting its application Vendor ID and Product ID, or it can identify itself as a DFU device by reporting a Vendor ID of 0xFFFF and a Product ID of 0xFFFE. If the TAS1020B fails to detect the presence of an EEPROM, or if an EEPROM is present but does not contain a valid header, the Vendor ID of 0xFFFF and Product ID of 0xFFFE are reported. If an EEPROM is present, but contains only valid header data, the Vendor ID and Product ID settings in the EEPROM header are reported, but the TAS1020B firmware comes up as a DFU device in the DFU program mode. If an EEPROM is present, and contains both a valid header and application code, the TAS1020B comes up as an application specific device. For all cases where the TAS1020B comes up in the DFU program mode, once application code has been downloaded, the TAS1020B is reset by a host-issued USB reset. After this reset, the TAS1020B comes up as an application device. When the TAS1020B comes up as an application device, the ROM-resident boot loader retrieves the application code from the EEPROM, if the EEPROM is not a device EEPROM, and then runs the application code. It is the application code that connects the TAS1020B to the USB. During the enumeration that follows connection to the USB, the application code identifies the device as an application specific device and the host loads the appropriate host driver(s). The boot loader and application code both use the CONT, SDW and FRSTE bits to control the enumeration process. • The function connect (CONT) bit is set to a 1 by the MCU to connect the TAS1020B device to the USB. When this bit is set to a 1, the USB DP line pullup resistor (PUR) output signal is enabled. Enabling PUR pulls DP high via external circuitry (see Figure 4-1). (When the TAS1020B powers up, this bit is cleared to a 0 and the PUR output is in the high-impedance state.) This bit is not affected by subsequent USB resets. • The shadow the boot ROM (SDW) bit is set to 1 by the MCU to switch the MCU memory configuration from boot loader mode to normal operating mode. Once set to 1, this bit is not affected by subsequent USB resets. • The function reset enable (FRSTE) bit is set to a 1 by the MCU to enable the USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits are not reset. In addition, when the FRSTE bit is set, the reset output (RSTO) signal from the TAS1020B device is active whenever a USB reset occurs. This bit, once set, is not affected by subsequent USB resets. 2.2.4 TAS1020B USB Reset Logic There are two mechanisms provided by the TAS1020B—an external reset MRESET and a USB reset. The reset logic used in the TAS1020B is presented in Figure 2-2. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 23 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com MRESET is a global reset that results in all the TAS1020B logic and the 8052 MCU core being reset. This input to the TAS1020B is typically used to implement a power-on reset at the application of power, but it can also be used with reset pushbutton switches and external circuits to implement global resets at any time. MRESET is an asynchronous reset that must be active for a minimum time period of one microsecond. The TAS1020B can also detect a USB reset condition. When this reset occurs, the TAS1020B responds by setting the function reset (RSTR) bit in the USB status register (USBSTA). However, the extent to which the internal logic is reset depends on the setting of the function reset enable bit (FRSTE) in the USB control register (USBCTL). If the MCU has set FRSTE to 1, incoming USB resets are treated as global resets, with all TAS1020B logic and the 8052 MCU core being reset. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits are not reset. Also, if the USB reset results in a global reset being issued, an interrupt to the 8052 MCU is not generated. But if the MCU has cleared FRSTE, incoming USB resets is treated as interrupts to the MCU (via INT0) if the corresponding function reset bit RSTR in the USB interrupt mask register USBMSK has been set by the MCU. If neither FRSTE or RSTR has been set by the MCU, USB resets have no effect on the TAS1020B, other than resetting the USB serial interface engine (SIE) and the USB buffer manager (UBM) in the TAS1020B. Regardless of the status of FRSTE and bit RSTR in the USB interrupt mask register USBMSK, the function reset bit RSTR in the USB status register USBSTA is always set whenever a USB reset condition is detected. If the USB reset results in the generation of a global reset, the global reset clears the function reset bit RSTR in USBSTA. If, instead, the USB reset results in an interrupt being generated, RSTR in register USBSTA is cleared when the MCU writes to the interrupt vector register VECINT while in the USB reset interrupt service routine (VECINT = 0x17). The TAS1020B has two reset outputs—RSTO and CRESET. RSTO is activated every time MRESET is active, and every time a USB reset occurs and bit FRSTE in the USB control register USBCTL is set. CRESET is typically used as a codec reset. Although labeled a reset line, it has no direct relationship to MRESET or detected USB resets. Instead, it is activated and deactivated when the on-chip 8052 MCU core writes a 0 and a 1, respectively, to the CRST bit in the codec port interface control and status register CPTCTL. 2.2.5 USB Suspend and Resume Modes The TAS1020B can recognize a suspend state. Figure 2-2 shows the logical implementation of the suspend and resume modes in the TAS1020B. The TAS1020B enters a suspend mode if a constant idle state (j state) is observed on the USB bus for a period of 5 ms. USB compliance also requires that a device enter a suspend state, drawing only suspend current from the bus, after no more than 10 ms of bus inactivity, The TAS1020B supports this requirement by creating a suspend interrupt to the on-chip MCU after a suspend condition has been present for 5 ms. Upon receiving this interrupt, the MCU firmware can then take the steps necessary to assure that the device enters a suspend state within the next 5 ms. There are two ways for the TAS1020B device to exit the suspend mode: 1) detection of USB resume signaling and 2) proactively performing a local remote wake-up event. 2.2.5.1 USB Suspend Mode When a suspend condition is detected on the USB, the suspend/resume logic sets the function suspend request bit (SUSR) in the USB status register, resulting in the generation of the function suspend request interrupt SUSR. To enter the low-power suspend state and disable all TAS1020B device clocks, the MCU firmware, upon receiving the SUSR interrupt, must set the idle mode bit (IDL), which is bit 0 in the MCU power control (PCON) register. Setting the IDL bit results in the TAS1020B suspending all internal clocks, including the clocks to the MCU. The MCU thus suspends instruction execution while in the idle mode. The MCU must not set the IDL bit while in the SUSR interrupt service routine (ISR), or while in any other ISR. As described in Section 2.2.5.3, it is intended that the receipt of an INT0 interrupt at the MCU result in exiting the suspend state. But if the MCU has suspended instruction execution while in an ISR, 24 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 subsequent INT0 activity is not recognized, as the MCU is still servicing an interrupt. For this reason then, it is necessary that IDL not be set while processing an ISR. (As described in Section 2.2.5.3, an external wake-up event will resume clocks within the TAS1020B. But even if the clocks to the MCU resume, if the MCU does not recognize INT0, the IDL bit remains set and thus the MCU core itself remains in the suspend state). The SUSR bit is cleared while in the SUSR ISR by writing to the interrupt vector register VECINT. While servicing the SUSR ISR, the VECINT output is 0x16 - the USB function suspend interrupt vector. As shown in Figure 2-2, the occurrence of a write to VECINT, while the USB function suspend interrupt vector is being output, results in clearing bit SUSR of the USB status register. (The data written to VECINT is of no consequence; the clearing action takes place upon decoding the write transaction to VECINT). 2.2.5.2 USB Resume Mode When the TAS1020B is in a suspend state, any non-idle signaling on the USB is detected by the suspend/resume logic and device operation resumes. When the resume signal is detected, the TAS1020B clocks are enabled and the function resume request bit (RESR) is set, resulting in the generation of the function resume request interrupt. The function resume request interrupt to the MCU automatically clears the idle mode bit IDL in the PCON register, and as a result the MCU exits the suspend state and becomes fully functional, with all internal clocks active. After the RETI from the ISR, the next instruction to be executed is the one following the instruction that set the IDL bit. The RESR bit is cleared while in the RESR ISR by writing to the interrupt vector register VECINT. 2.2.5.3 USB Remote Wake-Up Mode The TAS1020B device has the capability to remotely wake up the USB by generating resume signaling upstream, providing the host has granted permission to generate remote wake-ups via a SET_FEATURE DEVICE_REMOTE_WAKEUP control transaction. If remote wakeup capability has been granted, the MCU firmware, upon awakening from a suspend state, has to activate the remote wake-up request bit RWUP in the USB control register USBCTL. Activation of RWUP consists of the MCU firmware writing a 1 followed by a 0 to RWUP. This action creates a pulse, which results in the TAS1020B generating resume signaling upstream by driving a k state (non-idle) onto the USB bus. The USB specification requires that remote wake-up resume signaling not be generated until the suspend state has been active for at least 5 ms. In addition, the specification requires that the remote wake-up resume signaling be generated for at least 1ms but for no more than 15 ms. The 5 ms requirement is met by not entering the suspend mode until an idle state, or j state, is detected, uninterrupted, for 5 ms. The RWUP pulse results in driving a k state onto the USB bus for 1 to 2 ms, and thus the 15 ms requirement is also met. Moreover, if an application wishes to extend the duration of the k state on the USB bus, it need only extend the pulse width of RWUP. The resulting duration of the resume signaling is the duration of the RWUP pulse plus 1 to 2 ms. The condition that activates a remote wake-up is a transition from 1 to 0 on one of the P3 port bits whose corresponding mask bit has been set to zero. (When in the suspend mode, the XINT input is treated as port bit P3.2). As seen in Figure 2-2, the P3 mask register bits are gated with the P3 port input lines from the I/O port cells. The gated P3 port bits are then all ORed together and the output is ANDed with the suspend signal. The output of this logic drives the clock input of a flip-flop, and when the output of this logic transitions from 0 to 1, the flip-flop is set to 1. The setting of this flip-flop to 1 results in the TAS1020B exiting the suspend state and resuming all clocks, including those to the MCU core. The output of this flip-flop is also gated with bit XINTEN in the global control register GLOBCTL, and the output of this gate drives the INT0 interrupt logic. This means that a remote wake-up generates an INT0 interrupt to the MCU only if bit XINTEN has been set. Therefore, before entering a suspend state, the firmware must set XINTEN if remote wake-up capability is to be enabled. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 25 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com The wake-up interrupt is seen by the firmware as an XINT interrupt; that is, the interrupt vector register VECINT has an output value of 0x1F. If the XINT pin is to be used as an event marker during normal operation, and if one of the P3 port bits is to be used for a wake-up interrupt, the firmware must be able to distinguish between a wake-up interrupt and a normal XINT interrupt. One technique would be to examine the state of the IDL bit in the MCU power control register. If this bit is set, the interrupt event is a wake-up interrupt; otherwise, the interrupt is a normal XINT interrupt. If an XINT event should occur during a suspend mode, the event is ignored if the mask bit for P3.2 is set. (During a suspend mode the TAS1020B clocks are disabled, and thus an incoming XINT interrupt event does not propagate through the synchronization logic and activate the MCU INT0 input). 2.2.6 Adaptive Clock Generator (ACG) The adaptive clock generator is used to generate two programmable master clock output signals (MCLKO and MCLKO2) that can be used by the codec port interface and the codec device. Two separate and programmable frequency synthesizers provide the two master clocks. This allows the TAS1020B to support different record and playback rates for those devices that require separate master clocks to implement different rates. For isochronous transactions, the ACG can also support USB asynchronous, synchronous, and adaptive modes of operation. The ACG keeps count of the number of master clock events between USB SOF time marks, and the DCNTX/Y field of the endpoint register IEPDCNTX/Y keeps track of the number of samples received between USB SOF time marks. Synchronous isochronous operation can be accomplished by adjusting one of the two frequency synthesizers until the correct number of master clock events is obtained between USB SOF time marks. Similarly, monitoring the number of samples received between USB SOF events can accommodate adaptive isochronous operation. Here the frequency synthesizer is adjusted to obtain the proper codec output rate for the number of samples received. The TAS1020B can also accommodate asynchronous isochronous operation, and the input MCLKI is provided for this case. For asynchronous isochronous operation, the external clock pin MCLKI is used to derive the data and sync signal to the codec. However, the external clock that provides the input to pin MCLKI, instead of the master clock output (MCLKO or MCLKO2) from the ACG, must also source the codec's MCLK. A block diagram of the adaptive clock generator is shown in Figure 2-1. Each frequency synthesizer circuit generates a programmable clock with a frequency range of 12-25 MHz, and each frequency synthesizer output feeds a divide-by-M-circuit, which can be programmed to divide by 1 to 16. As a result, the frequency range of each master clock is 750 kHz to 25 MHz. Also, the duty cycle of each master clock is 50% for all programmable frequencies (after a possible short, or "runt", initial cycle). As indicated in Figure 2-1, multiplexers precede the master clocks MCLKO and MCLKO2. These multiplexers provide the option of using the output of either frequency synthesizer (after division by the divide-by-M circuit) or the MCLKI input (after division by the divide-by-I circuit) to source each master clock. Each master clock is also assigned its own divide circuit to generate its associated CSCLK. The C-port serial clock (CSCLK) is derived by setting the divide by B value in codec port interface configuration register CPTNCF4 [2:0] and the C-port serial clock 2 (CSCLK2) is derived by setting the divide by B2 value in codec port receive interface configuration register 4 CPTRXCNF4 [2:0]. In addition, although not shown in Figure 2-1, each master clock is assigned its own CSYNC generator, with the length and polarity of each CSYNC separately programmable. 26 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B 6 MHz PLL Frequency Synthesizer Oscillator MCLK0 Divide by M1 1 Frequency Synthesizer Divide by M2 2 Divide by I 4 4 3 ACG1DCTL[7:4] ACG2DCTL[7:4] ACG1DCTL[2:0] ACGCTL[4] ACGCTL[1] ACGCTL[3] ACGCTL[0] 16-Bit Counter ACGCTL[6] ACGCTL[7] MCLK02 ACGCAPH ACGCAPL SOF PSOF MCLKI Divide by B CPTCNF4 [2:0] CSCLK Divide by B2 CPTRXCNF4 [2:0] CSCLK2 TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 2-1. Adaptive Clock Generator Block Diagram The ACG is controlled by the registers shown in Table 2-2. See Section 6.5.3 for details. Table 2-2. AGC Control Registers FUNCTIONAL REGISTER ACTUAL BYTE-WIDE REGISTERS 24-bit frequency register #1 ACG1FRQ2 ACG1FRQ1 ACG1FRQ0 16-bit capture register ACGCAPH ACGCAPL 8-bit synthesizer 1 divider control register ACG1DCTL 8-bit ACG control register ACGCTL 24-bit frequency register #2 ACG2FRQ2 ACG2FRQ1 ACG2FRQ0 8-bit synthesizer 2 divider control register ACG2DCTL The main functional modules of the ACG are described in the following sections. 2.2.6.1 Programmable Frequency Synthesizer The 24-bit ACG frequency register value is used to program the frequency synthesizer, and the value of the frequency register can be updated by the MCU while the ACG is running. The high resolution of each frequency value programmed allows the firmware to adjust the frequency value by +LSB or more to lock onto the USB start-of-frame (SOF) signal and achieve a synchronous mode of operation, a necessity for streaming audio applications. The 24-bit frequency register value is updated and used by the frequency synthesizer only when MCU writes to the ACGFRQ0 register. The proper way to update a frequency value then is to write the least significant byte (ACGFRQ0) last. The frequency resolution of the output master clock depends on the actual frequency being output. In general, the frequency resolution decreases with increasing output frequencies. The clock frequency of the MCLKO output signal is calculated by using the formula: For N ≥ 24 and N < 50, Frequency Synthesizer output frequency = 600/N MHz For N = 50, frequency = 12 MHz Where N is the value in the 24-bit frequency register (ACGFRQ). The value of N can range from 24 to 50. The six most significant bits of the 24-bit frequency register are used to represent the integer portion of N, and the remaining 18 bits of the frequency register are used to represent the fractional portion of N. An example is shown below. Alternatively, with ACGnFRQ considered to be a 24-bit unsigned value: ACGnFRQ = [600 000 000 / output (Hz)] × 218 Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 27 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Where output (Hz) is the output of Frequency Synthesizer n. Example Frequency Register Calculation Suppose the desired MCLKO frequency is 24.576 MHz. Using the above formula, N = 24.4140625 decimal. To determine the binary value to be written to the ACGFRQ register, separately convert the integer value (24) to 6-bit binary and the fractional value (4140625) to 18-bit binary. As a result, the 24-bit binary value is 011000.011010100000000000. The corresponding values to program into the ACGFRQ registers are: ACGFRQ2 = 01100001b = 61h ACGFRQ1 = 10101000b = A8h ACGFRQ0 = 00000000b = 00h Keep in mind that writing to register ACGFRQ0 loads the frequency synthesizer with the new 24-bit value in registers ACGFRQ2, ACGFRQ1, and ACGFRQ0. Example Frequency Resolution Calculation To illustrate the frequency resolution capabilities of the ACG, the next possible higher and lower frequencies for MCLKO can be calculated. To get the next possible higher frequency of MCLKO (24.57600384 MHz), decrease the value of N by 1 LSB. Thus, N = 011000.01 – 10100111 –11111111 binary. To get the next possible lower frequency of MCLKO (24.57599600 MHz), increase the value of N by 1 LSB. Thus, N = 011000.01 – 10101000 – 00000001 binary. For this example with a nominal MCLKO frequency of 24.576 MHz, the frequency resolution is approximately 4 Hz. Table 2-3 lists typically used frequencies and the corresponding ACG frequency register values. Table 2-3. ACG Frequency Registers SYNTHESIZED CLOCK ACG1FRQ2/ ACG1FRQ1/ ACG1FRQ0/ OUTPUT ACG2FRQ2 ACG2FRQ1 ACG2FRQ0 25 MHz 0x60 0 0 24.576 MHz 0x61 0×A8 0x0F 22.579 MHz 0x6A 0x4B 0x20 18.432 MHz 0x82 0x35 0x55 16.934 MHz 0x8D 0xBA 0x09 16.384 MHz 0x92 0x7C 0x00 12.288 MHz 0xC3 0x50 0x00 12 MHz 0xC8 0 0 2.2.6.2 Capture Counter and Register The capture counter and register circuit consists of a 16-bit free running counter which runs at the capture clock frequency. The capture clock source can be selected by programming bits MCLK01S0 and MCLK01S1 in the ACGCTL register. The options are the divided output of frequency synthesizer no. 1, the divided output of frequency synthesizer no. 2, or the divided input clock MCLKI. At each USB start-of-frame (SOF) event or pseudo-start-of-frame (PSOF) event, the capture counter value is stored into the 16-bit capture register. This value is valid until the next SOF or PSOF signal occurs (~1 ms). The MCU 28 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 can read the 16-bit capture register value by reading the ACGCAPH and ACGCAPL registers. Because the counter is a free running counter, and because the count range of the counter extends over several frames before rolling over and beginning the count anew, the capture count values obtained are correlated over several SOF cycles. This attribute is useful should a case ever arise when the MCU fails to read the capture counter after a SOF event, and thus skips an SOF cycle. As shown in Figure 2-1, there is only one capture counter and register, and its capture clock frequency is always the clock selection for MCLKO. This means that MCLKO2 cannot be synchronized to the incoming USB data stream. However, MCLKO2 is intended to support record capability for those cases where record and playback are conducted at different master clock frequencies. Synchronization to the USB bus for record is handled by the handshaking protocol established between the assigned DMA channel and the USB buffer manager (UBM) (see Section 2.2.7.4.1, heading Circular Buffer Operation for Isochronous IN Transactions for more detail). Thus it is not necessary that MCLKO2 itself be synchronized to the USB bus. 2.2.7 USB Transfers The TAS1020B device supports all USB data transfer types: control, bulk, interrupt, and isochronous. In accordance with the USB specification, endpoint zero is reserved for the control endpoint and is bidirectional. In addition to the control endpoint, the TAS1020B is capable of supporting up to 7 IN endpoints and 7 OUT endpoints. These additional endpoints can be configured as bulk, interrupt, or isochronous endpoints. 2.2.7.1 Control Transfers Control transfers are used for configuration, command, and status communication between the host PC and the TAS1020B device. Control transfers to the TAS1020B device use IN endpoint 0 and OUT endpoint 0. The three types of control transfers are control write, control write with no data stage, and control reads. 2.2.7.1.1 Control Write Transfer (Out Transfer) The host PC uses a control write transfer to write data to the USB function. A control write transfer always consists of a setup stage transaction and an IN status stage, and can optionally contain one or more data stage transactions between the setup and status transactions. If the data to be transferred can be contained in the two byte value field of the setup transaction data packet, no data stage transaction is required. If the control information requires the transfer of more than two bytes of data, a control write transfer with data stage transactions will be required. The steps followed for a control write transfer are: Initialization Stage 1. MCU initializes IN endpoint 0 and OUT endpoint 0 by programming the appropriate USB endpoint configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the NACK bit for both IN endpoint 0 and OUT endpoint 0. Setup Stage Transaction 1. The host PC sends a setup token followed by the setup data packet addressed to OUT endpoint 0. If the data is received without an error, the USB Buffer Manager (UBM) writes the data to the setup data packet buffer, sets the setup stage transaction (SETUP) bit to a 1 in the USB status register, returns an ACK handshake to the host PC, and asserts the setup stage transaction interrupt. Note that as long as the setup stage transaction (SETUP) bit is set to a 1, the UBM returns a NACK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values. 2. The MCU services the interrupt, reads the setup data packet from the buffer, and decodes the command. If the command is not supported or valid, the MCU should set the STALL bit in the OUT endpoint 0 configuration byte and the IN endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This causes the device to return a STALL handshake for any data stage or status stage transactions. If the command decoded is supported, the MCU clears the interrupt, which Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 29 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com automatically clears the setup stage transaction bit. The MCU also sets the TOGGLE bit in the OUT endpoint 0 configuration byte to a 1. For control write transfers, the PID used by the host for the first OUT data packet is a DATA1 PID and the TOGGLE bit must match. Optional Data Stage Transaction 1. The host PC sends an out token packet followed by a data packet addressed to OUT endpoint 0. If the data packet is received without errors the UBM writes the data to the endpoint buffer, updates the data count value, toggles the TOGGLE bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 2. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU first must obtain the data count value. After reading the data packet, the MCU must clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host PC. 3. If the NACK bit is set to 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the in token packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then no handshake is returned to the host PC. Status Stage Transaction 1. For IN endpoint 0, the MCU clears the data count value to zero, sets the TOGGLE bit to 1, and clears the NACK bit to 0 to enable the data packet to be sent to the host PC. Note that for a status stage transaction a null data packet with a DATA1 PID is sent to the host PC. 2. The host PC sends an IN token packet addressed to IN endpoint 0. After receiving the IN token, the UBM transmits the null data packet to the host PC. If the data packet is received without errors by the host PC, an ACK handshake is returned. Upon receiving the ACK handshake, the UBM toggles the TOGGLE bit, sets the NACK bit to 1, and asserts the endpoint interrupt. 3. If the NACK bit is set to 1 when the IN token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC then the UBM prepares to retransmit the same data packet again. 2.2.7.1.2 Control Read Transfer (In Transfer) The host PC uses a control read transfer to read data from the USB function. A control read transfer consists of a setup stage transaction, at least one in data stage transaction, and an out status stage transaction. The steps followed for a control read transfer are: Initialization Stage 1. MCU initializes IN endpoint 0 and OUT endpoint 0 by programming the appropriate USB endpoint configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the NACK bit for both IN endpoint 0 and OUT endpoint 0. Setup Stage Transaction 1. The host PC sends a setup token followed by the setup data packet addressed to OUT endpoint 0. If the data is received without an error, the UBM writes the data to the setup data packet buffer, sets the setup stage transaction (SETUP) bit to a 1 in the USB status register, returns an ACK handshake to the host PC, and asserts the setup stage transaction interrupt. Note that as long as the setup stage transaction (SETUP) bit is set to a 1, the UBM returns a NACK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values. 2. The MCU services the interrupt, reads the setup data packet from the buffer, and decodes the command. If the command is not supported or is not valid, the MCU sets the STALL bit in the OUT endpoint 0 configuration byte and the IN endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This causes the device to return a STALL handshake for any data stage or 30 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 status stage transactions. If the command decoded is valid and is supported, the MCU clears the interrupt, which automatically clears the setup stage transaction bit. The MCU also sets the TOGGLE bit in the IN endpoint 0 configuration byte to a 1. For control read transfers, the PID used by the host for the first IN data packet is a DATA1 PID. Data Stage Transaction 1. The data packet to be sent to the host PC is written to the IN endpoint 0 buffer by the MCU. The MCU also updates the data count value then clears the IN endpoint 0 NACK bit to a 0 to enable the data packet to be sent to the host PC. 2. The host PC sends an IN token packet addressed to IN endpoint 0. After receiving the IN token, the UBM transmits the data packet to the host PC. If the data packet is received without an error by the host PC, then an ACK handshake is returned. The UBM then toggles the TOGGLE bit, sets the NACK bit to 1, and asserts the endpoint interrupt. 3. The MCU services the interrupt and prepares to send the next data packet to the host PC. 4. If the NACK bit is set to 1 when the IN token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet again. 5. MCU continues to send data packets until all data has been sent to the host PC. Status Stage Transaction 1. For OUT endpoint 0, the MCU sets the TOGGLE bit to 1, then clears the NACK bit to a 0 to enable a data packet to be sent by the host PC. Note that for a status stage transaction a null data packet with the DATA1 PID is sent by the host PC. 2. The host PC sends an OUT token packet and the null data packet to OUT endpoint 0. If the data packet is received without an error the UBM updates the data count value, toggles to the TOGGLE bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 3. The MCU services the interrupt. If the status transaction completed successfully, then the MCU clears the interrupt and clears the NACK bit. 4. If the NACK bit is set to 1 when the OUT token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the OUT token packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, no handshake is returned to the host PC. 2.2.7.2 Interrupt Transfers The TAS1020B supports interrupt data transfers both to and from the host PC. Devices that need to send or receive a small amount of data with a specified service period should use the interrupt transfer type. IN endpoints 1 through 7 and OUT endpoints 1 through 7 can all be configured as interrupt endpoints. 2.2.7.2.1 Interrupt Out Transaction The steps followed for an interrupt out transaction are: 1. MCU initializes one of the OUT endpoints as an out interrupt endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit. 2. The host PC sends an OUT token packet followed by a data packet addressed to the OUT endpoint. If the data is received without an error then the UBM writes the data to the endpoint buffer, updates the data count value, toggles the toggle bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU must first obtain the data count value. After reading the data packet, the MCU clears the Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 31 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com interrupt and clears the NACK bit to allow the reception of the next data packet from the host PC. 4. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NACK handshake to the host PC. If the STALL bit is set to 1 when the data packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, no handshake is returned to the host PC. NOTE In double buffer mode for interrupt out transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM writes the data packet to the X buffer. If the toggle bit is a 1, the UBM writes the data packet to the Y buffer. When a data packet is received, the MCU determines which buffer contains the data packet by reading the toggle bit. However, when using double buffer mode, the possibility exists for data packets to be received and written to both the X and Y buffer before the MCU responds to the endpoint interrupt. In this case, simply use the toggle bit to determine which buffer contains the data packet does not work. Hence, in double buffer mode, the MCU reads the X buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the buffers. 2.2.7.2.2 Interrupt In Transaction The steps followed for an interrupt in transaction are: 1. MCU initializes one of the IN endpoints as an in interrupt endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and setting the NACK bit. 2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates the data count value and clears the NACK bit to 0 to enable the data packet to be sent to the host PC. 3. The host PC sends an IN token packet addressed to the IN endpoint. After receiving the IN token, the UBM transmits the data packet to the host PC. If the data packet is received without errors by the host PC, an ACK handshake is returned. The UBM then toggles the toggle bit, sets the NACK bit to a 1, and asserts the endpoint interrupt. 4. The MCU services the interrupt and prepares to send the next data packet to the host PC. 5. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NACK handshake to the host PC. If the STALL bit is set to a 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet. NOTE In double buffer mode for interrupt IN transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM reads the data packet from the X buffer. If the toggle bit is 1, the UBM reads the data packet from the Y buffer. 2.2.7.3 Bulk Transfers The TAS1020B supports bulk data transfers both to and from the host PC. Devices that need to send or receive a large amount of non time-critical data should use the bulk transfer type. IN endpoints 1 through 7 and OUT endpoints 1 through 7 can be configured as bulk endpoints. TAS1020B supports single and double buffering for bulk transfers. 2.2.7.3.1 Bulk Out Transaction Using MCU The steps for a bulk out transaction are as follows: 32 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 1. MCU initializes one of the OUT endpoints as an OUT bulk endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit. 2. The host PC sends an OUT token packet followed by a data packet addressed to the OUT endpoint. If the data is received without an error, the UBM writes the data to the endpoint buffer, updates the data count value, toggles the toggle bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU must first retrieve the data count value. After reading the data packet, the MCU clears the interrupt and clears the NACK bit to allow the reception of the next data packet from the host PC. 4. If the NACK bit is set to 1 when the data packet is received, the UBM simply returns a NACK handshake to the host PC. If the STALL bit is set to 1 when the data packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, no handshake is returned to the host PC. NOTE In double buffer mode for bulk OUT transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM writes the data packet to the X buffer. If the toggle bit is a 1, the UBM writes the data packet to the Y buffer. When a data packet is received, the MCU determines which buffer contains the data packet by reading the toggle bit. However, when using double buffer mode, data packets may be received and written to both the X and Y buffer before the MCU responds to the endpoint interrupt. In this case, simply using the toggle bit to determine which buffer contains the data packet does not work. Hence, in double buffer mode, the MCU reads the X buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the buffers. 2.2.7.3.2 Bulk In Transaction Using MCU The steps followed for a bulk in transaction are: 1. MCU initializes one of the IN endpoints as an IN bulk endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint and setting the NACK bit. 2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates the data count value then clears the NACK bit to a 0 to enable the data packet to be sent to the host PC. 3. The host PC sends an IN token packet addressed to the IN endpoint. After receiving the IN token, the UBM transmits the data packet to the host PC. If the data packet is received without errors by the host PC, an ACK handshake is returned. The UBM then toggles the toggle bit, sets the NACK bit to a 1, and asserts the endpoint interrupt. 4. The MCU services the interrupt and prepares to send the next data packet to the host PC. 5. If the NACK bit is set to 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, the UBM prepares to retransmit the same data packet again. NOTE In double buffer mode for bulk IN transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM reads the data packet from the X buffer. If the toggle bit is a 1, the UBM reads the data packet from the Y buffer. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 33 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2.2.7.3.3 Bulk Out Transaction Through DMA This transaction is used by mass storage class USB applications to move bulk data to an external device via the TAS1020B DMA resources. The difference between MCU-supported bulk transactions and DMA-supported bulk transactions lies in how the data in the assigned out endpoint buffer is distributed to its final destination. Two modes of DMA operation are possible. One mode is a software handshake mode utilizing synchronization communication between the MCU, the USB Buffer Manager (UBM), and an external device. The second mode is a direct exchange mode that bypasses communication with the MCU and directly outputs USB packets to an external device via the DMA resources. Higher bandwidth transactions can be achieved in the direct exchange mode. In both modes, the on-chip C-port is used to output the received bulk data to an external device. To implement DMA-supported transactions, the C-port must be programmed to operate in either a general-purpose (GP) mode or an Audio Codec '97 (AC97) mode. When in the general-purpose mode, SYNC is disabled when there is no valid data in the buffer to be output; in the AC97 mode, the time slot valid bits in the tag field are disabled when there is no valid data in the buffer to be output. Software Handshake Using MCU, UBM, and External Device Bulk data has the lowest priority of all transfers on the USB bus. But when there is little other activity on the USB bus, bulk transfers can achieve significant transfer rates. Bulk transfer rates then can fluctuate greatly, and for this reason it is sometimes necessary to monitor the transfer rate of bulk transfers in order to throttle back the transfer rate when the rate exceeds the bandwidth of the target device. The software handshake mode is provided to enable the implementation of just such a throttling of data. The following steps explain the operation of the software handshake mode. 1. The MCU initializes one of the OUT endpoints as a bulk OUT endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit. 2. To configure a given DMA channel to process a given endpoint in a software handshake mode, the MCU must – Enable the handshake mode by setting the HSKEN bit in the DMA channel control register (DMACTL0 and DMACTL1) to 1. In this same register the MCU must also program the USB endpoint direction and endpoint number fields. – Program the DMA current buffer content register (DMABPCT0 and DMABPCT1) with the number of bulk out packets to be handled by the DMA process without MCU intervention once the MCU has invoked the DMA process. – Program the DMA channel time slot assignment register (DMATSH0 and DMATSH1) with the time slot assignments to be supported by the DMA channel and the number of bytes to be transferred for each supported time slot. 3. The MCU must also appropriately configure the C-port. (See Section 2.2.7.4 for more detail on initializing the C-port). Note that if the C-port is placed in mode 0 (general-purpose mode) the CPTBLK bit in the codec port interface configuration register 4 must be set to 1 to assure that SYNC is disabled when there is no valid data in the buffer to be output. 4. Data is now ready to be received. The UBM, after receiving the bulk out packet and placing it in the appropriate buffer, toggles the toggle bit if the double-buffer mode is set, sets the NACK bit to 1, stores the packet data count in the data count register, and issues an interrupt to the MCU. 5. If the external device indicates that it is ready to receive data, the MCU enables the DMA process by setting the DMAEN bit the DMA channel control register (DMACTL0 and DMACTL1). (Handshaking between the MCU and external device will have to have taken place earlier to determine the status of the external device). 6. Once enabled, the DMA engine proceeds to transfer the contents of the buffer(s) to the C-port for transmittal to the external device. Data availability in the buffer(s) is determined by examining the NACK flags - which are set to 1 when data has been received. For the double buffer case, the buffer to 34 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 be used to retrieve data for the C-port is determined by not only examining the NACK flags but also by monitoring the state of the toggle bit. The NACK bit is cleared by the DMA logic (as opposed to the MCU) each time an entire buffer content has been transferred to the C-port via DMA. 7. If the number of bulk out packets to be handled by the DMA process without MCU intervention is greater than one (the number can be as high as 64K packets), multiple buffer writes take place before the DMA process completes. Every time a data packet is written to a given buffer, the UBM generates the MCU endpoint interrupt. If the MCU wishes to remain autonomous to the DMA process, the MCU must mask off the MCU endpoint interrupt (by clearing the OEPIE bit in the USB out configuration register OEPCNFx) before enabling the DMA process. 8. When the DMA process completes, the DMA channel disables itself and issues a DMA0 or a DMA1 interrupt to the MCU. Upon receiving the interrupt, the MCU knows that DMABPCT packets have been sent out to the C-port. The MCU then enables the appropriate endpoint interrupt (if it had been previously masked off). The process is now complete. Direct Exchange Mode This mode offers the highest bandwidth for bulk OUT transactions. The process is almost identical to the software handshake mode, the only difference being that the Direct Exchange mode, once enabled, runs continuously until disabled; whereas the Software handshake mode only remains active for the processing of DMABPCT packets. The Direct Exchange mode is selected by clearing the bit HSKEN in the DMA channel control register (DMACTL0 and DMACTL1). When the MCU enables the DMA process, after appropriately setting up the endpoint configuration registers, the C-port configuration registers, and the DMA channel, the DMA process remains active until disabled by the MCU. While the DMA channel is active, received packets continue to be retrieved from the appropriate endpoint buffer and transferred to the C-port for transmission to the external device. 2.2.7.3.4 Bulk In Transaction Using DMA The TAS1020B does not support BULK IN using the DMA resources. 2.2.7.4 Isochronous Transfers The TAS1020B supports isochronous data transfers both to and from the host PC. Devices that need to send or receive data at a constant rate must use the isochronous transfer type rate if the bandwidth of the data exceeds the USB bandwidth allotted to interrupt type transactions. IN endpoints 1 through 7 and OUT endpoints 1 through 7 can all be configured as isochronous endpoints. Isochronous transfers must include the use of a DMA channel; MCU-supported isochronous transfers are not allowed. Since the TAS1020B has only two DMA channels, at any point in time only two isochronous transactions can be concurrently supported by the TAS1020B. To setup an isochronous IN or an isochronous OUT transaction, the MCU must initialize the appropriate IN or OUT USB endpoint configuration block. For isochronous transactions, this entails programming the buffer size and buffer base address, enabling the endpoint interrupt, setting the ISO bit (to flag that the endpoint is an isochronous endpoint), clearing the NACK bit, and enabling the endpoint. When the ISO bit is set, the hardware configures the buffer to be a single circular buffer (see Section 2.2.7.4.1), using the endpoint buffer size register I/OEPBSIZx and buffer base address register I/O EPBBAXx. The size of the circular buffer is the size specified in I/OEPSIZx. (This is not to be confused with the same value in I/OEPSIZx yielding two buffers of that size when the double buffer mode is selected for control, interrupt, and bulk transactions.) The TAS1020B DMA engine has two DMA channels. Each channel can be assigned to any IN or OUT endpoint that has been configured as an isochronous endpoint. (As previously discussed, DMA channels can also be assigned to bulk out endpoints). If an isochronous OUT endpoint receives data, the DMA channel assigned to the endpoint will retrieve the data from the endpoint buffer and transfer it to the C-port for outputting to the external device. If a DMA channel is assigned to an isochronous IN endpoint, the DMA channel transfers external device data received on the C-port to the IN endpoint buffer. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 35 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Each DMA channel can only implement data flow between endpoint buffers and the C-port. The configuration of each DMA channel includes a 14-bit field that defines which of the up to 14 time slots in the C-port audio frame the DMA channel supports. Both DMA channels could thus service OUT endpoints, or IN endpoints, with each DMA channel supporting different time slots in the audio frame. Each DMA channel also provides a current buffer count register (DMABCNT0/1). For isochronous OUT transactions, the count in the register represents the number of bytes being transferred from the OUT endpoint buffer to the C-port during the current USB frame. A new count is derived at each USB SOF event, and is the value of the write pointer address setting minus the read pointer address setting at the time of the USB SOF event. The MCU can read the content of this register. The steps required to service DMA-supported isochronous transfers are: 1. The MCU initializes an IN or OUT USB endpoint configuration block. This entails programming the buffer size and buffer base address, setting the ISO bit, setting the number of bytes per isochronous channel, clearing the NACK bit, and enabling the endpoint. Because the endpoint is configured as an isochronous endpoint, the buffer configuration parameters are used to implement a circular buffer rather than one or two linear buffers, and the size specified is the size of the single circular buffer. 2. The MCU configures the selected DMA channel. This entails: – Programming registers DMATSH0/1 and DMATSL0/1, which consists of assigning the time slots to be used and the number of bytes to be transferred per time slot. – Programming register DMACTL0/1, which consists of setting the USB endpoint direction, selecting the endpoint number, and setting the DMA channel enable bit DMAEN. 3. The MCU configures the C-port. This entails: – Programming register CPTCNF1, which consists of setting the number of time slots per audio frame and selecting the C-port interface mode (general purpose mode, AIC mode, etc.). – Programming register CPTCNF2, which consists of setting the length of time slot 0 (number of CSCLK serial clock cycles), setting the length of the remaining time slots (which are all the same in length), and setting the number of data bits per time slot. – Programming register CPTCNF3, which consists of: – Setting the state of DDLY. A 1 programs a one CSCLK clock delay on the data output and data input signals with reference to the leading edge of CSYNC. A 0 removes the delay. – Setting the state of TRSEN. A 1 sets the C-port output to the high-impedance state for those time slots that have no valid data. – Setting the state of CSCLKP. A 1 programs the C-port to be CSCLK falling edge active (CDATO and CSYNC transition on falling edge of CSCLK and DATI is sampled on rising edge of CSCLK). A 0 results in activity on the opposite edges of CSCLK. – Setting the state of CSYNCP. A 1 programs CSYNC to be active high. A 0 programs CSYNC to be active low. – Setting the state of CSYNCL. A 1 programs the length of CSYNC to be the same number of CSCLK cycles as time slot 0. A 0 programs CSYNC to be one CSCLK cycle in length. – Setting the state of BYOR. A 1 results in the DMA reversing the byte order in moving data to/from the endpoint buffer. – Setting the state of CSCLKD. A 1 sets the CSCLK port as an input port (TAS1020B receives CSCLK). A 0 sets the CSCLK port as an output port (TAS1020B sources CSCLK). – Setting the state of CSYNCD. A 1 sets the CSYNC port as an input port (TAS1020B receives CSYNC). A 0 sets the CSYNC port as an output port (TAS1020B sources CSYNC). – Programming register CPTCNF4, which consists of: – Specifying the 4-Bit field ATSL. This field defines which time slot is to be used for secondary communication (command/status) address and data. – Setting the state of CPTBLK. When DMA is to be used to transport USB bulk transfers to external devices via the C-port, the C-port must be placed in either a general-purpose mode or an AC '97 mode, and CPTBLK must be set to one. When the C-port is placed in the general-purpose mode, a state of 1 for CPTBLK results in CSYNC only being present when valid data is present in the current frame. When the C-port is placed in the AC '97 mode, a state 36 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 of 1 for CPTBLK results in CSYNC always being present, but the tag bits in time slot 0 being set to indicate the presence or absence of data. When CPTBLK is set to 0, CSYNC and CSCLK are free running once the C-port is enabled. – Specifying the 3-Bit field DIVB. This defines the divide ratio of MCLK to CSCLK. – Programming bits 4-7 of register CPTCTL to enable or disable the C-port transmit and receive interrupts. Bits 1-2 of register CPTCTL are used to select between primary and secondary codecs when using two codecs in the AC '97 mode. Bit 0 of register CPTCTL (CRST), when cleared to 0, is used to issue resets to external devices via the CRESET output pin. NOTE C-port registers CPTADR, CPTDATL, and CPTDATH are accessed during run time operation to set the address, the data, and the mode (receive (status) or command (write)) for secondary communications. Registers CPTVSLL and CPTVSLH are only used when the AC '97 mode is selected and are used to specify which time slots in the audio frame contain valid data. Registers CPTRXCNF2, CPTRXCNF3, and CPTRXCNF4 must be initialized when the C-port is used in the I2S mode (mode 5) to support an ADC and a DAC running at different frequencies. 2.2.7.4.1 Circular Memory Buffer Implementation A significant feature of DMA-supported isochronous transfers is the circular memory structure used to buffer the incoming data. In most applications, the C-port timing is derived from the USB frame rate using a soft-PLL provided in the TAS1020B firmware. However, the USB frame rate can vary within specified boundaries, and the output phase of the PLL can lag (or lead) the input during such variations. If a linear ping pong buffer implementation is used, tolerance must be built into switching between buffers to accommodate all possible magnitudes of variation in the relative timing between the input and output time references. A circular buffer topology greatly simplifies the implementation of the buffer as the need for decision points on when to switch buffers is eliminated. The circular buffer implementation used in TAS1020B utilizes the same endpoint start (I/OEPBBAXx) and size (I/OEPBSIZx) assignment used by the linear buffer implementation, and the size of the circular buffer is the size specified in I/OEPBSIZx. The circular buffer implementation does require the use of two additional registers - a read pointer and a write pointer. These two registers are controlled by hardware, but are made available to the MCU for debug purposes. Circular Buffer Operation for Isochronous OUT Transactions The operation of the circular buffer for isochronous OUT transactions is as follows. • Initially, the read and write pointers are set in hardware to the OUT endpoint start address. • As the first packet of isochronous data addressed to the endpoint is received, the UBM stores the data into the circular buffer and updates the value of the write pointer by a count of one for each byte written into the buffer. • As soon as the DMA channel detects that the read and write pointers are not the same value (data is available), the DMA channel could begin immediately retrieving data and outputting it to the C-port. However, the DMA channel waits until the next USB SOF is received. • Once the DMA channel has waited until the next SOF is received, the buffer contains a full packet of data. Upon receiving SOF, the DMA channel further waits until the start of the next C-port frame and then begins transferring the buffered data to the C-port, updating the read pointer by one count for each byte of data transferred. At the C-port the data is output to the external device in accordance with the timing requirements of the external device (8 frames for 8 kHz audio sampling, 48 frames for 48 kHz audio sampling, etc.). The DMA channel continues to retrieve data from the buffer and output it to the C-port, update the read pointer, and check the value of the write pointer. Should the DMA-controlled read pointer value ever equal the value of the UBM-controlled write pointer, the process goes on hold and awaits the next USB SOF, where the process again resumes. When the UBM completes writing a packet of data into the endpoint buffer, it loads the data count Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 37 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com value of that packer (number of data samples, not bytes) into field DCNTX/Y of register OEPDCNTX/Yx. The register chosen, OEPDCNTX or OEPDCNTY, is determined by the LSB of the frame count register USBFNL. An LSB value of 1 chooses OEPDCNTY; a value of 0 chooses OEPDCNTX. This count value does not play a role in implementing the data flow for isochronous out transactions, but is provided for and can be accessed by the MCU. As is discussed in the next section, the counts do play a role in implementing the data flow for isochronous in transactions. • The streaming of audio data via the DMA channel continues indefinitely until the DMA engine is halted by the MCU. Circular Buffer Operation for Isochronous IN Transactions For isochronous out transactions, the handshake implemented between the USB bus and the output device ensures that at each USB SOF event, the output has access to a complete USB frame of data. For isochronous in transactions, the mirror condition must be true: the handshake implemented between the USB bus and the input device must ensure that at each USB SOF event, the UBM has access to one or more complete frames of device data. Isochronous out transactions also ensure, by definition, that a complete USB frame of data is transmitted between USB SOF events. But the mirror condition here is not true, there may not be an integer number of device frames received between USB SOF events. If, at each USB SOF event, the UBM is to have access to one or more complete frames of data from the input device, the latest codec frame available to the UBM has to have completed prior to the USB SOF event. But it is not known when the last input device frame to complete prior to the USB SOF event occurs. Thus a timing mark must be set up to mark the worse case arrival time of the last complete input device frame prior to the USB SOF event. The slowest sampling rate supported for an input device is set at 8 kHz (8 kHz audio sampling). At 8 kHz, a frame arrives from the input device every 0.125 milliseconds, which is 1500 12 MHz USB clock periods. Thus a time mark can be set to occur 1500 clock periods before the next USB SOF event. When this time mark occurs, the DMA completes the current input device frame, if a frame is currently being received, and then sets a handshake flag. The DMA also updates the content of register IEPDCNTX/Y with the total number of samples collected since the previous handshake flag was set. When the USB SOF event occurs, the UBM looks at the flag to see if data is available. If data is available, the UBM refers to the count in the register to determine how much data is to be output on the next isochronous in transaction. To accommodate variations in the number of clocks at the output of the soft PLL, with respect to the incoming 12-MHz USB data rate, the time mark count is actually set to 1511, rather than 1500. The extra 11 clock periods assures that the last frame prior to the USB SOF event will have completed. The flag used is the NACK bit in the IEPDCNTX/Y register, and the data count is the 7-bit DCNTX/Y field in the same register. For isochronous in transactions, the register chosen, IEPDCNTX or IEPDCNTY, is also determined by the LSB of the frame count register USBFNL. But in the case of isochronous in transactions, an LSB value of 1 chooses IEPDCNTX and a value of 0 chooses IEPDCNTY. The selection logic for isochronous in transactions then is the reverse of that used for isochronous out transactions. The operation of the circular buffer for isochronous in transactions is as follows. • Initially, the read and write pointers are set in hardware to the IN endpoint start address. At the same time the NACK flags in the IEPDCNTX and IEPDCNTY registers are set to logic 1 and the DCNTX and DCNTY counts are cleared. • As the input device frames are received, they are stored in the circular buffer by the DMA engine. As each byte is stored in the buffer, the DMA engine updates the write pointer by one count, and also keeps count of the number of samples being stored. • When the time mark occurs, marking that there are 1511 USB clock periods remaining until the next USB SOF event occurs, the DMA engine awaits the completion of the current incoming input device frame (if one is currently being received). When the incoming input device frame completes, the DMA engine sets the NACK flag in IEPDCNTX/Y to logic 0 and loads the number of samples received into the DCNTX/Y field of IEPDCNTX/Y. 38 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 • At this time, the DMA engine zeroes its running count of data samples and awaits the next input device frame. For the DMA engine, the process repeats, and at the next time mark, the DMA engine sets the NACK flag in IEPDCNTX/Y to logic 0 and loads the number of samples received into the DCNTX/Y field of IEPDCNTXY. • At the same time that the DMA engine reinitializes itself to receive the next input device frame, the UBM has noted the clearing of the NACK flag in IEPDCNTX/Y. When this occurs, the UBM knows that one or more complete frames reside in the circular buffer, starting at the address pointed to by the read buffer, and that the integer number of frames comprise a total of DCNTX/Y samples. When the USB SOF event occurs, the UBM is thus prepared and can respond to the USB isochronous in transaction when it occurs. As the UBM retrieves data during the isochronous in transaction, it updates the read pointer by one count for each byte retrieved. When DCNTX/Y samples have been output, the NACK bit in IEPDCNTX/Y is set back to logic 1 and the isochronous transaction is terminated. The UBM now awaits the clearing of the NACK bit in IEPDCNTX/Y and the occurrence of the next USB SOF event, at which time the process repeats. The UBM now continues to alternate (ping pong) between the data count and NACK flag value in register IEPDCNTX and the data count and NACK flag value in register IEPDCNTY until the DMA process is terminated by the MCU. • If an isochronous in token is received when there is no new data to be output (the NACK flag bits in both IEPDCNTX and IEPDCNTY registers are at logic 1), the UBM will respond to the isochronous in request with a NULL packet. 2.2.8 Microcontroller Unit The TAS1020B chip contains an 8-bit microcontroller core for control and supervisory functions. The microcontroller core used is based on the industry standard 8052. It is software compatible (including instruction execution times) with the industry standard 8052AH and 8052BH discrete devices, having all their core features plus the additional features corresponding to standard 8052 / 8032 / 80C52BH / 80C32BH / 87C52 parts - except the ONCE mode and program lock are not supported. The MCU core has three 16-bit timer/counter units and a full-duplex serial port (UART). The timer/counter units and the UART are made available via the port 3 bits; thus some of the port 3 bits have dual functionality assignments in accordance with the 80C51 family of microcontrollers (see Section 2.2.11 for more detail on the dual functionality of port 3). 2.2.9 External MCU Mode Operation An external MCU mode of operation is provided for firmware development using an in-circuit emulator (ICE). The external MCU mode is selected by setting pin EXTEN on the TAS1020B high. When the external MCU mode is selected, the internal 8052 MCU core of the TAS1020B is disabled. Also in the external MCU mode, the GPIO ports are used for the external MCU data, address, and control signals. See Section 1.7, Terminal Functions - External MCU Mode, for details. When in the external mode of operation, the external MCU or ICE is able to access the memory mapped IO registers, the USB configuration blocks and the USB buffer space in the TAS1020B. Texas Instruments has developed a TAS1020B evaluation module (EVM) to allow customers to develop application firmware and to evaluate device performance. The EVM board provides a 40-pin dip socket for an ICE and headers to allow expansion of the system in a variety of ways. 2.2.10 Interrupt Logic The 8052 MCU core used in the TAS1020B supports the five standard 8052 MCU interrupt sources. These five standard MCU interrupt sources are timer 0, timer 1, serial port, external 1 (INT1), and external 0 (INT0).The timer 0, timer 1, and serial port interrupts are MCU-internal interrupts, but INT0 and INT1 are external to the MCU core. Figure 2-2 shows the associated interrupt circuitry external to the MCU core, but within the TAS1020B chip. INT0 is input into the MCU core via port 3 bit P3.2, and INT1 is input into the MCU core via port 3 bit P3.3. P3.3 can also be configured, under firmware control, to serve as a general-purpose IO (GPIO) port bit. But the input side of P3.2 must be dedicated to servicing the INT0 function, as all additional interrupt sources from within the TAS1020B device are ORed together to Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 39 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com generate the INT0 signal into port 3, bit P3.2. The other interrupt sources are: the eight USB IN endpoints, the eight USB OUT endpoints, USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo start-of-frame, USB setup stage transaction, USB setup stage transaction over-write, codec port interface transmit data register empty, codec port interface receive data register full, I2C interface transmit data register empty, I2C interface receive data register full, DMA channel 0, DMA channel 1, and the external interrupt XINT. 40 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B DP DM USB Bus Suspend Counter En clk Decode > 5 ms Reset Reset Counter clk Decode > 2.5 us En Interrupt Vector Reg (VECINT) Logic Interrupts Decode /XINT Int WE D[0:7] NX2 NX1 MCU write to Interrupt Vector Register ”clears” current vector to next vector, or to 24h if no other interrupt pending RST IDL Power Control Register (PCON) USB Interrupt Mask Register (USBMSK) Internal Interrupts (After Masks Applied) Must be programmed to be low level triggered (ITO bit in MCU’s TCON control register = 0), as multiple internal TAS1020B events can occur concurrently . The internal hardware assures that each interrupt remains low until the MCU signals that the interrupt has been serviced. Function Suspend Request Interrupt Function Resume Request Interrupt P3MSK7 P3MSK2 P3MSK0 P3.7−IN P3.6−IN P3.5−IN P3.4−IN P3.3−IN P3.1−IN P3.0−IN P3.7−IN P3.2−IN P3.0−IN USB Reset Interrupt Suspend FRSTE USB Control Register (USBCTL) XINTEN 7 6 5 0 Global Control Register (GLOBCTL) RESR 0 4 5 6 7 Cl Cl Cl Decode Resume Int Decode Suspend Int Decode USB Reset Int USB Status Register (USBSTA) 0 4 5 6 7 0 3 4 5 7 8052 MCU CORE CRST 0 1 7 Suspend Global Reset Codec Port Interface Control and Status Register (CPTCTL) Clear USB Serial Interface Engine (SIE) and USB Buffer Manager (UBM) 7 1 0 PLL SubSystem Turn Off Turn On D Q CL ’1’ P3 Mask Register (P3MSK) 7 6 3 2 1 0 Synchronized XINT Remote ”Wake−Up Interrupt Suspend TAS1020B Clocks Q D Q D Q D Q D 24 MHz Clk Q D CL 24 MHz Clk Set Set Set Q D 48 MHz Clk MRESET RSTO CRESET XINT (P3.2−IN) SUSR RSTR RESR SUSR RSTR TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 2-2. TAS1020B Interrupt, Reset, Suspend, and Resume Logic Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 41 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com The events that trigger the interrupt sources are: • USB OUT endpoint interrupts: these interrupts are issued by the USB Buffer Manager (UBM) whenever a complete data packet has been received and stored in an endpoint buffer. Each endpoint is assigned a dedicated OUT endpoint interrupt. For isochronous transactions, however, OUT endpoint interrupts are not issued. The firmware must clear OUT endpoint interrupts by writing to the interrupt vector register. • USB IN endpoint interrupts: these interrupts are issued by the USB buffer manager (UBM) whenever it receives an ACK handshake packet from the host PC indicating that a data packet sent by the UBM was received without error. Each endpoint is assigned a dedicated IN endpoint interrupt. For isochronous transactions, however, IN endpoint interrupts are not issued. The firmware must clear IN endpoint interrupts by writing to the interrupt vector register. • USB function reset interrupt: whenever the host PC issues a USB reset, the bit RSTR in the USB status register USBSTA is set. The setting of this bit causes all of the USB-related logic blocks in the TAS1020B to be reset. If the function reset enable (FRSTE) bit in the USB control register USBCTL is set, the setting of bit RSTR in the USB status register results in a global reset being issued - which resets the MCU core and activates the reset output RSTO. If bit FRSTE is not set, the setting of bit RSTR results in the USB function reset interrupt being issued. If a global reset is issued, it clears the USB status register USBSTA, and thus clears bit RSTR. If a USB function reset interrupt is issued, the interrupt and bit RSTR must be cleared in firmware by writing to the interrupt vector register. • USB function suspend interrupt: whenever the host PC keeps the USB bus in the idle or j state for more than 5 ms, bit SUSR in the USB status register USBSTA is set. This, in turn, results in the activation of the USB function suspend interrupt. The interrupt and bit SUSR must be cleared in firmware by writing to the interrupt vector register. • USB function resume interrupt: whenever a suspend state is active and the host PC resumes activity on the USB bus, bit RESR in the USB status register USBSTA is set. This, in turn, results in the activation of the USB function resume interrupt. The interrupt and bit RESR must be cleared in firmware by writing to the interrupt vector register. • USB start-of-frame interrupt: whenever the TAS1020B detects the reception of a start-of-frame (SOF) packet from the host PC, bit SOF in the USB status register USBSTA is set. This, in turn, results in the activation of the USB start-of-frame interrupt. The interrupt and bit SOF must be cleared in firmware by writing to the interrupt vector register. • USB pseudo start-of-frame interrupt: the TAS1020B employs a counter that runs between USB start-of-frame events, and is cleared upon every reception of a USB SOF event. This counter is included in the TAS1020B to generate pseudo start-of-frame interrupt in case the SOF packet on the USB bus is corrupted. This is done to maintain synchronization to the USB bus and maintain the fidelity any on going streaming audio application. If this count ever reaches a value representative of a time span longer than the 1 ms period of a USB frame, a USB SOF was not received. In such an event, bit PSOF in the USB status register USBSTA is set. This, in turn, results in the activation of the USB pseudo start-of-frame interrupt. The interrupt and bit PSOF must be cleared in firmware by writing to the interrupt vector register. • USB setup stage transaction interrupt: whenever a control transaction is initiated by the host PC, and the setup data packet following the setup token packet is received without error, bit SETUP in the USB status register USBSTA is set. This, in turn, results in the activation of the USB setup stage transaction interrupt. The interrupt and bit SETUP must be cleared in firmware by writing to the interrupt vector register. • USB setup stage transaction overwrite interrupt: the USB 1.1 specification states that should a setup transaction be received before a previously initiated control transaction is complete, the current control transaction must be aborted and the new transaction processed. The USB setup stage transaction interrupt addresses this requirement. The timing conditions under which this interrupt is issued are shown in Figure 2-3. In Figure 2-3, the host has sent two control transactions. Having received the setup data packet of the first transaction without error, the SETUP bit in the USB status register USBSTA is set and the USB setup stage transaction interrupt issued. While the MCU core is still processing the USB setup stage 42 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B SETUP TOKEN PACKET SETUP DATA PACKET ACK PACKET CONTROL TRANSACTION #1 CONTROL TRANSACTION #2 MCU CORE PROCESSING INTERRUPT USB Setup Stage Transaction Overwrite Interrupt USB Setup Stage Transaction Interrupt USB Bus Traffic SETUP Bit In USB Status Register STPOW Bit In USB Status Register SETUP TOKEN PACKET SETUP DATA PACKET ACK PACKET TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 transaction interrupt (as indicated by the set state of the SETUP bit, which the MCU does not clear until exiting the USB setup stage transaction interrupt service routine), the host issues another control transaction. Issuing another USB setup stage transaction interrupt would not be of value, as the MCU is still in the USB setup stage transaction interrupt service routine processing the first control transaction. Thus the USB setup stage transaction overwrite interrupt is used to indicate that a second control transaction has been received while still processing the first control transaction. If a setup data packet is received without error while the SETUP bit is set, the STPOW bit in the USB status register USBSTA is set and the USB setup stage transaction overwrite interrupt is issued. The interrupt and STPOW bit must be cleared in firmware by writing to the interrupt vector register. Figure 2-3. Activation of Setup Stage Transaction Overwrite Interrupt • Codec port interface transmit data register empty interrupt: codec port modes AC '97 and AIC, and the general-purpose codec port mode, all support secondary communication. Both secondary read and secondary write modes are supported. For the write mode (R/W bit in the codec port interface address register CPTADR cleared to logic 0), command/status can be sent to the codec port by the MCU for transmission to the codec. The codec hardware inserts the data into the proper time slot in the codec frame and transmit the data. The MCU writes the command/status data to the codec port interface data register CPTDATL (and register CPTDATH for 16-bit data). The data written by the MCU is not output until the address is written to the codec port interface address register CPTADR. Upon writing the address to CPTADR (and clearing bit R/W), the codec clears the transmit data register empty bit TXE in the codec port interface control and status register CPTCTL to logic 0. The clearing of this bit flags the hardware that new command/status data has been output. When the command/status data is taken by the codec, bit TXE is set to 1, and the codec port interface transmit data register empty interrupt is issued. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the TXE bit. • Codec port interface receive data register full interrupt: codec port modes AC '97 and AIC, and the general-purpose codec port mode, all support secondary communication. Both secondary read and secondary write modes are supported. For the read mode (R/W bit in the codec port interface address register CPTADR set to logic 1), command/status data received by the codec can be retrieved by the MCU. Upon receiving secondary command/status data, the codec hardware transfers the data to the codec port interface data register CPTDATL (and CPTDATH if 16-bit data is being transferred), sets the receive data register full bit RXF in codec port interface control and status register CPTCTL to logic 1, and issues the codec port interface receive data register full interrupt. When the MCU reads the command/status data, RXF is cleared to 0. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear bit RXF. (Note that all secondary command/status receive transactions take two codec frames to complete. First the MCU writes the address of the command/status data to be read to CPTADR and sets the R/W bit in register CPTADR to logic 1. On the next codec frame, the address is sent to the codec. On the following codec frame, the requested data is output by the codec and received at the TAS1020B codec port.) Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 43 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com • I2C interface transmit data register empty interrupt: whenever the MCU writes to the I2C interface transmit data register I2CDATO, it results in the hardware clearing the transmit data register empty bit TXE in the I2C interface control and status register I2CCTL. When the data byte is output onto the I2C bus, the hardware sets TXE back to logic 1 and the I2C interface transmit data register empty interrupt is issued. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the TXE bit. • I2C interface receive data register full interrupt: whenever the I2C interface receive data register I2CDATI receives a byte of data off the I2C bus, the hardware sets the receive data register full bit RXF in the I2C interface control and status register I2CCTL and issues the I2C interface receive data register full interrupt. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the RXF bit. The RXF bit in the I2C interface control and status register I2CCTL is cleared whenever the MCU reads the contents of the I2C interface receive data register I2CDATI. • External interrupt XINT: this interrupt is provided to give a user the ability to issue interrupts from external sources. XINT is logic 0 active. The interrupt is sampled by synchronization logic internal to the TAS1020B, as shown in Figure 2-2. As Figure 2-2 shows, XINT must be remain in an active-low state for at least one period of the 24 MHz clock to assure that the interrupt is recognized. Also, XINT must transition to an inactive state (logic 1) and then transition back to the active state (logic 0) if another XINT interrupt is to be recognized. If XINT remains in the active low state, it does not result in issuing multiple XINT interrupts. The firmware must clear this interrupt by writing to the interrupt vector register. • DMA channel 0 interrupt: this interrupt becomes active only during bulk OUT transactions utilizing DMA channel 0 when the software handshake mode is selected (see Section 2.2.7.3.3). In this mode of operation the programmable variable DMABPCT - registers DMABPCT0 and DMABPCT1 - instructs DMA channel 0 as to how many bulk OUT packets it must handle before ceasing operation and issuing the DMA channel 0 interrupt. The firmware must clear this interrupt by writing to the interrupt vector register. • DMA channel 1 interrupt: this interrupt is identical in operation to the DMA channel 0 interrupt. Note that the same count variable DMABPCT is used for both DMA interrupts. In fact, as described in Section 2.2.12, only one of the two DMA channels can be active when supporting a bulk OUT transaction. - thus the need for only one count variable DMABPCT. The interrupts for the USB IN endpoints and USB OUT endpoints can be masked. An interrupt for a particular endpoint occurs at the end of a successful transaction to that endpoint. A status bit for each IN and OUT endpoint also exists. However, these status bits are read only, and therefore, these bits are intended to be used for diagnostic purposes only. After a successful transaction to an endpoint, both the interrupt and status bit for an endpoint are asserted until the interrupt is cleared by the MCU. The USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo start-of- frame, USB setup stage transaction, and USB setup stage transaction over-write interrupts can all be masked. A status bit for each of these interrupts also exists. Refer to the USB interrupt mask register and the USB status register for more details. Note that the status bits for these interrupts are read only. For these interrupts, both the interrupt and status bit are asserted until the interrupt is cleared by the MCU. The codec port interface transmit data register empty, codec port interface receive data register full, I2C interface transmit data register empty, and I2C interface receive data register full interrupts can all be masked. A status bit for each of these interrupts also exists. Note that the status bits for these interrupts are read only. However, for these interrupts, the status bits are not cleared automatically when the interrupt is cleared by the MCU. Refer to the codec port interface control and status register CPTCTL and the I2C interface control and status register I2CCTL for more details. The external interrupt input (XINT) is logically ORed with the on-chip interrupt sources. An enable bit exists for this interrupt in the global control register GLOBCTL. This interrupt does not have a status bit. 44 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.11 General-Purpose I/O (GPIO) Ports Figure 2-4 shows the architecture of the MCU port bits in the TAS1020B. There are two GPIO ports visible to external devices - port 1 and port 3. In examining the functionality of these ports two interfaces must be examined - the I/O driver interface provided at the I/O pads of the TAS1020B and the interface provided at the M8052 MCU core. At each I/O pad servicing the GPIO ports, the individual data input (DI) and data output (DO) lines into the pads are combined into one bidirectional external line. Each I/O pad is also assigned a separate enable line EN. When EN is a logic 0 the output driver is enabled, and when EN is a logic 1 the input buffer is enabled. This implementation means that as an output the GPIO pin actively sinks current in the logic 0 state, but drives the logic 1 state through the 100-μa pullup. However, to obtain an acceptable rise time when the output transitions from a logic 0 to a logic 1, the EN signal remains active for two clock periods after the output data transitions from a logic 0 to a logic 1. For two clock periods then the output buffer actively drives the logic 1 output level before yielding to the 100 μa pullup. This implementation also means that to use a GPIO pin as an input, the DO line for that pin must be set to a logic 1 and the external source driving the pin must be able of sinking the 100 μa pullup when driving a logic 0. (Some port 3 bits also require that the alternate output data source be at logic 1 to use the pin as a GPIO input). The TAS1020B global control register has two bits - P1PUDIS and P3PUDIS - that control the enabling and disabling of the 100 μa pullups for port 1 and port 3 respectively. If firmware disables the 100-μA pullups in one of the ports - by setting P1PUDIS or P3PUDIS to logic 1 - then when a port bit is configured as an output, a logic 1 output will transition to a high-impedance state after the two clock delay period has expired. At power-up, and after a global reset, all GPIO pins are configured as input ports with all 100-μA pullups enabled(1). The MCU core implements each GPIO bit using three signals - DI, DO, and EN. For both port 1 and port 3, EN is derived from DO by ANDing DO with a two clock delayed version of DO. This provides a two-clock delay in transitioning EN from a logic 0 to a logic 1 after DO transitions from a logic 0 to a logic 1. It is this circuitry that results in the output buffer in the I/O pad actively driving a logic 1 output for two clock periods before yielding to the 100-μA pullup or transitioning to a high-impedance state. (1) At power-up, GPIO pins P3.0 and P3.1 can initialize as inputs, outputs driven high, or outputs driven low. After MRESET is high and clocks start, P3.0 and P3.1 become inputs. The user's firmware application can then reprogram them as desired. This behavior occurs only at power-up. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 45 Submit Documentation Feedback Product Folder Link(s): TAS1020B Mode 0 Tx Data Send Tx Clk Rx Data Tx Clk (mode 0) UART MCUDO Q MCU Data Out Alternate ADO Data Out MCU Read MCU Bus MCU MCUDI Data In ADI Alternate Data In EN DO DI P3.0 EN DO DI ADO MCUDO MCUDI ADI P3.1 EN DO DI ADO MCUDO MCUDI ADI P3.2 EN DO DI ADO MCUDO MCUDI ADI P3.3 EN DO DI ADO MCUDO MCUDI ADI P3.4 EN DO DI ADO MCUDO MCUDI ADI P3.5 EN DO DI ADO MCUDO MCUDI ADI P3.6 EN DO DI ADO MCUDO MCUDI ADI P3.7 Timer Logic Timer 0 Event Clk Timer 1 Event Clk Timer 1 Gate Q P1.3 Q P1.4 Q P1.5 Q P1.6 Q P1.7 Q P1.2 Q P1.1 Q P1.0 EN EN EN EN EN EN EN EN DO DI DO DI DO DI DO DI DO DI DO DI DO DI DO DI I/O Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 100 ua P3.1 UART Tx Data (Mode 0) TAS1020B Interrupt Logic On−Chip Interrupts P1PUDIS 0 GLOBCTL Reg Mux TAS1020B Read Pulse Mux TAS1020B Write Pulse Not Used Not Used EXTEN I/O Drivers M8052 MCU CORE TAS1020B P3.0 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua Q D Q D MCU Clk Delay Delay Delay Delay Delay Delay Delay Delay D Q D Q MCU Clk UART Rx Data Delay Timer 2 Event Clk Timer 2 Ext. Trigger P3.2 (output only) / XINT UART Tx Data (Mode 0) UART Tx Clk (Mode 0) P3.3 / INT1 / Timer 1 Gate P3.4 / Timer 0 Event P3.5 / Timer 1 Event WR (output only, internal MCU mode only) WRD (input only, external MCU mode only) RD (output only, internal MCU mode only) RRD (input only, external MCU mode only) Not Used Not Used INT0 Not Used INT1 Not Used Not Used WR Not Used RD Not Used MCU Read VREN RESET MCU Read MCU Read MCU Read MCU Read MCU Read MCU Read MCU Read VREN Reset P3PUDIS 7 6 5 4 3 2 1 Tx Data (Mode 0) Tx Data (Mode 0) TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-4. GPIO Port 1 and Port 3 Functionality Also, as shown in Figure 2-4, both ports can service logical units internal to the MCU core, as well as service the memory-mapped discrete input and output lines assigned to each port. 46 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.11.1 Port 3 GPIO Bits As illustrated in Figure 2-4, alternative inputs on port 3 are routed directly from the DI input at the MCU core interface to their destination within the MCU core. It is also noted that when the port bit is used as an alternative input, the value of the input can still be read by the MCU. If the port bit is to be used as a general-purpose input, the firmware must make the proper settings so that the alternative logic unit that receives the general-purpose input does not erroneously respond to the input. Each alternative output on port 3 is ANDed with the memory-mapped latch (Special Function Register - SFR) assigned to that port bit, and the result is DO. This means that if the alternate output is to be used, the latch must be set to logic 1. Similarly, if the latch is to be the source for DO, the alternate output must be logic 1. (The MCU core assures that if the logical unit supplying the alternate output is not used, its default state is logic 1). 2.2.11.1.1 UART Alternative Functions Port 3 GPIO bits P3.0 and P3.1, in addition to being able to serve as general-purpose I/O bits, can also serve to implement UART functionality. The UART implemented offers four modes of operation. In mode 0, UART output data is output on port bit P3.0 and the transmit clock (MCU clock/12) is output on port bit P3.1. In modes 1, 2, and 3 UART receive data is input on P3.0 and UART transmit data is output on P3.1. Modes 1, 2, and 3 are then full duplex modes; serial data can be transmitted and received simultaneously. In all four UART modes, transmission is initiated by any instruction that accesses the MCU-core register SBUF. If this register is not written to, the alternate output lines for P3.0 and P3.1 are at their default logic 1 state. P3.0 and P3.1 can then be used as general-purpose outputs if no instructions access register SBUF. The REN bit in the MCU serial port control register SCON enables UART reception if set to logic 1. If REN is cleared to logic 0, using P3.0 as a general-purpose input does not result in erroneous behavior in the UART logic block. P3.1 has no alternative input function, and thus it can be used as a general-purpose input if the latch assigned to that bit is set to logic 1 and no instructions access register SBUF. (P3.0 also requires that its latch be set to logic 1 and that no instructions access register SBUF if it is to be used as a general-purpose input). 2.2.11.1.2 External Interrupts XINT and INT1 The MCU core provides ports for two external interrupts (external to the MCU core) - INT0 and INT1. INT0 is an alternate input for port 3 bit P3.2 and INT1 is an alternate input for port 3 bit P3.3. As seen from both Figure 2-2 and Figure 2-4, INT0 is used to service all TAS1020B internal interrupts as well as the external interrupt XINT. INT1 only services GPIO pin P3.3, and thus can be used as a dedicated interrupt line. Because INT0 services all internal interrupts, the input DI for P3.2 must be dedicated to its alternative input function INT0. Thus P3.2 cannot be used as a general-purpose input. However, if the external interrupt XINT is not required, P3.2 can be used as a general-purpose output. Port 3 bit P3.3 can be used as a general-purpose output, a general-purpose input, or as INT1. This bit can also serve as a gate for timer 1 (see Section 2.2.11.1.3). 2.2.11.1.3 Timer Alternative Functions The MCU core has three 16-bit timer/counter registers: timer 0, timer 1, and timer 2. In the timer mode, the timer/counter register is incremented every MCU machine cycle (MCU clock/12). In the counter mode, the timer/counter register is incremented in response to a falling edge (logic 1 to logic 0 transition) at its assigned port bit input - P3.4 for timer 0, P3.5 for timer 1, and P1.0 for timer 2. To qualify as an event clock in the counter mode, the external source must hold each logic state - logic 1 and logic 0 - for a period of time greater than 12 MCU clock periods. This means that the maximum count rate in the counter mode is MCU clock/24. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 47 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Timer 1 can be gated on and off under external control to facilitate pulse width measurements. The external control is brought in on port 3 bit P3.3, which is the same input that sources the alternate input function INT1. Thus P3.3 can be thought of as having two alternate input functions. The MCU core also provides gating for timer 0 via P3.2. However, the input DI for P3.2 must be dedicated to INT0 so that the internal TAS1020B interrupts can be serviced. As a result, gated timing is not allowed on timer 0. In addition to the external event clock on port 1 bit P1.0, timer 2 has an external trigger input on port 1 bit P1.1 which can be used to either capture the value in the counter when in the counter mode or reload the timer when in the timer mode. If the C/NT bit in the appropriate MCU special function register (SFR) for a given timer is cleared to enable a timer function, or if the timer/counter interrupt is masked off by clearing the appropriate ET bit in the MCU interrupt enable register IE, the corresponding port bit input providing the external event clock can be used as a general-purpose input. For the external trigger input for timer 2, it is necessary to clear bit EXEN2 in the MCU timer/counter 2 control register T2CON if this input is to be used as a general-purpose input. 2.2.11.1.4 MCU Read/Write Pulse Alternate Function The TAS1020B provides the capability of replacing the internal MCU core with an in-circuit emulator (ICE) for firmware development. When in the external MCU mode of operation (EXTEN = 1), port 3 bits P3.7 and P3.6 respectively are used to input the ICE-generated memory read and write pulses so that the ICE can access the memory-mapped resources internal to the TAS1020B (but not those resources internal to the MCU core itself). When in the internal MCU mode, P3.6 and P3.7 output the external memory write and read pulses respectively from the MCU core, and can be used as troubleshooting aids. P3.6 and P3.7 cannot be used as GPIO resources. 2.2.11.2 Port 1 GPIO Bits Port 1 has two bits that have alternate input functionality - P1.0 and P1.1. The alternate function serviced by these inputs is timer 2. P1.0 provides the external event clock for timer 2 and P1.1 provides the external trigger. These alternate functions and the conditions under which these two bits can be used as GPIO bits are discussed in Section 2.2.11.1.3. Port 1 provides no alternate output functionality. 2.2.11.3 Pullup Macro Figure 2-5 shows the equivalent circuit of the pullup "resistor" of the TAS1020B. For use with 3.3-V I/Os only. Figure 2-5. Pull-Up Logic Symbol Table 2-4. Electrical Characteristics of Pullup Resistors(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO Output current VO = 0 V –35.98 –90.67 –197.38 μA FI Input loading factor TAP 1.65 pF FI Input loading factor PWRDN 2.50 SL Cpd Equivalent power dissipation capacitance 0.04 pF (1) When PWRDN = H, the current source is turned off. 48 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.12 DMA Controller The TAS1020B provides two DMA channels for transferring data between the USB endpoint buffers and the codec port interface. The DMA channels are provided to support the streaming of data for USB isochronous or bulk OUT endpoints only. Each DMA channel can be programmed to service one isochronous endpoint. The endpoint number and direction are programmable using the DMA channel control register provided for each DMA channel. For the two AC '97 modes supported by the TAS1020B, one DMA channel can be assigned to support bulk OUT transactions and the second DMA channel assigned to support isochronous IN transactions. An example would be downloading an AC3 file for storage via a bulk OUT transaction while, at the same time, supporting an isochronous recording session. For all formats and protocols other than AC '97, however, if a DMA channel is assigned to support bulk OUT transactions, it can be the only DMA channel active. If, for example, DMA channel 0 is assigned to support bulk OUT transactions in the General Purpose mode, then DMA channel 1 cannot be assigned to support bulk OUT or isochronous transactions. Section 2.2.7.3.3 provides more detail on DMA-supported bulk OUT transactions. The codec port interface time slots to be serviced by a particular DMA channel must also be programmed. For example, an AC '97 mode stereo speaker application uses time slots 3 and 4 for audio playback. Therefore, the DMA channel used to move the audio data to the codec port interface must set time slot assignment bits 3 and 4 to a 1. Each DMA channel is capable of being programmed to transfer data for time slots 0 through 13 using the two DMA channel time slot assignment registers provided for each DMA channel. The number of bytes to be transferred for each time slot is also programmable. The number of bytes used must be set based on the desired audio data format. 2.2.13 Codec Port Interface The codec port interface is a configurable serial interface used to transfer data between the TAS1020B IC and a codec device. The serial protocol and formats supported include AC '97 1.0, AC '97 2.0, and several I2S modes. In addition, a general-purpose mode is provided that can be configured to various user defined serial interface formats. Configuration of the interface is accomplished using the four codec port interface configuration registers: CPTCNF1, CPTCNF2, CPTCNF3, and CPTCNF4. In I2S mode 5, CPTRXCNF2, CPTRXCNF3, and CPTRXCNF4 are used to configure the C-port in the receive direction. See Section 6.5.4 for more details on these registers. The serial interface is a time division multiplexed (TDM) time slot based scheme. The basic format of the serial interface is determined by setting the number of time slots per codec frame and the number of serial clock cycles (or bits) per time slot. The interface in all modes is bidirectional and full duplex. For all modes except the I2S modes, command/status data as well as audio data can be transferred via the serial interface. Transfer of the audio data packets between the USB endpoint data buffers and the codec port interface is controlled by the DMA channels. The source and/or the destination of the command/status address and data values is controlled by the MCU. The features of the codec port interface that can be configured are: • The mode of operation • The number of time slots per codec frame • The number of serial clock cycles for slot 0 • The number of serial clock cycles for all slots other than slot 0 • The number of data bits per audio data time slot • The time slots to be used for command/status address and data • The serial clock (CSCLK) frequency in relation to the codec master clock (MCLK) frequency • The source of the serial clock signal (internally generated or an input from the codec device) Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 49 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com • The source of the codec master clock signal used to generate the internal serial clock signal (internally generated by the ACG or an input to the TAS1020B device) • The polarity, duration, and direction of the codec frame sync signal • The relationship between the codec frame sync signal and the serial clock signal • The relationship between the codec frame sync signal and the serial data signals • The relationship between the serial clock signal and the serial data signals • The use of zero padding or a high-impedance state for unused time slots and/or bits • The byte ordering to be used 2.2.13.1 General-Purpose Mode of Operation In the general-purpose mode the codec port interface can be configured to various user-defined serial interface formats using the pin assignments shown in Table 2-5. This mode gives the user flexibility to configure the TAS1020B to connect to various codecs and DSPs that do not use a standard serial interface format. Table 2-5. Terminal Assignments for Codec Port Interface General-Purpose Mode TERMINAL GENERAL-PURPOSE MODE 0 NO. NAME 35 CSYNC CSYNC I/O 37 CSCLK CSCLK I/O 38 CDATO CDATA0 O 36 CDATI CDATA1 I 34 CRESET CRESET O 32 CSCHNE NC O Serial bus protocols AC '97, AIC, and I2S are specific settings of the programmable parameters offered in the general-purpose mode. The general-purpose mode then can be thought of as the primary mode of the codec interface port, with all other modes being special cases of the general-purpose mode. Figure 2-6, Figure 2-7, and Figure 2-8 show three general-purpose mode codec configuration examples. Figure 2-6 gives the settings required to implement AC '97 1.0, Figure 2-7 gives the settings required to implement AIC, and Figure 2-8 gives the settings required to implement I2S. In all three cases the parameters that define these modes are included in the figures. It should be noted the MODE bits in codec port interface configuration register 1 (CPTCNF1) can be used to specifically select either AC '97 1.0, AIC, or I2S. However, when using the specific mode selections, the firmware still must set all parameters in the codec port interface configuration registers. The MODE bits are used simply to implement mode-specific behavior not covered by the programmable parameters. An example of this would be setting, when in one of the two AC '97 modes, those time slot tag bits in the time slot 0 tag word that correspond to the time slots that have valid data. 50 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.1 Parameter Assignments - AC '97 1.0 In Figure 2-6, the codec port interface is configured for 13 time slots. The word size for time slot 0 is 16 bits, whereas the word size for all other time slots is 20 bits. Time slots 1 and 2 are used for secondary communication, and, in the example of figure 2-5, time slots 3, 4, 6, 7, 8, and 9 have valid audio data. The sync line CSYNC is programmed to be logic 1 active for the duration of time slot 0. CSYNC and CDATO are programmed to transition on the rising edge of CSCLK, which means that CDATI will be sampled on the falling edge of CSCLK. For the example of Figure 2-6, each audio data word is only 16 bits in length, and the 4 LSBs of the 20-bit data word slot are set to logic 0. Byte order reversal (BYOR) is not set, so the byte ordering of the data as received is preserved - both from the USB bus (OUT transactions) and from the external codec (IN transactions). To conform with AC '97 timing requirements, it is necessary that both transmit and receive data be delayed by one CSCLK clock period with respect to the rising edge of CSYNC. This is accomplished by setting DDLY to logic 1. Lastly, DIVB is programmed to set CSCLK to MSCLK/2. This allows MSCLK to be set at 24.576 MHz and source the oscillator input XTRL_IN on AC '97 compliant codecs. Figure 2-6 also points out that time slot assignments in AC '97 modes need not be the same for input data frames and output data frames. For output data frames (CDATO), the settings in bit fields VTSL(3:7) and VTSL(8:12) define which time slots have valid data. For input data frames (CDATI) the valid time slots are determined from the settings of the time slot valid tag bits in the 16-bit tag word received in time slot 0. The hardware uses these bit settings to extract the valid data from the input data frame and output it, via a DMA channel, to an endpoint buffer resource. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 51 Submit Documentation Feedback Product Folder Link(s): TAS1020B 0 Tag Rdy CSYNC CSCLK CDATO 0 DDLY = 1 CSCLK CDATO D15 0 CSCLKP = 0 CSYNCP = 1 CSYNCL = 1 Time Slot 0 Length = TSL0L = 10b (16 CSCLK Periods) Time Slot Length = TSLL = 011b (20 CSCLK Periods) Data Bits Per Time Slot = BPTSL = 001b (16) Number Of Time Slots = NTSL = 01100b (13) Mode = MODE = 010b (AC’97 1.0 Mode) BYOR = 0 Cmd Time Slot = ATSL = 0001b VTSL(3:7) = 11011b VTSL(8:12) = 11000b CSYNC CDATI CDATO Tag TRSEN = 0 MCLKO (XTL_IN) CSCLK DIVB = 001b Status Addr Cmd Addr 1 Status Data Cmd Data 2 PCM Left PCM Left 3 PCM Rt PCM Rt 4 0 . . . 0 5 PCM Mike PCM Cen 6 PCM L Surr 7 PCM R Surr 8 LFE 9 0 . . . 0 10 0 . . . 0 11 0 . . . 0 12 TS1 1 TS2 2 TS12 12 0 13 ID1 14 ID0 15 D14 1 D13 2 D0 15 0 16 0 17 0 18 0 19 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-6. Codec Port Interface Parameters − AC '97 1.0 52 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.2 Parameter Assignments - AIC Figure 2-7 shows the parametric settings for the AIC mode. In Figure 2-7, the codec port interface is configured for 16 time slots. The word size for all time slots, including time slot 0, is 16 bits. Time slot 0 is the only active audio time slot and time slot 8 is assigned to handle secondary communications. The sync line CSYNC is programmed to be logic 1 active for one CSCLK period. DDLY is set to logic 1, and thus transmit data (CDATO) and receive data (CDATI) are both delayed by one CSCLK period with respect to the rising edge of CSYNC. CSYNC and CDATO are programmed to transition on the rising edge of CSCLK, and consequently CDATI is sampled on the falling edge of CSCLK. Byte order reversal (BYOR) is not set, so the byte ordering of the data as received is preserved - both from the USB bus (OUT transactions) and from the external codec (IN transactions). The 3-state enable (TRSEN) is set, and thus CDATO goes to a high-impedance state during the outputting of non-valid time slots. Lastly, CSCLK is set to MSCLK/8. (This parameter selection is not part of the AIC standard.) AIC requires both input (CDATI) and output (CDATO) audio data reside in time slot 0 and secondary communication information reside in time slot 8. Thus, unlike AC '97, AIC does not require the use of the valid time slot tag bits VTSL as there is no tag word needed to identify which time slots are valid. A unique feature of AIC is the generation of a second CSYNC frame sync pulse within a given frame if a secondary transaction is taking place. If the MCU has not output data requesting a secondary transaction, the second frame sync pulse shown in Figure 2-7 is not generated. Thus without secondary communication there are 256 CSCLK periods between frame sync pulses, and with secondary communication there are 128 CSCLK periods between frame sync pulses. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 53 Submit Documentation Feedback Product Folder Link(s): TAS1020B D15 Data Bits / Time Slot = BPTSL = 001b (16) Time Slot 0 Length = TSL0L = 10b (16) CSYNCL = 0, CSYNCP = 1 CSCLKP = 0 DDLY = 1 BYOR = 0 Time Slot 0 Time Slot 1 Time Slot 7 Time Slot 8 Time Slot 9 Time Slot 14 Time Slot 15 FC CSYNC DAC Data Register W. Data CDATO /Register R. Addr ADC Data Register Read CDATI Data CSCLK CSYNC CDATO or CDATI MCLKO CSCLK DIVB = 111b 1 NOTE: DA = Device Address FC Number of Time Slots = NTSL = 01111b (16) TRSEN = 1 Cmd Time Slot = ATSL = 1000b (8) Mode = MODE = 001b (AIC Mode) D14 D13 D12 D2 D1 D0 DA2 Data Bits / Time Slot = BPTSL = 001b (16) Time Slot Length = TSLL = 001b (16) CSYNCL = 0, CSYNCP = 1 CSCLKP = 0 DDLY = 1 CSCLK CSYNC CDATO or CDATI FC DA1 DA0 RW D2 D1 D0 2 3 4 5 6 7 8 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-7. Codec Port Interface Parameters − AIC 54 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.3 Parameter Assignments - I2S Figure 2-8 shows the parameter settings for I2S. I2S only uses two time slots. Time slot 0 is used for left channel audio data and time slot 1 is used for right channel audio data. Secondary communication is not allowed in I2S. The sync line CSYNC is programmed to be logic 0 active for the duration of time slot 0. CSYNC and CDATO are programmed to transition on the falling edge of CSCLK, which means that CDATI will be sampled on the rising edge of CSCLK. DDLY is set to logic 1, and thus transmit data (CDATO) and receive data (CDATI) are both delayed one CSCLK period with respect to the falling edge of CSYNC. The time slot length for both time slots is programmed to be 32 bits. I2S does allow the use of different word size lengths, and a word size length of 24 bits is selected for the example in Figure 2-8. Byte order reversal (BYOR) is not set, so the byte ordering of the data as received is preserved. CSCLK is set to MSCLK/4, which is a common ratio for I2S. For example, if 48 kHz audio sampling is used, CSCLK would be 64 × 48 kHz = 3.072 MHz. MCLK then would be 4 × 3.072 MHz 12.288 MHz, which is a standard master clock frequency used by I2S codecs for 48-kHz audio data. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 55 Submit Documentation Feedback Product Folder Link(s): TAS1020B 0 Time Slot 0 Time Slot 1 Time Slot 0 CSYNC CSCLK CDATO or CADTI DDLY = 1 CSYNCL = 1, CSYNCP = 0 CSCLKP = 1 BYOR = 0 TSL0L = 11b (32 CSCLK Periods) TSLL = 101b (32 CSCLK Periods) BPTSL = 100b (24) NTSL = 00001b (2) MCLKO CSCLK DIVB = 011b 0 L23 L22 L21 L20 L1 L0 0 0 0 0 0 0 R23 R22 R21 R20 0R1 R0 0 0 0 0 0 0 L23 L22 Mode = MODE = 100b or 101b (I2S) TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-8. Codec Port Interface Parameters – I2S 56 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.4 Byte Reversal Ordering For all data transactions managed under DMA control, the TAS1020B provides an option to reverse the ordering of the bytes within a data word as received. Byte order reversal, if selected, applies to both DMA channels. If, for example, one DMA channel is used to output audio to a codec and the second DMA channel is used to retrieve record data from a codec, byte reversal is applied to both audio streams. When re-ordering the bytes within an audio data word, both time slot length (TSLL/TSL0L) and data bits per time slot (BPTSL) must be taken into account. As an example consider Figure 2-9. In Figure 2-9 (a) 20-bit data in a 3-byte word is received either over the USB bus (OUT transaction) or from a codec (IN transaction). The byte order of the data as received is little endian, where the least significant byte is placed in the right-most byte position of the word. If BYOR = 1, byte reversal will be performed to yield an output that is big endian in byte order, where the least significant byte is placed in the left-most byte position of the word. However, in examining the byte-order reversed data in Figure 2-9 (b), it is noted that the two nibbles of the most significant byte are switched to prevent a gap in the serial data when output. The TAS1020B automatically performs this nibble reversal based on BPTSL being one nibble less than the time slot in length. a. Audio Word Received by TAS1020B 24 0 0 0 0 0 B19 B16 B15 B9 B8 B7 B1 B0 b. Received Audio Word After Byte Reversal 24 0 B7 B1 B0 B15 B9 B8 B19 B16 0 0 0 0 Figure 2-9. Byte Reversal Example 2.2.13.2 Audio Codec (AC) '97 1.0 Mode of Operation In AC '97 1.0 mode, the codec port interface can be configured as an AC link serial interface to the AC '97 codec device. Refer to the audio codec '97 specification revision 2.2 for additional information. The AC link serial interface is a time division multiplexed (TDM) slot based serial interface that is used to transfer both audio data and command/status data between the TAS1020B IC and the codec device. NO TAG shows the structure of the codec port interface signals for AC '97 1.0. Table 2-6. Terminal Assignments for Codec Port Interface AC '97 1.0 Mode 2 TERMINAL AC '97 VERSION 1.0 MODE 2 NO. NAME 35 CSYNC SYNC O 37 CSCLK BIT_CLK I 38 CDATO SDATA_OUT O 36 CDATI SDATA_IN I 34 CRESET RESET O 32 CSCHNE NC O In this mode, the codec port interface is configured as a bidirectional full duplex serial interface with a fixed rate of 48 kHz. Each 48-kHz frame is divided into 13 time slots, with the use of each time slot predefined by the audio codec AC '97 specification. Each time slot is 20 serial clock cycles in length except for time slot 0, which is only 16 serial clock cycles. The serial clock, which is referred to as the BIT_CLK for AC '97 modes, is set to 12.288 MHz. Based on the length of each slot, there is a total of 256 serial clock cycles per frame at a frequency of 12.288 MHz. As a result the frame frequency is 48 kHz. For the AC '97 modes, the BIT_CLK is input to the TAS1020B device from the codec. The BIT_CLK is Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 57 Submit Documentation Feedback Product Folder Link(s): TAS1020B MCLKO1 CSYNC CSCLK CDATO CDATI CRESET CSCHNE AC97CLK SYNC BIT_CLK SD_IN SD_OUT CRESET TAS1020B AC’97 IC TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com generated by the codec from the master clock (MCLK) input. The codec MCLK input, which can be generated by the TAS1020B device, must be a frequency of 24.576 MHz. The start of each 48-kHz frame is synchronized to the rising edge of the SYNC signal, which is an output of the TAS1020B device. The SYNC signal is driven high each frame for the duration of slot 0. See Figure 2-10 for details on connecting the TAS1020B to a codec device in this mode. Figure 2-10. Connection of the TAS1020B to an AC '97 Codec The AC link protocol defines slot 0 as a special slot called the tag slot and defines slots 1 through 12 as data slots. Slot 1 and slot 2 are used to transfer command and status information between the TAS1020B device and the codec. Slot 1 and slot 2 of the outgoing serial data stream are defined as the command address and command data slots, respectively. These slots are used for writing to the control registers in the codec. Slot 1 and slot 2 of the incoming serial data stream are defined as the status address and status data slots, respectively. These slots are used for reading from the control registers in the codec. Unused or reserved time slots and unused bit locations within a valid time slot are filled with zeros. Since each data time slot is 20 bits in length, the protocol supports 8-bit, 16-bit, 18-bit, or 20-bit data transfers. 2.2.13.3 Audio Codec (AC) '97 2.0 Mode of Operation The basic serial protocol for the AC '97 2.0 mode is the same as the AC '97 1.0 mode. The AC '97 2.0 mode, however, offers some additional features. In this mode, the TAS1020B provides support for multiple codec devices and also on-demand sampling. Table 2-7. Terminal Assignments for Codec Port Interface AC '97 2.0 Mode 3 TERMINAL AC '97 VERSION 2.0 MODE 3 NO. NAME 35 CSYNC SYNC O 37 CSCLK BIT_CLK I 38 CDATO SDATA_OUT O 36 CDATI SDATA_IN I 34 CRESET RESET O 32 CSCHNE SD_IN2 I The TAS1020B can connect directly to two AC '97 codecs. The interconnect for two codecs is shown in Figure 2-11. As noted in Figure 2-11, the support for two codecs only requires the use of one additional pin—CSCHNE (codec port interface secondary channel enable)—and this additional pin allows record transactions to consist of data from two codecs. The two serial data lines from the two codecs to the TAS1020B are ORed together inside the TAS1020B to form one final serial digital data stream. This means that the data output from each codec must reside in different time slots. This also explains why CSCHNE must be grounded when not used, as a floating input could result in unpredictable behavior and corrupt the serial data coming in on the other input pin, SDATA_IN1. AC '97 mode 2.0 also supports on-demand sampling. On-demand sampling is a codec-to-controller 58 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B Secondary MCLKO CSCHNE CRESET CDATI CDATO CSCLK CSYNC AC97CLK CRESET SDATA_OUT SDATA_IN BIT_CLK SYNC AC97CLK CRESET SDATA_OUT SDATA_IN BIT_CLK SYNC AC ’97 IC TAS1020B AC97 or MC97 Primary Serial Input Data TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 signaling protocol that is used to accommodate audio sampling rates that differ from the 48-kHz AC-link serial frame rate. An example would be streaming 44.1 kHz audio across the AC-link. The signaling protocol is implemented using the data request flags SLOTREQ[0-9] residing in SLOT1[2-11] of slot 1 of the AC '97 input frame. An active request (bit request flag = 0) results in data being sent to the codec on the next AC-link frame. The TAS1020B does not support on-demand sampling when used with two codecs. Only one codec using on-demand sampling can be supported by the TAS1020B. Figure 2-11. Connection of the TAS1020B to Multiple AC '97 Codecs 2.2.13.4 Inter-IC Sound (I2S) Modes of Operation The TAS1020B offers two I2S modes of operation, codec port interface mode 4 and codec port interface mode 5. The difference in the I2S modes is the number of serial data outputs and/or serial data inputs supported. For codec port interface mode 4, there is one serial data output (SDOUT1) and two serial data inputs (SDIN1, SDIN2). Hence, mode 4 can be used to connect the TAS1020B device to a codec with one stereo DAC and two ADCs. For codec port interface mode 5, one serial data output (SDOUT1) and one serial data input (SDIN2) are supported, but these data streams can be completely independent as each is assigned its separate sync pulse and bit clock. Mode 5 then can service applications that require different sampling rates for record and playback. Table 2-8 shows the TAS1020B codec terminal assignments and the respective signal names for each of the I2S modes. Figure 2-8 shows the signal waveforms for I2S. Table 2-8. Terminal Assignments for Codec Port Interface I2S Mode 4 and Mode 5 TERMINAL I2S I2S NO. NAME MODE 4 MODE 5 35 CSYNC LRCK O LRCK1 O 37 CSCLK SCLK O SCLK1 O 38 CDATO SDOUT1 O SDOUT1 O 36 CDATI SDIN1 I SDIN2 I 34 CRESET CRESET O SCLK2 O 32 CSCHNE SDIN2 I LRCK2 O Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 59 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com In all I2S modes, the codec port interface is configured as a bidirectional full duplex serial interface with two time slots per frame. The frame sync signal is the left/right clock (LRCK) signal. Time slot 0 is used for the left channel audio data, and time slot 1 is used for the right channel audio data. Both time slots must be set to 32 serial clock (SCLK) cycles in length giving an SCLK-to-LRCK ratio of 64. The serial clock frequency is based on the audio sample rate. For example, when using an audio sample rate (FS) of 48 kHz, the SCLK frequency must be set to 3.072 MHz (64×FS). (Note that the terms codec frame sync, audio sample rate (FS), and LRCK all refer to the same signal.) The LRCK signal has a 50% duty cycle. The LRCK signal is low for the left channel time slot and is high for the right channel time slot. In addition, the LRCK signal is synchronous to the falling edge of the SCLK. Serial data is shifted out on the falling edge of SCLK and shifted in on the rising edge of SCLK. Both for the left channel and the right channel, there is a one-SCLK cycle delay from the edge of LRCK before the most significant bit of the data is shifted out. For the I2S modes of the codec port interface, there is a 24-bit transmit and 24-bit receive shift register for each SDOUT and SDIN signal, respectively. As a result, the interface can actually support 16-bit, 18-bit, 20-bit or 24-bit transfers. The interface pads the unused bits automatically with zeros. The I2S protocol does not provide for command/status data transfers. Therefore, when using the TAS1020B device with a codec that uses an I2S serial interface for audio data transfers, the TAS1020B I2C serial interface can be used for codec command/status data transfers. 2.2.13.4.1 Mapping DMA Time Slots to Codec Port Interface Time Slots for I2S Modes The I2S serial data format uses two time slots (left channel—slot 0, and right channel—slot 1) for each serial data output or input. Because two serial data streams are input into the TAS1020B in I2S mode 4 operation, and since each input stream has its own unique slot 0 and slot 1 assignments associated with its data, the TAS1020B must contend with two slots arriving during time slot 0 and two slots arriving during time slot 1. Mapping is then required to transpose these multiple time slot occurrences to single, unique slot assignments for the DMA channel. Table 2-9 shows the mapping of the codec port interface time slots for each input to their corresponding DMA time slot assignments. As an example, suppose that codec port interface mode 4 is to be used with one serial data output and two serial data inputs. The DMA channel assigned to support the serial data output must have time slot assignment bits 0 and 1 set to 1. The DMA channel assigned to support the two serial data inputs must have time slot assignment bits 0, 1, 2, and 3 set to 1. Table 2-9. SLOT Assignments for Codec Port Interface I2S Mode 4 CODEC PORT INTERFACE DMA CHANNEL(S) SERIAL DATA TIME SLOT NUMBER TIME SLOT NUMBER LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL SDOUT1 0 1 0 1 SDIN1 0 1 0 2 SDIN2 0 1 1 3 Table 2-10. SLOT Assignments for Codec Port Interface I2S Mode 5 CODEC PORT INTERFACE DMA CHANNEL(S) SERIAL DATA TIME SLOT NUMBER TIME SLOT NUMBER LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL SDOUT1 0 1 0 1 SDIN2 0 1 0 1 60 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.5 AIC Mode of Operation AIC - audio interface circuit - is a standard adopted by Texas Instruments for interfacing digitized analog data to a TI DSP. The bus is specifically tailored to be compatible with the serial ports supplied with most TI DSP offerings. In later DSP offerings, these ports are referred to as McBSP ports. The AIC standard has four serial interface modes - pulse mode, SPI mode 0, SPI mode 1, and frame mode. The TAS1020B only supports the pulse mode of operation. (The pulse mode is so named because of the one CSCLK period duration of the sync signal). Three options exist for the pulse mode - master (frame sync is sourced by the codec), slave (frame sync is sourced by the TAS1020B), and continuous-transfer master (data is transmitted and received continuously, and frame sync is sourced by the codec). The TAS1020B directly supports the master and slave options. The continuous-transfer master mode option does not allow secondary communication. The AIC standard covers this case by specifying the use of a second data stream, synchronous with CSCLK, to directly program the internal registers of the codec. The TAS1020B has no means of outputting such a second data stream. The TAS1020B then can only support the continuous-transfer master mode option by the use of external logic, whereby the CDATO line can be multiplexed between the AIC data terminal and the direct configuration serial input terminal. Such a solution for implementing the continuous-transfer master mode option does introduce the restriction that audio data and control data cannot be transmitted concurrently. The AIC standard provides two options for requesting secondary communication - asserting an active-high logic level on a separate line (FC) or setting the LSB of the 16-bit data word high. The latter option is only available when the audio consists of 15-bit data words. The TAS1020B only supports the FC option. When the codec port interface is set to the AIC mode, the TAS1020B CSCHNE pin (pin 32) sources FC. Figure 2-7 shows the parameter settings for the AIC master or slave mode, and Section 2.2.13.1.2 provides detail on these settings. Table 2-11 shows the TAS1020B codec terminal assignments and the respective signal names for the AIC mode of operation. Table 2-11. Terminal Assignments for Codec Port Interface AIC Mode 1 TERMINAL AIC NO. NAME 35 CSYNC FS O 37 CSCLK SCLK O 38 CDATO DOUT O 36 CDATI DIN I 34 CRESET RESET O 32 CSCHNE FC O 2.2.13.6 Bulk Mode The TAS1020B supports bulk OUT data transactions through the codec port using one of the two available DMA channels, but the codec port needs to be configured in AC '97 or general-purpose mode to support bulk OUT transactions. AC '97 and the general-purpose mode are the only two modes of operation that support bulk OUT transactions, as these are the only two modes that have mechanisms in place to distinguish when valid data is or is not being output. AC '97 uses tag bits to indicate whether or not data is valid in any given time slot. In the general-purpose mode, no sync pulse is output if no valid data is available to be output. (In both AC '97 and the general-purpose mode, CPTBLK must be set to logic 1 if tag bits or the sync pulse, respectively, are to indicate the presence of valid data). See Section 2.2.7.3.3 for more detail on bulk OUT transactions using one of the two DMA channels. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 61 Submit Documentation Feedback Product Folder Link(s): TAS1020B Data Line Stable: Data Valid Change of Data Allowed SDA SCL TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2.2.14 I2C Interface The TAS1020B has a bidirectional two-wire serial interface that can be used to access other ICs. This serial interface is compatible with the I2C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps data transfer rates. The TAS1020B does not support all provisions of theI2C specification. The TAS1020B can only serve as a master device on the I2C bus, but as a master device, the TAS1020B does not support a multimaster bus environment (no bus arbitration), but can recognize wait state insertions on the bus. The I2C interface on the TAS1020B is provided to allow access to I2C slave devices, including EEPROMs and codecs. For example, if the application program code is stored in an EEPROM on the PCB, then the MCU downloads the code from the EEPROM to the TAS1020B on-chip RAM using the I2C interface. Another example is the control of a codec device that uses an I2S interface for audio data transfers and an I2C interface for control register read/write access. 2.2.14.1 Data Transfers The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the TAS1020B is a master only device, and therefore, the SCL signal is an output only. The SDA signal is a bidirectional signal that uses an open-drain output to allow the TAS1020B to be wire-ORed with other devices that use open-drain or open-collector outputs. All read and write data transfers on the serial bus are initiated by the TAS1020B. The TAS1020B is also responsible for generating the clock signal used for all data transfers. The data is transferred on the bus serially one bit at a time. However, the protocol requires that the address and data be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 2-12. As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can only change states while the SCL signal is low. Figure 2-12. Bit Transfer on the I2C Bus The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in Figure 2-13. As shown, the start condition is defined as a high-to-low transition of the SDA signal while the SCL signal is high. Also as shown, the stop condition is defined as a low-to-high transition of the SDA signal while the SCL signal is high. 62 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B SDA SCL S Start Condition P Stop Condition S Start Condition MSB Acknowledge Not Acknowledge 9 Clock Pulse For Acknowledge 1 2 8 Data Output By Slave Device Data Output By TAS1020B SDA SDA } } SCL TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 2-13. I2C START and STOP Conditions When the TAS1020B is the device receiving data information, the TAS1020B acknowledges each byte received by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL period, the slave device must stop driving the SDA signal. If the TAS1020B is unable to receive a byte, the SDA signal is not driven low and is pulled high external to the TAS1020B device. Also, if the TAS1020B has received the last byte of data, it signals an end of transmission to the slave device by issuing a not acknowledge, rather than an acknowledge, following reception of the last byte. A high during the SCL period indicates a not-acknowledge to the slave device. The acknowledge timing is shown in Figure 2-14. Read and write data transfers by the TAS1020B device can be done using single byte or multiple byte data transfers. Therefore, the actual transfer type used depends on the protocol required by the I2C slave device being accessed. Figure 2-14. TAS1020B Acknowledge on the I2C Bus 2.2.14.2 Single Byte Write As shown is Figure 2-15, a single byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be a 0. After receiving the correct I2C device address and the read/write bit, the I2C slave device responds with an acknowledge bit. Next, the TAS1020B transmits the address byte or bytes corresponding to the I2C slave device internal memory address being accessed. After receiving the address byte, the I2C slave device again responds with an acknowledge bit. Next, the TAS1020B device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the I2C slave device again responds with an acknowledge bit. Finally, the TAS1020B device transmits a stop condition to complete the single byte data write transfer. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 63 Submit Documentation Feedback Product Folder Link(s): TAS1020B A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Data Byte SDA D7 D6 D1 D0 ACK Stop Condition Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Last Data Byte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 D6 D1 D0 ACK Start Condition Acknowledge Acknowledge Acknowledge SDA First Data Byte A6 A4 A3 Other Data Bytes A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Data Byte SDA D7 D6 D1 D0 ACK I2C Device Address and Read/Write Bit Repeat Start Condition Not Acknowledge A1 A1 R/W TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-15. Single Byte Write Transfer 2.2.14.3 Multiple Byte Write A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the TAS1020B device to the I2C slave device as shown in Figure 2-16. After receiving each data byte, the I2C slave device responds with an acknowledge bit. Figure 2-16. Multiple Byte Write Transfer 2.2.14.4 Single Byte Read As shown in Figure 2-17, a single byte data read transfer begins with the TAS1020B device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually performed. Initially, a write is performed to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit must be a 0. After receiving the I2C device address and the read/write bit, the I2C slave device responds with an acknowledge bit. Also, after sending the internal memory address byte or bytes, the TAS1020B device transmits another start condition followed by the I2C slave device address and the read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the I2C device address and the read/write bit the I2C slave again responds with an acknowledge bit. Next, the I2C slave device transmits the data byte from the memory address being read. After receiving the data byte, the TAS1020B device transmits a not-acknowledge followed by a stop condition to complete the single byte data read transfer. Figure 2-17. Single Byte Read Transfer 64 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B A6 A0 ACK Acknowledge I2C Device Address and Read/Write Bit A6 A0 R/W ACK A4 A0 ACK R/W D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last Data Byte SDA D7 D6 D1 D0 ACK First Data Byte Repeat Start Condition Not Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Other Data Bytes A7 A6 A7 TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.14.5 Multiple Byte Read A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the I2C slave device to the TAS1020B device as shown in Figure 2-18. Except for the last data byte, the TAS1020B device responds with an acknowledge bit after receiving each data byte. Figure 2-18. Multiple Byte Read Transfer Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 65 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 3 Electrical Specifications 3.1 Absolute Maximum Ratings(1) over operating temperature range (unless otherwise noted) DVDD Supply voltage range −0.5 to 3.6 V VI Input voltage range 3.3-V TTL/LVCMOS −0.5 V to DVDD + 0.5 V Continuous power dissipation See Section 3.2 TOp Operating free air temperature range 0°C to 70°C TStg Storage temperature range (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3.2 Dissipation Ratings PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C POWER RATING ABOVE TA = 25°C POWER RATING TQFP 0.923 W 10.256 mW/°C 0.461 W 3.3 Recommended Operating Conditions MIN NOM MAX UNIT DVDD Digital supply voltage 3 3.3 3.6 V AVDD Analog supply voltage 3 3.3 3.6 V VIH High-level input voltage CMOS inputs 0.7 DVDD V VIL Low-level input voltage CMOS inputs 0 0.2 DVDD V VI Input voltage CMOS inputs 0 DVDD V VO Output voltage CMOS inputs 0 DVDD V 3.4 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage, GPIO port bits P3 [0-7] IOH = - 4 mA DVDD-0.5 V VOL Low-level output voltage, GPIO port bits P3 [0-7] IOL = 4 mA 0.5 V VOH High-level output voltage, GPIO port bits P1 [0-7] IOH = - 8 mA DVDD-0.5 V VOL Low-level output voltage, GPIO port bits P1 [0-7] IOL = 8 mA 0.5 V IOZ High-impedance output current ± 20 μA Pullup disabled VI = VIL - 20 IIL Low-level input current μA Enabled -100 Pullup disabled VI = VIH 20 IIH High-level input current μA Enabled 20 CPU clock 12 MHz 45.9 mA Digital supply voltage DVDD (3.3 V) CPU clock 24 MHz 50.9 IDD Suspend(1) 196 μA Normal 14.7 mA Analog supply voltage AVDD (3.3 V) Suspend 24 nA (1) In this 196 μA measurement, the bulk of suspend current (190 μA) is delivered to the USB cable through PUR pin. The remaining 6 μA is consumed by the device. As described in section 7.2.3 of USB 1.1 specification, When computing suspend current, the current from VBus through the pullup and pulldown resistors must be included. 66 Electrical Specifications Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B tw(L) XINT tr , tf 90% 10% VO(CRS) VOH VOL DM DP TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 3.5 Timing Characteristics 3.6 Clock and Control Signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT Internal 0.75 25 fMCLKO1 Clock frequency, MCLKO1 CL = 50 pF(1) MHz MCLKI 0.625 25 Internal 0.75 25 fMCLKO2 Clock frequency, MCLKO2 CL = 50 pF(1) MHz MCLKI 0.625 25 fMCLKI Clock frequency, MCLKI See (1) 5 25 MHz tw(L) Pulse duration, XINT low CL = 50 pF 0.2 10 μs (1) Worst case duty cycle is 45/55. Figure 3-1. External Interrupt Timing Waveform 3.7 USB Signals When Sourced by TAS1020B over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tr Transition rise time for DP or DM 4 20 ns tf Transition fall time for DP or DM 4 20 ns tRFM Rise/fall time matching (tr / tf) × 100 90% 110% VO(CRS) Voltage output signal crossover 1.3 2 V Figure 3-2. USB Differential Driver Timing Waveform Copyright © 2002–2011, Texas Instruments Incorporated Electrical Specifications 67 Submit Documentation Feedback Product Folder Link(s): TAS1020B tw1(H) tw1(L) tcyc1 tw2(H) tw2(L) tcyc2 BIT_CLK SYNC tsu th BIT_CLK tpd1 SYNC, SD_OUT SD_IN TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 3.8 Codec Port Interface Signals (AC ’97 Modes) TA = 25°C, DVDD = 3.3 V, AVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fBIT_CLK Frequency, BIT_CLK See (1) 12.288 MHz tcyc1 Cycle time, BIT_CLK See (1) 81.4 ns tw1(H) Pulse duration, BIT_CLK high See (1) 36 40.7 45 ns tw1(L) Pulse duration, BIT_CLK low See (1) 36 40.7 45 ns fSYNC Frequency, SYNC CL = 50 pF 48 kHz tcyc2 Cycle time, SYNC CL = 50 pF 20.8 μs tw2(H) Pulse duration, SYNC high CL = 50 pF 1.3 μs tw2(L) Pulse duration, SYNC low CL = 50 pF 19.5 μs tpd1 Propagation delay time, BIT_CLK rising edge to SYNC, SD_OUT CL = 50 pF 15 ns tsu Setup time, SD_IN to BIT_CLK falling edge 10 ns th Hold time, SD_IN from BIT_CLK falling edge 10 ns (1) Worst case duty cycle is 45/55. Figure 3-3. BIT_CLK and SYNC Timing Waveforms Figure 3-4. SYNC, SD_IN, and SD_OUT Timing Waveforms 68 Electrical Specifications Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B tsu th SCLK LRCLK, SD_OUT SD_IN tpd tcyc tsu th CSCLK CSYNC, CDATO, CSCHNE, CRESET CDATI tpd tcyc TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 3.9 Codec Port Interface Signals (I2S Modes) over recommended operating conditions (unless otherwise noted) TEST CONDITIONS MIN MAX UNIT fSCLK Frequency, SCLK CL = 50 pF (32)FS (64)FS MHz tcyc Cycle time, SCLK CL = 50 pF(1) 1/(64)FS 1/(32)FS ns tpd Propagation delay, SCLK falling edge to LRCLK and SDOUT CL = 50 pF 15 ns tsu Setup time, SDIN to SCLK rising edge 10 ns th Hold time, SDIN from SCLK rising edge 10 ns (1) Worst case duty cycle is 45/55. Figure 3-5. I2S Mode Timing Waveforms 3.10 Codec Port Interface Signals (General-Purpose Mode) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT fCSCLK Frequency, CSCLK CL = 50 pF 0.125 25 MHz tcyc Cycle time, CSCLK CL = 50 pF(1) 0.040 8 μs tpd Propagation delay, CSCLK to CSYNC, CDATO, CSCHNE and CRESET CL = 50 pF 15 ns tsu Setup time, CDATI to CSCLK 10 ns th Hold time, CDATI from CSCLK 10 ns (1) The timing waveforms in Figure 3-6 show the CSYNC, CDATO, CSCHNE, and CRESET signals generated with the rising edge of the clock and the CDATI signal sampled with the falling edge of the clock. The edge of the clock used is programmable. However, the timing characteristics are the same regardless of which edge of the clock is used. Figure 3-6. General-Purpose Mode Timing Waveforms Copyright © 2002–2011, Texas Instruments Incorporated Electrical Specifications 69 Submit Documentation Feedback Product Folder Link(s): TAS1020B tw(H) tw(L) tr tf tsu1 tpd1 SCL SDA tsu2 th2 tsu3 tbuf SCL SDA Start Condition Stop Condition SCL 1 2 8 9 SDA OUT SDA IN TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 3.11 I2C Interface Signals over recommended operating conditions (unless otherwise noted) STANDARD FAST MODE PARAMETER MODE UNIT MIN MAX MIN MAX fSCL Frequency, SCL 0 100 0 400 kHz tw(H) Pulse duration, SCL high 4 0.6 μs tw(L) Pulse duration, SCL low 4.7 1.3 μs tr Rise time, SCL and SDA 1000 300 ns tf Fall time, SCL and SDA 300 300 ns tsu1 Setup time, SDA to SCL 250 100 ns tpd1 Propagation delay, SCL to SDA (5-kΩ pullup resistor) 300 500 300 500 ns tbuf Bus free time between stop and start condition 4.7 1.3 μs tsu2 Setup time, SCL to start condition 4.7 0.6 μs th2 Hold time, start condition to SCL 4 0.6 μs tsu3 Setup time, SCL to stop condition 4 0.6 μs CL Load capacitance for each bus line 400 400 pF Figure 3-7. SCL and SDA Timing Waveforms Figure 3-8. Start and Stop Conditions Timing Waveforms Figure 3-9. Acknowledge Timing Waveform 70 Electrical Specifications Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B 24C64 33 28 2 3 4 5 6 7 8 P1.4 P1.3 32 31 30 CDATI CSYNC TEST EXTEN MCLKI PUR DP DM 27 26 29 9 10 11 12 25 1 P1.2 PLLFILO DVSS DVSS TAS1020B P1.5 P1.6 P1.7 CSCHNE 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 PLLFILI XTALI XTALO SCL SDA MCLKO2 MCLKO1 CDATO P1.1 CSCLK P1.0 NC DVDD NC P3.5 P3.4 P3.3 P3.1 P3.0 3.3 VD 3.3 VD 1 μF 3.3 VD 10 k! VCC WP SCL SDA GND A2 3.09 k! 1000 pF 100 pF AGND 3.3 VA 27 pF XTAL 6 MHz 27 pF AGND MCLKO A1 A0 DGND DGND 3.3 VD 2 k! Top Layer Ground Shield Ferrite Bead 9 ! at 100 MHz 20 k! + C1 C5 35 36 34 C3 C2 2 k! C4 Voltage Regulator + 10 μF 16 V C1 0.1 μF C2 0.1 μF DGND C3 0.1 μF C4 0.1 μF 3.3 VD (To TAS1020B Device Only) 1.0 ! 1 μF 16 V + C5 0.1 μF AGND 3.3 VA (To TAS1020B Device Only) 3.3 V DGND 1.0 ! CRESET MRESET RSTO P3.2/XINT RESET VREN DVDD AVDD DVDD DVSS AVSS USB_CONN 27.4 W 27.4 W 15 kW 1.5 kW PN2222A (see Note E) Data– Data+ VCC GND VCC TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 4 Application Information A. If MCLKI and CSCHNE are not used, they must be connected to DGND. B. Capacitors C1, C2, C3, C4, and C5 are as shown to indicate they must be mounted as close to the pins as possible. C. NC on pins 20 and 22 means they must be left unconnected when running in normal mode. D. Crystal load capacitors are shown as 27 pF, but recommendations of crystal manufactures should be followed. E. Q1 and associated circuitry is required for USB back-voltage certification test. Figure 4-1. Typical TAS1020B Device Connections Copyright © 2002–2011, Texas Instruments Incorporated Application Information 71 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 5 8K ROM The 8K ROM is mask-programmed as part of the TAS1020B manufacturing process. The ROM program provides the boot behavior as discussed in Section 2.2.2. It also provides support functions for the user's application. Source for the ROM image is provided in the TAS1020B Firmware Development Kit (http://focus.ti.com/docs/toolsw/folders/print/tas1020fdk.html). 5.1 ROM Errata It is not possible for an application that uses the ROM support functions to stall an invalid control transaction that has a data stage. 72 8K ROM Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6 MCU Memory and Memory-Mapped Registers This section describes the TAS1020B MCU memory configurations and operation. In general, the MCU memory operation is the same as the industry standard 8052 MCU. 6.1 MCU Memory Space The TAS1020B MCU memory is organized into three individual spaces: program memory, external data memory, and internal data memory. All memory resources reside within the TAS1020B; the terms internal and external refer to memory resources internal to and external to the MCU core residing in the TAS1020B. The total address range for the program memory and the external data memory spaces is 64K bytes each. The total address range for the internal data memory is 256 bytes. The actual mapping of physical memory resources into these three individual spaces is dependent on which operating mode is active, boot loader mode or normal mode. The operating mode is determined by the setting of the SDW bit in the MCU memory configuration register. At power turnon, or after a master reset, the SDW bit is reset and the boot loader mode is active. In this mode, and 8K ROM resource within the TAS1020B is mapped to program space beginning at address 0000h. This same 8K ROM is also mapped to program space beginning at address 8000h. The TAS1020B uses the 8K boot ROM as the program memory when in the boot loader mode. The boot ROM program code downloads the application program code from a nonvolatile memory (EEPROM) on the peripheral PCB, and writes the code to a 6K RAM resource internal to the TAS1020B. In the boot loader mode, this 6K RAM resource is mapped to the external data memory space starting at address 0000h. (If a valid EEPROM resource is not available, the TAS1020B initializes in the DFU program mode and requires a download of application code to RAM—see Section 2.2.2.2). After downloading the application program code to the 6K RAM resource, the boot ROM enables the normal operating mode by setting the ROM disable (SDW) bit to enable program code execution from the 6K RAM instead of the boot ROM. In the normal operating mode, the boot ROM is still mapped to program memory space starting at address 8000h, but the 6K RAM resource is now mapped to program memory space beginning at address 0000h. Also, in the normal operating mode, the RAM resource becomes a read-only memory resource that cannot be written to. Refer to Figure 6-1 and Figure 6-2 for details. In the normal operating mode, the external data memory space contains the data buffers for the USB endpoints, the configuration blocks for the USB endpoints, the setup data packet buffer for the USB control endpoint, and memory-mapped registers. The data buffers for the USB endpoints, the configuration blocks for the USB endpoints and the setup data packet buffer for the USB control endpoints are all implemented in RAM, and this RAM resource is separate from the 6K RAM resource used to house the application code. The memory-mapped registers used for control and status registers are implemented in hardware with flip-flops. The data buffers for the USB endpoints total 1304 bytes, the configuration blocks for the USB endpoints total 128 bytes, the setup packet buffer for the USB control endpoint is 8 bytes, and the memory-mapped-register space is 80 bytes. The total external data memory space used for these blocks of memory then is 1520 bytes. 6.2 Internal Data Memory The internal data memory space is a total of 256 bytes of RAM, which includes the 128 bytes of special function registers (SFR) space. The internal data memory space is mapped in accordance with the industry standard 8052 MCU. The internal data memory space is mapped from 00h to FFh with the SFRs mapped from 80h to FFh. The lower 128 bytes are accessible with both direct and indirect addressing. However, the upper 128 bytes, which is the SFR space, is only accessible with direct addressing. Note that the internal data memory space is separate and distinct from the external data memory space, and although both spaces begin at address 0000h, there is no overlap. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 73 Submit Documentation Feedback Product Folder Link(s): TAS1020B Program Memory FFFFh 24K − Reserved A000h 9FFFh Boot ROM (8K) 24K − Reserved 2000h 1FFFh Boot ROM (8K) (Boot loader and library 0000h of USB functions) External Data Memory FFFFh Memory Mapped Registers (80 Bytes) FFB0h FFAFh USB End-Point Configuration Blocks and Buffer Space (1440 Bytes) FA10h FA0Fh 58,000 Bytes − Reserved 1780h 177Fh Code RAM (6016 Bytes) (Read/Write) (Loaded from EEPROM 0000h by boot loader) 8000h 7FFFh TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 6-1. Boot Loader Mode Memory Map 74 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B Program Memory FFFFh 24K − Reserved A000h 9FFFh Boot ROM (8K) 26752 Bytes 0000h External Data Memory FFFFh Memory Mapped Registers (80 Bytes) FFB0h FFAFh USB End-Point Configuration Blocks and Buffer Space (1440 Bytes) FA10h FA0Fh 64016 Bytes − Reserved 1780h 177Fh Code RAM (6016 Bytes) 0000h 8000h 7FFFh (Read/Write) TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 6-2. Normal Operating Mode Memory Map 6.3 External MCU Mode Memory Space When using an external MCU for firmware development, only the USB configuration blocks, the USB buffer space, and the memory-mapped registers are accessible by the external MCU. See Section 6.4 for details. In this mode, only address lines A0 to A10 are input to the TAS1020B device from the external MCU. Therefore, the USB buffer space and the memory-mapped registers in the external data memory space are not fully decoded since all sixteen address lines are not available. Hence, the USB buffer space and the memory-mapped registers are actually accessible at any 2K boundary within the total 64K external data memory space of the external MCU. As a result, when using the TAS1020B in the external MCU mode, nothing can be mapped to the external data memory space of the external MCU except the USB buffer space and the memory-mapped registers of the TAS1020B device. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 75 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4 USB Endpoint Configuration Blocks and Data Buffer Space 6.4.1 USB Endpoint Configuration Blocks The USB endpoint configuration space contains 16 8-byte blocks that define configuration, buffer location, buffer size, and data count for the 16 (8 input and 8 output) USB endpoints. The MCU, UBM, and DMA all have access to these configuration blocks. Each of the 16 endpoints in the TAS1020B can be configured as a USB pipe endpoint by initializing the block configuration register assigned to each endpoint. The location of the endpoint X and Y data buffers for each endpoint is set by the value programmed into the X and Y buffer base address registers. Base addresses are octet (8-byte) aligned. The size of the X and Y buffers is set by initializing the buffer size register. The size of the X and Y buffers must be greater than or equal to the USB packet size associated with the endpoint. For Isochronous endpoints, the buffer size defines the size of the single circular buffer. For IN transactions, the X and Y data count registers assigned to each endpoint are set by the USB buffer manager (UBM) to register the size of the new data packet just received. For OUT transactions, the X and Y data count registers assigned to each endpoint are set by the DMA logic or the MCU to register the size of the data packet to be output. For control, interrupt, and bulk transactions, the data count is the number of samples per transaction. 6.4.2 Data Buffer Space The endpoint data buffer space (1304 bytes) provides rate buffering between the data traffic on the USB bus and data traffic to and from the codecs attached to the TAS1020B. Buffers are defined in this space by base address pointers and size descriptors in the USB endpoint configuration blocks. The MCU also has access to this space. In order to conserve RAM memory resources on the TAS1020B, several USB-specific routines have been included in the firmware resident in the on-chip ROM. These ROM support functions are detailed in Section 2.2.2.7. To provide temporary variable storage for these ROM support functions, locations FA10h through FA63h (84 bytes) of the 1304 bytes of data buffer space are reserved for use by the ROM support functions. This then leaves 1220 bytes for the endpoint buffer memories, which service applications up to 6 channels, 48 kHz sampling rate with 16 bits per sample or 4 channels, 48-kHz sampling rate with 24 bits per sample. (If the ROM support functions are not used, the entire block of 1304 bytes can be assigned to endpoint buffer memories.) The values entered into the X and Y buffer base address registers are offset addresses. The lower memory address (or Base address) of a given X (Y) buffer is determined by adding the value in the base address register (multiplied by 8) to the base address of the block of memory assigned to the X and Y buffers. For the TAS1020B, this base address is FA10h. However, the base address of the TUSB3200 members of the family of USB streaming audio controllers, of which the TAS1020B is also a member, is F800h. To maintain software compatibility between family members, the value entered into the base address register for the TAS1020B (as well as the other family members) must be the offset from the base address F800h. For example, assume the X buffer for IN endpoint 3 is to be established starting at address FA60h. For the TAS1020B, the offset of this address from the FA10h base address of the block of memory assigned to the X and Y buffers is 50h. Nevertheless, the value entered into the X buffer base address for IN endpoint 3 must be 4Ch, because F800h + 8 × 4Ch = FA60h. 76 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B External Data Memory Memory Mapped Registers (80 Bytes) Endpoint Configuration Blocks (128 Bytes) Setup Data Packet Buffer (8 Bytes) (see Note A) Endpoint Data Buffers (1220 Bytes) FFFFh FFB0h FFAFh FF30h FF2Fh FF28h FF27h FA10h DMA Access DMA Access MCU Access UBM Access FA64h FA63h ROM Support (84 Bytes) TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 A. See Section 6.4.5. Figure 6-3. USB Endpoint Configuration Blocks and Buffer Space Memory Map Table 6-1. USB Endpoint Configuration Blocks Address Map ADDRESS MNEMONIC NAME FFAFh OEPDCNTY0 OUT endpoint 0 - Y buffer data count byte FFAEh Reserved Reserved for future use FFADh OEPBBAY0 OUT endpoint 0 - Y buffer base address byte FFACh Reserved Reserved for future use FFABh OEPDCNTX0 OUT endpoint 0 - X buffer data count byte FFAAh OEPBSIZ0 OUT endpoint 0 - X and Y buffer size byte FFA9h OEPBBAX0 OUT endpoint 0 - X buffer base address byte FFA8h OEPCNF0 OUT endpoint 0 - configuration byte FFA7h OEPDCNTY1 OUT endpoint 1 - Y buffer data count byte FFA6h Reserved Reserved for future use FFA5h OEPBBAY1 OUT endpoint 1 - Y buffer base address byte FFA4h Reserved Reserved for future use FFA3h OEPDCNTX1 OUT endpoint 1 - X buffer data count byte FFA2h OEPBSIZ1 OUT endpoint 1 - X and Y buffer size byte FFA1h OEPBBAX1 OUT endpoint 1 - X buffer base address byte FFA0h OEPCNF1 OUT endpoint 1 - configuration byte FF9Fh OEPDCNTY2 OUT endpoint 2 - Y buffer data count byte FF9Eh Reserved Reserved for future use FF9Dh OEPBBAY2 OUT endpoint 2 - Y buffer base address byte FF9Ch Reserved Reserved for future use FF9Bh OEPDCNTX2 OUT endpoint 2 - X buffer data count byte FF9Ah OEPBSIZ2 OUT endpoint 2 - X and Y buffer size byte FF99h OEPBBAX2 OUT endpoint 2 - X buffer base address byte FF98h OEPCNF2 OUT endpoint 2 - configuration byte FF97h OEPDCNTY3 OUT endpoint 3 - Y buffer data count byte Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 77 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 6-1. USB Endpoint Configuration Blocks Address Map (continued) ADDRESS MNEMONIC NAME FF96h Reserved Reserved for future use FF95h OEPBBAY3 OUT endpoint 3 - Y buffer base address byte FF94h Reserved Reserved for future use FF93h OEPDCNTX3 OUT endpoint 3 - X buffer data count byte FF92h OEPBSIZ3 OUT endpoint 3 - X and Y buffer size byte FF91h OEPBBAX3 OUT endpoint 3 - X buffer base address byte FF90h OEPCNF3 OUT endpoint 3 - configuration byte FF8Fh OEPDCNTY4 OUT endpoint 4 - Y buffer data count byte FF8Eh Reserved Reserved for future use FF8Dh OEPBBAY4 OUT endpoint 4 - Y buffer base address byte FF8Ch Reserved Reserved for future use FF8Bh OEPDCNTX4 OUT endpoint 4 - X buffer data count byte FF8Ah OEPBSIZ4 OUT endpoint 4 - X and Y buffer size byte FF89h OEPBBAX4 OUT endpoint 4 - X buffer base address byte FF88h OEPCNF4 OUT endpoint 4 - configuration byte FF87h OEPDCNTY5 OUT endpoint 5 - Y buffer data count byte FF86h Reserved Reserved for future use FF85h OEPBBAY5 OUT endpoint 5 - Y buffer base address byte FF84h Reserved Reserved for future use FF83h OEPDCNTX5 OUT endpoint 5 - X buffer data count byte FF82h OEPBSIZ5 OUT endpoint 5 - X and Y buffer size byte FF81h OEPBBAX5 OUT endpoint 5 - X Buffer Base Address Byte FF80h OEPCNF5 OUT endpoint 5 - configuration byte FF7Fh OEPDCNTY6 OUT endpoint 6 - Y buffer data count byte FF7Eh Reserved Reserved for future use FF7Dh OEPBBAY6 OUT endpoint 6 - Y buffer base address byte FF7Ch Reserved Reserved for future use FF7Bh OEPDCNTX6 OUT endpoint 6 - X buffer data count byte FF7Ah OEPBSIZ6 OUT endpoint 6 - X and Y buffer size byte FF79h OEPBBAX6 OUT endpoint 6 - X buffer base address byte FF78h OEPCNF6 OUT endpoint 6 - configuration byte FF77h OEPDCNTY7 OUT endpoint 7 - Y buffer data count byte FF76h Reserved Reserved for future use FF75h OEPBBAY7 OUT endpoint 7 - Y buffer base address byte FF74h Reserved Reserved for future use FF73h OEPDCNTX7 OUT endpoint 7 - X buffer data count byte FF72h OEPBSIZ7 OUT endpoint 7 - X and Y buffer size byte FF71h OEPBBAX7 OUT endpoint 7 - X buffer base address byte FF70h OEPCNF7 OUT endpoint 7 - configuration byte FF6Fh IEPDCNTY0 IN endpoint 0 - Y buffer data count byte FF6Eh Reserved Reserved for future use FF6Dh IEPBBAY0 IN endpoint 0 - Y buffer base address byte FF6Ch Reserved Reserved for future use FF6Bh IEPDCNTX0 IN endpoint 0 - X buffer data count byte FF6Ah IEPBSIZ0 IN endpoint 0 - X and Y buffer size byte FF69h IEPBBAX0 IN endpoint 0 - X buffer base address byte FF68h IEPCNF0 IN endpoint 0 - configuration byte 78 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Table 6-1. USB Endpoint Configuration Blocks Address Map (continued) ADDRESS MNEMONIC NAME FF67h IEPDCNTY1 IN endpoint 1 - Y buffer data count byte FF66h Reserved Reserved for future use FF65h IEPBBAY1 IN endpoint 1 - Y buffer base address byte FF64h Reserved Reserved for future use FF63h IEPDCNTX1 IN endpoint 1 - X buffer data count byte FF62h IEPBSIZ1 IN endpoint 1 - X and Y buffer size byte FF61h IEPBBAX1 IN endpoint 1 - X buffer base address byte FF60h IEPCNF1 IN endpoint 1 - configuration byte FF5Fh IEPDCNTY2 IN endpoint 2 - Y buffer data count byte FF5Eh Reserved Reserved for future use FF5Dh IEPBBAY2 IN endpoint 2 - Y buffer base address byte FF5Ch Reserved Reserved for future use FF5Bh IEPDCNTX2 IN endpoint 2 - X buffer data count byte FF5Ah IEPBSIZ2 IN endpoint 2 - X and Y buffer size byte FF59h IEPBBAX2 IN endpoint 2 - X buffer base address byte FF58h IEPCNF2 IN endpoint 2 - configuration byte FF57h IEPDCNTY3 IN endpoint 3 - Y buffer data count byte FF56h Reserved Reserved for future use FF55h IEPBBAY3 IN endpoint 3 - Y buffer base address byte FF54h Reserved Reserved for future use FF53h IEPDCNTX3 IN endpoint 3 - X buffer data count byte FF52h IEPBSIZ3 IN endpoint 3 - X and Y buffer size byte FF51h IEPBBAX3 IN endpoint 3 - X buffer base address byte FF50h IEPCNF3 IN endpoint 3 - configuration byte FF4Fh IEPDCNTY4 IN endpoint 4 - Y buffer data count byte FF4Eh Reserved Reserved for future use FF4Dh IEPBBAY4 IN endpoint 4 - Y buffer base address byte FF4Ch Reserved Reserved for future use FF4Bh IEPDCNTX4 IN endpoint 4 - X buffer data count byte FF4Ah IEPBSIZ4 IN endpoint 4 - X and Y buffer size byte FF49h IEPBBAX4 IN endpoint 4 - X buffer base address byte FF48h IEPCNF4 IN endpoint 4 - configuration byte FF47h IEPDCNTY5 IN endpoint 5 - Y buffer data count byte FF46h Reserved Reserved for future use FF45h IEPBBAY5 IN endpoint 5 - Y buffer base address byte FF44h Reserved Reserved for future use FF43h IEPDCNTX5 IN endpoint 5 - X buffer data count byte FF42h IEPBSIZ5 IN endpoint 5 - X and Y buffer size byte FF41h IEPBBAX5 IN endpoint 5 - X buffer base address byte FF40h IEPCNF5 IN endpoint 5 - configuration byte FF3Fh IEPDCNTY6 IN endpoint 6 - Y buffer data count byte FF3Eh Reserved Reserved for future use FF3Dh IEPBBAY6 IN endpoint 6 - Y buffer base address byte FF3Ch Reserved Reserved for future use FF3Bh IEPDCNTX6 IN endpoint 6 - X buffer data count byte FF3Ah IEPBSIZ6 IN endpoint 6 - X and Y buffer size byte FF39h IEPBBAX6 IN endpoint 6 - X buffer base address byte Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 79 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 6-1. USB Endpoint Configuration Blocks Address Map (continued) ADDRESS MNEMONIC NAME FF38h IEPCNF6 IN endpoint 6 - configuration byte FF37h IEPDCNTY7 IN endpoint 7 - Y buffer data count byte FF36h Reserved Reserved for future use FF35h IEPBBAY7 IN endpoint 7 - Y buffer base address byte FF34h Reserved Reserved for future use FF33h IEPDCNTX7 IN endpoint 7 - X buffer data count byte FF32h IEPBSIZ7 IN endpoint 7 - X and Y buffer size byte FF31h IEPBBAX7 IN endpoint 7 - X buffer base address byte FF30h IEPCNF7 IN endpoint 7 - configuration byte 6.4.3 USB OUT Endpoint Configuration Bytes This section describes the individual bytes in the USB endpoint configuration blocks for the OUT endpoints. A set of 8 bytes is used for the control and operation of each USB OUT endpoint. In addition to the USB control endpoint, the TAS1020B supports up to a total of seven OUT endpoints. 6.4.3.1 USB OUT Endpoint - Y Buffer Data Count Byte (OEPDCNTYx) The USB OUT endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of data received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB OUT transaction to this endpoint to indicate that the USB endpoint Y buffer contains a valid data packet and that the Y buffer data count value is valid. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the host PC. 7 NACK No acknowledge Also for control, interrupt, and bulk endpoints to enable this endpoint to receive another data packet from the host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to receiving the next data packet. However, the MCU or DMA must clear this bit before reading the data packet from the buffer. The Y buffer data count value is set by the UBM when a new data packet is written to the Y buffer for the OUT endpoint. The 7-bit value is set to the number of bytes in the data packet for control, interrupt or bulk endpoint transfers and is set to the number of 6:0 DCNTY(6:0) Y Buffer data count samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. The data count value is read by the MCU or DMA to obtain the data packet size. 6.4.3.2 USB OUT Endpoint - Y Buffer Base Address Byte (OEPBBAYx) The USB OUT endpoint Y buffer base address byte contains the 8-bit value used to specify the base memory location for the Y data buffer for a particular USB OUT endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The Y buffer base address value is set by the MCU to program the base address 7:0 BBAY(10:3) Y Buffer base address location in memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. 80 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.4.3.3 USB OUT Endpoint - X Buffer Data Count Byte (OEPDCNTXx) The USB OUT endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB OUT transaction to this endpoint to indicate that the USB endpoint X buffer contains a valid data packet and that the X buffer data count value is valid. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the host PC. 7 NACK No acknowledge Also for control, interrupt, and bulk endpoints to enable this endpoint to receive another data packet from the host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to receiving the next data packet. However, the MCU or DMA must clear this bit before reading the data packet from the buffer. The X buffer data count value is set by the UBM when a new data packet is written to the X buffer for the OUT endpoint. The 7-bit value is set to the number of bytes in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of 6:0 DCNTX(6:0) X Buffer data count samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. The data count value is read by the MCU or DMA to obtain the data packet size. 6.4.3.4 USB OUT Endpoint - X and Y Buffer Size Byte (OEPBSIZx) The USB OUT endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two data buffers to be used for this endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the MCU to program the size of the X and Y data packet buffers. Both buffers are 7:0 BSIZ(7:0) Buffer size programmed to the same size based on this value. This value is in 8-byte units. For example, a value of 18h results in the size of the X and Y buffers each being set to 192 bytes. For isochronous transactions, the buffer size sets the size of the single circular buffer. 6.4.3.5 USB OUT Endpoint - X Buffer Base Address Byte (OEPBBAXx) The USB OUT endpoint X buffer base address byte contains the 8-bit value used to specify the base memory location for the X data buffer for a particular USB OUT endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The X buffer base address value is set by the MCU to program the base address 7:0 BBAX(10:3) X Buffer base address location in memory to be used for the X data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 81 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4.3.6 USB OUT Endpoint - Configuration Byte (OEPCNFx) The USB OUT endpoint configuration byte contains the various bits used to configure and control the endpoint. Note that the bits in this byte take on different functionality based on the type of endpoint defined. The control, interrupt, and bulk endpoints function differently than the isochronous endpoints. 6.4.3.6.1 USB OUT Endpoint Configuration Byte Settings—Control, interrupt, or Bulk Transactions This section defines the functionality of the bits in the USB OUT endpoint configuration byte for control, interrupt, and bulk endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPEN ISO TOGGLE DBUF STALL OEPIE — — Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 OEPEN Endpoint enable The endpoint enable bit is set to 1 by the MCU to enable the OUT endpoint. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular OUT endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU to use a particular OUT endpoint for control, interrupt, or bulk transactions. The toggle bit is controlled by the UBM and is toggled at the end of a successful out 5 TOGGLE Toggle data stage transaction if a valid data packet is received and the data packet PID matches the expected PID. The double buffer mode bit is set to 1 by the MCU to enable the use of both the X and 4 DBUF Double buffer mode Y data packet buffers for USB transactions to a particular OUT endpoint. This bit must be cleared to a 0 by the MCU to use the single buffer mode. In the single buffer mode, only the X buffer is used. The stall bit is set to 1 by the MCU to stall endpoint transactions. When this bit is set, the hardware automatically returns a stall handshake to the host PC for any transaction received for the endpoint. An exception is the control endpoint setup stage transaction, which must always received. This requirement allows a 3 STALL Stall Clear_Feature_Stall request to be received from the host PC. Control endpoint data and status stage transactions however can be stalled. The stall bit is cleared to a 0 by the MCU if a Clear_Feature_Stall request or a USB reset is received from the host PC. For a control write transaction, if the amount of data received is greater than expected, the UBM sets the stall bit to a 1 to stall the endpoint. When the stall bit is set to a 1 by the UBM, the USB OUT endpoint 0 interrupt is generated. 2 OEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the OUT endpoint interrupt. See Section 6.5.7.1 for details on the OUT endpoint interrupts. 1:0 — Reserved Reserved for future use 82 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.4.3.6.2 USB OUT Endpoint Configuration Byte Settings—Isochronous Transactions This section defines the functionality of the bits in the USB OUT endpoint configuration byte for isochronous endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 OEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the OUT endpoint. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular OUT endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU for a particular OUT endpoint to be used for control, interrupt, or bulk transactions. The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has 5 OVF Overflow occurred. This bit is used for diagnostic purposes only and is not used for normal operation. This bit can only be cleared to a 0 by the MCU. The bytes per sample bits are used to define the number of bytes per isochronous data sample. In other words, the total number of bytes in an entire audio codec frame. 4:0 BPS(4:0) Bytes per sample For example, a PCM 16-bit stereo audio data sample consists of 4 bytes. There are two bytes of left channel data and two bytes of right channel data. For a four channel system using 16-bit data, the total number of bytes is 8, which is the isochronous data sample size.00h = 1 byte, 01h = 2 bytes, …, 1Fh = 32 bytes 6.4.4 USB IN Endpoint Configuration Bytes This section describes the individual bytes in the USB endpoint configuration blocks for the IN endpoints. A set of 8 bytes is used for the control and operation of each USB IN endpoint. In addition to the USB control endpoint, the TAS1020B supports up to a total of seven IN endpoints. 6.4.4.1 USB IN Endpoint - Y Buffer Data Count Byte (IEPDCNTYx) The USB IN endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of data to be transmitted in a data packet to the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB IN transaction to this endpoint to indicate that the USB endpoint Y buffer is empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the 7 NACK No acknowledge host PC. Also for control, interrupt, and bulk endpoints to enable this endpoint to transmit another data packet to the Host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to sending the next data packet. However, the MCU or DMA must clear this bit after writing a data packet to the buffer. The Y buffer data count value is set by the MCU or DMA when a new data packet is written to the Y buffer for the IN endpoint. The 7-bit value is set to the number of bytes 6:0 DCNTY(6:0) Y Buffer data count in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 83 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4.4.2 USB IN Endpoint - Y Buffer Base Address Byte (IEPBBAYx) The USB IN endpoint Y buffer base address byte contains the 8-bit value used to specify the base memory location for the Y data buffer for a particular USB IN endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The Y buffer base address value is set by the MCU to program the base address 7:0 BBAY(10:3) Y Buffer base address location in memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. 6.4.4.3 USB IN Endpoint - X Buffer Data Count Byte (IEPDCNTXx) The USB IN endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB IN transaction to this endpoint to indicate that the USB endpoint X buffer is empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the 7 NACK No acknowledge host PC. Also for control, interrupt, and bulk endpoints to enable this endpoint to transmit another data packet to the host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to sending the next data packet. However, the MCU or DMA must clear this bit after writing a data packet to the buffer. The X buffer data count value is set by the MCU or DMA when a new data packet is written to the X buffer for the IN endpoint. The 7-bit value is set to the number of bytes 6:0 DCNTX(6:0) X Buffer data count in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. 6.4.4.4 USB IN Endpoint - X and Y Buffer Size Byte (IEPBSIZx) The USB IN endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two data buffers to be used for this endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the MCU to program the size of the X and Y data packet buffers. Both buffers are 7 BSIZ(7:0) Buffer size programmed to the same size based on this value. This value should be in 8 byte units. For example, a value of 18h results in the size of the X and Y buffers each being set to 192 bytes. For isochronous transactions, the buffer size sets the size of the single circular buffer. 84 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.4.4.5 USB IN Endpoint - X Buffer Base Address Byte (IEPBBAXx) The USB IN endpoint X buffer base address byte contains the 8-bit value used to specify the base memory location for the X data buffer for a particular USB IN endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The X buffer base address value is set by the MCU to program the base address 7:0 BBAX(10:3) X Buffer base address location in memory to be used for the X data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. 6.4.4.6 USB IN Endpoint - Configuration Byte (IEPCNFx) The USB IN endpoint configuration byte contains the various bits used to configure and control the endpoint. Note that the bits in this byte take on different functionality based on the type of endpoint defined. Basically, the control, interrupt and bulk endpoints function differently than the isochronous endpoints. 6.4.4.6.1 USB IN Endpoint Configuration Byte Settings - Control, Interrupt or Bulk Transactions This section defines the functionality of the bits in the USB IN endpoint configuration byte for control, interrupt, and bulk endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPEN ISO TOGGLE DBUF STALL IEPIE — — Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the IN endpoint. This bit does not affect the reception of the control endpoint setup stage transaction. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular IN endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU to use a particular IN endpoint for control, interrupt, or bulk transactions. The toggle bit is controlled by the UBM and is toggled at the end of a successful in 5 TOGGLE Toggle data stage transaction if a valid data packet is transmitted. If this bit is a 0, a DATA0 PID is transmitted in the data packet to the host PC. If this bit is a 1, a DATA1 PID is transmitted in the data packet. The double buffer mode bit is set to a 1 by the MCU to enable the use of both the X 4 DBUF Double buffer mode and Y data packet buffers for USB transactions to a particular IN endpoint. This bit must be cleared to a 0 by the MCU to use the single buffer mode. In the single buffer mode, only the X buffer is used. The stall bit is set to a 1 by the MCU to stall endpoint transactions. When this bit is 3 STALL Stall set, the hardware automatically returns a stall handshake to the host PC for any transaction received for the endpoint. 2 IEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the IN endpoint interrupt. See Section 6.5.7.2 for details on the IN endpoint interrupts. 1:0 — Reserved Reserved for future use. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 85 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4.4.6.2 USB IN Endpoint Configuration Byte Settings - Isochronous Transactions This section defines the functionality of the bits in the USB IN endpoint configuration byte for isochronous endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the IN endpoint. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular IN endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU for a particular IN endpoint to be used for control, interrupt, or bulk transactions. The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has 5 OVF Overflow occurred. This bit is used for diagnostic purposes only and is not used for normal operation. This bit can only be cleared to a 0 by the MCU. The bytes per sample bits are used to define the number of bytes per isochronous data sample. In other words, the total number of bytes in an entire audio codec frame. 4:0 BPS(4:0) Bytes per sample For example, a PCM 16-bit stereo audio data sample consists of 4 bytes. There are two bytes of left channel data and two bytes of right channel data. For a four channel system using 16-bit data, the total number of bytes is 8, which is the isochronous data sample size. 00h = 1 byte, 01h = 2 bytes, …, 1Fh = 32 bytes 6.4.5 USB Control Endpoint Setup Stage Data Packet Buffer The USB control endpoint setup stage data packet buffer is the buffer space used to store the 8-byte data packet received from the host PC during a control endpoint transfer setup stage transaction. Refer to Chapter 9 of the USB Specification for details on the data packet. Table 6-2. USB Control Endpoint Setup Data Packet Buffer Address Map ADDRESS NAME FF2Fh wLength - Number of bytes to transfer in the data stage FF2Eh wLength - Number of bytes to transfer in the data stage FF2Dh wIndex - Index or offset value FF2Ch wIndex - Index or offset value FF2Bh wValue - Value of a parameter specific to the request FF2Ah wValue - Value of a parameter specific to the request FF29h bRequest - Specifies the particular request FF28h bmRequestType - Identifies the characteristics of the request 86 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5 Memory-Mapped Registers The TAS1020B device provides a set of control and status registers to be used by the MCU to control the overall operation of the device. This section describes the memory-mapped registers. Table 6-3. Memory-Mapped Registers Address Map ADDRESS MNEMONIC NAME SECTION FFFFh USBFADR USB function address register Section 6.5.1.1 FFFEh USBSTA USB status register Section 6.5.1.2 FFFDh USBIMSK USB interrupt mask register Section 6.5.1.3 FFFCh USBCTL USB control register Section 6.5.1.4 FFFBh USBFNL USB frame number register (low-byte) Section 6.5.1.5 FFFAh USBFNH USB frame number register (high-byte) Section 6.5.1.6 FFF9h ACG2FRQ0 Adaptive clock generator2 frequency register (Byte 0) Section 6.5.3.6 FFF8h ACG2FRQ1 Adaptive clock generator2 frequency register (Byte 1) Section 6.5.3.7 FFF7h ACG2FRQ2 Adaptive clock generator2 frequency register (Byte 2) Section 6.5.3.8 FFF6h ACG2DCTL Adaptive clock generator2 divider control register Section 6.5.3.9 FFF5h Reserved Reserved for future use FFF4h DMABCNT1H DMA buffer content register (high-byte) (channel 1) Section 6.5.2.5 FFF3h DMABCNT1L DMA buffer content register (low-byte) (channel 1) Section 6.5.2.4 FFF2h DMABPCT0 DMA bulk packet count register (low-byte) Section 6.5.2.6 FFF1h DMABPCT1 DMA bulk packet count register (high-byte) Section 6.5.2.7 FFF0h DMATSL1 DMA time slot assignment register (low-byte) (channel 1) Section 6.5.2.1 FFEFh DMATSH1 DMA time slot assignment register (high-byte) (channel 1) Section 6.5.2.1 FFEEh DMACTL1 DMA control register (channel 1) Section 6.5.2.3 FFEDh Reserved Reserved for future use FFECh DMABCNT0H DMA current buffer content register (high-byte) (channel 0) Section 6.5.2.5 FFEBh DMABCNT0L DMA current buffer content register (low-byte) (channel 0) Section 6.5.2.4 FFEAh DMATSL0 DMA time slot assignment register (low-byte) (channel 0) Section 6.5.2.1 FFE9h DMATSH0 DMA time slot assignment register (high-byte) (channel 0) Section 6.5.2.2 FFE8h DMACTL0 DMA control register (channel 0) Section 6.5.2.3 FFE7h ACG1FRQ0 Adaptive clock generator1 frequency register (byte 0) Section 6.5.3.1 FFE6h ACG1FRQ1 Adaptive clock generator1 frequency register (byte 1) Section 6.5.3.2 FFE5h ACG1FRQ2 Adaptive clock generator1 frequency register (byte 2) Section 6.5.3.3 FFE4h ACGCAPL Adaptive clock generator1 MCLK capture register (low byte) Section 6.5.3.4 FFE3h ACGCAPH Adaptive clock generator1 MCLK capture register (high byte) Section 6.5.3.5 FFE2h ACG1DCTL Adaptive clock generator1 divider control register Section 6.5.3.10 FFE1h ACGCTL Adaptive clock generator control register Section 6.5.3.11 FFE0h CPTCNF1 Codec port interface configuration register 1 Section 6.5.4.1 FFDFh CPTCNF2 Codec port interface configuration register 2 Section 6.5.4.2 FFDEh CPTCNF3 Codec port interface configuration register 3 Section 6.5.4.3 FFDDh CPTCNF4 Codec port interface configuration register 4 Section 6.5.4.4 FFDCh CPTCTL Codec port interface control and status register Section 6.5.4.5 FFDBh CPTADR Codec port interface address register Section 6.5.4.6 FFDAh CPTDATL Codec port interface data register (low-byte) Section 6.5.4.7 FFD9h CPTDATH Codec port interface data register (high-byte) Section 6.5.4.8 FFD8h CPTVSLL Codec port interface valid slots register (low-byte) Section 6.5.4.9 FFD7h CPTVSLH Codec port interface valid slots register (high-byte) Section 6.5.4.10 FFD6h CPTRXCNF2 Codec port receive interface configuration register 2 Section 6.5.4.11 FFD5h CPTRXCNF3 Codec port receive interface configuration register 3 Section 6.5.4.12 Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 87 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 6-3. Memory-Mapped Registers Address Map (continued) ADDRESS MNEMONIC NAME SECTION FFD4h CPTRXCNF4 Codec port receive interface configuration register 4 Section 6.5.4.13 FFD3h Reserved Reserved for future use FFD2h Reserved Reserved for future use FFD1h Reserved Reserved for future use FFD0h Reserved Reserved for future use FFCFh Reserved Reserved for future use FFCEh Reserved Reserved for future use FFCDh Reserved Reserved for future use FFCCh Reserved Reserved for future use FFCBh Reserved Reserved for future use FFCAh P3MSK Mask register for P3 Section 6.5.5.1 FFC9h Reserved Reserved for future use FFC8h Reserved Reserved for future use FFC7h Reserved Reserved for future use FFC6h Reserved Reserved for future use FFC5h Reserved Reserved for future use FFC4h Reserved Reserved for future use FFC3h I2CADR I2C interface address register Section 6.5.6.1 FFC2h I2CDATI I2C interface receive data register Section 6.5.6.2 FFC1h I2CDATO I2C interface transmit data register Section 6.5.6.3 FFC0h I2CCTL I2C interface control and status register Section 6.5.6.4 FFBFh Reserved Reserved for future use FFBEh Reserved Reserved for future use FFBDh Reserved Reserved for future use FFBCh Ch0WrPtrL UBM write pointer (low-byte) (8 bits) Section 6.5.2.8 FFBBh Ch0WrPtrH UBM write pointer (high-byte) (3 bits) Section 6.5.2.9 FFBAh Ch0RdPtrL DMA read pointer (low-byte) (8 bits) Section 6.5.2.10 FFB9h Ch0RdPtrH DMA read pointer (high-byte) (3 bits) Section 6.5.2.11 FFB8h Ch1WrPtrL UBM write pointer (low-byte) (8 bits) Section 6.5.2.8 FFB7h Ch1WrPtrH UBM write pointer (high-byte) (3 bits) Section 6.5.2.9 FFB6h Ch1RdPtrL DMA read pointer (low-byte) (8 bits) Section 6.5.2.10 FFB5h Ch1RdPtrH DMA read pointer (high-byte) (3 bits) Section 6.5.2.11 FFB4h OEPINT USB OUT endpoint interrupt register Section 6.5.7.1 FFB3h IEPINT USB IN endpoint interrupt register Section 6.5.7.2 FFB2h VECINT Interrupt vector register Section 6.5.7.3 FFB1h GLOBCTL Global control register Section 6.5.7.4 FFB0h MEMCFG Memory configuration register Section 6.5.7.5 88 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.1 USB Registers This section describes the memory-mapped registers used for control and operation of the USB functions. This section consists of six registers used for USB functions. 6.5.1.1 USB Function Address Register (USBFADR - Address FFFFh) The USB function address register contains the current setting of the USB device address assigned to the function by the host. After power-on reset or USB reset, the default address is 00h. During enumeration of the function by the host, the MCU should load the assigned address to this register when a USB Set_Address request is received by the control endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic — FA6 FA5 FA4 FA3 FA2 FA1 FA0 Type R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 — Reserved Reserved for future use 6:0 FA(6:0) Function address The function address bit values are set by the MCU to program the USB device address assigned by the host PC. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 89 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.1.2 USB Status Register (USBSTA - Address FFFEh) The USB status register contains various status bits used for USB operations. Bit 7 6 5 4 3 2 1 0 Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The function reset bit is set to a 1 by hardware in response to the host PC initiating a USB reset to the function. When a USB reset occurs, all of the USB logic blocks, including the SIE, UBM, frame timer, and suspend/resume are automatically reset. The function reset enable (FRSTE) control bit in the USB control register, when set, 7 RSTR Function reset enables the USB reset to reset all remaining TAS1020B logic, except the shadow the ROM (SDW) and the USB function connect (CONT) bits. Also, when the FRSTE control bit is set to a 1, the reset output (RSTO) signal from the TAS1020B device is also active when a USB reset occurs. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The function suspend bit is set to a 1 by hardware when a USB suspend condition is 6 SUSR Function suspend detected by the suspend/resume logic. See Section 2.2.5 for details on the USB suspend and resume operation. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The function resume bit is set to a 1 by hardware when a USB resume condition is 5 RESR Function resume detected by the suspend/resume logic. See Section 2.2.5 for details on the USB suspend and resume operation. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The start-of-frame bit is set to a 1 by hardware when a new USB frame starts. This bit is set when the SOF packet from the host PC is detected, even if the TAS1020B 4 SOF Start-of-frame frame timer is not locked to the host PC frame timer. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The nominal SOF rate is 1 ms. The pseudo start-of-frame bit is set to a 1 by hardware when a USB pseudo SOF occurs. The pseudo SOF is an artificial SOF signal that is generated when the 3 PSOF Pseudo start-of-frame TAS1020B frame timer is not locked to the host PC frame timer. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The nominal pseudo SOF rate is 1 ms. The setup stage transaction bit is set to a 1 by hardware when a successful control endpoint setup stage transaction is completed. Upon completion of the setup stage 2 SETUP Setup stage transaction transaction, the USB control endpoint setup stage data packet buffer should contain a new setup stage data packet. This bit is read-only and is cleared when the MCU writes to the interrupt vector register. 1 — Reserved Reserved for future use The setup stage transaction over-write bit is set to a 1 by hardware when the data in Setup stage transaction the USB control endpoint setup data packet buffer is over-written. This scenario 0 STPOW over-write occurs when the host PC prematurely terminates a USB control transfer by simply starting a new control transfer with a new setup stage transaction. This bit is read-only and is cleared when the MCU writes to the interrupt vector register. 90 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.1.3 USB Interrupt Mask Register (USBIMSK - Address FFFDh) The USB interrupt mask register contains the interrupt mask bits used to enable or disable the generation of interrupts based on the corresponding status bits. Bit 7 6 5 4 3 2 1 0 Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW Type R/W R/W R/W R/W R/W R/W R R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 RSTR Function reset The function reset interrupt mask bit is set to a 1 by the MCU to enable the USB function reset interrupt. 6 SUSR Function suspend The function suspend interrupt mask bit is set to a 1 by the MCU to enable the USB function suspend interrupt. 5 RESR Function resume The function resume interrupt mask bit is set to a 1 by the MCU to enable the USB function resume interrupt. 4 SOF Start-of-frame The start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB start-of-frame interrupt. 3 PSOF Pseudo start-of-frame The pseudo start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB pseudo start-of-frame interrupt. 2 SETUP Setup stage transaction The setup stage transaction interrupt mask bit is set to a 1 by the MCU to enable the USB setup stage transaction interrupt. 1 — Reserved Reserved for future use 0 STPOW Setup stage transaction The setup stage transaction over-write interrupt mask bit is set to a 1 by the MCU to over-write enable the USB setup stage transaction over-write interrupt. 6.5.1.4 USB Control Register (USBCTL - Address FFFCh) The USB control register contains various control bits used for USB operations. Bit 7 6 5 4 3 2 1 0 Mnemonic CONT FEN RWUP FRSTE — — — SDW_OK Type R/W R/W R/W R/W R R R R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The function connect bit is set to 1 by the MCU to connect the TAS1020B device to the USB. As a result of connecting to the USB, the host PC should enumerate the 7 CONT Function connect function. When this bit is set, the USB data plus pullup resistor (PUR) output signal is enabled, which connects the pullup on the PCB to the TAS1020B 3.3-V supply voltage. When this bit is cleared to 0, the PUR output is in the high-impedance state. This bit is not affected by a USB reset. The function enable bit is set to 1 by the MCU to enable the TAS1020B device to 6 FEN Function enable respond to USB transactions. If this bit is cleared to 0, the UBM ignores all USB transactions. This bit is cleared by a USB reset. The remote wake-up bit is set to 1 by the MCU to request the suspend/resume logic to 5 RWUP Remote wake-up generate resume signaling upstream on the USB. This bit is used to exit a USB low-power suspend state when a remote wake-up event occurs. After initiating the resume signaling by setting this bit, the MCU should clear this bit within 2.5 μs. The function reset enable bit is set to 1 by the MCU to enable the USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the 4 FRSTE Function reset enable USB function connect (CONT) bits will not be reset. When this bit is set, the reset output (RSTO) signal from the TAS1020B device is also active when a USB reset occurs. This bit is not affected by USB reset. 3 — Reserved Reserved for future use. 2 — Reserved Reserved for future use. 1 — Reserved Reserved for future use. This bit is used as a confirmation bit to prevent a user from spuriously clearing the 0 SDW_OK SDW bit confirm SDW bit in the MEMCFG register. This bit must be set to 1 before clearing the SDW bit to switch from normal mode to boot mode. This bit is not affected by USB reset. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 91 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.1.5 USB Frame Number Register (Low Byte) (USBFNL - Address FFFBh) The USB frame number register (low byte) contains the least significant byte of the 11-bit frame number value received from the host PC in the start-of-frame packet. Bit 7 6 5 4 3 2 1 0 Mnemonic FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The frame number bit values are updated by hardware each USB frame with the frame number field value received in the USB start-of-frame packet. The frame 7:0 FN(7:0) Frame number number can be used as a time stamp by the USB function. If the TAS1020B frame timer is not locked to the host PC frame timer, then the frame number is incremented from the previous value when a pseudo start-of-frame occurs. 6.5.1.6 USB Frame Number Register (High Byte) (USBFNH - Address FFFAh) The USB frame number register (high byte) contains the most significant 3 bits of the 11-bit frame number value received from the host PC in the start-of-frame packet. Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — FN10 FN9 FN8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:3 — Reserved Reserved for future use. The frame number bit values are updated by hardware each USB frame with the frame number field value received in the USB start-of-frame packet. The frame 2:0 FN(10:8) Frame number number can be used as a time stamp by the USB function. If the TAS1020B frame timer is not locked to the host PC frame timer, then the frame number is incremented from the previous value when a pseudo start-of-frame occurs. 6.5.2 DMA Registers This section describes the memory-mapped registers used for the two DMA channels. Each DMA channel has a set of three registers. 6.5.2.1 DMA Time Slot Assignment Register (Low Byte) (DMATSL1 - Address FFF0h) (DMATSL0 - Address FFEAh) Bit 7 6 5 4 3 2 1 0 Mnemonic TSL7 TSL6 TSL5 TSL4 TSL3 TSL2 TSL1 TSL0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 TSL(7:0) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel. 92 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 - Address FFEFh) (DMATSH0 - Address FFE9h) Bit 7 6 5 4 3 2 1 0 Mnemonic BPTS1 BPTS0 TSL13 TSL12 TSL11 TSL10 TSL9 TSL8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The bytes per time slot bits are used to define the number of bytes to be transferred for each time slot supported by this DMA channel. 7:6 BPTS(1:0) Bytes per time slot 00b = 1 byte 01b = 2 bytes 10b = 3 bytes 11b = 4 bytes 5:0 TSL(13:8) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel. 6.5.2.3 DMA Control Register (DMACTL1 - Address FFEEh) (DMACTL0 - Address FFE8h) Bit 7 6 5 4 3 2 1 0 Mnemonic DMAEN HSKEN — — EPDIR EPNUM2 EPNUM1 EPNUM0 Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before 7 DMAEN DMA enable enabling the DMA channel, all other DMA channel configuration bits must be set to the desired value. This bit is relevant for BULK data transfer in the OUT direction through DMA. MCU must set this bit to a 1 to enable the handshake mode for the data transfer. If MCU sets this bit, MCU has to enable DMA for each received BULK OUT packet. DMA, 6 HSKEN Handshake enable once enabled, transfers the BULK OUT packet to the C-port, disables itself and generates an interrupt to the MCU. If MCU clears this bit, DMA handles the BULK OUT data transfer to the C-port without MCU intervention. For more details, see Section 2.2.7.3.3. 5 — Reserved Reserved for future use 4 — Reserved Reserved for future use The USB endpoint direction bit controls the direction of data transfer by this DMA 3 EPDIR USB endpoint direction channel. The MCU should set this bit to a 1 to configure this DMA channel to be used for a USB IN endpoint. The MCU must clear this bit to a 0 to configure this DMA channel to be used for a USB OUT endpoint. The USB endpoint number bits are set by the MCU to define the USB endpoint number supported by this DMA channel. Keep in mind that endpoint 0 is always used for the control endpoint, which is serviced by the MCU and not a DMA channel. 2:0 EPNUM(2:0) USB endpoint number 001b = Endpoint 1 010b = Endpoint 2 ⋮ 111b = Endpoint 7 000b = Illegal 6.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L - Address FFF3h) (DMABCNT0LAddress FFEBh) Bit 7 6 5 4 3 2 1 0 Mnemonic Size 7 Size 6 Size 5 Size 4 Size 3 Size 2 Size 1 Size 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the buffer content (bytes) for an ISO OUT endpoint. This register 7:0 Size(7:0) Buffer content is updated every SOF and is stable for the following USB frame, during which the MCU can read it to implement USB audio synchronization. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 93 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.2.5 DMA Current Buffer Content Register (High Byte) (DMABCNT1H - Address FFF4h) (DMABCNT0H - Address FFECh) Bit 7 6 5 4 3 2 1 0 Mnemonic Size 15 Size 14 Size 13 Size 12 Size 11 Size 10 Size 9 Size 8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the buffer content (bytes) for an ISO OUT endpoint. This register 7:0 Size(15:8) Buffer content is updated every SOF and is stable for the following USB frame, during which the MCU can read it to implement USB audio synchronization. 6.5.2.6 DMA Bulk Packet Count Register (Low Byte) (DMABPCT0 - Address FFF2h) Bit 7 6 5 4 3 2 1 0 Mnemonic PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the number of BULK OUT packets DMA has to handle in 7:0 PCNT (7:0) Bulk packet count handshake mode. MCU writes to this register before enabling the DMA to program the DMA to handle up to 64K BULK packets without MCU intervention. MCU can read this register anytime. 6.5.2.7 DMA Bulk Packet Count Register (High-byte) (DMABPCT1 - Address FFF1h) Bit 7 6 5 4 3 2 1 0 Mnemonic PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the number of BULK OUT packets DMA has to handle in 7:0 PCNT (15:8) Bulk packet count handshake mode. MCU writes to this register before enabling the DMA to program the DMA to handle up to 64K BULK packets without MCU intervention. MCU can read this register anytime. 6.5.2.8 UBM Write Pointer (Low Byte) (Ch0WrPtrL - Address FFBCh) (Ch1WrPtrL - Address FFB8h) Bit 7 6 5 4 3 2 1 0 Mnemonic WRPTR7 WRPTR6 WRPTR5 WRPTR4 WRPTR3 WRPTR2 WRPTR1 WRPTR0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 8 LSB bits of 11-bit UBM write pointer of the isochronous OUT 7:0 WRPTR(7:0) UBM write pointer endpoint buffer. MCU can read this register anytime. This 11-bit UBM write pointer WRPTR can be used in conjunction with the corresponding 11-bit CHn DMA RDPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 94 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.2.9 UBM Write Pointer (High Byte) (Ch0WrPtrH - Address FFBBh) (Ch1WrPtrH - Address FFB7h) Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — WRPTR10 WRPTR9 WRPTR8 Type — — — — — R R R Default — — — — — 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 3 MSB bits of 11-bit UBM write pointer of the isochronous OUT 2:0 WRPTR(10:8) UBM write pointer endpoint buffer. MCU can read this register anytime. This 11-bit UBM write pointer WRPTR can be used in conjunction with the corresponding 11-bit CHn DMA RDPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 7:3 — Reserved Reserved for future use 6.5.2.10 DMA Read Pointer (Low Byte) (Ch0RdPtrL - Address FFBAh) (Ch1RdPtrL - Address FFB6h) Bit 7 6 5 4 3 2 1 0 Mnemonic RDPTR7 RDPTR6 RDPTR5 RDPTR4 RDPTR3 RDPTR2 RDPTR1 RDPTR0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 8 LSB bits of 11-bit DMA channel n (n can be 0 or 1) read pointer of the Isochronous OUT endpoint buffer. MCU can read this register anytime. 7:0 RDPTR(7:0) DMA read pointer This 11-bit CHn DMA read pointer RDPTR can be used in conjunction with the corresponding 11-bit UBM write pointer WRPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 6.5.2.11 DMA Read Pointer (High Byte) (Ch0RdPtrH - Address FFB9h) (Ch1RdPtrH - Address FFB5h) Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — WRPTR10 WRPTR9 WRPTR8 Type — — — — — R R R Default — — — — — 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 3 MSB bits of 11-bit channel n (n can be 0 or 1) read pointer of the Isochronous OUT endpoint buffer. MCU can read this register anytime. This 11-bit 2:0 RDPTR(10:8) DMA read pointer CHn DMA RDPTR can be used in conjunction with the corresponding 11-bit UBM write pointer WRPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 7:3 — Reserved Reserved for future use Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 95 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.3 Adaptive Clock Generator Registers This section describes the memory-mapped registers used for two adaptive clock generators for their controls and operations. 6.5.3.1 Adaptive Clock Generator1 Frequency Register (Byte 0) (ACG1FRQ0 - Address FFE7h) The adaptive clock generator frequency register (byte 0) contains the least significant byte of the 24-bit ACG frequency value. The adaptive clock generator frequency registers, ACG1FRQ0, ACG1FRQ1, and ACG1FRQ2, contain the 24-bit value used to program the ACG1 frequency synthesizer. The 24-bit value of these three registers can be used to determine the codec master clock output (MCLKO) signal frequency. The output of the ACG2 frequency synthesizer can also be used to source MCLK0. See Section 2.2.6 for the operation details of the adaptive clock generator including instructions for programming the 24-bit ACG frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ7 FRQ6 FRQ5 FRQ4 FRQ3 FRQ2 FRQ1 FRQ0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(7:0) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer. 6.5.3.2 Adaptive Clock Generator1 Frequency Register (Byte 1) (ACG1FRQ1 - Address FFE6h) The adaptive clock generator frequency register (byte 1) contains the middle byte of the 24-bit ACG 1 frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(15:8) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer. 6.5.3.3 Adaptive Clock Generator1 Frequency Register (Byte 2) (ACG1FRQ2 - Address FFE5h) The adaptive clock generator frequency register (byte 2) contains the most significant byte of the 24-bit ACG frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(23:16) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer. 96 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL - Address FFE4h) The adaptive clock generator MCLK capture register (low byte) contains the least significant byte of the 16-bit codec master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs. The value of a16-bit free running counter, which is clocked with the MCLK signal, is captured at the beginning of each USB frame. The source of the MCLK signal used to clock the 16-bit timer can be selected to be either the MCLKO signal or the MCLKO2 signal. See Section 2.2.6 for the operation details of the adaptive clock generator. Bit 7 6 5 4 3 2 1 0 Mnemonic CAP7 CAP6 CAP5 CAP4 CAP3 CAP2 CAP1 CAP0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 CAP(7:0) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the least significant byte of the 16-bit value. 6.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH - Address FFE3h) The adaptive clock generator MCLK capture register (high byte) contains the most significant byte of the 16-bit codec master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs. Bit 7 6 5 4 3 2 1 0 Mnemonic CAP15 CAP14 CAP13 CAP12 CAP11 CAP10 CAP9 CAP8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 CAP(15:8) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the most significant byte of the 16-bit value. 6.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 - Address FFF9h) The adaptive clock generator control registers ACG2FRQ0, ACG2FRQ1, and ACG2FRQ2, contain the 24-bit value used to program the ACG2 frequency synthesizer. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ7 FRQ6 FRQ5 FRQ4 FRQ3 FRQ2 FRQ1 FRQ0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(7:0) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer. 6.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 - Address FFF8h) Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(15:8) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 97 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.3.8 Adaptive Clock Generator2 Frequency Register (Byte 2) (ACG2FRQ2 - Address FFF7h) Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(23:16) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer. 6.5.3.9 Adaptive Clock Generator2 Divider Control Register (ACG2DCTL - Address FFF6h) Bit 7 6 5 4 3 2 1 0 Mnemonic DIVM3 DIVM2 DIVM1 DIVM0 - - - - Type R/W R/W R/W R/W R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The divide by M control bits are set by the MCU to program the ACG2 frequency divider. 7:4 DIVM(3:0) Divide by M value 0000b = divide by 1 0001b = divide by 2 ⋮ 1111b = divide by 16 3:0 - Reserved Reserved for future use 6.5.3.10 Adaptive Clock Generator1 Divider Control Register (ACG1DCTL - Address FFE2h) Bit 7 6 5 4 3 2 1 0 Mnemonic DIVM3 DIVM2 DIVM1 DIVM0 - DIVI2 DIVI1 DIVI0 Type R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The divide by M control bits are set by the MCU to program the ACG1 frequency divider. 7:4 DIVM(3:0) Divide by M value 0000b = divide by 1 0001b = divide by 2 ⋮ 1111b = divide by 16 3 - Reserved Reserved for future use The divide by I control bits are set by the MCU to program the MCLKI divider. 000b = divide by 1 2:0 DIVI(2:0) Divide by I value 001b = divide by 2 ⋮ 111b = divide by 8 98 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.3.11 Adaptive Clock Generator Control Register (ACGCTL - Address FFE1h) Bit 7 6 5 4 3 2 1 0 Mnemonic MCLKO2EN MCLKO1EN - MCLKO1S1 MCLKO1S0 DIVEN MCLKO2S1 MCLKO2S0 Type R/W R/W R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This bit is set to 1 by the MCU to enable the MCLKO2 signal to be an output from the 7 MCLKO2EN MCLKO2 output enable TAS1020B device. If the MCLKO2 signal is not being used, then the MCU can clear this bit to 0 to set the output to logic 0. This bit is set to 1 by the MCU to enable the MCLKO1 signal to be an output from the 6 MCLKO1EN MCLKO1 output enable TAS1020B device. If the MCLKO1 signal is not being used, then the MCU can clear this bit to 0 to set the output to logic 0. 5 - Reserved Reserved for future use This bit in conjunction with MCLKO1S0, selects the source for MCLKO1. See the ACG block diagram (Figure 2-1). MCLKO1S1 MCLKO1S0 MCLKO1 4 MCLKO1S1 MCLKO1 clock select 0 0 acg_clk (after ÷M) x 1 mclki (after ÷I) 1 0 acg2_clk(after ÷M) 3 MCLKO1S0 MCLKO1 clock select See the description above. 2 DIVEN Divider enable The divider enable bit is set to 1 by the MCU to enable the divide-by-I and divide-by-M circuits. This bit in conjunction with MCLKO2S0, selects the MCLKO2. See the ACG block diagram (Figure 2-1). MCLKO2S1 MCLKO2S0 MCLKO2 1 MCLKO2S1 MCLKO2 clock select 0 0 acg_clk (after ÷M) x 1 mclki (after ÷I) 1 0 acg2_clk(after ÷M) 0 MCLKO2S0 MCLKO2 clock select See the description above. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 99 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4 Codec Port Interface Registers This section describes the memory-mapped registers used for the codec port interface control and operation. The codec port interface has a set of ten registers. Note that the four codec port interface configuration registers can only be written to by the MCU if the codec port enable bit (CPTEN) in the global control register is a 0 - the codec port is disabled. 6.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 - Address FFE0h) The codec port interface configuration register 1 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic NTSL4 NTSL3 NTSL2 NTSL1 NTSL0 MODE2 MODE1 MODE0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The number of time slots bits are set by the MCU to program the number of time slots per audio frame. 7:3 NTSL(4:0) Number of time slots 00000b = Illegal 00001b = 2 time slots per frame ⋮ 01101 = 14 time slots per frame The mode select bits are set by the MCU to program the codec port interface mode of operation. In addition to selecting the desired mode of operation, the MCU must also program the other configuration registers to obtain the correct serial interface format. 000b = mode 0 - General-purpose mode 001b = mode 1 - AIC mode 2:0 MODE(2:0) Mode select 010b = mode 2 - AC ’97 1.x mode 011b = mode 3 - AC ’97 2.x mode 100b = mode 4 - I2S mode - 1 OUT and 2 IN at same frequency 101b = mode 5 - I2S mode - 1 OUT and 1 IN at different frequencies 110b = Reserved 111b = Reserved 100 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 - Address FFDFh) The codec port interface configuration register 2 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic TSL0L1 TSL0L0 BPTSL2 BPTSL1 BPTSL0 TSLL2 TSLL1 TSLL0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The time slot 0 Length bits are set by the MCU to program the number of serial clock (CSCLK) cycles for time slot 0. 7:6 TSL0L(1:0) Time slot 0 length 00b = CSCLK cycles for time slot 0 same as other time slots 01b = 8 CSCLK cycles for time slot 0 10b = 16 CSCLK cycles for time slot 0 11b = 32 CSCLK cycles for time slot 0 The data bits per time slot bits are set by the MCU to program the number of data bits per audio time slot. Note that this value in not used for the secondary communication address and data time slots. 000b = 8 data bits per time slot 001b = 16 data bits per time slot 5:3 BPTSL(2:0) Data bits per time slot 010b = 18 data bits per time slot 011b = 20 data bits per time slot 100b = 24 data bits per time slot 101b = 32 data bits per time slot 110b = reserved 111b = reserved The time slot length bits are set by the MCU to program the number of serial clock (CSCLK) cycles for all time slots except time slot 0. 000b = 8 CSCLK cycles per time slot 001b = 16 CSCLK cycles per time slot 2:0 TSLL(2:0) Time slot length 010b = 18 CSCLK cycles per time slot 011b = 20 CSCLK cycles per time slot 100b = 24 CSCLK cycles per time slot 101b = 32 CSCLK cycles per time slot 110b = reserved 111b = reserved Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 101 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF3 - Address FFDEh) The codec port interface configuration register 3 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of 7 DDLY Data delay the serial data output and input signals in reference to the leading edge of the CSYNC signal. The MCU must clear this bit to a 0 for no delay between these signals. The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the serial data output signal to the high-impedance state for the time slots during the 6 TRSEN 3-State enable audio frame that are not valid. The MCU must clear this bit to a 0 to program the hardware to use zero-padding for the serial data output signal for time slots during the audio frame that are not valid. The CSCLK polarity bit is used by the MCU to program the clock edge used for the codec port interface frame sync (CSYNC) output signal, codec port interface serial data output (CDATO) signal and codec port interface serial data Input (CDATI) signal. When this bit is set to a 1, the CSYNC signal is generated with the negative edge of the codec port interface serial clock (CSCLK) signal. Also, when this bit is set to a 1, 5 CSCLKP CSCLK polarity the CDATO signal is generated with the negative edge of the CSCLK signal and the CDATI signal is sampled with the positive edge of the CSCLK signal. When this bit is cleared to a 0, the CSYNC signal is generated with the positive edge of the CSCLK signal. Also, when this bit is cleared to a 0, the CDATO signal is generated with the positive edge of the CSCLK signal and the CDATI signal is sampled with the negative edge of the CSCLK signal. The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the codec 4 CSYNCP CSYNC polarity port interface frame sync (CSYNC) output signal to be active high. The MCU must clear this bit to a 0 to program the polarity of the CSYNC output signal to be active low. The CSYNC length bit is set to a 1 by the MCU to program the length of the codec 3 CSYNCL CSYNC length port interface frame sync (CSYNC) output signal to be the same number of CSCLK cycles as time slot 0. The MCU must clear this bit to a 0 to program the length of the CSYNC output signal to be one CSCLK cycle. The byte order bit is used by the MCU to program the byte order for the data moved by the DMA between the USB endpoint buffer and the codec port interface. When this 2 BYOR Byte order bit is set to a 1, the byte order of each audio sample is reversed when the data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the byte order of the each audio sample is unchanged. The CSCLK direction bit is set to a 1 by the MCU to program the direction of the codec port interface serial clock (CSCLK) signal as an input to the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSCLK signal as an 1 CSCLKD CSCLK direction output from the TAS1020B device. This bit can optionally be set to 1 to select 'Input' only when General Purpose Mode 1 has been selected. The CSYNC direction bit is set to a 1 by the MCU to program the direction of the codec port interface frame sync (CSYNC) signal as an input to the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSYNC signal as an 0 CSYNCD CSYNC direction output from the TAS1020B device. This bit can optionally be set to 1 to select 'Input' only when General Purpose Mode 1 has been selected. 102 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 - Address FFDDh) The codec port interface configuration register 4 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic ATSL3 ATSL2 ATSL1 ATSL0 CPTBLK DIVB2 DIVB1 DIVB0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status address/data time slot bits are set by the MCU to program the time slots to be used for the secondary communication address and data values. For the AC ’97 modes of operation, this value must be set to 0001b which results in time slot 1 being used for the address and time slot 2 being used for the data. For the AIC Command/status and general-purpose modes of operation, the same time slot is used for both address 7:4 ATSL(3:0) address/data time slot and data. For the AIC mode of operation this value must be set to 0111b which results in time slot 7 being used for both the address and data. 0000b = time slot 0 0001b = time slot 1 ⋮ 1111b = time slot 15 This bit is used when C-port is in Mode 0. If this bit is cleared to 0, the C-port 3 CptBlk C-port bulk mode sync/clocks are free running once C-port is enabled. If this bit is set to 1, DMA controls the C-port sync/clocks. The sync/clocks are active only when valid data is present in a codec frame. The divide by B control bits are set by the MCU to program the divide ratio used to derive CSCLK from MCLKO. 000b = CSCLK output disabled 001b = divide by 2 2:0 DIVB(2:0) Divide by B value 010b = divide by 3 011b = divide by 4 100b = divide by 5 101b = divide by 6 110b = divide by 7 111b = divide by 8 Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 103 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.5 Codec Port Interface Control and Status Register (CPTCTL - Address FFDCh) The codec port interface control and status register contains various control and status bits used for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic RXF RXIE TXE TXIE — CID1 CID0 CRST Type R R/W R R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The receive data register full bit is set to a 1 by hardware when a new data value has been received into the receive data register from the codec device. This bit is read 7 RXF Receive data register full only and is cleared to a 0 by hardware when the MCU reads the new value from the receive data register. Note that when the MCU writes to the interrupt vector register, the codec port interface receive data register full interrupt is cleared but this status bit is not cleared at that time. 6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the C-port receive data register full interrupt. The transmit data register empty bit is set to a 1 by hardware when the data value in the transmit data register has been sent to the codec device. This bit is read only and 5 TXE Transmit data register is cleared to a 0 by hardware when a new data byte is written to the transmit data empty register by the MCU. Note that when the MCU writes to the interrupt vector register, the codec port interface transmit data register empty interrupt is cleared but this status bit is not cleared at that time. 4 TXIE Transmit interrupt The transmit interrupt enable bit is set to a 1 by the MCU to enable the codec port enable interface transmit data register empty interrupt. 3 — Reserved Reserved for future use The codec ID bits are used by the MCU to select between the primary codec device and the secondary codec device for secondary communication in the AC ’97 modes of 2:1 CID(1:0) Codec ID operation. When the bits are cleared to 00, the primary codec device is selected. When the bits are set to 01, 10 or 11, the secondary codec device is selected. Note that when only a primary codec device is connected to the TAS1020B, the bits remain cleared to 00. The codec reset bit is used by the MCU to control the codec port interface reset (CRESET) output signal from the TAS1020B device. When this bit is set to a 1, the CRESET signal is a high. When this bit is cleared to a 0, the CRESET signal is active 0 CRST Codec reset low. At power up this bit is cleared to a 0, which means the CRESET output signal is active low and remains active low until the MCU sets this bit to a 1. In I2S mode 5, this signal is not available because the CRESET pin becomes SCLK2, which is used to input data from a codec. 104 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh) The codec port interface address register contains the read/write control bit and address bits used for secondary communication between the TAS1020B MCU and the codec device. For write transactions to the codec, the 8-bit value in this register is sent to the codec in the designated time slot and appropriate bit locations. Note that for the different modes of operation, the number of address bits and the bit location of the read/write bit is different. For example, the AC ’97 modes require 7 address bits and the bit location of the read/write bit to be the most significant bit. The AIC mode only requires 4 address bits and the bit location of the read/write bit to be bit 13 of the 16-bits in the time slot. The MCU must load the read/write and address bits to the correct bit locations within this register for the different modes of operation. Shown below are the read/write control bit and address bits for the AC ’97 mode of operation. Bit 7 6 5 4 3 2 1 0 Mnemonic R/W A6 A5 A4 A3 A2 A1 A0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status read/write control bit value is set by the MCU to program the 7 R/W Command/status type of secondary communication transaction to be done. This bit must be set to a 1 read/write control by the MCU for a read transaction and cleared to a 0 by the MCU for a write transaction. The command/status address value is set by the MCU to program the codec device 6:0 A(6:0) Command/status control/status register address to be accessed during the read or write transaction. address The command/status address value is updated by hardware with the control/status register address value received from the codec device for read transactions. 6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh) The codec port interface data register (low byte) contains the least significant byte of the 16-bit command or status data value used for secondary communication between the TAS1020B MCU and the codec device. Note that for general-purpose mode or AIC mode only an 8-bit data value is used for secondary communication. Bit 7 6 5 4 3 2 1 0 Mnemonic D7 D6 D5 D4 D3 D2 D1 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status data value is set by the MCU with the command data to be 7:0 D(7:0) Command/status data transmitted to the codec device for write transactions. The command/status data value is updated by hardware with the status data received from the codec device for read transactions. 6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h) The codec port interface data register (high byte) contains the most significant byte of the 16-bit command or status data value used for secondary communication between the TAS1020B MCU and the codec device. This register is not used for general-purpose mode or AIC mode since these modes only support an 8-bit data value for secondary communication. Bit 7 6 5 4 3 2 1 0 Mnemonic D15 D14 D13 D12 D11 D10 D9 D8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status data value is set by the MCU with the command data to be 7:0 D(15:8) Command/status data transmitted to the codec device for write transactions. The command/status data value is updated by hardware with the status data received from the codec device for read transactions. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 105 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL - Address FFD8h) The codec port interface valid time slots register (low byte) contains the control bits used to specify which time slots in the audio frame contain valid data. This register is only used in the AC ’97 modes of operation. Bit 7 6 5 4 3 2 1 0 Mnemonic VTSL8 VTSL9 VTSL10 VTSL11 VTSL12 — — — Type R/W R/W R/W R/W R/W R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The valid time slot bits are set to a 1 by the MCU to define which time slots in the 7:3 VTSL(8:12) Valid time slot audio frame contain valid data. The MCU must clear to a 0 the bits corresponding to time slots that do not contain valid data. Note that bits 7 to 3 of this register correspond to time slots 8 to 12. 2:0 — Reserved Reserved for future use 6.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH - Address FFD7h) The codec port interface valid time slots register (high byte) contains the control bits used to specify which time slots in the audio frame contain valid data. In addition the valid frame, primary codec ready and secondary codec ready bits are contained in this register. This register is only used in the AC ’97 modes of operation. Bit 7 6 5 4 3 2 1 0 Mnemonic VF PCRDY SCRDY VTSL3 VTSL4 VTSL5 VTSL6 VTSL7 Type R/W R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The valid frame bit is set to a 1 by the MCU to indicate that the current audio frame 7 VF Valid frame contains at least one time slot with valid data. The MCU must clear this bit to a 0 to indicate that the current audio frame does not contain any time slots with valid data. The primary codec ready bit is updated by hardware each audio frame based on the 6 PCRDY Primary codec ready value of bit 15 in time slot 0 of the incoming serial data from the primary codec. This bit is set to a 1 to indicate the primary codec is ready for operation. The secondary codec ready bit is updated by hardware each audio frame based on 5 SCRDY Secondary codec ready the value of bit 15 in time slot 0 of the incoming serial data from the secondary codec. This bit is set to a 1 to indicate the secondary codec is ready for operation. Note that this bit is only used if a secondary codec is connected to the TAS1020B device. The valid time slot bits are set to a 1 by the MCU to define which time slots in the 4:0 VTSL(3:7) Valid time slot audio frame contain valid data. The MCU must clear to a 0 the bits corresponding to time slots that do not contain valid data. Note that bits 4 to 0 of this register correspond to time slots 3 to 7. 106 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.11 Codec Port Receive Interface Configuration Register 2 (CPTRXCNF2 - Address FFD6h) The codec port receive interface configuration register2 is only used in I2S Mode 5. Bit 7 6 5 4 3 2 1 0 Mnemonic - - BPTSL2 BPTSL1 BPTSL0 TSLL2 TSLL1 TSLL0 Type R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:6 — Reserved Reserved for future use The data bits per time slot bits are set by the MCU to program the number of data bits per audio time slot. Note that this value in not used for the secondary communication address and data time slots. 000b = 8 data bits per time slot 001b = 16 data bits per time slot 5:3 BPTSL(2:0) Data bits per time slot. 010b = 18 data bits per time slot 011b = 20 data bits per time slot 100b = 24 data bits per time slot 101b = 32 data bits per time slot 110b = reserved 111b = reserved The time slot length bits are set by the MCU to program the number of serial clock (SCLK2) cycles for all time slots. 000b = 8 SCLK2 cycles per time slot 001b = 16 SCLK2 cycles per time slot 2:0 TSLL(2:0) Time slot length 010b = 18 SCLK2 cycles per time slot 011b = 20 SCLK2 cycles per time slot 100b = 24 SCLK2 cycles per time slot 101b = 32 SCLK2 cycles per time slot 110b = reserved 111b= reserved Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 107 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 - Address FFD5h) The codec port receive interface configuration register3 is only used in I2S Mode 5. Bit 7 6 5 4 3 2 1 0 Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The data delay bit is set to 1 by the MCU to program a one SCLK2 cycle delay of the 7 DDLY Data delay serial data output and input signals in reference to the leading edge of the LRCK2 signal. The MCU must clear this bit to a 0 for no delay between these signals. The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the serial data output signal to the high-impedance state for time slots during the audio 6 TRSEN 3-state enable frame that are not valid. The MCU must clear this bit to a 0 to program the hardware to use zero-padding for the serial data output signal for time slots during the audio frame that are not valid. The CSCLKP polarity bit is used by the MCU to program the clock edge used for the codec port interface frame sync (LRCK2) output signal and codec port interface serial data input (CDAT1) signal. When this bit is set to a 1, the LRCK2 signal is generated 5 CSCLKP CSCLK polarity with the negative edge of the codec port interface serial clock (SCLK2) signal. Also, when this bit is set a 1, the CDATI signal is sampled with the positive edge of the SCLK2 signal. When this bit is cleared to 0, the LRCK2 signal is generated with the positive edge of SCLK2 and the CDATI signal is sampled with the negative edge of the SCLK2 signal. The CSYNCP polarity bit is set to a 1 by the MCU to program the polarity of the codec 4 CSYNCP CSYNC polarity port interface frame sync (LRCK2) output signal to be active high. The MCU must clear this bit to a 0 to program the polarity of the LRCK2 output signal to be active low. The CSYNCL polarity bit is set to a 1 by the MCU to program the length of the codec 3 CSYNCL CSYNC length port interface frame sync (LRCK2) output signal to be the same number of SCLK2 cycles as time slot 0. The MCU must clear this bit to a 0 to program the length of the LRCK2 output signal to be one SCLK2 cycle. The byte order bit is used by the MCU to program the byte order for the data moved by the DMA between the USB endpoint buffer and the codec port interface. When this 2 BYOR Byte order bit is set to a 1, the byte order of each audio sample is reversed when the data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the byte order of the each audio sample is unchanged. The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec 1 CSCLKD CSCLK direction port interface serial clock (SCLK2) signal as an input of the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSCLK signal as an output from the TAS1020B device. The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec 0 CSYNCD CSYNC direction port interface frame sync (LRCK2) signal as an input of the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the LRCK2 signal as an output from the TAS1020B device. 108 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.13 Codec Port Receive Interface Configuration Register 4 (CPTRXCNF4 - Address FFD4h) The codec port receive interface configuration register 4 is only used in I2S Mode 5. Bit 7 6 5 4 3 2 1 0 Mnemonic - - - - - DIVB22 DIVB21 DIVB20 Type R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:3 — Reserved Reserved for future use The divide by B2 control bits are set by the MCU to program the divide ratio used to derive SCLK2 from MCLKO2. 000b = SCLK2 output disabled 001b = divide by 2 2:0 DIVB2(2:0) Divide by B2 value 010b = divide by 3 011b = divide by 4 100b = divide by 5 101b = divide by 6 110b = divide by 7 111b = divide by 8 6.5.5 P3 Mask Register Mask register for P3 to enable the wake-up function for these pins when the device is in low-power mode. 6.5.5.1 P3 Mask Register (P3MSK - Address FFCAh) Bit 7 6 5 4 3 2 1 0 Mnemonic P3MSK7 P3MSK6 P3MSK5 P3MSK4 P3MSK3 P3MSK2 P3MSK1 P3MSK0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 P3MSK(7:0) 0 = Unmasked 1 = Masked Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 109 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.6 I2C Interface Registers This section describes the memory-mapped registers used for the I2C Interface control and operation. The I2C interface has a set of four registers. See Section 2.2.14 for the operation details of the I2C interface. 6.5.6.1 I2C Interface Address Register (I2CADR - Address FFC3h) The I2C interface address register contains the 7-bit I2C slave device address and the read/write transaction control bit. Bit 7 6 5 4 3 2 1 0 Mnemonic A6 A5 A4 A3 A2 A1 A0 RW Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The address bit values are set by the MCU to program the 7-bit I2C slave address of the device to be accessed. Each I2 7:1 A(6:0) Address C slave device must have a unique address on the I2C bus. This address is used to identify the device on the bus to be accessed and is not the internal memory address to be accessed within the device. The read/write control bit value is set by the MCU to program the type of I2C 0 RW Read/write control transaction to be done. This bit must be set to a 1 by the MCU for a read transaction and cleared to a 0 by the MCU for a write transaction. 6.5.6.2 I2C Interface Receive Data Register (I2CDATI - Address FFC2h) The I2C interface receive data register contains the most recent data byte received from the slave device. Bit 7 6 5 4 3 2 1 0 Mnemonic RXD7 RXD6 RXD5 RDXD4 RXD3 RXD2 RXD1 RXD0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 RXD(7:0) Receive data The receive data byte value is updated by hardware for each data byte received from the I2C slave device. 6.5.6.3 I2C Interface Transmit Data Register (I2CDATO - Address FFC1h) The I2C interface transmit data register contains the next address or data byte to be transmitted to the slave device in accordance with the protocol. Note that for both read and write transactions, the internal register or memory address of the slave device being accessed must be transmitted to the slave device. Bit 7 6 5 4 3 2 1 0 Mnemonic TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 Type W W W W W W W W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 TXD(7:0) Transmit data The transmit data byte value is set by the MCU for each address or data byte to be transmitted to the I2C slave device. 110 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.6.4 I2C Interface Control and Status Register (I2CCTL - Address FFC0h) The I2C interface control and status register contains various control and status bits used for the I2C interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic RXF RXIE ERR FRQ TXE TXIE STPRD STPWR Type R R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The receive data register full bit is set to a 1 by hardware when a new data byte has been received into the receive data register from the slave device. This bit is read only 7 RXF Receive data register full and is cleared to a 0 by hardware when the MCU reads the new byte from the receive data register. Note that when the MCU writes to the interrupt vector register, the I2C receive data register full interrupt is cleared but this status bit is not cleared at that time. 6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the I2C receive data register full interrupt. 5 ERR Error condition The error condition bit is set to a 1 by hardware when the slave device does not respond. This bit is read/write and can only be cleared by the MCU. The frequency select bit is used by the MCU to program the I2C serial clock (SCL) 4 FRQ Frequency select output signal frequency. A value of 0 sets the SCL frequency to 100 kHz and a value of 1 sets the SCL frequency to 400 kHz. The transmit data register empty bit is set to a 1 by hardware when the data byte in the transmit data register has been sent to the slave device. This bit is read only and 3 TXE Transmit data register is cleared to a 0 by hardware when a new data byte is written to the transmit data empty register by the MCU. Note that when the MCU writes to the interrupt vector register, the I2C transmit data register empty interrupt is cleared but this status bit is not cleared at that time. 2 TXIE Transmit interrupt The transmit interrupt enable bit is set to a 1 by the MCU to enable the I2C transmit enable data register empty interrupt. The stop read transaction bit is set to a 1 by the MCU to enable the hardware to 1 STPRD Stop - read transaction generate a stop condition on the I2C bus after the next data byte from the slave device is received into the receive data register. The MCU must clear this bit to a 0 after the read transaction has concluded. The stop write transaction bit is set to a 1 by the MCU to enable the hardware to 0 STPWR Stop - write transaction generate a stop condition on the I2C bus after the data byte in the transmit data register is sent to the slave device. The MCU must clear this bit to a 0 after the write transaction has concluded. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 111 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.7 Miscellaneous Registers This section describes the memory-mapped registers used for the control and operation of miscellaneous functions in the TAS1020B device. The registers include the USB OUT endpoint interrupt register, the USB IN endpoint interrupt register, the interrupt vector register, the global control register, and the memory configuration register. 6.5.7.1 USB OUT endpoint Interrupt Register (OEPINT - Address FFB4h) The USB OUT endpoint interrupt register contains the interrupt pending status bits for the USB OUT endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic purposes only. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPI7 OEPI6 OEPI5 OEPI4 OEPI3 OEPI2 OEPI1 OEPI0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The OUT endpoint interrupt status bit for a particular USB OUT endpoint is set to a 1 by the UBM when a successful completion of a transaction occurs to that OUT 7:0 OEPI(7:0) OUT endpoint interrupt endpoint. When a bit is set, an interrupt to the MCU is generated and the corresponding interrupt vector results. The status bit is cleared when the MCU writes to the interrupt vector register. These bits do not apply to isochronous OUT endpoints. 6.5.7.2 USB IN endpoint Interrupt Register (IEPINT - Address FFB3h) The USB IN endpoint interrupt register contains the interrupt pending status bits for the USB IN endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic purposes only. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPI7 IEPI6 IEPI5 IEPI4 IEPI3 IEPI2 IEPI1 IEPI0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The IN endpoint interrupt status bit for a particular USB IN endpoint is set to a 1 by the UBM when a successful completion of a transaction occurs to that IN endpoint. When 7:0 IEPI(7:0) IN endpoint interrupt a bit is set, an interrupt to the MCU is generated and the corresponding interrupt vector results. The status bit is cleared when the MCU writes to the interrupt vector register. These bits do not apply to isochronous IN endpoints. 112 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.7.3 Interrupt Vector Register (VECINT - Address FFB2h) The interrupt vector register contains a 6-bit vector value that identifies the interrupt source for the INT0 input to the MCU. All of the TAS1020B internal interrupt sources and the external interrupt input to the device are ORed together to generate the internal INT0 signal to the MCU. When there is not an interrupt pending, the interrupt vector value is set to 24h. To clear any interrupt and update the interrupt vector value to the next pending interrupt, the MCU should simply write any value to this register. The interrupt priority is fixed in order, ranging from vector value 1Fh with the highest priority to vector value 00h with the lowest priority. An exception to this priority is the control endpoint EP0 which has top priority. Bit 7 6 5 4 3 2 1 0 Mnemonic — — IVEC5 IVEC4 IVEC3 IVEC2 IVEC1 IVEC0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 — Reserved Reserved for future use 6 — Reserved Reserved for future use 00h = USB OUT endpoint 0 10h = USB setup stage transaction 01h = USB OUT endpoint 1 over-write 02h = USB OUT endpoint 2 11h = Reserved 03h = USB OUT endpoint 3 12h = USB setup stage transaction 04h = USB OUT endpoint 4 13h = USB pseudo start-of-frame 05h = USB OUT endpoint 5 14h = USB start-of-frame 06h = USB OUT endpoint 6 15h = USB function resume 07h = USB OUT endpoint 7 16h = USB function suspend 5:0 IVEC(5:0) Interrupt vector 08h = USB IN endpoint 0 17h = USB function reset 09h = USB IN endpoint 1 18h = C-port receive data register full 0Ah = USB IN endpoint 2 19h = C-port transmit data register empty 0Bh = USB IN endpoint 3 1Ah = Reserved 0Ch = USB IN endpoint 4 1Bh = Reserved 0Dh = USB IN endpoint 5 1Ch = I2C receive data register full 0Eh = USB IN endpoint 6 1Dh = I2C transmit data register empty 0Fh = USB IN endpoint 7 1Eh = Reserved1Fh = External interrupt input 20h = DMA Ch.0 interrupt 24h = No interrupt pending 21h = DMA Ch.1 interrupt 25h - 3Fh = Reserved 22h - 23h = Reserved Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 113 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.7.4 Global Control Register (GLOBCTL - Address FFB1h) The global control register contains various global control bits for the TAS1020B device. Bit 7 6 5 4 3 2 1 0 Mnemonic MCUCLK XINTEN P1PUDIS VREN RESET LPWR P3PUDIS CPTEN Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The MCU clock select bit is used by the MCU to program the clock frequency to be used for the MCU operation. 7 MCUCLK MCU clock select 0b = 12 MHz 1b = 24 MHz POR (Power On Reset) value is 0 (12 MHz). Setting this bit to 1 will change MCU clock frequency to 24 MHz. But, once set, this bit can only be cleared by master reset. 6 XINTEN External interrupt enable The external interrupt enable bit is set to a 1 by the MCU to enable the use of the external interrupt input to the TAS1020B device. 5 P1PUDIS Pullup resistor disable If set to 1, disables on-chip pullup resistors on P1 GPIO pins. 4 VREN VREN Memory-mapped GPIO pin 3 RESET RESET Memory-mapped GPIO pin The low power mode disable bit is used by the MCU to put the TAS1020B into a 2 LPWR Low power mode semi-low power state. When this bit is cleared to a 0, all USB functional blocks are powered down. For normal operation, the MCU must set this bit to a 1. 1 P3PUDIS Pullup resistor disable If set to 1, disables on-chip pullup resistors on P3 GPIO pins. The codec port enable bit is set to a 1 by the MCU to enable the operation of the 0 CPTEN Codec port enable codec port interface. Note that the codec port interface configuration registers must be fully programmed before this bit is set by the MCU. 6.5.7.5 Memory Configuration Register (MEMCFG - Address FFB0h) The memory configuration register contains various bits pertaining to the memory configuration of the TAS1020B device. Bit 7 6 5 4 3 2 1 0 Mnemonic MEMTYP CODESZ1 CODESZ0 REV3 REV2 REV1 REV0 SDW Type R R R R R R R R/W Default 1 0 1 0 0 0 1 0 BIT MNEMONIC NAME DESCRIPTION The code memory type bit identifies if the type of memory used for the application 7 MEMTYP Code memory type program code space is ROM or RAM. For the TAS1020B, an 8K byte RAM is used and this bit is tied to 1. The code space size bits identify the size of the application program code memory space. For the TAS1020B, an 8K byte RAM is used and these bits are tied to 01b. 6:5 CODESZ(1:0) Code space size 00b = 4K bytes 01b = 8K bytes 10b = 16K bytes 11b = 32K bytes The IC revision bits identify the revision of the IC. 0000b = Rev. - 4:1 REV(3:0) IC revision 0001b = Rev. A ⋮ 1111b = Rev. F The shadow the boot ROM bit is set to a 1 by the MCU to switch the MCU memory 0 SDW Shadow the boot ROM configuration from boot loader mode to normal operating mode. This must occur after completion of the download of the application program code by the boot ROM. See the SDW protection bit in USBCTL register. 114 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B PACKAGE OPTION ADDENDUM www.ti.com 23-Nov-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TAS1020BPFB NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS1020BPFBG4 NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS1020BPFBR NRND TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS1020BPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TAS1020BPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS1020BPFBR TQFP PFB 48 1000 336.6 336.6 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Individual Switch Controls Extremely Low Input Current Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information These triple 2-channel CMOS analog multiplexers/demultiplexers are designed for 2-V to 5.5-V VCC operation. The ’LV4053A devices handle both analog and digital signals. Each channel permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74LV4053AN SN74LV4053AN QFN − RGY Reel of 1000 SN74LV4053ARGYR LW053A SOIC D Tube of 40 SN74LV4053AD − LV4053A Reel of 2500 SN74LV4053ADR 40°C to 85°C SOP − NS Reel of 2000 SN74LV4053ANSR 74LV4053A −SSOP − DB Reel of 2000 SN74LV4053ADBR LW053A Tube of 90 SN74LV4053APW TSSOP − PW Reel of 2000 SN74LV4053APWR LW053A Reel of 250 SN74LV4053APWT TVSOP − DGV Reel of 2000 SN74LV4053ADGVR LW053A 55°C to 125°C CDIP − J Tube of 25 SNJ54LV4053AJ SNJ54LV4053AJ −CFP − W Tube of 150 SNJ54LV4053AW SNJ54LV4053AW † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright © 2005, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2Y1 2Y0 3Y1 3-COM 3Y0 INH GND GND VCC 2-COM 1-COM 1Y1 1Y0 A B C SN54LV4053A . . . J OR W PACKAGE SN74LV4053A . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) SN74LV4053A . . . RGY PACKAGE (TOP VIEW) 1 16 8 9 2 3 4 5 6 7 15 14 13 12 11 10 2-COM 1-COM 1Y1 1Y0 A B 2Y0 3Y1 3-COM 3Y0 INH GND 2Y1 C V GND CC SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS ON CHANNELS INH C B A L L L L 1Y0, 2Y0, 3Y0 L L L H 1Y1, 2Y0, 3Y0 L L H L 1Y0, 2Y1, 3Y0 L L H H 1Y1, 2Y1, 3Y0 L H L L 1Y0, 2Y0, 3Y1 L H L H 1Y1, 2Y0, 3Y1 L H H L 1Y0, 2Y1, 3Y1 L H H H 1Y1, 2Y1, 3Y1 H X X X None logic diagram (positive logic) 1Y0 1Y1 2Y0 2Y1 3Y0 1-COM INH B A 3-COM 3Y1 2-COM C 11 10 9 6 15 14 12 13 2 1 5 3 4 SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 5) SN54LV4053A SN74LV4053A UNIT MIN MAX MIN MAX VCC Supply voltage 2‡ 5.5 2‡ 5.5 V VCC = 2 V 1.5 1.5 V High level input voltage control inputs VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VIH High-voltage, V VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V 0.5 0.5 V Low level input voltage control inputs VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VIL Low-voltage, V VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3 VI Control input voltage 0 5.5 0 5.5 V VIO Input/output voltage 0 VCC 0 VCC V VCC = 2.3 V to 2.7 V 200 200 Δt/Δv Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V VCC = 4.5 V to 5.5 V 20 20 TA Operating free-air temperature −55 125 −40 85 °C ‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST V TA = 25°C SN54LV4053A SN74LV4053A UNIT CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX IT = 2 mA, 2.3 V 41 180 225 225 ron On-state T , VI = VCC or GND, VINH = VIL on 3 V 30 150 190 190 Ω switch resistance (see Figure 1) 4.5 V 23 75 100 100 IT = 2 mA, 2.3 V 139 500 600 600 ron(p) Peak on-state resistance on VI = VCC to GND, 3 V 63 180 225 225 Ω VINH = VIL 4.5 V 35 100 125 125 Difference in IT = 2 mA, 2.3 V 2 30 40 40 Δron on-state resistance on VI = VCC to GND, 3 V 1.6 20 30 30 Ω between switches VINH = VIL 4.5 V 1.3 15 20 20 II Control input current VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 ±1 μA IS(off) Off-state switch leakage current VI = VCC and VO = GND, or VI = GND and VO = VCC, VINH = VIH (see Figure 2) 5.5 V ±0.1 ±1 ±1 μA IS(on) On-state switch leakage current VI = VCC or GND, VINH = VIH (see Figure 3) 5.5 V ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 5.5 V 20 20 μA CIC Control input capacitance 2 pF CIS Common terminal capacitance 8.2 pF COS Switch terminal capacitance 5.6 pF CF Feedthrough capacitance 0.5 pF switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 15 pF (see Figure 4) 2.5 10 16 16 ns tPZH tPZL Enable delay time INH COM or Yn CL = 15 pF (see Figure 5) 7.6 18 23 23 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 15 pF (see Figure 5) 7.7 18 23 23 ns tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 50 pF (see Figure 4) 4.4 12 18 18 ns tPZH tPZL Enable delay time INH COM or Yn CL = 50 pF (see Figure 5) 8.8 28 35 35 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 50 pF (see Figure 5) 11.7 28 35 35 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 15 pF (see Figure 4) 1.6 6 10 10 ns tPZH tPZL Enable delay time INH COM or Yn CL = 15 pF (see Figure 5) 5.3 12 15 15 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 15 pF (see Figure 5) 6.1 12 15 15 ns tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 50 pF (see Figure 4) 2.9 9 12 12 ns tPZH tPZL Enable delay time INH COM or Yn CL = 50 pF (see Figure 5) 6.1 20 25 25 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 50 pF (see Figure 5) 8.9 20 25 25 ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) PARAMETER FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 15 pF (see Figure 4) 0.9 4 7 7 ns tPZH tPZL Enable delay time INH COM or Yn CL = 15 pF (see Figure 5) 3.8 8 10 10 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 15 pF (see Figure 5) 4.6 8 10 10 ns tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 50 pF (see Figure 4) 1.8 6 8 8 ns tPZH tPZL Enable delay time INH COM or Yn CL = 50 pF (see Figure 5) 4.3 14 18 18 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 50 pF (see Figure 5) 6.3 14 18 18 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 analog switch characteristics PARAMETER FROM TO TEST CONDITIONS V TA = 25°C UNIT (INPUT) (OUTPUT) VCC TYP CL = 50 pF, 2.3 V 30 Frequency response COM or Yn Yn or COM L p , RL = 600 Ω, fi = 1 MHz (sine wave) 3 V 35 MHz (switch on) fin (see Note 6 and Figure 6) 4.5 V 50 CL = 50 pF, 2.3 V −45 Crosstalk COM or Yn Yn or COM p , RL = 600 Ω, fin = 1 MHz (sine wave) 3 V −45 dB (between any switches) (see Note 7 and Figure 7) 4.5 V −45 CL = 50 pF, 2.3 V 20 Crosstalk (control input to signal output) INH COM or Yn p , RL = 600 Ω, fin = 1 MHz (square wave) 3 V 35 mV (see Figure 8) 4.5 V 65 CL = 50 pF, 2.3 V −45 Feedthrough attenuation COM or Yn Yn or COM p , RL = 600 Ω, fin = 1 MHz 3 V −45 dB (switch off) (see Note 7 and Figure 9) 4.5 V −45 CL = 50 pF, RL = 10 kΩ VI = 2 Vp-p 2.3 V 0.1 Sine-wave distortion COM or Yn Yn or COM kΩ, fin = 1 kHz ( i ) VI = 2.5 Vp-p 3 V 0.1 % sine wave) (see Figure 10) VI = 4 Vp-p 4.5 V 0.1 NOTES: 6. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB. 7. Adjust fin voltage to obtain 0-dBm input. operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 5.3 pF PARAMETER MEASUREMENT INFORMATION VCC VI = VCC or GND VINH = VIL 2 mA VO ron VI – VO 2 10–3 VI − VO VCC GND (ON) V Figure 1. On-State Resistance Test Circuit SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PARAMETER MEASUREMENT INFORMATION VINH = VIH VI VO Condition 1: VI = 0, VO = VCC Condition 2: VI = VCC, VO = 0 A VCC VCC GND (OFF) Figure 2. Off-State Switch Leakage-Current Test Circuit VCC VINH = VIL VI Open VCC GND A (ON) VI = VCC or GND Figure 3. On-State Switch Leakage-Current Test Circuit VCC VINH = VIL Input Output 50 Ω CL VCC GND (ON) Figure 4. Propagation Delay Time, Signal Input to Signal Output SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION CL VCC VO TEST CIRCUIT VOLTAGE WAVEFORMS 1 kΩ S1 S2 tPLZ/tPZL tPHZ/tPZH GND VCC TEST S1 S2 VCC GND VINH 50 Ω 50% VOL + 0.3 V tPZH tPHZ 50% 50% 50% tPZL 50% VCC VO 50% 0 V VOL VINH (tPZL, tPZH) (tPLZ, tPHZ) VCC VO 0 V VOL VINH VCC 0 V VOH VCC 0 V ≈0 V VOH VOH − 0.3 V ≈0 V ≈VCC ≈VCC GND VCC VI tPLZ Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output VO RL CL VCC 50 Ω fin VINH = GND 0.1 μF VCC GND (ON) NOTE A: fin is a sine wave. VCC/2 Figure 6. Frequency Response (Switch On) SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VO1 RL CL VCC 50 Ω fin VCC/2 VINH = GND 0.1 μF VO2 VCC VCC/2 VINH = VCC 600 Ω VCC GND (ON) VCC GND (OFF) 600 Ω RL CL fin Figure 7. Crosstalk Between Any Two Switches VO VCC VCC GND RL CL VCC/2 VCC/2 50 Ω VINH 600 Ω Figure 8. Crosstalk Between Control Input and Switch Output VO RL CL VCC VCC/2 VINH = VCC 0.1 μF fin VCC/2 50 Ω 600 Ω VCC GND (OFF) Figure 9. Feedthrough Attenuation (Switch Off) SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VO RL CL VCC VCC/2 VINH = GND 10 μF fin VCC GND (ON) 600 Ω 10 μF Figure 10. Sine-Wave Distortion PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LV4053AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV4053AN SN74LV4053ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV4053AN SN74LV4053ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV4053A SN74LV4053APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LV4053ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LW053A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN74LV4053A : PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 • Automotive: SN74LV4053A-Q1 • Enhanced Product: SN74LV4053A-EP NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74LV4053ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV4053ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV4053ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4053ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4053ADRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4053ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV4053ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV4053ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV4053ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV4053ADR SOIC D 16 2500 364.0 364.0 27.0 SN74LV4053ADRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74LV4053ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV4053APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV4053APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV4053APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV4053APWT TSSOP PW 16 250 367.0 367.0 35.0 SN74LV4053ARGYR VQFN RGY 16 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 14 3,70 3,50 4,90 5,10 20 DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 1 12 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 16 24 38 4,90 3,70 5,10 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 0,40 0,07 M 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. 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It allows you to program, debug, and analyze your applications using its unique streaming trace technology. ULINKpro, together with MDK-ARM, provides extended on-the-fly debug capabilities for Cortex-M devices. You are able to control the processor, set breakpoints, and read/write memory contents, all while the processor is running at full speed. High-Speed data and instruction trace are streamed directly to your PC enabling you to analyze detailed program behaviour. Features Supports ARM7, ARM9, Cortex-M0, Cortex-M1, Cortex-M3, and Cortex-M4 devices JTAG support for ARM7, ARM9, and Cortex-M Serial Wire Debug (SWD) support for Cortex-M Serial Wire Viewer (SWV) Data and Event Trace for Cortex-M up to 100Mbit/s (Manchester mode) Instruction Trace (ETM) for Cortex-M3 and Cortex-M4 up to 800Mbit/s Unique Streaming Trace direct to your PC, provides unlimited trace buffer JTAG Clock Speed up to 50MHz Supports Cortex-M devices running at up to 200MHz High-Speed Memory Read/Write up to 1MBytes/sec Seamless integration with the Keil μVision IDE & Debugger Wide target voltage range: 1.2V - 3.3V, 5V tolerant Support for 5V only devices using optional 5V Adapter Optional Isolation Adapter provides electrical isolation from the target system USB 2.0 High-Speed connection USB powered (no power supply required) Target Connectors 10-pin (0.05") - Cortex Debug Connector 20-pin (0.10") - ARM Standard JTAG Connector 20-pin (0.05") - Cortex Debug+ETM Connector The unique streaming trace capabilities of ULINKpro delivers sophisticated analysis features such as: Complete Code Coverage information about your program's execution ensures thorough application testing and verification Performance Analysis using the Execution Profiler and Performance Analyzer enable you to identify program bottlenecks, optimize your application, and to isolate problems Streaming instruction trace requires the target device to have ETM (Embedded Trace Macrocell) www.element14.com www.farnell.com www.newark.com Page <1> V1.0 30/07/13 Raspberry PI Heat Sink Kit The Farnell Raspberry PI heat sink kit will ensure your Raspberry PI remains cool with no need for Fans. They will also help extend the life of your Raspberry PI and thereby reduce hardware failures. The heat sink kit comprises of 3 high quality Pressfin heat sinks which are designed to fit the 3 main heat sources on the Raspberry PI. Included in the kit is a 30mm × 30mm piece of thermal adhesive tape to securely fix the heat sinks in place and to ensure a good thermal transfer bond. Dimensions : Millimetres Important Notice : This data sheet and its contents (the “Information”) belong to the members of the Premier Farnell group of companies (the “Group”) or are licensed to it. No licence is granted for the use of it other than for information purposes in connection with the products to which it relates. No licence of any intellectual property rights is granted. The Information is subject to change without notice and replaces all data sheets previously supplied. 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Part Number Table Description Part Number Raspberry PI Heat Sink Kit 2319947 Raspberry Pi Power Supply UK version Features: Built specifically for use with Raspberry Pi Class II design 5vdc 1A output via Micro USB Energy efficienct to ErP stage 2 ĞƐĐƌŝƉƟŽŶ͗ This 5vdc 1A UK Micro USB power supply is manufactured specifically for use with the Raspberry Pi device. It offers a highly efficient output ŵĞĞƟŶŐ ůĂƚĞƐƚ ƌW ƐƚĂŐĞ Ϯ ƌĞƋƵŝƌĞŵĞŶƚƐ ĂŶĚ ŝƐ ƐĂĨĞƚLJ ĂƉƉƌŽǀ ĞĚ͘ dŚŝƐ unit has a fixed UK pin and a 1.8 metre output cable and features ƐŚŽƌƚ ĐŝƌĐƵŝƚ ĂŶĚ Žǀ Ğƌ ĐƵƌƌĞŶƚ ƉƌŽƚĞĐƟŽŶ ĂƐ ƐƚĂŶĚĂƌĚ͘ dŚŝƐ ZĂƐƉďĞƌƌLJ Pi power supply has M.T.B.F of 50K hours at 25 degrees C. Part Number PW03060 Output 5vdc 1A maximum Current Min. 0.01A WŽǁ Ğƌ ;ǁ ĂƩ ƐͿ 5W Line Reg +/-5% at rated load dŽƚĂů K ƵƚƉƵƚ ZĞŐƵůĂƟŽŶ +/-5 % at 0—100% load Ripple & Noise (mV p-p) 200mV P-P WƌŽƚĞĐƟŽŶƐ Over Current and Short Circuit Case Size 54 x 50 x 42mm Weight (approx.) 70g DC Cord 1.8 Metres DC Plug Micro USB Rated Input Voltage 100-240Vac Full Input Voltage Range 90-264Vac Rated Frequency 50-60Hz Full Frequency Range 47-63Hz Efficiency 68.17% Leakage Current shall not exceed 0.25mA Input Power 7.72W max Input Current (RMS Max.) 0.18A max Hi-Pot Spec 3000Vac 10mA 1 min. (I.P. to O.P.) E Ž ůŽĂĚ ƉŽǁ Ğƌ ĐŽŶƐƵŵƉƟŽŶ 0.3W max K ƉĞƌĂƟŶŐ dĞŵƉĞƌĂƚƵƌĞ 0 to 40 degrees C Storage Temperature -20 to 80 degrees C K ƉĞƌĂƟŶŐ , ƵŵŝĚŝƚLJ 10% to 90% Safety Approvals BS EN60950-1 / CE marked EMC Standards EN55022:2006+A1:2007 / EN6100-3-2 / EN6100-3-3 Pb-free Yes RoHS Compliant MTBF 50K Hours at 25 degrees C See mechanical drawing and DC cable drawing on page 2. Full spec sheet on this PSU is available on request. Premier Farnell Ltd accepts ŶŽ ƌĞƐƉŽŶƐŝďŝůŝƚLJ ĨŽƌ ƚLJƉŽŐƌĂƉŚŝĐĂů ĞƌƌŽƌƐ ŝŶ ƚŚĞ ƉƌŽĚƵĐƟŽŶ ŽĨ ƚŚŝƐ ůĞĂŇĞƚ͘ WƌŽĚƵĐƚ ƐƉĞĐŝĮ ĐĂƟŽŶƐ ĂƌĞ ƐƵďũĞĐƚ ƚŽ ĐŚĂŶŐĞ ǁ ŝƚŚŽƵƚ ŶŽƟĐĞ Raspberry Pi Power Supply UK version Mechanical drawing: Output connector Keyboard, Mouse and Cable Bundles for the Raspberry Pi Kit Contents: HDMI Bundle DVI Bundle RPI-CABLE+ACC/HDMI RPI-CABLE+ACC/DVI Mini QWERTY Keyboard Optical USB Mouse 3.5mm Stereo Jack Plug Cable – 2m Stereo Phono (RCA) to 3.5mm Stereo Jack Plug Cable – 1.8m Cat5e Patch Cable, RJ45 Plug to RJ45 Plug – 3m High Speed HDMI Cable – 2m HDMI to DVI Cable – 2m LM3S6952 Microcontroller DATA SHEET DS-LM3S6952-1972 Copyright © 2007 Luminary Micro, Inc. PRELIMINARY Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 November 30, 2007 Preliminary Table of Contents About This Document .................................................................................................................... 20 Audience .............................................................................................................................................. 20 About This Manual ................................................................................................................................ 20 Related Documents ............................................................................................................................... 20 Documentation Conventions .................................................................................................................. 20 1 Architectural Overview ...................................................................................................... 22 1.1 Product Features ...................................................................................................................... 22 1.2 Target Applications .................................................................................................................... 28 1.3 High-Level Block Diagram ......................................................................................................... 29 1.4 Functional Overview .................................................................................................................. 29 1.4.1 ARM Cortex™-M3 ..................................................................................................................... 30 1.4.2 Motor Control Peripherals .......................................................................................................... 30 1.4.3 Analog Peripherals .................................................................................................................... 31 1.4.4 Serial Communications Peripherals ............................................................................................ 32 1.4.5 System Peripherals ................................................................................................................... 33 1.4.6 Memory Peripherals .................................................................................................................. 34 1.4.7 Additional Features ................................................................................................................... 35 1.4.8 Hardware Details ...................................................................................................................... 35 2 ARM Cortex-M3 Processor Core ...................................................................................... 37 2.1 Block Diagram .......................................................................................................................... 38 2.2 Functional Description ............................................................................................................... 38 2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 38 2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 39 2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 39 2.2.4 ROM Table ............................................................................................................................... 39 2.2.5 Memory Protection Unit (MPU) ................................................................................................... 39 2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 39 3 Memory Map ....................................................................................................................... 43 4 Interrupts ............................................................................................................................ 45 5 JTAG Interface .................................................................................................................... 48 5.1 Block Diagram .......................................................................................................................... 49 5.2 Functional Description ............................................................................................................... 49 5.2.1 JTAG Interface Pins .................................................................................................................. 50 5.2.2 JTAG TAP Controller ................................................................................................................. 51 5.2.3 Shift Registers .......................................................................................................................... 52 5.2.4 Operational Considerations ........................................................................................................ 52 5.3 Initialization and Configuration ................................................................................................... 55 5.4 Register Descriptions ................................................................................................................ 55 5.4.1 Instruction Register (IR) ............................................................................................................. 55 5.4.2 Data Registers .......................................................................................................................... 57 6 System Control ................................................................................................................... 59 6.1 Functional Description ............................................................................................................... 59 6.1.1 Device Identification .................................................................................................................. 59 6.1.2 Reset Control ............................................................................................................................ 59 November 30, 2007 3 Preliminary LM3S6952 Microcontroller 6.1.3 Power Control ........................................................................................................................... 62 6.1.4 Clock Control ............................................................................................................................ 62 6.1.5 System Control ......................................................................................................................... 64 6.2 Initialization and Configuration ................................................................................................... 65 6.3 Register Map ............................................................................................................................ 65 6.4 Register Descriptions ................................................................................................................ 66 7 Hibernation Module .......................................................................................................... 120 7.1 Block Diagram ........................................................................................................................ 121 7.2 Functional Description ............................................................................................................. 121 7.2.1 Register Access Timing ........................................................................................................... 121 7.2.2 Clock Source .......................................................................................................................... 122 7.2.3 Battery Management ............................................................................................................... 122 7.2.4 Real-Time Clock ...................................................................................................................... 122 7.2.5 Non-Volatile Memory ............................................................................................................... 123 7.2.6 Power Control ......................................................................................................................... 123 7.2.7 Interrupts and Status ............................................................................................................... 123 7.3 Initialization and Configuration ................................................................................................. 124 7.3.1 Initialization ............................................................................................................................. 124 7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 124 7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 124 7.3.4 External Wake-Up from Hibernation .......................................................................................... 125 7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 125 7.4 Register Map .......................................................................................................................... 125 7.5 Register Descriptions .............................................................................................................. 126 8 Internal Memory ............................................................................................................... 139 8.1 Block Diagram ........................................................................................................................ 139 8.2 Functional Description ............................................................................................................. 139 8.2.1 SRAM Memory ........................................................................................................................ 139 8.2.2 Flash Memory ......................................................................................................................... 140 8.3 Flash Memory Initialization and Configuration ........................................................................... 141 8.3.1 Flash Programming ................................................................................................................. 141 8.3.2 Nonvolatile Register Programming ........................................................................................... 142 8.4 Register Map .......................................................................................................................... 142 8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 143 8.6 Flash Register Descriptions (System Control Offset) .................................................................. 150 9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 163 9.1 Functional Description ............................................................................................................. 163 9.1.1 Data Control ........................................................................................................................... 164 9.1.2 Interrupt Control ...................................................................................................................... 165 9.1.3 Mode Control .......................................................................................................................... 166 9.1.4 Commit Control ....................................................................................................................... 166 9.1.5 Pad Control ............................................................................................................................. 166 9.1.6 Identification ........................................................................................................................... 166 9.2 Initialization and Configuration ................................................................................................. 166 9.3 Register Map .......................................................................................................................... 168 9.4 Register Descriptions .............................................................................................................. 169 4 November 30, 2007 Preliminary Table of Contents 10 General-Purpose Timers ................................................................................................. 204 10.1 Block Diagram ........................................................................................................................ 204 10.2 Functional Description ............................................................................................................. 205 10.2.1 GPTM Reset Conditions .......................................................................................................... 205 10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206 10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207 10.3 Initialization and Configuration ................................................................................................. 211 10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211 10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212 10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212 10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213 10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213 10.3.6 16-Bit PWM Mode ................................................................................................................... 214 10.4 Register Map .......................................................................................................................... 214 10.5 Register Descriptions .............................................................................................................. 215 11 Watchdog Timer ............................................................................................................... 240 11.1 Block Diagram ........................................................................................................................ 240 11.2 Functional Description ............................................................................................................. 240 11.3 Initialization and Configuration ................................................................................................. 241 11.4 Register Map .......................................................................................................................... 241 11.5 Register Descriptions .............................................................................................................. 242 12 Analog-to-Digital Converter (ADC) ................................................................................. 263 12.1 Block Diagram ........................................................................................................................ 264 12.2 Functional Description ............................................................................................................. 264 12.2.1 Sample Sequencers ................................................................................................................ 264 12.2.2 Module Control ........................................................................................................................ 265 12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266 12.2.4 Analog-to-Digital Converter ...................................................................................................... 266 12.2.5 Test Modes ............................................................................................................................. 266 12.2.6 Internal Temperature Sensor .................................................................................................... 266 12.3 Initialization and Configuration ................................................................................................. 267 12.3.1 Module Initialization ................................................................................................................. 267 12.3.2 Sample Sequencer Configuration ............................................................................................. 267 12.4 Register Map .......................................................................................................................... 268 12.5 Register Descriptions .............................................................................................................. 269 13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296 13.1 Block Diagram ........................................................................................................................ 297 13.2 Functional Description ............................................................................................................. 297 13.2.1 Transmit/Receive Logic ........................................................................................................... 297 13.2.2 Baud-Rate Generation ............................................................................................................. 298 13.2.3 Data Transmission .................................................................................................................. 299 13.2.4 Serial IR (SIR) ......................................................................................................................... 299 13.2.5 FIFO Operation ....................................................................................................................... 300 13.2.6 Interrupts ................................................................................................................................ 300 13.2.7 Loopback Operation ................................................................................................................ 301 13.2.8 IrDA SIR block ........................................................................................................................ 301 13.3 Initialization and Configuration ................................................................................................. 301 13.4 Register Map .......................................................................................................................... 302 November 30, 2007 5 Preliminary LM3S6952 Microcontroller 13.5 Register Descriptions .............................................................................................................. 303 14 Synchronous Serial Interface (SSI) ................................................................................ 337 14.1 Block Diagram ........................................................................................................................ 337 14.2 Functional Description ............................................................................................................. 337 14.2.1 Bit Rate Generation ................................................................................................................. 338 14.2.2 FIFO Operation ....................................................................................................................... 338 14.2.3 Interrupts ................................................................................................................................ 338 14.2.4 Frame Formats ....................................................................................................................... 339 14.3 Initialization and Configuration ................................................................................................. 346 14.4 Register Map .......................................................................................................................... 347 14.5 Register Descriptions .............................................................................................................. 348 15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374 15.1 Block Diagram ........................................................................................................................ 374 15.2 Functional Description ............................................................................................................. 374 15.2.1 I2C Bus Functional Overview .................................................................................................... 375 15.2.2 Available Speed Modes ........................................................................................................... 377 15.2.3 Interrupts ................................................................................................................................ 378 15.2.4 Loopback Operation ................................................................................................................ 378 15.2.5 Command Sequence Flow Charts ............................................................................................ 379 15.3 Initialization and Configuration ................................................................................................. 385 15.4 I2C Register Map ..................................................................................................................... 386 15.5 Register Descriptions (I2C Master) ........................................................................................... 387 15.6 Register Descriptions (I2C Slave) ............................................................................................. 400 16 Ethernet Controller .......................................................................................................... 409 16.1 Block Diagram ........................................................................................................................ 410 16.2 Functional Description ............................................................................................................. 410 16.2.1 Internal MII Operation .............................................................................................................. 410 16.2.2 PHY Configuration/Operation ................................................................................................... 411 16.2.3 MAC Configuration/Operation .................................................................................................. 412 16.2.4 Interrupts ................................................................................................................................ 414 16.3 Initialization and Configuration ................................................................................................. 415 16.4 Ethernet Register Map ............................................................................................................. 415 16.5 Ethernet MAC Register Descriptions ......................................................................................... 417 16.6 MII Management Register Descriptions ..................................................................................... 434 17 Analog Comparators ....................................................................................................... 453 17.1 Block Diagram ........................................................................................................................ 454 17.2 Functional Description ............................................................................................................. 454 17.2.1 Internal Reference Programming .............................................................................................. 456 17.3 Initialization and Configuration ................................................................................................. 457 17.4 Register Map .......................................................................................................................... 457 17.5 Register Descriptions .............................................................................................................. 458 18 Pulse Width Modulator (PWM) ........................................................................................ 466 18.1 Block Diagram ........................................................................................................................ 466 18.2 Functional Description ............................................................................................................. 466 18.2.1 PWM Timer ............................................................................................................................. 466 18.2.2 PWM Comparators .................................................................................................................. 467 18.2.3 PWM Signal Generator ............................................................................................................ 468 6 November 30, 2007 Preliminary Table of Contents 18.2.4 Dead-Band Generator ............................................................................................................. 469 18.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 469 18.2.6 Synchronization Methods ......................................................................................................... 469 18.2.7 Fault Conditions ...................................................................................................................... 470 18.2.8 Output Control Block ............................................................................................................... 470 18.3 Initialization and Configuration ................................................................................................. 470 18.4 Register Map .......................................................................................................................... 471 18.5 Register Descriptions .............................................................................................................. 472 19 Quadrature Encoder Interface (QEI) ............................................................................... 501 19.1 Block Diagram ........................................................................................................................ 501 19.2 Functional Description ............................................................................................................. 502 19.3 Initialization and Configuration ................................................................................................. 504 19.4 Register Map .......................................................................................................................... 504 19.5 Register Descriptions .............................................................................................................. 505 20 Pin Diagram ...................................................................................................................... 518 21 Signal Tables .................................................................................................................... 519 22 Operating Characteristics ............................................................................................... 533 23 Electrical Characteristics ................................................................................................ 534 23.1 DC Characteristics .................................................................................................................. 534 23.1.1 Maximum Ratings ................................................................................................................... 534 23.1.2 Recommended DC Operating Conditions .................................................................................. 534 23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 535 23.1.4 Power Specifications ............................................................................................................... 535 23.1.5 Flash Memory Characteristics .................................................................................................. 537 23.2 AC Characteristics ................................................................................................................... 537 23.2.1 Load Conditions ...................................................................................................................... 537 23.2.2 Clocks .................................................................................................................................... 537 23.2.3 Analog-to-Digital Converter ...................................................................................................... 538 23.2.4 Analog Comparator ................................................................................................................. 539 23.2.5 I2C ......................................................................................................................................... 539 23.2.6 Ethernet Controller .................................................................................................................. 540 23.2.7 Hibernation Module ................................................................................................................. 543 23.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 543 23.2.9 JTAG and Boundary Scan ........................................................................................................ 545 23.2.10 General-Purpose I/O ............................................................................................................... 546 23.2.11 Reset ..................................................................................................................................... 547 24 Package Information ........................................................................................................ 549 A Serial Flash Loader .......................................................................................................... 551 A.1 Serial Flash Loader ................................................................................................................. 551 A.2 Interfaces ............................................................................................................................... 551 A.2.1 UART ..................................................................................................................................... 551 A.2.2 SSI ......................................................................................................................................... 551 A.3 Packet Handling ...................................................................................................................... 552 A.3.1 Packet Format ........................................................................................................................ 552 A.3.2 Sending Packets ..................................................................................................................... 552 A.3.3 Receiving Packets ................................................................................................................... 552 November 30, 2007 7 Preliminary LM3S6952 Microcontroller A.4 Commands ............................................................................................................................. 553 A.4.1 COMMAND_PING (0X20) ........................................................................................................ 553 A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 553 A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 553 A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 554 A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 554 A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 554 B Register Quick Reference ............................................................................................... 556 C Ordering and Contact Information ................................................................................. 575 C.1 Ordering Information ................................................................................................................ 575 C.2 Kits ......................................................................................................................................... 575 C.3 Company Information .............................................................................................................. 575 C.4 Support Information ................................................................................................................. 576 8 November 30, 2007 Preliminary Table of Contents List of Figures Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 29 Figure 2-1. CPU Block Diagram ......................................................................................................... 38 Figure 2-2. TPIU Block Diagram ........................................................................................................ 39 Figure 5-1. JTAG Module Block Diagram ............................................................................................ 49 Figure 5-2. Test Access Port State Machine ....................................................................................... 52 Figure 5-3. IDCODE Register Format ................................................................................................. 57 Figure 5-4. BYPASS Register Format ................................................................................................ 58 Figure 5-5. Boundary Scan Register Format ....................................................................................... 58 Figure 6-1. External Circuitry to Extend Reset .................................................................................... 60 Figure 7-1. Hibernation Module Block Diagram ................................................................................. 121 Figure 8-1. Flash Block Diagram ...................................................................................................... 139 Figure 9-1. GPIO Port Block Diagram ............................................................................................... 164 Figure 9-2. GPIODATA Write Example ............................................................................................. 165 Figure 9-3. GPIODATA Read Example ............................................................................................. 165 Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205 Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209 Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210 Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211 Figure 11-1. WDT Module Block Diagram .......................................................................................... 240 Figure 12-1. ADC Module Block Diagram ........................................................................................... 264 Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 267 Figure 13-1. UART Module Block Diagram ......................................................................................... 297 Figure 13-2. UART Character Frame ................................................................................................. 298 Figure 13-3. IrDA Data Modulation ..................................................................................................... 300 Figure 14-1. SSI Module Block Diagram ............................................................................................. 337 Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339 Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340 Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341 Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341 Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342 Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343 Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343 Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344 Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345 Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346 Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346 Figure 15-1. I2C Block Diagram ......................................................................................................... 374 Figure 15-2. I2C Bus Configuration .................................................................................................... 375 Figure 15-3. START and STOP Conditions ......................................................................................... 375 Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376 Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376 Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376 Figure 15-7. Master Single SEND ...................................................................................................... 379 Figure 15-8. Master Single RECEIVE ................................................................................................. 380 Figure 15-9. Master Burst SEND ....................................................................................................... 381 November 30, 2007 9 Preliminary LM3S6952 Microcontroller Figure 15-10. Master Burst RECEIVE .................................................................................................. 382 Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383 Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384 Figure 15-13. Slave Command Sequence ............................................................................................ 385 Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410 Figure 16-2. Ethernet Controller ......................................................................................................... 410 Figure 16-3. Ethernet Frame ............................................................................................................. 412 Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 454 Figure 17-2. Structure of Comparator Unit .......................................................................................... 455 Figure 17-3. Comparator Internal Reference Structure ........................................................................ 456 Figure 18-1. PWM Module Block Diagram .......................................................................................... 466 Figure 18-2. PWM Count-Down Mode ................................................................................................ 467 Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 468 Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 468 Figure 18-5. PWM Dead-Band Generator ........................................................................................... 469 Figure 19-1. QEI Block Diagram ........................................................................................................ 501 Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503 Figure 20-1. Pin Connection Diagram ................................................................................................ 518 Figure 23-1. Load Conditions ............................................................................................................ 537 Figure 23-2. I2C Timing ..................................................................................................................... 540 Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 542 Figure 23-4. Hibernation Module Timing ............................................................................................. 543 Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 544 Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 544 Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 545 Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 546 Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 546 Figure 23-10. JTAG TRST Timing ........................................................................................................ 546 Figure 23-11. External Reset Timing (RST) .......................................................................................... 547 Figure 23-12. Power-On Reset Timing ................................................................................................. 548 Figure 23-13. Brown-Out Reset Timing ................................................................................................ 548 Figure 23-14. Software Reset Timing ................................................................................................... 548 Figure 23-15. Watchdog Reset Timing ................................................................................................. 548 Figure 24-1. 100-Pin LQFP Package .................................................................................................. 549 10 November 30, 2007 Preliminary Table of Contents List of Tables Table 1. Documentation Conventions ............................................................................................ 20 Table 3-1. Memory Map ................................................................................................................... 43 Table 4-1. Exception Types .............................................................................................................. 45 Table 4-2. Interrupts ........................................................................................................................ 46 Table 5-1. JTAG Port Pins Reset State ............................................................................................. 50 Table 5-2. JTAG Instruction Register Commands ............................................................................... 55 Table 6-1. System Control Register Map ........................................................................................... 65 Table 7-1. Hibernation Module Register Map ................................................................................... 125 Table 8-1. Flash Protection Policy Combinations ............................................................................. 141 Table 8-2. Flash Resident Registers ............................................................................................... 142 Table 8-3. Flash Register Map ........................................................................................................ 142 Table 9-1. GPIO Pad Configuration Examples ................................................................................. 167 Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 167 Table 9-3. GPIO Register Map ....................................................................................................... 168 Table 10-1. Available CCP Pins ........................................................................................................ 205 Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208 Table 10-3. Timers Register Map ...................................................................................................... 214 Table 11-1. Watchdog Timer Register Map ........................................................................................ 241 Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264 Table 12-2. ADC Register Map ......................................................................................................... 268 Table 13-1. UART Register Map ....................................................................................................... 302 Table 14-1. SSI Register Map .......................................................................................................... 347 Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377 Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386 Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391 Table 16-1. TX & RX FIFO Organization ........................................................................................... 413 Table 16-2. Ethernet Register Map ................................................................................................... 416 Table 17-1. Comparator 0 Operating Modes ..................................................................................... 455 Table 17-2. Comparator 1 Operating Modes ..................................................................................... 455 Table 17-3. Comparator 2 Operating Modes ...................................................................................... 456 Table 17-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 456 Table 17-5. Analog Comparators Register Map ................................................................................. 458 Table 18-1. PWM Register Map ........................................................................................................ 471 Table 19-1. QEI Register Map .......................................................................................................... 504 Table 21-1. Signals by Pin Number ................................................................................................... 519 Table 21-2. Signals by Signal Name ................................................................................................. 523 Table 21-3. Signals by Function, Except for GPIO ............................................................................. 527 Table 21-4. GPIO Pins and Alternate Functions ................................................................................. 531 Table 22-1. Temperature Characteristics ........................................................................................... 533 Table 22-2. Thermal Characteristics ................................................................................................. 533 Table 23-1. Maximum Ratings .......................................................................................................... 534 Table 23-2. Recommended DC Operating Conditions ........................................................................ 534 Table 23-3. LDO Regulator Characteristics ....................................................................................... 535 Table 23-4. Detailed Power Specifications ........................................................................................ 536 Table 23-5. Flash Memory Characteristics ........................................................................................ 537 Table 23-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 537 November 30, 2007 11 Preliminary LM3S6952 Microcontroller Table 23-7. Clock Characteristics ..................................................................................................... 537 Table 23-8. Crystal Characteristics ................................................................................................... 538 Table 23-9. ADC Characteristics ....................................................................................................... 538 Table 23-10. Analog Comparator Characteristics ................................................................................. 539 Table 23-11. Analog Comparator Voltage Reference Characteristics .................................................... 539 Table 23-12. I2C Characteristics ......................................................................................................... 539 Table 23-13. 100BASE-TX Transmitter Characteristics ........................................................................ 540 Table 23-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 540 Table 23-15. 100BASE-TX Receiver Characteristics ............................................................................ 540 Table 23-16. 10BASE-T Transmitter Characteristics ............................................................................ 540 Table 23-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 541 Table 23-18. 10BASE-T Receiver Characteristics ................................................................................ 541 Table 23-19. Isolation Transformers ................................................................................................... 541 Table 23-20. Ethernet Reference Crystal ............................................................................................ 542 Table 23-21. External XTLP Oscillator Characteristics ......................................................................... 542 Table 23-22. Hibernation Module Characteristics ................................................................................. 543 Table 23-23. SSI Characteristics ........................................................................................................ 543 Table 23-24. JTAG Characteristics ..................................................................................................... 545 Table 23-25. GPIO Characteristics ..................................................................................................... 547 Table 23-26. Reset Characteristics ..................................................................................................... 547 Table C-1. Part Ordering Information ............................................................................................... 575 12 November 30, 2007 Preliminary Table of Contents List of Registers System Control .............................................................................................................................. 59 Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 67 Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 69 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 70 Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 71 Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 72 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 73 Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 74 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 75 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 79 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 80 Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 82 Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 83 Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 85 Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 86 Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 88 Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 90 Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 96 Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 98 Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100 Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 103 Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 106 Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 109 Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 111 Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 113 Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 115 Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 116 Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 118 Hibernation Module ..................................................................................................................... 120 Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 127 Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 128 Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 129 Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 130 Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 131 Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 133 Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 134 Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 135 Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 136 Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 137 Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 138 Internal Memory ........................................................................................................................... 139 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 144 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 145 November 30, 2007 13 Preliminary LM3S6952 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 146 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 148 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 149 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 150 Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 151 Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 152 Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 153 Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 154 Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 155 Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 156 Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 157 Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 158 Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 159 Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 160 Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 161 Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 162 General-Purpose Input/Outputs (GPIOs) ................................................................................... 163 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175 Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179 Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186 Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187 Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188 Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189 Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190 Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192 Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193 Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194 Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195 Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196 Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197 Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198 Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199 Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200 Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201 Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202 14 November 30, 2007 Preliminary Table of Contents Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203 General-Purpose Timers ............................................................................................................. 204 Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216 Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217 Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219 Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221 Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224 Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226 Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227 Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228 Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230 Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231 Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232 Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233 Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234 Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237 Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239 Watchdog Timer ........................................................................................................................... 240 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244 Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245 Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246 Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247 Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248 Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252 Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253 Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254 Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255 Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256 Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257 Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258 Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259 Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260 Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262 Analog-to-Digital Converter (ADC) ............................................................................................. 263 Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 270 Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 271 Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 272 Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 273 Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 274 Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 275 November 30, 2007 15 Preliminary LM3S6952 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 278 Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 279 Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 280 Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 281 Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 282 Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 284 Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 287 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 287 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 287 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 287 Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 288 Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 288 Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 288 Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 288 Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 289 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 289 Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 290 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 290 Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 292 Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 293 Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 294 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296 Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304 Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306 Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308 Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310 Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311 Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312 Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313 Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315 Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317 Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319 Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323 Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325 Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326 Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327 Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328 Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329 Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330 Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331 Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332 Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333 Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334 Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335 Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336 16 November 30, 2007 Preliminary Table of Contents Synchronous Serial Interface (SSI) ............................................................................................ 337 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353 Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354 Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357 Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361 Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362 Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363 Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364 Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365 Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366 Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367 Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368 Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369 Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370 Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371 Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372 Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374 Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388 Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389 Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393 Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394 Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395 Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396 Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397 Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398 Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399 Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401 Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402 Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404 Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405 Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406 Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407 Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408 Ethernet Controller ...................................................................................................................... 409 Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 418 Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 420 Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 421 Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 422 Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 423 Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 424 Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 426 November 30, 2007 17 Preliminary LM3S6952 Microcontroller Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 427 Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 428 Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 429 Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 430 Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 431 Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 432 Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 433 Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 434 Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 435 Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 437 Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 439 Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 440 Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 ............................................................................................................................. 441 Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 ..................................................................................................... 443 Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 ............................................................................................................................. 444 Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 445 Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 .............................................................................................................................. 447 Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 449 Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 450 Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 451 Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 452 Analog Comparators ................................................................................................................... 453 Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 459 Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 460 Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 461 Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 462 Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 463 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 463 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 463 Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 464 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 464 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 464 Pulse Width Modulator (PWM) .................................................................................................... 466 Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 473 Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 474 Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 475 Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 476 Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 477 Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 478 Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 479 Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 480 Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 481 Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 482 Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 482 18 November 30, 2007 Preliminary Table of Contents Register 12: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 484 Register 13: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 484 Register 14: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 486 Register 15: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 486 Register 16: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 487 Register 17: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 487 Register 18: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 488 Register 19: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 488 Register 20: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 489 Register 21: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 489 Register 22: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 490 Register 23: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 490 Register 24: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 491 Register 25: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 491 Register 26: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 492 Register 27: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 492 Register 28: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 495 Register 29: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 495 Register 30: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 498 Register 31: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 498 Register 32: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 499 Register 33: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 499 Register 34: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 500 Register 35: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 500 Quadrature Encoder Interface (QEI) .......................................................................................... 501 Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 506 Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 508 Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 509 Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 510 Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 511 Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 512 Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 513 Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 514 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 515 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 516 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 517 November 30, 2007 19 Preliminary LM3S6952 Microcontroller About This Document This data sheet provides reference information for the LM3S6952 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ■ ARM® Cortex™-M3 Technical Reference Manual ■ ARM® CoreSight Technical Reference Manual ■ ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 1 on page 20. Table 1. Documentation Conventions Notation Meaning General Register Notation APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. REGISTER bit A single bit in a register. bit field Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 43. offset 0xnnn Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register N 20 November 30, 2007 Preliminary About This Document Notation Meaning Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. yy:xx This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Register Bit/Field Types RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. W1C WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted. Reset Value 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). assert a signal deassert a signal Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. SIGNAL Numbers An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. X Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x November 30, 2007 21 Preliminary LM3S6952 Microcontroller 1 Architectural Overview The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris® family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris® LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. The Stellaris® LM3S2000 series also marks the first integration of CAN capabilities with the revolutionary Cortex-M3 core. The Stellaris® LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an ARM architecture MCU. The Stellaris® LM3S8000 series combines Bosch Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer. The LM3S6952 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S6952 microcontroller features a Battery-backed Hibernation module to efficiently power down the LM3S6952 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S6952 microcontroller perfectly for battery applications. In addition, the LM3S6952 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S6952 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise needs. Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. 1.1 Product Features The LM3S6952 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications 22 November 30, 2007 Preliminary Architectural Overview – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 34 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ Internal Memory – 256 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 64 KB single-cycle SRAM ■ General-Purpose Timers – Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. Each GPTM can be configured to operate independently: • As a single 32-bit timer • As one 32-bit Real-Time Clock (RTC) to event capture • For Pulse Width Modulation (PWM) • To trigger analog-to-digital conversions – 32-bit Timer modes • Programmable one-shot timer • Programmable periodic timer • Real-Time Clock when using an external 32.768-KHz clock as the input November 30, 2007 23 Preliminary LM3S6952 Microcontroller • User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug • ADC event trigger – 16-bit Timer modes • General-purpose timer function with an 8-bit prescaler • Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug • ADC event trigger – 16-bit Input Capture modes • Input edge count capture • Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ 10/100 Ethernet Controller – Conforms to the IEEE 802.3-2002 Specification – Full- and half-duplex for both 100 Mbps and 10 Mbps operation – Integrated 10/100 Mbps Transceiver (PHY) – Automatic MDI/MDI-X cross-over correction – Programmable MAC address – Power-saving and power-down modes ■ Synchronous Serial Interface (SSI) 24 November 30, 2007 Preliminary Architectural Overview – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ UART – Three fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator with fractional divider – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – False-start-bit detection – Line-break generation and detection ■ ADC – Single- and differential-input configurations – Three 10-bit channels (inputs) when used as single-ended inputs – Sample rate of 500 thousand samples/second – Flexible, configurable analog-to-digital conversion – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs – Each sequence triggered by software or internal event (timers, analog comparators, PWM or GPIO) – On-chip temperature sensor ■ Analog Comparators – Three independent integrated analog comparators November 30, 2007 25 Preliminary LM3S6952 Microcontroller – Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence – Compare external pin input to external pin input or to internal programmable voltage reference ■ I2C – Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode – Interrupt generation – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ PWM – Two PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator, and a dead-band generator – One 16-bit counter • Runs in Down or Up/Down mode • Output frequency controlled by a 16-bit load value • Load value updates can be synchronized • Produces output signals at zero and load value – Two PWM comparators • Comparator value updates can be synchronized • Produces output signals on match – PWM generator • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals • Produces two independent PWM signals – Dead-band generator • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge • Can be bypassed, leaving input PWM signals unmodified – Flexible output control block with PWM output enable of each PWM signal • PWM output enable of each PWM signal • Optional output inversion of each PWM signal (polarity control) 26 November 30, 2007 Preliminary Architectural Overview • Optional fault handling for each PWM signal • Synchronization of timers in the PWM generator blocks • Synchronization of timer/comparator updates across the PWM generator blocks • Interrupt status summary of the PWM generator blocks – Can initiate an ADC sample sequence ■ QEI – Hardware position integrator tracks the encoder position – Velocity capture using built-in timer – Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature error detection ■ GPIOs – 6-43 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable interrupt generation as either edge-triggered or level-sensitive – Bit masking in both read and write operations through address lines – Can initiate an ADC sample sequence – Programmable control for GPIO pad configuration: • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – User-enabled LDO unregulated voltage detection and automatic reset November 30, 2007 27 Preliminary LM3S6952 Microcontroller – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Additional Features – Six reset sources – Programmable clock source control – Clock gating to individual peripherals for power savings – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces – Full JTAG boundary scan ■ Industrial-range 100-pin RoHS-compliant LQFP package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 28 November 30, 2007 Preliminary Architectural Overview 1.3 High-Level Block Diagram Figure 1-1 on page 29 represents the full set of features in the Stellaris® 6000 series of devices; not all features may be available on the LM3S6952 microcontroller. Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram 1.4 Functional Overview The following sections provide an overview of the features of the LM3S6952 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 575. November 30, 2007 29 Preliminary LM3S6952 Microcontroller 1.4.1 ARM Cortex™-M3 1.4.1.1 Processor Core (see page 37) All members of the Stellaris® product family, including the LM3S6952 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. “ARM Cortex-M3 Processor Core” on page 37 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.1.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 Nested Vectored Interrupt Controller (NVIC) The LM3S6952 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 34 interrupts. “Interrupts” on page 45 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S6952 controller features Pulse Width Modulation (PWM) outputs and the Quadrature Encoder Interface (QEI). 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square 30 November 30, 2007 Preliminary Architectural Overview wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S6952, PWM motion control functionality can be achieved through: ■ Dedicated, flexible motion control hardware using the PWM pins ■ The motion control features of the general-purpose timers using the CCP pins PWM Pins (see page 466) The LM3S6952 PWM module consists of two PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. CCP Pins (see page 210) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.2.2 QEI (see page 501) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. 1.4.3 Analog Peripherals To handle analog signals, the LM3S6952 microcontroller offers an Analog-to-Digital Converter (ADC). For support of analog signals, the LM3S6952 microcontroller offers three analog comparators. 1.4.3.1 ADC (see page 263) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The LM3S6952 ADC module features 10-bit conversion resolution and supports three input channels, plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 1.4.3.2 Analog Comparators (see page 453) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. November 30, 2007 31 Preliminary LM3S6952 Microcontroller The LM3S6952 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 1.4.4 Serial Communications Peripherals The LM3S6952 controller supports both asynchronous and synchronous serial communications with: ■ Three fully programmable 16C550-type UARTs ■ One SSI module ■ One I2C module ■ Ethernet controller 1.4.4.1 UART (see page 296) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S6952 controller includes three fully programmable 16C550-type UARTs that support data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 337) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The LM3S6952 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. 32 November 30, 2007 Preliminary Architectural Overview The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 374) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S6952 controller includes one I2C module that provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.4.4 Ethernet Controller (see page 409) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 163) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris® GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 6-43 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 519 for the signals available to each GPIO pin). November 30, 2007 33 Preliminary LM3S6952 Microcontroller The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 Three Programmable Timers (see page 204) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 240) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S6952 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 139) The LM3S6952 static random access memory (SRAM) controller supports 64 KB SRAM. The internal SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 140) The LM3S6952 Flash controller supports 256 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 34 November 30, 2007 Preliminary Architectural Overview 1.4.7 Additional Features 1.4.7.1 Memory Map (see page 43) A memory map lists the location of instructions and data in memory. The memory map for the LM3S6952 controller can be found in “Memory Map” on page 43. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (see page 48) The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (see page 59) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.7.4 Hibernation Module (see page 120) The Hibernation module provides logic to switch power off to the main processor and peripherals, and to wake on external or time-based events. The Hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 518 ■ “Signal Tables” on page 519 ■ “Operating Characteristics” on page 533 ■ “Electrical Characteristics” on page 534 November 30, 2007 35 Preliminary LM3S6952 Microcontroller ■ “Package Information” on page 549 36 November 30, 2007 Preliminary Architectural Overview 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution with a: – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual. November 30, 2007 37 Preliminary LM3S6952 Microcontroller 2.1 Block Diagram Figure 2-1. CPU Block Diagram Private Peripheral Bus (internal) Data Watchpoint and Trace Interrupts Debug Sleep Instrumentation Trace Macrocell Trace Port Interface Unit CM3 Core Instructions Data Flash Patch and Breakpoint Memory Protection Unit Adv. High- Perf. Bus Access Port Nested Vectored Interrupt Controller Serial Wire JTAG Debug Port Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus ROM Table Private Peripheral Bus (external) Serial Wire Output Trace Port (SWO) ARM Cortex-M3 2.2 Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris® implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 38. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow. 2.2.1 Serial Wire and JTAG Debug Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. 38 November 30, 2007 Preliminary ARM Cortex-M3 Processor Core 2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 39. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram ATB Interface Asynchronous FIFO APB Interface Trace Out (serializer) Debug ATB Slave Port APB Slave Port Serial Wire Trace Port (SWO) 2.2.4 ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S6952 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling ■ Controls power management ■ Implements system control registers November 30, 2007 39 Preliminary LM3S6952 Microcontroller The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault. All NVIC registers are accessible using byte, halfword, and word unless otherwise stated. All NVIC registers and system debug registers are little endian regardless of the endianness state of the processor. 2.2.6.1 Interrupts The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S6952 microcontroller supports 34 interrupts with eight priority levels. 2.2.6.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. Functional Description The timer consists of three registers: ■ A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ The reload value for the counter, used to provide the counter's wrap value. ■ The current value of the counter. A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices. When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks. Writing a value of zero to the Reload Value register disables the counter on the next wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. 40 November 30, 2007 Preliminary ARM Cortex-M3 Processor Core Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0 Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 16 COUNTFLAG R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:3 reserved RO 0 0 = external reference clock. (Not implemented for Stellaris microcontrollers.) 1 = core clock. If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 2 CLKSOURCE R/W 0 1 = counting down to 0 pends the SysTick handler. 0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0. 1 TICKINT R/W 0 1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 0 = counter disabled. 0 ENABLE R/W 0 SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0 November 30, 2007 41 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description 23:0 RELOAD W1C - Value to load into the SysTick Current Value Register when the counter reaches 0. SysTick Current Value Register Use the SysTick Current Value Register to find the current value in the register. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0 Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 23:0 CURRENT W1C - SysTick Calibration Value Register The SysTick Calibration Value register is not implemented. 42 November 30, 2007 Preliminary ARM Cortex-M3 Processor Core 3 Memory Map The memory map for the LM3S6952 controller is provided in Table 3-1 on page 43. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. Important: In Table 3-1 on page 43, addresses not listed are reserved. Table 3-1. Memory Mapa For details on registers, see page ... Start End Description Memory 0x0000.0000 0x0003.FFFF On-chip flash b 143 0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAMc 143 0x2010.0000 0x21FF.FFFF Reserved non-bit-banded SRAM space - 0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 139 0x2400.0000 0x3FFF.FFFF Reserved non-bit-banded SRAM space - FiRM Peripherals 0x4000.0000 0x4000.0FFF Watchdog timer 242 0x4000.4000 0x4000.4FFF GPIO Port A 169 0x4000.5000 0x4000.5FFF GPIO Port B 169 0x4000.6000 0x4000.6FFF GPIO Port C 169 0x4000.7000 0x4000.7FFF GPIO Port D 169 0x4000.8000 0x4000.8FFF SSI0 348 0x4000.C000 0x4000.CFFF UART0 303 0x4000.D000 0x4000.DFFF UART1 303 0x4000.E000 0x4000.EFFF UART2 303 Peripherals 0x4002.0000 0x4002.07FF I2C Master 0 387 0x4002.0800 0x4002.0FFF I2C Slave 0 400 0x4002.4000 0x4002.4FFF GPIO Port E 169 0x4002.5000 0x4002.5FFF GPIO Port F 169 0x4002.6000 0x4002.6FFF GPIO Port G 169 0x4002.8000 0x4002.8FFF PWM 472 0x4002.C000 0x4002.CFFF QEI0 505 0x4003.0000 0x4003.0FFF Timer0 215 0x4003.1000 0x4003.1FFF Timer1 215 0x4003.2000 0x4003.2FFF Timer2 215 0x4003.8000 0x4003.8FFF ADC 269 0x4003.C000 0x4003.CFFF Analog Comparators 453 0x4004.8000 0x4004.8FFF Ethernet Controller 417 0x400F.C000 0x400F.CFFF Hibernation Module 126 November 30, 2007 43 Preliminary LM3S6952 Microcontroller For details on registers, see page ... Start End Description 0x400F.D000 0x400F.DFFF Flash control 143 0x400F.E000 0x400F.EFFF System control 66 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - Private Peripheral Bus ARM® Cortex™-M3 Technical Reference Manual 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 0xE000.3000 0xE000.DFFF Reserved 0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC) 0xE000.F000 0xE003.FFFF Reserved 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 0xE004.1000 0xE004.1FFF Reserved - 0xE004.2000 0xE00F.FFFF Reserved - 0xE010.0000 0xFFFF.FFFF Reserved for vendor peripherals - a. All reserved space returns a bus fault when read or written. b. The unavailable flash will bus fault throughout this range. c. The unavailable SRAM will bus fault throughout this range. 44 November 30, 2007 Preliminary Memory Map 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 on page 45 lists all the exceptions. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 34 interrupts (listed in Table 4-2 on page 46). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts. Note: In Table 4-2 on page 46 interrupts not listed are reserved. Table 4-1. Exception Types Exception Type Position Prioritya Description - 0 - Stack top is loaded from first entry of vector table on reset. Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. Reset 1 -3 (highest) Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Non-Maskable 2 -2 Interrupt (NMI) All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. Hard Fault 3 -1 MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. Memory Management 4 settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Bus Fault 5 settable Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Usage Fault 6 settable - 7-10 - Reserved. SVCall 11 settable System service call with SVC instruction. This is synchronous. November 30, 2007 45 Preliminary LM3S6952 Microcontroller Exception Type Position Prioritya Description Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Debug Monitor 12 settable - 13 - Reserved. Pendable request for system service. This is asynchronous and only pended by software. PendSV 14 settable SysTick 15 settable System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 on page 46 lists the interrupts on the LM3S6952 controller. 16 and settable above Interrupts a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Interrupt (Bit in Interrupt Registers) Description 0 GPIO Port A 1 GPIO Port B 2 GPIO Port C 3 GPIO Port D 4 GPIO Port E 5 UART0 6 UART1 7 SSI0 8 I2C0 9 PWM Fault 10 PWM Generator 0 11 PWM Generator 1 13 QEI0 14 ADC Sequence 0 15 ADC Sequence 1 16 ADC Sequence 2 17 ADC Sequence 3 18 Watchdog timer 19 Timer0 A 20 Timer0 B 21 Timer1 A 22 Timer1 B 23 Timer2 A 24 Timer2 B 25 Analog Comparator 0 26 Analog Comparator 1 27 Analog Comparator 2 28 System Control 29 Flash Control 30 GPIO Port F 46 November 30, 2007 Preliminary Interrupts Interrupt (Bit in Interrupt Registers) Description 31 GPIO Port G 33 UART2 42 Ethernet Controller 43 Hibernation Module November 30, 2007 47 Preliminary LM3S6952 Microcontroller 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. The JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: – BYPASS instruction – IDCODE instruction – SAMPLE/PRELOAD instruction – EXTEST instruction – INTEST instruction ■ ARM additional instructions: – APACC instruction – DPACC instruction – ABORT instruction ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. 48 November 30, 2007 Preliminary JTAG Interface 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram Instruction Register (IR) TAP Controller BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TRST TCK TMS TDI TDO Cortex-M3 Debug Port 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 49. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 55 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 545 for JTAG timing diagrams. November 30, 2007 49 Preliminary LM3S6952 Microcontroller 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1 on page 50. Detailed information on each pin follows. Table 5-1. JTAG Port Pins Reset State Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TRST Input Enabled Disabled N/A N/A TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z 5.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 52. 50 November 30, 2007 Preliminary JTAG Interface By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 52. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. November 30, 2007 51 Preliminary LM3S6952 Microcontroller Figure 5-2. Test Access Port State Machine Test Logic Reset Run Test Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit 1 DR Exit 1 IR Exit 2 DR Exit 2 IR Pause DR Pause IR Update DR Update IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 55. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 52 November 30, 2007 Preliminary JTAG Interface 5.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. Recovering a "Locked" Device If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 11. Perform the SWD-to-JTAG switch sequence. November 30, 2007 53 Preliminary LM3S6952 Microcontroller 12. Release the RST signal. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 54. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 54 November 30, 2007 Preliminary JTAG Interface 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 5.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 5.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 55. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. JTAG Instruction Register Commands IR[3:0] Instruction Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0001 INTEST Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 0010 SAMPLE / PRELOAD 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1110 IDCODE 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. 5.4.1.1 EXTEST Instruction The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows November 30, 2007 55 Preliminary LM3S6952 Microcontroller tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.4.1.2 INTEST Instruction The INTEST instruction does not have an associated Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 58 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 58 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 58 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 58 for more information. 56 November 30, 2007 Preliminary JTAG Interface 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 57 for more information. 5.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 57 for more information. 5.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 5.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3 on page 57. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. IDCODE Register Format 5.4.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4 on page 58. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. November 30, 2007 57 Preliminary LM3S6952 Microcontroller Figure 5-4. BYPASS Register Format 5.4.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 58. Each GPIO pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the Data Register chain. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. Boundary Scan Register Format O TDO TDI O IN E UT O O IN U E T O O IN E UT O O IN U E T I N ... ... GPIO PB6 GPIO m RST GPIO m+1 GPIO n For detailed information on the order of the input, output, and output enable bits for each of the GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files, downloadable from www.luminarymicro.com. 5.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 58 November 30, 2007 Preliminary JTAG Interface 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 59 ■ Local control, such as reset (see “Reset Control” on page 59), power (see “Power Control” on page 62) and clock control (see “Clock Control” on page 62) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 64 6.1.1 Device Identification Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 6.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 59. 2. Power-on reset (POR), see “Power-On Reset (POR)” on page 60. 3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 60. 4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 61. 5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 61. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 6.1.2.3 RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see “JTAG Interface” on page 48). The external reset sequence is as follows: November 30, 2007 59 Preliminary LM3S6952 Microcontroller 1. The external reset pin (RST) is asserted and then de-asserted. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for synchronization. The external reset timing is shown in Figure 23-11 on page 547. 6.1.2.4 Power-On Reset (POR) The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit generates a reset signal to the internal logic when the power supply ramp reaches a threshold value (VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power supply (VDD) through a pull-up resistor (1K to 10K Ω). The device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within 10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset to hold the device in reset longer than the internal POR, the RST input may be used with the circuit as shown in Figure 6-1 on page 60. Figure 6-1. External Circuitry to Extend Reset R1 C1 R2 RST Stellaris D1 The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 23-12 on page 548. Note: The power-on reset also resets the JTAG controller. An external reset does not. 6.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. 60 November 30, 2007 Preliminary System Control Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivelent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 23-13 on page 548. 6.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 64). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 23-14 on page 548. 6.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. November 30, 2007 61 Preliminary LM3S6952 Microcontroller The watchdog reset timing is shown in Figure 23-15 on page 548. 6.1.3 Power Control The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. The LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25 pins on the printed circuit board. The LDO requires decoupling capacitors on the printed circuit board. If an external regulator is used, it is strongly recommended that the external regulator supply the controller only and not be shared with other devices on the printed circuit board. 6.1.4 Clock Control System control determines the control of clocks in this part. 6.1.4.1 Fundamental Clock Sources There are four clock sources for use in the device: ■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed depends on whether the main oscillator is used as the clock reference source to the PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit in the RCC register (see page 75). ■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. ■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency, accurate clock reference. It is intended to provide the system with a real-time clock source. The real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 120) and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (sysclk), is derived from any of the four sources plus two others: the output of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). 62 November 30, 2007 Preliminary System Control The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. 6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 75) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 6.1.4.3 PLL Frequency Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required. Software configures the PLL input reference clock source, specifies the output divisor to set the system clock frequency, and enables the PLL to drive the output. If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 79). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. The Crystal Value field (XTAL) on page 75 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 6.1.4.4 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 75 and page 80). 6.1.4.5 PLL Operation If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 23-6 on page 537). During this time, the PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set November 30, 2007 63 Preliminary LM3S6952 Microcontroller to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. 6.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor is not clocked and therefore no longer executes code. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Each mode is described in more detail below. There are four levels of operation for the device defined as: ■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. ■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside 64 November 30, 2007 Preliminary System Control of the Hibernation module see a normal "power on" sequence and the processor starts running code. It can determine that it has been restarted from Hibernate mode by inspecting the Hibernation module registers. 6.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source (using the main oscillator or internal oscillator) and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 6.3 Register Map Table 6-1 on page 65 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register’s address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use by Luminary Micro, Inc. Software should not modify any reserved memory address. Table 6-1. System Control Register Map See Offset Name Type Reset Description page 0x000 DID0 RO - Device Identification 0 67 0x004 DID1 RO - Device Identification 1 83 0x008 DC0 RO 0x00FF.007F Device Capabilities 0 85 0x010 DC1 RO 0x0011.32FF Device Capabilities 1 86 0x014 DC2 RO 0x0707.1117 Device Capabilities 2 88 0x018 DC3 RO 0x0F07.BFCF Device Capabilities 3 90 0x01C DC4 RO 0x5000.007F Device Capabilities 4 92 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 69 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 70 November 30, 2007 65 Preliminary LM3S6952 Microcontroller See Offset Name Type Reset Description page 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 115 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 116 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 118 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 71 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 72 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 73 0x05C RESC R/W - Reset Cause 74 0x060 RCC R/W 0x07AE.3AD1 Run-Mode Clock Configuration 75 0x064 PLLCFG RO - XTAL to PLL Translation 79 0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 80 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 94 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 100 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 109 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 96 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 103 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 111 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 98 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 106 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 113 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 82 6.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. 66 November 30, 2007 Preliminary System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved VER reserved CLASS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description First revision of the DID0 register format, for Stellaris® Fury-class devices . 0x1 30:28 VER RO 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:24 reserved RO 0x0 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x0 Stellaris® Sandstorm-class devices. 0x1 Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 November 30, 2007 67 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 15:8 MAJOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. 7:0 MINOR RO - 68 November 30, 2007 Preliminary System Control Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BORIOR reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 1 BORIOR R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 November 30, 2007 69 Preliminary LM3S6952 Microcontroller Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VADJ Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 5:0 VADJ R/W 0x0 70 November 30, 2007 Preliminary System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLRIS reserved BORRIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 6 PLLLRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 1 BORRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 November 30, 2007 71 Preliminary LM3S6952 Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLIM reserved BORIM reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 1 BORIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 72 November 30, 2007 Preliminary System Control Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 71). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLMIS reserved BORMIS reserved Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 1 BORMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 November 30, 2007 73 Preliminary LM3S6952 Microcontroller Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LDO SW WDT BOR POR EXT Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Reset When set, indicates the LDO circuit has lost regulation and has generated a reset event. 5 LDO R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 4 SW R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 3 WDT R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 2 BOR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 1 POR R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. 0 EXT R/W - 74 November 30, 2007 Preliminary System Control Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x07AE.3AD1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0x0 Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 27 ACG R/W 0 November 30, 2007 75 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. Value Divisor (BYPASS=1) Frequency (BYPASS=0) 0x0 reserved reserved 0x1 /2 reserved 0x2 /3 reserved 0x3 /4 50 MHz 0x4 /5 40 MHz 0x5 /6 33.33 MHz 0x6 /7 28.57 MHz 0x7 /8 25 MHz 0x8 /9 22.22 MHz 0x9 /10 20 MHz 0xA /11 18.18 MHz 0xB /12 16.67 MHz 0xC /13 15.38 MHz 0xD /14 14.29 MHz 0xE /15 13.33 MHz 0xF /16 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 75), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 26:23 SYSDIV R/W 0xF Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. 22 USESYSDIV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21 reserved RO 0 Enable PWM Clock Divisor Use the PWM clock divider as the source for the PWM clock. 20 USEPWMDIV R/W 0 76 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. This clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. Value Divisor 0x0 /2 0x1 /4 0x2 /8 0x3 /16 0x4 /32 0x5 /64 0x6 /64 0x7 /64 (default) 19:17 PWMDIV R/W 0x7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16:14 reserved RO 0 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 13 PWRDN R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. Note: The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. While the ADC works in a 14-18 MHz range, to maintain a 1 M sample/second rate, the ADC must be provided a 16-MHz clock source. 11 BYPASS R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 reserved RO 0 November 30, 2007 77 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value 0x0 1.000 reserved 0x1 1.8432 reserved 0x2 2.000 reserved 0x3 2.4576 reserved 0x4 3.579545 MHz 0x5 3.6864 MHz 0x6 4 MHz 0x7 4.096 MHz 0x8 4.9152 MHz 0x9 5 MHz 0xA 5.12 MHz 0xB 6 MHz (reset value) 0xC 6.144 MHz 0xD 7.3728 MHz 0xE 8 MHz 0xF 8.192 MHz 9:6 XTAL R/W 0xB Oscillator Source Picks among the four input sources for the OSC. The values are: Value Input Source 0x0 Main oscillator (default) 0x1 Internal oscillator (default) 0x2 Internal oscillator / 4 (this is necessary if used as input to PLL) 0x3 reserved 5:4 OSCSRC R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 Main Oscillator Disable 0: Main oscillator is enabled. 1: Main oscillator is disabled (default). 0 MOSCDIS R/W 1 78 November 30, 2007 Preliminary System Control Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 75). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved F R Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x0 PLL F Value This field specifies the value supplied to the PLL’s F input. 13:5 F RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 4:0 R RO - November 30, 2007 79 Preliminary LM3S6952 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified. The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system clock frequency for improved Deep Sleep power consumption. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 USERCC2 reserved SYSDIV2 reserved Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Use RCC2 When set, overrides the RCC register fields. 31 USERCC2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30:29 reserved RO 0x0 System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. This field is wider than the RCC register SYSDIV field in order to provide additional divisor values. This permits the system clock to be run at much lower frequencies during Deep Sleep mode. For example, where the RCC register SYSDIV encoding of 1111 provides /16, the RCC2 register SYSDIV2 encoding of 111111 provides /64. 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:14 reserved RO 0x0 Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 Bypass PLL When set, bypasses the PLL for the clock source. 11 BYPASS2 R/W 1 80 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:7 reserved RO 0x0 System Clock Source Value Description 0x0 Main oscillator (MOSC) 0x1 Internal oscillator (IOSC) 0x2 Internal oscillator / 4 0x3 30 kHz internal oscillator 0x7 32 kHz external oscillator 6:4 OSCSRC2 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0 November 30, 2007 81 Preliminary LM3S6952 Microcontroller Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DSDIVORIDE reserved Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DSOSCSRC reserved Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:29 reserved RO 0x0 Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 28:23 DSDIVORIDE R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:7 reserved RO 0x0 Clock Source When set, forces IOSC to be clock source during Deep Sleep mode. Value Name Description 0x0 NOORIDE No override to the oscillator clock source is done 0x1 IOSC Use internal 12 MHz oscillator as source 0x3 30kHz Use 30 kHz internal oscillator 0x7 32kHz Use 32 kHz external oscillator 6:4 DSOSCSRC R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x0 82 November 30, 2007 Preliminary System Control Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VER FAM PARTNO Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINCOUNT reserved TEMP PKG ROHS QUAL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 0 0 0 1 0 1 1 - - Bit/Field Name Type Reset Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description First revision of the DID1 register format, indicating a Stellaris Fury-class device. 0x1 31:28 VER RO 0x1 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 0x0 27:24 FAM RO 0x0 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x78 LM3S6952 23:16 PARTNO RO 0x78 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin package 15:13 PINCOUNT RO 0x2 November 30, 2007 83 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:8 reserved RO 0 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 Industrial temperature range (-40°C to 85°C) 7:5 TEMP RO 0x1 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 LQFP package 4:3 PKG RO 0x1 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 2 ROHS RO 1 Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 1:0 QUAL RO - 84 November 30, 2007 Preliminary System Control Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 31:16 SRAMSZ RO 0x00FF Flash Size Indicates the size of the on-chip flash memory. Value Description 0x007F 256 KB of Flash 15:0 FLASHSZ RO 0x007F November 30, 2007 85 Preliminary LM3S6952 Microcontroller Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0011.32FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Module Present When set, indicates that the PWM module is present. 20 PWM RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC Module Present When set, indicates that the ADC module is present. 16 ADC RO 1 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 15:12 MINSYSDIV RO 0x3 Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x2 500K samples/second 11:8 MAXADCSPD RO 0x2 86 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 7 MPU RO 1 Hibernation Module Present When set, indicates that the Hibernation module is present. 6 HIB RO 1 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 5 TEMPSNS RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 4 PLL RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 3 WDT RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 2 SWO RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 1 SWD RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 0 JTAG RO 1 November 30, 2007 87 Preliminary LM3S6952 Microcontroller Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x0707.1117 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 26 COMP2 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 25 COMP1 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 24 COMP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 18 TIMER2 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 17 TIMER1 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 16 TIMER0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C Module 0 Present When set, indicates that I2C module 0 is present. 12 I2C0 RO 1 88 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0 QEI0 Present When set, indicates that QEI module 0 is present. 8 QEI0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 reserved RO 0 SSI0 Present When set, indicates that SSI module 0 is present. 4 SSI0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Present When set, indicates that UART module 2 is present. 2 UART2 RO 1 UART1 Present When set, indicates that UART module 1 is present. 1 UART1 RO 1 UART0 Present When set, indicates that UART module 0 is present. 0 UART0 RO 1 November 30, 2007 89 Preliminary LM3S6952 Microcontroller Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x0F07.BFCF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CCP3 CCP2 CCP1 CCP0 reserved ADC2 ADC1 ADC0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWMFAULT reserved C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved PWM3 PWM2 PWM1 PWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 27 CCP3 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 26 CCP2 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 25 CCP1 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 24 CCP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 ADC2 Pin Present When set, indicates that ADC pin 2 is present. 18 ADC2 RO 1 ADC1 Pin Present When set, indicates that ADC pin 1 is present. 17 ADC1 RO 1 ADC0 Pin Present When set, indicates that ADC pin 0 is present. 16 ADC0 RO 1 PWM Fault Pin Present When set, indicates that the PWM Fault pin is present. 15 PWMFAULT RO 1 90 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 reserved RO 0 C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. 13 C2PLUS RO 1 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. 12 C2MINUS RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 11 C1O RO 1 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 10 C1PLUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 9 C1MINUS RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 8 C0O RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 7 C0PLUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 6 C0MINUS RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 3 PWM3 RO 1 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 2 PWM2 RO 1 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 1 PWM1 RO 1 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 0 PWM0 RO 1 November 30, 2007 91 Preliminary LM3S6952 Microcontroller Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5000.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 Ethernet PHY0 Present When set, indicates that Ethernet PHY module 0 is present. 30 EPHY0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 Ethernet MAC0 Present When set, indicates that Ethernet MAC module 0 is present. 28 EMAC0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 GPIO Port G Present When set, indicates that GPIO Port G is present. 6 GPIOG RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 5 GPIOF RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 4 GPIOE RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 3 GPIOD RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 2 GPIOC RO 1 92 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description GPIO Port B Present When set, indicates that GPIO Port B is present. 1 GPIOB RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 0 GPIOA RO 1 November 30, 2007 93 Preliminary LM3S6952 Microcontroller Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 reserved RO 0 94 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 11:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 95 Preliminary LM3S6952 Microcontroller Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 reserved RO 0 96 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 11:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 97 Preliminary LM3S6952 Microcontroller Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 reserved RO 0 98 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 11:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 99 Preliminary LM3S6952 Microcontroller Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0 Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 100 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 8 QEI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 November 30, 2007 101 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 102 November 30, 2007 Preliminary System Control Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0 Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 November 30, 2007 103 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 8 QEI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 104 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 November 30, 2007 105 Preliminary LM3S6952 Microcontroller Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0 Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 106 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 8 QEI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 November 30, 2007 107 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 108 November 30, 2007 Preliminary System Control Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 November 30, 2007 109 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 110 November 30, 2007 Preliminary System Control Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 November 30, 2007 111 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 112 November 30, 2007 Preliminary System Control Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 November 30, 2007 113 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 114 November 30, 2007 Preliminary System Control Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved HIB reserved WDT reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Reset Control Reset control for PWM module. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC0 Reset Control Reset control for SAR ADC module 0. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:7 reserved RO 0 HIB Reset Control Reset control for the Hibernation module. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Reset Control Reset control for Watchdog unit. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 115 Preliminary LM3S6952 Microcontroller Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0 Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comp 2 Reset Control Reset control for analog comparator 2. 26 COMP2 R/W 0 Analog Comp 1 Reset Control Reset control for analog comparator 1. 25 COMP1 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 18 TIMER2 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 17 TIMER1 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Reset Control Reset control for I2C unit 0. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0 116 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description QEI0 Reset Control Reset control for QEI unit 0. 8 QEI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 reserved RO 0 SSI0 Reset Control Reset control for SSI unit 0. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Reset Control Reset control for UART unit 2. 2 UART2 R/W 0 UART1 Reset Control Reset control for UART unit 1. 1 UART1 R/W 0 UART0 Reset Control Reset control for UART unit 0. 0 UART0 R/W 0 November 30, 2007 117 Preliminary LM3S6952 Microcontroller Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Reset Control Reset control for Ethernet PHY unit 0. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Reset Control Reset control for Ethernet MAC unit 0. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 Port G Reset Control Reset control for GPIO Port G. 6 GPIOG R/W 0 Port F Reset Control Reset control for GPIO Port F. 5 GPIOF R/W 0 Port E Reset Control Reset control for GPIO Port E. 4 GPIOE R/W 0 Port D Reset Control Reset control for GPIO Port D. 3 GPIOD R/W 0 Port C Reset Control Reset control for GPIO Port C. 2 GPIOC R/W 0 Port B Reset Control Reset control for GPIO Port B. 1 GPIOB R/W 0 118 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Port A Reset Control Reset control for GPIO Port A. 0 GPIOA R/W 0 November 30, 2007 119 Preliminary LM3S6952 Microcontroller 7 Hibernation Module The Hibernation Module manages removal and restoration of power to the rest of the microcontroller to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation Module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in real-time clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: ■ Power-switching logic to discrete external regulator ■ Dedicated pin for waking from an external signal ■ Low-battery detection, signaling, and interrupt generation ■ 32-bit real-time counter (RTC) ■ Two 32-bit RTC match registers for timed wake-up and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal ■ RTC predivider trim for making fine adjustments to the clock rate ■ 64 32-bit words of non-volatile memory ■ Programmable interrupts for RTC match, external wake, and low battery events 120 November 30, 2007 Preliminary Hibernation Module 7.1 Block Diagram Figure 7-1. Hibernation Module Block Diagram HIBIM HIBRIS HIBMIS HIBIC HIBRTCT Pre-Divider /128 XOSC0 XOSC1 HIBCTL.CLK32EN HIBCTL.CLKSEL HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 RTC Interrupts Power Sequence Logic MATCH0/1 WAKE Interrupts to CPU Low Battery Detect LOWBAT VDD VBAT HIB HIBCTL.LOWBATEN HIBCTL.PWRCUT HIBCTL.EXTWEN HIBCTL.RTCWEN HIBCTL.VABORT Non-Volatile Memory HIBDATA 7.2 Functional Description The Hibernation module controls the power to the processor with an enable signal (HIB) that signals an external voltage regulator to turn off. The Hibernation module power is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. The Hibernation module also has a separate clock source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low, and optionally prevent hibernation when this occurs. Power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 543). 7.2.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain Hibernation registers, or between a write followed by a read to those same registers. There is no November 30, 2007 121 Preliminary LM3S6952 Microcontroller restriction on timing for back-to-back reads from the Hibernation module. Refer to “Register Descriptions” on page 126 for details about which registers are subject to this timing restriction. 7.2.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature will not be used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator can be connected to the XOSC0 pin. The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a 32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. 7.2.3 Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage becomes too low. When this happens, an interrupt can be generated. The module can also be configured so that it will not go into Hibernate mode if the battery voltage is too low. Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 123). 7.2.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see “Clock Source” on page 122). The 32.768-kHz clock signal is fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate, and down from 0x7FFF in order to speed up the RTC rate. The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust 122 November 30, 2007 Preliminary Hibernation Module the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see “Interrupts and Status” on page 123). 7.2.5 Non-Volatile Memory The Hibernation module contains 64 32-bit words of memory which are retained during hibernation. This memory is powered from the battery or auxiliary power supply during hibernation. The processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. The non-volatile memory can be accessed through the HIBDATA registers. 7.2.6 Power Control The Hibernation module controls power to the processor through the use of the HIB pin, which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the microcontroller. The Hibernation module remains powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power supply as the logic 1 reference. When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 123) and by looking for state data in the non-volatile memory (see “Non-Volatile Memory” on page 123). When the HIB signal deasserts, enabling the external regulator, the external regulator must reach the operating voltage within tHIB_TO_VDD. 7.2.7 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register. November 30, 2007 123 Preliminary LM3S6952 Microcontroller 7.3 Initialization and Configuration The Hibernation module can be configured in several different combinations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access Timing” on page 121). The registers that require a delay are denoted with a footnote in Table 7-1 on page 125. 7.3.1 Initialization The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal is used, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any other operations with the Hibernation module. If a 32.678-kHz oscillator is used, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input. 2. No delay is necessary. The above is only necessary when the entire system is initialized for the first time. If the processor is powered due to a wake from hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. 7.3.2 RTC Match Functionality (No Hibernation) The following steps are needed to use the RTC match functionality of the Hibernation module: 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 7.3.3 RTC Match/Wake-Up from Hibernation The following steps are needed to use the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 124 November 30, 2007 Preliminary Hibernation Module 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 7.3.4 External Wake-Up from Hibernation The following steps are needed to use the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 7.3.5 RTC/External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 7.4 Register Map Table 7-1 on page 125 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 121. Table 7-1. Hibernation Module Register Map See Offset Name Type Reset Description page 0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 127 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 128 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 129 0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 130 0x010 HIBCTL R/W 0x0000.0000 Hibernation Control 131 0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 133 0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 134 0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 135 0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 136 0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 137 0x030- HIBDATA R/W 0x0000.0000 Hibernation Data 138 0x12C November 30, 2007 125 Preliminary LM3S6952 Microcontroller 7.5 Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. 126 November 30, 2007 Preliminary Hibernation Module Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description RTC Counter A read returns the 32-bit counter value. This register is read-only. To change the value, use the HIBRTCLD register. 31:0 RTCC RO 0x0000.0000 November 30, 2007 127 Preliminary LM3S6952 Microcontroller Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 31:0 RTCM0 R/W 0xFFFF.FFFF 128 November 30, 2007 Preliminary Hibernation Module Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCM1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. 31:0 RTCM1 R/W 0xFFFF.FFFF November 30, 2007 129 Preliminary LM3S6952 Microcontroller Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCLD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCLD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 31:0 RTCLD R/W 0xFFFF.FFFF 130 November 30, 2007 Preliminary Hibernation Module Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Power Cut Abort Enable 0: Power cut occurs during a low-battery alert 1: Power cut is aborted 7 VABORT R/W 0 32-kHz Oscillator Enable 0: Disabled 1: Enabled This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 6 CLK32EN R/W 0 Low Battery Monitoring Enable 0: Disabled 1: Enabled When set, low battery voltage detection is enabled. 5 LOWBATEN R/W 0 External WAKE Pin Enable 0: Disabled 1: Enabled When set, an external event on the WAKE pin will re-power the device. 4 PINWEN R/W 0 RTC Wake-up Enable 0: Disabled 1: Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. 3 RTCWEN R/W 0 November 30, 2007 131 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Hibernation Module Clock Select 0: Use Divide by 128 output. Use this value for a 4-MHz crystal. 1: Use raw output. Use this value for a 32-kHz oscillator. 2 CLKSEL R/W 0 Hibernation Request 0: Disabled 1: Hibernation initiated After a wake-up event, this bit is cleared by hardware. 1 HIBREQ R/W 0 RTC Timer Enable 0: Disabled 1: Enabled 0 RTCEN R/W 0 132 November 30, 2007 Preliminary Hibernation Module Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 External Wake-Up Interrupt Mask 0: Masked 1: Unmasked 3 EXTW R/W 0 Low Battery Voltage Interrupt Mask 0: Masked 1: Unmasked 2 LOWBAT R/W 0 RTC Alert1 Interrupt Mask 0: Masked 1: Unmasked 1 RTCALT1 R/W 0 RTC Alert0 Interrupt Mask 0: Masked 1: Unmasked 0 RTCALT0 R/W 0 November 30, 2007 133 Preliminary LM3S6952 Microcontroller Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Raw Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status 134 November 30, 2007 Preliminary Hibernation Module Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Masked Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status November 30, 2007 135 Preliminary LM3S6952 Microcontroller Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 External Wake-Up Masked Interrupt Clear Reads return an indeterminate value. 3 EXTW R/W1C 0 Low Battery Voltage Masked Interrupt Clear Reads return an indeterminate value. 2 LOWBAT R/W1C 0 RTC Alert1 Masked Interrupt Clear Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert0 Masked Interrupt Clear Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 136 November 30, 2007 Preliminary Hibernation Module Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRIM Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. The compensation is made by software by adjusting the default value of 0x7FFF up or down. 15:0 TRIM R/W 0x7FFF November 30, 2007 137 Preliminary LM3S6952 Microcontroller Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store any non-volatile state data and will not lose power during a power cut operation. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description 31:0 RTD R/W 0x0000.0000 Hibernation Module NV Registers[63:0] 138 November 30, 2007 Preliminary Hibernation Module 8 Internal Memory The LM3S6952 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 8.1 Block Diagram Figure 8-1. Flash Block Diagram Flash Control FMA FCMISC FCIM FCRIS FMC FMD Flash Timing USECRL Flash Protection FMPREn FMPPEn Flash Array SRAM Array Bridge Cortex-M3 ICode DCode System Bus APB User Registers USER_REG0 USER_REG1 USER_DBG 8.2 Functional Description This section describes the functionality of both the flash and SRAM memories. 8.2.1 SRAM Memory The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: November 30, 2007 139 Preliminary LM3S6952 Microcontroller bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. 8.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 551 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 8.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 8.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the DCode bus. The policies may be combined as shown in Table 8-1 on page 141. 140 November 30, 2007 Preliminary Internal Memory Table 8-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 0 0 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 0 1 1 1 No protection. The block may be written, erased, executed or read. An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 142. 8.3 Flash Memory Initialization and Configuration 8.3.1 Flash Programming The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. 8.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 8.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 8.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. November 30, 2007 141 Preliminary LM3S6952 Microcontroller 8.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the flash memory itself. These registers exist in a separate space from the main flash array and are not affected by an ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit in the FMC register to activate a write operation. For the USER_DBG register, the data to be written must be loaded into the FMD register before it is "committed". All other registers are R/W and can have their operation tried before committing them to nonvolatile memory. Important: These registers can only have bits changed from 1 to 0 by the user and there is no mechanism for the user to erase them back to a 1 value. In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective registers to indicate that they are available for user write. These three registers can only be written once whereas the flash protection registers may be written multiple times. Table 8-2 on page 142 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 8-2. Flash Resident Registersa Register to be Committed FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0008 FMPRE3 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_DBG 0x7510.0000 FMD a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device. 8.4 Register Map Table 8-3 on page 142 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System Control base address of 0x400F.E000. Table 8-3. Flash Register Map See Offset Name Type Reset Description page Flash Control Offset 0x000 FMA R/W 0x0000.0000 Flash Memory Address 144 142 November 30, 2007 Preliminary Internal Memory See Offset Name Type Reset Description page 0x004 FMD R/W 0x0000.0000 Flash Memory Data 145 0x008 FMC R/W 0x0000.0000 Flash Memory Control 146 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 148 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 149 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 150 System Control Offset 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 152 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 152 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 153 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 153 0x140 USECRL R/W 0x31 USec Reload 151 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 154 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 155 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 156 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 157 0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 158 0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 159 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 160 0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 161 0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 162 8.5 Flash Register Descriptions (Flash Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. November 30, 2007 143 Preliminary LM3S6952 Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved OFFSET Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:18 reserved RO 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 142 for details on values for this field). 17:0 OFFSET R/W 0x0 144 November 30, 2007 Preliminary Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Data Value Data value for write operation. 31:0 DATA R/W 0x0 November 30, 2007 145 Preliminary LM3S6952 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 144). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 145) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved COMT MERASE ERASE WRITE Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 31:16 WRKEY WO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:4 reserved RO 0x0 Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 3 COMT R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 2 MERASE R/W 0 146 November 30, 2007 Preliminary Internal Memory Bit/Field Name Type Reset Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 1 ERASE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 μs. 0 WRITE R/W 0 November 30, 2007 147 Preliminary LM3S6952 Microcontroller Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIS ARIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 146). 1 PRIS RO 0 Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPREn) and Flash Memory Protection Program Enable (FMPPEn) registers. Otherwise, no access has tried to improperly access the flash. 0 ARIS RO 0 148 November 30, 2007 Preliminary Internal Memory Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMASK AMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programming-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 1 PMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 0 AMASK R/W 0 November 30, 2007 149 Preliminary LM3S6952 Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMISC AMISC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 148) is also cleared when the PMISC bit is cleared. 1 PMISC R/W1C 0 Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. 0 AMISC R/W1C 0 8.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 150 November 30, 2007 Preliminary Internal Memory Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved USEC Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 7:0 USEC R/W 0x31 November 30, 2007 151 Preliminary LM3S6952 Microcontroller Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.D000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF 152 November 30, 2007 Preliminary Internal Memory Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.D000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF November 30, 2007 153 Preliminary LM3S6952 Microcontroller Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DBG1 DBG0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Bit/Field Name Type Reset Description User Debug Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:2 DATA R/W 0x1FFFFFFF Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 1 DBG1 R/W 1 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 154 November 30, 2007 Preliminary Internal Memory Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:0 DATA R/W 0x7FFFFFFF November 30, 2007 155 Preliminary LM3S6952 Microcontroller Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:0 DATA R/W 0x7FFFFFFF 156 November 30, 2007 Preliminary Internal Memory Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF November 30, 2007 157 Preliminary LM3S6952 Microcontroller Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF 158 November 30, 2007 Preliminary Internal Memory Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF November 30, 2007 159 Preliminary LM3S6952 Microcontroller Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF 160 November 30, 2007 Preliminary Internal Memory Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF November 30, 2007 161 Preliminary LM3S6952 Microcontroller Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF 162 November 30, 2007 Preliminary Internal Memory 9 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module is FiRM-compliant and supports 6-43 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ 5-V-tolerant input/outputs ■ Bit masking in both read and write operations through address lines ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 9.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 9-1 on page 164). The LM3S6952 microcontroller contains seven ports and thus seven of these physical GPIO blocks. November 30, 2007 163 Preliminary LM3S6952 Microcontroller Figure 9-1. GPIO Port Block Diagram Alternate Input Alternate Output Alternate Output Enable Interrupt GPIO Input GPIO Output GPIO Output Enable Pad Output Pad Output Enable Package I/O Pin GPIODATA GPIODIR Data Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Interrupt Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Pad Control GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Identification Registers GPIOAFSEL Mode Control DEMUX MUX MUX Digital I/O Pad Pad Input GPIOLOCK Commit Control GPIOCR 9.1.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 9.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 171) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 9.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 170) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. 164 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 9-2 on page 165, where u is data unchanged by the write. Figure 9-2. GPIODATA Write Example 0 0 1 0 0 1 1 0 1 0 u u 1 u u 0 1 u 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 GPIODATA 0xEB 0x098 ADDR[9:2] During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 165. Figure 9-3. GPIODATA Read Example 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 7 6 5 4 3 2 1 0 Returned Value GPIODATA 0x0C4 ADDR[9:2] 9.1.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 172) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 173) ■ GPIO Interrupt Event (GPIOIEV) register (see page 174) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 175). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 176 and page 177). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. November 30, 2007 165 Preliminary LM3S6952 Microcontroller In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 178). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 9.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 9.1.4 Commit Control The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. 9.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 9.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 167 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-2 on page 167 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. 166 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Table 9-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Valuea AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR Digital Input (GPIO) 0 0 0 1 ? ? X X X X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Input 0 0 1 1 X X X X X X (GPIO) Open Drain Output 0 1 1 1 X X ? ? ? ? (GPIO) Open Drain 1 X 1 1 X X ? ? ? ? Input/Output (I2C) Digital Input (Timer 1 X 0 1 ? ? X X X X CCP) Digital Input (QEI) 1 X 0 1 ? ? X X X X Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ? Digital Output (Timer 1 X 0 1 ? ? ? ? ? ? PWM) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (SSI) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (UART) Analog Input 0 0 0 0 0 0 X X X X (Comparator) Digital Output 1 X 0 1 ? ? ? ? ? ? (Comparator) a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 9-2. GPIO Interrupt Configuration Example Desired Pin 2 Bit Valuea Interrupt Event Trigger Register 7 6 5 4 3 2 1 0 0=edge X X X X X 0 X X 1=level GPIOIS 0=single X X X X X 0 X X edge 1=both edges GPIOIBE 0=Low level, X X X X X 1 X X or negative edge 1=High level, or positive edge GPIOIEV 0=masked 0 0 0 0 0 1 0 0 1=not masked GPIOIM a. X=Ignored (don’t care bit) November 30, 2007 167 Preliminary LM3S6952 Microcontroller 9.3 Register Map Table 9-3 on page 168 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 ■ GPIO Port B: 0x4000.5000 ■ GPIO Port C: 0x4000.6000 ■ GPIO Port D: 0x4000.7000 ■ GPIO Port E: 0x4002.4000 ■ GPIO Port F: 0x4002.5000 ■ GPIO Port G: 0x4002.6000 Important: The GPIO registers in this chapter are duplicated in each GPIO block, however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 9-3. GPIO Register Map See Offset Name Type Reset Description page 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 170 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 171 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 172 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 173 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 174 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 175 168 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) See Offset Name Type Reset Description page 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 176 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 177 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 178 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 179 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 181 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 182 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 183 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 184 0x510 GPIOPUR R/W - GPIO Pull-Up Select 185 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 186 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 187 0x51C GPIODEN R/W - GPIO Digital Enable 188 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 189 0x524 GPIOCR - - GPIO Commit 190 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 192 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 193 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 194 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 195 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 196 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 197 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 198 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 199 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 200 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 201 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 202 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 203 9.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. November 30, 2007 169 Preliminary LM3S6952 Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 171). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 164 for examples of reads and writes. 7:0 DATA R/W 0x00 170 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. 7:0 DIR R/W 0x00 November 30, 2007 171 Preliminary LM3S6952 Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IS Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). 7:0 IS R/W 0x00 172 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 172) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 174). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IBE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 174). 0 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 7:0 IBE R/W 0x00 November 30, 2007 173 Preliminary LM3S6952 Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 172). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IEV Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description Falling edge or Low levels on corresponding pins trigger interrupts. 0 Rising edge or High levels on corresponding pins trigger interrupts. 1 7:0 IEV R/W 0x00 174 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IME Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. 7:0 IME R/W 0x00 November 30, 2007 175 Preliminary LM3S6952 Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 175). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. 7:0 RIS RO 0x00 176 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. 7:0 MIS RO 0x00 November 30, 2007 177 Preliminary LM3S6952 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IC Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. 7:0 IC W1C 0x00 178 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x420 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AFSEL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 November 30, 2007 179 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). Hardware control of corresponding GPIO line (alternate hardware function). 1 Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 AFSEL R/W - 180 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV2 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV2 R/W 0xFF November 30, 2007 181 Preliminary LM3S6952 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV4 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV4 R/W 0x00 182 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV8 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV8 R/W 0x00 November 30, 2007 183 Preliminary LM3S6952 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 188). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 166). GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ODE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. 7:0 ODE R/W 0x00 184 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 186). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x510 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PUE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 PUE R/W - November 30, 2007 185 Preliminary LM3S6952 Microcontroller Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 185). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PDE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 7:0 PDE R/W 0x00 186 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 183). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SRL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. 7:0 SRL R/W 0x00 November 30, 2007 187 Preliminary LM3S6952 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x51C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 DEN R/W - 188 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 190). Writing 0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description GPIO Lock A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked 31:0 LOCK R/W 0x0000.0001 November 30, 2007 189 Preliminary LM3S6952 Microcontroller Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and GPIOAFSEL registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x524 Type -, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CR Type RO RO RO RO RO RO RO RO - - - - - - - - Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 190 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. 7:0 CR - - November 30, 2007 191 Preliminary LM3S6952 Microcontroller Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] 192 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] November 30, 2007 193 Preliminary LM3S6952 Microcontroller Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] 194 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] November 30, 2007 195 Preliminary LM3S6952 Microcontroller Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x61 196 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 197 Preliminary LM3S6952 Microcontroller Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 198 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 199 Preliminary LM3S6952 Microcontroller Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 200 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 201 Preliminary LM3S6952 Microcontroller Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 202 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 203 Preliminary LM3S6952 Microcontroller 10 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1, and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. Note: Timer2 is an internal timer and can only be used to generate internal interrupts or trigger ADC events. The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers. Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 40) and the PWM timer in the PWM module (see “PWM Timer” on page 466). The following modes are supported: ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock using 32.768-KHz input clock – Software-controlled event stalling (excluding RTC mode) ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – Software-controlled event stalling ■ 16-bit Input Capture modes – Input edge count capture – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 10.1 Block Diagram Note: In Figure 10-1 on page 205, the specific CCP pins available depend on the Stellaris® device. See Table 10-1 on page 205 for the available CCPs. 204 November 30, 2007 Preliminary General-Purpose Timers Figure 10-1. GPTM Module Block Diagram TA Comparator TB Comparator GPTMTBR GPTMAR Clock / Edge Detect RTC Divider Clock / Edge Detect TimerA Interrupt TimerB Interrupt System Clock 0x0000 (Down Counter Modes) 0x0000 (Down Counter Modes) 32 KHz or Even CCP Pin Odd CCP Pin En En TimerA Control GPTMTAPMR GPTMTAILR GPTMTAMATCHR GPTMTAPR GPTMTAMR TimerB Control GPTMTBPMR GPTMTBILR GPTMTBMATCHR GPTMTBPR GPTMTBMR Interrupt / Config GPTMCFG GPTMRIS GPTMICR GPTMMIS GPTMIMR GPTMCTL Table 10-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 Timer 1 TimerA CCP2 - TimerB - CCP3 Timer 2 TimerA - - TimerB - - 10.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 216), the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and the GPTM TimerB Mode (GPTMTBMR) register (see page 219). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 10.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load November 30, 2007 205 Preliminary LM3S6952 Microcontroller (GPTMTAILR) register (see page 230) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 231). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 234) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 235). 10.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 230 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 231 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 238 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 239 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 10.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 221), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and output triggers when it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 226), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 228). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 224), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 227). The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. 206 November 30, 2007 Preliminary General-Purpose Timers If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 10.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 232) by the controller. The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 10.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 216). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 10.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. November 30, 2007 207 Preliminary LM3S6952 Microcontroller If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 10-2. 16-Bit Timer With Prescaler Configurations Prescale #Clock (T c)a Max Time Units 00000000 1 1.3107 mS 00000001 2 2.6214 mS 00000010 3 3.9321 mS ------------ -- -- -- 11111100 254 332.9229 mS 11111110 255 334.2336 mS 11111111 256 335.5443 mS a. Tc is the clock period. 10.2.3.2 16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 10-2 on page 209 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. 208 November 30, 2007 Preliminary General-Purpose Timers Figure 10-2. 16-Bit Input Edge Count Mode Example 0x000A 0x0006 0x0007 0x0008 0x0009 Input Signal Timer stops, flags asserted Timer reload Count on next cycle Ignored Ignored 10.2.3.3 16-Bit Input Edge Time Mode Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 10-3 on page 210 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). November 30, 2007 209 Preliminary LM3S6952 Microcontroller Figure 10-3. 16-Bit Input Edge Time Mode Example GPTMTnR=Y Input Signal Time Count GPTMTnR=X GPTMTnR=Z Z X Y 0xFFFF 10.2.3.4 16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 10-4 on page 211 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. 210 November 30, 2007 Preliminary General-Purpose Timers Figure 10-4. 16-Bit PWM Mode Example Output Signal Time Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A TnPWML = 0 TnPWML = 1 TnEN set 10.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, and TIMER2 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 10.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. November 30, 2007 211 Preliminary LM3S6952 Microcontroller 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 212. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4 pins. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 10.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 212 November 30, 2007 Preliminary General-Purpose Timers In One-Shot mode, the timer stops counting after step 8 on page 212. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 213 through step 9 on page 213. 10.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM November 30, 2007 213 Preliminary LM3S6952 Microcontroller Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 10.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register and the GPTM Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 10.4 Register Map Table 10-3 on page 214 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 Table 10-3. Timers Register Map See Offset Name Type Reset Description page 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 216 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 217 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 219 214 November 30, 2007 Preliminary General-Purpose Timers See Offset Name Type Reset Description page 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 221 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 224 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 226 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 227 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 228 GPTM TimerA Interval Load 230 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x028 GPTMTAILR R/W 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 231 GPTM TimerA Match 232 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x030 GPTMTAMATCHR R/W 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 233 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 234 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 235 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 236 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 237 GPTM TimerA 238 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x048 GPTMTAR RO 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 239 10.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. November 30, 2007 215 Preliminary LM3S6952 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPTMCFG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved. 0x3 Reserved. 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x4-0x7 2:0 GPTMCFG R/W 0x0 216 November 30, 2007 Preliminary General-Purpose Timers Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAAMS TACMR TAMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. 3 TAAMS R/W 0 GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode. 1 Edge-Time mode. 2 TACMR R/W 0 November 30, 2007 217 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 1:0 TAMR R/W 0x0 218 November 30, 2007 Preliminary General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBAMS TBCMR TBMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. 3 TBAMS R/W 0 GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode. 1 Edge-Time mode. 2 TBCMR R/W 0 November 30, 2007 219 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register’s contents are ignored and GPTMTAMR is used. 1:0 TBMR R/W 0x0 220 November 30, 2007 Preliminary General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:15 reserved RO 0x00 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 14 TBPWML R/W 0 GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output TimerB trigger is disabled. 1 The output TimerB trigger is enabled. 13 TBOTE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 November 30, 2007 221 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 11:10 TBEVENT R/W 0x0 GPTM TimerB Stall Enable The TBSTALL values are defined as follows: Value Description 0 TimerB stalling is disabled. 1 TimerB stalling is enabled. 9 TBSTALL R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 8 TBEN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 6 TAPWML R/W 0 GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output TimerA trigger is disabled. 1 The output TimerA trigger is enabled. 5 TAOTE R/W 0 222 November 30, 2007 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 0 RTC counting is disabled. 1 RTC counting is enabled. 4 RTCEN R/W 0 GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 3:2 TAEVENT R/W 0x0 GPTM TimerA Stall Enable The TASTALL values are defined as follows: Value Description 0 TimerA stalling is disabled. 1 TimerA stalling is enabled. 1 TASTALL R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 0 TAEN R/W 0 November 30, 2007 223 Preliminary LM3S6952 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 10 CBEIM R/W 0 GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 9 CBMIM R/W 0 GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 8 TBTOIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0 224 November 30, 2007 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 3 RTCIM R/W 0 GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 2 CAEIM R/W 0 GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 1 CAMIM R/W 0 GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 0 TATOIM R/W 0 November 30, 2007 225 Preliminary LM3S6952 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 10 CBERIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 9 CBMRIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 8 TBTORIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 3 RTCRIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 1 CAMRIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 0 TATORIS RO 0 226 November 30, 2007 Preliminary General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 10 CBEMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 9 CBMMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 8 TBTOMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 3 RTCMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 1 CAMMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. 0 TATOMIS RO 0 November 30, 2007 227 Preliminary LM3S6952 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 10 CBECINT W1C 0 GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 9 CBMCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 8 TBTOCINT W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 228 November 30, 2007 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 3 RTCCINT W1C 0 GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 2 CAECINT W1C 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 1 CAMCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 0 TATOCINT W1C 0 November 30, 2007 229 Preliminary LM3S6952 Microcontroller Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x028 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAILRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TAILRH R/W GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 15:0 TAILRL R/W 0xFFFF 230 November 30, 2007 Preliminary General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 15:0 TBILRL R/W 0xFFFF November 30, 2007 231 Preliminary LM3S6952 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x030 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAMRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TAMRH R/W GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 15:0 TAMRL R/W 0xFFFF 232 November 30, 2007 Preliminary General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 15:0 TBMRL R/W 0xFFFF November 30, 2007 233 Preliminary LM3S6952 Microcontroller Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 10-2 on page 208 for more details and an example. 7:0 TAPSR R/W 0x00 234 November 30, 2007 Preliminary General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 10-2 on page 208 for more details and an example. 7:0 TBPSR R/W 0x00 November 30, 2007 235 Preliminary LM3S6952 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 7:0 TAPSMR R/W 0x00 236 November 30, 2007 Preliminary General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 7:0 TBPSMR R/W 0x00 November 30, 2007 237 Preliminary LM3S6952 Microcontroller Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x048 Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TARH Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TARL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TARH RO GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TARL RO 0xFFFF 238 November 30, 2007 Preliminary General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBRL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TBRL RO 0xFFFF November 30, 2007 239 Preliminary LM3S6952 Microcontroller 11 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a locking register, and user-enabled stalling. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 11.1 Block Diagram Figure 11-1. WDT Module Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR WDTRIS WDTMIS WDTLOCK WDTTEST WDTLOAD WDTVALUE Comparator 32-Bit Down Counter 0x00000000 Interrupt System Clock Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 11.2 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the 240 November 30, 2007 Preliminary Watchdog Timer Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 11.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 11.4 Register Map Table 11-1 on page 241 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 11-1. Watchdog Timer Register Map See Offset Name Type Reset Description page 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 243 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 244 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 245 0x00C WDTICR WO - Watchdog Interrupt Clear 246 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 247 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 248 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 249 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 250 November 30, 2007 241 Preliminary LM3S6952 Microcontroller See Offset Name Type Reset Description page 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 251 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 252 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 253 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 254 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 255 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 256 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 257 0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 258 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 259 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 260 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 261 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 262 11.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 242 November 30, 2007 Preliminary Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description 31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value November 30, 2007 243 Preliminary LM3S6952 Microcontroller Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Watchdog Value Current value of the 32-bit down counter. 31:0 WDTValue RO 0xFFFF.FFFF 244 November 30, 2007 Preliminary Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RESEN INTEN Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 Disabled. 1 Enable the Watchdog module reset output. 1 RESEN R/W 0 Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 1 Interrupt event enabled. Once enabled, all writes are ignored. 0 INTEN R/W 0 November 30, 2007 245 Preliminary LM3S6952 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 WDTIntClr WO - Watchdog Interrupt Clear 246 November 30, 2007 Preliminary Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTRIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 0 WDTRIS RO 0 November 30, 2007 247 Preliminary LM3S6952 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 0 WDTMIS RO 0 248 November 30, 2007 Preliminary Watchdog Timer Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved STALL reserved Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:9 reserved RO 0x00 Watchdog Stall Enable When set to 1, if the Stellaris® microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 8 STALL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 0x00 November 30, 2007 249 Preliminary LM3S6952 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 31:0 WDTLock R/W 0x0000 250 November 30, 2007 Preliminary Watchdog Timer Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] November 30, 2007 251 Preliminary LM3S6952 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] 252 November 30, 2007 Preliminary Watchdog Timer Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] November 30, 2007 253 Preliminary LM3S6952 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] 254 November 30, 2007 Preliminary Watchdog Timer Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] November 30, 2007 255 Preliminary LM3S6952 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] 256 November 30, 2007 Preliminary Watchdog Timer Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] November 30, 2007 257 Preliminary LM3S6952 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] 258 November 30, 2007 Preliminary Watchdog Timer Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] November 30, 2007 259 Preliminary LM3S6952 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] 260 November 30, 2007 Preliminary Watchdog Timer Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] November 30, 2007 261 Preliminary LM3S6952 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] 262 November 30, 2007 Preliminary Watchdog Timer 12 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris® ADC module features 10-bit conversion resolution and supports three input channels, plus an internal temperature sensor. The ADC module contains a programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. The Stellaris® ADC provides the following features: ■ Three analog input channels ■ Single-ended and differential-input configurations ■ Internal temperature sensor ■ Sample rate of 500 thousand samples/second ■ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy November 30, 2007 263 Preliminary LM3S6952 Microcontroller 12.1 Block Diagram Figure 12-1. ADC Module Block Diagram Analog-to-Digital Converter ADCSSFIFO0 ADCSSFIFO1 ADCSSFIFO2 ADCSSFIFO3 FIFO Block ADCSSFSTAT0 ADCSSCTL0 ADCSSMUX0 Sample Sequencer 0 ADCSSFSTAT1 ADCSSCTL1 ADCSSMUX1 Sample Sequencer 1 ADCSSFSTAT2 ADCSSCTL2 ADCSSMUX2 Sample Sequencer 2 ADCSSFSTAT3 ADCSSCTL3 ADCSSMUX3 Sample Sequencer 3 ADCUSTAT ADCOSTAT ADCACTSS Control/Status ADCSSPRI ADCISC ADCRIS ADCIM Interrupt Control SS0 Interrupt Analog Inputs SS1 Interrupt SS2 Interrupt SS3 Interrupt ADCEMUX ADCPSSI Trigger Events SS0 SS1 SS2 SS3 Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Hardware Averager ADCSAC 12.2 Functional Description The Stellaris® ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approach found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the controller. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. 12.2.1 Sample Sequencers The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 12-1 on page 264 shows the maximum number of samples that each Sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 12-1. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 1 1 SS2 4 4 SS1 4 4 SS0 8 8 264 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample Sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured before being enabled. When configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 12.2.2 Module Control Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such as interrupt generation, sequence prioritization, and trigger configuration. Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock divider configuration targets 16.667 MHz operation for all Stellaris® devices. 12.2.2.1 Interrupts The Sample Sequencers dictate the events that cause interrupts, but they don't have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. 12.2.2.2 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample Sequencer units with the same priority do not provide consistent results, so software must ensure that all active Sample Sequencer units have a unique priority value. 12.2.2.3 Sampling Events Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select (ADCEMUX) register. The external peripheral triggering sources vary by Stellaris® family member, November 30, 2007 265 Preliminary LM3S6952 Microcontroller but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible to starve other lower priority sequences. 12.2.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 281). There is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or differential. 12.2.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. 12.2.5 Test Modes There is a user-available test mode that allows for loopback operation within the digital portion of the ADC module. This can be useful for debugging software without having to provide actual analog stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see page 294). 12.2.6 Internal Temperature Sensor The internal temperature sensor provides an analog temperature reading as well as a reference voltage. The voltage at the output terminal SENSO is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 12-2 on page 267. 266 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Figure 12-2. Internal Temperature Sensor Characteristic 12.3 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 12.3.1 Module Initialization Initialization of the ADC module is a simple process with very few steps. The main steps include enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 100). 2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority. 12.3.2 Sample Sequencer Configuration Configuration of the Sample Sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. The configuration for each Sample Sequencer should be as follows: 1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in the ADCACTSS register. Programming of the Sample Sequencers is allowed without having them enabled. Disabling the Sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. November 30, 2007 267 Preliminary LM3S6952 Microcontroller 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the ADCACTSS register. 12.4 Register Map Table 12-2 on page 268 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s address, relative to the ADC base address of 0x4003.8000. Table 12-2. ADC Register Map See Offset Name Type Reset Description page 0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 270 0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 271 0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 272 0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 273 0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 274 0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 275 0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 278 0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 279 0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 280 0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 281 0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 282 0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 284 0x048 ADCSSFIFO0 RO 0x0000.0000 ADC Sample Sequence Result FIFO 0 287 0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 288 0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 289 0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 290 0x068 ADCSSFIFO1 RO 0x0000.0000 ADC Sample Sequence Result FIFO 1 287 0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 288 0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 289 0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 290 0x088 ADCSSFIFO2 RO 0x0000.0000 ADC Sample Sequence Result FIFO 2 287 0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 288 0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 292 268 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) See Offset Name Type Reset Description page 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 293 0x0A8 ADCSSFIFO3 RO 0x0000.0000 ADC Sample Sequence Result FIFO 3 287 0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 288 0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 294 12.5 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. November 30, 2007 269 Preliminary LM3S6952 Microcontroller Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be enabled/disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ASEN3 ASEN2 ASEN1 ASEN0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 ADC SS3 Enable Specifies whether Sample Sequencer 3 is enabled. If set, the sample sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is inactive. 3 ASEN3 R/W 0 ADC SS2 Enable Specifies whether Sample Sequencer 2 is enabled. If set, the sample sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is inactive. 2 ASEN2 R/W 0 ADC SS1 Enable Specifies whether Sample Sequencer 1 is enabled. If set, the sample sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is inactive. 1 ASEN1 R/W 0 ADC SS0 Enable Specifies whether Sample Sequencer 0 is enabled. If set, the sample sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is inactive. 0 ASEN0 R/W 0 270 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INR3 INR2 INR1 INR0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL3 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN3 bit. 3 INR3 RO 0 SS2 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL2 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN2 bit. 2 INR2 RO 0 SS1 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL1 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN1 bit. 1 INR1 RO 0 SS0 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL0 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN0 bit. 0 INR0 RO 0 November 30, 2007 271 Preliminary LM3S6952 Microcontroller Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MASK3 MASK2 MASK1 MASK0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 3 MASK3 R/W 0 SS2 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 2 MASK2 R/W 0 SS1 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 1 MASK1 R/W 0 SS0 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 0 MASK0 R/W 0 272 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing interrupt conditions, and shows the status of controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still cleared via the ADCISC register, even if the IN bit is not set. ADC Interrupt Status and Clear (ADCISC) Base 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IN3 IN2 IN1 IN0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 Interrupt Status and Clear This bit is set by hardware when the MASK3 and INR3 bits are both 1, providing a level-based interrupt to the controller. It is cleared by writing a 1, and also clears the INR3 bit. 3 IN3 R/W1C 0 SS2 Interrupt Status and Clear This bit is set by hardware when the MASK2 and INR2 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR2 bit. 2 IN2 R/W1C 0 SS1 Interrupt Status and Clear This bit is set by hardware when the MASK1 and INR1 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR1 bit. 1 IN1 R/W1C 0 SS0 Interrupt Status and Clear This bit is set by hardware when the MASK0 and INR0 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR0 bit. 0 IN0 R/W1C 0 November 30, 2007 273 Preliminary LM3S6952 Microcontroller Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OV3 OV2 OV1 OV0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 3 OV3 R/W1C 0 SS2 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 2 OV2 R/W1C 0 SS1 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS0 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 0 OV0 R/W1C 0 274 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each Sample Sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM3 EM2 EM1 EM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 PWM0 0x7 PWM1 0x8 PWM2 0x9-0xE reserved 0xF Always (continuously sample) 15:12 EM3 R/W 0x00 November 30, 2007 275 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 PWM0 0x7 PWM1 0x8 PWM2 0x9-0xE reserved 0xF Always (continuously sample) 11:8 EM2 R/W 0x00 SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 PWM0 0x7 PWM1 0x8 PWM2 0x9-0xE reserved 0xF Always (continuously sample) 7:4 EM1 R/W 0x00 276 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 PWM0 0x7 PWM1 0x8 PWM2 0x9-0xE reserved 0xF Always (continuously sample) 3:0 EM0 R/W 0x00 November 30, 2007 277 Preliminary LM3S6952 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding underflow condition can be cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved UV3 UV2 UV1 UV0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 3 UV3 R/W1C 0 SS2 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 2 UV2 R/W1C 0 SS1 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS0 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 278 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority or the ADC behavior is inconsistent. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS3 reserved SS2 reserved SS1 reserved SS0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x00 SS3 Priority The SS3 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the Sequencers must be uniquely mapped. ADC behavior is not consistent if two or more fields are equal. 13:12 SS3 R/W 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0x0 SS2 Priority The SS2 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. 9:8 SS2 R/W 0x2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0x0 SS1 Priority The SS1 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. 5:4 SS1 R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 SS0 Priority The SS0 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. 1:0 SS0 R/W 0x0 November 30, 2007 279 Preliminary LM3S6952 Microcontroller Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the Sample Sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.8000 Offset 0x028 Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS3 SS2 SS1 SS0 Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved WO - SS3 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS register. 3 SS3 WO - SS2 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS register. 2 SS2 WO - SS1 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS register. 1 SS1 WO - SS0 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS register. 0 SS0 WO - 280 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG = 7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) Base 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AVG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 No hardware oversampling 0x1 2x hardware oversampling 0x2 4x hardware oversampling 0x3 8x hardware oversampling 0x4 16x hardware oversampling 0x5 32x hardware oversampling 0x6 64x hardware oversampling 0x7 Reserved 2:0 AVG R/W 0x0 November 30, 2007 281 Preliminary LM3S6952 Microcontroller Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:30 reserved RO 0 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the Sample Sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 1 indicates the input is ADC1. 29:28 MUX7 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:26 reserved RO 0 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 25:24 MUX6 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:22 reserved RO 0 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 21:20 MUX5 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:18 reserved RO 0 282 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 17:16 MUX4 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:14 reserved RO 0 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 13:12 MUX3 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 9:8 MUX2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 5:4 MUX1 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 1:0 MUX0 R/W 0 November 30, 2007 283 Preliminary LM3S6952 Microcontroller Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) Base 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description 8th Sample Temp Sensor Select The TS7 bit is used during the eighth sample of the sample sequence and specifies the input source of the sample. If set, the temperature sensor is read. Otherwise, the input pin specified by the ADCSSMUX register is read. 31 TS7 R/W 0 8th Sample Interrupt Enable The IE7 bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal (INR0 bit) is asserted at the end of the sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to a controller-level interrupt. When this bit is set, the raw interrupt is asserted, otherwise it is not. It is legal to have multiple samples within a sequence generate interrupts. 30 IE7 R/W 0 8th Sample is End of Sequence The END7 bit indicates that this is the last sample of the sequence. It is possible to end the sequence on any sample position. Samples defined after the sample containing a set END are not requested for conversion even though the fields may be non-zero. It is required that software write the END bit somewhere within the sequence. (Sample Sequencer 3, which only has a single sample in the sequence, is hardwired to have the END0 bit set.) Setting this bit indicates that this sample is the last in the sequence. 29 END7 R/W 0 8th Sample Diff Input Select The D7 bit indicates that the analog input is to be differentially sampled. The corresponding ADCSSMUXx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". The temperature sensor does not have a differential option. When set, the analog inputs are differentially sampled. 28 D7 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 27 TS6 R/W 0 284 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 26 IE6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 25 END6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 24 D6 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 23 TS5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 21 END5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 20 D5 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 19 TS4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 17 END4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 16 D4 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 13 END3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 12 D3 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 11 TS2 R/W 0 November 30, 2007 285 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 9 END2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 8 D2 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 7 TS1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 5 END1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 4 D1 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 286 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 This register contains the conversion results for samples collected with the Sample Sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0) Base 0x4003.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0x00 9:0 DATA RO 0x00 Conversion Result Data November 30, 2007 287 Preliminary LM3S6952 Microcontroller Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the Sample Sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1, ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) Base 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FULL reserved EMPTY HPTR TPTR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:13 reserved RO 0x00 FIFO Full When set, indicates that the FIFO is currently full. 12 FULL RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0x00 FIFO Empty When set, indicates that the FIFO is currently empty. 8 EMPTY RO 1 FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. 7:4 HPTR RO 0x00 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. 3:0 TPTR RO 0x00 288 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 282 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) Base 0x4003.8000 Offset 0x060 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x00 13:12 MUX3 R/W 0 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 9:8 MUX2 R/W 0 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 5:4 MUX1 R/W 0 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 1:0 MUX0 R/W 0 1st Sample Input Select November 30, 2007 289 Preliminary LM3S6952 Microcontroller Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on page 284 for detailed bit descriptions. ADC Sample Sequence Control 1 (ADCSSCTL1) Base 0x4003.8000 Offset 0x064 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 13 END3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 12 D3 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 11 TS2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 9 END2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 8 D2 R/W 0 290 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 7 TS1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 5 END1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 4 D1 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 November 30, 2007 291 Preliminary LM3S6952 Microcontroller Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 282 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 1:0 MUX0 R/W 0 1st Sample Input Select 292 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 284 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) Base 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TS0 IE0 END0 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 1 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 November 30, 2007 293 Preliminary LM3S6952 Microcontroller Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned. Read-Only Register ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CNT CONT DIFF TS MUX Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0x00 Continuous Sample Counter Continuous sample counter that is initialized to 0 and counts each sample as it processed. This helps provide a unique value for the data received. 9:6 CNT RO 0x0 Continuation Sample Indicator When set, indicates that this is a continuation sample. For example, if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 5 CONT RO 0 Differential Sample Indicator When set, indicates that this is a differential sample. 4 DIFF RO 0 Temp Sensor Sample Indicator When set, indicates that this is a temperature sensor sample. 3 TS RO 0 Analog Input Indicator Indicates which analog input is to be sampled. 2:0 MUX RO 0x0 294 November 30, 2007 Preliminary Analog-to-Digital Converter (ADC) Write-Only Register ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LB Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Loopback Mode Enable When set, forces a loopback within the digital block to provide information on input and unique numbering. The 10-bit loopback data is defined as shown in the read for bits 9:0 above. 0 LB WO 0 November 30, 2007 295 Preliminary LM3S6952 Microcontroller 13 Universal Asynchronous Receivers/Transmitters (UARTs) The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S6952 controller is equipped with three UART modules. Each UART has the following features: ■ Separate transmit and receive FIFOs ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Programmable baud-rate generator allowing rates up to 3.125 Mbps ■ Standard asynchronous communication bits for start, stop, and parity ■ False start bit detection ■ Line-break generation and detection ■ Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing: – Programmable use of IrDA Serial InfraRed (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration 296 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) 13.1 Block Diagram Figure 13-1. UART Module Block Diagram Receiver Transmitter System Clock Control / Status UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Baud Rate Generator UARTIBRD UARTFBRD Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTDR TXFIFO 16x8 ... RXFIFO 16x8 ... Interrupt UnTx UnRx 13.2 Functional Description Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 315). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 13.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data November 30, 2007 297 Preliminary LM3S6952 Microcontroller bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 13-2 on page 298 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 13-2. UART Character Frame 1 0 5-8 data bits LSB MSB Parity bit if enabled 1-2 stop bits UnTX n Start 13.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 311) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 312). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.): BRD = BRDI + BRDF = SysClk / (16 * Baud Rate) The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 313), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 298 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) 13.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 308) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 297). The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 306). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 13.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output, and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. Figure 13-3 on page 300 shows the UART transmit and receive signals, with and without IrDA modulation. November 30, 2007 299 Preliminary LM3S6952 Microcontroller Figure 13-3. IrDA Data Modulation 0 1 0 1 0 0 1 1 0 1 Data bits 0 1 0 1 0 0 1 1 0 1 Start Data bits bit Start Stop Bit period Bit period 3 16 UnTx UnTx with IrDA UnRx with IrDA UnRx Stop bit In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. 13.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 304). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 313). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 308) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 317). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 13.2.6 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error 300 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 322). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 319) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 321). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 323). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 13.2.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 315). In loopback mode, data transmitted on UnTx is received on the UnRx input. 13.2.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 13.3 Initialization and Configuration To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1 register. This section discusses the steps that are required for using a UART module. For this example, the system clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit November 30, 2007 301 Preliminary LM3S6952 Microcontroller ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 298, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 311) should be set to 10. The value to be loaded into the UARTFBRD register (see page 312) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. 13.4 Register Map Table 13-1 on page 302 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 ■ UART2: 0x4000.E000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 315) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 13-1. UART Register Map See Offset Name Type Reset Description page 0x000 UARTDR R/W 0x0000.0000 UART Data 304 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 306 0x018 UARTFR RO 0x0000.0090 UART Flag 308 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 310 302 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) See Offset Name Type Reset Description page 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 311 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 312 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 313 0x030 UARTCTL R/W 0x0000.0300 UART Control 315 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 317 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 319 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 321 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 322 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 323 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 325 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 326 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 327 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 328 0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 329 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 330 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 331 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 332 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 333 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 334 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 335 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 336 13.5 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. November 30, 2007 303 Preliminary LM3S6952 Microcontroller Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OE BE PE FE DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0 UART Overrun Error The OE values are defined as follows: Value Description 0 There has been no data loss due to a FIFO overrun. New data was received when the FIFO was full, resulting in data loss. 1 11 OE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 10 BE RO 0 304 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 9 PE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 8 FE RO 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. 7:0 DATA R/W 0 November 30, 2007 305 Preliminary LM3S6952 Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Read-Only Receive Status (UARTRSR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OE BE PE FE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0 UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 3 OE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 2 BE RO 0 306 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 1 PE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. 0 FE RO 0 Write-Only Error Clear (UARTECR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved WO 0 Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. 7:0 DATA WO 0 November 30, 2007 307 Preliminary LM3S6952 Microcontroller Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXFE RXFF TXFF RXFE BUSY reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 7 TXFE RO 1 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 6 RXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 5 TXFF RO 0 308 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 4 RXFE RO 1 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 3 BUSY RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 309 Preliminary LM3S6952 Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ILPDVSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 7:0 ILPDVSR R/W 0x00 310 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIVINT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0 15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor November 30, 2007 311 Preliminary LM3S6952 Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIVFRAC Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor 312 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SPS WLEN FEN STP2 EPS PEN BRK Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 7 SPS R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 6:5 WLEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 4 FEN R/W 0 November 30, 2007 313 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. 3 STP2 R/W 0 UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 2 EPS R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 1 PEN R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 0 BRK R/W 0 314 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RXE TXE LBE reserved SIRLP SIREN UARTEN Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0 UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. 9 RXE R/W 1 UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. 8 TXE R/W 1 UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 7 LBE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:3 reserved RO 0 November 30, 2007 315 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 310 for more information. 2 SIRLP R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 1 SIREN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 UARTEN R/W 0 316 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RXIFLSEL TXIFLSEL Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO ≥ 1/8 full 0x1 RX FIFO ≥ ¼ full 0x2 RX FIFO ≥ ½ full (default) 0x3 RX FIFO ≥ ¾ full 0x4 RX FIFO ≥ 7/8 full 0x5-0x7 Reserved 5:3 RXIFLSEL R/W 0x2 November 30, 2007 317 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ 1/8 full 0x1 TX FIFO ≤ ¼ full 0x2 TX FIFO ≤ ½ full (default) 0x3 TX FIFO ≤ ¾ full 0x4 TX FIFO ≤ 7/8 full 0x5-0x7 Reserved 2:0 TXIFLSEL R/W 0x2 318 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 10 OEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 9 BEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. 5 TXIM R/W 0 November 30, 2007 319 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 4 RXIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x00 320 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 10 OERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 9 BERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0xF November 30, 2007 321 Preliminary LM3S6952 Microcontroller Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 10 OEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 9 BEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0 322 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 10 OEIC W1C 0 Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 9 BEIC W1C 0 Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 8 PEIC W1C 0 November 30, 2007 323 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 7 FEIC W1C 0 Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 6 RTIC W1C 0 Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 5 TXIC W1C 0 Receive Interrupt Clear The RXIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 4 RXIC W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x00 324 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x0000 November 30, 2007 325 Preliminary LM3S6952 Microcontroller Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x0000 326 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x0000 November 30, 2007 327 Preliminary LM3S6952 Microcontroller Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x0000 328 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x11 November 30, 2007 329 Preliminary LM3S6952 Microcontroller Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 330 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 November 30, 2007 331 Preliminary LM3S6952 Microcontroller Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 332 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D November 30, 2007 333 Preliminary LM3S6952 Microcontroller Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 334 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 November 30, 2007 335 Preliminary LM3S6952 Microcontroller Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 336 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) 14 Synchronous Serial Interface (SSI) The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris® SSI module has the following features: ■ Master or slave operation ■ Programmable clock bit rate and prescale ■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing 14.1 Block Diagram Figure 14-1. SSI Module Block Diagram Transmit/ Receive Logic Clock Prescaler SSICPSR Control / Status SSICR0 SSICR1 SSISR Interrupt Control SSIIM SSIMIS SSIRIS SSIICR SSIDR TxFIFO 8 x 16 ... RxFIFO 8 x 16 ... System Clock SSITx SSIRx SSIClk SSIFss Interrupt Identification Registers SSIPCellID0 SSIPeriphID0 SSIPeriphID4 SSIPCellID1 SSIPeriphID1 SSIPeriphID5 SSIPCellID2 SSIPeriphID2 SSIPeriphID6 SSIPCellID3 SSIPeriphID3 SSIPeriphID7 14.2 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with November 30, 2007 337 Preliminary LM3S6952 Microcontroller internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 14.2.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 356). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 349). The frequency of the output clock SSIClk is defined by: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be able to operate at that speed. For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 543 to view SSI timing parameters. 14.2.2 FIFO Operation 14.2.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 353), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. 14.2.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 14.2.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service ■ Receive FIFO service ■ Receive FIFO time-out ■ Receive FIFO overrun All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each 338 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 357). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 359 and page 360, respectively). 14.2.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 14.2.4.1 Texas Instruments Synchronous Serial Frame Format Figure 14-2 on page 339 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk 4 to 16 bits SSIFss SSITx/SSIRx MSB LSB November 30, 2007 339 Preliminary LM3S6952 Microcontroller In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 14-3 on page 340 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) MSB LSB 4 to 16 bits SSIClk SSIFss SSITx/SSIRx 14.2.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 14.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 14-4 on page 341 and Figure 14-5 on page 341. 340 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 4 to 16 bits SSIClk SSIFss SSIRx Q SSITx MSB MSB LSB LSB Note: Q is undefined. Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB SSITx MSB LSB 4 to 16 bits LSB MSB MSB MSB LSB In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. November 30, 2007 341 Preliminary LM3S6952 Microcontroller 14.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 14-6 on page 342, which covers both single and continuous transfers. Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 4 to 16 bits SSIClk SSIFss SSIRx SSITx Q MSB Q MSB LSB LSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 14.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 14-7 on page 343 and Figure 14-8 on page 343. 342 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 4 to 16 bits SSIClk SSIFss SSIRx SSITx MSB Q MSB LSB LSB Note: Q is undefined. Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits LSB MSB In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. November 30, 2007 343 Preliminary LM3S6952 Microcontroller 14.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 14-9 on page 344, which covers both single and continuous transfers. Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 4 to 16 bits SSIClk SSIFss SSIRx SSITx Q Q MSB MSB LSB LSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 14.2.4.7 MICROWIRE Frame Format Figure 14-10 on page 345 shows the MICROWIRE frame format, again for a single frame. Figure 14-11 on page 346 shows the same format when back-to-back frames are transmitted. 344 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Figure 14-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSIRx MSB LSB 4 to 16 bits output data 0 SSITx MSB LSB 8-bit control MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. November 30, 2007 345 Preliminary LM3S6952 Microcontroller Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) 8-bit control SSIClk SSIFss SSIRx MSB LSB 4 to 16 bits output data 0 SSITx LSB MSB LSB MSB In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 14-12 on page 346 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave tSetup=(2*tSSIClk) tHold=tSSIClk 14.3 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 346 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 14.4 Register Map Table 14-1 on page 347 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 14-1. SSI Register Map See Offset Name Type Reset Description page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 349 November 30, 2007 347 Preliminary LM3S6952 Microcontroller See Offset Name Type Reset Description page 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 351 0x008 SSIDR R/W 0x0000.0000 SSI Data 353 0x00C SSISR RO 0x0000.0003 SSI Status 354 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 356 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 357 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 359 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 360 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 361 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 362 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 363 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 364 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 365 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 366 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 367 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 368 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 369 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 370 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 371 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 372 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 373 14.5 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. 348 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCR SPH SPO FRF DSS Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 15:8 SCR R/W 0x0000 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 7 SPH R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. 6 SPO R/W 0 November 30, 2007 349 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Intruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 5:4 FRF R/W 0x0 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data 3:0 DSS R/W 0x00 350 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SOD MS SSE LBM Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 0 SSI can drive SSITx output in Slave Output mode. 1 SSI must not drive the SSITx output in Slave mode. 3 SOD R/W 0 SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 Device configured as a master. 1 Device configured as a slave. 2 MS R/W 0 November 30, 2007 351 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 SSI operation disabled. 1 SSI operation enabled. Note: This bit must be set to 0 before any control registers are reprogrammed. 1 SSE R/W 0 SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 Normal serial port operation enabled. Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 1 0 LBM R/W 0 352 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 3: SSI Data (SSIDR), offset 0x008 SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. 15:0 DATA R/W 0x0000 November 30, 2007 353 Preliminary LM3S6952 Microcontroller Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BSY RFF RNE TNF TFE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x00 SSI Busy Bit The BSY values are defined as follows: Value Description 0 SSI is idle. SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. 1 4 BSY RO 0 SSI Receive FIFO Full The RFF values are defined as follows: Value Description 0 Receive FIFO is not full. 1 Receive FIFO is full. 3 RFF RO 0 SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 0 Receive FIFO is empty. 1 Receive FIFO is not empty. 2 RNE RO 0 SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 Transmit FIFO is full. 1 Transmit FIFO is not full. 1 TNF RO 1 354 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Bit/Field Name Type Reset Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. 0 TFE R0 1 November 30, 2007 355 Preliminary LM3S6952 Microcontroller Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CPSDVSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 7:0 CPSDVSR R/W 0x00 356 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXIM RXIM RTIM RORIM Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 0 TX FIFO half-full or less condition interrupt is masked. 1 TX FIFO half-full or less condition interrupt is not masked. 3 TXIM R/W 0 SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 0 RX FIFO half-full or more condition interrupt is masked. 1 RX FIFO half-full or more condition interrupt is not masked. 2 RXIM R/W 0 SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 RX FIFO time-out interrupt is masked. 1 RX FIFO time-out interrupt is not masked. 1 RTIM R/W 0 November 30, 2007 357 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 RX FIFO overrun interrupt is masked. 1 RX FIFO overrun interrupt is not masked. 0 RORIM R/W 0 358 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXRIS RXRIS RTRIS RORRIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXRIS RO 1 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 2 RXRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 1 RTRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. 0 RORRIS RO 0 November 30, 2007 359 Preliminary LM3S6952 Microcontroller Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXMIS RXMIS RTMIS RORMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0 SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 2 RXMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 1 RTMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. 0 RORMIS RO 0 360 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RTIC RORIC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. 1 RTIC W1C 0 SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. 0 RORIC W1C 0 November 30, 2007 361 Preliminary LM3S6952 Microcontroller Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x00 362 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x00 November 30, 2007 363 Preliminary LM3S6952 Microcontroller Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x00 364 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x00 November 30, 2007 365 Preliminary LM3S6952 Microcontroller Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x22 366 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 367 Preliminary LM3S6952 Microcontroller Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 368 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 369 Preliminary LM3S6952 Microcontroller Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 370 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 371 Preliminary LM3S6952 Microcontroller Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 372 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 373 Preliminary LM3S6952 Microcontroller 15 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S6952 microcontroller includes one I2C module, providing the ability to interact (both send and receive) with other I2C devices on the bus. Devices on the I2C bus can be designated as either a master or a slave. The Stellaris® I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates interrupts when data has been sent or requested by a master. 15.1 Block Diagram Figure 15-1. I2C Block Diagram I2C I/O Select I2C Master Core Interrupt I2C Slave Core I2CSCL I2CSDA I2CSDA I2CSCL I2CSDA I2CSCL I2CMSA I2CMCS I2CMDR I2CMTPR I2CMIMR I2CMRIS I2CMICR I2CMCR I2CSOAR I2CSCSR I2CSDR I2CSIM I2CSRIS I2CSMIS I2CMMIS I2CSICR I2C Control 15.2 Functional Description The I2C module is comprised of both master and slave functions which are implemented as separate peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 375. See “I2C” on page 539 for I2C timing diagrams. 374 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Figure 15-2. I2C Bus Configuration RPUP StellarisTM I2CSCL I2CSDA RPUP 3rd Party Device with I2C Interface SCL SDA I2C Bus SCL SDA 3rd Party Device with I2C Interface SCL SDA 15.2.1 I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris® microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are high. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 375) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 15.2.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 15-3 on page 375. Figure 15-3. START and STOP Conditions START condition SDA SCL STOP condition SDA SCL 15.2.1.2 Data Format with 7-Bit Address Data transfers follow the format shown in Figure 15-4 on page 376. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within a single transfer. November 30, 2007 375 Preliminary LM3S6952 Microcontroller Figure 15-4. Complete Data Transfer with a 7-Bit Address Slave address Data SDA MSB LSB R/S ACK MSB LSB ACK SCL 1 2 7 8 9 1 2 7 8 9 The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 376). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. Figure 15-5. R/S Bit in First Byte R/S LSB Slave address MSB 15.2.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is low (see Figure 15-6 on page 376). Figure 15-6. Data Validity During Bit Transfer on the I2C Bus Change of data allowed Dataline stable SDA SCL 15.2.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in “Data Validity” on page 376. When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Since the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. 376 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface 15.2.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low) will switch off its data output stage and retire until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 15.2.2 Available Speed Modes The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP. where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see page 394). The I2C clock period is calculated as follows: SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/T = 333 Khz Table 15-1 on page 377 gives examples of timer period, system clock, and speed mode (Standard or Fast). Table 15-1. Examples of I2C Master Timer Period versus Speed Mode System Clock Timer Period Standard Mode Timer Period Fast Mode 4 Mhz 0x01 100 Kbps - - 6 Mhz 0x02 100 Kbps - - 12.5 Mhz 0x06 89 Kbps 0x01 312 Kbps 16.7 Mhz 0x08 93 Kbps 0x02 278 Kbps 20 Mhz 0x09 100 Kbps 0x02 333 Kbps 25 Mhz 0x0C 96.2 Kbps 0x03 312 Kbps 33Mhz 0x10 97.1 Kbps 0x04 330 Kbps 40Mhz 0x13 100 Kbps 0x04 400 Kbps November 30, 2007 377 Preliminary LM3S6952 Microcontroller System Clock Timer Period Standard Mode Timer Period Fast Mode 50Mhz 0x18 100 Kbps 0x06 357 Kbps 15.2.3 Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested There is a separate interrupt signal for the I2C master and I2C modules. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 15.2.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction. An error condition is asserted if the last transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of the bus due to a lost arbitration round with another master. If an error is not detected, the application can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 15.2.3.2 I2C Slave Interrupts The slave module generates interrupts as it receives requests from an I2C master. To enable the I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 15.2.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. 378 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface 15.2.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 15.2.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. Figure 15-7. Master Single SEND Idle Write Slave Address to I2CMSA Write data to I2CMDR Read I2CMCS Sequence may be omitted in a Single Master system BUSBSY bit=0? NO Write ---0-111 to I2CMCS YES Read I2CMCS BUSY bit=0? ERROR bit=0? YES Error Service Idle YES NO NO November 30, 2007 379 Preliminary LM3S6952 Microcontroller Figure 15-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Read I2CMCS Sequence may be omitted in a Single Master system BUSBSY bit=0? NO Write ---00111 to I2CMCS YES Read I2CMCS BUSY bit=0? ERROR bit=0? YES Error Service Idle NO NO Read data from I2CMDR YES 380 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Figure 15-9. Master Burst SEND Idle Write Slave Address to I2CMSA Write data to I2CMDR Read I2CMCS BUSBSY bit=0? YES Write ---0-011 to I2CMCS NO Read I2CMCS BUSY bit=0? YES ERROR bit=0? YES Write data to ARBLST bit=1? I2CMDR Write ---0-100 to Index=n? I2CMCS NO Error Service Idle YES Write ---0-001 to I2CMCS Write ---0-101 to I2CMCS YES Read I2CMCS BUSY bit=0? ERROR bit=0? YES NO Idle YES Error Service NO NO NO NO Sequence may be omitted in a Single Master system November 30, 2007 381 Preliminary LM3S6952 Microcontroller Figure 15-10. Master Burst RECEIVE Idle Write Slave Address to I2CMSA Read I2CMCS BUSBSY bit=0? NO Write ---01011 to I2CMCS YES Read I2CMCS BUSY bit=0? NO ERROR bit=0? YES ARBLST bit=1? Write ---0-100 to I2CMCS NO Error Service YES Idle Read data from I2CMDR Index=m-1? Write ---00101 to I2CMCS YES Idle Read data from Error Service I2CMDR ERROR bit=0? YES Write ---01001 to I2CMCS Read I2CMCS BUSY bit=0? NO YES Sequence may be omitted in a Single Master system NO NO NO 382 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Figure 15-11. Master Burst RECEIVE after Burst SEND Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Master operates in Master Receive mode Idle Repeated START condition is generated with changing data direction November 30, 2007 383 Preliminary LM3S6952 Microcontroller Figure 15-12. Master Burst SEND after Burst RECEIVE Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Idle Repeated START condition is generated with changing data direction 15.2.5.2 I2C Slave Command Sequences Figure 15-13 on page 385 presents the command sequence available for the I2C slave. 384 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Figure 15-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR RREQ bit=1? Read data from I2CSDR YES TREQ bit=1? NO Write data to I2CSDR YES NO FBR is also valid 15.3 Initialization and Configuration The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation. 4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020. 5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: November 30, 2007 385 Preliminary LM3S6952 Microcontroller TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 6. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data. 8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has been cleared. 15.4 I2C Register Map Table 15-2 on page 386 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave: ■ I2C Master 0: 0x4002.0000 ■ I2C Slave 0: 0x4002.0800 Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map See Offset Name Type Reset Description page I2C Master 0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 388 0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 389 0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 393 0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 394 0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 395 0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 396 0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 397 0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 398 0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 399 I2C Slave 0x000 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 401 0x004 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 402 0x008 I2CSDR R/W 0x0000.0000 I2C Slave Data 404 0x00C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 405 386 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface See Offset Name Type Reset Description page 0x010 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 406 0x014 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 407 0x018 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 408 15.5 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also “Register Descriptions (I2C Slave)” on page 400. November 30, 2007 387 Preliminary LM3S6952 Microcontroller Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low). I2C Master Slave Address (I2CMSA) I2C Master 0 base: 0x4002.0000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SA R/S Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 I2C Slave Address This field specifies bits A6 through A0 of the slave address. 7:1 SA R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Send (Low). Value Description 0 Send. 1 Receive. 0 R/S R/W 0 388 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after each byte. This bit must be reset when the I2C bus controller requires no further data to be sent from the slave transmitter. Read-Only Status Register I2C Master Control/Status (I2CMCS) I2C Master 0 base: 0x4002.0000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x00 Bus Busy This bit specifies the state of the I2C bus. If set, the bus is busy; otherwise, the bus is idle. The bit changes based on the START and STOP conditions. 6 BUSBSY RO 0 I2C Idle This bit specifies the I2C controller state. If set, the controller is idle; otherwise the controller is not idle. 5 IDLE RO 0 Arbitration Lost This bit specifies the result of bus arbitration. If set, the controller lost arbitration; otherwise, the controller won arbitration. 4 ARBLST RO 0 November 30, 2007 389 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Acknowledge Data This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 3 DATACK RO 0 Acknowledge Address This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 2 ADRACK RO 0 Error This bit specifies the result of the last bus operation. If set, an error occurred on the last operation; otherwise, no error was detected. The error can be from the slave address not being acknowledged, the transmit data not being acknowledged, or because the controller lost arbitration. 1 ERROR RO 0 I2C Busy This bit specifies the state of the controller. If set, the controller is busy; otherwise, the controller is idle. When the BUSY bit is set, the other status bits are not valid. 0 BUSY RO 0 Write-Only Control Register I2C Master Control/Status (I2CMCS) I2C Master 0 base: 0x4002.0000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ACK STOP START RUN Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved WO 0x00 Data Acknowledge Enable When set, causes received data byte to be acknowledged automatically by the master. See field decoding in Table 15-3 on page 391. 3 ACK WO 0 Generate STOP When set, causes the generation of the STOP condition. See field decoding in Table 15-3 on page 391. 2 STOP WO 0 390 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset Description Generate START When set, causes the generation of a START or repeated START condition. See field decoding in Table 15-3 on page 391. 1 START WO 0 I2C Master Enable When set, allows the master to send or receive data. See field decoding in Table 15-3 on page 391. 0 RUN WO 0 Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) Current I2CMSA[0] I2CMCS[3:0] Description State R/S ACK STOP START RUN START condition followed by SEND (master goes to the Master Transmit state). Idle 0 Xa 0 1 1 START condition followed by a SEND and STOP condition (master remains in Idle state). 0 X 1 1 1 START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). 1 0 0 1 1 START condition followed by RECEIVE and STOP condition (master remains in Idle state). 1 0 1 1 1 START condition followed by RECEIVE (master goes to the Master Receive state). 1 1 0 1 1 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. NOP. SEND operation (master remains in Master Transmit state). Master X X 0 0 1 Transmit X X 1 0 0 STOP condition (master goes to Idle state). SEND followed by STOP condition (master goes to Idle state). X X 1 0 1 Repeated START condition followed by a SEND (master remains in Master Transmit state). 0 X 0 1 1 Repeated START condition followed by SEND and STOP condition (master goes to Idle state). 0 X 1 1 1 Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). 1 0 0 1 1 Repeated START condition followed by a SEND and STOP condition (master goes to Idle state). 1 0 1 1 1 Repeated START condition followed by RECEIVE (master goes to Master Receive state). 1 1 0 1 1 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. NOP. November 30, 2007 391 Preliminary LM3S6952 Microcontroller Current I2CMSA[0] I2CMCS[3:0] Description State R/S ACK STOP START RUN RECEIVE operation with negative ACK (master remains in Master Receive state). Master X 0 0 0 1 Receive X X 1 0 0 STOP condition (master goes to Idle state).b RECEIVE followed by STOP condition (master goes to Idle state). X 0 1 0 1 RECEIVE operation (master remains in Master Receive state). X 1 0 0 1 X 1 1 0 1 Illegal. Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). 1 0 0 1 1 Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). 1 0 1 1 1 Repeated START condition followed by RECEIVE (master remains in Master Receive state). 1 1 0 1 1 Repeated START condition followed by SEND (master goes to Master Transmit state). 0 X 0 1 1 Repeated START condition followed by SEND and STOP condition (master goes to Idle state). 0 X 1 1 1 All other combinations not listed are non-operations. NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. 392 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 3: I2C Master Data (I2CMDR), offset 0x008 This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C Master 0 base: 0x4002.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Data Transferred Data transferred during transaction. 7:0 DATA R/W 0x00 November 30, 2007 393 Preliminary LM3S6952 Microcontroller Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. I2C Master Timer Period (I2CMTPR) I2C Master 0 base: 0x4002.0000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TPR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 255). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). 7:0 TPR R/W 0x1 394 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C Master 0 base: 0x4002.0000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IM Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 IM R/W 0 November 30, 2007 395 Preliminary LM3S6952 Microcontroller Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C Master 0 base: 0x4002.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C master block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 0 RIS RO 0 396 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C Master 0 base: 0x4002.0000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C master block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 MIS RO 0 November 30, 2007 397 Preliminary LM3S6952 Microcontroller Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt. I2C Master Interrupt Clear (I2CMICR) I2C Master 0 base: 0x4002.0000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Interrupt Clear This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise, a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 0 IC WO 0 398 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C Master 0 base: 0x4002.0000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SFE MFE reserved LPBK Type RO RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 I2C Slave Function Enable This bit specifies whether the interface may operate in Slave mode. If set, Slave mode is enabled; otherwise, Slave mode is disabled. 5 SFE R/W 0 I2C Master Function Enable This bit specifies whether the interface may operate in Master mode. If set, Master mode is enabled; otherwise, Master mode is disabled and the interface clock is disabled. 4 MFE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:1 reserved RO 0x00 I2C Loopback This bit specifies whether the interface is operating normally or in Loopback mode. If set, the device is put in a test mode loopback configuration; otherwise, the device operates normally. 0 LPBK R/W 0 November 30, 2007 399 Preliminary LM3S6952 Microcontroller 15.6 Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also “Register Descriptions (I2C Master)” on page 387. 400 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 This register consists of seven address bits that identify the Stellaris® I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C Slave 0 base: 0x4002.0800 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OAR Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x00 I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. 6:0 OAR R/W 0x00 November 30, 2007 401 Preliminary LM3S6952 Microcontroller Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 This register accesses one control bit when written, and three status bits when read. The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First Byte Received (FBR) bit is set only after the Stellaris® device detects its own slave address and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that the Stellaris® I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit indicates that the Stellaris® I2C device is addressed as a Slave Transmitter. Write one data byte into the I2C Slave Data (I2CSDR) register to clear the TREQ bit. The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the Stellaris® I2C slave operation. Read-Only Status Register I2C Slave Control/Status (I2CSCSR) I2C Slave 0 base: 0x4002.0800 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FBR TREQ RREQ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 First Byte Received Indicates that the first byte following the slave’s own address is received. This bit is only valid when the RREQ bit is set, and is automatically cleared when data has been read from the I2CSDR register. Note: This bit is not used for slave transmit operations. 2 FBR RO 0 Transmit Request This bit specifies the state of the I2C slave with regards to outstanding transmit requests. If set, the I2C unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the I2CSDR register. Otherwise, there is no outstanding transmit request. 1 TREQ RO 0 Receive Request This bit specifies the status of the I2C slave with regards to outstanding receive requests. If set, the I2C unit has outstanding receive data from the I2C master and uses clock stretching to delay the master until the data has been read from the I2CSDR register. Otherwise, no receive data is outstanding. 0 RREQ RO 0 402 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Write-Only Control Register I2C Slave Control/Status (I2CSCSR) I2C Slave 0 base: 0x4002.0800 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Device Active Value Description 0 Disables the I2C slave operation. 1 Enables the I2C slave operation. 0 DA WO 0 November 30, 2007 403 Preliminary LM3S6952 Microcontroller Register 12: I2C Slave Data (I2CSDR), offset 0x008 This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C Slave 0 base: 0x4002.0800 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 7:0 DATA R/W 0x0 404 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C Slave 0 base: 0x4002.0800 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IM Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 IM R/W 0 November 30, 2007 405 Preliminary LM3S6952 Microcontroller Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C Slave 0 base: 0x4002.0800 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C slave block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 0 RIS RO 0 406 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C Slave 0 base: 0x4002.0800 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C slave block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 MIS RO 0 November 30, 2007 407 Preliminary LM3S6952 Microcontroller Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 This register clears the raw interrupt. I2C Slave Interrupt Clear (I2CSICR) I2C Slave 0 base: 0x4002.0800 Offset 0x018 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Clear Interrupt This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 0 IC WO 0 408 November 30, 2007 Preliminary Inter-Integrated Circuit (I2C) Interface 16 Ethernet Controller The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Ethernet Controller module has the following features: ■ Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line – 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler – Full-featured auto-negotiation ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps – Power-saving and power-down modes ■ Highly configurable – Programmable MAC address – LED activity selection – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Physical media manipulation – Automatic MDI/MDI-X cross-over correction – Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception November 30, 2007 409 Preliminary LM3S6952 Microcontroller 16.1 Block Diagram Figure 16-1. Ethernet Controller Block Diagram MACISR MACIACK MACIMR Interrupt Control MACRCR MACNPR Receive Control MACTCR MACITHR MACTRR Transmit Control Transmit FIFO Receive FIFO MACIAR0 MACIAR1 Individual Address MACMDTX MACMCR MACMDVR MACMAR MACMDRX MII Control MACDR Data Access TXOP TXON RXIP RXIN XTLP XTLN MDIX Clock Reference Transmit Encoding Pulse Shaping Receive Decoding Clock Recovery Auto Negotiation Carrier Sense MR3 MR0 MR1 MR2 MR4 Media Independent Interface Management Register Set MR5 MR18 MR6 MR16 MR17 MR19 MR23 MR24 Collision Detect System Clock Interrupt 16.2 Functional Description As shown in Figure 16-2 on page 410, the Ethernet Controller is functionally divided into two layers or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media Independent Interface (MII). Figure 16-2. Ethernet Controller Cortex M3 Media Access Controller MAC (Layer 2) Physical Layer Entity PHY (Layer 1) Magnetics RJ45 Ethernet Controller 16.2.1 Internal MII Operation For the MII management interface to function properly, the MDIO signal must be connected through a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent management transactions on this internal MII to function. Note that it is possible for data transmission across the MII to still function since the PHY layer will auto-negotiate the link parameters by default. 410 November 30, 2007 Preliminary Ethernet Controller For the MII management interface to function properly, the internal clock must be divided down from the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider used for scaling down the system clock. See page 430 for more details about the use of this register. 16.2.2 PHY Configuration/Operation The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external filter is required. 16.2.2.1 Clock Selection The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground. 16.2.2.2 Auto-Negotiation The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function can be enabled via register settings. The auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset. Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding. Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart. 16.2.2.3 Polarity Correction The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the signal polarity. 16.2.2.4 MDI/MDI-X Configuration The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002 specification. This eliminates the need for cross-over cables when connecting to another device, such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 452 for additional details about these settings. 16.2.2.5 LED Indicators The PHY supports two LED signals that can be used to indicate various states of operation of the Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page November 30, 2007 411 Preliminary LM3S6952 Microcontroller 163 for additional details. The function of these pins is programmable via the PHY layer MR23 register. Refer to page 451 for additonal details on how to program these LED functions. 16.2.3 MAC Configuration/Operation 16.2.3.1 Ethernet Frame Format Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure 16-3 on page 412. Figure 16-3. Ethernet Frame Preamble SFD Destination Address Source Address Length/ Type Data FCS 7 Bytes 6 Bytes 6 Bytes 2 Bytes 1 Byte 4 Bytes 46 - 1500 Bytes The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. ■ Preamble The Preamble field is used by the physical layer signaling circuitry to synchronize with the received frame’s timing. The preamble is 7 octets long. ■ Start Frame Delimiter (SFD) The SFD field follows the preamble pattern and indicates the start of the frame. Its value is 1010.1011. ■ Destination Address (DA) This field specifies destination addresses for which the frame is intended. The LSB of the DA determines whether the address is an individual (0), or group/multicast (1) address. ■ Source Address (SA) The source address field identifies the station from which the frame was initiated. ■ Length/Type Field The meaning of this field depends on its numeric value. The first of two octets is most significant. This field can be interpreted as length or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes type interpretation if the value of the Length/Type field is greater than 1500 decimal. ■ Data The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values can appear in this field. A minimum frame size is required to properly meet the IEEE standard. If necessary, the data field is extended by appending extra bits (a pad). The pad field can have a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets. The MAC module automatically inserts pads if required, though it can be disabled by a register 412 November 30, 2007 Preliminary Ethernet Controller write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received is too large to fit into the Ethernet Controller’s RAM. ■ Frame Check Sequence (FCS) The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this field is computed over destination address, source address, length/type, data, and pad fields using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by the CRC bit in the MACTCTL register. For received frames, this field is automatically checked. If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is disabled by the BADCRC bit in the MACRCTL register. 16.2.3.2 MAC Layer FIFOs For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to 1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload of up to 2032 bytes. For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames, up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO, an overflow error will be indicated. For details regarding the TX and RX FIFO layout, refer to Table 16-1 on page 413. Please note the following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions. For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been written to the FIFO. Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a word boundary. Table 16-1. TX & RX FIFO Organization FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read) Sequence 1st 7:0 Data Length LSB Frame Length LSB 15:8 Data Length MSB Frame Length MSB 23:16 DA oct 1 31:24 DA oct 2 2nd 7:0 DA oct 3 15:8 DA oct 4 23:16 DA oct 5 31:24 DA oct 6 3rd 7:0 SA oct 1 15:8 SA oct 2 23:16 SA oct 3 31:24 SA oct 4 November 30, 2007 413 Preliminary LM3S6952 Microcontroller FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read) Sequence 4th 7:0 SA oct 5 15:8 SA oct 6 23:16 Len/Type MSB 31:24 Len/Type LSB 5th to nth 7:0 data oct n 15:8 data oct n+1 23:16 data oct n+2 31:24 data oct n+3 FCS 1 (if the CRC bit in FCS 1 MACCTL is 0) last 7:0 FCS 2 (if the CRC bit in FCS 2 MACCTL is 0) 15:8 FCS 3 (if the CRC bit in FCS 3 MACCTL is 0) 23:16 FCS 4 (if the CRC bit in FCS 4 MACCTL is 0) 31:24 16.2.3.3 Ethernet Transmission Options The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS) at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test purposes, in order to generate a frame with an invalid CRC, this feature can be disabled. The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by the PADEN bit in the MACTCTL register. At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the DUPLEX bit in the MACTCTL register. 16.2.3.4 Ethernet Reception Options Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject incoming Ethernet frames with an invalid FCS field. The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and MACIA1 register will be placed into the RX FIFO. 16.2.4 Interrupts The Ethernet Controller can generate an interrupt for one or more of the following conditions: ■ A frame has been received into an empty RX FIFO ■ A frame transmission error has occurred ■ A frame has been transmitted successfully ■ A frame has been received with no room in the RX FIFO (overrun) 414 November 30, 2007 Preliminary Ethernet Controller ■ A frame has been received with one or more error conditions (for example, FCS failed) ■ An MII management transaction between the MAC and PHY layers has completed ■ One or more of the following PHY layer conditions occurs: – Auto-Negotiate Complete – Remote Fault – Link Status Change – Link Partner Acknowledge – Parallel Detect Fault – Page Received – Receive Error – Jabber Event Detected 16.3 Initialization and Configuration To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0 bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller for basic operation. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a 20-MHz system clock, the MACDIV value would be 4. 2. Program the MACIA0 and MACIA1 register for address filtering. 3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16. 4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08. 5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO will be available for the next transmit frame. 7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. When the frame (including the FCS field) has been read, the NPR field should decrement by one. When there are no more frames in the RX FIFO, the NPR field will read 0. 16.4 Ethernet Register Map Table 16-2 on page 416 lists the Ethernet MAC registers. All addresses given are relative to the Ethernet MAC base address of 0x4004.8000. November 30, 2007 415 Preliminary LM3S6952 Microcontroller The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. Table 16-2 on page 416 also lists these MII Management registers. All addresses given are absolute and are written directly to the REGADR field of the MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY implementations. The only variance allowed is for features that may or may not be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are reserved. Table 16-2. Ethernet Register Map See Offset Name Type Reset Description page Ethernet MAC 0x000 MACRIS RO 0x0000.0000 Ethernet MAC Raw Interrupt Status 418 0x000 MACIACK W1C 0x0000.0000 Ethernet MAC Interrupt Acknowledge 420 0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 421 0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 422 0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 423 0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 424 0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 426 0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 427 0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 428 0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 429 0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 430 0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 431 0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 432 0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 433 0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 434 MII Management - MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 435 - MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 437 Ethernet PHY Management Register 2 – PHY Identifier 439 - MR2 RO 0x000E 1 Ethernet PHY Management Register 3 – PHY Identifier 440 - MR3 RO 0x7237 2 Ethernet PHYManagement Register 4 – Auto-Negotiation 441 - MR4 R/W 0x01E1 Advertisement Ethernet PHYManagement Register 5 – Auto-Negotiation 443 - MR5 RO 0x0000 Link Partner Base Page Ability 416 November 30, 2007 Preliminary Ethernet Controller See Offset Name Type Reset Description page Ethernet PHYManagement Register 6 – Auto-Negotiation 444 - MR6 RO 0x0000 Expansion Ethernet PHY Management Register 16 – 445 - MR16 R/W 0x0140 Vendor-Specific Ethernet PHY Management Register 17 – Interrupt 447 - MR17 R/W 0x0000 Control/Status - MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 449 Ethernet PHY Management Register 19 – Transceiver 450 - MR19 R/W 0x4000 Control Ethernet PHY Management Register 23 – LED 451 - MR23 R/W 0x0010 Configuration Ethernet PHY Management Register 24 –MDI/MDIX 452 - MR24 R/W 0x00C0 Control 16.5 Ethernet MAC Register Descriptions The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. Also see “MII Management Register Descriptions” on page 434. November 30, 2007 417 Preliminary LM3S6952 Microcontroller Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 The MACRIS register is the interrupt status register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. Ethernet MAC Raw Interrupt Status (MACRIS) Base 0x4004.8000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x0 PHY Interrupt When set, indicates that an enabled interrupt in the PHY layer has occured. MR17 in the PHY must be read to determine the specific PHY event that triggered this interrupt. 6 PHYINT RO 0x0 MII Transaction Complete When set, indicates that a transaction (read or write) on the MII interface has completed successfully. 5 MDINT RO 0x0 Receive Error This bit indicates that an error was encountered on the receiver. The possible errors that can cause this interrupt bit to be set are: ■ A receive error occurs during the reception of a frame (100 Mb/s only). ■ The frame is not an integer number of bytes (dribble bits) due to an alignment error. ■ The CRC of the frame does not pass the FCS check. ■ The length/type field is inconsistent with the frame data size when interpreted as a length field. 4 RXER RO 0x0 FIFO Overrrun When set, indicates that an overrun was encountered on the receive FIFO. 3 FOV RO 0x0 Transmit FIFO Empty When set, indicates that the packet was transmitted and that the TX FIFO is empty. 2 TXEMP RO 0x0 418 November 30, 2007 Preliminary Ethernet Controller Bit/Field Name Type Reset Description Transmit Error When set, indicates that an error was encountered on the transmitter. The possible errors that can cause this interrupt bit to be set are: ■ The data length field stored in the TX FIFO exceeds 2032. The frame is not sent when this error occurs. ■ The retransmission attempts during the backoff process have exceeded the maximum limit of 16. 1 TXER RO 0x0 Packet Received When set, indicates that at least one packet has been received and is stored in the receiver FIFO. 0 RXINT RO 0x0 November 30, 2007 419 Preliminary LM3S6952 Microcontroller Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet MAC Raw Interrupt Status (MACRIS) register. Ethernet MAC Interrupt Acknowledge (MACIACK) Base 0x4004.8000 Offset 0x000 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT Type RO RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x0 Clear PHY Interrupt A write of a 1 clears the PHYINT interrupt read from the MACRIS register. 6 PHYINT W1C 0x0 Clear MII Transaction Complete A write of a 1 clears the MDINT interrupt read from the MACRIS register. 5 MDINT W1C 0x0 Clear Receive Error A write of a 1 clears the RXER interrupt read from the MACRIS register. 4 RXER W1C 0x0 Clear FIFO Overrun A write of a 1 clears the FOV interrupt read from the MACRIS register. 3 FOV W1C 0x0 Clear Transmit FIFO Empty A write of a 1 clears the TXEMP interrupt read from the MACRIS register. 2 TXEMP W1C 0x0 Clear Transmit Error A write of a 1 clears the TXER interrupt read from the MACRIS register and resets the TX FIFO write pointer. 1 TXER W1C 0x0 Clear Packet Received A write of a 1 clears the RXINT interrupt read from the MACRIS register. 0 RXINT W1C 0x0 420 November 30, 2007 Preliminary Ethernet Controller Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the interrupt, while writing a 1 enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x0 Mask PHY Interrupt This bit masks the PHYINT bit in the MACRIS register from being asserted. 6 PHYINTM R/W 1 Mask MII Transaction Complete This bit masks the MDINT bit in the MACRIS register from being asserted. 5 MDINTM R/W 1 Mask Receive Error This bit masks the RXER bit in the MACRIS register from being asserted. 4 RXERM R/W 1 Mask FIFO Overrrun This bit masks the FOV bit in the MACRIS register from being asserted. 3 FOVM R/W 1 Mask Transmit FIFO Empty This bit masks the TXEMP bit in the MACRIS register from being asserted. 2 TXEMPM R/W 1 Mask Transmit Error This bit masks the TXER bit in the MACRIS register from being asserted. 1 TXERM R/W 1 Mask Packet Received This bit masks the RXINT bit in the MACRIS register from being asserted. 0 RXINTM R/W 1 November 30, 2007 421 Preliminary LM3S6952 Microcontroller Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register enables software to configure the receive module and control the types of frames that are received from the physical medium. It is important to note that when the receive module is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field will be received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.8000 Offset 0x008 Type R/W, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RSTFIFO BADCRC PRMS AMUL RXEN Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x0 Clear Receive FIFO When set, clears the receive FIFO. This should be done when software initialization is performed. It is recommended that the receiver be disabled (RXEN = 0), and then the reset initiated (RSTFIFO = 1). This sequence will flush and reset the RX FIFO. 4 RSTFIFO R/W 0x0 Enable Reject Bad CRC The BADCRC bit enables the rejection of frames with an incorrectly calculated CRC. 3 BADCRC R/W 0x1 Enable Promiscuous Mode The PRMS bit enables Promiscuous mode, which accepts all valid frames, regardless of the Destination Address. 2 PRMS R/W 0x0 Enable Multicast Frames The AMUL bit enables the reception of multicast frames from the physical medium. 1 AMUL R/W 0x0 Enable Receiver The RXEN bit enables the Ethernet receiver. When this bit is Low, the receiver is disabled and all frames on the physical medium are ignored. 0 RXEN R/W 0x0 422 November 30, 2007 Preliminary Ethernet Controller Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register enables software to configure the transmit module, and control frames are placed onto the physical medium. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DUPLEX reserved CRC PADEN TXEN Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x0 Enable Duplex Mode When set, enables Duplex mode, allowing simultaneous transmission and reception. 4 DUPLEX R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0x0 Enable CRC Generation When set, enables the automatic generation of the CRC and the placement at the end of the packet. If this bit is not set, the frames placed in the TX FIFO will be sent exactly as they are written into the FIFO. 2 CRC R/W 0x0 Enable Packet Padding When set, enables the automatic padding of packets that do not meet the minimum frame size. 1 PADEN R/W 0x0 Enable Transmitter When set, enables the transmitter. When this bit is 0, the transmitter is disabled. 0 TXEN R/W 0x0 November 30, 2007 423 Preliminary LM3S6952 Microcontroller Register 6: Ethernet MAC Data (MACDATA), offset 0x010 This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is then auto-incremented to the next TX FIFO location. There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written. Read-Only Register Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXDATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Receive FIFO Data The RXDATA bits represent the next four bytes of data stored in the RX FIFO. 31:0 RXDATA RO 0x0 Write-Only Register Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXDATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 424 November 30, 2007 Preliminary Ethernet Controller Bit/Field Name Type Reset Description Transmit FIFO Data The TXDATA bits represent the next four bytes of data to place in the TX FIFO for transmission. 31:0 TXDATA WO 0x0 November 30, 2007 425 Preliminary LM3S6952 Microcontroller Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MACOCT4 MACOCT3 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACOCT2 MACOCT1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description MAC Address Octet 4 The MACOCT4 bits represent the fourth octet of the MAC address used to uniquely identify each Ethernet Controller. 31:24 MACOCT4 R/W 0x0 MAC Address Octet 3 The MACOCT3 bits represent the third octet of the MAC address used to uniquely identify each Ethernet Controller. 23:16 MACOCT3 R/W 0x0 MAC Address Octet 2 The MACOCT2 bits represent the second octet of the MAC address used to uniquely identify each Ethernet Controller. 15:8 MACOCT2 R/W 0x0 MAC Address Octet 1 The MACOCT1 bits represent the first octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT1 R/W 0x0 426 November 30, 2007 Preliminary Ethernet Controller Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.8000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACOCT6 MACOCT5 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 MAC Address Octet 6 The MACOCT6 bits represent the sixth octet of the MAC address used to uniquely identify each Ethernet Controller. 15:8 MACOCT6 R/W 0x0 MAC Address Octet 5 The MACOCT5 bits represent the fifth octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT5 R/W 0x0 November 30, 2007 427 Preliminary LM3S6952 Microcontroller Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature. Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission starts when: Number of Bytes >= 4 (THRESH x 8 + 1) Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins and then the number of bytes indicated by the Data Length field is sent out on the physical medium. Because under-run checking is not performed, it is possible that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate values to be written to the physical medium rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software. If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register must be set with an explicit write. This initiates the transmission of the frame even though the threshold limit has not been reached. If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Ethernet MAC Threshold (MACTHR) Base 0x4004.8000 Offset 0x01C Type R/W, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved THRESH Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x0 Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds this value, transmission of the packet begins. 5:0 THRESH R/W 0x3F 428 November 30, 2007 Preliminary Ethernet Controller Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description of each of these registers can be found in Table 16-2 on page 416 and in “MII Management Register Descriptions” on page 434. In order to initiate a read transaction from the MII Management registers, the WRITE bit must be written with a 0 during the same cycle that the START bit is written with a 1. In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written with a 1 during the same cycle that the START bit is written with a 1. Ethernet MAC Management Control (MACMCTL) Base 0x4004.8000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved REGADR reserved WRITE START Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0 MII Register Address The REGADR bit field represents the MII Management register address for the next MII management interface transaction. 7:3 REGADR R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0x0 MII Register Transaction Type The WRITE bit represents the operation of the next MII management interface transaction. If WRITE is set, the next operation will be a write; otherwise, it will be a read. 1 WRITE R/W 0x0 MII Register Transaction Enable The START bit represents the initiation of the next MII management interface transaction. When a 1 is written to this bit, the MII register located at REGADR will be read (WRITE=0) or written (WRITE=1). 0 START R/W 0x0 November 30, 2007 429 Preliminary LM3S6952 Microcontroller Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions between the system and the MII Management registers. The frequency of the MDC clock can be calculated from the following formula: Fmdc = Fipclk / (2 * (MACMDVR + 1 )) The clock divider must be written with a value that ensures that the MDC clock will not exceed a frequency of 2.5 MHz. Ethernet MAC Management Divider (MACMDV) Base 0x4004.8000 Offset 0x024 Type R/W, reset 0x0000.0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIV Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0 Clock Divider The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the MAC and PHY over the serial MII interface. 7:0 DIV R/W 0x80 430 November 30, 2007 Preliminary Ethernet Controller Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDTX Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 MII Register Transmit Data The MDTX bits represent the data that will be written in the next MII management transaction. 15:0 MDTX R/W 0x0 November 30, 2007 431 Preliminary LM3S6952 Microcontroller Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDRX Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 MII Register Receive Data The MDRX bits represent the data that was read in the previous MII management transaction. 15:0 MDRX R/W 0x0 432 November 30, 2007 Preliminary Ethernet Controller Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set. Ethernet MAC Number of Packets (MACNP) Base 0x4004.8000 Offset 0x034 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NPR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x0 Number of Packets in Receive FIFO The NPR bits represent the number of packets stored in the RX FIFO. While the NPR field is greater than 0, the RXINT interrupt in the MACRIS register will be asserted. 5:0 NPR RO 0x0 November 30, 2007 433 Preliminary LM3S6952 Microcontroller Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NEWTX Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x0 New Transmission When set, the NEWTX bit initiates an Ethernet transmission once the packet has been placed in the TX FIFO. This bit is cleared once the transmission has been completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set. 0 NEWTX R/W 0x0 16.6 MII Management Register Descriptions The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY. The registers are collectively known as the MII Management registers. All addresses given are absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register Descriptions” on page 417. 434 November 30, 2007 Preliminary Ethernet Controller Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 This register enables software to configure the operation of the PHY. The default settings of these registers are designed to initialize the PHY to a normal operational mode without configuration. Ethernet PHY Management Register 0 – Control (MR0) Base 0x4004.8000 Address 0x00 Type R/W, reset 0x3100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT reserved Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Reset Registers When set, resets the registers to their default state and reinitializes internal state machines. Once the reset operation has completed, this bit is cleared by hardware. 15 RESET R/W 0 Loopback Mode When set, enables the Loopback mode of operation. The receive circuitry is isolated from the physical medium and transmissions are sent back through the receive circuitry instead of the medium. 14 LOOPBK R/W 0 Speed Select 1: Enables the 100 Mb/s mode of operation (100BASE-TX). 0: Enables the 10 Mb/s mode of operation (10BASE-T). 13 SPEEDSL R/W 1 Auto-Negotiation Enable When set, enables the Auto-Negotiation process. 12 ANEGEN R/W 1 Power Down When set, places the PHY into a low-power consuming state. 11 PWRDN R/W 0 Isolate When set, isolates transmit and receive data paths and ignores all signaling on these buses. 10 ISO R/W 0 Restart Auto-Negotiation When set, restarts the Auto-Negotiation process. Once the restart has initiated, this bit is cleared by hardware. 9 RANEG R/W 0 Set Duplex Mode 1: Enables the Full-Duplex mode of operation. This bit can be set by software in a manual configuration process or by the Auto-Negotiation process. 0: Enables the Half-Duplex mode of operation. 8 DUPLEX R/W 1 November 30, 2007 435 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Collision Test When set, enables the Collision Test mode of operation. The COLT bit asserts after the initiation of a transmission and de-asserts once the transmission is halted. 7 COLT R/W 0 6:0 reserved R/W 0x00 Write as 0, ignore on read. 436 November 30, 2007 Preliminary Ethernet Controller Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 This register enables software to determine the capabilities of the PHY and perform its initialization and operation appropriately. Ethernet PHY Management Register 1 – Status (MR1) Base 0x4004.8000 Address 0x01 Type RO, reset 0x7849 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 100X_F 100X_H 10T_F 10T_H reserved MFPS ANEGC RFAULT ANEGA LINK JAB EXTD Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO Reset 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 100BASE-TX Full-Duplex Mode When set, indicates that the PHY is capable of supporting 100BASE-TX Full-Duplex mode. 14 100X_F RO 1 100BASE-TX Half-Duplex Mode When set, indicates that the PHY is capable of supporting 100BASE-TX Half-Duplex mode. 13 100X_H RO 1 10BASE-T Full-Duplex Mode When set, indicates that the PHY is capable of 10BASE-T Full-Duplex mode. 12 10T_F RO 1 10BASE-T Half-Duplex Mode When set, indicates that the PHY is capable of supporting 10BASE-T Half-Duplex mode. 11 10T_H RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:7 reserved RO 0 Management Frames with Preamble Suppressed When set, indicates that the Management Interface is capable of receiving management frames with the preamble suppressed. 6 MFPS RO 1 Auto-Negotiation Complete When set, indicates that the Auto-Negotiation process has been completed and that the extended registers defined by the Auto-Negotiation protocol are valid. 5 ANEGC RO 0 Remote Fault When set, indicates that a remote fault condition has been detected. This bit remains set until it is read, even if the condition no longer exists. 4 RFAULT RC 0 November 30, 2007 437 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Auto-Negotiation When set, indicates that the PHY has the ability to perform Auto-Negotiation. 3 ANEGA RO 1 Link Made When set, indicates that a valid link has been established by the PHY. 2 LINK RO 0 Jabber Condition When set, indicates that a jabber condition has been detected by the PHY. This bit remains set until it is read, even if the jabber condition no longer exists. 1 JAB RC 0 Extended Capabilities When set, indicates that the PHY provides an extended set of capabilities that can be accessed through the extended register set. 0 EXTD RO 1 438 November 30, 2007 Preliminary Ethernet Controller Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Base 0x4004.8000 Address 0x02 Type RO, reset 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUI[21:6] Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 Bit/Field Name Type Reset Description Organizationally Unique Identifier[21:6] This field, along with the OUI[5:0] field in MR3, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 15:0 OUI[21:6] RO 0x000E November 30, 2007 439 Preliminary LM3S6952 Microcontroller Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Base 0x4004.8000 Address 0x03 Type RO, reset 0x7237 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUI[5:0] MN RN Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 Bit/Field Name Type Reset Description Organizationally Unique Identifier[5:0] This field, along with the OUI[21:6] field in MR2, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 15:10 OUI[5:0] RO 0x1C Model Number The MN field represents the Model Number of the PHY. 9:4 MN RO 0x23 Revision Number The RN field represents the Revision Number of the PHY. 3:0 RN RO 0x7 440 November 30, 2007 Preliminary Ethernet Controller Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is re-initiated. Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4) Base 0x4004.8000 Address 0x04 Type R/W, reset 0x01E1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP reserved RF reserved A3 A2 A1 A0 S[4:0] Type RO RO R/W RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit/Field Name Type Reset Description Next Page When set, indicates the PHY is capable of Next Page exchanges to provide more detailed information on the PHY’s capabilities. 15 NP RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 reserved RO 0 Remote Fault When set, indicates to the link partner that a Remote Fault condition has been encountered. 13 RF R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:9 reserved RO 0 Technology Ability Field[3] When set, indicates that the PHY supports the 100Base-TX full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated with the RANEG bit in the MR0 register. 8 A3 R/W 1 Technology Ability Field[2] When set, indicates that the PHY supports the 100Base-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 7 A2 R/W 1 Technology Ability Field[1] When set, indicates that the PHY supports the 10Base-T full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 6 A1 R/W 1 Technology Ability Field[0] When set, indicates that the PHY supports the 10Base-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 5 A0 R/W 1 November 30, 2007 441 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Selector Field The S[4:0] field encodes 32 possible messages for communicating between PHYs. This field is hard-coded to 0x01, indicating that the Stellaris® PHY is IEEE 802.3 compliant. 4:0 S[4:0] RO 0x01 442 November 30, 2007 Preliminary Ethernet Controller Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 This register provides the advertised abilities of the link partner’s PHY that are received and stored during Auto-Negotiation. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5) Base 0x4004.8000 Address 0x05 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP ACK RF A[7:0] S[4:0] Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Next Page When set, indicates that the link partner’s PHY is capable of Next page exchanges to provide more detailed information on the PHY’s capabilities. 15 NP RO 0 Acknowledge When set, indicates that the device has successfully received the link partner’s advertised abilities during Auto-Negotiation. 14 ACK RO 0 Remote Fault Used as a standard transport mechanism for transmitting simple fault information. 13 RF RO 0 Technology Ability Field The A[7:0] field encodes individual technologies that are supported by the PHY. See the MR4 register. 12:5 A[7:0] RO 0x00 Selector Field The S[4:0] field encodes possible messages for communicating between PHYs. Value Description 0x00 Reserved 0x01 IEEE Std 802.3 0x02 IEEE Std 802.9 ISLAN-16T 0x03 IEEE Std 802.5 0x04 IEEE Std 1394 0x05–0x1F Reserved 4:0 S[4:0] RO 0x00 November 30, 2007 443 Preliminary LM3S6952 Microcontroller Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 This register enables software to determine the Auto-Negotiation and Next Page capabilities of the PHY and the link partner after Auto-Negotiation. Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Base 0x4004.8000 Address 0x06 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PDF LPNPA reserved PRX LPANEGA Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0x000 Parallel Detection Fault When set, indicates that more than one technology has been detected at link up. This bit is cleared when read. 4 PDF RC 0 Link Partner is Next Page Able When set, indicates that the link partner is Next Page Able. 3 LPNPA RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0x000 New Page Received When set, indicates that a New Page has been received from the link partner and stored in the appropriate location. This bit remains set until the register is read. 1 PRX RC 0 Link Partner is Auto-Negotiation Able When set, indicates that the Link partner is Auto-Negotiation Able. 0 LPANEGA RO 0 444 November 30, 2007 Preliminary Ethernet Controller Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 This register enables software to configure the operation of vendor-specific modes of the PHY. Ethernet PHY Management Register 16 – Vendor-Specific (MR16) Base 0x4004.8000 Address 0x10 Type R/W, reset 0x0140 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RPTR INPOL reserved TXHIM SQEI NL10 reserved APOL RVSPOL reserved PCSBP RXCC Type R/W R/W RO R/W R/W R/W RO RO RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 Bit/Field Name Type Reset Description Repeater Mode When set, enables the repeater mode of operation. In this mode, full-duplex is not allowed and the Carrier Sense signal only responds to receive activity. If the PHY is configured to 10Base-T mode, the SQE test function is disabled. 15 RPTR R/W 0 Interrupt Polarity 1: Sets the polarity of the PHY interrupt to be active High. 0: Sets the polarity of the PHY interrupt to active Low. Important: Because the Media Access Controller expects active Low interrupts from the PHY, this bit must always be written with a 0 to ensure proper operation. 14 INPOL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 Transmit High Impedance Mode When set, enables the transmitter High Impedance mode. In this mode, the TXOP and TXON transmitter pins are put into a high impedance state. The RXIP and RXIN pins remain fully functional. 12 TXHIM R/W 0 SQE Inhibit Testing When set, prohibits 10Base-T SQE testing. When 0, the SQE testing is performed by generating a Collision pulse following the completion of the transmission of a frame. 11 SQEI R/W 0 Natural Loopback Mode When set, enables the 10Base-T Natural Loopback mode. This causes the transmission data received by the PHY to be looped back onto the receive data path when 10Base-T mode is enabled. 10 NL10 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:6 reserved RO 0x05 November 30, 2007 445 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Auto-Polarity Disable When set, disables the PHY’s auto-polarity function. If this bit is 0, the PHY automatically inverts the received signal due to a wrong polarity connection during Auto-Negotiation if the PHY is in 10Base-T mode. 5 APOL R/W 0 Receive Data Polarity This bit indicates whether the receive data pulses are being inverted. If the APOL bit is 0, then the RVSPOL bit is read-only and indicates whether the auto-polarity circuitry is reversing the polarity. In this case, a 1 in the RVSPOL bit indicates that the receive data is inverted while a 0 indicates that the receive data is not inverted. If the APOL bit is 1, then the RVSPOL bit is writable and software can force the receive data to be inverted. Setting RVSPOL to 1 forces the receive data to be inverted while a 0 does not invert the receive data. 4 RVSPOL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 PCS Bypass When set, enables the bypass of the PCS and scrambling/descrambling functions in 100Base-TX mode. This mode is only valid when Auto-Negotiation is disabled and 100Base-T mode is enabled. 1 PCSBP R/W 0 Receive Clock Control When set, enables the Receive Clock Control power saving mode if the PHY is configured in 100Base-TX mode. This mode shuts down the receive clock when no data is being received from the physical medium to save power. This mode should not be used when PCSBP is enabled and is automatically disabled when the LOOPBK bit in the MR0 register is set. 0 RXCC R/W 0 446 November 30, 2007 Preliminary Ethernet Controller Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 This register provides the means for controlling and observing the events, which trigger a PHY interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial Interface as a means to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding bit in the lower byte to signal a PHY interrupt in the MACRIS register. Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17) Base 0x4004.8000 Address 0x11 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INTRXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT Type R/W R/W R/W R/W R/W R/W R/W R/W RC RC RC RC RC RC RC RC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Jabber Interrupt Enable When set, enables system interrupts when a Jabber condition is detected by the PHY. 15 JABBER_IE R/W 0 Receive Error Interrupt Enable When set, enables system interrupts when a receive error is detected by the PHY. 14 RXER_IE R/W 0 Page Received Interrupt Enable When set, enables system interrupts when a new page is received by the PHY. 13 PRX_IE R/W 0 Parallel Detection Fault Interrupt Enable When set, enables system interrupts when a Parallel Detection Fault is detected by the PHY. 12 PDF_IE R/W 0 LP Acknowledge Interrupt Enable When set, enables system interrupts when FLP bursts are received with the Acknowledge bit during Auto-Negotiation. 11 LPACK_IE R/W 0 Link Status Change Interrupt Enable When set, enables system interrupts when the Link Status changes from OK to FAIL. 10 LSCHG_IE R/W 0 Remote Fault Interrupt Enable When set, enables system interrupts when a Remote Fault condition is signaled by the link partner. 9 RFAULT_IE R/W 0 Auto-Negotiation Complete Interrupt Enable When set, enables system interrupts when the Auto-Negotiation sequence has completed successfully. 8 ANEGCOMP_IE R/W 0 November 30, 2007 447 Preliminary LM3S6952 Microcontroller Bit/Field Name Type Reset Description Jabber Event Interrupt When set, indicates that a Jabber event has been detected by the 10Base-T circuitry. 7 JABBER_INT RC 0 Receive Error Interrupt When set, indicates that a receive error has been detected by the PHY. 6 RXER_INT RC 0 Page Receive Interrupt When set, indicates that a new page has been received from the link partner during Auto-Negotiation. 5 PRX_INT RC 0 Parallel Detection Fault Interrupt When set, indicates that a Parallel Detection Fault has been detected by the PHY during the Auto-Negotiation process. 4 PDF_INT RC 0 LP Acknowledge Interrupt When set, indicates that an FLP burst has been received with the Acknowledge bit set during Auto-Negotiation. 3 LPACK_INT RC 0 Link Status Change Interrupt When set, indicates that the link status has changed from OK to FAIL. 2 LSCHG_INT RC 0 Remote Fault Interrupt When set, indicates that a Remote Fault condition has been signaled by the link partner. 1 RFAULT_INT RC 0 Auto-Negotiation Complete Interrupt When set, indicates that the Auto-Negotiation sequence has completed successfully. 0 ANEGCOMP_INT RC 0 448 November 30, 2007 Preliminary Ethernet Controller Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 This register enables software to diagnose the results of the previous Auto-Negotiation. Ethernet PHY Management Register 18 – Diagnostic (MR18) Base 0x4004.8000 Address 0x12 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ANEGF DPLX RATE RXSD RX_LOCK reserved Type RO RO RO RC RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 Auto-Negotiation Failure When set, indicates that no common technology was found during Auto-Negotiation and has failed. This bit remains set until read. 12 ANEGF RC 0 Duplex Mode When set, indicates that Full-Duplex was the highest common denominator found during the Auto-Negotiation process. Otherwise, Half-Duplex was the highest common denominator found. 11 DPLX RO 0 Rate When set, indicates that 100Base-TX was the highest common denominator found during the Auto-Negotiation process. Otherwise, 10Base-TX was the highest common denominator found. 10 RATE RO 0 Receive Detection When set, indicates that receive signal detection has occurred (in 100Base-TX mode) or that Manchester-encoded data has been detected (in 10Base-T mode). 9 RXSD RO 0 Receive PLL Lock When set, indicates that the Receive PLL has locked onto the receive signal for the selected speed of operation (10Base-T or 100Base-TX). 8 RX_LOCK RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 00 November 30, 2007 449 Preliminary LM3S6952 Microcontroller Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 This register enables software to set the gain of the transmit output to compensate for transformer loss. Ethernet PHY Management Register 19 – Transceiver Control (MR19) Base 0x4004.8000 Address 0x13 Type R/W, reset 0x4000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXO[1:0] reserved Type R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Transmit Amplitude Selection The TXO[1:0] field sets the transmit output amplitude to account for transmit transformer insertion loss. Value Description 0x0 Gain set for 0.0dB of insertion loss 0x1 Gain set for 0.4dB of insertion loss 0x2 Gain set for 0.8dB of insertion loss 0x3 Gain set for 1.2dB of insertion loss 15:14 TXO[1:0] R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13:0 reserved RO 0x0 450 November 30, 2007 Preliminary Ethernet Controller Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 This register enables software to select the source that will cause the LEDs to toggle. Ethernet PHY Management Register 23 – LED Configuration (MR23) Base 0x4004.8000 Address 0x17 Type R/W, reset 0x0010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LED1[3:0] LED0[3:0] Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 reserved RO 0x0 LED1 Source The LED1 field selects the source that will toggle the LED1 signal. Value Description 0x0 Link OK 0x1 RX or TX Activity (Default LED1) 0x2 TX Activity 0x3 RX Activity 0x4 Collision 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity 7:4 LED1[3:0] R/W 1 LED0 Source The LED0 field selects the source that will toggle the LED0 signal. Value Description 0x0 Link OK (Default LED0) 0x1 RX or TX Activity 0x2 TX Activity 0x3 RX Activity 0x4 Collision 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity 3:0 LED0[3:0] R/W 0 November 30, 2007 451 Preliminary LM3S6952 Microcontroller Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities. Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24) Base 0x4004.8000 Address 0x18 Type R/W, reset 0x00C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PD_MODEAUTO_SW MDIX MDIX_CM MDIX_SD Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 reserved RO 0x0 Parallel Detection Mode When set, enables the Parallel Detection mode and allows auto-switching to work when Auto-Negotiation is not enabled. 7 PD_MODE R/W 0 Auto-Switching Enable When set, enables Auto-Switching of the MDI/MDIX mux. 6 AUTO_SW R/W 0 Auto-Switching Configuration When set, indicates that the MDI/MDIX mux is in the crossover (MDIX) configuration. When 0, it indicates that the mux is in the pass-through (MDI) configuration. When the AUTO_SW bit is 1, the MDIX bit is read-only. When the AUTO_SW bit is 0, the MDIX bit is read/write and can be configured manually. 5 MDIX R/W 0 Auto-Switching Complete When set, indicates that the auto-switching sequence has completed. If 0, it indicates that the sequence has not completed or that auto-switching is disabled. 4 MDIX_CM RO 0 Auto-Switching Seed This field provides the initial seed for the switching algorithm. This seed directly affects the number of attempts [5,4] respectively to write bits [3:0]. A 0 sets the seed to 0x5. 3:0 MDIX_SD R/W 0 452 November 30, 2007 Preliminary Ethernet Controller 17 Analog Comparators An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6952 controller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. Note: Not all comparators have the option to drive an output pin. See the Comparator Operating Mode tables for more information. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. November 30, 2007 453 Preliminary LM3S6952 Microcontroller 17.1 Block Diagram Figure 17-1. Analog Comparator Module Block Diagram interrupt C2+ C2- output +ve input (alternate) +ve input interrupt -ve input reference input Comparator 2 ACSTAT2 ACCTL2 interrupt C1- C1+ output +ve input (alternate) +ve input interrupt -ve input reference input Comparator 1 ACSTAT1 ACCTL1 C1o Voltage Ref ACREFCTL output +ve input (alternate) +ve input interrupt -ve input reference input Comparator 0 ACSTAT0 ACCTL0 C0+ internal bus interrupt C0- C0o