L6562 STMicroelectronics - Farnell Element 14 - Revenir à l'accueil
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Analog-Devices-Basic..> 08-Sep-2014 17:49 1.9M
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Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464KL6562 November 2005 1 Features ■ REALISED IN BCD TECHNOLOGY ■ TRANSITION-MODE CONTROL OF PFC PREREGULATORS ■ PROPRIETARY MULTIPLIER DESIGN FOR MINIMUM THD OF AC INPUT CURRENT ■ VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION ■ ULTRA-LOW (≤70μA) START-UP CURRENT ■ LOW (≤4 mA) QUIESCENT CURRENT ■ EXTENDED IC SUPPLY VOLTAGE RANGE ■ ON-CHIP FILTER ON CURRENT SENSE ■ DISABLE FUNCTION ■ 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE ■ -600/+800mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN AND VOLTAGE CLAMP ■ DIP-8/SO-8 PACKAGES ECOPACK® 1.1 APPLICATIONS ■ PFC PRE-REGULATORS FOR: – IEC61000-3-2 COMPLIANT SMPS (TV, DESKTOP PC, MONITOR) UP TO 300W – HI-END AC-DC ADAPTER/CHARGER – ENTRY LEVEL SERVER & WEB SERVER 2 Description The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible with the predecessor L6561, it offers improved performance. TRANSITION-MODE PFC CONTROLLER Figure 2. Block Diagram + - MULTIPLIER AND THD OPTIMIZER VREF2 OVERVOLTAGE DETECTION VOLTAGE REGULATOR UVLO INTERNAL SUPPLY 7V + - 2.5V R1 R2 R S Q - + DRIVER STARTER + - ZERO CURRENT DETECTOR DISABLE 2.1 V 1.6 V VCC 8 1 2 3 4 ZCD VCC INV COMP MULT CS GD 7 5 GND 6 25 V 40K 5pF 15 V Starter stop Rev. 8 Figure 1. Packages Table 1. Order Codes Part Number Package L6562N DIP-8 L6562D SO-8 L6562DTR Tape & Reel DIP-8 SO-8 L6562 2/16 2 Description (continued) The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj = 25°C) internal voltage reference. The device features extremely low consumption (≤70 μA before start-up and <4 mA running) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS's up to 300W. Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Symbol Pin Parameter Value Unit VCC 8 IC Supply voltage (Icc = 20 mA) self-limited V --- 1 to 4 Analog Inputs & Outputs -0.3 to 8 V IZCD 5 Zero Current Detector Max. Current -50 (source) 10 (sink) mA Ptot Power Dissipation @Tamb = 50°C (DIP-8) (SO-8) 1 0.65 W Tj Junction Temperature Operating range -40 to 150 °C Tstg Storage Temperature -55 to 150 °C Symbol Parameter SO8 Minidip Unit Rth j-amb Max. Thermal Resistance, Junction-to-ambient 150 100 °C/W ZCD INV COMP MULT CS Vcc GD GND 1 2 3 4 8 7 6 5 3/16 L6562 Table 4. Pin Description N° Pin Function 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off. 5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes. Table 5. Electrical Characteristics (Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VOLTAGE VCC Operating range After turn-on 10.3 22 V VCCon Turn-on threshold (1) 11 12 13 V VCCOff Turn-off threshold (1) 8.7 9.5 10.3 V Hys Hysteresis 2.2 2.8 V VZ Zener Voltage ICC = 20 mA 22 25 28 V SUPPLY CURRENT Istart-up Start-up Current Before turn-on, VCC =11V 40 70 μA Iq Quiescent Current After turn-on 2.5 3.75 mA ICC Operating Supply Current @ 70 kHz 3.5 5 mA Iq Quiescent Current During OVP (either static or dynamic) or VZCD =150 mV 2.2 mA MULTIPLIER INPUT IMULT Input Bias Current VVFF = 0 to 4 V -1 μA VMULT Linear Operation Range 0 to 3 V Output Max. Slope VMULT = 0 to 0.5V VCOMP = Upper clamp 1.65 1.9 V/V K Gain (2) VMULT = 1 V, VCOMP = 4 V 0.5 0.6 0.7 1/V ERROR AMPLIFIER VINV Voltage Feedback Input Threshold Tj = 25 °C 2.465 2.5 2.535 V 10.3 V < Vcc < 22 V (1) 2.44 2.56 Line Regulation Vcc = 10.3 V to 22V 2 5 mV IINV Input Bias Current VINV = 0 to 3 V -1 μA ΔVCS ΔVMULT --------------------- L6562 4/16 (1) All parameters are in tracking (2) The multiplier output is given by: (3) Parameters guaranteed by design, functionality tested in production. Gv Voltage Gain Open loop 60 80 dB GB Gain-Bandwidth Product 1 MHz ICOMP Source Current VCOMP = 4V, VINV = 2.4 V -2 -3.5 -5 mA Sink Current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 mA VCOMP Upper Clamp Voltage ISOURCE = 0.5 mA 5.3 5.7 6 V Lower Clamp Voltage ISINK = 0.5 mA (1) 2.1 2.25 2.4 V CURRENT SENSE COMPARATOR ICS Input Bias Current VCS = 0 -1 μA td(H-L) Delay to Output 200 350 ns VCS clamp Current sense reference clamp VCOMP = Upper clamp 1.6 1.7 1.8 V VCSoffset Current sense offset VMULT = 0 30 mV VMULT = 2.5V 5 ZERO CURRENT DETECTOR VZCDH Upper Clamp Voltage IZCD = 2.5 mA 5.0 5.7 6.5 V VZCDL Lower Clamp Voltage IZCD = -2.5 mA 0.3 0.65 1 V VZCDA Arming Voltage (positive-going edge) (3) 2.1 V VZCDT Triggering Voltage (negative-going edge) (3) 1.6 V IZCDb Input Bias Current VZCD = 1 to 4.5 V 2 μA IZCDsrc Source Current Capability -2.5 -5.5 mA IZCDsnk Sink Current Capability 2.5 mA VZCDdis Disable threshold 150 200 250 mV VZCDen Restart threshold 350 mV IZCDres Restart Current after Disable 30 75 μA STARTER tSTART Start Timer period 75 130 300 μs OUTPUT OVERVOLTAGE IOVP Dynamic OVP triggering current 35 40 45 μA Hys Hysteresis (3) 30 μA Static OVP threshold (1) 2.1 2.25 2.4 V GATE DRIVER VOH Dropout Voltage IGDsource = 20 mA 2 2.6 IGDsource = 200 mA 2.5 3 V VOL IGDsink = 200 mA 0.9 1.9 V tf Voltage Fall Time 30 70 ns tr Voltage Rise Time 40 80 ns VOclamp Output clamp voltage IGDsource = 5mA; Vcc = 20V 10 12 15 V UVLO saturation VCC = 0 to VCCon, Isink=10mA 1.1 V Table 5. Electrical Characteristics (continued) (Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit Vcs = K ⋅ VMULT ⋅ (VCOMP – 2.5) 5/16 L6562 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Vcc(V) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 ICC (mA) 0 5 10 15 20 Co = 1nF f = 70 kHz Tj = 25°C 25 Tj (°C) VCC-ON (V) VCC-OFF (V) -50 0 50 100 150 9 9.5 10 10.5 11 11.5 12 12.5 -50 0 50 100 150 0.02 0.05 0.1 0.2 0.5 1 2 5 Icc 10 [mA] Operating Quiescent Disabled or during OVP Before start-up Vcc = 12 V Co = 1 nF f = 70 kHz Tj (°C) Tj (°C) VccZ (V) -50 0 50 100 150 22 23 24 25 26 27 28 L6562 6/16 Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj VREF (V) -50 0 50 100 150 2.4 2.45 2.5 2.55 2.6 Vcc = 12 V Tj (°C) IOVP (μA) -50 0 50 100 150 39 39.5 40 40.5 41 Vcc = 12 V Tj (°C) Tj (°C) Vpin2 (V) -50 0 50 100 150 2 3 4 5 6 Upper clamp Lower clamp Vcc = 12 V Tj (°C) tD(H-L) (ns) -50 0 50 100 150 0 100 200 300 400 500 Vcc = 12 V VMULT (pin 3) (V) VCOMP (pin 2) (V) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 VCS (pin 4) 2.6 3.0 3.2 4.5 5.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 (V) 4.0 2.8 upper voltage clamp 3.5 Tj (°C) K -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1 Vcc = 12 V VCOMP =4 V VMULT =1V 7/16 L6562 Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Tj (°C) VCSx (V) -50 0 50 100 150 1 1.2 1.4 1.6 1.8 2 Vcc = 12 V VCOMP= Upper clamp Tj (°C) Tstart (μs) -50 0 50 100 150 100 110 120 130 140 150 Vcc = 12 V Tj (°C) VZCD (V) -50 0 50 100 150 0 1 2 3 4 5 6 7 Vcc = 12 V IZCD = ±2.5 mA Upper clamp Lower clamp Tj (°C) IZCDsrc (mA) -50 0 50 100 150 -8 -6 -4 -2 0 Vcc = 12 V VZCD= lower clamp Vpin7[V] 0 200 400 600 800 1,000 0 1 2 3 4 IGD[mA] Tj = 25 °C Vcc = 11 V SINK 0 100 200 300 400 500 600 700 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 Vpin7[V] IGD[mA] Tj = 25 °C Vcc = 11 V SOURCE Vcc - 2.0 Vcc - 2.5 Vcc - 3.0 Vcc - 3.5 Vcc - 4.0 L6562 8/16 Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj Tj (°C) Vpin7clamp (V) -50 0 50 100 150 10 11 12 13 14 15 Vcc = 20 V Tj (°C) -50 0 50 100 150 0.5 0.6 0.7 0.8 0.9 1 1.1 Vcc = 0 V Vpin7 (V) 4 Application Information 4.1 Overvoltage protection Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple components, the current through R1, IR1, equals that through R2, IR2. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then: . If the output voltage experiences an abrupt change ΔVo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why ΔVo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become: . The difference current ΔIR1=I'R1-IR2=I'R1-IR1=ΔVo/R1 will flow through the compensation network and enter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about 37 μA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the output. As the current exceeds 40 μA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is maintained until the current falls below approximately 10 μA, which re-enables the internal starter and allows switching to restart. The output ΔVo that is able to trigger the Dynamic OVP function is then: . An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ΔVo. Since ΔVo << Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo = 400 V, ΔVo = 40 V. Then: R1=40V/40μA=1MΩ; R2=1MΩ·2.5/(400-2.5)=6.289kΩ. The tolerance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value. IR2 2.5 R2 -------- IR1 Vo – 2.5 R1 = = = --------------------- I'R1 Vo – 2.5 + ΔVo R1 = --------------------------------------- ΔVo R1 40 10 –6 = ⋅ ⋅ 9/16 L6562 When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier output will saturate low; hence, when this is detected, the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its linear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low. When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply system. 4.2 THD optimizer circuit The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the highfrequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key waveforms of a standard TM PFC controller are compared to those of the L6562. Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to Imains Vdrain Imains Vdrain Input current Input current MOSFET's drain voltage MOSFET's drain voltage Rectified mains voltage Rectified mains voltage Input current Input current L6562 10/16 the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC preregulator - thus making the action of the optimizer circuit little effective. Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic NTC 2.5 Ω 8 3 BRIDGE STBR606 R1 1.5 MΩ C1 1 μF 400V R3 22 kΩ C29 22 μF 25V FUSE 5A/250V R4 180 kΩ D8 1N4150 D2 1N5248B R14 100 Ω C5 12 nF R6 68 kΩ T 5 6 L6562 7 2 1 R7 10 Ω MOS STP12NM50 7 °C/W heat sink 4 R11 750 kΩ C6 100 μF 450V Vo=400V Po=250W - Vac (85V to 265V) R9 0.33Ω 1W R13 9.53 kΩ + - C4 100 nF C2 10nF D1 STTH5L06 R50 10 kΩ C3 2.2 μF R2 1.5 MΩ R5 180 kΩ R10 0.33Ω 1W R12 750 kΩ C23 680 nF Boost Inductor Spec: EB0057-C (COILCRAFT) D3 1N5406 NTC 2.5 Ω 8 3 BRIDGE DF06M R1 750 kΩ C1 0.47 μF 400V R3 10 kΩ C29 22 μF 25V FUSE 4A/250V R4 180 kΩ D8 1N4150 D2 1N5248B R14 100 Ω C5 12 nF R6 68 kΩ T 5 6 L6562 7 2 1 R7 33 Ω MOS STP8NM50 4 R11 750 kΩ C6 47 μF 450V Vo=400V Po=80W - Vac (85V to 265V) R9 0.82Ω 0.6 W R13 9.53 kΩ + - C4 100 nF C2 10nF D1 STTH1L06 R50 12 kΩ C3 680 nF R2 750 kΩ R5 180 kΩ R10 0.82Ω 0.6 W R12 750 kΩ C23 330 nF Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, 3C85 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 105 turns 20x0.1 mm Secondary: 11 turns 0.1 mm 11/16 L6562 Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Vin (VAC) Pin (W) Vo (VDC) ΔVo(Vpk-pk) Po (W) η (%) PF THD (%) 85 86.4 394.79 12.8 80.16 92.8 0.998 3.6 110 84.6 394.86 12.8 80.20 94.8 0.996 4.2 135 83.8 394.86 12.8 80.20 95.7 0.991 4.9 175 83.2 394.87 15.5 80.20 96.4 0.981 6.5 220 82.9 394.87 15.7 80.20 96.7 0.956 7.8 265 82.7 394.87 15.9 80.20 97.0 0.915 9.2 Note: measurements done with the line filter shown in figure 23 Vin (VAC) Pin (W) Vo (VDC) ΔVo(Vpk-pk) Po (W) η (%) PF THD (%) 85 42.8 394.86 6.6 40.20 93.9 0.994 5.5 110 42.5 394.90 6.6 40.20 94.6 0.985 6.2 135 42.5 394.91 6.7 40.20 94.6 0.967 7.1 175 42.5 394.93 8.0 40.19 94.6 0.939 8.3 220 42.6 394.94 8.2 40.19 94.3 0.869 9.8 265 42.6 394.94 8.3 40.19 94.3 0.776 11.4 Note: measurements done with the line filter shown in figure 23 L6562 12/16 Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation Vin (VAC) Pin (W) Vo (VDC) ΔVo(Vpk-pk) Po (W) 85 0.4 396.77 0.45 0 110 0.3 396.82 0.55 0 135 0.3 396.83 0.60 0 175 (*) 0.4 396.90 1.00 0 220 (*) 0.4 396.95 1.40 0 265 (*) 0.5 396.98 1.65 0 (*) Vcc = 12V supplied externally to the AC source B82732 47 mH, 1.3A EPCOS B81133 470 nF, X2 EPCOS to EVAL6562N B81133 680 nF, X2 EPCOS 13/16 L6562 5 Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 27. DIP-8 Mechanical Data & Package Dimensions OUTLINE AND MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 0.125 0.150 Z 1.52 0.060 DIP-8 L6562 14/16 Figure 28. SO-8 Mechanical Data & Package Dimensions OUTLINE AND MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 0° (min.), 8° (max.) ddd 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). SO-8 0016023 C 15/16 L6562 6 Revision History Table 9. Revision History Date Revision Description of Changes January 2004 5 First Issue June 2004 6 Modified the Style-look in compliance with the “Corporate Technical Publications Design Guide”. Changed input of the power amplifier connected to Multiplier (Fig. 2). May 2005 7 Modified Table 2: Absolute Maximim Ratings. November 2005 8 Added in Section 5 the ECOPACK® certicate of conformity. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com SMAJ Transil™ Features ■ Peak pulse power: – 400 W (10/1000 μs) – 2.3 kW (8/20 μs) ■ Stand off voltage range: from 5 V to 188 V ■ Unidirectional and bidirectional types ■ Low leakage current: – 0.2 μA at 25 °C – 1 μA at 85 °C ■ Operating Tj max: 150 °C ■ High power capability at Tj max: – 270 W (10/1000 μs) ■ JEDEC registered package outline Complies with the following standards ■ IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) ■ IEC 61000-4-5 (see Table 3 for surge level) ■ MIL STD 883G, method 3015-7 Class 3B – 25 kV HBM (human body model) ■ Resin meets UL 94, V0 ■ MIL-STD-750, method 2026 solderability ■ EIA STD RS-481 and IEC 60286-3 packing ■ IPC 7531 footprint Description The SMAJ Transil series has been designed to protect sensitive equipment against electrostatic discharges according to IEC 61000-4-2, and MIL STD 883, method 3015, and electrical over stress according to IEC 61000-4-4 and 5. These devices are generally used against surges below 400 W (10/1000 μs). Planar technology makes these devices suitable for high-end equipment and SMPS where low leakage current and high junction temperature are required to provide reliability and stability over time. SMAJ are packaged in SMA (SMA footprint in accordance with IPC 7531 standard). TM: Transil is a trademark of STMicroelectronics K A Unidirectional Bidirectional SMA (JEDEC DO-214AC) www.st.com Characteristics SMAJ 2/10 Doc ID 5544 Rev 12 1 Characteristics Figure 1. Electrical characteristics - definitions Figure 2. Pulse definition for electrical characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit PPP Peak pulse power dissipation (1) Tj initial = Tamb 400 W Tstg Storage temperature range -65 to +150 °C Tj Operating junction temperature range -55 to +150 °C TL Maximum lead temperature for soldering during 10 s. 260 °C 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Table 2. Thermal resistances Symbol Parameter Value Unit Rth(j-l) Junction to leads 30 °C/W Rth(j-a) Junction to ambient on printed circuit on recommended pad layout 120 °C/W VCLVBR VRM IRM IR IPP V I IRM IR IPP VRMVBR VCL V CLVBR VRM IRM IR IPP V I IF VF Unidirectional Bidirectional Symbol Parameter V Stand-off voltage V Breakdown voltage V Clamping voltage I Leakage current @ V I Peak pulse current T Voltage temperature coefficient V Forward voltage drop R Dynamic resistance RM BR CL RM RM PP F D α Repetitive pulse current tr = rise time (μs) tp = pulse duration time (μs) tr tp SMAJ Characteristics Doc ID 5544 Rev 12 3/10 Table 3. Electrical characteristics - parameter values (Tamb = 25 °C) Order code IRM max@VRM VBR @IR (1) VCL @IPP 10/1000 μs RD (2) 10/1000 μs VCL @IPP 8/20 μs RD (2) 8/20 μs αT (3) 25 °C 85 °C min typ max max max μA V V mA V A(4) Ω V A(4) Ω 10-4/° C SMAJ5.0A/CA 20 50 5 6.4 6.74 10 9.2 43.5 0.049 13.4 174 0.036 5.7 SMAJ6.0A/CA 20 50 6 6.7 7.05 10 10.3 38.8 0.075 13.7 170 0.037 5.9 SMAJ6.5A/CA 20 50 6.5 7.2 7.58 10 11.2 35.7 0.091 14.5 160 0.041 6.1 SMAJ8.5A/CA 20 50 8.5 9.4 9.9 1 14.4 27.7 0.145 19.5 124 0.073 7.3 SMAJ10A/CA 0.2 1 10 11.1 11.7 1 17 23.5 0.201 21.7 106 0.089 7.8 SMAJ12A/CA 0.2 1 12 13.3 14 1 19.9 20.1 0.259 25.3 91 0.116 8.3 SMAJ13A/CA 0.2 1 13 14.4 15.2 1 21.5 18.6 0.298 27.2 85 0.132 8.4 SMAJ15A/CA 0.2 1 15 16.7 17.6 1 24.4 16.4 0.361 32.5 71 0.197 8.8 SMAJ18A/CA 0.2 1 18 20 21.1 1 29.2 13.7 0.514 39.3 59 0.291 9.2 SMAJ20A/CA 0.2 1 20 22.2 23.4 1 32.4 12.3 0.637 42.8 54 0.338 9.4 SMAJ22A/CA 0.2 1 22 24.4 25.7 1 35.5 11.2 0.760 48.3 48 0.444 9.6 SMAJ24A/CA 0.2 1 24 26.7 28.1 1 38.9 10.3 0.912 50 46 0.446 9.6 SMAJ26A/CA 0.2 1 26 28.9 30.4 1 42.1 9.5 1.07 53.5 43 0.502 9.7 SMAJ28A/CA 0.2 1 28 31.1 32.7 1 45.4 8.8 1.26 59 39 0.632 9.8 SMAJ30A/CA 0.2 1 30 33.3 35.1 1 48.4 8.3 1.39 64.3 36 0.762 9.9 SMAJ33A/CA 0.2 1 33 36.7 38.6 1 53.3 7.5 1.70 69.7 33 0.884 10 SMAJ40A/CA 0.2 1 40 44.4 46.7 1 64.5 6.2 2.49 84 27 1.30 10.1 SMAJ43A/CA 0.2 1 43 47.8 50.3 1 69.4 5.7 2.91 91 25 1.53 10.2 SMAJ48A/CA 0.2 1 48 53.3 56.1 1 77.4 5.2 3.56 100 23 1.79 10.3 SMAJ58A/CA 0.2 1 58 64.4 67.8 1 93.6 4.3 5.21 121 19 2.62 10.4 SMAJ70A/CA 0.2 1 70 77.8 81.9 1 113 3.5 7.72 146 16 3.75 10.5 SMAJ85A/CA 0.2 1 85 94 99 1 137 2.9 11.4 178 13 5.70 10.6 SMAJ100A/CA 0.2 1 100 111 117 1 162 2.5 15.7 212 11 8.10 10.7 SMAJ130A/CA 0.2 1 130 144 152 1 209 1.9 26.0 265 9 11.7 10.8 SMAJ154A/CA 0.2 1 154 171 180 1 246 1.6 35.6 317 7 18.3 10.8 SMAJ170A/CA 0.2 1 170 189 199 1 275 1.4 47.2 353 6.5 22.2 10.8 SMAJ188A/CA 0.2 1 188 209 220 1 328 1.4 69.3 388 6 26.2 10.8 1. Pulse test : tp < 50 ms 2. To calculate maximum clamping voltage at other surge level,use the following formula: VCLmax = VCL - RD x (IPP - IPPappli) where IPPappli is the surge current in the application 3. To calculate VBR or VCL versus junction temperature, use the following formulas: VBR @ TJ = VBR @ 25°C x (1 + αT x (TJ – 25)), VCL @ TJ = VCL @ 25°C x (1 + αT x (TJ – 25)) 4. Surge capability given for both directions for unidirectional and bidirectional types. Characteristics SMAJ 4/10 Doc ID 5544 Rev 12 Figure 5. Clamping voltage versus peak pulse current (exponential waveform, maximum values) Figure 3. Peak pulse power dissipation versus initial junction temperature Figure 4. Peak pulse power versus exponential pulse duration (Tj initial = 25° C) 0 100 200 300 400 500 0 25 50 75 100 125 150 175 Ppp (W) Tj(°C) 0.1 1.0 10.0 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 PPP(kW) Tj initial = 25 °C tP(ms) 0.1 1.0 10.0 100.0 1000.0 1 10 100 1000 10/1000 μs Tj initial=25 °C 8/20 μs 10 ms SMAJ5.0A SMAJ12A SMAJ24A SMAJ40A SMAJ85A SMAJ188A IPP(A) VCL(V) SMAJ Characteristics Doc ID 5544 Rev 12 5/10 Figure 6. Junction capacitance versus reverse applied voltage for unidirectional types (typical values) Figure 7. Junction capacitance versus reverse applied voltage for bidirectional types (typical values) 10 100 1000 10000 1 10 100 1000 C( pF) F=1 MHz VOSC=30 mVRMS Tj=25 °C SMAJ5.0A SMAJ12A SMAJ24A SMAJ40A SMAJ85A SMAJ188A VR(V) 10 100 1000 10000 1 10 100 1000 C(pF) F=1 MHz VOSC=30 mVRMS Tj=25 °C SMAJ5.0CA SMAJ12CA SMAJ24CA SMAJ40CA SMAJ85CA V SMAJ188CA R(V) Figure 8. Peak forward voltage drop versus peak forward current (typical values) Figure 9. Relative variation of thermal impedance, junction to ambient, versus pulse duration Figure 10. Thermal resistance, junction to ambient, versus copper surface under each lead Figure 11. Leakage current versus junction temperature (typical values) IFM(A) 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Tj =25 °C Tj =125 °C VFM(V) 0.01 0.10 1.00 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 Zth(j-a) /Rth(j-a) Recommended pad layout PCB FR4, copper thickness = 35 μm tP(s) R (°C/W) th(j-a) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SCU(cm²) PCB FR4, copper thickness = 35 μm IR(nA) 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 25 50 75 100 125 150 VR=VRM VRM ≥ 10 V VR=VRM VRM< 10 V Tj(°C) Ordering information scheme SMAJ 6/10 Doc ID 5544 Rev 12 2 Ordering information scheme Figure 12. Ordering information scheme SM A J 85 CA - TR Surface mount Peak pulse power A = 400 WTransil in SMA Stand off voltage 85 = 85 V Type A = Unidirectinal CA = Bidirectional Delivery mode TR = Tape and reel SMAJ Package information Doc ID 5544 Rev 12 7/10 3 Package information ● Case: JEDEC DO-214AC molded plastic over planar junction ● Terminals: solder plated, solderable per MIL-STD-750, Method 2026 ● Polarity: for unidirectional types the band indicates cathode. ● Flammability: epoxy is rated UL94V-0 ● RoHS package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 4. SMA dimensions Ref. Dimensions Millimeters Inches Min. Max. Min. Max. A1 1.90 2.45 0.075 0.094 A2 0.05 0.20 0.002 0.008 b 1.25 1.65 0.049 0.065 c 0.15 0.40 0.006 0.016 D 2.25 2.90 0.089 0.114 E 4.80 5.35 0.189 0.211 E1 3.95 4.60 0.156 0.181 L 0.75 1.50 0.030 0.059 Figure 13. Footprint dimensions in mm (inches) Figure 14. Marking layout(1) 1. Marking layout can vary according to assembly location. E C L E1 D A1 A2 b 2.63 (0.103) 5.43 (0.214) 1.4 1.64 (0.064) 1.4 (0.055) (0.055) y w w e z x x x e: ECOPACK compliance XXX: Marking Z: Manufacturing location Y: Year WW: week Cathode bar ( unidirectional devices only ) Package information SMAJ 8/10 Doc ID 5544 Rev 12 Table 5. Marking Order code Marking Order code Marking SMAJ5.0A-TR AE SMAJ5.0CA-TR AA SMAJ6.0A-TR DUB SMAJ6.0CA-TR DBB SMAJ6.5A-TR DUC SMAJ6.5CA-TR DBC SMAJ8.5A-TR DUH SMAJ8.5CA-TR DBH SMAJ10A-TR AX SMAJ10CA-TR AC SMAJ12A-TR DUK SMAJ12CA-TR DBK SMAJ13A-TR BG SMAJ13CA-TR BH SMAJ15A-TR BM SMAJ15CA-TR AJ SMAJ18A-TR DUQ SMAJ18CA-TR DBQ SMAJ20A-TR DUR SMAJ20CA-TR DBR SMAJ22A-TR DUS SMAJ22CA-TR DBS SMAJ24A-TR DUT SMAJ24CA-TR DBT SMAJ26A-TR DUU SMAJ26CA-TR DBU SMAJ28A-TR CG SMAJ28CA-TR CH SMAJ30A-TR CK SMAJ30CA-TR CL SMAJ33A-TR CM SMAJ33CA-TR CN SMAJ40A-TR DUZ SMAJ40CA-TR DBZ SMAJ43A-TR EUA SMAJ43CA-TR EBA SMAJ48A-TR CX SMAJ48CA-TR CY SMAJ58A-TR EUF SMAJ58CA-TR EBF SMAJ70A-TR EUI SMAJ70CA-TR EBI SMAJ85A-TR EUL SMAJ85CA-TR EBL SMAJ100A-TR EUN SMAJ100CA-TR EBN SMAJ130A-TR EUQ SMAJ130CA-TR EBQ SMAJ154A-TR EUT SMAJ154CA-TR EBT SMAJ170A-TR SR SMAJ170CA-TR SS SMAJ188A-TR EUV SMAJ188CA-TR EBV SMAJ Ordering information Doc ID 5544 Rev 12 9/10 4 Ordering information 5 Revision history Table 6. Ordering information Order code Marking Package Weight Base qty Delivery mode SMAJxxxA/CA-TR(1) 1. Where xxx is nominal value of VBR and A or CA indicates unidirectional or bidirectional version. See Table 3 for list of available devices and their order codes See Table 5 on page 8 SMA 0.071 g 5000 Tape and reel Table 7. Document revision history Date Revision Changes September-1998 5B Previous update. 02-Aug-2004 6 SMA package dimensions update. Reference A1 max. changed from 2.70mm (0.106) to 2.03mm (0.080). 10-Dec-2004 7 Template layout update. No content change. 10-Feb-2006 8 Added unidirectional marking on cover page and Figure 14. Changed Figure 13. Foot print. 14-May-2009 9 Updated ECOPACK statement. Reformatted to current standards. 17-Sep-2009 10 Document updated for low leakage current. 05-Nov-2009 11 Corrected typographical error in Package information. 09-Jul-2010 12 Changed timescale in Figure 9. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 1/15 TDA7296 February 2005 1 FEATURES ■ MULTIPOWER BCD TECHNOLOGY ■ VERY HIGH OPERATING VOLTAGE RANGE (±35V) ■ DMOS POWER STAGE ■ HIGH OUTPUT POWER (UP TO 60W MUSIC POWER) ■ MUTING/STAND-BY FUNCTIONS ■ NO SWITCH ON/OFF NOISE ■ NO BOUCHEROT CELLS ■ VERY LOW DISTORTION ■ VERY LOW NOISE ■ SHORT CIRCUIT PROTECTION ■ THERMAL SHUTDOWN 2 DESCRIPTION The TDA7296 is a monolithic integrated circuit in Multiwatt15 package, intended for use as audio class AB amplifier in Hi-Fi field applications (Home Stereo, self powered loudspeakers, Topclass TV). Thanks to the wide voltage range and to the high out current capability it is able to supply the highest power into both 4Ω and 8Ω loads even in presence of poor supply regulation, with high Supply Voltage Rejection. The built in muting function with turn on delay simplifies the remote operation avoiding switching onoff noises. 70V - 60W DMOS AUDIO AMPLIFIER WITH MUTE/ST-BY Figure 2. Typical Application and Test Circuit IN- 2 R2 680Ω C2 22μF C1 470nF IN+ R1 22K R6 2.7Ω C10 100nF 3 R3 22K - + MUTE STBY 4 VM VSTBY 10 9 IN+MUTE MUTE STBY R4 22K THERMAL SHUTDOWN S/C PROTECTION R5 10K C3 10μF C4 10μF 1 STBY-GND C5 22μF 7 13 14 6 8 15 -Vs -PWVs BOOTSTRAP OUT +Vs +PWVs C9 100nF C8 1000μF -Vs D93AU011 C7 100nF +Vs C6 1000μF Note: The Boucherot cell R6, C10, normally not necessary for a stable operation it could be needed in presence of particular load impedances at VS <±25V. Rev. 10 Figure 1. Package Table 1. Order Codes Part Number Package TDA7296 Multiwatt15V TDA7296HS Multiwatt15H (Short Leads) Multiwatt15V Multiwatt15H (Short Leads) TDA7296 2/15 Figure 3. Pin Connection Table 2. Absolute Maximum Ratings Table 3. Thermal Data Figure 4. Block Diagram Symbol Parameter Value Unit VS Supply Voltage (No Signal) ±35 V IO Output Peak Current 5 A Ptot Power Dissipation Tcase = 70°C 50 W Top Operating Ambient Temperature Range 0 to 70 °C Tstg, Tj Storage and Junction Temperature 150 °C Symbol Parameter Typ. Max Unit Rth j-case Thermal Resistance Junction-case 1 1.5 °C/W 3/15 TDA7296 Table 4. Electrical Characteristcs (Refer to the Test Circuit VS = ±24V, RL = 8Ω, GV = 30dB; Rg = 50Ω; Tamb = 25°C, f = 1 kHz; unless otherwise specified). Note (*): MUSIC POWER is the maximal power which the amplifier is capable of producing across the rated load resistance (regardless of non linearity) 1 sec after the application of a sinusoidal input signal of frequency 1KHz. Note (**): Tested with optimized Application Board (see fig.5) Symbol Parameter Test Condition Min. Typ. Max. Unit VS Supply Range ±10 ±35 V Iq Quiescent Current 20 30 65 mA Ib Input Bias Current 500 nA VOS Input Offset Voltage -10 10 mV IOS Input Offset Current -100 100 nA PO RMS Continuous Output Power d = 05% VS = ± 24V, RL = 8Ω; VS = ± 21V, RL = 6Ω; VS = ± 18V, RL = 4Ω; 27 27 27 30 30 30 WWW Music Power (RMS) Δt = 1s (*) d = 10% VS = ± 29V, RL = 8Ω; VS = ± 24V, RL = 6Ω; VS = ± 22V, RL = 4Ω; 60 60 60 WWW d Total Harmonic Distortion (**) PO = 5W; f = 1kHz PO = 0.1 to 20W; f = 20Hz to 20kHz 0.005 0.1 % VS = ± 18V, RL = 4Ω; PO = 5W; f = 1kHz PO = 0.1 to 20W; f = 20Hz to 20kHz 0.01 0.1 %% SR Slew Rate 7 10 V/μs GV Open Loop Voltage Gain 80 dB GV Closed Loop Voltage Gain (1) 24 30 40 dB eN Total Input Noise A = curve 1 μV f = 20Hz to 20kHz 2 5 μV fL ,fH frequency response (-3dB) PO =1W 20Hz to 20kHz Ri Input Resistance 100 kΩ SVR Supply Voltage Rejection f = 100Hz; Vripple = 0.5Vrms 60 75 dB TS Thermal Shutdown 145 °C STAND-BY FUNCTION (Ref: -Vs or GND) VST on Stand-by on Threshold 1.5 V VST off Stand-by off Threshold 3.5 V ATTst-by Stand-by Attenuation 70 90 dB Iq st-by Quiescent Current @ Stand-by 1 3 mA MUTE FUNCTION (Ref: -Vs ro GND) VMon Mute on Threshold 1.5 V VMoff Mute off Threshold 3.5 V ATTmute Mute AttenuatIon 60 80 dB TDA7296 4/15 Figure 5. P.C.B. and Components Layout of the Circuit of figure 2. Note: The Stand-by and Mute functions can be referred either to GND or -VS. On the P.C.B. is possible to set both the configuration through the jumper J1. 5/15 TDA7296 3 APPLICATION SUGGESTIONS (see Test and Application Circuits of the Fig. 2) The recommended values of the external components are those shown on the application circuit of Figure 2. Different values can be used; the following table can help the designer. (*) R1 = R3 for pop optimization (**) Closed Loop Gain has to be ≥ 24dB COMPONENTS SUGGESTED VALUE PURPOSE LARGER THAN SUGGESTED SMALLER THAN SUGGESTED R1 (*) 22k Input Resistance Increase Input Impedance Decrease Input Impedance R2 680Ω Closed Loop Gain Set to 30db (**) Decrease of Gain Increase of Gain R3 (*) 22k Increase of Gain Decrease of Gain R4 22k St-by Time Constant Larger St-by ON/OFF Time Smaller St-by ON/OFF Time; Pop Noise R5 10k Mute Time Constant Larger Mute ON/OFF Time Smaller Mute ON/OFF Time C1 0.47μF Input DC Decoupling Higher Low Frequency Cutoff C2 22μF Feedback DC Decoupling Higher Low Frequency Cutoff C3 10μF Mute Time Constant Larger Mute ON/OFF Time Smaller Mute ON/OFF Time C4 10μF St-by Time Constant Larger St-by ON/OFF Time Smaller St-by ON/OFF Time; Pop Noise C5 22μF Bootstrapping Signal Degradation at Low Frequency C6, C8 1000μF Supply Voltage Bypass Danger of Oscillation C7, C9 0.1μF Supply Voltage Bypass Danger of Oscillation TDA7296 6/15 4 TYPICAL CHARACTERISTICS (Application Circuit of fig 2 unless otherwise specified) Figure 6. : Output Power vs. Supply Voltage. Figure 7. Distortion vs. Output Power Figure 8. Output Power vs. Supply Voltage Figure 9. Distortion vs. Output Power Figure 10. Distortion vs. Frequency Figure 11. Distortion vs. Frequency 7/15 TDA7296 Figure 12. Quiescent Current vs. Supply Voltage Figure 13. Supply Voltage Rejection vs. Frequency Figure 14. Mute Attenuation vs. Vpin10 Figure 15. St-by Attenuation vs. Vpin9 Figure 16. Power Dissipation vs. Output Power Figure 17. Power Dissipation vs. Output Power TDA7296 8/15 5 INTRODUCTION In consumer electronics, an increasing demand has arisen for very high power monolithic audio amplifiers able to match, with a low cost the performance obtained from the best discrete designs. The task of realizing this linear integrated circuit in conventional bipolar technology is made extremely difficult by the occurence of 2nd breakdown phenomenon. It limits the safe operating area (SOA) of the power devices, and as a consequence, the maximum attainable output power, especially in presence of highly reactive loads. Moreover, full exploitation of the SOA translates into a substantial increase in circuit and layout complexity due to the need for sophisticated protection circuits. To overcome these substantial drawbacks, the use of power MOS devices, which are immune from secondary breakdown is highly desirable. The device described has therefore been developed in a mixed bipolar- MOS high voltage technology called BCD 80. 5.1 Output Stage The main design task one is confronted with while developing an integrated circuit as a power operational amplifier, independently of the technology used, is that of realising the output stage. The solution shown as a principle schematic by Fig 18 represents the DMOS unity-gain output buffer of the TDA7296. This large-signal, high-power buffer must be capable of handling extremely high current and voltage levels while maintaining acceptably low harmonic distortion and good behaviour over frequency response; moreover, an accurate control of quiescent current is required. A local linearizing feedback, provided by differential amplifier A, is used to fullfil the above requirements, allowing a simple and effective quiescent current setting. Proper biasing of the power output transistors alone is however not enough to guarantee the absence of crossover distortion. While a linearization of the DC transfer characteristic of the stage is obtained, the dynamic behaviour of the system must be taken into account. A significant aid in keeping the distortion contributed by the final stage as low as possible is provided by the compensation scheme, which exploits the direct connection of the Miller capacitor at the amplifier’s output to introduce a local AC feedback path enclosing the output stage itself. 5.2 Protections In designing a power IC, particular attention must be reserved to the circuits devoted to protection of the device from short circuit or overload conditions. Due to the absence of the 2nd breakdown phenomenon, the SOA of the power DMOS transistors is delimited only by a maximum dissipation curve dependent on the duration of the applied stimulus. In order to fully exploit the capabilities of the power transistors, the protection scheme implemented in this device combines a conventional SOA protection circuit with a novel local temperature sensing technique which " dynamically" controls the maximum dissipation. Figure 18. Principle Schematic of a DMOS Unity-gain Buffer. 9/15 TDA7296 Figure 19. Turn ON/OFF Suggested Sequence In addition to the overload protection described above, the device features a thermal shutdown circuit which initially puts the device into a muting state (@ Tj = 145°C) and then into stand-by (@ Tj = 150°C). Full protection against electrostatic discharges on every pin is included. 5.3 Other Features The device is provided with both stand-by and mute functions, independently driven by two CMOS logic compatible input pins. The circuits dedicated to the switching on and off of the amplifier have been carefully optimized to avoid any kind of uncontrolled audible transient at the output. The sequence that we recommend during the ON/OFF transients is shown by Figure 19. The application of figure 20 shows the possibility of using only one command for both st-by and mute functions. On both the pins, the maximum applicable range corresponds to the operating supply voltage. PLAY OFF ST-BY MUTE MUTE ST-BY OFF D93AU013 5V 5V +Vs (V) +35 -35 VMUTE PIN #10 (V) VST-BY PIN #9 (V) -Vs VIN (mV) IP (mA) VOUT (V) TDA7296 10/15 Figure 20. Single Signal ST-BY/MUTE Control Circuit 6 BRIDGE APPLICATION Another application suggestion is the BRIDGE configuration, where two TDA7296 are used, as shown by the schematic diagram. In this application, the value of the load must not be lower than 8 Ohm for dissipation and current capability reasons. A suitable field of application includes HI-FI/TV subwoofers realizations. The main advantages offered by this solution are: – High power performances with limited supply voltage level. – Considerably high output power even with high load values (i.e. 16 Ohm). The characteristics shown by figures 23 and 24, measured with loads respectively 8 Ohm and 16 Ohm. With Rl= 8 Ohm, Vs = ±18V the maximum output power obtainable is 60W, while with Rl=16 Ohm, Vs = ±24V the maximum Pout is 60W. Figure 21. Bridge Application Circuit 1N4148 10K 30K 20K 10μF 10μF MUTE STBY D93AU014 MUTE/ ST-BY 0.56μF 22K 0.22μF 2200μF + - 22μF 22K 680 22K 3 1 4 7 13 +Vs Vi 15 8 2 14 6 10 9 + - 3 0.56μF 22K 1 4 2 14 6 22μF 22K 680 10 9 22μF 15 8 -Vs 2200μF 0.22μF 22μF 20K 10K 30K 1N4148 ST-BY/MUTE 7 13 D93AU015A 11/15 TDA7296 Figure 22. Frequency Response of the Bridge Application Figure 23. Distortion vs. Output Power Figure 24. Distortion vs. Output Power TDA7296 12/15 Figure 25. Multiwatt15V Mechanical Data & Package Dimensions OUTLINE AND MECHANICAL DATA 0016036 J DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A5 0.197 B 2.65 0.104 C 1.6 0.063 D 1 0.039 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 G 1.02 1.27 1.52 0.040 0.050 0.060 G1 17.53 17.78 18.03 0.690 0.700 0.710 H1 19.6 0.772 H2 20.2 0.795 L 21.9 22.2 22.5 0.862 0.874 0.886 L1 21.7 22.1 22.5 0.854 0.87 0.886 L2 17.65 18.1 0.695 0.713 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 L7 2.65 2.9 0.104 0.114 M 4.25 4.55 4.85 0.167 0.179 0.191 M1 4.73 5.08 5.43 0.186 0.200 0.214 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 Multiwatt15 (Vertical) 13/15 TDA7296 Figure 26. Multiwatt15 Horizontal (Short leads) Mechanical Data & Package Dimensions OUTLINE AND MECHANICAL DATA A C B E L5 L7 L2 L1 F G1 G H2 L4 L3 S1 S H1 Diam 1 MW15HME V V V V V H2 N R1 P R R 0067558 E DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 0.063 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 G 1.02 1.27 1.52 0.040 0.050 0.060 G1 17.53 17.78 18.03 0.690 0.700 0.709 H1 19.6 20.2 0.772 0.795 H2 19.6 20.2 0.772 0.795 L1 17.80 18.00 18.20 0.701 0.709 0.717 L2 2.54 0.100 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 L5 2.70 3.00 3.30 0.106 0.118 0.130 L7 2.65 2.9 0.104 0.114 R 1.5 0.059 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 Multiwatt15 H (Short leads) TDA7296 14/15 Table 5. Revision History Date Revision Description of Changes January 2004 8 First Issue in EDOCS DMS September 2004 9 Added Package Multiwatt15 Horizontal (Short leads) February 2005 10 Corrected mistyping error in Table 2. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 15/15 TDA7296 TL084, TL084A, TL084B General purpose JFET quad operational amplifiers Datasheet — production data Features ■ Wide common-mode (up to VCC +) and differential voltage range ■ Low input bias and offset current ■ Output short-circuit protection ■ High input impedance JFET input stage ■ Internal frequency compensation ■ Latch up free operation ■ High slew rate: 16 V/μs (typical) Description The TL084, TL084A, and TL084B are high-speed, JFET input, quad operational amplifiers incorporating well matched, high voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. D TSSOP14(Thin shrink small outline package)NDIP14(Plastic package)DSO-14(Plastic micropackage)Pin connections(Top view)Inverting Input 2Non-inverting Input 2Non-inverting Input 1CCV -CCV1234856791011121314+Output 3Output 4Non-inverting Input 4Inverting Input 4Non-inverting Input 3Inverting Input 3-+-+-+-+Output 1Inverting Input 1Output 2 www.st.com Contents TL084, TL084A, TL084B 2/19 Doc ID 2301 Rev 5 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Parameter measurement information . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 DIP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TL084, TL084A, TL084B Schematic diagram Doc ID 2301 Rev 5 3/19 1 Schematic diagram Figure 1. Circuit schematics (for each amplifier) Output Non- inver ting input I nverting input VC C VC C 2 0 0 1 0 0Ω Ω 1 0 0Ω 1.3k 30k 1.3k 35k 35k 1 0 0Ω 8.2k Absolute maximum ratings and operating conditions TL084, TL084A, TL084B 4/19 Doc ID 2301 Rev 5 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage(1) 1. All voltage values, except differential voltage, are with respect to the zero reference level (ground) of the supply voltages where the zero reference level is the midpoint between VCC + and VCC -. ±18 Vin Input voltage(2) V 2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less. ±15 Vid Differential input voltage(3) 3. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. ±30 Rthja Thermal resistance junction to ambient(4)(5) DIP14 TSSOP14 SO-14 4. Short-circuits can cause excessive heating and destructive dissipation. 5. Rth are typical values. 80 100 105 °C/W Rthjc Thermal resistance junction to case(4)(5) DIP14 TSSOP14 SO-14 33 32 31 Ptot Power dissipation 680 mW Output short-circuit duration(6) 6. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. Infinite Toper Operating free-air temperature range: for TL084I/TL084AI/TL084BI -40 to +105 Operating free-air temperature range: °C for TL084C/TL084AC/TL084BC 0 to +70 Tstg Storage temperature range -65 to +150 ESD HBM: human body model(7) 7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 1000 MM: machine model(8) V 8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating. 150 CDM: charged device model(9) 9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to the ground. 1500 TL084, TL084A, TL084B Absolute maximum ratings and operating conditions Doc ID 2301 Rev 5 5/19 Table 2. Operating conditions Symbol Parameter TL084I/AI/BI TL084C/AC/BC Unit VCC Supply voltage range 6 to 36 V Toper Operating free-air temperature range -40 to +105 0 to +70 °C Electrical characteristics TL084, TL084A, TL084B 6/19 Doc ID 2301 Rev 5 3 Electrical characteristics Table 3. VCC = ±15 V, Tamb = +25 °C (unless otherwise specified) Symbol Parameter TL084I/AI/AC/BI/BC TL084C Unit Min. Typ. Max. Min. Typ. Max. Vio Input offset voltage (Rs = 50 Ω) Tamb = +25 °C TL084 Tamb = +25 °C TL084A Tamb = +25 °C TL084B Tmin ≤ Tamb ≤ Tmax TL084 Tmin ≤ Tamb ≤ Tmax TL084A Tmin ≤ Tamb ≤ Tmax TL084B 331 10 63 13 75 3 10 13 mV ΔVio/ΔT Input offset voltage drift 10 10 μV/°C Iio Input offset current Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 5 100 4 5 100 4 pA nA Iib Input bias current(1) Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 20 200 20 30 200 20 pA nA Avd Large signal voltage gain (RL = 2 kΩ, Vo = ±10 V) Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 50 25 200 25 15 200 V/mV SVR Supply voltage rejection ratio (RS = 50 Ω) Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 80 80 86 70 70 86 dB ICC Supply current, no load Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 1.4 2.5 2.5 1.4 2.5 2.5 mA Vicm Input common mode voltage range ±11 +15 -12 ±11 +15 -12 V CMR Common mode rejection ratio (RS = 50 Ω) Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 80 80 86 70 70 86 dB Ios Output short-circuit current Tamb = +25 °C Tmin ≤ Tamb ≤ Tmax 10 10 40 60 60 10 10 40 60 60 mA ±Vopp Output voltage swing Tamb = +25 °C RL = 2 kΩ RL = 10 kΩ Tmin ≤ Tamb ≤ Tmax RL = 2 kΩ RL = 10 kΩ 10 12 10 12 12 13.5 10 12 10 12 12 13.5 V SR Slew rate Vin = 10 V, RL = 2 kΩ, CL = 100 pF, unity gain 8 16 8 16 V/μs TL084, TL084A, TL084B Electrical characteristics Doc ID 2301 Rev 5 7/19 tr Rise time Vin = 20 mV, RL = 2 kΩ, CL = 100 pF, unity gain 0.1 0.1 μs Kov Overshoot Vin = 20 mV, RL = 2 kΩ, CL = 100 pF, unity gain 10 10 % GBP Gain bandwidth product Vin = 10 mV, RL = 2 kΩ, CL = 100 pF, F= 100 kHz 2.5 4 2.5 4 MHz Ri Input resistance 1012 1012 Ω THD Total harmonic distortion F= 1 kHz, RL = 2 kΩ,CL = 100 pF, Av = 20 dB, Vo = 2 Vpp) 0.01 0.01 % en Equivalent input noise voltage RS = 100 Ω, F= 1 kHz 15 15 ∅m Phase margin 45 45 degree s Vo1/Vo2 Channel separation Av = 100 120 120 dB 1. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature. Table 3. VCC = ±15 V, Tamb = +25 °C (unless otherwise specified) (continued) Symbol Parameter TL084I/AI/AC/BI/BC TL084C Unit Min. Typ. Max. Min. Typ. Max. nV Hz ----------- Electrical characteristics TL084, TL084A, TL084B 8/19 Doc ID 2301 Rev 5 Figure 2. Maximum peak-to-peak output voltage vs. frequency (RL = 2 kΩ) Figure 3. Maximum peak-to-peak output voltage vs. frequency (RL = 10 kΩ) Figure 4. Maximum peak-to-peak output voltage vs. frequency and temp. Figure 5. Maximum peak-to-peak output voltage vs. free air temp. Figure 6. Maximum peak-to-peak output voltage vs. load resistance Figure 7. Maximum peak-to-peak output voltage vs. supply voltage 30 25 20 15 10 5 0 2 4 6 8 10 12 14 16 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE (V) R L = 10 kΩ Tamb = +25°C SUPPLY VOLTAGE ( V ) TL084, TL084A, TL084B Electrical characteristics Doc ID 2301 Rev 5 9/19 Figure 8. Input bias current vs. free air temp. Figure 9. Large signal differential voltage amplification vs. free air temp. 100 10 1 0.1 0.01 INPUT BIAS CUR R ENT (nA) -50 -25 0 25 50 75 100 125 TEMPERATURE (°C ) V C C = 15V 1000 400 200 100 20 40 10 4 2 1 DIFFERENTIAL VOLTAGE AMPLIFICATION (V/mV) -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) R L = 2k Ω VO = 10V VCC = 15V Figure 10. Large signal differential voltage amplification and phase shift vs. frequency Figure 11. Total power dissipation vs. free air temp. (V/mV) 250 225 200 175 150 125 100 75 50 25 0 TOTAL POWE R DIS S IPATION (mW) -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C ) VC C = 15V No signal No load Figure 12. Supply current per amplifier vs. free air temp. Figure 13. Supply current per amplifier vs. supply voltage 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 SUPPLY CUR R ENT (mA) -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C ) VC C = 15V No signal No load 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 SUPPLY CURRENT (mA) 2 4 6 8 10 12 14 16 No signal No load Tamb = +25°C SUPPLY VOLTAGE ( V ) Electrical characteristics TL084, TL084A, TL084B 10/19 Doc ID 2301 Rev 5 Figure 14. Common mode rejection ratio vs. free air temp. Figure 15. Voltage follower large signal pulse response 89 88 87 86 85 84 -50 -25 0 25 50 75 100 125 COMMON MODE MODE R E JE CTION RATIO (dB) TEMPERATURE (°C ) 83 -75 R L = 1 0 kΩ V = 15V C C Figure 16. Output voltage vs. elapsed time Figure 17. Equivalent input noise voltage vs. frequency Figure 18. Total harmonic distortion vs. frequency t r 28 24 20 16 12 8 4 0 -4 OUTPUT VOLTAGE (mV) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 TIME ( μs ) 10% 90% OVERSHOOT R L = 2k Ω Tamb = +25°C V C C = 15V 70 60 50 40 30 20 10 0 EQUIVALENT INPUT NOIS E VOLTAGE (nV/VHz) 10 40 100 400 1k 4k 10k 40k 100k FREQUENCY (Hz) A V = 10 R S = 100 Ω T amb = +25°C VC C = 15V 1 0.4 0.1 0.04 0.01 0.004 0.001 TOTAL HARMONIC DISTOR TION (%) 100 400 1k 4k 10k 40k 100k FREQUENCY (Hz) A V = 1 T amb = +25°C V C C = 15V V O (rms) = 6V A V = 1 T amb = +25°C V O (rms) = 6V V C C = 15V TL084, TL084A, TL084B Parameter measurement information Doc ID 2301 Rev 5 11/19 4 Parameter measurement information Figure 19. Voltage follower Figure 20. Gain-of-10 inverting amplifier eI - TL084 R L 1/4 CL= 100pF 1k Ω 10k Ω eo Typical applications TL084, TL084A, TL084B 12/19 Doc ID 2301 Rev 5 5 Typical applications Figure 21. Audio distribution amplifier Figure 22. Positive feeback bandpass filter - T L084 1 /4 - - - T L084 1 /4 TL084 1/4 T L084 1 /4 1M Ω 1μF Output A Output B Output C Input 100k Ω 100k Ω 100k Ω 100k Ω 1OO μF V C C+ fO = 1 00 kH z - T L 0 8 4 - 2 2 0pF 1/4 43k Ω Input 1 .5 k Ω 43k Ω 22 0pF 43 k Ω 16k Ω T L 08 4 1/4 30k Ω Output A - T L 08 4 1/4 1 .5 k Ω 22 0pF 43k Ω 220 pF 43 k Ω - T L 08 4 1/4 43k Ω 16k Ω 30k Ω Output B Ground TL084, TL084A, TL084B Typical applications Doc ID 2301 Rev 5 13/19 Figure 23. Output A Figure 24. Output B Second order bandpass filter fo = 100 kHz; Q = 30; Gain = 4 Cascaded bandpass filter fo = 100 kHz; Q = 69; Gain = 16 Package information TL084, TL084A, TL084B 14/19 Doc ID 2301 Rev 5 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 DIP14 package information Figure 25. DIP14 package mechanical drawing Table 4. DIP14 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. a1 0.51 0.020 B 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 2.54 0.050 0.100 TL084, TL084A, TL084B Package information Doc ID 2301 Rev 5 15/19 6.2 TSSOP14 package information Figure 26. TSSOP14 package mechanical drawing Figure 27. TSSOP14 package mechanical data Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.2 0.047 A1 0.05 0.15 0.002 0.004 0.006 A2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0° 8° 0° 8° L1 0.45 0.60 0.75 0.018 0.024 0.030 b c E A A2 E1 D 1 PIN 1 IDENTIFICATION A1 K L e Package information TL084, TL084A, TL084B 16/19 Doc ID 2301 Rev 5 6.3 SO-14 package information Figure 28. SO-14 package mechanical drawing Table 5. SO-14 package mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.35 1.75 0.05 0.068 A1 0.10 0.25 0.004 0.009 A2 1.10 1.65 0.04 0.06 B 0.33 0.51 0.01 0.02 C 0.19 0.25 0.007 0.009 D 8.55 8.75 0.33 0.34 E 3.80 4.0 0.15 0.15 e 1.27 0.05 H 5.80 6.20 0.22 0.24 h 0.25 0.50 0.009 0.02 L 0.40 1.27 0.015 0.05 k 8° (max.) ddd 0.10 0.004 TL084, TL084A, TL084B Ordering information Doc ID 2301 Rev 5 17/19 7 Ordering information Table 6. Order codes Order code Temperature range Package Packing Marking TL084IN TL084AIN TL084BIN -40°C, +105°C DIP14 Tube TL084IN TL084AIN TL084BIN TL084ID/IDT TL084AID/AIDT TL084BID/BIDT SO-14 Tube or tape & reel 084I 084AI 084BI TL084IYDT(1) TL084AIYDT(1) TL084BIYDT(1) 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent. SO-14 (Automotive grade) Tube or tape & reel 084IY 084AIY 084BIY TL084IP/IPT TL084AIP/AIPT TL084BIP/BIPT TSSOP14 Tube or tape & reel 084I 084AI 084BI TL084CN TL084ACN TL084BCN 0°C, +70°C DIP14 Tube TL084CN TL084ACN TL084BCN TL084CD/CDT TL084ACD/ACDT TL084BCD/BCDT SO-14 Tube or tape & reel 084C 084AC 084BC TL084CP/CPT TL084ACP/ACPT TL084BCP/BCPT TSSOP14 Tube or tape & reel 084C 084AC 084BC Revision history TL084, TL084A, TL084B 18/19 Doc ID 2301 Rev 5 8 Revision history Table 7. Document revision history Date Revision Changes 28-Mar-2001 1 Initial release. 30-Jul-2007 2 Added values for Rthja, Rthjc and ESD in Table 1: Absolute maximum ratings. Added Table 2: Operating conditions. Expanded Table 6: Order codes. Template update. 15-Jul-2008 3 Removed information concerning military temperature ranges (TL084Mx, TL084AMx, TL084BMx). Added automotive grade order codes in Table 6: Order codes. 05-Jul-2012 4 Removed commercial types TL084IYD, TL084AIYD and TL084BIYD. Updated Table 6: Order codes. 29-Jan-2013 5 Added part numbers TL084A and TL084B. Added SO-14 package silhouette. Updated layout of Table 1: Absolute maximum ratings. Updated of Table 3: VCC = ±15 V, Tamb = +25 °C (unless otherwise specified). Replaced SO-14 package mechanical drawing (Figure 28: SO-14 package mechanical drawing). Replaced SO-14 package mechanical data (Table 5: SO-14 package mechanical data). TL084, TL084A, TL084B Doc ID 2301 Rev 5 19/19 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com January 2009 Rev 2 1/16 16 NE556 SA556 - SE556 General-purpose dual bipolar timers Features ■ Low turn-off time ■ Maximum operating frequency greater than 500 kHz ■ Timing from microseconds to hours ■ Operates in both astable and monostable modes ■ Output can source or sink up to 200 mA ■ Adjustable duty cycle ■ TTL compatible ■ Temperature stability of 0.005% per °C Description The NE556, SA556 and SE556 dual monolithic timing circuits are highly stable controllers capable of producing accurate time delays or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuits may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA. N DIP14 (Plastic package) D SO14 (Plastic micropackage) Pin connections (top view) ! "# ! www.st.com Schematic diagrams NE556 - SA556 - SE556 2/16 1 Schematic diagrams Figure 1. Block diagram Figure 2. Schematic diagram $!%&$' () * * * !+""%! ! ,'+)-,') & . +& $/!"% 0 +#$+1+2 !%&% !%&% () & 3 #!''/"% 2#% 0)0 #!' '/"% $!%&$' ()/!/! ! 4* ! . . . . . ! 4* ! * ! * . . . . . . . . $!%&$' !+""%! !%&% +& $/!"% "# . . ! * ! * ! * ! * . . . ! * ! ! 4* ! . . ! 4* . . . . ! 4* !+""%! ()/!/! ,'+),') ! * 4* NE556 - SA556 - SE556 Absolute maximum ratings and operating conditions 3/16 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage 18 V IOUT Output current (sink and source) ±225 mA Rthja Thermal resistance junction to ambient(1) DIP14 SO-14 1. Short-circuits can cause excessive heating. These values are typical and valid only for a single layer PCB. 80 105 °C/W Rthjc Thermal resistance junction to case (1) DIP14 SO-14 33 31 °C/W ESD Human body model (HBM)(2) 2. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 1000 Machine model (MM)(3) V 3. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of connected pin combinations while the other pins are floating. 150 Charged device model (CDM)(4) 4. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. 1500 Latch-up immunity 200 mA TLEAD Lead temperature (soldering 10 seconds) 260 °C Tj Junction temperature 150 °C Tstg Storage temperature range -65 to 150 °C Table 2. Operating conditions Symbol Parameter Value Unit VCC Supply voltage NE556 SA556 SE556 4.5 to 16 4.5 to 16 4.5 to 18 V Vth, Vtrig, Vcl, Vreset Maximum input voltage VCC V IOUT Output current (sink and source) ±200 mA Toper Operating free air temperature range NE556 SA556 SE556 0 to 70 -40 to 105 -55 to 125 °C Electrical characteristics NE556 - SA556 - SE556 4/16 3 Electrical characteristics Table 3. Tamb = +25° C, VCC = +5 V to +15 V (unless otherwise specified) Symbol Parameter SE556 NE556 - SA556 Unit Min. Typ. Max. Min. Typ. Max. ICC Supply current (RL ∝) (2 timers) Low state VCC = +5V VCC = +15V High State VCC = +5V 6 20 4 10 24 6 20 4 12 30 mA Timing error (monostable) (RA = 2kΩ to 100kΩ, C = 0.1μF) Initial accuracy (1) Drift with temperature Drift with supply voltage 0.5 30 0.05 2 100 0.2 1 50 0.1 3 0.5 % ppm/°C %/V Timing error (astable) (RA, RB = 1kΩ to 100kΩ, C = 0.1μF, VCC= +15V) Initial accuracy (1) Drift with temperature Drift with supply voltage 1.5 90 0.15 2.25 150 0.3 % ppm/°C %/V VCL Control voltage level VCC = +15V VCC = +5V 9.6 2.9 10 3.33 10.4 3.8 9 2.6 10 3.33 11 4 V Vth Threshold voltage VCC = +15V VCC = +5V 9.4 2.7 10 3.33 10.6 4 8.8 2.4 10 3.33 11.2 4.2 V Ith Threshold current (2) 0.1 0.25 0.1 0.25 μA Vtrig Trigger voltage VCC = +15V VCC = +5V 4.8 1.45 5 1.67 5.2 1.9 4.5 1.1 5 1.67 5.6 2.2 V Itrig Trigger current (Vtrig = 0V) 0.5 0.9 0.5 2.0 μA Vreset Reset voltage (3) 0.4 0.7 1 0.4 0.7 1 V Ireset Reset current Vreset = +0.4V Vreset = 0V 0.1 0.4 0.4 1 0.1 0.4 0.4 1.5 mA VOL Low level output voltage VCC = +15V IO(sink) = 10mA IO(sink) = 50mA IO(sink) = 100mA IO(sink) = 200mA VCC = +5V IO(sink) = 8mA IO(sink) = 5mA 0.1 0.4 2 2.5 0.1 0.05 0.15 0.5 2.2 0.25 0.2 0.1 0.4 2 2.5 0.3 0.25 0.25 0.75 2.5 0.4 0.35 V VOH High level output voltage VCC = +15V IO(sink) = 200mA IO(sink) = 100mA VCC = +5V IO(sink) = 100mA 13 3 12.5 13.3 3.3 12.75 2.75 12.5 13.3 3.3 V NE556 - SA556 - SE556 Electrical characteristics 5/16 Idis(off) Discharge pin leakage current (output high) (Vdis = 10V) 20 100 20 100 nA Vdis(sat) Discharge pin saturation voltage (output low) (4) VCC = +15V, Idis = 15mA VCC = +5V, Idis = 4.5mA 180 80 480 200 180 80 480 200 mV tr tf Output rise time Output fall time 100 100 200 200 100 100 300 300 ns toff Turn-off time (5) (Vreset = VCC) 0.5 0.5 μs 1. Tested at VCC = +5 V and VCC = +15 V 2. This will determine the maximum value of RA + RB for +15V operation the max total is R = 20 MΩ and for +5 V operation the max total R = 3.5 MΩ 3. Specified with trigger input high 4. No protection against excessive pin 7 current is necessary, providing the package dissipation rating will not be exceeded 5. Time measured from a positive going input pulse from 0 to 0.8 x VCC into the threshold to the drop from high to low of the output trigger is tied to threshold. Table 3. Tamb = +25° C, VCC = +5 V to +15 V (unless otherwise specified) (continued) Symbol Parameter SE556 NE556 - SA556 Unit Min. Typ. Max. Min. Typ. Max. Electrical characteristics NE556 - SA556 - SE556 6/16 Figure 3. Minimum pulse width required for triggering Figure 4. Supply current versus supply voltage Figure 5. Delay time versus temperature Figure 6. Low output voltage versus output sink current Figure 7. Low output voltage versus output sink current Figure 8. Low output voltage versus output sink current NE556 - SA556 - SE556 Electrical characteristics 7/16 Figure 9. High output voltage drop versus output Figure 10. Delay time versus supply voltage Figure 11. Propagation delay versus voltage level of trigger value Application information NE556 - SA556 - SE556 8/16 4 Application information 4.1 Typical application Figure 12. 50% duty cycle oscillator t1 = 0.693 RA.C Figure 13. Pulse width modulator ! / 56 56 56 56 56 * 56 * ! 4, t2 = [(RARB)/(RA+RB)]CLn RB – 2RA 2RB – RA --------------------------- f = t1 t1 + t2 ----------------- RB < 1 2 --- RA ti ! / 56 56 56 56 56 56 (0'/+# +#0 NE556 - SA556 - SE556 Application information 9/16 Figure 14. Tone burst generator For a tone burst generator the first timer is used as a monostable and determines the tone duration when triggered by a positive pulse at pin 6. The second timer is enabled by the high output or the monostable. It is connected as an astable and determines the frequency of the tone. Figure 15. Monostable operation !/ !1 ! 78 4 !/3!16 " " 4, 2 #% &% 3 " 4, 2 #% &% ! ! 84!4 ! / 56 56 56 56 56 !' !' , 56 84!4 / Application information NE556 - SA556 - SE556 10/16 Figure 16. Astable operation t1 = 0.693 (RA + RB) C output high t2 = 0.693 RBC output low ! / 56 56 56 56 56 !' !' 56 !1 9 : 4, 8 4 !/3!16 NE556 - SA556 - SE556 Package information 11/16 5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Package information NE556 - SA556 - SE556 12/16 5.1 DIP14 package information Figure 17. DIP14 package mechanical drawing Note: D and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm. Table 4. DIP14 package mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 5.33 0.21 A1 0.38 0.015 A2 2.92 3.30 4.95 0.11 0.13 0.19 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.04 0.06 0.07 c 0.20 0.25 0.36 0.007 0.009 0.01 D 18.67 19.05 19.69 0.73 0.75 0.77 E 7.62 7.87 8.26 0.30 0.31 0.32 E1 6.10 6.35 7.11 0.24 0.25 0.28 e 2.54 0.10 e1 15.24 0.60 eA 7.62 0.30 eB 10.92 0.43 L 2.92 3.30 3.81 0.11 0.13 0.15 NE556 - SA556 - SE556 Package information 13/16 5.2 SO-14 package information Figure 18. SO-14 package mechanical drawing Note: D and F dimensions do not include mold flash or protrusions. Mold flash or protrusions must not exceed 0.15 mm. Table 5. SO-14 package mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.35 1.75 0.05 0.068 A1 0.10 0.25 0.004 0.009 A2 1.10 1.65 0.04 0.06 B 0.33 0.51 0.01 0.02 C 0.19 0.25 0.007 0.009 D 8.55 8.75 0.33 0.34 E 3.80 4.0 0.15 0.15 e 1.27 0.05 H 5.80 6.20 0.22 0.24 h 0.25 0.50 0.009 0.02 L 0.40 1.27 0.015 0.05 k 8° (max.) ddd 0.10 0.004 Ordering information NE556 - SA556 - SE556 14/16 6 Ordering information Table 6. Order codes Part number Temperature range Package Packing Marking NE556N 0°C, +70°C DIP14 Tube NE556N NE556D/DT SO-14 Tube or tape & reel NE556 SA556N -40°C, +105°C DIP14 Tube SA556N SA556D/DT SO-14 Tube or tape & reel SA556 SE556N -55°C, + 125°C DIP14 Tube SE556N SE556D/DT SO-14 Tube or tape & reel SE556 NE556 - SA556 - SE556 Revision history 15/16 7 Revision history Table 7. Document revision history Date Revision Changes 01-Jun-2003 1 Initial release. 27-Jan-2009 2 Document reformatted. Added IOUT value in Table 1: Absolute maximum ratings and Table 2: Operating conditions. Added ESD tolerance, latch-up tolerance, Rthja and Rthjcin Table 1: Absolute maximum ratings. Updated Section 5.1: DIP14 package information and Section 5.2: SO-14 package information. NE556 - SA556 - SE556 16/16 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com L293B L293E July 2003 n OUTPUT CURRENT 1A PER CHANNEL n PEAK OUTPUT CURRENT 2A PER CHANNEL (non repetitive) n INHIBIT FACILITY n HIGH NOISE IMMUNITY n SEPARATE LOGIC SUPPLY n OVERTEMPERATURE PROTECTION DESCRIPTION The L293B and L293E are quad push-pull drivers capable of delivering output currents to 1A per channel. Each channel is controlled by a TTLcompatible logic input and each pair of drivers (a full bridge) is equipped with an inhibit input which turns off all four transistors. A separate supply input is provided for the logic so that it may be run off a lower voltage to reduce dissipation. Additionally, the L293E has external connection of sensing resistors, for switchmode control. The L293B and L293E are package in 16 and 20- pin plastic DIPs respectively ; both use the four center pins to conduct heat to the printed circuit board. DIP16 POWERDIP(16+2+2) ORDERING NUMBERS: L293B L293E PUSH-PULL FOUR CHANNEL DRIVERS PIN CONNECTION (Top view) DIP16 - L293B POWERDIP (16+2+2) - L293E L293E L293B 2/12 BLOCK DIAGRAMS DIP16 - L293B POWERDIP (16+2+2) - L293E 3/12 L293E L293B SCHEMATIC DIAGRAM (*) In the L293 these points are not externally available. They are internally connected to the ground (substrate). O Pins of L293 () Pins of L293E. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vs Supply Voltage 36 V Vss Logic Supply Voltage 36 V Vi Input Voltage 7 V Vinh Inhibit Voltage 7 V Iout Peak Output Current (non repetitive t = 5ms) 2 A Ptot Total Power Dissipation at Tground-pins = 80°C 5 W Tstg, Tj Storage and Junction Temperature –40 to +150 oC L293E L293B 4/12 THERMAL DATA ELECTRICAL CHARACTERISTCS * See figure 1 ** Referred to L293E TRUTH TABLE (*) High output impedance (**) Relative to the considerate channel Symbol Parameter Value Unit Rth j-case Thermal Resistance Junction-case Max. 14 oC/W Rth j-amb Thermal Resistance Junction-ambient Max. 80 oC/W Symbol Parameter Test Condition Min. Typ. Max. Unit Vs Supply Voltage Vss 36 V Vss Logic Supply Voltage 4.5 36 V Is Total Quiescent Supply Current Vi = L; Io = 0; Vinh = H 2 6 mA Vi = h; Io = 0; Vinh = H 16 24 mA Vinh = L 4 mA Iss Total Quiescent Logic Supply Current Vi = L; Io = 0; Vinh = H 44 60 mA Vi = h; Io = 0; Vinh = H 16 22 mA Vinh = L 16 24 mA ViL Input Low Voltage -0.3 1.5 V ViH Input High Voltage VSS £ 7V 2.3 Vss V VSS > 7V 2.3 7 V IiL Low Voltage Input Current Vil = 1.5V -10 mA IiH High Voltage Input Current 2.3V £ VIH £ VSS - 0.6V 30 100 mA VinhL Inhibit Low Voltage -0.3 1.5 V VinhH Inhibit High Voltage VSS £7V 2.3 Vss V VSS > 7V 2.3 7 V IinhL Low Voltage Inhibit Current VinhL = 1.5V -30 -100 mA IinhH High Voltage Inhibit Current 2.3V £VinhH£ Vss- 0.6V ±10 mA VCEsatH Source Output Saturation Voltage Io = -1A 1.4 1.8 V VCEsatL Sink Output Saturation Voltage Io = 1A 1.2 1.8 V VSENS Sensing Voltage (pins 4, 7, 14, 17) (**) 2 V tr Rise Time 0.1 to 0.9 Vo (*) 250 ns tf Fall Time 0.9 to 0.1 Vo (*) 250 ns ton Turn-on Delay 0.5 Vi to 0.5 Vo (*) 750 ns toff Turn-off Delay 0.5 Vi to 0.5 Vo (*) 200 ns Vi (each channel) Vo Vinh (**) H H H L L H H X (*) L L X (*) L 5/12 L293E L293B Figure 1. Switching Timers Figure 2. Saturation voltage versus Output Current Figure 3. Source Saturation Voltage versus Ambient Temperature Figure 4. Sink Saturation Voltage versus Ambient Temperature Figure 5. Quiescent Logic Supply Current versus Logic Supply Voltage L293E L293B 6/12 Figure 6. Output Voltage versus Input Voltage Figure 7. Output Voltage versus Inhibit Voltage APPLICATION INFORMATION Figure 8. DC Motor Controls (with connection to ground and to the supply voltage) L = Low H = High X = Don’t Care Figure 9. Bidirectional DC Motor Control L = Low H = High X = Don’t Care Vinh A M1 B M2 H H Fast Motor Stop H Run H L Run L Fast Motor Stop L X Free Running X Free Running Motor Stop Motor Stop Inputs Function Vinh = H C = H ; D = L Turn Right C = L ; D = H Turn Left C = D Fast Motor Stop Vinh = L C = X ; D = X Free Running Motor Stop 7/12 L293E L293B Figure 10. Bipolar Stepping Motor Control L293E L293B 8/12 Figure 11. Stepping Motor Driver with Phase Current Control and Short Circuit Protection 9/12 L293E L293B MOUNTING INSTRUCTIONS The Rth j-amb of the L293B and the L293E can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board as shown in figure 12 or to an external heatsink (figure 13). During soldering the pins temperature must not exceed 260°C and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper area must be connected to electrical ground. Figure 12. Example of P.C. Board Copper Area which is Used as Heatsink Figure 13. External Heatsink Mounting Example (Rth = 30°C/W) L293E L293B 10/12 DIP16 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 OUTLINE AND MECHANICAL DATA 11/12 L293E L293B DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.85 1.40 0.033 0.055 b 0.50 0.020 b1 0.38 0.50 0.015 0.020 D 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L 3.30 0.130 Z 1.27 0.050 Powerdip 20 OUTLINE AND MECHANICAL DATA Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. STMicroelectronics acknowledges the trademarks of all companies referred to in this document. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United LF351 Wide bandwidth single JFET operational amplifiers Features ■ Internally adjustable input offset voltage ■ Low power consumption ■ Wide common-mode (up to VCC +) and differential voltage range ■ Low input bias and offset current ■ Output short-circuit protection ■ High input impedance JFET input stage ■ Internal frequency compensation ■ Latch up free operation ■ High slew rate 16 V/μs (typical) Description These circuits are high speed JFET input single operational amplifiers incorporating well matched, high voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. N DIP8 (Plastic package) D SO-8 (Plastic micro package) 1 - Offset null 1 2 - Inverting input 3 - Non-inverting input 4 - VCC- 5 - Offset null 2 6 - Output 7 - VCC+ 8 - N.C. Pin connections (top view) www.st.com Schematics LF351 2/14 1 Schematics Figure 1. Schematic diagram Figure 2. Input offset voltage null circuit Output Non-inverting input Inverting input VCC VCC 100W 1.3k 30k 35k 35k 100W 1.3k 8.2k Offset Null1 Offset Null2 100W 200W LF351 Absolute maximum ratings and operating conditions 3/14 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage(1) ±18 V Vi Input voltage(2) ±15 V Vid Differential input voltage(3) ±30 V Rthja Thermal resistance junction to ambient(4) SO-8 DIP8 125 85 °C/W Rthjc Thermal resistance junction to case(4) SO-8 DIP8 40 41 °C/W Output short-circuit duration(5) Infinite Tstg Storage temperature range -65 to +150 °C ESD HBM: human body model(6) 500 V MM: machine model(7) 200 V CDM: charged device model(8) 1.5 kV 1. All voltage values, except differential voltage, are with respect to the zero reference level (ground) of the supply voltages where the zero reference level is the midpoint between VCC + and VCC -. 2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less. 3. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical. 5. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded 6. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 7. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of connected pin combinations while the other pins are floating. 8. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. Table 2. Operating conditions Symbol Parameter LF151 LF251 LF351 Unit VCC Supply voltage 6 to 32 V Toper Operating free-air temperature range -55 to +125 -40 to +105 0 to +70 °C Electrical characteristics LF351 4/14 3 Electrical characteristics Table 3. Electrical characteristics at VCC = ±15 V, Tamb = +25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Vio Input offset voltage (Rs = 10kΩ) Tmin ≤ Tamb ≤ Tmax 3 10 13 mV DVio Input offset voltage drift 10 μV/°C Iio Input offset current (1) Tmin ≤ Tamb ≤ Tmax 5 100 4 pA nA Iib Input bias current (1) Tmin ≤ Tamb ≤ Tmax 20 200 20 pA nA Avd Large signal voltage gain (RL = 2kΩ, Vo = ±10V) Tmin ≤ Tamb ≤ Tmax 50 25 200 V/mV SVR Supply voltage rejection ratio (RS = 10kΩ) Tmin ≤ Tamb ≤ Tmax 80 80 86 dB ICC Supply current, no load Tmin ≤ Tamb ≤ Tmax 1.4 3.4 3.4 mA Vicm Input common mode voltage range ±11 +15 -12 V CMR Common mode rejection ratio (RS = 10kΩ) Tmin ≤ Tamb ≤ Tmax 70 70 86 dB IOS Output short-circuit current Tmin ≤ Tamb ≤ Tmax 10 10 40 60 60 mA ±Vopp Output voltage swing RL = 2kΩ RL = 10kΩ Tmin ≤ Tamb ≤ Tmax RL = 2kΩ RL = 10kΩ 10 12 10 12 12 13.5 V SR Slew rate, Vi = 10V, RL = 2kΩ, CL = 100pF, unity gain 12 16 V/μs tr Rise time, Vi = 20mV, RL = 2kΩ, CL = 100pF, unity gain 0.1 μs Kov Overshoot, Vi = 20mV, RL = 2kΩ, CL = 100pF, unity gain 10 % GBP Gain bandwidth product, f = 100kHz, Vin = 10mV, RL = 2kΩ, CL = 100pF 2.5 4 MHz Ri Input resistance 1012 Ω THD Total harmonic distortion f= 1kHz, Av= 20dB, RL= 2kΩ, CL=100pF, Vo= 2Vpp 0.01 % en Equivalent input noise voltage RS = 100Ω, f = 1KHz 15 ∅m Phase margin 45 Degrees 1. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature. nV Hz ----------- LF351 Electrical characteristics 5/14 Figure 3. Maximum peak-to-peak output voltage versus frequency Figure 4. Maximum peak-to-peak output voltage versus frequency Figure 5. Maximum peak-to-peak output voltage versus frequency Figure 6. Maximum peak-to-peak output voltage versus free air temp. Figure 7. Maximum peak-to-peak output voltage versus load resistance Figure 8. Maximum peak-to-peak output voltage versus supply voltage Electrical characteristics LF351 6/14 Figure 9. Input bias current versus free air temperature Figure 10. Large signal differential voltage amplification versus free air temp. Figure 11. Large signal differential voltage amplification and phase shift versus frequency Figure 12. Total power dissipation versus free air temperature Figure 13. Supply current per amplifier versus free air temperature Figure 14. Supply current per amplifier versus supply voltage LF351 Electrical characteristics 7/14 Figure 15. Common mode rejection ratio versus free air temperature Figure 16. Voltage follower large signal pulse response Figure 17. Output voltage versus elapsed time Figure 18. Equivalent input noise voltage versus frequency Figure 19. Total harmonic distortion versus frequency Parameter measurement information LF351 8/14 4 Parameter measurement information Figure 20. Voltage follower Figure 21. Gain-of-10 inverting amplifier LF351 Typical application 9/14 5 Typical application Figure 22. Square wave oscillator (0.5 Hz) Figure 23. High Q notch filter Package information LF351 10/14 6 Package information In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com. LF351 Package information 11/14 6.1 DIP8 package information Figure 24. DIP8 package mechanical drawing Table 4. DIP8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 5.33 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 9.02 9.27 10.16 0.355 0.365 0.400 E 7.62 7.87 8.26 0.300 0.310 0.325 E1 6.10 6.35 7.11 0.240 0.250 0.280 e 2.54 0.100 eA 7.62 0.300 eB 10.92 0.430 L 2.92 3.30 3.81 0.115 0.130 0.150 Package information LF351 12/14 6.2 SO-8 package information Figure 25. SO-8 package mechanical drawing Table 5. SO-8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.75 0.069 A1 0.10 0.25 0.004 0.010 A2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 1° 8° 1° 8° ccc 0.10 0.004 LF351 Ordering information 13/14 7 Ordering information 8 Revision history Table 6. Order codes Order code Temperature range Package Packing Marking LF151N -55°C, +125°C DIP8 Tape LF151N LF151D LF151DT SO-8 Tape or Tape & reel 151 LF251N -40°C, +105°C DIP8 Tape LF251N LF251D LF251DT SO-8 Tape or Tape & reel 251 LF351N 0°C, +70°C DIP8 Tape LF351N LF351D LF351DT SO-8 Tape or Tape & reel 351 Table 7. Document revision history Date Revision Changes 17-May-2001 1 Initial release. 28-April-2008 2 Updated document format. LF351 14/14 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com LM158, LM258, LM358 Low-power dual operational amplifiers Datasheet - production data Features • Internally frequency-compensated • Large DC voltage gain: 100 dB • Wide bandwidth (unity gain): 1.1 MHz (temperature compensated) • Very low supply current per operator essentially independent of supply voltage • Low input bias current: 20 nA (temperature compensated) • Low input offset voltage: 2 mV • Low input offset current: 2 nA • Input common-mode voltage range includes negative rails • Differential input voltage range equal to the power supply voltage • Large output voltage swing 0 V to (VCC + -1.5 V) Description These circuits consist of two independent, high-gain, internally frequency-compensated op-amps, specifically designed to operate from a single power supply over a wide range of voltages. The low-power supply drain is independent of the magnitude of the power supply voltage. Application areas include transducer amplifiers, DC gain blocks and all the conventional op-amp circuits, which can now be more easily implemented in single power supply systems. For example, these circuits can be directly supplied with the standard +5 V, which is used in logic systems and will easily provide the required interface electronics with no additional power supply. In linear mode, the input common-mode voltage range includes ground and the output voltage can also swing to ground, even though operated from only a single power supply voltage. DIP8 (Plastic package) SO8 and MiniSO8 (Plastic micropackage) TSSOP8 (Thin shrink small outline package) Pin connections (Top view) 1 2 3 Out1 In1- In1+ Vcc- 4 8 7 6 Vcc+ Out2 In2- 5 In2+ DFN8 2 x 2 mm (Plastic micropackage) www.st.com Contents LM158, LM258, LM358 2/22 DocID2163 Rev 11 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 DIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 DFN8 2 x 2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DocID2163 Rev 11 3/22 LM158, LM258, LM358 Schematic diagram 22 1 Schematic diagram Figure 1. Schematic diagram (1/2 LM158) 6μA 4μA 100μA Q2 Q3 Q1 Q4 Inverting input Non-inverting input Q8 Q9 Q10 Q11 Q12 50μA Q13 Output Q7 Q6 Q5 R SC VCC CC GND Absolute maximum ratings LM158, LM258, LM358 4/22 DocID2163 Rev 11 2 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol Parameter LM158,A LM258,A LM358,A Unit VCC Supply voltage +/-16 or 32 V Vi Input voltage 32 V Vid Differential input voltage 32 V Output short-circuit duration (1) 1. Short-circuits from the output to VCC can cause excessive heating if VCC > 15 V. The maximum output current is approximately 40 mA independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short circuits on all amplifiers. Infinite Iin Input current (2) 2. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward-biased and thereby acting as input diode clamp. In addition to this diode action, there is NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the Op-amps to go to the VCC voltage level (or to ground for a large overdrive) for the time during which an input is driven negative. This is not destructive and normal output is restored for input voltages above -0.3 V. 5 mA in DC or 50 mA in AC (duty cycle = 10%, T=1s) mA Toper Operating free-air temperature range -55 to +125 -40 to +105 0 to +70 °C Tstg Storage temperature range -65 to +150 °C Tj Maximum junction temperature 150 °C Rthja Thermal resistance junction to ambient(3) SO8 MiniSO8 TSSOP8 DIP8 DFN8 2x2 3. Short-circuits can cause excessive heating and destructive dissipation. Rth are typical values. 125 190 120 85 57 °C/W Rthjc Thermal resistance junction to case (3) SO8 MiniSO8 TSSOP8 DIP8 40 39 37 41 °C/W ESD HBM: human body model(4) 4. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kW resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 300 V MM: machine model(5) 5. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 W). This is done for all couples of connected pin combinations while the other pins are floating. 200 V CDM: charged device model(6) 6. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. 1.5 kV DocID2163 Rev 11 5/22 LM158, LM258, LM358 Operating conditions 22 3 Operating conditions Table 2. Operating conditions Symbol Parameter Value Unit VCC Supply voltage 3 to 30 V Vicm Common mode input voltage range(1) 1. When used in comparator, the functionality is guaranteed as long as at least one input remains within the operating common mode voltage range. VCC - -0.3 to VCC + -1.5 V Toper Operating free air temperature range LM158 LM258 LM358 -55 to +125 -40 to +105 0 to +70 °C Electrical characteristics LM158, LM258, LM358 6/22 DocID2163 Rev 11 4 Electrical characteristics Table 3. Electrical characteristics for VCC + = +5 V, VCC - = Ground, Vo = 1.4 V, Tamb = +25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Vio Input offset voltage (1) LM158A LM258A, LM358A LM158, LM258 LM358 1 2 2357 mV Tmin £ Tamb £ Tmax LM158A, LM258A, LM358A LM158, LM258 LM358 479 DVio Input offset voltage drift LM158A, LM258A, LM358A LM158, LM258, LM358 77 15 30 μV/°C Iio Input offset current LM158A, LM258A, LM358A LM158, LM258, LM358 Tmin £ Tamb £ Tmax LM158A, LM258A, LM358A LM158, LM258, LM358 22 10 30 30 40 nA DIio Input offset current drift LM158A, LM258A, LM358A LM158, LM258, LM358 10 10 200 300 pA/°C Iib Input bias current (2) LM158A, LM258A, LM358A LM158, LM258, LM358 Tmin £ Tamb £ Tmax LM158A, LM258A, LM358A LM158, LM258, LM358 20 20 50 150 100 200 nA Avd Large signal voltage gain VCC += +15 V, RL = 2 kW, Vo = 1.4 V to 11.4 V Tmin £ Tamb £ Tmax 50 25 100 V/mV SVR Supply voltage rejection ratio VCC + = 5 V to 30 V, Rs £ 10 kW Tmin £ Tamb £ Tmax 65 65 100 dB ICC Supply current, all amp, no load Tmin £ Tamb £ Tmax VCC + = +5 V Tmin £ Tamb £ Tmax VCC + = +30 V 0.7 1.2 2 mA Vicm Input common mode voltage range VCC += +30 V (3) Tmin £ Tamb £ Tmax 0 0 VCC + -1.5 VCC + -2 V DocID2163 Rev 11 7/22 LM158, LM258, LM358 Electrical characteristics 22 CMR Common mode rejection ratio Rs £ 10 kW Tmin £ Tamb £ Tmax 70 60 85 dB Isource Output current source VCC + = +15 V, Vo = +2 V, Vid = +1 V 20 40 60 mA Isink Output sink current VCC + = +15 V, Vo = +2 V, Vid = -1 V VCC + = +15 V, Vo = +0.2 V, Vid = -1 V 10 12 20 50 mA μA VOH High level output voltage RL = 2 kW, VCC + = 30 V Tmin £ Tamb £ Tmax RL = 10 kW, VCC + = 30 V Tmin £ Tamb £ Tmax 26 26 27 27 27 28 V VOL Low level output voltage RL = 10 kW Tmin £ Tamb £ Tmax 5 20 20 mV SR Slew rate VCC + = 15 V, Vi = 0.5 to 3 V, RL = 2 kW, CL = 100 pF, unity gain 0.3 0.6 V/μs GBP Gain bandwidth product VCC + = 30 V, f = 100 kHz, Vin = 10 mV, RL = 2 kW, CL = 100 pF 0.7 1.1 MHz THD Total harmonic distortion f = 1 kHz, Av = 20 dB, RL = 2 kW, Vo = 2 Vpp, CL = 100 pF, VO = 2 Vpp 0.02 % en Equivalent input noise voltage f = 1 kHz, Rs = 100 W, VCC + = 30 V 55 Vo1/Vo2 Channel separation(4) 1 kHz £ f £ 20 kHz 120 dB 1. Vo = 1.4 V, Rs = 0 W, 5 V < VCC + < 30 V, 0 < Vic < VCC + - 1.5 V 2. The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so there is no change in the load on the input lines. 3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is VCC + - 1.5 V, but either or both inputs can go to +32 V without damage. 4. Due to the proximity of external components, ensure that stray capacitance between these external parts does not cause coupling. Typically, this can be detected because this type of capacitance increases at higher frequencies. Table 3. Electrical characteristics for VCC + = +5 V, VCC - = Ground, Vo = 1.4 V, Tamb = +25°C (unless otherwise specified) (continued) Symbol Parameter Min. Typ. Max. Unit nV Hz ----------- Electrical characteristics LM158, LM258, LM358 8/22 DocID2163 Rev 11 Figure 2. Open-loop frequency response Figure 3. Large signal frequency response VOLTAGE GAIN (dB) 1.0 10 100 1k 10k 100k 1M 10M VCC = +10 to +15 V & FREQUENCY (Hz) 10 M VI VCC/2 VCC = 30 V & -55°C 0.1 F VCC VO - + -55°C Tamb +125°C 140 120 100 80 60 40 20 0 Tamb +125°C - + OUTPUT SWING (Vpp) 1k 10k 100k 1M FREQUENCY (Hz) 100 k VI 1 k VO 20 15 10 5 0 2 k +15 V +7 V Figure 4. Voltage follower pulse response with VCC = 15 V Figure 5. Voltage follower pulse response with VCC = 30 V INPUT VOLTAGE (V) TIME (s) RL 2 k OUTPUT VOLTAGE (V) 4 3 2 1 0 3 2 1 VCC = +15 V 0 10 20 30 40 Input Output 50 pF + - OUTPUT VOLTAGE (mV) 0 1 2 3 4 5 6 7 8 TIME (s) eI Tamb = +25°C VCC = 30 V 500 450 400 350 300 250 eO Figure 6. Input current Figure 7. Output voltage vs sink current INPUT CURRENT (mA) TEMPERATURE (°C) -55 -35 -15 5 25 45 65 85 105 125 90 80 70 60 50 40 30 20 10 0 VCC = +30 V VCC = +15 V VCC = +5 V VI = 0 V - + OUTPUT VOLTAGE (v) 0.001 0.01 0.1 1 10 100 OUTPUT SINK CURRENT (mA) VO VCC/2 VCC = +5 V VCC = +15 V VCC = +30 V VCC IO 10 1 0.1 0.01 Tamb = + 25°C DocID2163 Rev 11 9/22 LM158, LM258, LM358 Electrical characteristics 22 Figure 8. Output voltage vs source current Figure 9. Current limiting + - OUTPUT VOLTAGE REFERENCED TO VCC+ (V) 0.001 0.01 0.1 1 10 100 OUTPUT SOURCE CURRENT (mA) VO Independent of VCC VCC/2 IO 8 5 2 1 Tamb = + 25°C VCC 7 6 4 3 - + OUTPUT CURRENT (mA) -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE °C IO 90 80 50 40 30 20 10 0 70 60 Figure 10. Input voltage range Figure 11. Open-loop gain Figure 12. Supply current Figure 13. Input current Negative Positive INPUT VOLTAGE (V) 0 5 10 15 POWER SUPPLY VOLTAGE (±V) 10 5 15 VOLTAGE GAIN (dB) POSITIVE SUPPLY VOLTAGE (V) 0 10 20 30 40 120 40 160 80 RL = 20 k RL = 2 k - + SUPPLY CURRENT (mA) 0 10 20 30 POSITIVE SUPPLY VOLTAGE (V) mA VCC ID Tamb = 0°C to +125°C 4 3 2 1 Tamb = -55°C INPUT CURRENT (nA) 0 10 20 30 POSITIVE SUPPLY VOLTAGE (V) 100 75 50 25 Tamb = +25°C Electrical characteristics LM158, LM258, LM358 10/22 DocID2163 Rev 11 Figure 14. Gain bandwidth product Figure 15. Power supply rejection ratio GAIN BANDWIDTH PRODUCT (MHz) -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1.05 0.45 0.3 0.15 VCC = ± 15 V 1.2 0.9 0.75 0.6 1.35 1.5 0 POWER SUPPLY REJECTION RATIO (dB) SVR -55 -35 -15 5 25 45 65 85 105 125 100 80 75 70 105 95 90 85 110 115 65 TEMPERATURE (°C) 60 Figure 16. Common-mode rejection ratio Figure 17. Phase margin vs. capacitive load COMMON MODE REJECTION RATIO (dB) -55 -35 -15 5 25 45 65 85 105 125 100 80 75 70 105 95 90 85 110 115 65 TEMPERATURE (°C) 60 Phase Margin at Vcc=15V and Vicm=7.5V Vs. Iout and Capacitive load value DocID2163 Rev 11 11/22 LM158, LM258, LM358 Typical applications 22 5 Typical applications Single supply voltage VCC = +5 VDC. Figure 18. AC-coupled inverting amplifier Figure 19. Non-inverting DC amplifier 1/2 LM158 ~ 0 2VPP R 10k L Co eo R 6.2k B R 100k f R1 CI 10k eI VCC R2 100k C1 10F R3 100k A =- R V R1 f (as shown AV = -10) R1 10k R2 1M 1/2 LM158 10k eI eO +5V e O (V) (mV) 0 AV= 1 + R2 R1 (As shown AV = 101) Figure 20. AC-coupled non-inverting amplifier Figure 21. DC summing amplifier 1/2 LM158 ~ 0 2VPP R 10k L Co eo R 6.2k B C1 0.1F eI VCC (as shown AV = 11) A = 1 +R2 V R1 R1 100k R2 1M CI R3 1M R4 100k R5 100k C2 10F 1/2 LM158 eO e 4 e 3 e 2 e 1 100k 100k 100k 100k 100k 100k eo = e1 + e2 - e3 - e4 where (e1 + e2) ≥ (e3 + e4) to keep eo ≥ 0V Figure 22. High input Z, DC differential amplifier Figure 23. High input Z adjustable gain DC instrumentation amplifier R1 100k R2 100k R4 100k R3 100k +V2 +V1 Vo 1/2 LM158 1/2 LM158 if R1 = R5 and R3 = R4 = R6 = R7 eo = [1 + ] ( (e2 + e1) As shown eo = 101 (e2 + e1) 2R1 R2 ----------- R3 100k eO 1/2 LM158 R1 100k e 1 R7 100k R6 100k R5 100k e 2 R2 2k Gain adjust R4 100k 1/2 LM158 1/2 LM158 if R1 = R5 and R3 = R4 = R6 = R7 eo = [ 1 + ] ( (e2 + e1) As shown eo = 101 (e2 + e1) 2R1 R2 ----------- Typical applications LM158, LM258, LM358 12/22 DocID2163 Rev 11 Figure 24. Using symmetrical amplifiers to reduce input current Figure 25. Low drift peak detector Figure 26. Active band-pass filter 1/2 LM158 IB 2N 929 0.001F IB 3M IB I eo I e I IB IB Input current compensation 1.5M 1/2 LM158 IB 2N 929 0.001F IB 3R 3M IB Input current compensation eo IB e I 1/2 LM158 Zo ZI C 1F 2IB R 1M 2IB 1/2 LM158 1/2 LM158 1/2 LM158 R8 100k C3 10F R7 100k R5 470k C1 330pF Vo VCC R6 470k C2 330pF R4 10M R1 100k R2 100k +V1 R3 100k 1/2 LM158 1/2 LM158 DocID2163 Rev 11 13/22 LM158, LM258, LM358 Package information 22 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Package information LM158, LM258, LM358 14/22 DocID2163 Rev 11 6.1 DIP8 package information Figure 27. DIP8 package mechanical drawing Table 4. DIP8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 5.33 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 9.02 9.27 10.16 0.355 0.365 0.400 E 7.62 7.87 8.26 0.300 0.310 0.325 E1 6.10 6.35 7.11 0.240 0.250 0.280 e 2.54 0.100 eA 7.62 0.300 eB 10.92 0.430 L 2.92 3.30 3.81 0.115 0.130 0.150 DocID2163 Rev 11 15/22 LM158, LM258, LM358 Package information 22 6.2 SO8 package information Figure 28. SO8 package mechanical drawing Table 5. SO8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.75 0.069 A1 0.10 0.25 0.004 0.010 A2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 1.04 0.040 k 1° 8° 1° 8° ccc 0.10 0.004 Package information LM158, LM258, LM358 16/22 DocID2163 Rev 11 6.3 MiniSO8 package information Figure 29. MiniSO8 package mechanical drawing Table 6. MiniSO8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.1 0.043 A1 0 0.15 0 0.006 A2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e 0.65 0.026 L 0.40 0.60 0.80 0.016 0.024 0.031 L1 0.95 0.037 L2 0.25 0.010 k 0° 8° 0° 8° ccc 0.10 0.004 DocID2163 Rev 11 17/22 LM158, LM258, LM358 Package information 22 6.4 TSSOP8 package information Figure 30. TSSOP8 package mechanical drawing Table 7. TSSOP8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.2 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 2.90 3.00 3.10 0.114 0.118 0.122 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.177 e 0.65 0.0256 k 0° 8° 0° 8° L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1 0.039 aaa 0.1 0.004 Package information LM158, LM258, LM358 18/22 DocID2163 Rev 11 6.5 DFN8 2 x 2 package mechanical data Figure 31. DFN8 2 x 2 package mechanical drawing Table 8. DFN8 2 x 2 x 0.6 mm package mechanical data (pitch 0.5 mm) Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.51 0.55 0.60 0.020 0.022 0.024 A1 0.05 0.002 A3 0.15 0.006 b 0.18 0.25 0.30 0.007 0.010 0.012 D 1.85 2.00 2.15 0.073 0.079 0.085 D2 1.45 1.60 1.70 0.057 0.063 0.067 E 1.85 2.00 2.15 0.073 0.079 0.085 E2 0.75 0.90 1.00 0.030 0.035 0.039 e 0.50 0.020 L 0.50 0.020 ddd 0.08 0.003 DocID2163 Rev 11 19/22 LM158, LM258, LM358 Package information 22 Figure 32. DFN8 2 x 2 footprint recommendation Ordering information LM158, LM258, LM358 20/22 DocID2163 Rev 11 7 Ordering information Table 9. Order codes Order code Temperature range Package Packaging Marking LM158N -55°C, +125°C DIP8 Tube LM158N LM158QT DFN8 2x2 Tape and reel K4A LM158DT SO8 158 LM258AN LM258N -40°C, +105°C DIP8 Tube LM258A LM258N LM258ADT SO8 Tape and reel 258A LM258AYDT(1) SO8 Automotive grade 258AY LM258D LM258DT SO8 Tube or tape and reel 258 Tape and reel LM258PT LM258APT TSSOP8 258 258A LM258YPT(2) LM258AYPT(2) TSSOP8 Automotive grade 258Y 258AY LM258AST LM258ST MiniSO8 K408 K416 LM258QT DFN8 2x2 K4C LM358N LM358AN 0°C, +70°C DIP8 Tube LM358N LM358AN LM358D LM358DT SO8 Tube or tape and reel 358 LM358YDT(1) SO8 Automotive grade Tape and reel 358Y LM358AD LM358ADT SO8 Tube or tape and reel 358A LM358PT LM358APT TSSOP8 Tape and reel 358 358A LM358YPT(2) LM358AYPT(2) TSSOP8 Automotive grade 358Y 358AY LM358ST LM358AST MiniSO8 K405 K404 LM358QT DFN8 2x2 K4E 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are qualified. 2. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are on-going. DocID2163 Rev 11 21/22 LM158, LM258, LM358 Revision history 22 8 Revision history Table 10. Document revision history Date Revision Changes 01-Jul- 2003 1 First release. 02-Jan-2005 2 Rthja and Tj parameters added in AMR Table 1 on page 4. 01-Jul-2005 3 ESD protection inserted in Table 1 on page 4. 05-Oct-2006 4 Added Figure 17: Phase margin vs. capacitive load. 30-Nov-2006 5 Added missing ordering information. 25-Apr-2007 6 Removed LM158A, LM258A and LM358A from document title. Corrected error in MiniSO-8 package data. L1 is 0.004 inch. Added automotive grade order codes in Section 7 on page 20. 12-Feb-2008 7 Corrected VCC max (30 V instead of 32 V) in operating conditions. Changed presentation of electrical characteristics table. Deleted Vopp parameter in electrical characteristics table. Corrected miniSO-8 package information. Corrected temperature range for automotive grade order codes. Updated automotive grade footnotes in order codes table. 26-Aug-2008 8 Added limitations on input current in Table 1: Absolute maximum ratings. Corrected title for Figure 11. Added E and L1 parameters in Table 5: SO8 package mechanical data. Changed Figure 30. 02-Sep-2011 9 In Chapter 6: Package information, added: – DFN8 2 x 2 mm package mechanical drawing – DFN8 2 x 2 mm recommended footprint – DFN8 2 x 2 mm order codes. 06-Apr-2012 10 Removed order codes LM158YD, LM258AYD, LM258YD and LM358YD from Table 9: Order codes. 11-Jun-2013 11 Table 9: Order codes: removed order codes LM158D, LM158YDT, LM258YDT, and LM258AD; added automotive grade qualification to order codes LM258ATDT and LM358YDT; updated marking for order codes LM158DT and LM258D/LM258DT; updated temperature range, packages, and packaging for several order codes. LM158, LM258, LM358 22/22 DocID2163 Rev 11 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com L78 Positive voltage regulator ICs Datasheet - production data Features • Output current up to 1.5 A • Output voltages of 5; 6; 8; 8.5; 9; 12; 15; 18; 24 V • Thermal overload protection • Short circuit protection • Output transition SOA protection • 2 % output voltage tolerance (A version) • Guaranteed in extended temperature range (A version) Description The L78 series of three-terminal positive regulators is available in TO-220, TO-220FP, D²PAK and DPAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type embeds internal current limiting, thermal shutdown and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltage and currents. TO-220 TO-220FP DPAK D²PAK www.st.com Contents Positive voltage regulator ICs 2/58 DocID2143 Rev 32 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Design consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DocID2143 Rev 32 3/58 Positive voltage regulator ICs List of tables 58 List of tables Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Electrical characteristics of L7805A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Electrical characteristics of L7806A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Electrical characteristics of L7808A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Electrical characteristics of L7809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Electrical characteristics of L7812A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Electrical characteristics of L7815A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Electrical characteristics of L7824A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. Electrical characteristics of L7805C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Electrical characteristics of L7806C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Electrical characteristics of L7808C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Electrical characteristics of L7885C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Electrical characteristics of L7809C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 15. Electrical characteristics of L7812C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. Electrical characteristics of L7815C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. Electrical characteristics of L7818C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. Electrical characteristics of L7824C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. TO-220 (dual gauge) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 20. TO-220 SG (single gauge) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. TO-220FP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22. DPAK mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 23. D²PAK (SMD 2L STD-ST) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24. D²PAK (SMD 2L Wooseok-subcon.) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 25. DPAK and D²PAK tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 26. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 List of figures Positive voltage regulator ICs 4/58 DocID2143 Rev 32 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. DC parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Ripple rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Fixed output regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Current regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Circuit for increasing output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. Adjustable output regulator (7 to 30 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12. 0.5 to 10 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. High current voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. High output current with short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 15. Tracking voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16. Split power supply (± 15 V - 1 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. Negative output voltage circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18. Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. High input voltage circuit (configuration 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 20. High input voltage circuit (configuration 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 21. High input and output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 22. Reducing power dissipation with dropping resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 23. Remote shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 24. Power AM modulator (unity voltage gain, IO £ 0.5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 25. Adjustable output voltage with temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 26. Light controllers (VO(min) = VXX + VBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 27. Protection against input short-circuit with high capacitance loads . . . . . . . . . . . . . . . . . . . 34 Figure 28. Dropout voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 29. Peak output current vs. input/output differential voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 30. Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 31. Output voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 32. Output impedance vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 33. Quiescent current vs. junction temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 34. Load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 35. Line transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 36. Quiescent current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 37. TO-220 (dual gauge) drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 38. TO-220 SG (single gauge) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 39. TO-220FP drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 40. DPAK drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 41. DPAK footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 42. D²PAK (SMD 2L STD-ST) type A drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 43. D²PAK (SMD 2L Wooseok-subcon.) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 44. D²PAK (SMD 2L Wooseok-subcon.) footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 45. Tube for TO-220 (dual gauge) (mm.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 46. Tube for TO-220 (single gauge) (mm.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 47. Tape for DPAK and D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 48. Reel for DPAK and D2PAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DocID2143 Rev 32 5/58 Positive voltage regulator ICs Diagram 58 1 Diagram Figure 1. Block diagram Pin configuration Positive voltage regulator ICs 6/58 DocID2143 Rev 32 2 Pin configuration Figure 2. Pin connections (top view) Figure 3. Schematic diagram DocID2143 Rev 32 7/58 Positive voltage regulator ICs Maximum ratings 58 3 Maximum ratings Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 1. Absolute maximum ratings Symbol Parameter Value Unit VI DC input voltage for VO= 5 to 18 V 35 V for VO= 20, 24 V 40 IO Output current Internally limited PD Power dissipation Internally limited TSTG Storage temperature range -65 to 150 °C TOP Operating junction temperature range for L78xxC, L78xxAC 0 to 125 °C for L78xxAB -40 to 125 Table 2. Thermal data Symbol Parameter D²PAK DPAK TO-220 TO-220FP Unit RthJC Thermal resistance junction-case 3 8 5 5 °C/W RthJA Thermal resistance junction-ambient 62.5 100 50 60 °C/W Figure 4. Application circuits Test circuits Positive voltage regulator ICs 8/58 DocID2143 Rev 32 4 Test circuits Figure 5. DC parameter Figure 6. Load regulation Figure 7. Ripple rejection DocID2143 Rev 32 9/58 Positive voltage regulator ICs Electrical characteristics 58 5 Electrical characteristics VI = 10 V, IO = 1 A, TJ = 0 to 125 °C (L7805AC), TJ = -40 to 125 °C (L7805AB), unless otherwise specified(a). a. Minimum load current for regulation is 5 mA. Table 3. Electrical characteristics of L7805A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 4.9 5 5.1 V VO Output voltage IO = 5 mA to 1 A, VI = 7.5 to 18 V 4.8 5 5.2 V VO Output voltage IO = 1 A, VI = 18 to 20 V, TJ = 25°C 4.8 5 5.2 V ΔVO (1) Line regulation VI = 7.5 to 25 V, IO = 500 mA, TJ = 25°C 7 50 mV VI = 8 to 12 V 10 50 mV VI = 8 to 12 V, TJ = 25°C 2 25 mV VI = 7.3 to 20 V, TJ = 25°C 7 50 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 8 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 8 to 23 V, IO = 500 mA 0.8 mA VI = 7.5 to 20 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 8 to 18 V, f = 120 Hz, IO = 500 mA 68 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1.1 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 10/58 DocID2143 Rev 32 VI = 11 V, IO = 1 A, TJ = 0 to 125 °C (L7806AC), TJ = -40 to 125 °C (L7806AB), unless otherwise specified(b). b. Minimum load current for regulation is 5 mA. Table 4. Electrical characteristics of L7806A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 5.88 6 6.12 V VO Output voltage IO = 5 mA to 1 A, VI = 8.6 to 19 V 5.76 6 6.24 V VO Output voltage IO = 1 A, VI = 19 to 21 V, TJ = 25°C 5.76 6 6.24 V ΔVO (1) Line regulation VI = 8.6 to 25 V, IO = 500 mA, TJ = 25°C 9 60 mV VI = 9 to 13 V 11 60 mV VI = 9 to 13 V, TJ = 25°C 3 30 mV VI = 8.3 to 21 V, TJ = 25°C 9 60 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 9 to 24 V, IO = 500 mA 0.8 mA VI = 8.6 to 21 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 9 to 19 V, f = 120 Hz, IO = 500 mA 65 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -0.8 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 11/58 Positive voltage regulator ICs Electrical characteristics 58 VI = 14 V, IO = 1 A, TJ = 0 to 125 °C (L7808AC), TJ = -40 to 125 °C (L7808AB), unless otherwise specified(c). c. Minimum load current for regulation is 5 mA. Table 5. Electrical characteristics of L7808A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 7.84 8 8.16 V VO Output voltage IO = 5 mA to 1 A, VI = 10.6 to 21 V 7.7 8 8.3 V VO Output voltage IO = 1 A, VI = 21 to 23 V, TJ = 25°C 7.7 8 8.3 V ΔVO (1) Line regulation VI = 10.6 to 25 V, IO = 500 mA, TJ = 25°C 12 80 mV VI = 11 to 17 V 15 80 mV VI = 11 to 17 V, TJ = 25°C 5 40 mV VI = 10.4 to 23 V, TJ = 25°C 12 80 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 11 to 23 V, IO = 500 mA 0.8 mA VI = 10.6 to 23 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 11.5 to 21.5 V, f = 120 Hz, IO = 500 mA 62 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -0.8 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 12/58 DocID2143 Rev 32 VI = 15 V, IO = 1 A, TJ = 0 to 125 °C (L7809AC), TJ = -40 to 125 °C (L7809AB), unless otherwise specified(d). d. Minimum load current for regulation is 5 mA. Table 6. Electrical characteristics of L7809A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 8.82 9 9.18 V VO Output voltage IO = 5 mA to 1 A, VI = 10.6 to 22 V 8.65 9 9.35 V VO Output voltage IO = 1 A, VI = 22 to 24 V, TJ = 25°C 8.65 9 9.35 V ΔVO (1) Line regulation VI = 10.6 to 25 V, IO = 500 mA, TJ = 25°C 12 90 mV VI = 11 to 17 V 15 90 mV VI = 11 to 17 V, TJ = 25°C 5 45 mV VI = 11.4 to 23 V, TJ = 25°C 12 90 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 11 to 25 V, IO = 500 mA 0.8 mA VI = 10.6 to 23 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 11.5 to 21.5 V, f = 120 Hz, IO = 500 mA 61 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -0.8 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 13/58 Positive voltage regulator ICs Electrical characteristics 58 VI = 19 V, IO = 1 A, TJ = 0 to 125 °C (L7812AC), TJ = -40 to 125 °C (L7812AB), unless otherwise specified(e). e. Minimum load current for regulation is 5 mA. Table 7. Electrical characteristics of L7812A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 11.75 12 12.25 V VO Output voltage IO = 5 mA to 1 A, VI = 14.8 to 25 V 11.5 12 12.5 V VO Output voltage IO = 1 A, VI = 25 to 27 V, TJ = 25°C 11.5 12 12.5 V ΔVO (1) Line regulation VI = 14.8 to 30 V, IO = 500 mA, TJ = 25°C 13 120 mV VI = 16 to 12 V 16 120 mV VI = 16 to 12 V, TJ = 25°C 6 60 mV VI = 14.5 to 27 V, TJ = 25°C 13 120 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.4 6 mA 6 mA ΔIq Quiescent current change VI = 15 to 30 V, IO = 500 mA 0.8 mA VI = 14.8 to 27 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 15 to 25 V, f = 120 Hz, IO = 500 mA 60 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B = 10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 14/58 DocID2143 Rev 32 VI = 23 V, IO = 1 A, TJ = 0 to 125 °C (L7815AC), TJ = -40 to 125 °C (L7815AB), unless otherwise specified(f). f. Minimum load current for regulation is 5 mA. Table 8. Electrical characteristics of L7815A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 14.7 15 15.3 V VO Output voltage IO = 5 mA to 1 A, VI = 17.9 to 28 V 14.4 15 15.6 V VO Output voltage IO = 1 A, VI = 28 to 30 V, TJ = 25°C 14.4 15 15.6 V ΔVO (1) Line regulation VI = 17.9 to 30 V, IO = 500 mA, TJ = 25°C 13 150 mV VI = 20 to 26 V 16 150 mV VI = 20 to 26 V, TJ = 25°C 6 75 mV VI = 17.5 to 30 V, TJ = 25°C 13 150 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.4 6 mA 6 mA ΔIq Quiescent current change VI = 17.5 to 30 V, IO = 500 mA 0.8 mA VI = 17.5 to 30 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 18.5 to 28.5 V, f = 120 Hz, IO = 500 mA 58 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B = 10Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 15/58 Positive voltage regulator ICs Electrical characteristics 58 VI = 33 V, IO = 1 A, TJ = 0 to 125 °C (L7824AC), TJ = -40 to 125 °C (L7824AB), unless otherwise specified(g). g. Minimum load current for regulation is 5 mA. Table 9. Electrical characteristics of L7824A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 23.5 24 24.5 V VO Output voltage IO = 5 mA to 1 A, VI = 27.3 to 37 V 23 24 25 V VO Output voltage IO = 1 A, VI = 37 to 38 V, TJ = 25°C 23 24 25 V ΔVO (1) Line regulation VI = 27 to 38 V, IO = 500 mA, TJ = 25°C 31 240 mV VI = 30 to 36 V 35 200 mV VI = 30 to 36 V, TJ = 25°C 14 120 mV VI = 26.7 to 38 V, TJ = 25°C 31 240 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.6 6 mA 6 mA ΔIq Quiescent current change VI = 27.3 to 38 V, IO = 500 mA 0.8 mA VI = 27.3 to 38 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 28 to 38 V, f = 120 Hz, IO = 500 mA 54 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B = 10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 20 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1.5 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 16/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 10 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(h). h. Minimum load current for regulation is 5 mA. Table 10. Electrical characteristics of L7805C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 4.8 5 5.2 V VO Output voltage IO = 5 mA to 1 A, VI = 7 to 18 V 4.75 5 5.25 V VO Output voltage IO = 1 A, VI = 18 to 20V, TJ = 25°C 4.75 5 5.25 V ΔVO (1) Line regulation VI = 7 to 25 V, TJ = 25°C 3 100 mV VI = 8 to 12 V, TJ = 25°C 1 50 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 100 mV IO = 250 to 750 mA, TJ = 25°C 50 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 7 to 23 V 0.8 ΔVO/ΔT Output voltage drift IO = 5 mA -1.1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 40 μV/VO SVR Supply voltage rejection VI = 8 to 18 V, f = 120 Hz 62 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.75 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 17/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 11 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(i). i. Minimum load current for regulation is 5 mA. Table 11. Electrical characteristics of L7806C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 5.75 6 6.25 V VO Output voltage IO = 5 mA to 1 A, VI = 8 to 19 V 5.7 6 6.3 V VO Output voltage IO = 1 A, VI = 19 to 21 V, TJ = 25°C 5.7 6 6.3 V ΔVO (1) Line regulation VI = 8 to 25 V, TJ = 25°C 120 mV VI = 9 to 13 V, TJ = 25°C 60 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 120 mV IO = 250 to 750 mA, TJ = 25°C 60 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 8 to 24 V 1.3 ΔVO/ΔT Output voltage drift IO = 5 mA -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 45 μV/VO SVR Supply voltage rejection VI = 9 to 19 V, f = 120 Hz 59 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.55 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 18/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 14 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(j). j. Minimum load current for regulation is 5 mA. Table 12. Electrical characteristics of L7808C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 7.7 8 8.3 V VO Output voltage IO = 5 mA to 1 A, VI = 10.5 to 21 V 7.6 8 8.4 V VO Output voltage IO = 1 A, VI = 21 to 25 V, TJ = 25°C 7.6 8 8.4 V ΔVO (1) Line regulation VI = 10.5 to 25 V, TJ = 25°C 160 mV VI = 11 to 17 V, TJ = 25°C 80 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 160 mV IO = 250 to 750 mA, TJ = 25°C 80 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 10.5 to 25 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 52 μV/VO SVR Supply voltage rejection VI = 11.5 to 21.5 V, f = 120 Hz 56 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 16 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.45 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 19/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 14.5 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(k). k. Minimum load current for regulation is 5 mA. Table 13. Electrical characteristics of L7885C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 8.2 8.5 8.8 V VO Output voltage IO = 5 mA to 1 A, VI = 11 to 21.5 V 8.1 8.5 8.9 V VO Output voltage IO = 1 A, VI = 21.5 to 26 V, TJ = 25°C 8.1 8.5 8.9 V ΔVO (1) Line regulation VI = 11 to 27 V, TJ = 25°C 160 mV VI = 11.5 to 17.5 V, TJ = 25°C 80 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 160 mV IO = 250 to 750 mA, TJ = 25°C 80 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 11 to 26 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 55 μV/VO SVR Supply voltage rejection VI = 12 to 22 V, f = 120 Hz 56 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 16 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.45 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 20/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 15 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(l). l. Minimum load current for regulation is 5 mA. Table 14. Electrical characteristics of L7809C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 8.64 9 9.36 V VO Output voltage IO = 5 mA to 1 A, VI = 11.5 to 22 V 8.55 9 9.45 V VO Output voltage IO = 1 A, VI = 22 to 26 V, TJ = 25°C 8.55 9 9.45 V ΔVO (1) Line regulation VI = 11.5 to 26 V, TJ = 25°C 180 mV VI = 12 to 18 V, TJ = 25°C 90 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 180 mV IO = 250 to 750 mA, TJ = 25°C 90 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 11.5 to 26 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 70 μV/VO SVR Supply voltage rejection VI = 12 to 23 V, f = 120 Hz 55 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.40 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 21/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 19 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(m). m. Minimum load current for regulation is 5 mA. Table 15. Electrical characteristics of L7812C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 11.5 12 12.5 V VO Output voltage IO = 5 mA to 1 A, VI = 14.5 to 25 V 11.4 12 12.6 V VO Output voltage IO = 1 A, VI = 25 to 27 V, TJ = 25°C 11.4 12 12.6 V ΔVO (1) Line regulation VI = 14.5 to 30 V, TJ = 25°C 240 mV VI = 16 to 22 V, TJ = 25°C 120 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 240 mV IO = 250 to 750 mA, TJ = 25°C 120 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 14.5 to 30 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 75 μV/VO SVR Supply voltage rejection VI = 15 to 25 V, f = 120 Hz 55 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.35 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 22/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 23 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(n). n. Minimum load current for regulation is 5 mA. Table 16. Electrical characteristics of L7815C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 14.4 15 15.6 V VO Output voltage IO = 5 mA to 1 A, VI = 17.5 to 28 V 14.25 15 15.75 V VO Output voltage IO = 1 A, VI = 28 to 30 V, TJ = 25°C 14.25 15 15.75 V ΔVO (1) Line regulation VI = 17.5 to 30 V, TJ = 25°C 300 mV VI = 20 to 26 V, TJ = 25°C 150 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 300 mV IO = 250 to 750 mA, TJ = 25°C 150 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1A 0.5 mA VI = 17.5 to 30 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100kHz, TJ = 25°C 90 μV/VO SVR Supply voltage rejection VI = 18.5 to 28.5 V, f = 120 Hz 54 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.23 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 23/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 26 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(o). o. Minimum load current for regulation is 5 mA. Table 17. Electrical characteristics of L7818C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 17.3 18 18.7 V VO Output voltage IO = 5 mA to 1 A, VI = 21 to 31 V 17.1 18 18.9 V VO Output voltage IO = 1 A, VI = 31 to 33 V, TJ = 25°C 17.1 18 18.9 V ΔVO (1) Line regulation VI = 21 to 33 V, TJ = 25°C 360 mV VI = 24 to 30 V, TJ = 25°C 180 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 360 mV IO = 250 to 750 mA, TJ = 25°C 180 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 21 to 33 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 110 μV/VO SVR Supply voltage rejection VI = 22 to 32 V, f = 120 Hz 53 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 22 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.20 A Iscp Short circuit peak current TJ = 25°C 2.1 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 24/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 33 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(p). p. Minimum load current for regulation is 5 mA. Table 18. Electrical characteristics of L7824C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 23 24 25 V VO Output voltage IO = 5 mA to 1 A, VI = 27 to 37 V 22.8 24 25.2 V VO Output voltage IO = 1 A, VI = 37 to 38 V, TJ = 25°C 22.8 24 25.2 V ΔVO (1) Line regulation VI = 27 to 38 V, TJ = 25°C 480 mV VI = 30 to 36 V, TJ = 25°C 240 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 480 mV IO = 250 to 750 mA, TJ = 25°C 240 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 27 to 38 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1.5 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 170 μV/VO SVR Supply voltage rejection VI = 28 to 38 V, f = 120 Hz 50 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 28 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.15 A Iscp Short circuit peak current TJ = 25°C 2.1 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 25/58 Positive voltage regulator ICs Application information 58 6 Application information 6.1 Design consideration The L78 Series of fixed voltage regulators are designed with thermal overload protection that shuts down the circuit when subjected to an excessive power overload condition, internal short-circuit protection that limits the maximum current the circuit will pass, and output transistor safe-area compensation that reduces the output short-circuit current as the voltage across the pass transistor is increased. In many low current applications, compensation capacitors are not required. However, it is recommended that the regulator input be bypassed with capacitor if the regulator is connected to the power supply filter with long lengths, or if the output load capacitance is large. An input bypass capacitor should be selected to provide good high frequency characteristics to insure stable operation under all load conditions. A 0.33 μF or larger tantalum, mylar or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with the shortest possible leads directly across the regulators input terminals. Normally good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator has no external sense lead. The addition of an operational amplifier allows adjustment to higher or intermediate values while retaining regulation characteristics. The minimum voltage obtained with the arrangement is 2 V greater than the regulator voltage. The circuit of Figure 13 can be modified to provide supply protection against short circuit by adding a short circuit sense resistor, RSC, and an additional PNP transistor. The current sensing PNP must be able to handle the short circuit current of the three terminal regulator Therefore a four ampere plastic power transistor is specified. Figure 8. Fixed output regulator 1. Although no output capacitor is need for stability, it does improve transient response. 2. Required if regulator is located an appreciable distance from power supply filter. Application information Positive voltage regulator ICs 26/58 DocID2143 Rev 32 Figure 9. Current regulator Figure 10. Circuit for increasing output voltage DocID2143 Rev 32 27/58 Positive voltage regulator ICs Application information 58 Figure 11. Adjustable output regulator (7 to 30 V) Figure 12. 0.5 to 10 V regulator VO=VXXR4/R1 Application information Positive voltage regulator ICs 28/58 DocID2143 Rev 32 Figure 13. High current voltage regulator Figure 14. High output current with short circuit protection DocID2143 Rev 32 29/58 Positive voltage regulator ICs Application information 58 * Against potential latch-up problems. Figure 15. Tracking voltage regulator Figure 16. Split power supply (± 15 V - 1 A) Application information Positive voltage regulator ICs 30/58 DocID2143 Rev 32 Figure 17. Negative output voltage circuit Figure 18. Switching regulator Figure 19. High input voltage circuit (configuration 1) DocID2143 Rev 32 31/58 Positive voltage regulator ICs Application information 58 Figure 20. High input voltage circuit (configuration 2) Figure 21. High input and output voltage Figure 22. Reducing power dissipation with dropping resistor Application information Positive voltage regulator ICs 32/58 DocID2143 Rev 32 Note: The circuit performs well up to 100 kHz. Figure 23. Remote shutdown Figure 24. Power AM modulator (unity voltage gain, IO ≤ 0.5) DocID2143 Rev 32 33/58 Positive voltage regulator ICs Application information 58 Note: Q2 is connected as a diode in order to compensate the variation of the Q1 VBE with the temperature. C allows a slow rise time of the VO. Figure 25. Adjustable output voltage with temperature compensation Figure 26. Light controllers (VO(min) = VXX + VBE) Application information Positive voltage regulator ICs 34/58 DocID2143 Rev 32 Note: Application with high capacitance loads and an output voltage greater than 6 volts need an external diode (see Figure 22 on page 31) to protect the device against input short circuit. In this case the input voltage falls rapidly while the output voltage decrease slowly. The capacitance discharges by means of the base-emitter junction of the series pass transistor in the regulator. If the energy is sufficiently high, the transistor may be destroyed. The external diode by-passes the current from the IC to ground. Figure 27. Protection against input short-circuit with high capacitance loads DocID2143 Rev 32 35/58 Positive voltage regulator ICs Typical performance 58 7 Typical performance Figure 28. Dropout voltage vs. junction temperature Figure 29. Peak output current vs. input/output differential voltage Figure 30. Supply voltage rejection vs. frequency Figure 31. Output voltage vs. junction temperature Typical performance Positive voltage regulator ICs 36/58 DocID2143 Rev 32 Figure 32. Output impedance vs. frequency Figure 33. Quiescent current vs. junction temp. Figure 34. Load transient response Figure 35. Line transient response Figure 36. Quiescent current vs. input voltage DocID2143 Rev 32 37/58 Positive voltage regulator ICs Package mechanical data 58 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Package mechanical data Positive voltage regulator ICs 38/58 DocID2143 Rev 32 Figure 37. TO-220 (dual gauge) drawing DocID2143 Rev 32 39/58 Positive voltage regulator ICs Package mechanical data 58 Table 19. TO-220 (dual gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 Package mechanical data Positive voltage regulator ICs 40/58 DocID2143 Rev 32 Figure 38. TO-220 SG (single gauge) drawing DocID2143 Rev 32 41/58 Positive voltage regulator ICs Package mechanical data 58 Table 20. TO-220 SG (single gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 0.51 0.60 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 Package mechanical data Positive voltage regulator ICs 42/58 DocID2143 Rev 32 Figure 39. TO-220FP drawing 7012510A-H DocID2143 Rev 32 43/58 Positive voltage regulator ICs Package mechanical data 58 Table 21. TO-220FP mechanical data Dim. mm. Min. Typ. Max. A 4.40 4.60 B 2.5 2.7 D 2.5 2.75 E 0.45 0.70 F 0.75 1 F1 1.15 1.50 F2 1.15 1.50 G 4.95 5.2 G1 2.4 2.7 H 10.0 10.40 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 DIA. 3 3.2 Package mechanical data Positive voltage regulator ICs 44/58 DocID2143 Rev 32 Figure 40. DPAK drawing 0068772_K DocID2143 Rev 32 45/58 Positive voltage regulator ICs Package mechanical data 58 Table 22. DPAK mechanical data Dim. mm Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 5.10 E 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.80 L2 0.80 L4 0.60 1.00 R 0.20 V2 0° 8° Package mechanical data Positive voltage regulator ICs 46/58 DocID2143 Rev 32 Figure 41. DPAK footprint (q) q. All dimensions are in millimeters Footprint_REV_K DocID2143 Rev 32 47/58 Positive voltage regulator ICs Package mechanical data 58 Figure 42. D²PAK (SMD 2L STD-ST) type A drawing 0079457_T Package mechanical data Positive voltage regulator ICs 48/58 DocID2143 Rev 32 Table 23. D²PAK (SMD 2L STD-ST) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R 0.4 V2 0° 8° DocID2143 Rev 32 49/58 Positive voltage regulator ICs Package mechanical data 58 Figure 43. D²PAK (SMD 2L Wooseok-subcon.) drawing 0079457_T Package mechanical data Positive voltage regulator ICs 50/58 DocID2143 Rev 32 Table 24. D²PAK (SMD 2L Wooseok-subcon.) mechanical data Dim. mm Min. Typ. Max. A 4.30 4.70 A1 0 0.20 b 0.70 0.90 b2 1.17 1.37 c 0.45 0.50 0.60 c2 1.25 1.30 1.40 D 9 9.20 9.40 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.08 H 15 15.30 J1 2.20 2.60 L 1.79 2.79 L1 1 1.40 L2 1.20 1.60 R 0.30 V2 0° 3° DocID2143 Rev 32 51/58 Positive voltage regulator ICs Package mechanical data 58 Figure 44. D²PAK (SMD 2L Wooseok-subcon.) footprint Packaging mechanical data Positive voltage regulator ICs 52/58 DocID2143 Rev 32 9 Packaging mechanical data Figure 45. Tube for TO-220 (dual gauge) (mm.) Figure 46. Tube for TO-220 (single gauge) (mm.) DocID2143 Rev 32 53/58 Positive voltage regulator ICs Packaging mechanical data 58 Figure 47. Tape for DPAK and D2PAK Figure 48. Reel for DPAK and D2PAK A0 P1 D1 P0 F W E D B0 K0 T User direction of feed P2 10 pitches cumulative tolerance on tape +/- 0.2 mm User direction of feed R Bending radius B1 For machine ref. only including draft and radii concentric around B0 AM08852v1 Top cover tape A D B Full radius G measured at hub C N REEL DIMENSIONS 40mm min. Access hole At sl ot location T Tape slot in core for tape start 25 mm min. width AM08851v2 Packaging mechanical data Positive voltage regulator ICs 54/58 DocID2143 Rev 32 Table 25. DPAK and D²PAK tape and reel mechanical data Tape Reel Dim. mm Dim. mm Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 B1 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID2143 Rev 32 55/58 Positive voltage regulator ICs Order codes 58 10 Order codes Table 26. Order codes Part numbers Order codes TO-220 (single gauge) TO-220 (dual gauge) DPAK D²PAK TO-220FP Output voltages L7805C L7805CV L7805CDT-TR L7805CD2T-TR L7805CP 5 V L7805CV-DG 5 V L7805AB L7805ABV L7805ABD2T-TR L7805ABP 5 V L7805ABV-DG 5 V L7805AC L7805ACV L7805ACD2T-TR L7805ACP 5 V L7805ACV-DG 5 V L7806C L7806CV L7806CD2T-TR 6 V L7806CV-DG 6 V L7806AB L7806ABV L7806ABD2T-TR 6 V L7806ABV-DG 6 V L7806AC L7806ACV 6 V L7806ACV-DG 6 V L7808C L7808CV L7808CD2T-TR 8 V L7808CV-DG 8 V L7808AB L7808ABV L7808ABD2T-TR 8 V L7808ABV-DG 8 V L7808AC L7808ACV 8 V L7808ACV-DG 8 V L7885C L7885CV 8.5 V L7809C L7809CV L7809CD2T-TR L7809CP 9 V L7809CV-DG 9 V L7809AB L7809ABV L7809ABD2T-TR 9 V L7809ABV-DG 9 V L7809AC L7809ACV 9 V L7812C L7812CV L7812CD2T-TR L7812CP 12 V L7812CV-DG 12 V L7812AB L7812ABV L7812ABD2T-TR 12 V L7812ABV-DG 12 V L7812AC L7812ACV L7812ACD2T-TR 12 V L7812ACV-DG 12 V Order codes Positive voltage regulator ICs 56/58 DocID2143 Rev 32 L7815C L7815CV L7815CD2T-TR L7815CP 15 V L7815CV-DG 15 V L7815AB L7815ABV L7815ABD2T-TR 15 V L7815ABV-DG 15 V L7815AC L7815ACV L7815ACD2T-TR 15 V L7815ACV-DG 15 V L7818C L7818CV 18 V L7818CV-DG 18 V L7824C L7824CV L7824CD2T-TR L7824CP 24 V L7824CV-DG 24 V L7824AB L7824ABV 24 V L7824ABV-DG 24 V L7824AC L7824ACV 24 V L7824ACV-DG 24 V Table 26. Order codes (continued) Part numbers Order codes TO-220 (single gauge) TO-220 (dual gauge) DPAK D²PAK TO-220FP Output voltages DocID2143 Rev 32 57/58 Positive voltage regulator ICs Revision history 58 11 Revision history Table 27. Document revision history Date Revision Changes 21-Jun-2004 12 Document updating. 03-Aug-2006 13 Order codes has been updated and new template. 19-Jan-2007 14 D²PAK mechanical data has been updated and add footprint data. 31-May-2007 15 Order codes has been updated. 29-Aug-2007 16 Added Table 1 in cover page. 11-Dec-2007 17 Modified: Table 26. 06-Feb-2008 18 Added: TO-220 mechanical data Figure 38 on page 38 , Figure 39 on page 39, and Table 23 on page 37. Modified: Table 26 on page 55. 18-Mar-2008 19 Added: Table 29: DPAK mechanical data on page 50, Table 30: Tape and reel DPAK mechanical data on page 52. Modified: Table 26 on page 55. 26-Jan-2010 20 Modified Table 1 on page 1 and Table 23 on page 37, added: Figure 38 on page 38 and Figure 39 on page 39, Figure 45 on page 52 and Figure 46 on page 52. 04-Mar-2010 21 Added notes Figure 38 on page 38. 08-Sep-2010 22 Modified Table 26 on page 55. 23-Nov-2010 23 Added: TJ = 25 °C test condition in ΔVO on Table 3, 4, 5, 6, 7, 8 and Table 9. 16-Sep-2011 24 Modified title on page 1. 30-Nov-2011 25 Added: order codes L7805CV-DG, L7806CV-DG, L7808ABV-DG, L7812CV-DG and L7815CV-DG Table 26 on page 55. 08-Feb-2012 26 Added: order codes L7805ACV-DG, L7805ABV-DG, L7806ABV-DG, L7808CVDG, L7809CV-DG, L7812ACV-DG, L7818CV-DG, L7824CV-DG Table 26 on page 55. 27-Mar-2012 27 Added: order codes L7812ABV-DG, L7815ABV-DG Table 26 on page 55. 27-Apr-2012 28 Modified: VI = 10.4 to 23 V ==> VI = 11.4 to 23 V test conditon value Line regulation Table 6 on page 12. 10-May-2012 29 Added: order codes L7806ACV-DG, L7808ACV-DG, L7815ACV-DG, L7824ABV-DG and L7824ACV-DG Table 26 on page 55. 19-Sep-2012 30 Modified load regulation units from V to mV in Table 3 to Table 9. 12-Mar-2013 31 Modified: VO output voltage at 25 °C min. value 14.4 V Table 16 on page 22. 04-Mar-2014 32 Part numbers L78xx, L78xxC, L78xxAB, L78xxAC changed to L78. Removed TO-3 package. Updated the description in cover page, Section 2: Pin configuration, Section 3: Maximum ratings, Section 4: Test circuits, Section 5: Electrical characteristics, Section 6: Application information, Section 8: Package mechanical data and Table 26: Order codes. Added Section 9: Packaging mechanical data. Minor text changes. Positive voltage regulator ICs 58/58 DocID2143 Rev 32 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of Flash memory – Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM – Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) FBGA UFBGA176 (10 × 10 mm) LQFP176 (24 × 24 mm) WLCSP90 Table 1. Device summary Reference Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE www.st.com Contents STM32F405xx, STM32F407xx 2/185 DocID022152 Rev 4 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 28 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 33 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID022152 Rev 4 3/185 STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 80 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 80 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 80 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 102 Contents STM32F405xx, STM32F407xx 4/185 DocID022152 Rev 4 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 155 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 156 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 171 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 173 A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID022152 Rev 4 5/185 STM32F405xx, STM32F407xx List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 Table 3. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 7. STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 10. STM32F40x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 79 Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 80 Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 83 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 88 Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 89 Table 26. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 31. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 33. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 35. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 36. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 37. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 39. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 40. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 41. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 42. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 43. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 44. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 45. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 46. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 List of tables STM32F405xx, STM32F407xx 6/185 DocID022152 Rev 4 Table 47. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 48. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 49. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 50. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 51. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 52. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 53. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 55. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 56. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 57. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 58. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 59. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 61. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 62. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 63. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 64. Dynamic characteristics: Ehternet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 65. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 66. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 70. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 71. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 72. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 73. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 74. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 138 Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 139 Table 77. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 78. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 80. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 85. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 86. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 87. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 88. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 89. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 159 Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 160 Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 162 Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 164 Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 167 DocID022152 Rev 4 7/185 STM32F405xx, STM32F407xx List of tables Table 96. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 97. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 98. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 List of figures STM32F405xx, STM32F407xx 8/185 DocID022152 Rev 4 List of figures Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64. . . . . . . . . . . . 15 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. STM32F40x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24 Figure 8. PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12. STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 13. STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15. STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 16. STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 17. STM32F40x WLCSP90 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18. STM32F40x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 85 Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 85 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 86 Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 86 Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 89 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 90 Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 39. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DocID022152 Rev 4 9/185 STM32F405xx, STM32F407xx List of figures Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 44. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 124 Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 133 Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 133 Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138 Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 139 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 148 Figure 64. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 148 Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 150 Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 151 Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 154 Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154 Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 75. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 159 Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 160 Figure 78. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 162 Figure 80. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 164 Figure 82. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 167 Figure 85. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 87. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 171 List of figures STM32F405xx, STM32F407xx 10/185 DocID022152 Rev 4 Figure 88. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172 Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 90. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 91. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 92. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DocID022152 Rev 4 11/185 STM32F405xx, STM32F407xx Introduction 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming manual (PM0214) available from www.st.com. Description STM32F405xx, STM32F407xx 12/185 DocID022152 Rev 4 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. • Up to three I2Cs • Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus two UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • An SDIO/MMC interface • Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances STM32F405xx, STM32F407xx Description DocID022152 Rev 4 13/185 Figure 5 shows the general block diagram of the device family. Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix Flash memory in Kbytes 1024 512 512 1024 512 1024 512 1024 SRAM in Kbytes System 192(112+16+64) Backup 4 FSMC memory controller No Yes(1) Ethernet No Yes Timers Generalpurpose 10 Advanced -control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Description STM32F405xx, STM32F407xx 14/185 DocID022152 Rev 4 Communi cation interfaces SPI / I2S 3/2 (full duplex)(2) I2C 3 USART/ UART 4/2 USB OTG FS Yes USB OTG HS Yes CAN 2 SDIO Yes Camera interface No Yes GPIOs 51 72 82 114 72 82 114 140 12-bit ADC Number of channels 3 16 13 16 24 13 16 24 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz Operating voltage 1.8 to 3.6 V(3) Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Package LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix DocID022152 Rev 4 15/185 STM32F405xx, STM32F407xx Description 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto- pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 31 1 16 17 32 48 33 64 49 47 VSS VSS VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration ai18489 Description STM32F405xx, STM32F407xx 16/185 DocID022152 Rev 4 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 20 49 1 25 26 50 75 51 100 76 73 19 VSS VSS VDD VSS VSS VSS 0 ΩΩ resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration ai18488c 99 (VSS) VDD VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VSS for the STM32F4xx VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx ai18487d 31 71 1 36 37 72 108 73 144 109 VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 106 VSS 30 Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VDD or signal from external power supply supervisor for the STM32F4xx VDD VSS VSS VSS 143 (PDR_ON) VDD VSS VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx Signal from external power supply supervisor DocID022152 Rev 4 17/185 STM32F405xx, STM32F407xx Description Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages MS19919V3 1 44 45 88 132 89 176 133 Two 0 Ω resistors connected to: - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx 171 (PDR_ON) VDDVSS Signal from external power supply supervisor Description STM32F405xx, STM32F407xx 18/185 DocID022152 Rev 4 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The camera interface and ethernet are available only on STM32F407xx devices. MS19920V3 GPIO PORT A AHB/APB2 140 AF PA[15:0] TIM1 / PWM 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF RX, TX, CK, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF APB 1 30M Hz 8 analog inputs common to the 3 ADCs VDDREF_ADC MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX DAC1_OUT as AF ITF WWDG 4 KB BKPSRAM RTC_AF1 OSC32_IN OSC32_OUT VDDA, VSSA NRST 16b SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA2 SCL, SDA, SMBA as AF JTAG & SW ARM Cortex-M4 168 MHz ETM NVIC MPU TRACECLK TRACED[3:0] Ethernet MAC 10/100 DMA/ FIFO MII or RMII as AF MDIO as AF USB OTG HS DP, DM ULPI:CK, D[7:0], DIR, STP, NXT ID, VBUS, SOF DMA2 8 Streams FIFO ART ACCEL/ CACHE SRAM 112 KB CLK, NE [3:0], A[23:0], D[31:0], OEN, WEN, NBL[3:0], NL, NREG, NWAIT/IORDY, CD INTN, NIIS16 as AF RNG Camera interface HSYNC, VSYNC PUIXCLK, D[13:0] PHY USB OTG FS DP DM ID, VBUS, SOF FIFO AHB1 168 MHz PHY FIFO @VDDA @VDDA POR/PDR BOR Supply supervision @VDDA PVD Int POR reset XTAL 32 kHz MAN AGT RTC RC HS FCLK RC LS PWR interface IWDG @VBAT AWU Reset & clock control P L L1&2 PCLKx VDD = 1.8 to 3.6 V VSS VCAP1, VCPA2 Voltage regulator 3.3 to 1.2 V VDD Power managmt Backup register RTC_AF1 AHB bus-matrix 8S7M LS 2 channels as AF DAC1 DAC2 Flash up to 1 MB SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash External memory controller (FSMC) TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 SP3/I2S3 I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS bxCAN1 bxCAN2 SPI1 EXT IT. WKUP D-BUS FIFO FPU APB142 MHz (max) SRAM 16 KB CCM data RAM 64 KB AHB3 AHB2 168 MHz NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO I-BUS S-BUS DMA/ FIFO DMA1 8 Streams FIFO PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I TIM8 / PWM 16b 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 DAC2_OUT as AF 16b 16b SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX RX, TX as AF RX, TX as AF RX, TX as AF CTS, RTS as AF RX, TX as AF CTS, RTS as AF 1 channel as AF smcard irDA smcard irDA 16b 16b 16b 1 channel as AF 2 channels as AF 32b 16b 16b 32b 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF DMA1 AHB/APB1 LS OSC_IN OSC_OUT HCLKx XTAL OSC 4- 16MHz FIFO SP2/I2S2 NIORD, IOWR, INT[2:3] ADC3 ADC2 ADC1 Temperature sensor IF TIM9 16b TIM10 16b TIM11 16b smcard irDA USART1 irDA smcard USART6 APB2 84 MHz @VDD @VDD @VDDA DocID022152 Rev 4 19/185 STM32F405xx, STM32F407xx Description 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. Note: Cortex-M4F is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. Description STM32F405xx, STM32F407xx 20/185 DocID022152 Rev 4 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40x products embed: • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DocID022152 Rev 4 21/185 STM32F405xx, STM32F407xx Description Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S S0 S1 S2 S3 S4 S5 S6 S7 ICODE DCODE ACCEL Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB1 peripherals AHB2 FSMC Static MemCtl M0 M1 M2 M3 M4 M5 M6 I-bus D-bus S-bus DMA_PI DMA_MEM1 DMA_MEM2 DMA_P2 ETHERNET_M USB_HS_M ai18490c CCM data RAM 64-Kbyte APB1 APB2 peripherals Description STM32F405xx, STM32F407xx 22/185 DocID022152 Rev 4 2.2.9 Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL DocID022152 Rev 4 23/185 STM32F405xx, STM32F407xx Description clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 21: Power supply scheme for more details. Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Refer to Table 2 in order to identify the packages supporting this option. 2.2.15 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. Description STM32F405xx, STM32F407xx 24/185 DocID022152 Rev 4 The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. Figure 7. Power supply supervisor interconnection with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal. MS31383V3 NRST VDD PDR_ON External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V or 1.8 V (1) VDD Application reset signal (optional) DocID022152 Rev 4 25/185 STM32F405xx, STM32F407xx Description Figure 8. PDR_ON and NRST control with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.16 Voltage regulator The regulator has four operating modes: • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down • Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost) MS19009V6 VDD time PDR = 1.7 V or 1.8 V (1) time NRST PDR_ON PDR_ON Reset by other source than power supply supervisor Description STM32F405xx, STM32F407xx 26/185 DocID022152 Rev 4 Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 21: Power supply scheme When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. Figure 9. Regulator OFF ai18498V4 External VCAP_1/2 power supply supervisor Ext. reset controller active when VCAP_1/2 < Min V12 V12 VCAP_1 VCAP_2 BYPASS_REG VDD PA0 NRST Application reset signal (optional) VDD V12 DocID022152 Rev 4 27/185 STM32F405xx, STM32F407xx Description The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 14: General operating conditions). Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or OFFoff). 2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges. ai18491e VDD time Min V12 PDR = 1.7 V or 1.8 V (2) VCAP_1/VCAP_2 V12 NRST time Description STM32F405xx, STM32F407xx 28/185 DocID022152 Rev 4 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or offOFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability 2.2.18 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC VDD time Min V12 VCAP_1/VCAP_2 V12 PA0 asserted externally NRST time ai18492d PDR = 1.7 V or 1.8 V (2) Table 3. Regulator ON/OFF and internal reset ON/OFF availability Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP64 LQFP100 Yes No Yes No LQFP144 LQFP176 Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor WLCSP90 UFBGA176 Yes BYPASS_REG set to VSS Yes BYPASS_REG set to VDD DocID022152 Rev 4 29/185 STM32F405xx, STM32F407xx Description has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 μs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 2.2.19 Low-power modes The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V12 domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Description STM32F405xx, STM32F407xx 30/185 DocID022152 Rev 4 Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.20 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 2.2.21 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Advanced -control TIM1, TIM8 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 Yes 84 168 DocID022152 Rev 4 31/185 STM32F405xx, STM32F407xx Description Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. General purpose TIM2, TIM5 32-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM3, TIM4 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 84 168 TIM10 , TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 84 168 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 42 84 TIM13 , TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 42 84 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 42 84 Table 4. Timer feature comparison (continued) Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Description STM32F405xx, STM32F407xx 32/185 DocID022152 Rev 4 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. DocID022152 Rev 4 33/185 STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. 2.2.22 Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Description STM32F405xx, STM32F407xx 34/185 DocID022152 Rev 4 2.2.24 Serial peripheral interface (SPI) The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.25 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.2.26 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. Table 5. USART feature comparison USART name Standard features Modem (RTS/ CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s (oversampling by 16) Max. baud rate in Mbit/s (oversampling by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) USART6 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) DocID022152 Rev 4 35/185 STM32F405xx, STM32F407xx Description The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.27 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F407xx devices. The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx. The STM32F407xx includes the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time Description STM32F405xx, STM32F407xx 36/185 DocID022152 Rev 4 2.2.29 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID022152 Rev 4 37/185 STM32F405xx, STM32F407xx Description 2.2.32 Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image 2.2.33 Random number generator (RNG) All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. 2.2.35 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally Description STM32F405xx, STM32F407xx 38/185 DocID022152 Rev 4 connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.37 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.39 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40x through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID022152 Rev 4 39/185 STM32F405xx, STM32F407xx Pinouts and pin description 3 Pinouts and pin description Figure 12. STM32F40x LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14 PC15 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai18493b PC13 PH0 PH1 VSS Pinouts and pin description STM32F405xx, STM32F407xx 40/185 DocID022152 Rev 4 Figure 13. STM32F40x LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 PE3 PE4 PE5 PE6 VBAT PC14 PC15 VSS VDD PH0 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 VDD VSS VCAP_2 PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai18495c LQFP100 PC13 PH1 DocID022152 Rev 4 41/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 14. STM32F40x LQFP144 pinout VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 VDD PE3 VSS PE4 PE5 PA13 PE6 PA12 VBAT PA11 PC13 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 VDD PF5 VSS VSS PG8 VDD PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST VDD PC0 VSS PC1 PD13 PC2 PD12 PC3 PD11 VSSA VDD PD10 PD9 VREF+ PD8 VDDA PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 LQFP144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai18496b VCAP_2 VSS Pinouts and pin description STM32F405xx, STM32F407xx 42/185 DocID022152 Rev 4 Figure 15. STM32F40x LQFP176 pinout MS19916V3 PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PI7 PI6 PE2 PE3 PE4 PE5 PA13 PE6 PA12 VBAT PA11 PI8 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 PF5 PG8 PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST V PC0 V PC1 PD13 PC2 PD12 PC3 PD11 PD10 PD9 VREF+ PD8 PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 LQFP176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 PI4 PA15 PA14 PI3 PI2 PI5 140 139 138 137 136 135 134 133 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 88 81 82 83 84 85 86 87 PI1 PI0 PH15 PH14 PH13 PH12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 PC13 PI9 PI10 PI11 VSS PH2 PH3 VDD VSS VDD VDDA VSSA VDDA BYPASS_REG VDD VDD VSS VDD VCAP_1 VDD VSS VDD VCAP_2 VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD DocID022152 Rev 4 43/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 16. STM32F40x UFBGA176 ballout 1. This figure shows the package top view. ai18497b 1 2 3 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 VSS 4 5 6 7 8 Pinouts and pin description STM32F405xx, STM32F407xx 44/185 DocID022152 Rev 4 Figure 17. STM32F40x WLCSP90 ballout 1. This figure shows the package bump view. A VBAT PC13 PDR_ON PB4 PD7 PD4 PC12 B PC15 VDD PB7 PB3 PD6 PD2 PA15 C PA0 VSS PB6 PD5 PD1 PC11 PI0 D PC2 PB8 PA13 E PC3 VSS F PH1 PA1 G NRST H VSSA J PA2 PA 4 PA7 PB2 PE11 PB11 PB12 MS30402V1 1 PA14 PI1 PA12 PA10 PA9 PC0 PC9 PC8 PH0 PB13 PC6 PD14 PD12 PE8 PE12 BYPASS_ REG PD9 PD8 PE9 PB14 10 9 8 7 6 5 4 3 2 VDD PC14 VCAP_2 PA11 PB5 PD0 PC10 PA8 VSS VDD VSS VDD PC7 VDD PE10 PE14 VCAP_1 PD15 PE13 PE15 PD10 PD11 PA3 PA6 PB1 PB10 PB15 PB9 BOOT0 VDDA PA5 PB0 PE7 Table 6. Legend/abbreviations used in the pinout table Name Abbreviation Definition Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I/O Input / output pin I/O structure FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DocID022152 Rev 4 45/185 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 - - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 A10 6 6 C1 6 VBAT S - - - - D2 7 PI8 I/O FT (2)( 3) EVENTOUT RTC_TAMP1, RTC_TAMP2, RTC_TS 2 A9 7 7 D1 8 PC13 I/O FT (2) (3) EVENTOUT RTC_OUT, RTC_TAMP1, RTC_TS 3 B10 8 8 E1 9 PC14/OSC32_IN (PC14) I/O FT (2)( 3) EVENTOUT OSC32_IN(4) 4 B9 9 9 F1 10 PC15/ OSC32_OUT (PC15) I/O FT (2)( 3) EVENTOUT OSC32_OUT(4) - - - - D3 11 PI9 I/O FT CAN1_RX / EVENTOUT - - - - E3 12 PI10 I/O FT ETH_MII_RX_ER / EVENTOUT - - - - E4 13 PI11 I/O FT OTG_HS_ULPI_DIR / EVENTOUT - - - - F2 14 VSS S - - - - F3 15 VDD S - - - 10 E2 16 PF0 I/O FT FSMC_A0 / I2C2_SDA / EVENTOUT Pinouts and pin description STM32F405xx, STM32F407xx 46/185 DocID022152 Rev 4 - - - 11 H3 17 PF1 I/O FT FSMC_A1 / I2C2_SCL / EVENTOUT - - - 12 H2 18 PF2 I/O FT FSMC_A2 / I2C2_SMBA / EVENTOUT - - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9 - - - 14 J3 20 PF4 I/O FT (4) FSMC_A4/EVENTOUT ADC3_IN14 - - - 15 K3 21 PF5 I/O FT (4) FSMC_A5/EVENTOUT ADC3_IN15 - C9 10 16 G2 22 VSS S - B8 11 17 G3 23 VDD S - - - 18 K2 24 PF6 I/O FT (4) TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG / EVENTOUT ADC3_IN5 - - - 20 L3 26 PF8 I/O FT (4) TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8 5 F10 12 23 G1 29 PH0/OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 F9 13 24 H1 30 PH1/OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 G10 14 25 J1 31 NRST I/O RS T 8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/ EVENTOUT ADC123_IN10 9 - 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11 10 D10 17 28 M4 34 PC2 I/O FT (4) SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT ADC123_IN12 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 47/185 STM32F405xx, STM32F407xx Pinouts and pin description 11 E9 18 29 M5 35 PC3 I/O FT (4) SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_IN13 - - 19 30 G3 36 VDD S 12 H10 20 31 M1 37 VSSA S - - - - N1 - VREF– S - - 21 32 P1 38 VREF+ S 13 G9 22 33 R1 39 VDDA S 14 C10 23 34 N3 40 PA0/WKUP (PA0) I/O FT (5) USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT ADC123_IN0/WKUP(4 ) 15 F8 24 35 N2 41 PA1 I/O FT (4) USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT ADC123_IN1 16 J10 25 36 P2 42 PA2 I/O FT (4) USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT ADC123_IN2 - - - - F4 43 PH2 I/O FT ETH_MII_CRS/EVENTOU T - - - - G4 44 PH3 I/O FT ETH_MII_COL/EVENTOU T - - - - H4 45 PH4 I/O FT I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - - J4 46 PH5 I/O FT I2C2_SDA/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 48/185 DocID022152 Rev 4 17 H9 26 37 R2 47 PA3 I/O FT (4) USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 18 E5 27 38 - - VSS S D9 L4 48 BYPASS_REG I FT 19 E4 28 39 K4 49 VDD S 20 J9 29 40 N4 50 PA4 I/O TTa (4) SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC_OUT1 21 G8 30 41 P4 51 PA5 I/O TTa (4) SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CH1N/ EVENTOUT ADC12_IN5/DAC_OU T2 22 H8 31 42 P3 52 PA6 I/O FT (4) SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 23 J8 32 43 R3 53 PA7 I/O FT (4) SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT ADC12_IN7 24 - 33 44 N5 54 PC4 I/O FT (4) ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 - 34 45 P5 55 PC5 I/O FT (4) ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT ADC12_IN15 26 G7 35 46 R5 56 PB0 I/O FT (4) TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 49/185 STM32F405xx, STM32F407xx Pinouts and pin description 27 H7 36 47 R4 57 PB1 I/O FT (4) TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT ADC12_IN9 28 J7 37 48 M6 58 PB2/BOOT1 (PB2) I/O FT EVENTOUT - - - 49 R6 59 PF11 I/O FT DCMI_D12/ EVENTOUT - - - 50 P6 60 PF12 I/O FT FSMC_A6/ EVENTOUT - - - 51 M8 61 VSS S - - - 52 N8 62 VDD S - - - 53 N6 63 PF13 I/O FT FSMC_A7/ EVENTOUT - - - 54 R7 64 PF14 I/O FT FSMC_A8/ EVENTOUT - - - 55 P7 65 PF15 I/O FT FSMC_A9/ EVENTOUT - - - 56 N7 66 PG0 I/O FT FSMC_A10/ EVENTOUT - - - 57 M7 67 PG1 I/O FT FSMC_A11/ EVENTOUT - G6 38 58 R8 68 PE7 I/O FT FSMC_D4/TIM1_ETR/ EVENTOUT - H6 39 59 P8 69 PE8 I/O FT FSMC_D5/ TIM1_CH1N/ EVENTOUT - J6 40 60 P9 70 PE9 I/O FT FSMC_D6/TIM1_CH1/ EVENTOUT - - - 61 M9 71 VSS S - - - 62 N9 72 VDD S - F6 41 63 R9 73 PE10 I/O FT FSMC_D7/TIM1_CH2N/ EVENTOUT - J5 42 64 P10 74 PE11 I/O FT FSMC_D8/TIM1_CH2/ EVENTOUT - H5 43 65 R10 75 PE12 I/O FT FSMC_D9/TIM1_CH3N/ EVENTOUT - G5 44 66 N11 76 PE13 I/O FT FSMC_D10/TIM1_CH3/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 50/185 DocID022152 Rev 4 - F5 45 67 P11 77 PE14 I/O FT FSMC_D11/TIM1_CH4/ EVENTOUT - G4 46 68 R11 78 PE15 I/O FT FSMC_D12/TIM1_BKIN/ EVENTOUT 29 H4 47 69 R12 79 PB10 I/O FT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT 30 J4 48 70 R13 80 PB11 I/O FT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT 31 F4 49 71 M10 81 VCAP_1 S 32 - 50 72 N10 82 VDD S - - - - M11 83 PH6 I/O FT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - - N12 84 PH7 I/O FT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - - M12 85 PH8 I/O FT I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - - M13 86 PH9 I/O FT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - - L13 87 PH10 I/O FT TIM5_CH1 / DCMI_D1/ EVENTOUT - - - - L12 88 PH11 I/O FT TIM5_CH2 / DCMI_D2/ EVENTOUT - - - - K12 89 PH12 I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT - - - - H12 90 VSS S - - - - J12 91 VDD S Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 51/185 STM32F405xx, STM32F407xx Pinouts and pin description 33 J3 51 73 P12 92 PB12 I/O FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT 34 J1 52 74 P13 93 PB13 I/O FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT OTG_HS_VBUS 35 J2 53 75 R14 94 PB14 I/O FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT 36 H1 54 76 R15 95 PB15 I/O FT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT RTC_REFIN - H2 55 77 P15 96 PD8 I/O FT FSMC_D13 / USART3_TX/ EVENTOUT - H3 56 78 P14 97 PD9 I/O FT FSMC_D14 / USART3_RX/ EVENTOUT - G3 57 79 N15 98 PD10 I/O FT FSMC_D15 / USART3_CK/ EVENTOUT - G1 58 80 N14 99 PD11 I/O FT FSMC_CLE / FSMC_A16/USART3_CT S/ EVENTOUT - G2 59 81 N13 100 PD12 I/O FT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 52/185 DocID022152 Rev 4 - - 60 82 M15 101 PD13 I/O FT FSMC_A18/TIM4_CH2/ EVENTOUT - - - 83 - 102 VSS S - - - 84 J13 103 VDD S - F2 61 85 M14 104 PD14 I/O FT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT - F1 62 86 L14 105 PD15 I/O FT FSMC_D1/TIM4_CH4/ EVENTOUT - - - 87 L15 106 PG2 I/O FT FSMC_A12/ EVENTOUT - - - 88 K15 107 PG3 I/O FT FSMC_A13/ EVENTOUT - - - 89 K14 108 PG4 I/O FT FSMC_A14/ EVENTOUT - - - 90 K13 109 PG5 I/O FT FSMC_A15/ EVENTOUT - - - 91 J15 110 PG6 I/O FT FSMC_INT2/ EVENTOUT - - - 92 J14 111 PG7 I/O FT FSMC_INT3 /USART6_CK/ EVENTOUT - - - 93 H14 112 PG8 I/O FT USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - - 94 G12 113 VSS S - - - 95 H13 114 VDD S 37 F3 63 96 H15 115 PC6 I/O FT I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT 38 E1 64 97 G15 116 PC7 I/O FT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 E2 65 98 G14 117 PC8 I/O FT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 53/185 STM32F405xx, STM32F407xx Pinouts and pin description 40 E3 66 99 F14 118 PC9 I/O FT I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 41 D1 67 100 F15 119 PA8 I/O FT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 D2 68 101 E15 120 PA9 I/O FT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT OTG_FS_VBUS 43 D3 69 102 D15 121 PA10 I/O FT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT 44 C1 70 103 C15 122 PA11 I/O FT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 45 C2 71 104 B15 123 PA12 I/O FT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 D4 72 105 A15 124 PA13 (JTMS-SWDIO) I/O FT JTMS-SWDIO/ EVENTOUT 47 B1 73 106 F13 125 VCAP_2 S - E7 74 107 F12 126 VSS S 48 E6 75 108 G13 127 VDD S - - - - E12 128 PH13 I/O FT TIM8_CH1N / CAN1_TX/ EVENTOUT - - - - E13 129 PH14 I/O FT TIM8_CH2N / DCMI_D4/ EVENTOUT - - - - D13 130 PH15 I/O FT TIM8_CH3N / DCMI_D11/ EVENTOUT - C3 - - E14 131 PI0 I/O FT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 54/185 DocID022152 Rev 4 - B2 - - D14 132 PI1 I/O FT SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT - - - - C14 133 PI2 I/O FT TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT - - - - C13 134 PI3 I/O FT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - - D9 135 VSS S - - - - C9 136 VDD S 49 A2 76 109 A14 137 PA14 (JTCK/SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 50 B3 77 110 A13 138 PA15 (JTDI) I/O FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ET R / SPI1_NSS / EVENTOUT 51 D5 78 111 B14 139 PC10 I/O FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT 52 C4 79 112 B13 140 PC11 I/O FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT 53 A3 80 113 A12 141 PC12 I/O FT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT - D6 81 114 B12 142 PD0 I/O FT FSMC_D2/CAN1_RX/ EVENTOUT - C5 82 115 C12 143 PD1 I/O FT FSMC_D3 / CAN1_TX/ EVENTOUT 54 B4 83 116 D12 144 PD2 I/O FT TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 55/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 84 117 D11 145 PD3 I/O FT FSMC_CLK/ USART2_CTS/ EVENTOUT - A4 85 118 D10 146 PD4 I/O FT FSMC_NOE/ USART2_RTS/ EVENTOUT - C6 86 119 C11 147 PD5 I/O FT FSMC_NWE/USART2_TX / EVENTOUT - - - 120 D8 148 VSS S - - - 121 C8 149 VDD S - B5 87 122 B11 150 PD6 I/O FT FSMC_NWAIT/ USART2_RX/ EVENTOUT - A5 88 123 A11 151 PD7 I/O FT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT - - - 124 C10 152 PG9 I/O FT USART6_RX / FSMC_NE2/FSMC_NCE3 / EVENTOUT - - - 125 B10 153 PG10 I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT - - - 126 B9 154 PG11 I/O FT FSMC_NCE4_2 / ETH_MII_TX_EN/ ETH _RMII_TX_EN/ EVENTOUT - - - 127 B8 155 PG12 I/O FT FSMC_NE4 / USART6_RTS/ EVENTOUT - - - 128 A8 156 PG13 I/O FT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT - - - 129 A7 157 PG14 I/O FT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 56/185 DocID022152 Rev 4 - E8 - 130 D7 158 VSS S - F7 - 131 C7 159 VDD S - - - 132 B7 160 PG15 I/O FT USART6_CTS / DCMI_D13/ EVENTOUT 55 B6 89 133 A10 161 PB3 (JTDO/ TRACESWO) I/O FT JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT 56 A6 90 134 A9 162 PB4 (NJTRST) I/O FT NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT 57 D7 91 135 A6 163 PB5 I/O FT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH 2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT 58 C7 92 136 B6 164 PB6 I/O FT I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT 59 B7 93 137 B5 165 PB7 I/O FT I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT 60 A7 94 138 D6 166 BOOT0 I B VPP 61 D8 95 139 A5 167 PB8 I/O FT TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT 62 C8 96 140 B4 168 PB9 I/O FT SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 57/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 97 141 A4 169 PE0 I/O FT TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - - 98 142 A3 170 PE1 I/O FT FSMC_NBL1 / DCMI_D3/ EVENTOUT 63 - 99 - D5 - VSS S - A8 - 143 C6 171 PDR_ON I FT 64 A1 10 0 144 C5 172 VDD S - - - - D4 173 PI4 I/O FT TIM8_BKIN / DCMI_D5/ EVENTOUT - - - - C4 174 PI5 I/O FT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - - C3 175 PI6 I/O FT TIM8_CH2 / DCMI_D6/ EVENTOUT - - - - C2 176 PI7 I/O FT TIM8_CH3 / DCMI_D7/ EVENTOUT 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Table 8. FSMC pin definition Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PE2 A23 A23 Yes PE3 A19 A19 Yes Pinouts and pin description STM32F405xx, STM32F407xx 58/185 DocID022152 Rev 4 PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 - - PF1 A1 A1 - - PF2 A2 A2 - - PF3 A3 A3 - - PF4 A4 A4 - - PF5 A5 A5 - - PF6 NIORD - - PF7 NREG - - PF8 NIOWR - - PF9 CD - - PF10 INTR - - PF12 A6 A6 - - PF13 A7 A7 - - PF14 A8 A8 - - PF15 A9 A9 - - PG0 A10 A10 - - PG1 A11 - - PE7 D4 D4 DA4 D4 Yes Yes PE8 D5 D5 DA5 D5 Yes Yes PE9 D6 D6 DA6 D6 Yes Yes PE10 D7 D7 DA7 D7 Yes Yes PE11 D8 D8 DA8 D8 Yes Yes PE12 D9 D9 DA9 D9 Yes Yes PE13 D10 D10 DA10 D10 Yes Yes PE14 D11 D11 DA11 D11 Yes Yes PE15 D12 D12 DA12 D12 Yes Yes PD8 D13 D13 DA13 D13 Yes Yes PD9 D14 D14 DA14 D14 Yes Yes PD10 D15 D15 DA15 D15 Yes Yes PD11 A16 A16 CLE Yes Yes Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit DocID022152 Rev 4 59/185 STM32F405xx, STM32F407xx Pinouts and pin description PD12 A17 A17 ALE Yes Yes PD13 A18 A18 Yes PD14 D0 D0 DA0 D0 Yes Yes PD15 D1 D1 DA1 D1 Yes Yes PG2 A12 - - PG3 A13 - - PG4 A14 - - PG5 A15 - - PG6 INT2 - - PG7 INT3 - - PD0 D2 D2 DA2 D2 Yes Yes PD1 D3 D3 DA3 D3 Yes Yes PD3 CLK CLK Yes PD4 NOE NOE NOE NOE Yes Yes PD5 NWE NWE NWE NWE Yes Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes Yes PD7 NE1 NE1 NCE2 Yes Yes PG9 NE2 NE2 NCE3 - - PG10 NCE4_1 NE3 NE3 - - PG11 NCE4_2 - - PG12 NE4 NE4 - - PG13 A24 A24 - - PG14 A25 A25 - - PB7 NADV NADV Yes Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column. 2. Ports F and G are not available in devices delivered in 100-pin packages. Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit Pinouts and pin description STM32F405xx, STM32F407xx 60/185 DocID022152 Rev 4 Table 9. Alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port A PA0 TIM2_CH1_E TR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII__REF _CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_ D0 ETH _MII_COL EVENTOUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK OTG_HS_SO F DCMI_HSYN C EVENTOUT PA5 TIM2_CH1_E TR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_ CK EVENTOUT PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT PA9 TIM1_CH2 I2C3_SMB A USART1_TX DCMI_D0 EVENTOUT PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMSSWDIO EVENTOUT PA14 JTCKSWCLK EVENTOUT PA15 JTDI TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS/ I2S3_WS EVENTOUT STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 61/185 Port B PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_ D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_ D2 ETH _MII_RXD3 EVENTOUT PB2 EVENTOUT PB3 JTDO/ TRACES WO TIM2_CH2 SPI1_SCK SPI3_SCK I2S3_CK EVENTOUT PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO I2S3ext_SD EVENTOUT PB5 TIM3_CH2 I2C1_SMB A SPI1_MOSI SPI3_MOSI I2S3_SD CAN2_RX OTG_HS_ULPI_ D7 ETH _PPS_OUT DCMI_D10 EVENTOUT PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYN C EVENTOUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS I2S2_WS CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT PB10 TIM2_CH3 I2C2_SCL SPI2_SCK I2S2_CK USART3_TX OTG_HS_ULPI_ D3 ETH_ MII_RX_ER EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_ D4 ETH _MII_TX_EN ETH _RMII_TX_EN EVENTOUT PB12 TIM1_BKIN I2C2_SMB A SPI2_NSS I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_ D5 ETH _MII_TXD0 ETH _RMII_TXD0 OTG_HS_ID EVENTOUT PB13 TIM1_CH1N SPI2_SCK I2S2_CK USART3_CTS CAN2_TX OTG_HS_ULPI_ D6 ETH _MII_TXD1 ETH _RMII_TXD1 EVENTOUT PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO I2S2ext_SD USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT PB15 RTC_ REFIN TIM1_CH3N TIM8_CH3N SPI2_MOSI I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 62/185 DocID022152 Rev 4 Port C PC0 OTG_HS_ULPI_ STP EVENTOUT PC1 ETH_MDC EVENTOUT PC2 SPI2_MISO I2S2ext_SD OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT PC3 SPI2_MOSI I2S2_SD OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN SDIO_D1 DCMI_D3 EVENTOUT PC10 SPI3_SCK/ I2S3_CK USART3_TX/ UART4_TX SDIO_D2 DCMI_D8 EVENTOUT PC11 I2S3ext_SD SPI3_MISO/ USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT PC12 SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 63/185 Port D PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 64/185 DocID022152 Rev 4 Port E PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT PE1 FSMC_NBL1 DCMI_D3 EVENTOUT PE2 TRACECL K ETH _MII_TXD3 FSMC_A23 EVENTOUT PE3 TRACED0 FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 65/185 Port F PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_ SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT PF8 TIM13_CH1 FSMC_ NIOWR EVENTOUT PF9 TIM14_CH1 FSMC_CD EVENTOUT PF10 FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 66/185 DocID022152 Rev 4 Port G PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT PG7 USART6_CK FSMC_INT3 EVENTOUT PG8 USART6_ RTS ETH _PPS_OUT EVENTOUT PG9 USART6_RX FSMC_NE2/ FSMC_NCE3 EVENTOUT PG10 FSMC_ NCE4_1/ FSMC_NE3 EVENTOUT PG11 ETH _MII_TX_EN ETH _RMII_ TX_EN FSMC_NCE4_ 2 EVENTOUT PG12 USART6_ RTS FSMC_NE4 EVENTOUT PG13 UART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 FSMC_A24 EVENTOUT PG14 USART6_TX ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A25 EVENTOUT PG15 USART6_ CTS DCMI_D13 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 67/185 Port H PH0 EVENTOUT PH1 EVENTOUT PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT PH4 I2C2_SCL OTG_HS_ULPI_ NXT EVENTOUT PH5 I2C2_SDA EVENTOUT PH6 I2C2_SMB A TIM12_CH1 ETH _MII_RXD2 EVENTOUT PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT PH8 I2C3_SDA DCMI_HSYN C EVENTOUT PH9 I2C3_SMB A TIM12_CH2 DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TIM8_CH1N CAN1_TX EVENTOUT PH14 TIM8_CH2N DCMI_D4 EVENTOUT PH15 TIM8_CH3N DCMI_D11 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 68/185 DocID022152 Rev 4 Port I PI0 TIM5_CH4 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT PI1 SPI2_SCK I2S2_CK DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO I2S2ext_SD DCMI_D9 EVENTOUT PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_ VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT PI8 EVENTOUT PI9 CAN1_RX EVENTOUT PI10 ETH _MII_RX_ER EVENTOUT PI11 OTG_HS_ULPI_ DIR EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI DocID022152 Rev 4 69/185 STM32F405xx, STM32F407xx Memory mapping 4 Memory mapping The memory map is shown in Figure 18. Figure 18. STM32F40x memory map 512-Mbyte block 7 Cortex-M4's internal peripherals 512-Mbyte block 6 Not used 512-Mbyte block 5 FSMC registers 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 512-Mbyte block 1 SRAM 0x0000 0000 0x1FFF FFFF 0x2000 0000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 0x6000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xFFFF FFFF 512-Mbyte block 0 Code Flash 0x0810 0000 - 0x0FFF FFFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1FFF C000 - 0x1FFF C007 0x0800 0000 - 0x080F FFFF 0x0010 0000 - 0x07FF FFFF 0x0000 0000 - 0x000F FFFF System memory + OTP Reserved Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins SRAM (16 KB aliased by bit-banding) Reserved 0x2000 0000 - 0x2001 BFFF 0x2001 C000 - 0x2001 FFFF 0x2002 0000 - 0x3FFF FFFF 0x4000 0000 Reserved 0x4000 7FFF 0x4000 7800 - 0x4000 FFFF 0x4001 0000 0x4001 57FF 0x4002 000 Reserved 0x5006 0C00 - 0x5FFF FFFF 0x6000 0000 AHB3 0xA000 0FFF 0xA000 1000 - 0xDFFF FFFF ai18513f Option Bytes Reserved 0x4001 5800 - 0x4001 FFFF 0x5006 0BFF AHB2 0x5000 0000 Reserved 0x4008 0000 - 0x4FFF FFFF AHB1 SRAM (112 KB aliased by bit-banding) Reserved 0x1FFF C008 - 0x1FFF FFFF Reserved 0x1FFF 7A10 - 0x1FFF 7FFF CCM data RAM (64 KB data SRAM) 0x1000 0000 - 0x1000 FFFF Reserved 0x1001 0000 - 0x1FFE FFFF Reserved APB2 0x4007 FFFF APB1 CORTEX-M4 internal peripherals 0xE000 0000 - 0xE00F FFFF Reserved 0xE010 0000 - 0xFFFF FFFF Memory mapping STM32F405xx, STM32F407xx 70/185 DocID022152 Rev 4 Table 10. STM32F40x register boundary addresses Bus Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 1000 - 0xDFFF FFFF Reserved AHB3 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF FSMC bank 4 0x8000 0000 - 0x8FFF FFFF FSMC bank 3 0x7000 0000 - 0x7FFF FFFF FSMC bank 2 0x6000 0000 - 0x6FFF FFFF FSMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved AHB2 0x5006 0800 - 0x5006 0BFF RNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4008 0000- 0x4FFF FFFF Reserved DocID022152 Rev 4 71/185 STM32F405xx, STM32F407xx Memory mapping AHB1 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 9400 - 0x4003 FFFF Reserved 0x4002 9000 - 0x4002 93FF ETHERNET MAC 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 0x4001 5800- 0x4001 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Memory mapping STM32F405xx, STM32F407xx 72/185 DocID022152 Rev 4 APB2 0x4001 4C00 - 0x4001 57FF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7800- 0x4000 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral DocID022152 Rev 4 73/185 STM32F405xx, STM32F407xx Memory mapping APB1 0x4000 7800 - 0x4000 7FFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Electrical characteristics STM32F405xx, STM32F407xx 74/185 DocID022152 Rev 4 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Pin input voltage MS19011V1 C = 50 pF STM32F pin OSC_OUT (Hi-Z when using HSE or LSE) MS19010V1 STM32F pin VIN OSC_OUT (Hi-Z when using HSE or LSE) DocID022152 Rev 4 75/185 STM32F405xx, STM32F407xx Electrical characteristics 5.1.6 Power supply scheme Figure 21. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15: Power supply supervisor. 3. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 μF ceramic capacitor must be connected to one of the VDD pin. 5. VDDA=VDD and VSSA=VSS. MS19911V2 Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Kernel logic (CPU, digital & RAM) Analog: RCs, PLL,.. Power switch VBAT GPIOs OUT IN 15 × 100 nF + 1 × 4.7 μF VBAT = 1.65 to 3.6V Voltage regulator VDDA ADC Level shifter IO Logic VDD 100 nF + 1 μF Flash memory VCAP_1 2 × 2.2 μF VCAP_2 BYPASS_REG PDR_ON Reset controller VDD 1/2/...14/15 VSS 1/2/...14/15 VDD VREF+ VREFVSSA VREF 100 nF + 1 μF Electrical characteristics STM32F405xx, STM32F407xx 76/185 DocID022152 Rev 4 5.1.7 Current consumption measurement Figure 22. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 VBAT VDD VDDA IDD_VBAT IDD Table 11. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA, VDD)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V VIN Input voltage on five-volt tolerant pin(2) 2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current. VSS–0.3 VDD+4 Input voltage on any other pin VSS–0.3 4.0 |ΔVDDx| Variations between different VDD power pins - 50 mV |VSSX − VSS| Variations between all the different ground pins - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) DocID022152 Rev 4 77/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 12. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 150 mA IVSS Total current out of VSS ground lines (sink)(1) 150 IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IINJ(PIN) (2) 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. Injected current on five-volt tolerant I/O(3) 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN
