KA3525A SMPS Controller - Farnell Element 14 - Revenir à l'accueil
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©2002 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.1 Features • 5V ±1% Reference • Oscillator Sync Terminal • Internal Soft Start • Deadtime Control • Under Voltage Lockout Description The KA3525A is a monolithic integrated circuit that includes all of the control circuits necessary for a pulse width modulating regulator. There are a voltage reference, an error amplifier, a pulse width modulator, an oscillator, an under voltage lockout, a soft start circuit, and the output driver in the chip. 16-DIP 1 Internal Block Diagram 16 15 12 1 2 9 8 10 5 7 3 6 4 14 11 13 U.V.L.O. BAND GAP REF 5V LATCH S R F/F Q Q 5K VC OUTPUT A OUTPUT B OSCILLATOR DISCHARGE 5K ERR AMP PWM COMP _ + _ + CT VREF VCC GND EA(-) EA(+) EAOUT C (SOFT START) SHUT DOWN SYNC RT OSC OUTPUT KA3525A SMPS Controller KA3525A 2 Absolute Maximum Ratings Electrical Characteristics (VCC = 20V, TA = 0 to +70°C, unless otherwise specified) Parameter Symbol Value Unit Supply Voltage VCC 40 V Collector Supply Voltage VC 40 V Output Current, Sink or Source IO 500 mA Reference Output Current IREF 50 mA Oscillator Charging Current ICHG(OSC) 5 mA Power Dissipation (TA = 25°C) PD 1000 m/W Operating Temperature TOPR 0 ~ +70 °C Storage Temperature TSTG -65 ~ +150 °C Lead Temperature (Soldering, 10sec) TLEAD +300 °C Parameter Symbol Conditions Min. Typ. Max. Unit REFERENCE SECTION Reference Output Voltage VREF TJ = 25°C 5.0 5.1 5.2 V Line Regulation ∆VREF VCC = 8 to 35V - 9 20 mV Load Regulation ∆VREF IREF = 0 to 20mA - 20 50 mV Short Circuit Output Current ISC VREF = 0, TJ = 25°C - 80 100 mA Total Output Variation (Note1) ∆VREF Line, Load and Temperature 4.95 - 5.25 V Temperature Stability (Note1) STT - - 20 50 mV Long Term Stability (Note1) ST TJ = 125°C ,1KHRS - 20 50 mV OSCILLATOR SECTION Initial Accuracy (Note1, 2) ACCUR TJ = 25°C - ±3 ±6 % Frequency Change With Voltage ∆f/∆VCC VCC = 8 to 35V (Note1, 2) - ±0.8 ±2 % Maximum Frequency f(MAX) RT = 2kΩ, CT = 470pF 400 430 - kHz Minimum Frequency f(MIN) RT = 200kΩ, CT = 0.1uF - 60 120 Hz Clock Amplitude (Note1, 2) V(CLK) - 34- V Clock Width (Note1, 2) tW(CLK) TJ = 25°C 0.3 0.6 1 µs Sync Threshold VTH(SYNC) - 1.2 2 2.8 V Sync Input Current II(SYNC) Sync = 3.5V - 1.3 2.5 mA KA3525A 3 Electrical Characteristics (Continued) (VCC = 20V, TA = 0 to +70°C, unless otherwise specified) Note : 1. These parameters. although guaranteed over the recommended operating conditions, are not 100% tested in production 2. Tested at fOSC=40kHz (RT =3.6K, CT =0.01uF, RI = 0Ω) Parameter Symbol Conditions Min. Typ. Max. Unit ERROR AMPLIFIER SECTION (VCM = 5.1V) Input Offset Voltage VIO - - 1.5 10 mV Input Bias Current IBIAS - - 1 10 µA Input Offset Current IIO - - 0.1 1 µA Open Loop Voltage Gain GVO RL ≥ 10MΩ 60 80 - dB Common Mode Rejection Ratio CMRR VCM = 1.5 to 5.2V 60 90 - dB Power Supply Rejection Ratio PSRR VCC = 8 to 3.5V 50 60 - dB PWM COMPARATOR SECTION Minimum Duty Cycle D(MIN) - - - 0% Maximum Duty Cycle D(MAX) - 45 49 - % Input Threshold Voltage (Note2) VTH1 Zero Duty Cycle 0.7 0.9 - V Input Threshold Voltage (Note2) VTH2 Max Duty Cycle - 3.2 3.6 V SOFT-START SECTION Soft Start Current ISOFT VSD = 0V, VSS = 0V 25 51 80 µA Soft Start Low Level Voltage VSL VSD = 25V - 0.3 0.7 V Shutdown Threshold Voltage VTH(SD) - 0.9 1.3 1.7 V Shutdown Input Current IN(SD) VSD = 2.5V - 0.3 1 mA OUTPUT SECTION Low Output Voltage I VOL I ISINK = 20mA - 0.1 0.4 V Low Output Voltage II VOL II ISINK = 100mA - 0.05 2 V High Output Voltage I VCH I ISOURCE = 20mA 18 19 - V High Output Voltage II VCH II ISOURCE = 100mA 17 18 - V Under Voltage Lockout VUV V8 and V9 = High 6 7 8 V Collector Leakage Current ILKG VCC = 35V - 80 200 µA Rise Time (Note1) tR CL = 1uF, TJ = 25°C - 80 600 ns Fall Time (Note1) tF CL = 1uF, TJ = 25°C - 70 300 ns STANDBY CURRENT Supply Current ICC VCC = 35V - 12 20 mA KA3525A 4 Test Circuit 16 15 12 1 2 9 8 10 5 7 13 11 14 3 6 BAND GAP REF 5V U.V.L.O. A B 0.1 Vcc 0.1 3k RWM ADJ 10k 1.5K 10K 0.01 5.0uF 5.0k 5.0k 5.0k 100 F/F ERR AMP ERR AMP OSCILLATOR LATCH S S R SOFT START + SHUTDOWN VREF CT RAMP 0.009 0.1 + 3.6k 0.001 DEAD TIME OUT B 10k 10k OUT A VC CLOCK _ + + _ RT KA3525A 5 Mechanical Dimensions Package #1 #8 #9 #16 6.40 ±0.20 7.62 0.300 2.54 0.100 0.252 ±0.008 0~15° 0.25 +0.10 –0.05 0.010 +0.004 –0.002 3.30 ±0.30 0.130 ±0.012 3.25 ±0.20 0.128 ±0.008 19.40 ±0.20 0.764 ±0.008 19.80 0.780 MAX 5.08 0.200 0.38 0.014 MAX MIN 0.81 0.032 ( ) 0.46 ±0.10 0.018 ±0.004 0.059 ±0.004 1.50 ±0.10 16-DIP KA3525A 10/2/02 0.0m 001 Stock#DSxxxxxxxx 2002 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. Ordering Information Product Number Package Operating Temperature KA3525A 16-DIP 0 ~ +70°C ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FPS Rev.1.0.6 TM is a trademark of Fairchild Semiconductor Corporation. Features • Internal Avalanche Rugged Sense FET • Advanced Burst-Mode operation consumes under 1 W at 240VAC & 0.5W load • Precision Fixed Operating Frequency (66kHz) • Internal Start-up Circuit • Improved Pulse by Pulse Current Limiting • Over Voltage Protection (OVP) • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lock Out (UVLO) with hysteresis • Low Operating Current (2.5mA) • Built-in Soft Start Application • SMPS for LCD monitor and STB • Adaptor Description The FSDM0565RB is an integrated Pulse Width Modulator (PWM) and Sense FET specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high voltage power switching regulator which combine an avalanche rugged Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of flyback converters. Table 1. Maximum Output Power Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit Figure 1. Typical Flyback Application OUTPUT POWER TABLE PRODUCT 230VAC ±15%(3) 85-265VAC Adapter(1) Open Frame(2) Adapter(1) Open Frame(2) FSDM0565RB 60W 70W 50W 60W FSDM0565RBI 60W 70W 50W 60W FSDM07652RB 70W 80W 60W 70W Drain Source Vstr Vfb Vcc PWM AC IN DC OUT FSDM0565RB Green Mode Fairchild Power Switch (FPSTM) FSDM0565RB 2 Internal Block Diagram Figure 2. Functional Block Diagram of FSDM0565RB 8V/12V 3 1 2 4 5 Vref Internal Bias S Q Q R OSC Vcc Vref Idelay IFB VSD TSD Vovp Vcc VCL S Q Q R R 2.5R Vcc good Vcc Drain N.C FB GND Gate driver 6 Vstr Istart Vcc good 0.5/0.7V LEB PWM Soft start + - FSDM0565RB 3 Pin Definitions Pin Configuration Figure 3. Pin Configuration (Top View) Pin Number Pin Name Pin Function Description 1 Drain This pin is the high voltage power Sense FET drain. It is designed to drive the transformer directly. 2 GND This pin is the control ground and the Sense FET source. 3 Vcc This pin is the positive supply voltage input. During start up, the power is supplied by an internal high voltage current source that is connected to the Vstr pin. When Vcc reaches 12V, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. 4 Vfb This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6.0V, the over load protection is activated resulting in shutdown of the FPSTM. 5 N.C - 6 Vstr This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled. 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain TO-220F-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain I2-PAK-6L FSDM0565RB 4 Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L=14mH, starting Tj=25°C 3. L=13uH, starting Tj=25°C Thermal Impedance Notes: 1. Free standing with no heat-sink under natural convection. 2. Infinite cooling condition - Refer to the SEMI G30-88. Parameter Symbol Value Unit Drain-source voltage VDSS 650 V Vstr Max Voltage VSTR 650 V Pulsed Drain current (Tc=25°C)(1) IDM 11 ADC Continuous Drain Current(Tc=25°C) ID 2.8 A Continuous Drain Current(Tc=100°C) 1.7 A Single pulsed avalanche energy (2) EAS 190 mJ Single pulsed avalanche current (3) IAS - A Supply voltage VCC 20 V Input voltage range VFB -0.3 to VCC V Total power dissipation(Tc=25°C) PD(Watt H/S) 45 (TO-220-6L) W 75 (I2-PAK-6L) Operating junction temperature Tj Internally limited °C Operating ambient temperature TA -25 to +85 °C Storage temperature range TSTG -55 to +150 °C ESD Capability, HBM Model (All pins excepts for Vstr and Vfb) - 2.0 (GND-Vstr/Vfb=1.5kV) kV ESD Capability, Machine Model (All pins excepts for Vstr and Vfb) - 300 (GND-Vstr/Vfb=225V) V Parameter Symbol Package Value Unit Junction-to-Ambient Thermal θJA(1) TO-220F-6L 49.90 °C/W I2-PAK-6L 30 Junction-to-Case Thermal θJC(2) TO-220F-6L 2.78 °C/W I2-PAK-6L 1.67 FSDM0565RB 5 Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Sense FET SECTION Drain source breakdown voltage BVDSS VGS = 0V, ID = 250μA 650 - - V Zero gate voltage drain current IDSS VDS = 650V, VGS = 0V - - 500 μA VDS= 520V VGS = 0V, TC = 125°C - - 500 μA Static drain source on resistance (1) RDS(ON) VGS = 10V, ID = 2.5A - 1.76 2.2 Ω Output capacitance COSS VGS = 0V, VDS = 25V, f = 1MHz - 78 - pF Turn on delay time TD(ON) VDD= 325V, ID= 5A (MOSFET switching time is essentially independent of operating temperature) - 22 - ns Rise time TR - 52 - Turn off delay time TD(OFF) - 95 - Fall time TF - 50 - CONTROL SECTION Initial frequency FOSC VFB = 3V 60 66 72 kHz Voltage stability FSTABLE 13V ≤ Vcc ≤ 18V 0 1 3 % Temperature stability (2) ΔFOSC -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 % Maximum duty cycle DMAX - 77 82 87 % Minimum duty cycle DMIN - - - 0% Start threshold voltage VSTART VFB=GND 11 12 13 V Stop threshold voltage VSTOP VFB=GND 7 8 9 V Feedback source current IFB VFB=GND 0.7 0.9 1.1 mA Soft-start time TS Vfb=3 - 10 15 ms Leading Edge Blanking time TLEB - - 250 - ns BURST MODE SECTION Burst Mode Voltages (2) VBURH Vcc=14V - 0.7 - V VBURL Vcc=14V - 0.5 - V PROTECTION SECTION Peak current limit (4) IOVER VFB=5V, VCC=14V 2.0 2.25 2.5 A Over voltage protection VOVP - 18 19 20 V Thermal shutdown temperature (2) TSD 130 145 160 °C Shutdown feedback voltage VSD VFB ≥ 5.5V 5.5 6.0 6.5 V Shutdown delay current IDELAY VFB=5V 2.8 3.5 4.2 μA FSDM0565RB 6 Notes: 1. Pulse test : Pulse width ≤ 300μS, duty ≤ 2% 2. These parameters, although guaranteed at the design, are not tested in mass production. 3. These parameters, although guaranteed, are tested in EDS(wafer test) process. 4. These parameters indicate the inductor current. 5. This parameter is the current flowing into the control IC. TOTAL DEVICE SECTION Operating supply current (5) IOP VFB=GND, VCC=14V IOP(MIN) VFB=GND, VCC=10V - 2.5 5 mA IOP(MAX) VFB=GND, VCC=18V FSDM0565RB 7 Comparison Between FS6M07652RTC and FSDM0565RB Function FS6M07652RTC FSDM0565RB FSDM0565RB Advantages Soft-Start Adjustable soft-start time using an external capacitor Internal soft-start with typically 10ms (fixed) • Gradually increasing current limit during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot Burst Mode Operation • Built into controller • Output voltage drops to around half • Built into controller • Output voltage fixed • Improve light load efficiency • Reduces no-load consumption FSDM0565RB 8 Typical Performance Characteristics (These Characteristic Graphs are Normalized at Ta= 25°C) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Operating Frequency (Fosc) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Start Thershold Voltage (Vstart) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Stop Threshold Voltage (Vstop) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Maximum Duty Cycle (Dmax) Operating Current vs. Temp Start Threshold Voltage vs. Temp Stop Threshold Voltage vs. Temp Operating Freqency vs. Temp Maximum Duty vs. Temp Feedback Source Current vs. Temp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Operating Current (Iop) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) FB Source Current (Ifb) FSDM0565RB 9 Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Shutdown Delay Current (Idelay) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Over Voltage Protection (Vovp) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 Junction Temperature(℃) Peak Current Limit(Self protection) (Iover) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) FB Burst Mode Enable Voltage (Vfbe) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) FB Burst Mode Disable Voltage (Vfbd) ShutDown Feedback Voltage vs. Temp ShutDown Delay Current vs. Temp Over Voltage Protection vs. Temp Burst Mode Enable Voltage vs. Temp Burst Mode Disable Voltage vs. Temp Current Limit vs. Temp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Shutdown FB Voltage (Vsd) FSDM0565RB 10 Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) Soft Start Time vs. Temp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 Junction Temperature(℃) Soft Start Time (Normalized to 25℃) FSDM0565RB 11 Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vcc pin had an external start-up resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in Figure 4. When Vcc reaches 12V, the FSDM0565RB begins switching and the internal high voltage current source is disabled. Then, the FSDM0565RB continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 8V. Figure 4. Internal startup circuit 2. Feedback Control : FSDM0565RB employs current mode control, as shown in Figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 2.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of PWM comparator (Vfb*) as shown in Figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. 2.2 Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSDM0565RB employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Figure 5. Pulse width modulation (PWM) circuit 3. Protection Circuit : The FSDM0565RB has several self protective functions such as over load protection (OLP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 8V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FSDM0565RB resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 6). 8V/12V 3 Vref Internal Bias Vcc 6 Vstr Istart Vcc good VDC CVcc 4 OSC Vcc Vref Idelay IFB VSD R 2.5R Gate driver OLP D1 D2 + Vfb* - Vfb KA431 CB Vo H11A817A Rsense SenseFET FSDM0565RB 12 Figure 6. Auto restart operation 3.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 3.5uA current source starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is terminated as shown in Figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 6.0V with 3.5uA. In general, a 10 ~ 50 ms delay time is typical for most applications. Figure 7. Over load protection 3.2 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FSDM0565RB uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. 3.3 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 150°C, the thermal shutdown is activated. 4. Soft Start : The FSDM0565RB has an internal soft start circuit that increases PWM comparator inverting input voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 10msec, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. Fault situation 8V 12V Vcc Vds t Fault occurs Fault removed Normal operation Normal operation Power on VFB t 2.5V 6.0V Over load protection T12= Cfb*(6.0-2.5)/I delay T1 T2 FSDM0565RB 13 5. Burst operation : In order to minimize power dissipation in standby mode, the FSDM0565RB enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 8, the device automatically enters burst mode when the feedback voltage drops below VBURL(500mV). At this point switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH(700mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. Figure 8. Waveforms of burst operation VFB Vds 0.5V 0.7V Ids Vo Voset time Switching disabled T1 T2 T3 Switching disabled T4 FSDM0565RB 14 Typical application circuit Features • High efficiency (>81% at 85Vac input) • Low zero load power consumption (<300mW at 240Vac input) • Low standby mode power consumption (<800mW at 240Vac input and 0.3W load) • Low component count • Enhanced system reliability through various protection functions • Internal soft-start (10ms) Key Design Notes • Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these resistors since the startup pin is internally disconnected after startup. • The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is required, C106 can be reduced to 10nF. • Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener diode also increases the immunity against line surge. 1. Schematic Application Output power Input voltage Output voltage (Max current) LCD Monitor 40W Universal input (85-265Vac) 5V (2.0A) 12V (2.5A) 3 4 C102 220nF 275VAC LF101 23mH C101 220nF 275VAC RT1 5D-9 F1 FUSE 250V 2A C103 100uF 400V R102 30kΩ R105 40kΩ R103 56kΩ 2W C104 2.2nF 1kV D101 UF 4007 C106 47nF 50V C105 22uF 50V D102 TVR10G R104 5Ω 1 2 3 4 5 T1 EER3016 BD101 2KBP06M3N257 1 2 R101 560kΩ 1W IC1 FSDM0565RB Vstr NC Vfb Vcc Drain GND 1 2 3 4 5 6 ZD101 22V 8 10 D202 MBRF10100 C201 1000uF 25V C202 1000uF 25V L201 12V, 2.5A 6 7 D201 MBRF1045 C203 1000uF 10V C204 1000uF 10V L202 5V, 2A R201 1kΩ R202 1.2kΩ R204 5.6kΩ R203 12kΩ C205 47nF R205 5.6kΩ C301 4.7nF IC301 H11A817A IC201 KA431 ZD102 10V FSDM0565RB 15 2. Transformer Schematic Diagram 3.Winding Specification 4.Electrical Characteristics 5. Core & Bobbin Core : EER 3016 Bobbin : EER3016 Ae(mm2) : 96 No Pin (s→f) Wire Turns Winding Method Na 4 → 5 0.2φ × 1 8 Center Winding Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 2 → 1 0.4φ × 1 18 Solenoid Winding Insulation: Polyester Tape t = 0.050mm, 2Layers N12V 10 → 8 0.3φ × 3 7 Center Winding Insulation: Polyester Tape t = 0.050mm, 2Layers N5V 7 → 6 0.3φ × 3 3 Center Winding Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 3 → 2 0.4φ × 1 18 Solenoid Winding Outer Insulation: Polyester Tape t = 0.050mm, 2Layers Pin Specification Remarks Inductance 1 - 3 520uH ± 10% 100kHz, 1V Leakage Inductance 1 - 3 10uH Max 2nd all short EER3016 Np /2 N12V Na 1 2 3 4 5 6 7 8 9 10 Np /2 N5V FSDM0565RB 16 6.Demo Circuit Part List Part Value Note Part Value Note Fuse C301 4.7nF Polyester Film Cap. F101 2A/250V NTC Inductor RT101 5D-9 L201 5uH Wire 1.2mm Resistor L202 5uH Wire 1.2mm R101 560K 1W R102 30K 1/4W R103 56K 2W R104 5 1/4W Diode R105 40K 1/4W D101 UF4007 R201 1K 1/4W D102 TVR10G R202 1.2K 1/4W D201 MBRF1045 R203 12K 1/4W D202 MBRF10100 R204 5.6K 1/4W ZD101 Zener Diode 22V R205 5.6K 1/4W ZD102 Zener Diode 10V Bridge Diode BD101 2KBP06M 3N257 Bridge Diode Capacitor C101 220nF/275VAC Box Capacitor Line Filter C102 220nF/275VAC Box Capacitor LF101 23mH Wire 0.4mm C103 100uF/400V Electrolytic Capacitor IC C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM0565RB FPSTM(5A,650V) C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-coupler C201 1000uF/25V Electrolytic Capacitor C202 1000uF/25V Electrolytic Capacitor C203 1000uF/10V Electrolytic Capacitor C204 1000uF/10V Electrolytic Capacitor C205 47nF/50V Ceramic Capacitor FSDM0565RB 17 7. Layout Figure 9. Layout Considerations for FSDM0565RB Figure 10. Layout Considerations for FSDM0565RB FSDM0565RB 18 Package Dimensions TO-220F-6L(Forming) FSDM0565RB 19 Package Dimensions (Continued) I2-PAK-6L(Forming) FSDM0565RB 1/9/06 0.0m 001 © 2006 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. Ordering Information WDTU : Forming Type Product Number Package Marking Code BVdss Rds(on)Max. FSDM0565RBWDTU TO-220F-6L(Forming) DM0565R 650V 2.2 Ω FSDM0565RBIWDTU I2-PAK-6L (Forming) DM0565R 650V 2.2 Ω Data Sheet: JN5148-001 IEEE802.15.4 Wireless Microcontroller © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 1 Overview Features: Transceiver • 2.4GHz IEEE802.15.4 compliant • Time of Flight ranging engine • 128-bit AES security processor • MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers • 500 & 667kbps data rate modes • Integrated sleep oscillator for low power • On chip power regulation for 2.0V to 3.6V battery operation • Deep sleep current 100nA • Sleep current with active sleep timer 1.25µA • <$0.50 external component cost • Rx current 17.5mA • Tx current 15.0mA • Receiver sensitivity -95dBm • Transmit power 2.5dBm Features: Microcontroller • Low power 32-bit RISC CPU, 4 to 32MHz clock speed • Variable instruction width for high coding efficiency • Multi-stage instruction pipeline • 128kB ROM and 128kB RAM for bootloaded program code & data • JTAG debug interface • 4-input 12-bit ADC, 2 12-bit DACs, 2 comparators • 3 application timer/counters, • 2 UARTs • SPI port with 5 selects • 2-wire serial interface • 4-wire digital audio interface • Watchdog timer • Low power pulse counters • Up to 21 DIO Industrial temp (-40°C to +85°C) 8x8mm 56-lead Punched QFN Lead-free and RoHS compliant The JN5148-001 is an ultra low power, high performance wireless microcontroller targeted at JenNet and ZigBee PRO networking applications. The device features an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multistage instruction pipeline and low power operation with programmable clock speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver, 128kB of ROM, 128kB of RAM, and a rich mix of analogue and digital peripherals. The large memory footprint allows the device to run both a network stack (e.g. ZigBee PRO) and an embedded application or in a coprocessor mode. The operating current is below 18mA, allowing operation direct from a coin cell. Enhanced peripherals include low power pulse counters running in sleep mode designed for pulse counting in AMR applications and a unique Time of Flight ranging engine, allowing accurate location services to be implemented on wireless sensor networks. It also includes a 4-wire I2 S audio interface, to interface directly to mainstream audio CODECs, as well as conventional MCU peripherals. Block Diagram 32-bit RISC CPU Timers UAR Ts 12-bit ADC, Comparators 12-bit DACs, Temp Sensor 2-Wire Serial RAM SPI 128kB 128-bit AES Encryption Accelerator 2.4GHz Radio ROM 128kB Power Management XTAL O-QPSK Modem IEEE802.15.4 MAC Accelerator 32-byte OTP eFuse 4-Wire Audio Sleep Counters Time of Flight Engine Watchdog Timer Benefits • Single chip integrates transceiver and microcontroller for wireless sensor networks • Large memory footprint to run ZigBee PRO or JenNet together with an application • Very low current solution for long battery life • Highly featured 32-bit RISC CPU for high performance and low power • System BOM is low in component count and cost • Extensive user peripherals Applications • Robust and secure low power wireless applications • ZigBee PRO and JenNet networks • Smart metering (e.g. AMR) • Home and commercial building automation • Location Aware services – e.g. Asset Tracking • Industrial systems • Telemetry • Remote Control • Toys and gaming peripherals2 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Contents 1 Introduction 6 1.1 Wireless Transceiver 6 1.2 RISC CPU and Memory 6 1.3 Peripherals 7 1.4 Block Diagram 8 2 Pin Configurations 9 2.1 Pin Assignment 10 2.2 Pin Descriptions 12 2.2.1 Power Supplies 12 2.2.2 Reset 12 2.2.3 32MHz Oscillator 12 2.2.4 Radio 12 2.2.5 Analogue Peripherals 13 2.2.6 Digital Input/Output 13 3 CPU 15 4 Memory Organisation 16 4.1 ROM 16 4.2 RAM 17 4.3 OTP eFuse Memory 17 4.4 External Memory 17 4.4.1 External Memory Encryption 18 4.5 Peripherals 18 4.6 Unused Memory Addresses 18 5 System Clocks 19 5.1 16MHz System Clock 19 5.1.1 32MHz Oscillator 19 5.1.2 24MHz RC Oscillator 19 5.2 32kHz System Clock 20 5.2.1 32kHz RC Oscillator 20 5.2.2 32kHz Crystal Oscillator 20 5.2.3 32kHz External Clock 20 6 Reset 21 6.1 Internal Power-on Reset 21 6.2 External Reset 22 6.3 Software Reset 22 6.4 Brown-out Detect 23 6.5 Watchdog Timer 23 7 Interrupt System 24 7.1 System Calls 24 7.2 Processor Exceptions 24 7.2.1 Bus Error 24 7.2.2 Alignment 24 7.2.3 Illegal Instruction 24 7.2.4 Stack Overflow 24 7.3 Hardware Interrupts 25© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 3 8 Wireless Transceiver 26 8.1 Radio 26 8.1.1 Radio External Components 27 8.1.2 Antenna Diversity 27 8.2 Modem 29 8.3 Baseband Processor 30 8.3.1 Transmit 30 8.3.2 Reception 30 8.3.3 Auto Acknowledge 31 8.3.4 Beacon Generation 31 8.3.5 Security 31 8.4 Security Coprocessor 31 8.5 Location Awareness 31 8.6 Higher Data Rates 32 9 Digital Input/Output 33 10 Serial Peripheral Interface 35 11 Timers 38 11.1 Peripheral Timer/Counters 38 11.1.1 Pulse Width Modulation Mode 39 11.1.2 Capture Mode 39 11.1.3 Counter/Timer Mode 40 11.1.4 Delta-Sigma Mode 40 11.1.5 Example Timer / Counter Application 41 11.2 Tick Timer 41 11.3 Wakeup Timers 42 11.3.1 RC Oscillator Calibration 43 12 Pulse Counters 44 13 Serial Communications 45 13.1 Interrupts 46 13.2 UART Application 46 14 JTAG Debug Interface 47 15 Two-Wire Serial Interface 48 15.1 Connecting Devices 48 15.2 Clock Stretching 49 15.3 Master Two-wire Serial Interface 49 15.4 Slave Two-wire Serial Interface 50 16 Four-Wire Digital Audio Interface 51 17 Random Number Generator 53 18 Sample FIFO 54 19 Intelligent Peripheral Interface 55 19.1 Data Transfer Format 55 19.2 JN5148 (Slave) Initiated Data Transfer 56 19.3 Remote (Master) Processor Initiated Data Transfer 564 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 20 Analogue Peripherals 58 20.1 Analogue to Digital Converter 59 20.1.1 Operation 59 20.1.2 Supply Monitor 60 20.1.3 Temperature Sensor 60 20.2 Digital to Analogue Converter 60 20.2.1 Operation 60 20.3 Comparators 61 21 Power Management and Sleep Modes 62 21.1 Operating Modes 62 21.1.1 Power Domains 62 21.2 Active Processing Mode 62 21.2.1 CPU Doze 62 21.3 Sleep Mode 62 21.3.1 Wakeup Timer Event 63 21.3.2 DIO Event 63 21.3.3 Comparator Event 63 21.3.4 Pulse Counter 63 21.4 Deep Sleep Mode 63 22 Electrical Characteristics 64 22.1 Maximum Ratings 64 22.2 DC Electrical Characteristics 64 22.2.1 Operating Conditions 64 22.2.2 DC Current Consumption 65 22.2.3 I/O Characteristics 66 22.3 AC Characteristics 66 22.3.1 Reset and Voltage Brown-Out 66 22.3.2 SPI MasterTiming 68 22.3.3 Intelligent Peripheral (SPI Slave) Timing 68 22.3.4 Two-wire Serial Interface 69 22.3.5 Four-Wire Digital Audio Interface 70 22.3.6 Wakeup and Boot Load Timings 70 22.3.7 Bandgap Reference 71 22.3.8 Analogue to Digital Converters 71 22.3.9 Digital to Analogue Converters 72 22.3.10 Comparators 73 22.3.11 32kHz RC Oscillator 73 22.3.12 32kHz Crystal Oscillator 74 22.3.13 32MHz Crystal Oscillator 74 22.3.14 24MHz RC Oscillator 75 22.3.15 Temperature Sensor 75 22.3.16 Radio Transceiver 76© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 5 Appendix A Mechanical and Ordering Information 81 A.1 56-pin QFN Package Drawing 81 A.2 PCB Decal 82 A.3 Ordering Information 83 A.4 Device Package Marking 84 A.5 Tape and Reel Information 85 A.5.1 Tape Orientation and Dimensions 85 A.5.2 Reel Information: 180mm Reel 86 A.5.3 Reel Information: 330mm Reel 87 A.5.4 Dry Pack Requirement for Moisture Sensitive Material 87 Appendix B Development Support 88 B.1 Crystal Oscillators 88 B.1.1 Crystal Equivalent Circuit 88 B.1.2 Crystal Load Capacitance 88 B.1.3 Crystal ESR and Required Transconductance 89 B.2 32MHz Oscillator 90 B.3 32kHz Oscillator 92 B.4 JN5148 Module Reference Designs 94 B.4.1 Schematic Diagram 94 B.4.2 PCB Design and Reflow Profile 96 Related Documents 97 RoHS Compliance 97 Status Information 97 Disclaimers 98 Trademarks 98 Version Control 99 Contact Details 1006 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 1 Introduction The JN5148-001 is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including JenNet and ZigBee PRO. It includes all of the functionality required to meet the IEEE802.15.4, JenNet and ZigBee PRO specifications and has additional processor capability to run a wide range of applications including, but not limited to Smart Energy, Automatic Meter Reading, Remote Control, Home and Building Automation, Toys and Gaming. Applications that transfer data wirelessly tend to be more complex than wired ones. Wireless protocols make stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application development must consider the requirements of the wireless network in addition to the product functionality and user interfaces. To minimise this complexity, NXP provides a series of software libraries and interfaces that control the transceiver and peripherals of the JN5148. These libraries and interfaces remove the need for the developer to understand wireless protocols and greatly simplifies the programming complexities of power modes, interrupts and hardware functionality. In view of the above, the register details of the JN5148 are not provided in the datasheet. The device includes a Wireless Transceiver, RISC CPU, on chip memory and an extensive range of peripherals. Hereafter, the JN5148-001 will be referred to as JN5148. 1.1 Wireless Transceiver The Wireless Transceiver comprises a 2.45GHz radio, a modem, a baseband controller and a security coprocessor. In addition, the radio also provides an output to control transmit-receive switching of external devices such as power amplifiers allowing applications that require increased transmit power to be realised very easily. Appendix B.4, describes a complete reference design including Printed Circuit Board (PCB) design and Bill Of Materials (BOM). The security coprocessor provides hardware-based 128-bit AES-CCM* modes as specified by the IEEE802.15.4 2006 standard. Specifically this includes encryption and authentication covered by the MIC –32/ -64/ -128, ENC and ENC-MIC –32/ -64/ -128 modes of operation. The transceiver elements (radio, modem and baseband) work together to provide IEEE802.15.4 Medium Access Control (MAC) under the control of a protocol stack. Applications incorporating IEEE802.15.4 functionality can be rapidly developed by combining user-developed application software with a protocol stack library. 1.2 RISC CPU and Memory A 32-bit RISC CPU allows software to be run on chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN5148 has a unified memory architecture, code memory, data memory, peripheral devices and I/O ports are organised within the same linear address space. The device contains 128kbytes of ROM, 128kbytes of RAM and a 32-byte One Time Programmable (OTP) eFuse memory. © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 7 1.3 Peripherals The following peripherals are available on chip: • Master SPI port with five select outputs • Two UARTs with support for hardware or software flow control • Three programmable Timer/Counters – all three support Pulse Width Modulation (PWM) capability, two have capture/compare facility • Two programmable Sleep Timers and a Tick Timer • Two-wire serial interface (compatible with SMbus and I2 C) supporting master and slave operation • Four-wire digital audio interface (compatible with I²S) • Slave SPI port for Intelligent peripheral mode (shared with digital I/O) • Twenty-one digital I/O lines (multiplexed with peripherals such as timers and UARTs) • Four channel, 12-bit, Analogue to Digital converter • Two 12-bit Digital to Analogue converters • Two programmable analogue comparators • Internal temperature sensor and battery monitor • Time Of Flight ranging engine • Two low power pulse counters • Random number generator • Watchdog Timer and Voltage Brown-out • Sample FIFO for digital audio interface or ADC/DAC • JTAG hardware debug port User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. 8 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 1.4 Block Diagram 32-bit RISC CPU Reset SPI Master MUX UART0 UART1 Wakeup Timer1 Wakeup Timer0 Security Coprocessor DIO6/TXD0/JTAG_TDO DIO7/RXD0/JTAG_TDI DIO4/CTS0/JTAG_TCK DIO5/RTS0/JTAG_TMS DIO19/TXD1/JTAG_TDO DIO17/CTS1/IP_SEL/DAI_SCK/ JTAG_TCK DIO18/RTS1/IP_INT/DAI_SDOUT/ JTAG_TMS Digital Baseband Radio Programmable Interrupt Controller Timer0 2-wire Interf ace Timer1 SPICLK DIO10/TIM0OUT/32KXTALOUT SPIMOSI SPIMISO SPISEL0 DIO0/SPISEL1 DIO3/SPISEL4/RFTX DIO2/SPISEL3/RFRX DIO1/SPISEL2/PC0 DIO9/TIM0CAP/32KXTALIN/32KIN DIO8/TIM0CK_GT/PC1 DIO13/TIM1OUT/ADE/DAI_SDIN DIO11/TIM1CK_GT/TIM2OUT DIO12/TIM1CAP/ADO/DAI_WS DIO14/SIF_CLK/IP_CLK DIO15/SIF_D/IP_DO DIO16/RXD1/IP_DI/JTAG_TDI From Peripherals RESETN Wireless Transceiv er 32MHz Clock Generator XTAL_IN XTAL_OUT RF_IN VCOTUNE Tick Timer Voltage Regulators 1.8V VDD1 VDD2 Intelligent Peripheral IBAIS VB_XX Clock Divider Multiplier Timer2 SPISEL1 SPISEL2 SPISEL3 SPISEL4 TXD0 RXD0 RTS0 CTS0 TXD1 RXD1 RTS1 CTS1 TIM0CK_GT TIM0CAP TIM0OUT TIM1CK_GT TIM1CAP TIM1OUT TIM2OUT SIF_D SIF_CLK IP_DO IP_DI IP_INT IP_CLK IP_SEL 4-wire Digital Audio Interf ace I2S_OUT I2S_DIN I2S_CLK I2S_SYNC Pulse Counters PC0 PC1 JTAG Debug JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO RAM 128kB ROM 128kB OTP eFuse 32kHz RC Osc 32kHz Clock Select 32KIN 32kHz Clock Gen 32KXTALIN 32KXTALOUT Antenna Div ersity ADO ADE Time Of Flight Sample FIFO DIO20/RXD1/JTAG_TDI 24MHz RC Osc Comparator2 COMP2P COMP2M COMP1P/ Comparator1 EXT_PA_C COMP1M/ EXT_PA_B DAC1 DAC2 DAC1 DAC2 ADC M U ADC4 X ADC1 ADC2 ADC3 Temperature Sensor Supply Monitor CPU and 16MHz System Clock Watchdog Timer Brown-out Detect Figure 1: JN5148 Block Diagram DIO 16/IP_DI© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 9 2 Pin Configurations DIO16/RXD 1/IP_DI/JTAG_TDI DIO17/CTS1/IP_SEL/DAI_SC K/JTAG_TCK VSS3 DIO18/RTS1/IP_INT/DAI_SDOUT/JTAG_TMS DIO19/TXD1/JTAG_TDO VSS2 VSSS XTAL_OUT XTAL_IN VB_SYNTH VCOTUNE VB_VCO VDD1 IBIAS VREF VB_RF2 RF_IN VB_RF COMP1M COMP1P ADC1 ADC2 ADC3 ADC4 COMP2M COMP2P VB_A NC DAC1 DAC2 DIO20/RXD 1/JTAG_TDI VSS1 SPICLK SPIMISO VB_RAM SPIMOSI SPISEL0 DIO0/SPISEL1 RESETN VB_DIG DIO1/SPISEL2/PC0 DIO2/SPISEL3/RFRX DIO15/SIF_D/IP_DO DIO14/SIF_C LK/IP_CLK DIO13/T IM1OUT/ADE/DAI_SDIN DIO12/T IM1CAP/ADO/DAI_WS DIO11/T IM1CK_GT /TIM2OUT DIO10/T IM0OUT/32KXT ALOUT DIO9/TIM0CAP/32KXT ALIN/32KIN VDD2 DIO8/TIM0CK_GT/PC 1 DIO7/RXD0/JT AG_TDI DIO6/TXD0/JTAG_TDO DIO5/RTS0/JTAG_TMS DIO4/CTS0/JTAG_TCK DIO3/SPISEL4/RFTX VSSA (Paddl e) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Figure 2: 56-pin QFN Configuration (top view) Note: Please refer to Appendix B.4 JN5148 Module Reference Design for important applications information regarding the connection of the PADDLE to the PCB. DIO 16/IP_DI10 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 2.1 Pin Assignment Pin No Power supplies Signal Type Description 10, 12, 16, 18, 27, 35, 40 VB_SYNTH, VB_VCO, VB_RF2, VB_RF, VB_A, VB_RAM, VB_DIG 1.8V Regulated supply voltage 13, 49 VDD1, VDD2 3.3V Supplies: VDD1 for analogue, VDD2 for digital 32, 6, 3, 7, Paddle VSS1, VSS2, VSS3, VSSS, VSSA 0V Grounds (see appendix A.2 for paddle details) 28 NC No connect General 39 RESETN CMOS Reset input 8, 9 XTAL_OUT, XTAL_IN 1.8V System crystal oscillator Radio 11 VCOTUNE 1.8V VCO tuning RC network 14 IBIAS 1.8V Bias current control 17 RF_IN 1.8V RF antenna Analogue Peripheral I/O 21, 22, 23, 24 ADC1, ADC2, ADC3, ADC4 3.3V ADC inputs 15 VREF 1.8V Analogue peripheral reference voltage 29, 30 DAC1, DAC2 3.3V DAC outputs 19, 20 COMP1M/EXT_PA_B, COMP1P/EXT_PA_C 3.3V Comparator 1 inputs and external PA control 25, 26 COMP2M, COMP2P 3.3V Comparator 2 inputs Digital Peripheral I/O Primary Alternate Functions 33 SPICLK CMOS SPI Clock Output 36 SPIMOSI CMOS SPI Master Out Slave In Output 34 SPIMISO CMOS SPI Master In Slave Out Input 37 SPISEL0 CMOS SPI Slave Select Output 0 38 DIO0 SPISEL1 CMOS DIO0 or SPI Slave Select Output 1 41 DIO1 SPISEL2 PC0 CMOS DIO1, SPI Slave Select Output 2 or Pulse Counter0 Input 42 DIO2 SPISEL3 RFRX CMOS DIO2, SPI Slave Select Output 3 or Radio Receive Control Output 43 DIO3 SPISEL4 RFTX CMOS DIO3, SPI Slave Select Output 4 or Radio Transmit Control Output 44 DIO4 CTS0 JTAG_TCK CMOS DIO4, UART 0 Clear To Send Input or JTAG CLK 45 DIO5 RTS0 JTAG_TMS CMOS DIO5, UART 0 Request To Send Output or JTAG Mode Select 46 DIO6 TXD0 JTAG_TDO CMOS DIO6, UART 0 Transmit Data Output or JTAG Data Output 47 DIO7 RXD0 JTAG_TDI CMOS DIO7, UART 0 Receive Data Input or JTAG Data Input 48 DIO8 TIM0CK_GT PC1 CMOS DIO8, Timer0 Clock/Gate Input or Pulse Counter1 Input 50 DIO9 TIM0CAP 32KXTALIN 32KIN CMOS DIO9, Timer0 Capture Input, 32K External Crystal Input or 32K Clock Input© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 11 Pin No Digital Peripheral I/O Signal Type Description Primary Alternate Functions 51 DIO10 TIM0OUT 32KXTALOUT CMOS DIO10, Timer0 PWM Output or 32K External Crystal Output 52 DIO11 TIM1CK_GT TIM2OUT CMOS DIO11, Timer1 Clock/Gate Input or Timer2 PWM Output 53 DIO12 TIM1CAP ADO DAI_WS CMOS DIO12, Timer1 Capture Input, Antenna Diversity or Digital Audio Word Select 54 DIO13 TIM1OUT ADE DAI_SDIN CMOS DIO13, Timer1 PWM Output, Antenna Diversity or Digital Audio Data Input 55 DIO14 SIF_CLK IP_CLK CMOS DIO14, Serial Interface Clock or Intelligent Peripheral Clock Input 56 DIO15 SIF_D IP_DO CMOS DIO15, Serial Interface Data or Intelligent Peripheral Data Out 1 DIO16 IP_DI CMOS DIO16 or Intelligent Peripheral Data In 2 DIO17 CTS1 IP_SEL DAI_SCK JTAG_TCK CMOS DIO17, UART 1 Clear To Send Input, Intelligent Peripheral Device Select Input or Digital Audio Clock or JTAG CLK 4 DIO18 RTS1 IP_INT DAI_SDOUT JTAG_TMS CMOS DIO18, UART 1 Request To Send Output, Intelligent Peripheral Interrupt Output or Digital Audio Data Output or JTAG Mode Select 5 DIO19 TXD1 JTAG_TDO CMOS DIO19 or UART 1 Transmit Data Output or JTAG Data Out 31 DIO 20 RXD1 JTAG_TDI CMOS DIO 20, UART 1 Receive Data Input or JTAG data In The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.12 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 2.2 Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 is the power supply for the digital circuitry; and should also be decoupled to ground. A 10uF tantalum capacitor is required. Decoupling pins for the internal 1.8V regulators are provided which require a 100nF capacitor located as close to the device as practical. VB_RF, VB_A and VB_SYNTH should be decoupled with an additional 47pF capacitor, while VB_RAM and VB_DIG require only 100nF. VB_RF and VB_RF2 should be connected together as close to the device as practical, and only require one 100nF capacitor and one 47pF capacitor. The pin VB_VCO requires a 10nF capacitor in parallel with a 47pF capacitor. Refer to B.4.1 for schematic diagram. VSSA, VSSS, VSS1, VSS2, VSS3 are the ground pins. Users are strongly discouraged from connecting their own circuits to the 1.8v regulated supply pins, as the regulators have been optimised to supply only enough current for the internal circuits. 2.2.2 Reset RESETN is a bi-directional active low reset pin that is connected to a 40kΩ internal pull-up resistor. It may be pulled low by an external circuit, or can be driven low by the JN5148 if an internal reset is generated. Typically, it will be used to provide a system reset signal. Refer to section 6.2, External Reset, for more details. 2.2.3 32MHz Oscillator A crystal is connected between XTALIN and XTALOUT to form the reference oscillator, which drives the system clock. A capacitor to analogue ground is required on each of these pins. Refer to section 5.1 16MHz System Clock for more details. The 32MHz reference frequency is divided down to 16MHz and this is used as the system clock throughout the device. 2.2.4 Radio The radio is a single ended design, requiring a capacitor and just two inductors to match to 50Ω microstrip line to the RF_IN pin. An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and references within the radio.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 13 2.2.5 Analogue Peripherals Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference. There are four ADC inputs, two pairs of comparator inputs and two DAC outputs. The analogue I/O pins on the JN5148 can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in Figure 3: Analogue I/O Cell In reset and deep sleep, the analogue peripherals are all off and the DAC outputs are in a high impedance state. In sleep, the ADC and DACs are off, with the DAC outputs in high impedance state. The comparators may optionally be used as a wakeup source. Unused ADC and comparator inputs should be left unconnected. VDD1 Analogue I/O Pin VSSA Analogue Peripheral Figure 3: Analogue I/O Cell 2.2.6 Digital Input/Output Digital I/O pins on the JN5148 can have signals applied up to 2V higher than VDD2 (with the exception of pins DIO9 and DIO10 that are 3V tolerant) and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these pins see section 22.2.3 I/O Characteristics. When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal pull up resistors (40kΩ nominal) that can be disabled. When used in their secondary function (selected when the appropriate peripheral block is enabled through software library calls) then their direction is fixed by the function. The pull up resistor is enabled or disabled independently of the function and direction; the default state from reset is enabled. A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic.14 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 I O IE VDD2 VSS Pu RPU RPROT OE DIO[x] Pin Figure 4: DIO Pin Equivalent Schematic In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5148 from sleep.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 15 3 CPU The CPU of the JN5148 is a 32-bit load and store RISC processor. It has been architected for three key requirements: • Low power consumption for battery powered applications • High performance to implement a wireless protocol at the same time as complex applications • Efficient coding of high-level languages such as C provided with the NXP Software Developer’s Kit It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the same address space. Registers for peripheral units, such as the timers, UARTs and the baseband processor are also mapped into this space. The CPU has access to a block of 15 32-bit General-Purpose (GP) registers together with a small number of special purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle while those that access memory require a further cycle to allow the memory to respond. The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms needed by Digital Signal Processing applications. The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in complex data structures is very efficient due to the provision of several addressing modes, together with the ability to be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming method for the JN5148 is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger. The CPU architecture also contains features that make the processor suitable for embedded, real-time applications. In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the processor. To provide protection for device-wide resources being altered by one task and affecting another, the processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in user mode in a RTOS environment. Embedded applications require efficient handling of external hardware events. When using JenOS, prioritised interrupts are supported, with 15 priority levels, and can be configured as required by the application. To improve power consumption a number of power-saving modes are implemented in the JN5148, described more fully in section 21 - Power Management and Sleep Modes. One of these modes is the CPU doze mode; under software control, the processor can be shut down and on an interrupt it will wake up to service the request. Additionally, it is possible under software control, to set the speed of the CPU to 4, 8, 16 or 32MHz. This feature can be used to trade-off processing power against current consumption.16 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 4 Memory Organisation This section describes the different memories found within the JN5148. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space. 0x00000000 0x00020000 RAM (128kB) 0xF0000000 0xFFFFFFFF Unpopulated ROM (128kB) 0xF0020000 RAM Echo 0x04000000 Peripherals 0x02000000 Figure 5: JN5148 Memory Map 4.1 ROM The ROM is 128k bytes in size, and can be accessed by the processor in a single CPU clock cycle. The ROM contents include bootloader to allow external Flash memory contents to be bootloaded into RAM at runtime, a default interrupt vector table, an interrupt manager, IEEE802.15.4 MAC and APIs for interfacing on-chip peripherals. The operation of the boot loader is described in detail in Application Note [7]. The interrupt manager routes interrupt calls to the application’s soft interrupt vector table contained within RAM. Section 7 contains further information regarding the handling of interrupts. ROM contents are shown in Figure 6. Interrupt Vectors Interrupt Manager Boot Loader IEEE802.15.4 Stack 0x00000000 0x00020000 APIs Spare Figure 6: Typical ROM contents© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 17 4.2 RAM The JN5148 contains 128kBytes of high speed RAM. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered. Typical RAM contents are shown in Figure 7. MAC Data Interrupt Vector Table Application CPU Stack (Grows Down) 0x04000000 0x04020000 MAC Address Figure 7: Typical RAM Contents 4.3 OTP eFuse Memory The JN5148 contains a total of 32bytes of eFuse memory; this is a One Time Programmable (OTP) memory that can be used to support on chip 64-bit MAC ID and a 128-bit AES security key. A limited number of bits are available for customer use for storage of configuration information; configuration of these is made through use of software APIs. For further information on how to program and use the eFuse memory, please contact technical support via the online tech-support system. Alternatively, NXP can provide an eFuse programming service for customers that wish to use the eFuse but do not wish to undertake this for themselves. For further details of this service, please contact your local NXP sales office. 4.4 External Memory An external memory with an SPI interface may be used to provide storage for program code and data for the device when external power is removed. The memory is connected to the SPI interface using select line SPISEL0; this select line is dedicated to the external memory interface and is not available for use with other external devices. See Figure 8 for connection details. JN5148 Serial Memory SPISEL0 SPIMISO SPIMOSI SPICLK SS SDO SDI CLK Figure 8: Connecting External Serial Memory18 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash memory devices that are supported as standard through the JN5148 bootloader are given in Table 1. NXP recommends that where possible one of these devices should be selected. Manufacturer Device Number SST (Silicon Storage Technology) 25VF010A (1Mbit device) Numonyx M25P10-A (1Mbit device), M25P40 (4Mbit device) Table 1: Supported Flash Memories Applications wishing to use an alternate Flash memory device should refer to application note [2] JN-AN-1038 Programming Flash devices not supported by the JN51xx ROM-based bootloader. This application note provides guidance on developing an interface to an alternate device. 4.4.1 External Memory Encryption The contents of the external serial memory may be encrypted. The AES security processor combined with a user programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is stored in eFuse. When bootloading program code from external serial memory, the JN5148 automatically accesses the encryption key to execute the decryption process. User program code does not need to handle any of the decryption process; it is transparent. With encryption enabled, the time taken to boot code from external flash is increased. 4.5 Peripherals All peripherals have their registers mapped into the memory space. Access to these registers requires 3 clock cycles. Applications have access to the peripherals through the software libraries that present a high-level view of the peripheral’s functions through a series of dedicated software routines. These routines provide both a tested method for using the peripherals and allow bug-free application code to be developed more rapidly. For details, see the JN51xx Integrated Peripherals API User Guide (JN-UG-3066)[5]. 4.6 Unused Memory Addresses Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 19 5 System Clocks Two system clocks are used to provide timing references into the on-chip subsystems of the JN5148. A 16MHz clock, generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. A 32kHz clock is used by the sleep timer and during the startup phase of the chip. 5.1 16MHz System Clock The 16MHz system clock is used by the digital and analogue peripherals and the transceiver. A scaled version (4,8,16 or 32MHz) of this clock is also used by the processor and memories. For most operations it is necessary to source this clock from the 32MHz oscillator. Crystal oscillators are generally slow to start. Hence to provide a faster start-up following a sleep cycle a fast RC oscillator is provided that can be used as the source for the 16MHz system clock. The oscillator starts very quickly and is typically 24MHz causing the system clock to run at 12MHz. Using a clock of this speed scales down the speed of the processor and any peripherals in use. For the SPI interface this causes no functional issues as the generated SPI clock is slightly slower and is used to clock the external SPI slave. Use of the radio is not possible when using the 24MHz RC oscillator. Additionally, timers and UARTs should not be used as the exact frequency will not be known. The JN5148 device can be configured to wake up from sleep using the fast RC oscillator and automatically switch over to use the 32MHz xtal as the clock source, when it has started up. This could allow application code to be downloaded from the flash before the xtal is ready, typically improving start-up time by 550usec. Alternatively, the switch over can be controlled by software, or the system could always use the 32MHz oscillator as the clock source. 5.1.1 32MHz Oscillator The JN5148 contains the necessary on chip components to build a 32MHz reference oscillator with the addition of an external crystal resonator and two tuning capacitors. The schematic of these components are shown in Figure 9. The two capacitors, C1 and C2, should typically be 15pF and use a COG dielectric. Due to the small size of these capacitors, it is important to keep the traces to the external components as short as possible. The on chip transconductance amplifier is compensated for temperature variation, and is self-biasing by means of the internal resistor R1. The electrical specification of the oscillator can be found in section 22.3.13. Please refer to Appendix B for development support with the crystal oscillator circuit. XTALOUT C1 C2 R1 XTALIN JN5148 Figure 9: 32MHz Crystal Oscillator Connections 5.1.2 24MHz RC Oscillator An on-chip 24MHz RC oscillator is provided. No external components are required for this oscillator. The electrical specification of the oscillator can be found in section 22.3.14.20 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 5.2 32kHz System Clock The 32kHz system clock is used for timing the length of a sleep period (see section 21 Power Management and Sleep Modes) and also to generate the system clock used internally during reset. The clock can be selected from one of three sources through the application software: • 32kHz RC Oscillator • 32kHz Crystal Oscillator • 32kHz External Clock Upon a chip reset or power-up the JN5148 defaults to using the internal 32kHz RC Oscillator. If another clock source is selected then it will remain in use for all 32kHz timing until a chip reset is performed. 5.2.1 32kHz RC Oscillator The internal 32kHz RC oscillator requires no external components. The internal timing components of the oscillator have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz ±30%. To make this useful as a timing source for accurate wakeup from sleep, a frequency calibration factor derived from the more accurate 16MHz clock may be applied. The calibration factor is derived through software, details can be found in section 11.3.1. For detailed electrical specifications, see section 22.3.11. 5.2.2 32kHz Crystal Oscillator In order to obtain more accurate sleep periods, the JN5148 contains the necessary on-chip components to build a 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between 32KXTALIN and 32KXTALOUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. Due to the small size of the capacitors, it is important to keep the traces to the external components as short as possible. The electrical specification of the oscillator can be found in section 22.3.12. The oscillator cell is flexible and can operate with a range of commonly available 32.768kHz crystals with load capacitances from 6 to 12.5pF. However, the maximum ESR of the crystal and the supply current are both functions of the actual crystal used, see appendix B.1 for more details. 32KXTALIN 32KXTALOUT JN5148 Figure 10: 32kHz crystal oscillator connections 5.2.3 32kHz External Clock An externally supplied 32kHz reference clock on the 32KIN input (DIO9) may be provided to the JN5148. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate sleep cycle timings compared to the internal RC oscillator. (See section 22.2.3 I/O Characteristics, DIO9 is a 3V tolerant input)© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 21 6 Reset A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5148 goes through is as follows. When power is applied, the 32kHz RC oscillator starts up and stabilises, which takes approximately 100µsec. At this point, the 32MHz crystal oscillator is enabled and power is applied to the processor and peripheral logic. The logic blocks are held in reset until the 32MHz crystal oscillator stabilises, typically this takes 0.75ms. Then the internal reset is removed from the CPU and peripheral logic and the CPU starts to run code beginning at the reset vector, consisting of initialisation code and the resident boot loader. [7] Section 22.3.1 provides detailed electrical data and timing. The JN5148 has five sources of reset: • Internal Power-on Reset • External Reset • Software Reset • Watchdog timer • Brown-out detect Note: When the device exits a reset condition, device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, then the device must be held in reset until the operating conditions are met. (See section 22.3) 6.1 Internal Power-on Reset For the majority of applications the internal power-on reset is capable of generating the required reset signal. When power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD reaches the specified threshold, the reset signal is generated and can be observed as a rising edge on the RESETN pin. This signal is held internally until the power supply and oscillator stabilisation time has elapsed, when the internal reset signal is then removed and the CPU is allowed to run. RESETN Pin Internal RESET VDD Figure 11: Internal Power-on Reset When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. Use of the external reset circuit show in Figure 12 is suggested. 22 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 RESETN C1 R1 JN5148 VDD 18k 470nF Figure 12: External Reset Generation The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin. 6.2 External Reset An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The JN5148 is held in reset while the RESETN pin is low. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the internal reset process starts. Multiple devices may connect to the RESETN pin in an open-collector mode. The JN5148 has an internal pull-up resistor connect to the RESETN pin. The pin is an input for an external reset, an output during the power-on reset and may optionally be an output during a software reset. No devices should drive the RESETN pin high. Internal Reset RESETN pin Reset Figure 13: External Reset 6.3 Software Reset A system reset can be triggered at any time through software control, causing a full chip reset and invalidating the RAM contents. For example this can be executed within a user’s application upon detection of a system failure. When performing the reset, the RESETN pin is driven low for 1µsec; depending on the external components this may or may not be visible on the pin. In addition, the RESETN line can be driven low by the JN5148 to provide a reset to other devices in the system (e.g. external sensors) without resetting itself. When the RESETN line is not driven it will pull back high through either the internal pull-up resistor or any external circuitry. It is essential to ensure that the RESETN line pulls back high within 100µsec after the JN5148 stops driving the line; otherwise a system reset will occur. Due to this, careful consideration should be taken of any capacitance on this line. For instance, the RC values recommended in section 6.1 may need to be replaced with a suitable reset IC© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 23 6.4 Brown-out Detect An internal brown-out detect module is used to monitor the supply voltage to the JN5148; this can be used whilst the device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN5148 to perform a chip reset. Equally, dips in the supply voltage can be detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it. The brown-out detect is enabled by default from power-up and can extend the reset during power-up. This will keep the CPU in reset until the voltage exceeds the brown-out threshold voltage. The threshold voltage is configurable to 2.0V, 2.3V, 2.7V and 3.0V and is controllable by software. From power-up the threshold is set by eFuse settings and the default chip configuration is for the 2.3V threshold. It is recommended that the threshold is set so that, as a minimum, the chip is held in reset until the voltage reaches the level required by the external memory device on the SPI interface. 6.5 Watchdog Timer A watchdog timer is provided to guard against software lockups. It operates by counting cycles of the 32kHz system clock. A pre-scaler is provided to allow the expiry period to be set between typically 8ms and 16.4 seconds. Failure to restart the watchdog timer within the pre-configured timer period will cause a chip reset to be performed. A status bit is set if the watchdog was triggered so that the software can differentiate watchdog initiated resets from other resets, and can perform any required recovery once it restarts. If the source of the 32kHz system clock is the 32kHz RC oscillator then the watchdog expiry periods are subject to the variation in period of the RC oscillator. After power up, reset, start from deep sleep or start from sleep, the watchdog is always enabled with the largest timeout period and will commence counting as if it had just been restarted. Under software control the watchdog can be disabled. If it is enabled, the user must regularly restart the watchdog timer to stop it from expiring and causing a reset. The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if enabled once the debugger un-stalls the CPU. 24 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 7 Interrupt System The interrupt system on the JN5148 is a hardware-vectored interrupt system. The JN5148 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor mode. Interrupt sources and their vector locations are listed in Table 2 below: Interrupt Source Vector Location Interrupt Definition Bus error 0x08 Typically cause by an attempt to access an invalid address or a disabled peripheral Tick timer 0x0e Tick timer interrupt asserted Alignment error 0x14 Load/store address to non-naturally-aligned location Illegal instruction 0x1a Attempt to execute an unrecognised instruction Hardware interrupt 0x20 interrupt asserted System call 0x26 System call initiated by b.sys instruction Trap 0x2c caused by the b.trap instruction or the debug unit Reset 0x38 Caused by software or hardware reset. Stack Overflow 0x3e Stack overflow Table 2: Interrupt Vectors 7.1 System Calls The b.trap and b.sys instructions allow processor exceptions to be generated by software. A system call exception will be generated when the b.sys instruction is executed. This exception can, for example, be used to enable a task to switch the processor into supervisor mode when a real time operating system is in use. (See section 3 for further details.) The b.trap instruction is commonly used for trapping errors and for debugging. 7.2 Processor Exceptions 7.2.1 Bus Error A bus error exception is generated when software attempts to access a memory address that does not exist, or is not populated with memory or peripheral registers or when writing to ROM. 7.2.2 Alignment Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are 0xFFF0, 0xFFF4, 0xFFF8 etc. 7.2.3 Illegal Instruction If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal instruction exception. 7.2.4 Stack Overflow When enabled, a stack overflow exception occurs if the stack pointer reaches a programmable location.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 25 7.3 Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals library [5]. For details of the interrupts generated from each peripheral see the respective section in this datasheet. Interrupts can be used to wake the JN5148 from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and analogue comparator interrupts remain powered to bring the JN5148 out of sleep. Prioritised external interrupt handling (i.e., interrupts from hardware peripherals) is provided to enable an application to control an events priority to provide for deterministic program execution. The priority Interrupt controller provides 15 levels of prioritised interrupts. The priority level of all interrupts can be set, with value 0 being used to indicate that the source can never produce an external interrupt, 1 for the lowest priority source(s) and 15 for the highest priority source(s). Note that multiple interrupt sources can be assigned the same priority level if desired. If while processing an interrupt, a new event occurs at the same or lower priority level, a new external interrupt will not be triggered. However, if a new higher priority event occurs, the external interrupt will again be asserted, interrupting the current interrupt service routine. Once the interrupt service routine is complete, lower priority events can be serviced. 26 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 8 Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standardsbased wireless transceiver that transmits and receives data over the air in the unlicensed 2.4GHz band. 8.1 Radio Figure 14 shows the single ended radio architecture. LNA synth PA ADC Reference & Bias Switch Radio Calibration Lim1 Lim2 Lim3 Lim4 sigma delta D-Type Figure 14: Radio Architecture The radio comprises a low-IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matching network, which consists of two inductors and a capacitor, this arrangement creates a 50Ω port and removes the need for a balun. A 50Ω single ended antenna can be connected directly to this port. The 32MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop characteristic. The receiver chain starts with the low noise amplifier / mixer combination whose outputs are passed to a lowpass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a digital signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. To improve the performance and reduce current consumption, automatic calibration is applied to various blocks in the RX path. In the transmit direction, the digital stream from the Modem is passed to a digital sigma-delta modulator which controls the feedback dividers in the synthesiser, (dual point modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 27 8.1.1 Radio External Components In order to realise the full performance of the radio it is essential that the reference PCB layout and BOM are carefully followed. See Appendix B.4. The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to provide good noise isolation between the digital logic of the JN5148 and the analogue blocks. These regulators are also controlled by the baseband controller and protocol software to minimise power consumption. Decoupling for internal regulators is required as described in section 2.2.1, Power Supplies For single ended antennas or connectors, a balun is not required, however a matching network is needed. The RF matching network requires three external components and the IBIAS pin requires one external component as shown in schematic in B.4.1. These components are critical and should be placed close to the JN5148 pins and analogue ground as defined in Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout Constraints. Specifically, the output of the network comprising L2, C1 and L1 is designed to present an accurate match to a 50 ohm resistive network as well as provide a DC path to the final output stage or antenna. Users wishing to match to other active devices such as amplifiers should design their networks to match to 50 ohms at the output of L1 R1 43K IBIAS C20 100nF L2 2.7nH VB_RF VREF VB_RF2 RF_IN C12 47pF C3 100nF VB_RF1 C1 47pF L1 5.6nH To Coaxial Socket or Integrated Antenna VB_RF Figure 15 External Radio Components 8.1.2 Antenna Diversity Support is provided for antenna diversity. Antenna diversity is a technique that maximises the performance of an antenna system. It allows the radio to switch between two antennas that have very low correlation between their received signals. Typically, this is achieved by spacing two antennas around 0.25 wavelengths apart or by using two orthogonal polarisations. So, if a packet is transmitted and no acknowledgement is received, the radio system can switch to the other antenna for the retry, with a different probability of success. The JN5148 provides an output (ADO) on DIO12 that is asserted on odd numbered retries and optionally its complement (ADE) on DIO13, that can be used to control an antenna switch; this enables antenna diversity to be implemented easily (see Figure 16 and Figure 17).28 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Antenna A Antenna B A B COM SEL SELB ADO (DIO[12]) ADE (DIO[13]) Device RF Port RF Switch: Single-Pole, Double-Throw (SPDT) Figure 16 Simple Antenna Diversity Implementation using External RF Switch ADO (DIO[12]) TX Active RX Active ADE (DIO[13]) 1st TX-RX Cycle 2nd TX-RX Cycle (1st Retry) Figure 17 Antenna Diversity ADO Signal for TX with Acknowledgement If two DIO pins cannot be spared, DIO13 can be configured to be a normal DIO pin, and the inverse of ADO generated with an inverter on the PCB. © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 29 8.2 Modem The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard. It also provides a high data rate modes at 500 and 667kbps. AGC Demodulation Symbol Detection (Despreading) Modulation Spreading TX RX TX Data Interface RX Data Interface VCO Sigma-Delta Modulator IF Signal Gain Figure 18 Modem Architecture Features provided to support network channel selection algorithms include Energy Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel Assessment (CCA). The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the IEEE 802.15.4 ED function and LQI function. The ED and LQI are both related to receiver power in the same way, as shown in Fig19. LQI is associated with a received packet, whereas ED is an indication of signal power on air at a particular moment. The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold. Figure 19 Energy Detect Value vs Receive Power Level30 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 8.3 Baseband Processor The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to implement the sequencing of events required by the protocol and to schedule timed events with millisecond resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software layer performs the higher-layer aspects of the protocol, sending management and data messages between endpoint and coordinator nodes, using the services provided by the baseband processor. Append Checksum Verify Checksum CSMA CCA Backoff Control Deserialiser Serialiser Tx/Rx Frame Buffer Tx Bitstream Rx Bitstream Protocol Timing Engine Supervisor Radio Status Control Processor Bus Protocol Timers Security Coprocessor Decrypt Port Encrypt Port AES Codec Figure 20: Baseband Processor 8.3.1 Transmit A transmission is performed by software writing the data to be transferred into the Tx/Rx Frame Buffer, together with parameters such as the destination address and the number of retries allowed, and programming one of the protocol timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor controls the sequencing of the radio and modem to perform the type of transmission required. It can perform all the algorithms required by IEEE802.15.4 such as CSMA/CA, GTS without processor intervention including retries and random backoffs. When the transmission begins, the header of the frame is constructed from the parameters programmed by the software and sent with the frame data through the serialiser to the Modem. At the same time, the radio is prepared for transmission. During the passage of the bitstream to the modem, it passes through a CRC checksum generator that calculates the checksum on-the-fly, and appends it to the end of the frame. If using slotted access, it is possible for a transmission to overrun the time in its allocated slot; the Baseband Processor handles this situation autonomously and notifies the protocol software via interrupt, rather than requiring it to handle the overrun explicitly. 8.3.2 Reception During reception, the radio is set to receive on a particular channel. On receipt of data from the modem, the frame is directed into the Tx/Rx Frame Buffer where both header and frame data can be read by the protocol software. An interrupt may be provided on receipt of the frame header. As the frame data is being received from the modem it is passed through a checksum generator; at the end of the reception the checksum result is compared with the checksum at the end of the message to ensure that the data has been received correctly. An interrupt may be © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 31 provided to indicate successful packet reception. During reception, the modem determines the Link Quality, which is made available at the end of the reception as part of the requirements of IEEE802.15.4. 8.3.3 Auto Acknowledge Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The JN5148 baseband processor can automatically construct and send the acknowledgement packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence. The JN5148 baseband processor can also request an acknowledge for packets being transmitted and handle the reception of acknowledged packets without processor intervention. 8.3.4 Beacon Generation In beaconing networks, the baseband processor can automatically generate and send beacon frames; the repetition rate of the beacons is programmed by the CPU, and the baseband then constructs the beacon contents from data delivered by the CPU. The baseband processor schedules the beacons and transmits them without CPU intervention. 8.3.5 Security The transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm is handled by the security coprocessor and the stack software. The application software must provide the appropriate encrypt/decrypt keys for the transmission or reception. On transmission, the key can be programmed at the same time as the rest of the frame data and setup information. 8.4 Security Coprocessor The security coprocessor is available to the application software to perform encryption/decryption operations. A hardware implementation of the encryption engine significantly speeds up the processing of the encrypted packets over a pure software implementation. The AES library for the JN5148 provides operations that utilise the encryption engine in the device and allow the contents of memory buffers to be transformed. Information such as the type of security operation to be performed and the encrypt/decrypt key to be used must also be provided. Processor Interface AES Block Encrpytion Controller AES Encoder Key Generation Figure 21: Security Coprocessor Architecture 8.5 Location Awareness The JN5148 provides the ability for an application to obtain the Time Of Flight (TOF) between two network nodes. The TOF information is an alternative metric to that of the existing Energy Detect value (RSSI) that has been typically used for calculating the relative inter-nodal separation, for subsequent use in a location awareness system. For short ranges RSSI will typically give a better accuracy than TOF, however for distances above 5 to 10 meters TOF will offer significant improvements in accuracy compared to RSSI. In general, the RSSI error scales with distance, such that if the distance doubles then the error doubles.32 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 8.6 Higher Data Rates To support the demands of applications that require high data throughputs such as in audio or data streaming applications, the JN5148 supports higher data rate modes that offer 500kbps or 667kbps on air transmission rates. The switching between standard and higher data rates is controlled via software, When operating in a higher data rate mode standard IEEE802.15.4 features, such as clear channel assessment, can still be used. This allows the JN5148 in a higher data rate mode to co-exist in an IEEE802.15.4 based network (adhering to the correct bit rates and frame timing etc.) whilst at the same time providing the benefit of the higher data rate where required. When operating in a higher data rate mode, the receive sensitivity will be degraded by at least 3dB.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 33 9 Digital Input/Output There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the device, see section 2.1. Once a peripheral is enabled it takes precedence over the device pins. Refer to the individual module sections for a full description of the alternate peripherals functions. Following a reset (and whilst the reset input is held low), all peripherals are off and the DIO pins are configured as inputs with the internals pull-ups turned on. When a peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or outputs. Each pin can be controlled individually by setting the direction and then reading or writing to the pin. The individual pull-up resistors, RPU, can also be enabled or disabled as needed and the setting is held through sleep cycles. The pull-ups are generally configured once after reset depending on the external components and functionality. For instance, outputs should generally have the pull-ups disabled. An input that is always driven should also have the pull-up disabled. When configured as an input each pin can be used to generate an interrupt upon a change of state (selectable transition either from low to high or high to low); the interrupt can be enabled or disabled. When the device is sleeping, these interrupts become events that can be used to wake the device up. Equally the status of the interrupt may be read. See section 21 Power Management and Sleep Modes for further details on sleep and wakeup. The state of all DIO pins can be read, irrespective of whether the DIO is configured as an input or an output. Throughout a sleep cycle the direction of the DIO, and the state of the outputs, is held. This is based on the resultant of the GPIO Data/ Direction registers and the effect of any enabled peripherals at the point of entering sleep. Following a wake-up these directions and output values are maintained under control of the GPIO data / direction registers. Any peripherals enabled before the sleep cycle are not automatically re-enabled, this must be done through software after the wake-up. For example, if DIO0 is configured to be SPISEL1 then it becomes an output. The output value is controlled by the SPI functional block. If the device then enters a sleep cycle, the DIO will remain an output and hold the value being output when entering sleep. After wake-up the DIO will still be an output with the same value but controlled from the GPIO Data/Direction registers. It can be altered with the software functions that adjust the DIO, or the application may re-configure it to be SPISEL1. Unused DIO pins are recommended to be set as inputs with the pull-up enabled. Two DIO pins can optionally be used to provide control signals for RF circuitry (eg switches and PA) in high power range extenders. DIO3 / RFTX is asserted when the radio is in the transmit state and similarly, DIO2 / RFRX is asserted when the radio is in the receiver state.34 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 4-wire Digital Audio Interface Antenna Diversity JTAG Debug Pulse Counters Intelligent Peripheral MUX 2-wire Interface Timer2 Timer1 Timer0 UART1 UART0 SPI Master SPISEL1 SPISEL2 SPISEL3 SPISEL4 TXD0 RXD0 RTS0 CTS0 TXD1 RXD1 RTS1 CTS1 TIM0CK_GT TIM0OUT TIM0CAP TIM1CK_GT TIM1OUT TIM1CAP TIM2OUT SIF_D SIF_CLK IP_DO IP_DI IP_INT IP_CLK IP_SEL PC0 PC1 JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO ADO ADE I2S_OUT I2S_DIN I2S_CLK I2S_SYNC SPICLK SPIMOSI SPIMISO SPISEL0 DIO0/SPISEL1 DIO1/SPISEL2/PC0 DIO2/SPISEL3/RFRX DIO3/SPISEL4/RFTX DIO4/CTS0/JTAG_TCK DIO5/RTS0/JTAG_TMS DIO6/TXD0/JTAG_TDO DIO7/RXD0/JTAG_TDI DIO8/TIM0CK_GT/PC1 DIO9/TIM0CAP/32KXTALIN/32KIN DIO10/TIM0OUT/32KXTALOUT DIO11/TIM1CK_GT/TIM2OUT DIO12/TIM1CAP/ADO/DAI_WS DIO13/TIM1OUT/ADE/DAI_SDN DIO14/SIF_CLK/IP_CLK DIO15/SIF_D/IP_DO DIO16/IP_DI DIO17/CTS1/IP_SEL/DAI_SCK/ JTAG_TCK DIO18/RTS1/IP_INT/DAI_SDOUT/ JTAG_TMS DIO19/TXD1/JTAG_TDO DIO20/RXD1/JTAG_TDI Figure 22 DIO Block Diagram© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 35 10 Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5148 and peripheral devices. The JN5148 operates as a master on the SPI bus and all other devices connected to the SPI are expected to be slave devices under the control of the JN5148 CPU. The SPI includes the following features: • Full-duplex, three-wire synchronous data transfer • Programmable bit rates (up to 16Mbit/s) • Programmable transaction size up to 32-bits • Standard SPI modes 0,1,2 and 3 • Manual or Automatic slave select generation (up to 5 slaves) • Maskable transaction complete interrupt • LSB First or MSB First Data Transfer • Supports delayed read edges Clock Divider SPI Bus Cycle Controller Data Buffer DIV Clock Edge Select Data CHAR_LEN LSB SPIMISO SPIMOSI SPICLK Select Latch SPISEL [4..0] 16 MHz Figure 23: SPI Block Diagram The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously. There are three dedicated pins SPICLK, SPIMOSI, SPIMISO that are shared across all devices on the bus. MasterOut-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN5148. The JN5148 provides five slave selects, SPISEL0 to SPISEL4 to allow five SPI peripherals on the bus. SPISEL0 is a dedicated pin; this is generally connected to a serial Flash/ EEPROM memory holding application code that is downloaded to internal RAM via software from reset. SPISEL1 to 4, are alternate functions of pins DIO0 to 3 respectively. The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted between transfers when required, to enable longer transfers to be performed. When the device reset is active, the three outputs SPISEL, SPICLK and SPI_MOSI are tri-stated and SPI_MISO is set to be an input. The pull-up resistors associated with all four pins will be active at this time. 36 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 SI C SO SS Slave 0 Flash/ EEPROM Memory JN5148 37 38 41 42 43 36 33 34 SI C SO SS Slave 1 User Defined SI C SO SS Slave 2 User Defined SI C SO SS Slave 3 User Defined SI C SO SS Slave 4 User Defined SPIMISO SPIMOSI SPICLK SPISEL4 SPISEL2 SPISEL3 SPISEL1 SPISEL0 Figure 24: Typical JN5148 SPI Peripheral Connection The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5148 supports transfers at selectable data rates from 16MHz to 125kHz selected by a clock divider. Both SPICLK clock phase and polarity are configurable. The clock phase determines which edge of SPICLK is used by the JN5148 to present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The interface should be configured appropriately for the SPI slave being accessed. SPICLK Mode Description Polarity (CPOL) Phase (CPHA) 0 0 0 SPICLK is low when idle – the first edge is positive. Valid data is output on SPIMOSI before the first clock and changes every negative edge. SPIMISO is sampled every positive edge. 0 1 1 SPICLK is low when idle – the first edge is positive. Valid data is output on SPIMOSI every positive edge. SPIMISO is sampled every negative edge. 1 0 2 SPICLK is high when idle – the first edge is negative. Valid data is output on SPIMOSI before the first clock edge and is changed every positive edge. SPIMISO is sampled every negative edge. 1 1 3 SPICLK is high when idle – the first edge is negative. Valid data is output on SPIMOSI every negative edge. SPIMISO is sampled every positive edge. Table 3 SPI Configurations If more than one SPISEL line is to be used in a system they must be used in numerical order starting from SPISEL0. For instance if 3 SPI select lines are to be used, they must be SPISEL0, 1 and 2. A SPISEL line can be automatically deasserted between transactions if required, or it may stay asserted over a number of transactions. For devices such as memories where a large amount of data can be received by the master by continually providing SPICLK transitions, the ability for the select line to stay asserted is an advantage since it keeps the slave enabled over the whole of the transfer. A transaction commences with the SPI bus being set to the correct configuration, and then the slave device is selected. Upon commencement of transmission (1 to 32 bits) data is placed in the FIFO data buffer and clocked out, at the same time generating the corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of data bits is being received from the slave as it transmits. The data that is received during this transmission can be read (1 to 32 bits). If the master simply needs to provide a number of SPICLK transitions to allow data to be © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 37 sent from a slave, it should perform transmit using dummy data. An interrupt can be generated when the transaction has completed or alternatively the interface can be polled. If a slave device wishes to signal the JN5148 indicating that it has data to provide, it may be connected to one of the DIO pins that can be enabled as an interrupt. Figure 25 shows a complex SPI transfer, reading data from a FLASH device, that can be achieved using the SPI master interface. The slave select line must stay low for many separate SPI accesses, and therefore manual slave select mode must be used. The required slave select can then be asserted (active low) at the start of the transfer. A sequence 8 and 32 bit transfers can be used to issue the command and address to the FLASH device and then to read data back. Finally, the slave select can be deselected to end the transaction. 0 1 2 3 4 5 6 7 Instruction (0x03) 23 22 21 3 2 1 0 8 9 10 28 29 30 31 24-bit Address MSB Instruction Transaction 7 6 5 4 3 2 1 0 MSB 0 1 2 3 4 5 7 8N-1 3 2 1 0 LSB Read Data Bytes Transaction(s) 1-N SPISEL SPICLK SPIMOSI SPIMISO SPISEL SPICLK SPIMOSI SPIMISO 8 9 10 7 6 5 MSB Byte 1 Byte 2 Byte N value unused by peripherals 6 Figure 25: Example SPI Waveforms – Reading from FLASH device using Mode 038 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 11 Timers 11.1 Peripheral Timer/Counters Three general-purpose timer/counter units are available that can be independently configured to operate in one of five possible modes. Timer 0 and 1 support all 5 modes of operation and Timer 2 supports PWM and Delta-Sigma modes only. The timers have the following: • 5-bit prescaler, divides system clock by 2 prescale value as the clock to the timer (prescaler range is 0 to 16) • Clocked from internal system clock (16MHz) • 16-bit counter, 16-bit Rise and Fall (period) registers • Timer: can generate interrupts off Rise and Fall counts. Can be gated by external signal • Counter: counts number of transitions on external event signal. Can use low-high, high-low or both transitions • PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse. Can set period and mark-space ratio • Capture: measures times between transitions of an applied signal • Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes • Timer usage of external IO can be controlled on a pin by pin basis Interrupt Generator Rise Fall Delta-Sigma Counter Reset Generator = Prescaler INT Int Enable SYSCLK S/w Reset System Reset Single Shot = S R OE Gate Gate Edge Select Reset PWM/DeltaSigma Capture Generator Capture Enable PWM/∆−Σ PWM/∆−Σ TIMxCK_GT TIMxOUT TIMxCAP Figure 26: Timer Unit Block Diagram© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 39 The clock source for the timer unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler where a value of 0 leaves the clock unmodified and other values divide it by 2 prescale value. For example, a prescale value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz. The counter is optionally gated by a signal on the clock/gate input (TIMxCK_GT). If the gate function is selected, then the counter is frozen when the clock/gate input is high. An interrupt can be generated whenever the counter is equal to the value in either of the High or Low registers. The internal Output Enable (OE) signal enables or disables the timer output. The Timer 0 signals CK_GT, CAP and OUT are alternate functions of pins DIO8, 9 and 10 respectively and Timer 1 signals CK_GT, CAP and OUT are alternate functions of pins DIO11, 12, and 13 respectively. Timer 2 OUT is an alternate function of DIO11 If operating in timer mode it is not necessary to use any of the DIO pins, allowing the standard DIO functionality to be available to the application. Note, timer 0 may only be used as an internal timer or in counter mode (counting events) if an external 32kHz crystal is used. If timer 2 is used in PWM or Delta-Sigma mode then timer 1 does not have access to its clock/gate pin. Therefore, it can not operate in counter mode (counting events) or use the gate function. 11.1.1 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode allows the user to specify an overall cycle time and pulse length within the cycle. The pulse can be generated either as a single shot or as a train of pulses with a repetition rate determined by the cycle time. In this mode, the cycle time and low periods of the PWM output signal can be set by the values of two independent 16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset and the cycle repeats. The PWM waveform is available on TIMxOUT when the output driver is enabled. Rise Fall Figure 27: PWM Output Timings 11.1.2 Capture Mode The capture mode can be used to measure the time between transitions of a signal applied to the capture input (TIMxCAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register. The pulse width is the difference in counts in the two registers multiplied by the period of the prescaled clock. Upon reading the capture registers the counter is stopped. The values in the High and Low registers will be updated whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the mode was started. Therefore, if multiple pulses are seen on TIMxCAP before the counter is stopped only the last pulse width will be stored.40 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 CLK CAPT x 9 3 x 14 t RISE t RISE t FALL t FALL Rise Fall 9 5 3 4 7 Capture Mode Enabled Figure 28: Capture Mode 11.1.3 Counter/Timer Mode The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use. As a timer the clock source is from the system clock, prescaled if required. The timer period is programmed into the Fall register and the Fall register match interrupt enabled. The timer is started as either a single-shot or a repeating timer, and generates an interrupt when the counter reaches the Fall register value. When used to count external events on TIMxCK_GT the clock source is selected from the input pin and the number of events programmed into the Fall register. The Fall register match interrupt is enabled and the counter started, usually in single shot mode. An interrupt is generated when the programmed number of transitions is seen on the input pin. The transitions counted can configured to be rising, falling or both rising and falling edges. Edges on the event signal must be at least 100nsec apart, i.e. pulses must be wider than 100nsec. 11.1.4 Delta-Sigma Mode A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be implemented with up to 16-bit resolution. This requires that a resistor-capacitor network is placed between the output DIO pin and digital ground. A stream of pulses with digital voltage levels is generated which is integrated by the RC network to give an analogue voltage. A conversion time is defined in terms of a number of clock cycles. The width of the pulses generated is the period of a clock cycle. The number of pulses output in the cycle, together with the integrator RC values, will determine the resulting analogue voltage. For example, generating approximately half the number of pulses that make up a complete conversion period will produce a voltage on the RC output of VDD1/2, provided the RC time constant is chosen correctly. During a conversion, the pulses will be pseudo-randomly dispersed throughout the cycle in order to produce a steady voltage on the output of the RC network. The output signal is asserted for the number of clock periods defined in the High register, with the total period being 216 cycles. For the same value in the High register, the pattern of pulses on subsequent cycles is different, due to the pseudo-random distribution. The delta-sigma convertor output can operate in a Return-To-Zero (RTZ) or a Non-Return-to-Zero (NRZ) mode. The NRZ mode will allow several pulses to be output next to each other. The RTZ mode ensures that each pulse is separated from the next by at least one period. This improves linearity if the rise and fall times of the output are different to one another. Essentially, the output signal is low on every other output clock period, and the conversion cycle time is twice the NRZ cycle time ie 217 clocks. The integrated output will only reach half VDD2 in RTZ mode, since even at full scale only half the cycle contains pulses. Figure 29 and Figure 30 illustrate the difference between RTZ and NRZ for the same programmed number of pulses.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 41 1 2 3 1 2 N Conversion cycle 1 217 N Conversion cycle 2 3 Figure 29: Return To Zero Mode in Operation 1 2 3 1 2 N Conversion cycle 1 N 3 216 Conversion cycle 2 Figure 30: Non-Return to Zero Mode 11.1.5 Example Timer / Counter Application Figure 31 shows an application of the JN5148 timers to provide closed loop speed control. Timer 0 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls the power in the DC motor. Timer 1 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application software executing the control algorithm. If required for other functionality, then the unused IO associated with the timers could be used as general purpose DIO. JN5148 Timer 0 Timer 1 CLK/GATE CLK/GATE CAPTURE CAPTURE PWM PWM M Tacho 48 50 52 53 54 1N4007 +12V IRF521 51 1 pulse/rev Figure 31: Closed Loop PWM Speed Control Using JN5148 Timers 11.2 Tick Timer The JN5148 contains a hardware timer that can be used for generating timing interrupts to software. It may be used to implement regular events such as ticks for software timers or an operating system, as a high-precision timing reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include: • 32-bit counter42 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 • 28-bit match value • Maskable timer interrupt • Single-shot, Restartable or Continuous modes of operation Match Value Counter = Mode Control & & SysClk Run Match Int Enable Tick Timer Interrupt Reset Mode Figure 32: Tick Timer The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated by a signal from the mode control block. A match register allows comparison between the counter and a programmed value. The match value, measured in 16MHz clock cycles is programmed through software, in the range 0 to 0x0FFFFFFF. The output of the comparison can be used to generate an interrupt if the interrupt is enabled and used in controlling the counter in the different modes. Upon configuring the timer mode, the counter is also reset. If the mode is programmed as single shot, the counter begins to count from zero until the match value is reached. The match signal will be generated which will cause an interrupt if enabled, and the counter will stop counting. The counter is restarted by reprogramming the mode. If the mode is programmed as restartable, the operation of the counter is the same as for the single shot mode, except that when the match value is reached the counter is reset and begins counting from zero. An interrupt will be generated when the match value is reached if it is enabled. Continuous mode operation is similar to restartable, except that when the match value is reached, the counter is not reset but continues to count. An interrupt will be generated when the match value is reached if enabled. 11.3 Wakeup Timers Two 32-bit wakeup timers are available in the JN5148 driven from the 32kHz internal clock. They may run during sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period timings that may be required by the application. The wakeup timers do not run during deep sleep and may optionally be disabled in sleep mode through software control. When a wakeup timer expires it typically generates an interrupt, if the device is asleep then the interrupt may be used as an event to end the sleep period. See Section 21 for further details on how they are used during sleep periods. Features include: • 35-bit down-counter • Optionally runs during sleep periods • Clocked by 32kHz system clock; either 32kHz RC oscillator, 32kHz XTAL oscillator or 32kHz clock input© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 43 A wakeup timer consists of a 35-bit down counter clocked from the selected 32 kHz clock. An interrupt or wakeup event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wakeup event is required, the timer interrupt should be enabled before loading the count value for the period. Once the count value is loaded and counter started, the counter begins to count down; the counter can be stopped at any time through software control. The counter will remain at the value it contained when the timer was stopped and no interrupt will be generated. The status of the timers can be read to indicate if the timers are running and/or have expired; this is useful when the timer interrupts are masked. This operation will reset any expired status flags. 11.3.1 RC Oscillator Calibration The RC oscillator that can be used to time sleep periods is designed to require very little power to operate and be self-contained, requiring no external timing components and hence is lower cost. As a consequence of using on-chip resistors and capacitors, the inherent absolute accuracy and temperature coefficient is lower than that of a crystal oscillator, but once calibrated the accuracy approaches that of a crystal oscillator. Sleep time periods should be as close to the desired time as possible in order to allow the device to wake up in time for important events, for example beacon transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can be programmed to wake up very close to the calculated time of the event and so keep current consumption to a minimum. If the sleep time is less accurate, it will be necessary to wake up earlier in order to be certain the event will be captured. If the device wakes earlier, it will be awake for longer and so reduce battery life. In order to allow sleep time periods to be as close to the desired length as possible, the true frequency of the RC oscillator needs to be determined to better than the initial 30% accuracy. The calibration factor can then be used to calculate the true number of nominal 32kHz periods needed to make up a particular sleep time. A calibration reference counter, clocked from the 16MHz system clock, is provided to allow comparisons to be made between the 32kHz RC clock and the 16MHz system clock when the JN5148 is awake. Wakeup timer0 counts for a set number of 32kHz clock periods during which time the reference counter runs. When the wakeup timer reaches zero the reference counter is stopped, allowing software to read the number of 16MHz clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer. The true period of the 32kHz clock can thus be determined and used when programming a wakeup timer to achieve a better accuracy and hence more accurate sleep periods For a RC oscillator running at exactly 32,000Hz the value returned by the calibration procedure should be 10000, for a calibration period of twenty 32,000Hz clock periods. If the oscillator is running faster than 32,000Hz the count will be less than 10000, if running slower the value will be higher. For a calibration count of 9000, indicating that the RC oscillator period is running at approximately 35kHz, to time for a period of 2 seconds the timer should be loaded with 71,111 ((10000/9000) x (32000 x 2)) rather than 64000.44 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 12 Pulse Counters Two 16-bit counters are provided that can increment during all modes of operation (including sleep), based on pulses received on 2 dedicated DIO inputs; DIO1 and DIO8. The pulses can be de-bounced using the 32kHz clock to guard against false counting on slow or noisy edges. Increments occur from a configurable rising or falling edge on the respective DIO input. Each counter has an associated 16-bit reference that is loaded by the user. An interrupt (and wakeup event if asleep) may be generated when a counter reaches its pre-configured reference value. The two counters may optionally be cascaded together to provide a single 32-bit counter, linked to DIO1. The counters do not saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues when the reference value is reached without software interaction so that pulses are not missed even if there is a long delay before an interrupt is serviced or during the wakeup process. The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be used.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 45 13 Serial Communications The JN5148 has two independent Universal Asynchronous Receiver/Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. Each interface performs serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices. In both directions, a 16-byte deep FIFO buffer allows the CPU to read and write multiple characters on each transaction. This means that the CPU is freed from handling data on a character-by-character basis, with the associated high processor overhead. The UARTs have the following features: • Emulates behaviour of industry standard NS16450 and NS16550A UARTs • 16 byte transmit and receive FIFO buffers reduce interrupts to CPU, with direct access to fill levels of each • Adds / deletes standard start, stop and parity communication bits to or from the serial data • Independently controlled transmit, receive, status and data sent interrupts • Optional modem flow control signals CTS and RTS • Fully programmable data formats: baud rate, start, stop and parity settings • False start bit detection, parity, framing and FIFO overrun error detect and break indication • Internal diagnostic capabilities: loop-back controls for communications link fault isolation • Flow control by software or automatically by hardware Processor Bus Divisor Latch Registers Line Status Register Line Control Register FIFO Control Register Receiver FIFO Transmitter FIFO Baud Generator Logic Transmitter Shift Register Receiver Shift Register Transmitter Logic Receiver Logic RXD TXD Modem Control Register Modem Status Register Modem Signals Logic RTS CTS Interrupt ID Register Interrupt Enable Register Interrupt Logic Internal Interrupt Figure 33: UART Block Diagram The serial interface contains programmable fields that can be used to set number of data bits (5, 6,7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation of single or multiple stop bit, (for 5 bit data, multiple is 1.5 stop bits; for 6, 7 or 8 data bits, multiple is 2 bits). The baud rate is programmable up to 1Mbps, standard baud rates such as 4800, 9600, 19.2k, 38.4k etc. can be configured. For applications requiring hardware flow control, two control signals are provided: Clear-To-Send (CTS) and RequestTo-Send (RTS). CTS is an indication sent by an external device to the UART that it is ready to receive data. RTS is an indication sent by the UART to the external device that it is ready to receive data. RTS is controlled from software, while the value of CTS can be read. Monitoring and control of CTS and RTS is a software activity, normally performed as part of interrupt processing. The signals do not control parts of the UART hardware, but simply indicate to software the state of the UART external interface. Alternatively, the Automatic Flow Control mode can be set 46 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted. Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO, one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The status of the transmitter can be checked to see if it is empty, and if there is a character being transmitted. The status of the receiver can also be checked, indicating if conditions such as parity error, framing error or break indication have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if there is data held in the receive FIFO. UART 0 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO4, 5, 6 and 7 respectively and UART 1 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO17, 18, 19 and 20 respectively. If CTS and RTS are not required on the devices external pins, then they may be disabled, this allows the DIOx function to be used for other purposes. Note: With the automatic flow control threshold set to 15, the hardware flow control within the UART block negates RTS when the receive FIFO is about to become full. In some instances it has been observed that remote devices that are transmitting data do not respond quickly enough to the de-asserted CTS and continue to transmit data. In these instances the data will be lost in a receive FIFO overflow. 13.1 Interrupts Interrupt generation can be controlled for the UART block, and is divided into four categories: • Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times. • Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted. • Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an entire character. • Modem Status: Generated when the CTS (Clear To Send) input control line changes. 13.2 UART Application The following example shows the UART connected to a 9-pin connector compatible with a PC. As the JN5148 device pins do not provide the RS232 line voltage, a level shifter is used. JN5148 RTS CTS TXD UART0 RXD RS232 Lev el Shif ter 1 2 3 4 5 6 7 8 9 CD RD TD DTR SG DSR RTS CTS RI PC COM Port 1 5 Pin Signal 6 9 46 47 45 44 Figure 34: JN5148 Serial Communication Link© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 47 14 JTAG Debug Interface The JN5148 includes an IEEE1149.1 compliant JTAG port for the sole purpose of software code debug with NXP's Software Developer’s Kit. The JTAG interface is disabled by default and is enabled under software control. Therefore, debugging is only possible if enabled by the application. Once enabled, the application executes as normal until the external debugger controller initiates debug activity. The Debugger supports breakpoints and watchpoints based on four comparisons between any of program counter, load/store effective address and load/store data. There is the ability to chain the comparisons together. There is also the ability, under debugger control to perform the following commands: go, stop, reset, step over/into/out/next, run to cursor and breakpoints. In addition, under control of the debugger, it is possible to: • Read and write registers on the wishbone bus • Read ROM and RAM, and write to RAM • Read and write CPU internal registers The Debugger interface is accessed, depending upon the configuration, through the pins used for UART0 or UART1. This is enabled under software control and is dealt with in JN-AN-1118 JN5148 Application Debugging [4]. The following table details which DIO are used for the JTAG interface depending upon the configuration. Signal DIO Assignment UART0 pins UART1 pins clock (TCK) 4 17 control (TMS) 5 18 data out (TDO) 6 19 data in (TDI) 7 20 Table 4 Hardware Debugger IO If doze mode is active when debugging is started, the processor will be woken and then respond to debugger commands. It is not possible to wake the device from sleep using the debug interface and debugging is not available while the device is sleeping. When using the debug interface, program execution is halted, and control of the CPU is handed to the debugger. The watchdog, tick timer and the three timers described in section 11 are stalled while the debugger is in control of the CPU. When control is handed from the CPU to the debugger or back a small number of CPU clock cycles are taken flushing or reloading the CPU pipeline. Because of this, when a program is halted by the debugger and then restarted again, a small number of tick timer cycles will elapse. It is possible to prevent all hardware debugging by blowing the relevant Efuse bit. The JTAG interface does not support boundary scan testing. It is recommended that the JN5148 is not connected as part of the board scan chain.48 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 15 Two-Wire Serial Interface The JN5148 includes industry standard two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following features: Common to both master and slave: • Compatible with both I2 C and SMbus peripherals • Support for 7 and 10-bit addressing modes • Optional pulse suppression on signal inputs Master only: • Multi-master operation • Software programmable clock frequency • Clock stretching and wait state generation • Software programmable acknowledge bit • Interrupt or bit-polling driven byte-by-byte data-transfers • Bus busy detection Slave only: • Programmable slave address • Simple byte level transfer protocol • Write data flow control with optional clock stretching or acknowledge mechanism • Read data preloaded or provided as required 15.1 Connecting Devices The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial interface function of these pins is selected when the interface is enabled. They are both bi-directional lines, connected internally to the positive supply voltage via weak (45kΩ) programmable pull-up resistors. However, it is recommended that external 4.7kΩ pull-ups be used for reliable operation at high bus speeds, as shown in Figure 35. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an opendrain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is solely dependent on the bus capacitance limit of 400pF. SIF_CLK SIF_D VDD D1_OUT D1_IN CLK1_IN CLK1_OUT D2_IN CLK2_IN CLK2_OUT DEVICE 1 DEVICE 2 RP RP Pullup Resistors D2_OUT JN5148 SIF DIO14 DIO15 Figure 35: Connection Details© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 49 15.2 Clock Stretching Slave devices can use clock stretching to slow down the transfer bit rate. After the master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period and then release it. If the slave’s SIF_CLK low period is greater than the master’s low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait states. SIF_CLK SIF_CLK SIF_CLK Master SIF_CLK Slave SIF_CLK Wired-AND SIF_CLK Clock held low by Slave Figure 36: Clock Stretching 15.3 Master Two-wire Serial Interface When operating as a master device, it provides the clock signal and a prescale register determines the clock rate, allowing operation up to 400kbit/s. Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for indicating when start, stop, read, write and acknowledge control should be generated. Write data written into a transmit buffer will be written out across the two-wire interface when indicated, and read data received on the interface is made available in a receive buffer. Indication of when a particular transfer has completed may be indicated by means of an interrupt or by polling a status bit. The first byte of data transferred by the device after a start bit is the slave address. The JN5148 supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address will respond by returning an acknowledge bit. The master interface provides a true multi-master bus including collision detection and arbitration that prevents data corruption. If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock. Because of the wired-AND connection of the interface, a high-to-low transition on the bus affects all connected devices. This means a high-to-low transition on the SIF_CLK line causes all concerned devices to count off their low period. Once the clock input of a device has gone low, it will hold the SIF_CLK line in that state until the clock high state is reached when it releases the SIF_CLK line. Due to the wired-AND connection, the SIF_CLK line will therefore be held low by the device with the longest low period, and held high by the device with the shortest high period. SIF_CLK1 SIF_CLK2 SIF_CLK Master1 SIF_CLK Master2 SIF_CLK Wired-AND SIF_CLK Start counting low period Start counting high period Wait State Figure 37: Multi-Master Clock Synchronisation After each transfer has completed, the status of the device must be checked to ensure that the data has been acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost.50 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 15.4 Slave Two-wire Serial Interface When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal low if it is required to apply clock stretching. Only transfers whose address matches the value programmed into the interface’s address register are accepted. The interface allows both 7 and 10 bit addresses to be programmed, but only responds with an acknowledge to a single address. Addresses defined as “reserved” will not be responded to, and should not be programmed into the address register. A list of reserved addresses is shown in Table 5. Address Name Behaviour 0000 000 General Call/Start Byte Ignored 0000 001 CBUS address Ignored 0000 010 Reserved Ignored 0000 011 Reserved Ignored 0000 1XX Hs-mode master code Ignored 1111 1XX Reserved Ignored 1111 0XX 10-bit address Only responded to if 10 bit address set in address register Table 5 : List of two-wire serial interface reserved addresses Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for taking write data from a receive buffer and providing read data to a transmit buffer when indicated. A series of interrupt status bits are provided to control the flow of data. For writes, in to the slave interface, it is important that data is taken from the receive buffer by the processor before the next byte of data arrives. To enable this, the interface may be configured to work in two possible backoff modes: • Not Acknowledge mode – where the interface returns a Not Acknowledge (NACK) to the master if more data is received before the previous data has been taken. This will lead to the termination of the current data transfer. • Clock Stretching mode – where the interface holds the clock line low until the previous data has been taken. This will occur after transfer of the next data but before issuing an acknowledge For reads, from the slave interface, the data may be preloaded into the transmit buffer when it is empty (i.e. at the start of day, or when the last data has been read), or fetched each time a read transfer is requested. When using data preload, read data in the buffer must be replenished following a data write, as the transmit and received data is contained in a shared buffer. The interface will hold the bus using clock stretching when the transmit buffer is empty. Interrupts may be triggered when: • Data Buffer read data is required – a byte of data to be read should be provided to avoid the interface from clock stretching • Data Buffer read data has been taken – this indicates when the next data may be preloaded into the data buffer • Data Buffer write data is available – a byte of data should be taken from the data buffer to avoid data backoff as defined above • The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop or Restart is seen • A protocol error has been spotted on the interface© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 51 16 Four-Wire Digital Audio Interface The JN5148 includes a four-wire digital audio interface that can be used for interfacing to audio CODECs. The following features are supported: • Compatible with the industry standard I²S interface • Option to support I²S, left justified and right justified modes • Optional support for connection to mono sample FIFO with data transferred on the left or right channel • Master only • Transmit on falling edge and receive on rising edge • Up to 8MHz maximum clock range • Maximum system size of 32-bits, allowing up to 16-bits per channel (left or right channels) • Option for pad bit insertion, allowing length of transfer per channel to be anything from 16 to 32 bits • Data Transfer size range of 1 to 16-bits per channel • Option to invert WS (normally 0 for left, but allow 1 for left instead) • Continuous clock output option to support CODECs which use it as a clock source • Separate input and output data lines • Option to invert idle state of WS (to indicate left or right) The Word Select (WS), Data In (SDIN), Clock (SCK) and Data Out (SDOUT) lines are alternate functions of DIO lines 12,13,17 and 18 respectively. Data transfer is always bidirectional. Data placed in the Data Buffer before a transfer command is issued will be transmitted on SDOUT whilst the data received on SDIN will be placed in the Data Buffer at the end of the transfer. Indication that a transfer has completed is by means of an interrupt or by polling a status bit. Left channel data is always sent first, with MSB first on each channel. The interface will always transfer both left and right channel data. For mono data transfer, the user should pad out the unused channel with 0’s, and ignore any data returned on the unused channel. The length of a data transfer is derived as follows: • When padding is disabled – Data Transfer Length = 2 x Data Transfer Size • When padding is enabled – Data Transfer Length = 2 x (16 + Extra Pad Length) Timing of the 3 main modes is shown in Figure 38, Figure 39 and Figure 40. The Data Buffer shows how the data is stored and how it will be transferred onto the interface. SD Max Size indicates how the maximum transfer size (16 with no additional padding) will transfer, whilst SD 3-bits indicates how 3 bits of data will be aligned when padding is enabled. Received data in the Data Buffer will always be padded out with 0’s if the Data Transfer Size is less than 16- bits, and any bits received beyond 16-bits when extra padding is used, will be discarded. In the examples, the polarity of WS is shown with Left channel = 0, and the idle state is Right Channel. 52 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Data Buffer Right R2 R1 R0 Left L2 L1 L0 SCK WS SD Max Size SD 3-bits MSB LSB MSB LSB Left Right L2 L1 L0 0 R2 R1 R0 MSB-1 MSB-2 MSB-1 MSB-2 0 0 0 Figure 38: I²S Mode Data Buffer Right R2 R1 R0 Left L2 L1 L0 SCK WS SD Max Size SD 3-bits MSB LSB MSB LSB Left Right L2 L1 L0 0 R2 R1 R0 MSB-1 MSB-2 MSB-1 MSB-2 0 0 0 Figure 39: Left Justified Mode Data Buffer Right R2 R1 R0 Left L2 L1 L0 SCK WS SD Max Size SD 3-bits MSB LSB MSB LSB Left Right 0 L2 L1 L0 R2 R1 R0 MSB-1 MSB-1 0 0 0 Figure 40: Right Justified Mode© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 53 17 Random Number Generator A random number generator is provided which creates a 16-bit random number each time it is invoked. Consecutive calls can be made to build up any length of random number required. Each call takes approximately 0.25msec to complete. Alternatively, continuous generation mode can be used where a new number is generated approximately every 0.25msec. In either mode of operation an interrupt can be generated to indicate when the number is available, or a status bit can be polled. The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these clocks are asynchronous to each other, each sampled bit is unpredictable and hence random.54 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 18 Sample FIFO A 10 deep FIFO is provided to buffer data between the CPU and either the four-wire digital audio interface or the DAC/ ADC. It supports single channel input and output data, up to 16 bits wide. When used it can reduce the rate at which the processor has to generate/process data, and this may allow more efficient operation. Interrupts can be generated based on fill levels and also FIFO empty and full conditions. Normal configuration of the digital audio interface or the DAC/ ADC is still required when accessing the data via the FIFO. When used with the DAC / ADC functions a timing signal is generated by the DAC/ ADC functions to control the transfer of data to and from the FIFO and the analogue peripherals. The transfers will occur at the sample rate configured within the DAC / ADC functions. When the FIFO is linked to the four-wire digital audio interface, timer 2 must be used to generate an internal timing signal to control the flow of data across the interface. The timer does not require any external pins to be enabled. The timer should be set up to produce a PWM output with a rising edge generated every time a digital audio transfer is required. The transfer rate is typically configured to be the audio sample rate, e.g. 8kHz. If the transfer rate is too fast or slow data will be transferred correctly between the FIFO and the digital audio block.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 55 19 Intelligent Peripheral Interface The Intelligent Peripheral (IP) Interface is provided for systems that are more complex, where there is a processor that requires a wireless peripheral. As an example, the JN5148 may provide a complete JenNet or ZigBee PRO wireless network interface to a phone, computer, PDA, set-top box or games console. No resources are required from the main processor compared to a transceiver as the complete wireless protocol may be run on the internal JN5148 CPU. The wireless peripheral may be controlled via one of the UARTs but the IP interface is intended to provide a high-speed, low-processor-overhead interface. The intelligent peripheral interface is a SPI slave interface and uses pins shared with other DIO signals. The interface is designed to allow message passing and data transfer. Data received and transmitted on the IP interface is copied directly to and from a dedicated area of memory without intervention from the CPU. This memory area, the intelligent peripheral memory block, contains 64 32-bit word receive and transmit buffers. JN5148 Intelligent Peripheral Interface SPI MASTER System Processor (e.g. in cellphone, computer) CPU IP_DO SPIMISO IP_INT SPIINT IP_DI SPIMOSI IP_SEL SPISEL IP_CLK SPICLK Figure 41: Intelligent Peripheral Connection The interface functions as a SPI slave. It is possible to select the clock edge of IP_CLK on which data on the IP_DIN line of the interface is sampled, and the state of data output IP_DOUT is changed. The order of transmission is MSB first. The IP_DO data output is tri-stated when the device is inactive, i.e. the device is not selected via IP_SEL. An interrupt output line IP_INT is available so that the JN5148 can indicate to an external master that it has data to transfer. The interface can be clocked at up to 8MHz The IP interface signals IP_CLK, IP_DO, IP_DI, IP_SEL, IP_INT are alternate functions of pins DIO14 to 18 respectively. 19.1 Data Transfer Format Transfers are started by the remote processor asserting the IP_SEL line and terminated by the remote processor deasserting IP_SEL. Data transfers are bi-directional and traffic in both directions has a format of status byte, data length byte (of the number of 32-bit words to transfer) and data packet (from the receive and transmit buffers), as shown in Figure 42 The first byte transferred into the JN5148 is a status byte with the format shown in Table 6. This is followed by a padding byte that should be set to zero. The first byte output by the JN5148 is a padding byte, that should be ignored, followed by a status byte with the format shown in Table 6 Bit Field Description 7:2 RSVD Reserved, set to 0 1 TXQ 1: Data queued for transmission 0 RXRDY 1: Buffer ready to receive data Table 6: IP Status Byte Format56 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 If data is queued for transmission and the recipient has indicated that they are ready for it (RXRDY in incoming status byte was 1), the next byte to be transmitted is the data length in words (N). If either the JN5148 or the remote processor has no data to transfer, then the data length should be set to zero. The transaction can be terminated by the master after the status and padding bytes have been sent if it is not possible to send data in either direction. This may be because neither party has data to send or because the receiver does not have a buffer available. If the data length is non-zero, the data in the JN5148 transmit memory buffer is sent, beginning at the start of the buffer. At the same time that data bytes are being sent from the transmit buffer, the JN5148 receive buffer is being filled with incoming data, beginning from the start of the buffer. The remote processor, acting as the master, must determine the larger of its incoming or outgoing data transfers and deassert IP_SEL when all of the transmit and receive data has been transferred. The data is transferred into or out of the buffers starting from the lowest address in the buffer, and each word is assembled with the MSB first on the serial data lines. Following a transaction, IP_SEL must be high (deasserted) for at least 400nsec before a further transaction can begin. IP_SEL IP_CLK IP_DI Status (8-bit) N words of data IP_DO data length or 0s (8-bit) padding (8-bit) Status (8-bit) data length or 0s (8-bit) N words of data padding (8-bit) Figure 42: Intelligent Peripheral Data Transfer Waveforms The N words of data transferred on the interface are also formatted. The first three bytes, of the first word, must be zero. These are followed by a one byte length field that must be one less than the data length shown in the data length field in Figure 42, i.e. N-1. Following this are the (N-1) words of data. The application running on the JN5148 has high level software functions for sending and receiving data on this interface. The function of generating and interpreting the individual bytes on the interface is handled by hardware within the device. The remote processor must generate, and interpret, the signals in the interface. For instance, this may be done with a configurable SPI master interface. 19.2 JN5148 (Slave) Initiated Data Transfer To send data, the data is written into either buffer 0 or 1 of the intelligent peripheral memory area. Then the buffer number is written together with the data length. If the call is successful, the interrupt line IP_INT will signal to the remote processor that there is a message ready to be sent from the JN5148. When a remote processor starts a transfer to the JN5148 by deasserting IP_SEL, then IP_INT is deasserted. If the transfer is unsuccessful and the data is not output then IP_INT is reasserted after the transfer to indicate that data is still waiting to be sent. The interface can be configured to generate an internal interrupt whenever a transaction completes (for example IP_SEL becomes inactive after a transfer starts). It is also possible to mask the interrupt. The end of the transmission can be signalled by an interrupt, or the interface can be polled. To receive data the interface must be firstly initialised and when this is done, the bit RXRDY sent in the status byte from the IP block will show that data can be received by the JN5148. Successful data arrival can be indicated by an interrupt, or the interface can be polled. IP_INT is asserted if the JN5148 is configured to be able to receive, and the remote processor has previously attempted to send data but the RXRDY indicated that it could not be sent. To send and receive at the same time, the transmit and receive buffers must be set to be different. 19.3 Remote (Master) Processor Initiated Data Transfer The remote processor (master) must initiate a transfer to send data to the JN5148 (slave) by asserting the slave select pin, IP_SEL, and generating its status byte on IP_DI with TXRDY set. After receiving the status byte from the JN5148, the master should check that the JN5148 has a buffer ready by reading the RXRDY bit of the received status byte. If the RXRDY bit is 0 indicating that the JN5148 cannot accept data, it must terminate the transfer by deasserting IP_SEL unless it is receiving data from the JN5148. If the RXRDY bit is 1, indicating that the JN5148 can accept data, then the master should generate a further 8 clocks on IP_CLK in order to transfer its own message length on IP_DI. The master must continue clocking the interface until sufficient clocks have been generated to send © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 57 all the data specified in the length field to the JN5148. The master must then deassert IP_SEL to show the transfer is complete. The master may initiate a transfer to read data from the JN5148 by asserting the slave select pin, IP_SEL, and generating its status byte on IP_DI with RXRDY set. After receiving the status byte from the JN5148, it should check that the JN5148 has a buffer ready by reading the TXRDY bit of the received status byte. If the TXRDY bit is 0, indicating that the JN5148 does not have data to send, it must terminate the transfer by deasserting IP_SEL unless it is transmitting data to the JN5148. If the TXRDY bit is 1, indicating that the JN5148 can send data, then the master must generate a further 8 clocks on IP_CLK in order to receive the message length on IP_DO. The master must continue clocking the interface until sufficient clocks have been generated to receive all the data specified in the length field from the JN5148. The master should then deassert IP_SEL to show the transfer is complete. Data can be sent in both directions at once and the master must ensure both transfers have completed before deasserting IP_SEL.58 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 20 Analogue Peripherals The JN5148 contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors, switches and actuators. ADC DAC1 DAC2 VREF Chip Boundary Internal Reference Processor Bus Supply Voltage (VDD1) Vref select Temp Sensor Comparator 2 Comparator 1 COMP2M COMP1M COMP1P COMP2P DAC1 DAC2 ADC1 ADC2 ADC3 ADC4 Vref Figure 43: Analogue Peripherals In order to provide good isolation from digital noise, the analogue peripherals are powered by a separate regulator, supplied from the analogue supply VDD1 and referenced to analogue ground VSSA. A common reference Vref for the ADC and DAC can be selected between an internal bandgap reference or an external voltage reference supplied to the VREF pin. Gain settings for the ADC and DAC are independent of each other. The ADC and DAC are clocked from a common clock source derived from the 16MHz clock© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 59 20.1 Analogue to Digital Converter The 12-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input channels: four available externally, one connected to an internal temperature sensor, and one connected to an internal supply monitoring circuit. 20.1.1 Operation The input range of the ADC can be set between 0V to either the reference voltage or twice the reference voltage. The reference can be either taken from the internal voltage reference or from the external voltage applied to the VREF pin. For example, an external reference of 1.2V supplied to VREF may be used to set the ADC range between 0V and 2.4V. VREF Gain Setting Maximum Input Range Supply Voltage Range (VDD) 1.2V 1.6V 1.2V 1.6V 0 0 1 1 1.2V 1.6V 2.4V 3.2V 2.2V - 3.6V 2.2V - 3.6V 2.6V - 3.6V 3.4V - 3.6V Table 7 ADC/DAC Maximum Input Range The input clock to the ADC is 16MHz and can be divided down to 2MHz, 1MHz, 500kHz and 250kHz. During an ADC conversion the selected input channel is sampled for a fixed period and then held. This sampling period is defined as a number of ADC clock periods and can be programmed to 2, 4, 6 or 8. The conversion rate is ((3 x Sample period) + 14) clock periods. For example for 500kHz conversion with sample period of 2 will be (3 x 2) + 14 = 20 clock periods, 40usecs or 25kHz. . The ADC can be operated in either a single conversion mode or alternatively a new conversion can be started as soon as the previous one has completed, to give continuous conversions. If the source resistance of the input voltage is 1kΩ or less, then the default sampling time of 2 clocks should be used. The input to the ADC can be modelled as a resistor of 5kΩ(typ) and 10kΩ (max) to represent the on-resistance of the switches and the sampling capacitor 8pF. The sampling time required can then be calculated, by adding the sensor source resistance to the switch resistance, multiplying by the capacitance giving a time constant. Assuming normal exponential RC charging, the number of time constants required to give an acceptable error can be calculated, 7 time constants gives an error of 0.1%, so for 12-bit accuracy 10 time constants should be the target. For a source with zero resistance, 10 time constants is 800 nsecs, hence the smallest sampling window of 2 clock periods can be used. ADC pin 5 K 8 pF Sample Switch ADC front end Figure 44 ADC Input Equivalent Circuit The ADC sampling period, input range and mode (single shot or continuous) are controlled through software. When the ADC conversion is complete, an interrupt is generated. Alternatively the conversion status can be polled. When operating in continuous mode, it is recommended that the interrupt is used to signal the end of a conversion, since conversion times may range from 10 to 152 µsecs. Polling over this period would be wasteful of processor bandwidth. To facilitate averaging of the ADC values, which is a common practice in microcontrollers, a dedicated accumulator has been added, the user can define the accumulation to occur over 2,4,8 or 16 samples. The end of conversion 60 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 interrupt can be modified to occur at the end of the chosen accumulation period, alternatively polling can still be used. Software can then be used to apply the appropriate rounding and shifting to generate the average value, as well as setting up the accumulation function. For detailed electrical specifications, see section 22.3.8. 20.1.2 Supply Monitor The internal supply monitor allows the voltage on the analogue supply pin VDD1 to be measured. This is achieved with a potential divider that reduces the voltage by a factor of 0.666, allowing it to fall inside the input range of the ADC when set with an input range twice the internal voltage reference. The resistor chain that performs the voltage reduction is disabled until the measurement is made to avoid a continuous drain on the supply. 20.1.3 Temperature Sensor The on chip temperature sensor can be used either to provide an absolute measure of the device temperature or to detect changes in the ambient temperature. In common with most on chip temperature sensors, it is not trimmed and so the absolute accuracy variation is large; the user may wish to calibrate the sensor prior to use. The sensor forces a constant current through a forward biased diode to provide a voltage output proportional to the chip die temperature which can then be measured using the ADC. The measured voltage has a linear relationship to temperature as described in section 22.3.15. Because this sensor is on chip, any measurements taken must account for the thermal time constants. For example, if the device just came out of sleep mode the user application should wait until the temperature has stabilised before taking a measurement. 20.2 Digital to Analogue Converter The Digital to Analogue Converter (DAC) provides two output channels and is capable of producing voltages of 0 to Vref or 0 to 2Vref where Vref is selected between the internal reference and the VREF pin, with a resolution of 12-bits and a minimum conversion time of 10µsecs (2MHz clock). 20.2.1 Operation The output range of each DAC can be set independently to swing between 0V to either the reference voltage or twice the reference voltage. The reference voltage is selected from the internal reference or the VREF pin. For example, an external reference of 0.8V supplied to VREF may be used to set DAC1 maximum output of 0.8V and DAC2 maximum output of 1.6V. The DAC output amplifier is capable of driving a capacitive load up to that specified in section 22.3.9 Programmable clock periods allow a trade-off between conversion speed and resolution. The full 12-bit resolution is achieved with the 250kHz clock rate. See section 22.3.9 electrical characteristics, for more details. The conversion period of the DACs are given by the same formula as the ADC conversion time and so can vary between 10 and 152uS. The DAC values may be updated at the same time as the ADC is active. The clock divider ratio, interrupt enable and reference voltage select are all controlled through software, options common to both the ADC and DAC. The DAC output range and initial value can be set and the subsequent updates provided by updating only the DAC value. Polling is available to determine if a DAC channel is busy performing a conversion. The DAC can be disabled which will power down the DAC cell. Simultaneous conversions with DAC1 and DAC2 are possible. To use both DACs at the same time it is only necessary to enable them and supply the digital values via the software. The DACs should not be used in single shot mode, but continuous conversion mode only, in order to maintain a steady output voltage. © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 61 20.3 Comparators The JN5148 contains two analogue comparators COMP1 and COMP2 that are designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level (common to both comparators) can be set to a nominal value of 0mV, 10mV, 20mV or 40mV. In addition, the source of the negative input signal for each comparator (COMP1M and COMP2M) can be set to the internal voltage reference, the output of DAC1 or DAC2 (COMP1 or COMP2 respectively) or the appropriate external pin. The comparator outputs are routed to internal registers and can be polled, or can be used to generate interrupts. The comparators can be disabled to reduce power consumption. The comparators have a low power mode where the response time of the comparator is slower than normal and is specified in section 22.3.10. This mode may be used during non-sleep operation however it is particularly useful in sleep mode to wake up the JN5148 from sleep where low current consumption is important. The wakeup action and the configuration for which edge of the comparator output will be active are controlled through software. In sleep mode the negative input signal source, must be configured to be driven from the external pins.62 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 21 Power Management and Sleep Modes 21.1 Operating Modes Three operating modes are provided in the JN5148 that enable the system power consumption to be controlled carefully to maximise battery life. • Active Processing Mode • Sleep Mode • Deep Sleep Mode The variation in power consumption of the three modes is a result of having a series of power domains within the chip that may be controllably powered on or off. 21.1.1 Power Domains The JN5148 has the following power domains: • VDD Supply Domain: supplies the wake-up timers and controller, DIO blocks, Comparators, 32kHz RC and crystal oscillators. This domain is driven from the external supply (battery) and is always powered. The wake-up timers and controller, and the 32kHz RC and crystal oscillators may be powered on or off in sleep mode through software control. • Digital Logic Domain: supplies the digital peripherals, CPU, ROM, Baseband controller, Modem and Encryption processor. It is powered off during sleep mode. • Analogue Domain: supplies the ADC, DACs and the temperature sensor. It is powered off during sleep mode and may be powered on or off in active processing mode through software control. • RAM Domain: supplies the RAM during sleep mode to retain the memory contents. It may be powered on or off for sleep mode through software control. • Radio Domain: supplies the radio interface. It is powered during transmit and receive and controlled by the baseband processor. It is powered off during sleep mode. The current consumption figures for the different modes of operation of the device is given in section 22.2.2. 21.2 Active Processing Mode Active processing mode in the JN5148 is where all of the application processing takes place. By default, the CPU will execute at the selected clock speed executing application firmware. All of the peripherals are available to the application, as are options to actively enable or disable them to control power consumption; see specific peripheral sections for details. Whilst in Active processing mode there is the option to doze the CPU but keep the rest of the chip active; this is particularly useful for radio transmit and receive operations, where the CPU operation is not required therefore saving power. 21.2.1 CPU Doze Whilst in doze mode, CPU operation is stopped but the chip remains powered and the digital peripherals continue to run. Doze mode is entered through software and is terminated by any interrupt request. Once the interrupt service routine has been executed, normal program execution resumes. Doze mode uses more power than sleep and deep sleep modes but requires less time to restart and can therefore be used as a low power alternative to an idle loop. Whilst in CPU doze the current associated with the CPU is not consumed, therefore the basic device current is reduced as shown in the figures in section 22.2.2.1. 21.3 Sleep Mode The JN5148 enters sleep mode through software control. In this mode most of the internal chip functions are shutdown to save power, however the state of DIO pins are retained, including the output values and pull-up enables, © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 63 and this therefore preserves any interface to the outside world. The DAC outputs are placed into a high impedance state. When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period. If the wakeup timers are not to be used for a wakeup event and the application does not require them to run continually, then power can be saved by switching off the 32kHz oscillator if selected as the system clock through software control. The oscillator will be restarted when a wakeup event occurs. Whilst in sleep mode one of four possible events can cause a wakeup to occur: transitions on DIO inputs, expiry of wakeup timers, pulse counters maturing or comparator events. If any of these events occur, and the relevant interrupt is enabled, then an interrupt is generated that will cause a wakeup from sleep. It is possible for multiple wakeup sources to trigger an event at the same instant and only one of them will be accountable for the wakeup period. It is therefore necessary in software to remove all other pending wakeup events prior to requesting entry back into sleep mode; otherwise, the device will re-awaken immediately. When wakeup occurs, a similar sequence of events to the reset process described in section 6.1 happens, including the checking of the supply voltage by the Brown Out Detector 6.4. The 32MHz oscillator is started up, once stable the power to CPU system is enabled and the reset is removed. Software determines that this is a reset from sleep and so commences with the wakeup process. If RAM contents were held through sleep, wakeup is quicker as the application program does not have to be reloaded from Flash memory. See section 22.3.6 for wake-up timings. 21.3.1 Wakeup Timer Event The JN5148 contains two 35-bit wakeup timers that are counters clocked from the 32kHz oscillator, and can be programmed to generate a wake-up event. Following a wakeup event, the timers continue to run. These timers are described in section 11.3. Timer events can be generated from both of the two timers; one is intended for use by the 802.15.4 protocol, the other being available for use by the Application running on the CPU. These timers are available to run at any time, even during sleep mode. 21.3.2 DIO Event Any DIO pin when used as an input has the capability, by detecting a transition, to generate a wake-up event. Once this feature has been enabled the type of transition can be specified (rising or falling edge). Even when groups of DIO lines are configured as alternative functions such as the UARTs or Timers etc, any input line in the group can still be used to provide a wakeup event. This means that an external device communicating over the UART can wakeup a sleeping device by asserting its RTS signal pin (which is the CTS input of the JN5148). 21.3.3 Comparator Event The comparator can generate a wakeup interrupt when a change in the relative levels of the positive and negative inputs occurs. The ability to wakeup when continuously monitoring analogue signals is useful in ultra-low power applications. For example, the JN5148 can remain in sleep mode until the voltage drops below a threshold and then be woken up to deal with the alarm condition. 21.3.4 Pulse Counter The JN5148 contains two 16 bit pulse counters that can be programmed to generate a wake-up event. Following the wakeup event the counters will continue to operate and therefore no pulse will be missed during the wake-up process. These counters are described in section 12. To minimise sleep current it is possible to disable the 32K RC oscillator and still use the pulse counters to cause a wake-up event, provided debounce mode is not required. 21.4 Deep Sleep Mode Deep sleep mode gives the lowest power consumption. All switchable power domains are off and certain functions in the VDD supply power domain, including the 32kHz oscillator are stopped. This mode can be exited by a power down, a hardware reset on the RESETN pin, or a DIO event. The DIO event in this mode causes a chip reset to occur.64 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22 Electrical Characteristics 22.1 Maximum Ratings Exceeding these conditions may result in damage to the device. Parameter Min Max Device supply voltage VDD1, VDD2 -0.3V 3.6V Supply voltage at voltage regulator bypass pins VB_xxx -0.3V 1.98V Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RF_IN. -0.3V VB_xxx + 0.3V Voltage on analogue pins VREF, ADC1-4, DAC1-2, COMP1M, COMP1P, COMP2M, COMP2P, IBIAS -0.3V VDD1 + 0.3V Voltage on 5v tolerant digital pins SPICLK, SPIMOSI, SPIMISO, SPISEL0, DIO0-8 & DIO11-20, RESETN -0.3V Lower of (VDD2 + 2V) and 5.5V Voltage on 3v tolerant digital pins DIO9, DIO10 -0.3V VDD2 + 0.3V Storage temperature -40ºC 150ºC Reflow soldering temperature according to IPC/JEDEC J-STD-020C 260ºC ESD rating 4 Human Body Model 1 2.0kV Charged Device Model 2 500V 1) Testing for Human Body Model discharge is performed as specified in JEDEC Standard JESD22-A114. 2) Testing for Charged Device Model discharge is performed as specified in JEDEC Standard JESD22-C101. 22.2 DC Electrical Characteristics 22.2.1 Operating Conditions Supply Min Max VDD1, VDD2 2.0V 3.6V Ambient temperature range -40ºC 85ºC© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 65 22.2.2 DC Current Consumption VDD = 2.0 to 3.6V, -40 to +85º C 22.2.2.1 Active Processing Mode: Min Typ Max Unit Notes CPU processing 32,16,8 or 4MHz 1600 + 280/MHz µA SPI, GPIOs enabled. When in CPU doze the current related to CPU speed is not consumed. Radio transmit 15.0 mA CPU in software doze – radio transmitting Radio receive 17.5 mA CPU in software doze – radio in receive mode The following current figures should be added to those above if the feature is being used ADC 655 µA Temperature sensor and battery measurements require ADC DAC 215 / 235 µA One / both Comparator 73 / 0.8 µA Normal / low-power UART 90 µA For each UART Timer 30 µA For each Timer 2-wire serial interface 70 µA 22.2.2.2 Sleep Mode Mode: Min Typ Max Unit Notes Sleep mode with I/O wakeup 0.12 µA Waiting on I/O event Sleep mode with I/O and RC Oscillator timer wakeup – measured at 25ºC 1.25 µA As above, but also waiting on timer event. If both wakeup timers are enabled then add another 0.05µA 32kHz crystal oscillator 1.5 µA As alternative sleep timer The following current figures should be added to those above if the feature is being used RAM retention– measured at 25ºC 2.2 µA For full 128kB retained Comparator (low-power mode) 0.8 µA Reduced response time 22.2.2.3 Deep Sleep Mode Mode: Min Typ Max Unit Notes Deep sleep mode– measured at 25ºC 100 nA Waiting on chip RESET or I/O event66 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.2.3 I/O Characteristics VDD = 2.0 to 3.6V, -40 to +85º C Parameter Min Typ Max Unit Notes Internal DIO pullup resistors 22 24 31 35 34 40 56 63 53 63 92 104 kΩ VDD2 = 3.6V, 25C VDD2 = 3.0V, 25C VDD2 = 2.2V, 25C VDD2 = 2.0V, 25C Digital I/O High Input (except DIO9, DIO10) VDD2 x 0.7 Lower of (VDD2 + 2V) and 5.5V V 5V Tolerant I/O only Digital I/O High Input ( DIO9, DIO10) VDD2 x 0.7 VDD2 V Digital I/O low Input -0.3 VDD2 x 0.27 V Digital I/O input hysteresis 140 230 310 mV DIO High O/P (2.7-3.6V) VDD2 x 0.8 VDD2 V With 4mA load DIO Low O/P (2.7-3.6V) 0 0.4 V With 4mA load DIO High O/P (2.2-2.7V) VDD2 x 0.8 VDD2 V With 3mA load DIO Low O/P (2.2-2.7V) 0 0.4 V With 3mA load DIO High O/P (2.0-2.2V) VDD2 x 0.8 VDD2 V With 2.5mA load DIO Low O/P (2.0-2.2V) 0 0.4 V With 2.5mA load Current sink/source capability 4 3 2.5 mA VDD2 = 2.7V to 3.6V VDD2 = 2.2V to 2.7V VDD2 = 2.0V to 2.2V IIL - Input Leakage Current 50 nA Vcc = 3.6V, pin low IIH - Input Leakage Current 50 nA Vcc = 3.6V, pin high 22.3 AC Characteristics 22.3.1 Reset and Voltage Brown-Out RESETN Internal RESET VDD VPOT t STAB Figure 45: Internal Power-on Reset without showing Brown-Out© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 67 Internal RESET RESETN VRST t STAB t RST Figure 46: Externally Applied Reset VDD = 2.0 to 3.6V, -40 to +85º C Parameter Min Typ Max Unit Notes External Reset pulse width to initiate reset sequence (tRST) 1 µs Assumes internal pullup resistor value of 100K worst case and ~5pF external capacitance External Reset threshold voltage (VRST) VDD2 x 0.7 V Minimum voltage to avoid being reset Internal Power-on Reset threshold voltage (VPOT) 1.47 1.42 V Rising Falling Reset stabilisation time (tSTAB) 0.84 ms Note 1 Brown-out Threshold Voltage (VTH) 1.87 2.16 2.54 2.83 1.95 2.25 2.65 2.95 2.01 2.32 2.73 3.04 V Configurable threshold with 4 levels Brown-out Hysteresis (VHYS) 45 60 85 100 mV Corresponding to the 4 threshold levels 1 Time from release of reset to start of executing ROM code. Loading program from Flash occurs in addition to this. VTH + VHYS VTH DVDD Internal POR Internal BOReset VPOT Figure 47: Power on Reset followed by Brown-out Detect68 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.2 SPI MasterTiming t t SSH SSS t CK t SI t HI MOSI (mode=1,3) SS MOSI (mode=0,2) MISO (mode=0,2) MISO (mode=1,3) t VO t VO CLK (mode=0,1) t SI t HI CLK (mode=2,3) Figure 48: SPI Timing (Master) Parameter Symbol Min Max Unit Clock period tCK 62.5 - ns Data setup time tSI 16.7 @ 3.3V 18.2 @ 2.7V 21.0 @ 2.0V - ns Data hold time tHI 0 ns Data invalid period tVO - 15 ns Select set-up period tSSS 60 - ns Select hold period tSSH 30 (SPICLK = 16MHz) 0 (SPICLK<16MHz, mode=0 or 2) 60 (SPICLK<16MHz, mode=1 or 3) - ns 22.3.3 Intelligent Peripheral (SPI Slave) Timing IP_SEL IP_CLK IP_DI IP_DO t si t hi t vo t sss t t ssh ck t lz t hz Figure 49: Intelligent Peripheral (SPI Slave) Timing© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 69 Parameter Symbol Min Max Unit Clock period tck 125.0 - ns Data setup time tsi 15 - ns Data hold time thi 15 ns Data invalid period tvo - 40 ns Select set-up period tsss 15 - ns Select hold period tssh 15 - ns Select asserted to output data driven tlz 20 ns Select negated to data output tri-stated thz 20 ns 22.3.4 Two-wire Serial Interface t BUF S Sr P S t LOW t HD;STA t F t R t HD;DAT t HIGH t SU;DAT t SU;STA t HD;STA t SU;STO t SP t R t F SIF_D SIF_CLK Figure 50: Two-wire Serial Interface Timing Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SIF_CLK clock frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD:STA 4 - 0.6 - µs LOW period of the SIF_CLK clock tLOW 4.7 - 1.3 - µs HIGH period of the SIF_CLK clock tHIGH 4 - 0.6 - µs Set-up time for repeated START condition tSU:STA 4.7 - 0.6 - µs Data setup time SIF_D tSU:DAT 0.25 - 0.1 - µs Rise Time SIF_D and SIF_CLK tR - 1000 20+0.1Cb 300 ns Fall Time SIF_D and SIF_CLK tF - 300 20+0.1Cb 300 ns Set-up time for STOP condition tSU:STO 4 - 0.6 - µs Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - µs Pulse width of spikes that will be suppressed by input filters (Note 1) tSP - 60 - 60 ns Capacitive load for each bus line Cb - 400 - 400 pF Noise margin at the LOW level for each connected device (including hysteresis) Vnl 0.1VDD - 0.1VDD - V Noise margin at the HIGH level for each connected device (including hysteresis) Vnh 0.2VDD - 0.2VDD - V Note 1: This figure indicates the pulse width that is guaranteed to be suppressed. Pulse with widths up to 125nsec may alos get suppressed.70 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.5 Four-Wire Digital Audio Interface SCK WS/SDOUT SDIN t ck t dtr t sr t hr t hc t lc Parameter Symbol Maximum Frequency (8MHz) Generic Unit Min Max Min Max DAI_SCK clock period tck 125 - 125 - ns LOW period of the DAI_SCK clock tlc 43 - 0.35tck - ns HIGH period of the DAI_SCK clock thc 43 - 0.35tck - ns Transmit delay time tdtr - 50 - 0.4tck ns Receive set-up time tsr 25 - 0.2tck - ns Receive hold time thr 0 - 0 - ns 22.3.6 Wakeup and Boot Load Timings Parameter Min Typ Max Unit Notes Time for crystal to stabilise ready for Boot Load 0.84 ms Reached oscillator amplitude threshold Time for crystal to stabilise ready for radio activity 1.0 ms Wake up from Deep Sleep or from Sleep (memory not held) 0.84 + 0.5* program size in kBytes ms Assumes SPI clock to external Flash is 16MHz Wake up from Sleep (memory held) 0.84 ms Wake up from CPU Doze mode 0.2 µs Wake up from Sleep using 24MHz RC oscillator (memory held) 0.29 ms© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 71 22.3.7 Bandgap Reference VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Unit Notes Voltage 1.156 1.192 1.216 V DC power supply rejection 58 dB at 25ºC Temperature coefficient -35 +30 ppm/ºC 20 to 85ºC -40ºC to 20ºC Point of inflexion +25 ºC 22.3.8 Analogue to Digital Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Min Typ Max Unit Notes Resolution 12 bits 500kHz Clock Current consumption 655 µA Integral nonlinearity ± 5 LSB 0 to Vref range Differential nonlinearity -1 +2 LSB Guaranteed monotonic Offset error + 10 mV Gain error - 20 mV Internal clock 500 kHz 16MHz input clock, ÷32 No. internal clock periods to sample input 2, 4, 6 or 8 Programmable Conversion time 40 µs 500kHz Clock with sample period of 2 Input voltage range 0.04 Vref or 2*Vref V Switchable. Refer to 20.1.1 Vref (Internal) See Section 22.3.7 Bandgap Reference Vref (External) 1.15 1.2 1.6 V Allowable range into VREF pin Input capacitance 8 pF In series with 5K ohms72 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.9 Digital to Analogue Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Min Typ Max Unit Notes Resolution 12 bits Current consumption 215 (single) 235 (both) µA Integral nonlinearity ± 2 LSB Differential nonlinearity -1 +1 LSB Guaranteed monotonic Offset error ± 10 mV Gain error ± 10 mV Internal clock 2MHz, 1MHz, 500kHz, 250kHz 16MHz input clock, programmable prescaler Output settling time to 0.5LSB 5 µs With 10k ohms & 20pF load Minimum Update time 10 µs 2MHz Clock with sample period of 2 Output voltage swing 0 Lower of Vdd-1.2 and Vref V Output voltage swing Gain =0 Output voltage swing 0 Lower of 2x(Vdd-1.2 ) and Vdd-0.2 and 2xVref V Output voltage swing Gain =1 Vref (Internal) See Section 22.3.7 Bandgap Reference VREF (External) 0.8 1.2 1.6 V Allowable range into VREF pin Resistive load 10 kΩ To ground Capacitive load 20 pF Digital input coding Binary© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 73 22.3.10 Comparators VDD = 2.0 to 3.6V -40 to +85ºC Parameter Min Typ Max Unit Notes Analogue response time (normal) 80 125 ns +/- 250mV overdrive 10pF load Total response time (normal) including delay to Interrupt controller 105 + 125 ns Digital delay can be up to a max. of two 16MHz clock periods Analogue response time (low power) 2.4 µs +/- 250mV overdrive No digital delay Hysteresis 4 12 28 10 20 40 16 26 50 mV Programmable in 3 steps and zero Vref (Internal) See Section 22.3.7 Bandgap Reference V Common Mode input range 0 Vdd V Current (normal mode) 54 73 102 µA Current (low power mode) 0.8 µA 22.3.11 32kHz RC Oscillator VDD = 2.0 to 3.6V, -40 to +85 ºC Parameter Min Typ Max Unit Notes Current consumption of cell and counter logic 1.45 1.25 1.05 µA 3.6V 3.0V 2.0V 32kHz clock native accuracy -30% 32kHz +30% Typical is at 3.0V 25°C Calibrated 32kHz accuracy ±250 ppm For a 1 second sleep period calibrating over 20 x 32kHz clock periods Variation with temperature -0.010 %/°C Variation with VDD2 -1.1 %/V74 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.12 32kHz Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Unit Notes Current consumption of cell and counter logic 1.5 µA This is sensitive to the ESR of the crystal,Vdd and total capacitance at each pin Start – up time 0.8 s Assuming xtal with ESR of less than 40kohms and CL= 9pF External caps = 15pF (Vdd/2mV pk-pk) see Appendix B Input capacitance 1.4 pF Bondpad and package Transconductance 17 uA/V External Capacitors (CL=9pF) 15 pF Total external capacitance needs to be 2*CL, allowing for stray capacitance from chip, package and PCB Amplitude at Xout Vdd-0.2 Vp-p 22.3.13 32MHz Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Unit Notes Current consumption 300 375 450 µA Excluding bandgap ref. Start – up time 0.84 ms Assuming xtal with ESR of less than 40ohms and CL= 9pF External caps = 15pF see Appendix B Input capacitance 1.4 pF Bondpad and package Transconductance 3.65 4.30 5.16 mA/V DC voltages, XTALIN / XTALOUT 390/425 425/465 470/520 mV External Capacitors (CL=9pF) 15 pF Total external capacitance needs to be 2*CL, allowing for stray capacitance from chip, package and PCB Amplitude detect threshold 320 mVp-p Threshold detection accessible via API© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 75 22.3.14 24MHz RC Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Unit Notes Current consumption of cell 160 µA Clock native accuracy -22% 24MHz +28% Calibrated centre frequency accuracy -7% 24MHz +7% Variation with temperature -0.015 %/°C Variation with VDD2 0.15 %/V Startup time 1 us 22.3.15 Temperature Sensor VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Unit Notes Operating Range -40 - 85 °C Sensor Gain -1.44 -1.55 -1.66 mV/°C Accuracy - - ±10 °C Non-linearity - - 2.5 °C Output Voltage 630 855 mV Includes absolute variation due to manufacturing & temp Typical Voltage 745 mV Typical at 3.0V 25°C Resolution 0.154 0.182 0.209 °C/LSB 0 to Vref ADC I/P Range76 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.16 Radio Transceiver This JN5148 meets all the requirements of the IEEE802.15.4 standard over 2.0 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with NXP’s Module Reference Designs. Compliant with FCC part 15, rules, IC Canada, ETSI ETS 300-328 and Japan ARIB STD-T66 The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. Parameter Min Typical Max Notes RF Port Characteristics Type Single Ended Impedance 1 50ohm 2.4-2.5GHz Frequency range 2.400 GHz 2.485GHz ESD levels (pin 17) TDB 1) With external matching inductors and assuming PCB layout as in Appendix B.4.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 77 Radio Parameters: 2.0-3.6V, +25ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -92 -95 dBm Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 Maximum input signal +5 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 19/34 [27/49] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2 / +2 ch) [CW Interferer] 40/45 [54/54] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 48 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 52 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -61 <-70 -58 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 40 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power +0.5 +2.5 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -40 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 10 [2.0] 15 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.178 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Radio Parameters: 2.0-3.6V, -40ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -93.5 -96.5 dBm Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 Maximum input signal +9 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 19/34 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2 / +2 ch) [CW Interferer] 40/45 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 47 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 49 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -60 <-70 -57 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 39 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power +0.75 +2.75 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -38 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 9 [2.0] 15 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 79 Radio Parameters: 2.0-3.6V, +85ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -90 -93 dBm Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 Maximum input signal +3 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 19/34 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2 / +2 ch) [CW Interferer] 40/45 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 49 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 53 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -62 <-70 -59 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 41 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power -0.2 +1.8 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -42 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 10 [2.0] 15 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.180 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3: Up to an extra 2.5dB of attenuation is available if required.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 81 Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing Figure 51: 56-pin QFN Package Drawings Controlling Dimension: mm Symbol millimetres Min. Nom. Max. A ------ ------ 0.9 A1 0.00 0.01 0.05 A2 ------ 0.65 0.7 A3 0.20 Ref. b 0.2 0.25 0.3 D 8.00 bsc D1 7.75 bsc D2 6.20 6.40 6.60 E 8.00 bsc E1 7.75 bsc E2 6.20 6.40 6.60 L 0.30 0.40 0.50 e 0.50 bsc υ1 0° ------ 12° R 0.09 ------ ------ Tolerances of Form and Position aaa 0.10 bbb 0.10 ccc 0.0582 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 A.2 PCB Decal The following PCB decal is recommended; all dimensions are in millimetres (mm). Figure 52: PCB Decal The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 83 A.3 Ordering Information The standard qualification for the JN5148 is Industrial temperature range: -40ºC to +85ºC, packaged in a 56-pin QFN package. Ordering Code Format: JN5148/XXX XXX: ROM Variant 001 Supports all available networking stacks Ordering Codes: Part Number Ordering Code Description JN5148-001 JN5148/001 JN5148 microcontroller The chip is available in three different reel quantities: • 500 on 180mm reel • 1000 on 180mm reel • 2500 on 330mm reel Where this Data Sheet is denoted as “Advanced” or “Preliminary”, devices will be either Engineering Samples or Prototypes. Devices of this status are marked with an Rx suffix after the ROM identifier to identify the revision of silicon during these product phases - for example JN5148-001R1-T. The Standard Supply Multiple (SSM) for Engineering Samples or Prototypes is 50 units with a maximum of 250 units. If the quantity of Engineering Samples or Prototypes ordered is less than a reel quantity, then these will be shipped in tape form only, with no reel and will not be dry packaged in a moisture sensitive environment. The SSM for Production status devices is one reel, all reels are dry packaged in a moisture sensitive bag see A.5.3.84 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 A.4 Device Package Marking The diagram below shows the package markings for JN5148. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the specific markings for a JN5148-001 device, that came from assembly build number 1000135 and was manufactured week 12 of 2008. Jennic JNXXXX-SSS FFFFFFF YYWW Jennic JN5148-001 0812 1000135 Figure 53: Device Package Marking Legend: JN Jennic XXXX 4 digit part number SSS 3 digit software ROM identifier FFFFFFF 7 digit assembly build number YY 2 digit year number WW 2 digit week number Where this Data Sheet is denoted as “Advanced” or “Preliminary”, devices will be either Engineering Samples or Prototypes. Devices of this status have an Rx suffix after the software ROM identifier, for example JN5148-001R1.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 85 A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientation of the 56QFN package in the tape is as shown in Figure 54. Figure 54: Tape and Reel Orientation Figure 55 shows the detailed dimensions of the tape used for 8x8mm 56QFN devices. ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED Reference Dimensions (mm) Ao 8.30 ±0.10 Bo 8.30 ±0.10 Ko 1.10 ±0.10 F 7.50 ±0.10 P1 12.00 ±0.10 W 16.00 ±0.30 (I) Measured from centreline of sprocket hole to centreline of pocket (II) Cumulative tolerance of 10 sprocket holes is ±0.20mm (III) Measured from centreline of sprocket hole to centreline of pocket (IV) Other material available Figure 55: Tape Dimensions86 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 A.5.2 Reel Information: 180mm Reel Surface Resistivity Between 10e9 – 10e11 Ohms Square Material High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space. Figure 56: 180mm Reel Dimensions© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 87 A.5.3 Reel Information: 330mm Reel Surface Resistivity Between 10e9 – 10e11 Ohms Square Material High Impact Polystyrene with Antistatic Additive All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 3 window design to allow adequate labelling space. Figure 57: 330mm Reel Dimensions A.5.4 Dry Pack Requirement for Moisture Sensitive Material Moisture sensitive material, as classified by JEDEC standard J-STD-033, must be dry packed. The 56 lead QFN package is MSL2A/260° C, and is dried before sealing in a moisture barrier bag (MBB) with desiccant bag weighing at 67.5 grams of activated clay and a humidity indicator card (HIC) meeting MIL-L-8835 specification. The MBB has a moisture-sensitivity caution label to indicate the moisture-sensitive classification of the enclosed devices.88 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Appendix B Development Support B.1 Crystal Oscillators This section covers some of the general background to crystal oscillators, to help the user make informed decisions concerning the choice of crystal and the associated capacitors. B.1.1 Crystal Equivalent Circuit Cs Lm Rm Cm C1 C2 Where Cm is the motional capacitance Lm is the motional inductance. This together with Cm defines the oscillation frequency (series) Rm is the equivalent series resistance ( ESR ). CS is the shunt or package capacitance and this is a parasitic B.1.2 Crystal Load Capacitance The crystal load capacitance is the total capacitance seen at the crystal pins, from all sources. As the load capacitance (CL) affects the oscillation frequency by a process known as ‘pulling’, crystal manufacturers specify the frequency for a given load capacitance only. A typical pulling coefficient is 15ppm/pF, to put this into context the maximum frequency error in the IEEE802.15.4 specification is +/-40ppm for the transmitted signal. Therefore, it is important for resonance at 32MHz exactly, that the specified load capacitance is provided. The load capacitance can be calculated using: CL = 1 2 1 2 T T T T C C C C + × Total capacitance CT1 = C1 + C1P + C1in Where C1 is the capacitor component C1P is the PCB parasitic capacitance. With the recommended layout this is about 1.6pF C1in is the on-chip parasitic capacitance and is about 1.4pF typically. Similarly for CT 2 Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 89 B.1.3 Crystal ESR and Required Transconductance The resistor in the crystal equivalent circuit represents the energy lost. To maintain oscillation, power must be supplied by the amplifier, but how much? Firstly, the Pi connected capacitors C1 and C2 with CS from the crystal, apply an impedance transformation to Rm, when viewed from the amplifier. This new value is given by: 2 ˆ + = L S L m m C C C R R The amplifier is a transconductance amplifier, which takes a voltage and produces an output current. The amplifier together with the capacitors C1 and C2, form a circuit, which provides a negative resistance, when viewed from the crystal. The value of which is given by: 2 1× 2 ×ω = T T m NEG C C g R Where gm is the transconductance ω is the frequency in rad/s Derivations of these formulas can be easily found in textbooks. In order to give quick and reliable oscillator start-up, a common rule of thumb is to set the amplifier negative resistance to be a minimum of 4 times the effective crystal resistance. This gives 2 T1× T 2 ×ω m C C g ≥ 2 4 + L S L m C C C R This can be used to give an equation for the required transconductance. 1 2 2 1 2 1 2 2 4 [ ( ) ] T T m S T T T T m C C R C C C C C g × × + + × ≥ ω Example: Using typical 32MHz crystal parameters of Rm =40Ω, CS =1pF and CT1 =CT 2 =18pF ( for a load capacitance of 9pF), the equation above gives the required transconductance ( gm ) as 2.59mA/V. The JN5148 has a typical value for transconductance of 4.3mA/V The example and equation illustrate the trade-off that exists between the load capacitance and crystal ESR. For example, a crystal with a higher load capacitance can be used, but the value of max. ESR that can be tolerated is reduced. Also note, that the circuit sensitivity to external capacitance [ C1 , C2 ] is a square law. Meeting the criteria for start-up is only one aspect of the way these parameters affect performance, they also affect the time taken during start-up to reach a given, (or full), amplitude. Unfortunately, there is no simple mathematical model for this, but the trend is the same. Therefore, both a larger load capacitance and larger crystal ESR will give a longer start-up time, which has the disadvantages of reduced battery life and increased latency. 90 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.2 32MHz Oscillator The JN5148 contains the necessary on-chip components to build a 32 MHz reference oscillator with the addition of an external crystal resonator, two tuning capacitors. The schematic of these components are shown in Figure 58. The two capacitors, C1 and C2, will typically be 15pF ±5% and use a COG dielectric. For a detailed specification of the crystal required and factors affecting C1 and C2 see Appendix B.1. As with all crystal oscillators the PCB layout is especially important, both to keep parasitic capacitors to a minimum and to reduce the possibility of PCB noise being coupled into the oscillator. XTALOUT C1 C2 XTALIN R1 JN5148 Figure 58: Crystal oscillator connections The clock generated by this oscillator provides the reference for most of the JN5148 subsystems, including the transceiver, processor, memory and digital and analogue peripherals. 32MHz Crystal Requirements Parameter Min Typ Max Notes Crystal Frequency 32MHz Crystal Tolerance 40ppm Including temperature and ageing Crystal ESR Range (Rm) 10Ω 60Ω See below for more details Crystal Load Capacitance Range (CL) 6pF 9pF 12pF See below for more details Not all Combinations of Crystal Load Capacitance and ESR are Valid Recommended Crystal Load Capacitance 9pF and max ESR 40 Ω External Capacitors (C1 & C2) For recommended Crystal 15pF CL = 9pF, total external capacitance needs to be 2*CL. , allowing for stray capacitance from chip, package and PCB © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 91 As is stated above, not all combinations of crystal load capacitance and ESR are valid, and as explained in Appendix B.1.3 there is a trade-off that exists between the load capacitance and crystal ESR to achieve reliable performance. For this reason, we recommend that for a 9pF load capacitance crystals be specified with a maximum ESR of 40 ohms. For lower load capacitances the recommended maximum ESR rises, for example, CL=7pF the max ESR is 61 ohms. For the lower cost crystals in the large HC49 package, a load capacitance of 9 or 10pF is widely available and the max ESR of 30 ohms specified by many manufacturers is acceptable. Also available in this package style, are crystals with a load capacitance of 12pF, but in this case the max ESR required is 25 ohms or better. Below is measurement data showing the variation of the crystal oscillator amplifier transconductance with temperature and supply voltage, notice how small the variation is. Circuit techniques have been used to apply compensation, such that the user need only design for nominal conditions. 32MHz Crystal Oscillator 4.1 4.15 4.2 4.25 4.3 4.35 -40 -20 0 20 40 60 80 100 Temperature (C) Transconductance (mA/V) 32MHz Crystal Oscillator 4.28 4.29 4.3 4.31 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Supply Voltage (VDD) Transconductance (mA/V)92 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN5148 contains the necessary on-chip components to build an optional 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between XTAL32K_IN and XTAL32K_OUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. The schematic of these components are shown in Figure 59. The two capacitors, C1 and C2, will typically be in the range 10 to 22pF ±5% and use a COG dielectric. As with all crystal oscillators the PCB layout is especially important, both to keep parasitic capacitors to a minimum and to reduce the possibility of PCB noise being coupled into the oscillator. XTAL32K_IN XTAL32K_OUT JN5148 Figure 59: 32kHz crystal oscillator connections The electrical specification of the oscillator can be found in 22.3.12. The oscillator cell is flexible and can operate with a range of commonly available 32kHz crystals with load capacitances from 6 to 12.5p, and ESR up to 80KΩ. It achieves this by using automatic gain control (AGC), which senses the signal swing. As explained in Appendix B.1.3 there is a trade-off that exists between the load capacitance and crystal ESR to achieve reliable performance. The use of an AGC function allows a wider range of crystal load capacitors and ESR’s to be accommodated than would otherwise be possible. However, this benefit does mean the supply current varies with the supply voltage (VDD), value of the total capacitance at each pin, and the crystal ESR. This is described in the table and graphs below. 32kHz Crystal Requirements Parameter Min Typ Max Notes Crystal Frequency 32kHz Supply Current 1.6uA Vdd=3v, temp=25 C, load cap =9pF, Rm=25K Supply Current Temp. Coeff. 0.1%/ C Vdd=3v Crystal ESR Range (Rm) 10KΩ 25KΩ 80KΩ See below for more details Crystal Load Capacitance Range (CL) 6pF 9pF 12.5pF See below for more details Not all Combinations of Crystal Load Capacitance and ESR are Valid © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 93 Three examples of typical crystals are given, each with the value of external capacitors to use, plus the likely supply current and start-up time that can be expected. Also given is the maximum recommended ESR based on the start-up criteria given in Appendix B.1.3. The values of the external capacitors can be calculated using the equation in Appendix B.1.2 . Load Capacitance Ext Capacitors Current Start-up Time Max ESR 9pF 15pF 1.6uA 0.8Sec 70KΩ 6pF 9pF 1.4uA 0.6sec 80KΩ 12.5pF 22pF 2.4uA 1.1sec 35KΩ Below is measurement data showing the variation of the crystal oscillator supply current with voltage and with crystal ESR, for two load capacitances. 32KHz Crystal Oscillator Current 0.6 0.8 1 1.2 1.4 1.6 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Supply Voltage (VDD) Normalised Current (IDD) 32KHz Crystal Oscillator Current 0.6 0.8 1 1.2 1.4 1.6 10 20 30 40 50 60 70 80 Crystal ESR (K ohm) Normalised Current (IDD) 9pF 12.5pF94 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.4 JN5148 Module Reference Designs For customers wishing to integrate the JN5148 device directly into their system, NXP provide a range of Module Reference Designs, covering standard and high-power modules fitted with different Antennae To ensure the correct performance, it is strongly recommended that where possible the design details provided by the reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions, track layouts etc. In order to minimise all risks, it is recommended that the entire layout of the appropriate reference module, if possible, be replicated in the end design. For full details, consult the Standard Module Reference Design JN-RD-6015 [6]. B.4.1 Schematic Diagram A schematic diagram of the JN5148 PCB antenna reference module is shown in Figure 60. Details of component values and PCB layout constraints can be found in Table 8. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 56 55 54 53 52 51 50 49 48 47 46 45 44 43 SPI Selects Analogue IO UART0/JTAG Timers Two Wire Serial Port RXD1 UART1/JTAG DIO16 CTS1 VSS3 RTS1 TXD1 VSS2 VSSS XTAL_OUT XTAL_IN VB_SYNTH VCOTUNE (NC) VB_VCOR1 43K IBIAS C16 100nF VDD1 C14 100nF VDD C13 10uF C24 47pF C18 47pF C2 10nF C15 100nF Y1 C11 15pF C10 15pF C20 100nF L2 2.7nH VB_RF VREF VB_RF2 RF_IN VB_RF C12 47pF C3 100nF VB_RF1 C1M C1P ADC1 ADC2 ADC3 ADC4 C2M C2P VB_A C9 47pF C8 100nF NC VDD VDD RXD1 SPIMOSI SPIMOSI SPICLK SPICLK C6 100nF C7 100nF SPISEL3 SPISEL2 VB_DIG RESETN SPISEL1 SPISEL0 VB_RAM SPIMISO VSS1 DAC2 DAC1 1 2 3 4 8 7 6 5 SS SD0 WP VSS SDI CLK HOLD VCC Serial Flash Memory RXD0 TXD0 RTS0 CTS0 SPISEL4 VDD SIF_D SIF_CLK TIM1OUT TIM1CAP TIM1CK_GT TIM0OUT TIM0CAP VDD2 TIM0CK_GT VSSA JN5148 C1 47pF L1 5.6nH To Coaxial Socket Or Integrated Antenna Figure 60: JN5148 Printed Antenna Reference Module Schematic Diagram© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 95 Component Designator Value/Type Function PCB Layout Constraints C13 10uF Power source decoupling C14 100nF Analogue Power decoupling Adjacent to U1 pin 13 C16 100nF Digital power decoupling Adjacent to U1 pin 49 C15 100nF VB Synth decoupling Less than 5mm from U1 pin 10 C18 47pF VB Synth decoupling Less than 5mm from U1 pin 10 C2 10nF VB VCO decoupling Less than 5mm from U1 pin 12 C24 47pF VB VCO decoupling Less than 5mm from U1 pin 12 C3 100nF VB RF decoupling Less than 5mm from U1 pin 16 and U1 pin 18 C12 47pF VB RF decoupling Less than 5mm from U1 pin 16 and U1 pin 18 C8 100nF VB A decoupling Less than 5mm from U1 pin 27 C9 47pF VB A decoupling Less than 5mm from U1 pin 27 C6 100nF VB RAM decoupling Less than 5mm from U1 pin 35 C7 100nF VB Dig decoupling Less than 5mm from U1 pin 40 R1 43k I Bias Resistor Less than 5mm from U1 pin 14 C20 100nF Vref decoupling Less than 5mm from U1 pin 15 U2 4Mbit Serial Flash Memory (Numonyx M25P40) Y1 32MHz Crystal (AEL X32M000000S025) (CL = 9pF, Max ESR 40R) C10 15pF +/-5% COG Crystal Load Capacitor Adjacent to pin 8 and Y1 pin 1 C11 15pF +/-5% COG Crystal Load Capacitor Adjacent to pin 9 and Y1 pin 3 R2 Not fitted C1 47pF AC Coupling Phycomp 2238-869-15479 Must be copied directly from the reference design. L1 5.6nH RF Matching Inductor MuRata LQP15MN5N6B02 L2 2.7nH Load Inductor MuRata LQP15MN2N7B02 Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout Constraints The paddle should be connected directly to ground. Any pads that requiring connection to ground should do so by connecting directly to the paddle.96 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.4.2 PCB Design and Reflow Profile PCB and land pattern designs are key to the reliability of any electronic circuit design. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) defines a number of standards for electronic devices. One of these is the "Surface Mount Design and Land Pattern Standard" IPC-SM-782 [3], commonly referred to as “IPC782". This specification defines the physical packaging characteristics and land patterns for a range of surface mounted devices. IPC782 is also a useful reference document for general surface mount design techniques, containing sections on design requirements, reliability and testability. NXP strongly recommends that this be referred to when designing the PCB. The suggested reflow profile is shown in Figure 61. The specific paste manufacturers guidelines on peak flow temperature, soak times, time above liquidus and ramp rates should also be referenced. Figure 61: Recommended Reflow Profile for Lead-free Solder Paste or PPF lead frame© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 97 Related Documents [1] IEEE Std 802.15.4-2003 IEEE Standard for Information Technology – Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs). [2] JN-AN-1038 Programming Flash devices not supported by the JN51xx ROM-based bootloader [3] IPC-SM-782 Surface Mount Design and Land Pattern Standard [4] JN-AN-1118 JN5148 Application Debugging [5] JN-UG-3066 JN51xx Integrated Peripherals API User Guide [6] JN-RD-6015 Standard Module Reference Design [7] JN-AN-1003 Boot Loader Operation RoHS Compliance JN5148 devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS) and of the China RoHS (SJ/T11363 – 2006) requirements which came into force on 1st March 2007. Status Information The status of this Data Sheet is. Production NXP products progress according to the following format: Advance The Data Sheet shows the specification of a product in planning or in development. The functionality and electrical performance specifications are target values of the design and may be used as a guide to the final specification. Integrated circuits are identified with an Rx suffix, for example JN5148-001R1. NXP reserves the right to make changes to the product specification at anytime without notice. Preliminary The Data Sheet shows the specification of a product that is commercially available, but is not yet fully qualified. The functionality of the product is final. The electrical performance specifications are target values and may used as a guide to the final specification. Integrated circuits are identified with an Rx suffix, for example JN5148-001R1. NXP reserves the right to make changes to the product specification at anytime without notice. Production This is the production Data Sheet for the product. All functional and electrical performance specifications, where included, including min and max values are derived from detailed product characterization. This Data Sheet supersedes all previous document versions. NXP reserves the right to make changes to the product specification at anytime.98 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Operating Conditions section or the Electrical Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. 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Trademarks All trademarks are the property of their respective owners.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 99 Version Control Version Notes 1.0 12th December 2008 – First issue, released as Advance Information 1.1 15th May 2009 – Major revision 1.2 15th July – Released as Preliminary and revised Electrical Parameters section 1.3 20th January 2010 – Revision to sections 1.1, 2.2.1 & 8.1 – 8.4 and figs 1,2,22 & 47. Also, the bill of materials and reference design number have been updated. 1.4 2nd April 2010 – Released as Production with revised Electrical Parameters section 1.5 14th September 2010 – Logo updated and support for JenNet added 1.6 24th November 2010 – Ordering information changed 1.7 5th May 2011 – Tape and reel information updated 1.8 12th September 2012 – NXP branding applied 1.9 6th September 2013 – Modified description of interrupts within the CPU in Chapter 3100 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Contact Details NXP Laboratories UK Ltd (Formerly Jennic Ltd) Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 For the contact details of your local NXP office or distributor, refer to the NXP web site: www.nxp.com Data Sheet: JN516x IEEE802.15.4 Wireless Microcontroller © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 1 Overview Features: Radio • 2.4GHz IEEE802.15.4 compliant • 128-bit AES security processor • MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers • Integrated ultra low power sleep oscillator – 0.6µA • 2.0V to 3.6V battery operation • Deep sleep current 0.12µA (Wake-up from IO) • <$0.15 external component cost • RX current 17mA , TX 15mA • Receiver sensitivity -95dBm • Transmit power 2.5dBm • Time of Flight engine for ranging • Antenna Diversity (Auto RX) Features: Microcontroller • 32-bit RISC CPU, 1 to 32MHz clock speed • Variable instruction width for high coding efficiency • Multi-stage instruction pipeline • JN5161: 64kB/8kB/4kB • JN5164: 160kB/32kB/4kB • JN5168: 256kB/32kB/4kB (Flash/RAM/EEPROM) • Data EEPROM with guaranteed 100k write operations. • RF4CE, JenNet-IP, ZigBee SE and ZigBee Light Link stacks • 2-wire I2C compatible serial interface. Can operate as either master or slave • 5xPWM (4x timer & 1 timer/counter) • 2 low power sleep counters • 2x UART • SPI Master & Slave port, 3 selects • Supply voltage monitor with 8 programmable thresholds • 4-input 10-bit ADC, comparator • Battery and temperature sensors • Watchdog & Brown Out Reset • Up to 20 Digital IO Pins (DIO) • Infra-red remote control transmitter Temp range (-40°C to +125°C) 6x6mm 40-lead Lead-free and RoHS compliant The JN516x series is a range of ultra low power, high performance wireless microcontrollers supporting JenNet-IP, ZigBee PRO or RF4CE networking stacks to facilitate the development of Home Automation, Smart Energy, Light Link and Remote control applications. They feature an enhanced 32- bit RISC processor with embedded Flash and EEPROM memory, offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds. They also include a 2.4GHz IEEE802.15.4 compliant transceiver and a comprehensive mix of analogue and digital peripherals. Three memory configurations are available to suit different applications. The best in class operating current of 15mA, with a 0.6uA sleep timer mode, gives excellent battery life allowing operation direct from a coin cell. The peripherals support a wide range of applications. They include a 2-wire I 2 C, and SPI ports which can operate as either master or slave, a four channel ADC with battery and a temperature sensor. It can support a large switch matrix of up to 100 elements, or alternatively a 20 key capacitive touch pad. Block Diagram 32-bit RISC CPU 4xPWM + Timer 2xUART 10-bit ADC Battery and Temp Sensors 2-Wire Serial (Master/Slave) SPI Master & Slave RAM 128-bit AES Hardware 2.4GHz Including Diversity Flash Power Management XTAL O-QPSK Modem 4kB EEPROM 20 DIO Sleep Counter Watchdog Timer Voltage Brownout 8/32K 64/160/256K Radio 4-Channel IEEE 802.15.4 Baseband Processor Encryption Benefits • Single chip device to run stack and application • Very low current solution for long battery life – over 10 yrs • Supports multiple network stacks • Highly featured 32-bit RISC CPU for high performance and low power • System BOM is low in component count and cost • Flexible sensor interfacing options Applications • Robust and secure low power wireless applications • RF4CE Remote Controls • JenNet-IP networks • ZigBee SE networks • ZigBee Light Link networks • Lighting & Home automation • Toys and gaming peripherals • Smart Energy • Energy harvesting, for example self powered light switch2 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Contents Benefits 1 Applications 1 1 Introduction 6 1.1 Wireless Transceiver 6 1.2 RISC CPU and Memory 6 1.3 Peripherals 7 1.4 Block Diagram – JN516x 8 2 Pin Configurations 9 2.1 Pin Assignment 10 2.2 Pin Descriptions 12 2.2.1 Power Supplies 12 2.2.2 Reset 12 2.2.3 32MHz Oscillator 12 2.2.4 Radio 12 2.2.5 Analogue Peripherals 13 2.2.6 Digital Input/Output 13 3 CPU 15 4 Memory Organisation 16 4.1 FLASH 16 4.2 RAM 16 4.3 OTP Configuration Memory 16 4.4 EEPROM 17 4.5 External Memory 17 4.6 Peripherals 17 4.7 Unused Memory Addresses 17 5 System Clocks 18 5.1 High-Speed (32MHz) System Clock 18 5.1.1 32MHz Crystal Oscillator 18 5.1.2 High-Speed RC Oscillator 19 5.2 Low-speed (32kHz) System Clock 19 5.2.1 32kHz RC Oscillator 19 5.2.2 32kHz Crystal Oscillator 20 5.2.3 32kHz External Clock 20 6 Reset 21 6.1 Internal Power-On / Brown-out Reset (BOR) 21 6.2 External Reset 22 6.3 Software Reset 22 6.4 Supply Voltage Monitor (SVM) 22 6.5 Watchdog Timer 23 7 Interrupt System 24 7.1 System Calls 24 7.2 Processor Exceptions 24 7.2.1 Bus Error 24© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 3 7.2.2 Alignment 24 7.2.3 Illegal Instruction 24 7.2.4 Stack Overflow 24 7.3 Hardware Interrupts 25 8 Wireless Transceiver 26 8.1 Radio 26 8.1.1 Radio External Components 27 8.1.2 Antenna Diversity 27 8.2 Modem 29 8.3 Baseband Processor 30 8.3.1 Transmit 30 8.3.2 Reception 30 8.3.3 Auto Acknowledge 31 8.3.4 Beacon Generation 31 8.3.5 Security 31 8.4 Security Coprocessor 31 8.5 Time of Flight Engine 31 9 Digital Input/Output 32 10 Serial Peripheral Interface 34 10.1 Serial Peripheral Interface Master 34 10.2 Serial Peripheral Interface Slave 37 11 Timers 38 11.1 Peripheral Timer/Counters 38 11.1.1 Pulse Width Modulation Mode 39 11.1.2 Capture Mode 39 11.1.3 Counter/Timer Mode 40 11.1.4 Delta-Sigma Mode 40 11.1.5 Infra-Red Transmission Mode 41 11.1.6 Example Timer/Counter Application 41 11.2 Tick Timer 42 11.3 Wakeup Timers 42 11.3.1 32 KHZ RC Oscillator Calibration 43 12 Pulse Counters 44 13 Serial Communications 45 13.1 Interrupts 46 13.2 UART Application 46 14 JTAG Test Interface 48 15 Two-Wire Serial Interface (I2 C) 49 15.1 Connecting Devices 49 15.2 Clock Stretching 50 15.3 Master Two-wire Serial Interface 50 15.4 Slave Two-wire Serial Interface 52 16 Random Number Generator 534 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 17 Analogue Peripherals 54 17.1 Analogue to Digital Converter 54 17.1.1 Operation 55 17.1.2 Supply Monitor 56 17.1.3 Temperature Sensor 56 17.1.4 ADC Sample Buffer Mode 56 17.2 Comparator 56 18 Power Management and Sleep Modes 57 18.1 Operating Modes 57 18.1.1 Power Domains 57 18.2 Active Processing Mode 57 18.2.1 CPU Doze 57 18.3 Sleep Mode 57 18.3.1 Wakeup Timer Event 58 18.3.2 DIO Event 58 18.3.3 Comparator Event 58 18.3.4 Pulse Counter 58 18.4 Deep Sleep Mode 58 19 Electrical Characteristics 59 19.1 Maximum Ratings 59 19.2 DC Electrical Characteristics 59 19.2.1 Operating Conditions 59 19.2.2 DC Current Consumption 60 19.2.3 I/O Characteristics 61 19.3 AC Characteristics 61 19.3.1 Reset and Supply Voltage Monitor 61 19.3.2 SPI Master Timing 63 19.3.3 SPI Slave Timing 64 19.3.4 Two-wire Serial Interface 65 19.3.5 Wakeup Timings 65 19.3.6 Bandgap Reference 66 19.3.7 Analogue to Digital Converters 66 19.3.8 Comparator 67 19.3.9 32kHz RC Oscillator 67 19.3.10 32kHz Crystal Oscillator 68 19.3.11 32MHz Crystal Oscillator 68 19.3.12 High-Speed RC Oscillator 69 19.3.13 Temperature Sensor 69 19.3.14 Non-Volatile Memory 69 19.3.15 Radio Transceiver 70 Appendix A Mechanical and Ordering Information 76 A.1 SOT618-1 HVQFN40 40-pin QFN Package Drawing 76 A.2 Footprint Information 77 A.3 Ordering Information 78 A.4 Device Package Marking 79 A.5 Tape and Reel Information 80 A.5.1 Tape Orientation and Dimensions 80 A.5.2 Reel Information: 180mm Reel 81 A.5.3 Reel Information: 330mm Reel 82© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 5 A.5.4 Dry Pack Requirement for Moisture Sensitive Material 82 Appendix B Development Support 83 B.1 Crystal Oscillators 83 B.1.1 Crystal Equivalent Circuit 83 B.1.2 Crystal Load Capacitance 83 B.1.3 Crystal ESR and Required Transconductance 84 B.2 32MHz Oscillator 85 B.3 32kHz Oscillator 87 B.4 JN516x Module Reference Designs 89 B.4.1 Schematic Diagram 89 B.4.2 PCB Design and Reflow Profile 91 B.4.3 Moisture Sensitivity Level (MSL) 91 Related Documents 92 RoHS Compliance 92 Status Information 92 Disclaimers 93 Trademarks 93 Version Control 93 Contact Details 946 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 1 Introduction The JN516x is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including Zigbee PRO, ZigBee Smart Energy, ZigBee LightLink, RF4CE and JenNet-IP. There are 3 versions in the range, differing only by memory configuration JN5161-001: 64kB Flash, 8kB RAM, 4 kB EEPROM, suitable for IEEE802.15.4 and RF4CE applications JN5164-001: 160kB Flash, 32kB RAM, 4 kB EEPROM suitable for Jennet-IP, IEEE802.15.4 and RF4CE applications JN5168-001: 256kB Flash, 32kB RAM, 4 kB EEPROM suitable for all applications Applications that transfer data wirelessly tend to be more complex than wired ones. Wireless protocols make stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application development must consider the requirements of the wireless network in addition to the product functionality and user interfaces. To minimise this complexity, NXP provides a series of software libraries and interfaces that control the transceiver and peripherals of the JN516x. These libraries and interfaces remove the need for the developer to understand wireless protocols and greatly simplifies the programming complexities of power modes, interrupts and hardware functionality. In view of the above, it is not necessary to provide the register details of the JN516x in the datasheet. The device includes a Wireless Transceiver, RISC CPU, on chip memory and an extensive range of peripherals. 1.1 Wireless Transceiver The Wireless Transceiver comprises a 2.45GHz radio, a modem, a baseband controller and a security coprocessor. In addition, the radio also provides an output to control transmit-receive switching of external devices such as power amplifiers allowing applications that require increased transmit power to be realised very easily. Appendix B.4, describes a complete reference design including Printed Circuit Board (PCB) design and Bill Of Materials (BOM). The security coprocessor provides hardware-based 128-bit AES-CCM* modes as specified by the IEEE802.15.4 2006 standard. Specifically this includes encryption and authentication covered by the MIC –32/-64/-128, ENC and ENC-MIC –32/-64/-128 modes of operation. The transceiver elements (radio, modem and baseband) work together to provide IEEE802.15.4 (2006) MAC and PHY functionality under the control of a protocol stack. Applications incorporating IEEE802.15.4 functionality can be developed rapidly by combining user-developed application software with a protocol stack library. 1.2 RISC CPU and Memory A 32-bit RISC CPU allows software to be run on-chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN516x has a unified memory architecture, code memory, data memory, peripheral devices and I/O ports are organised within the same linear address space. The device contains up to 256kbytes of Flash, up to 32kbytes of RAM and 4kbytes EEPROM . © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 7 1.3 Peripherals The following peripherals are available on chip: • Master SPI port with three select outputs • Slave SPI port • Two UART’s, one capable of hardware flow control (4-wire, includes RTS/CTS), and the other just 2-wire (RX/TX) • One programmable Timer/Counter which supports Pulse Width Modulation (PWM) and capture/compare, plus four PWM timers which support PWM and Timer modes only. • Two programmable Sleep Timers and a Tick Timer • Two-wire serial interface (compatible with SMbus and I2 C) supporting master and slave operation • Twenty digital I/O lines (multiplexed with peripherals such as timers, SPI and UARTs) • Two digital outputs (multiplexed with SPI port) • 10-bit, Analogue to Digital converter with up to four input channels. Autonomous multi-channel sampling • Programmable analogue comparator • Internal temperature sensor and battery monitor • Two low power pulse counters • Random number generator • Watchdog Timer and Supply Voltage Monitor • JTAG hardware debug port • Infra-red remote control transmitter, supported by one of the PWM timers • Transmit and receive antenna diversity with automatic receive switching based on received energy detection • Time of Flight engine for ranging User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. 8 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 1.4 Block Diagram – JN516x Wireless Transceiver 32-bit RISC CPU MUX Security Processor Digital Baseband Radio Programmable Interrupt Controller From Peripherals RF_IN VCOTUNE Tick Timer Voltage Regulators 1.8V VDD1 VDD2 IBIAS VB_XX EEPROM 4KB CPU and 16MHz System Clock 32MHz Xtal Clock Generator XTAL_IN XTAL_OUT Clock Source & Rate Select Highspeed RC Osc Watchdog Timer Supply Voltage Monitor Reset Wakeup Timer1 Wakeup Timer0 RESETN 32kHz Clock Select 32KIN Comparator1 COMP1P COMP1M ADC M U ADC4 X ADC1 VREF/ADC2 ADC3 Temperature Sensor Supply Monitor 32kHz RC Osc 32kHz Xtal Osc 32KXTALIN 32KXTALOUT SPI Slave DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19 DO0 DO1 TXD0 SPI Master UART0 UART1 RXD0 RTS0 CTS0 TxD1 RxD1 TIM0CK_GT TIM0OUT TIM0CAP PWM1 PWM2 PWM3 PWM4 SIF_D SIF_CLK PC0 PC1 JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO ADO ADE Timer0 PWMs 2-wire Interface Pulse Counters JTAG Debug Antenna Diversity SPICLK SPIMOSI SPIMISO SPISEL0 SPICLK SPIMOSI SPIMISO SPISEL0 SPISEL1 SPISEL2 FLASH 256/160/64KB RAM 32/32/8KB Figure 1: JN516x Block Diagram© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 9 2 Pin Configurations 1 40 39 38 37 36 35 34 33 32 31 VSSA 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 DIO16 DIO17 RESETN XTAL_OUT XTAL_IN VB_SYNTH VCOTUNE VB_VCO VDD1 IBIAS VREF/ADC2 VB_RF2 RF_IN VB_RF1 ADC1 DIO0 DIO1 DIO2 DIO3 DO0 VSS1 DO1 DIO18 DIO19 VB_RAM DIO4 DIO5 DIO6 DIO7 VDD2 DIO15 VSS2 DIO14 DIO13 DIO12 VB_DIG DIO11 DIO10 DIO9 DIO8 Figure 2: 40-pin QFN Configuration (top view) Note: Please refer to Appendix B.4 JN516x Module Reference Design for important applications information regarding the connection of the PADDLE to the PCB. 10 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 2.1 Pin Assignment Pin No Power supplies Signal Type Description 6, 8, 12, 14, 25, 35 VB_SYNTH, VB_VCO, VB_RF2, VB_RF1, VB_RAM, VB_DIG 1.8V Regulated supply voltage 9, 30 VDD1, VDD2 3.3V Supplies: VDD1 for analogue, VDD2 for digital 21, 39, Paddle VSS1, VSS2, VSSA 0V Grounds (see appendix A.2 for paddle details) General 3 RESETN CMOS Reset input 4,5 XTAL_OUT, XTAL_IN 1.8V System crystal oscillator Radio 7 VCOTUNE 1.8V VCO tuning RC network 10 IBIAS 1.8V Bias current control 13 RF_IN 1.8V RF antenna Analogue Peripheral I/O 15, 16, 17 ADC1, DIO0 (ADC3), DIO1 (ADC4) 3.3V ADC inputs 11 VREF/ADC2 1.8V Analogue peripheral reference voltage or ADC input 2 1, 2 DIO16 (COMP1P), DIO17 (COMP1M) 3.3V Comparator inputs Digital Peripheral I/O Primary Alternate Functions 16 DIO0 SPISEL1 ADC3 CMOS DIO0, SPI Master Select Output 1 or ADC input 3 17 DIO1 SPISEL2 ADC4 PC0 CMOS DIO1, SPI Master Select Output 2, ADC input 4 or Pulse Counter 0 Input 18 DIO2 RFRX TIM0CK_GT CMOS DIO2, Radio Receive Control Output or Timer0 Clock/Gate Input 19 DIO3 RFTX TIM0CAP CMOS DIO3, Radio Transmit Control Output or Timer0 Capture Input 26 DIO4 CTS0 JTAG_TCK TIM0OUT PC0 CMOS DIO4, UART 0 Clear To Send Input, JTAG CLK Input, Timer0 PWM Output, or Pulse Counter 0 input 27 DIO5 RTS0 JTAG_TMS PWM1 PC1 CMOS DIO5, UART 0 Request To Send Output, JTAG Mode Select Input, PWM1 Output or Pulse Counter 1 Input 28 DIO6 TXD0 JTAG_TDO PWM2 CMOS DIO6, UART 0 Transmit Data Output, JTAG Data Output or PWM2 Output 29 DIO7 RXD0 JTAG_TDI PWM3 CMOS DIO7, UART 0 Receive Data Input, JTAG Data Input or PWM 3 Output 31 DIO8 TIM0CK_GT PC1 PWM4 CMOS DIO8, Timer0 Clock/Gate Input, Pulse Counter1 Input or PWM 4 Output© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 11 32 DIO9 TIM0CAP 32KXTALIN RXD1 32KIN CMOS DIO9, Timer0 Capture Input, 32K External Crystal Input, UART 1 Receive Data Input or 32K external clock Input 33 DIO10 TIM0OUT 32KXTALOUT CMOS DIO10, Timer0 PWM Output or 32K External Crystal Output 34 DIO11 PWM1 TXD1 CMOS DIO11, PWM1 Output or UART 1 Transmit Data Output 36 DIO12 PWM2 CTS0 JTAG_TCK ADO SPISMO SI CMOS DIO12, PWM2 Output, UART 0 Clear To Send Input, JTAG CLK Input, Antenna Diversity Odd Output or SPI Slave Master Out Slave In Input 37 DIO13 PWM3 RTS0 JTAG_TMS ADE SPISMI SO CMOS DIO13, PWM3 Output, UART 0 Request To Send Output, JTAG Mode Select Input, Antenna Diversity Even output or SPI Slave Master In Slave Out Output 38 DIO14 SIF_CLK TXD0 TXD1 JTAG_TDO SPISEL 1 SPISSE L CMOS DIO14, Serial Interface Clock, UART 0 Transmit Data Output, UART 1 Transmit Data Output, JTAG Data Output, SPI Master Select Output 1 or SPI Slave Select Input 40 DIO15 SIF_D RXD0 RXD1 JTAG_TDI SPISEL 2 SPISCL K CMOS DIO15, Serial Interface Data, UART 0 Receive Data Input, UART 1 Receive Data Input, JTAG Data Input, SPI Master Select Output 2 or SPI Slave Clock Input 1 DIO16 COMP1P SIF_CLK SPISMOSI CMOS DIO16, Comparator Positive Input, Serial Interface clock or SPI Slave Master Out Slave In Input 2 DIO17 COMP1M SIF_D SPISMISO CMOS DIO17, Comparator Negative Input, Serial Interface Data or SPI Slave Master In Slave Out Output 23 DIO18 SPIMOSI CMOS SPI Master Out Slave In Output 24 DIO19 SPISEL0 CMOS SPI Master Select Output 0 20 DO0 SPICLK PWM2 CMOS SPI Master Clock Output or PWM2 Output 22 DO1 SPIMISO PWM3 CMOS SPI Master In Slave Out Input or PWM3 Output The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN516x failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.12 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 2.2 Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 is the power supply for the digital circuitry; and should also be decoupled to ground. In addition, a common 10µF tantalum capacitor is required for low frequencies. Decoupling pins for the internal 1.8V regulators are provided which each require a100nF capacitor located as close to the device as practical. VB_SYNTH, VB_RAM and VB_DIG require only a 100nF capacitor. VB_RF and VB_RF2 should be connected together as close to the device as practical, and require one 100nF capacitor and one 47pF capacitor. The pin VB_VCO requires a 10nF capacitor. Refer to B.4.1 for schematic diagram. VSSA (paddle), VSS1, VSS2 are the ground pins. Users are strongly discouraged from connecting their own circuits to the 1.8v regulated supply pins, as the regulators have been optimised to supply only enough current for the internal circuits. 2.2.2 Reset RESETN is an active low reset input pin that is connected to a 500kΩ internal pull-up resistor. It may be pulled low by an external circuit. Refer to Section 6.2 for more details. 2.2.3 32MHz Oscillator A crystal is connected between XTAL_IN and XTAL_OUT to form the reference oscillator, which drives the system clock. A capacitor to analogue ground is required on each of these pins. Refer to Section 5.1 for more details. The 32MHz reference frequency is divided down to 16MHz and this is used as the system clock throughout the device. 2.2.4 Radio The radio is a single ended design, requiring a capacitor and just two inductors to match to 50Ω microstrip line to the RF_IN pin. An external resistor (43kΩ) is required between IBIAS and analogue ground (paddle) to set various bias currents and references within the radio.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 13 2.2.5 Analogue Peripherals The ADC requires a reference voltage to use as part of its operation. It can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ground and the performance of the analogue peripherals is dependent on the quality of this reference. There are four ADC inputs and a pair of comparator inputs. ADC1 has a designated input pin but ADC2 uses the same pin as VREF, invalidating its use as an ADC pin when an external reference voltage is required. The remaining 2 ADC channels are shared with the digital I/Os DIO0 and DIO1 and connect to pins 16 and 17. When these two ADC channels are selected, the corresponding DIOs must be configured as Inputs with their pull-ups disabled. Similarly, the comparator shares pins 1 and 2 with DIO16 and DIO17, so when the comparator is selected these pins must be configured as Inputs with their pull-ups disabled. The analogue I/O pins on the JN516x can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in Figure 3. Figure 4 demonstrates a special case, where a digital I/O pin doubles as an input to analogue devices. This applies to ADC3, ADC4, COMP1P and COMP1M. In reset, sleep and deep sleep, the analogue peripherals are all off. In sleep, the comparator may optionally be used as a wakeup source. Unused ADC and comparator inputs should not be left unconnected, for example connected to analogue ground. VDD1 Analogue I/O Pin VSSA Analogue Peripheral Figure 3: Analogue I/O Cell 2.2.6 Digital Input/Output For the DC properties of these pins see Section 19.2.3. When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal pull up resistors (50kΩ nominal) that can be disabled. When used in their secondary function (selected when the appropriate peripheral block is enabled through software library calls), their direction is fixed by the function. The pull up resistor is enabled or disabled independently of the function and direction; the default state from reset is enabled. A schematic view of the digital I/O cell is in Figure 4. The dotted lines through resistor RESD represent a path that exists only on DIO0, DIO1, DIO16 and DIO17 which are also inputs to the ADC (ADC3, ADC4) and Comparator (COMP1P, COMP1M) respectively. To use these DIO pins for their analogue functions, the DIO must be set as an Input with its pull-up resistor, RPU, disabled.14 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 O VDD2 Pu RPU OE DIO[x] Pin RESD ADC or COMP1 Input I IE RPROT VSS VSS Figure 4: DIO Pin Equivalent Schematic In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN516x from sleep.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 15 3 CPU The CPU of the JN516x is a 32-bit load and store RISC processor. It has been architected for three key requirements: • Low power consumption for battery powered applications • High performance to implement a wireless protocol at the same time as complex applications • Efficient coding of high-level languages such as C provided with the Software Developers Kit It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the same address space. Registers for peripheral units, such as the timers, UART and the baseband processor are also mapped into this space. The CPU has access to a block of 15 32-bit General-Purpose (GP) registers together with a small number of special purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle while those that access memory require a further cycle to allow the memory to respond. The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms needed by Digital Signal Processing applications. The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in complex data structures is very efficient due to the provision of several addressing modes, together with the ability to be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming method for the JN516x is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger. The CPU architecture also contains features that make the processor suitable for embedded, real-time applications. In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the processor. To provide protection for device-wide resources being altered by one task and affecting another, the processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in user mode in a RTOS environment. Embedded applications require efficient handling of external hardware events. Exception processing (including reset and interrupt handling) is enhanced by the inclusion of a number of special-purpose registers into which the PC and status register contents are copied as part of the operation of the exception hardware. This means that the essential registers for exception handling are stored in one cycle, rather than the slower method of pushing them onto the processor stack. The PC is also loaded with the vector address for the exception that occurred, allowing the handler to start executing in the next cycle. To improve power consumption a number of power-saving modes are implemented in the JN516x, described more fully in Section 18. One of these modes is the CPU doze mode; under software control, the processor can be shut down and on an interrupt it will wake up to service the request. Additionally, it is possible under software control, to set the speed of the CPU to 1, 2, 4, 8, 16 or 32MHz. This feature can be used to trade-off processing power against current consumption.16 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 4 Memory Organisation This section describes the different memories found within the JN516x. The device contains Flash, RAM, and EEPROM memory, the wireless transceiver and peripherals all within the same linear address space. 0xFFFFFFFF Unpopulated 0xF0008000 RAM 0x04000000 0x02000000 FLASH Boot Code 8K 0x000C0000 0x00000000 0x00080000 Flash & EEPROM Registers 0x01000000 Peripherals FLASH Applications Code (256KB) Figure 5: JN5168 Memory Map 4.1 FLASH The embedded Flash consists of 2 parts: an 8K region used for holding boot code, and a 256K region (JN5168) used for application code. The sector size of the application code is always 32K, for any size of Flash memory. The maximum number of write cycles or endurance is, 10k guaranteed and typically 100k, while the data retention is guaranteed for at least 10 years. The boot code region is pre-programmed by NXP on supplied parts, and contains code to handle reset, interrupts and other events (see section 7). It also contains a Flash Programming Interface to allow interaction with the PC-based Flash Programming Utility which allows user code compiled using the supplied SDK to be programmed into the Application space. For further information, refer to the Flash Programmer User Guide.[9]. The memory can be erased by a single or multiple sectors and written to in units of 256 bytes, known as pagewords. 4.2 RAM The JN516x devices contain up to 32Kbytes of high speed RAM, which can be accessed by the CPU in a single clock cycle. It is primarily used to hold the CPU Stack together with program variables and data. If necessary, the CPU can execute code contained within the RAM (although it would normally just execute code directly from the embedded Flash). Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered, allowing a quicker resumption of processing once woken. 4.3 OTP Configuration Memory The JN516x devices contain a quantity of One Time Programmable (OTP) memory as part of the embedded Flash (Index Sector). This can be used to securely hold such things as a user 64-bit MAC address and a 128-bit AES security key. By default the 64-bit MAC address is pre-programmed by NXP on supplied parts; however customers © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 17 can use their own MAC address and override the default one. The user MAC address and other data can be written to the OTP memory using the Flash programmer [9]. Details on how to obtain and install MAC addresses can be found in the Flash Programmer User Guide. In addition 384bits are available, organised as three 128bit words, for customer use for storage of configuration or other information. 4.4 EEPROM The JN516x devices contain 4Kbytes of EEPROM. The maximum number of write cycles or endurance is, 100k guaranteed and 1M typically while the data retention is guaranteed for at least 20 years. (The Persistent Data Manager, includes a wear-levelling algorithm which can help to extend the endurance.) This non-volatile memory is primarily used to hold persistent data generated from such things as the Network Stack software component (e.g. network topology, routing tables). As the EEPROM holds its contents through sleep and reset events, this means more stable operation and faster recovery is possible after outages. Access to the EEPROM is via registers mapped into the Flash and EEPROM Registers region of the address map. The memory can be erased by a single or multiple pages of 64 bytes. It can be written to in single or multiple bytes up to 64 bytes. The customer may use part of the EEPROM to store its own data if desired by interfacing with the Persistent Data Manager. Optionally the PDM can also store data in an external memory. For further information, please read - JenOS User Guide [12]. 4.5 External Memory An optional external serial non-volatile memory (eg Flash or EEPROM) with a SPI interface may be used to provide additional storage for program code, such as a new code image or further data for the device when external power is removed. The memory can be connected to the SPI Master interface using select line SPISEL0 (see fig 6 for details) JN516x Serial Memory SPISEL0 SPIMISO SPIMOSI SPICLK SS SDO SDI CLK Figure 6: Connecting External Serial Memory The contents of the external serial memory may be encrypted. The AES security processor combined with a user programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is stored in the flash memory index section. When bootloading program code from external serial memory, the JN516x automatically accesses the encryption key to execute the decryption process, user program code does not need to handle any of the decryption process; it is transparent. For more details, including the how the program code encrypts data for the external memory, see the application note Boot Loader Operation. [8] 4.6 Peripherals All peripherals have their registers mapped into the memory space. Access to these registers requires 3 peripheral clock cycles. Applications have access to the peripherals through the software libraries that present a high-level view of the peripheral’s functions through a series of dedicated software routines. These routines provide both a tested method for using the peripherals and allow bug-free application code to be developed more rapidly. For details, see Peripherals API User Guide [4]. 4.7 Unused Memory Addresses Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated.18 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 5 System Clocks Two system clocks are used to drive the on-chip subsystems of the JN516x. The wake-up timers are driven from a low frequency clock (notionally 32kHz). All other subsystems (transceiver, processor, memory and digital and analogue peripherals) are driven by a high-speed clock (notionally 32MHz), or a divided-down version of it. The high-speed clock is either generated by the accurate crystal-controlled oscillator (32MHz) or the less accurate high-speed RC oscillator ( 27-32MHz calibrated). The low-speed clock is either generated by the accurate crystalcontrolled oscillator (32.768kHz), the less accurate RC oscillator (centered on 32kHz) or can be supplied externally 5.1 High-Speed (32MHz) System Clock The selected high-speed system clock is used directly by the radio subsystem, whereas a divided-by-two version is used by the remainder of the transceiver and the digital and analogue peripherals. The direct or divided down version of the clock is used to drive the processor and memories (32, 16, 8, 4, 2 or 1MHz). High Speed RC Oscillator 32MHz Crystal Oscillator Div by 1,2,4,8,16 or 32 Div by 2 PERIPHERAL SYSTEM CLOCK CPU CLOCK Figure 7 System and CPU Clocks Crystal oscillators are generally slow to start. Hence to provide a fast start-up following a sleep cycle or reset, the fast RC oscillator is always used as the initial source for the high-speed system clock. The oscillator starts very quickly and will run at 25-32MHz (uncalibrated) or 32MHz +/-5% (calibrated). Although this means that the system clock will be running at an undefined frequency (slightly slower or faster than nominal), this does not prevent the CPU and Memory subsystems operating normally, so the program code can execute. However, it is not possible to use the radio or UARTs, as even after calibration (initiated by the user software calling an API function) there is still a +/-5% tolerance in the clock rate over voltage and temperature. Other digital peripherals can be used (eg SPI Master/Slave), but care must be taken if using Timers due to the clock frequency inaccuracy. Further details of the High-Speed RC Oscillator can be found in section 19.3.11. On wake-up from sleep, the JN516x uses the Fast RC oscillator. It can then either: • Automatically switch over to use the 32MHz clock source when it has started up. • Continue to use the fast RC oscillator until software triggers the switch-over to the 32MHz clock source, for example when the radio is required. • Continue to use the RC oscillator until the device goes back into one of the sleep modes. The use of the fast RC Oscillator at wake-up means there is no need to wait for the 32MHz crystal oscillator to stabilise Consequently, the application code will start executing quickly using the clock from the high-speed RC oscillator. 5.1.1 32MHz Crystal Oscillator The JN516x contains the necessary on chip components to build a 32MHz reference oscillator with the addition of an external crystal resonator and two tuning capacitors. The schematic of these components are shown in Figure 8. The two capacitors, C1 and C2, should typically be 15pF and use a COG dielectric. Due to the small size of these capacitors, it is important to keep the traces to the external components as short as possible. The on chip transconductance amplifier is compensated for temperature variation, and is self-biasing by means of the internal resistor R1. This oscillator provides the frequency reference for the radio and therefore it is essential that the reference PCB layout and BOM are carefully followed. The electrical specification of the oscillator can be found in © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 19 Section 19.3.11. Please refer to Appendix B for development support with the crystal oscillator circuit. The oscillator includes a function which flags when the amplitude of oscillation has reached a satisfactory level for full operation, and this is checked before the source of the high-speed system clock is changed to the 32MHz crystal oscillator XTALOUT C1 C2 XTALIN R1 JN516x Figure 8: 32MHz Crystal Oscillator Connections For operation over the extended temperature range, 85 to 125 deg C, special care is required; this is because the temperature characteristics of crystal resonators are generally in excess of +/-40ppm frequency tolerance defined by the IEEE802.15.4 standard. The oscillator cell contains additional circuitry to compensate for the poor performance of the crystal resonators above 100 deg C. Full details, including the software API function, can be found in the application note JN516x Temperature-dependent Operating Guidelines [2] 5.1.2 High-Speed RC Oscillator An on-chip High-Speed RC oscillator is provided in addition to the 32MHz crystal oscillator for two purposes, to allow a fast start-up from reset or sleep and to provide a lower current alternative to the crystal oscillator for non-timing critical applications. By default the oscillator will run at 27MHz typically with a wide tolerance. It can be calibrated, using a software API function, which will result in a nominal frequency of 32MHz with a +/-1.6% tolerance at 3v and 25 deg C. However, it should be noted that over the full operating range of voltage and temperature this will increase to +/-5%. The calibration information is retained through speed cycles and when the oscillator is disabled, so typically the calibration function only needs to be called once. No external components are required for this oscillator. The electrical specification of the oscillator can be found in Section 19.3.12. 5.2 Low-speed (32kHz) System Clock The 32kHz system clock is used for timing the length of a sleep period (see Section 18). The clock can be selected from one of three sources through the application software: • 32kHz RC Oscillator • 32kHz Crystal Oscillator • 32kHz External Clock Upon a chip reset or power-up the JN516x defaults to using the internal 32kHz RC Oscillator. If another clock source is selected then it will remain in use for all 32kHz timing until a chip reset is performed. 5.2.1 32kHz RC Oscillator The internal 32kHz RC oscillator requires no external components. The internal timing components of the oscillator have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz -10% /+40%. To make this useful as a timing source for accurate wakeup from sleep, a frequency calibration factor derived from the more accurate 16MHz clock may be applied. The calibration factor is derived through software, details can be found in Section 11.3.1. Software must check that the 32kHz RC oscillator is running before using it. The oscillator has a default current consumption of around 0.5uA, optionally this can be reduced to 0.375uA, however, the 20 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 calibrated accuracy and temperature coefficient will be worse as a consequence. For detailed electrical specifications, see Section 19.3.9. 5.2.2 32kHz Crystal Oscillator In order to obtain more accurate sleep periods, the JN516x contains the necessary on-chip components to build a 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between 32KXTALIN and 32KXTALOUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. Due to the small size of the capacitors, it is important to keep the traces to the external components as short as possible. The electrical specification of the oscillator can be found in Section 19.3.10. The oscillator cell is flexible and can operate with a range of commonly available 32.768kHz crystals with load capacitances from 6 to 12.5pF. However, the maximum ESR of the crystal and the supply current are both functions of the actual crystal used, see Appendix B.1 for more details. 32KXTALIN 32KXTALOUT JN516x Figure 9: 32kHz Crystal Oscillator Connections 5.2.3 32kHz External Clock An externally supplied 32kHz reference clock on the 32KXTALIN input (DIO9) may be provided to the JN516x. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate sleep cycle timings compared to the internal RC oscillator. (See Section 19.2.3)© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 21 6 Reset A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN516x goes through is as follows. When power is first applied or when the external reset is released, the High-Speed RC oscillator and 32MHz crystal oscillator are activated. After a short wait period (13µsec approx) while the High-Speed RC starts up, and so long as the supply voltage satisfies the default Supply Voltage Monitor (SVM) threshold (2.0V+0.045V hysteresis), the internal 1.8V regulators are turned on to power the processor and peripheral logic. The regulators are allowed to stabilise (about 15us) followed by a further wait (150usec approx) to allow the Flash and EEPROM bandgaps to stabilise and allow their initialisation, including reading the user SVM threshold from the Flash. This is applied to the SVM and, after a brief pause (approx 2.5usec), the SVM is checked again. If the supply is above the new SVM threshold, the CPU and peripheral logic is released from reset and the CPU starts to run code beginning at the reset vector. This runs the bootloader code contained within the flash, which looks for a valid application to run, first from the internal flash and then from any connected external serial memory over the SPI Master interface. Once found, required variables are initialised in RAM before the application is called at its AppColdStart entry point. More details on the bootloader can be found in the application note - Boot Loader Operation. [8] The JN516x has five sources of reset: • Internal Power-on / Brown-out Reset (BOR) • External Reset • Software Reset • Watchdog timer • Supply Voltage detect Note: When the device exits a reset condition, device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, then the device must be held in reset until the operating conditions are met. (See Section 19.3) 6.1 Internal Power-On / Brown-out Reset (BOR) For the majority of applications the internal power-on reset is capable of generating the required reset signal. When power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD reaches the specified threshold, the reset signal is generated. This signal is held internally until the power supply and oscillator stabilisation time has elapsed, when the internal reset signal is then removed and the CPU is allowed to run. The BOR circuit has the ability to reject spikes on the VDD rail to avoid false triggering of the reset module. Typically for a negative going square pulse of duration 1uS, the voltage must fall to 1.2v before a reset is generated. Similarly for a triangular wave pulse of 10us width, the voltage must fall to 1.3v before causing a reset. The exact characteristics are complex and these are only examples. Internal RESET VDD Figure 10: Internal Power-on Reset When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. If necessary, use of the external reset circuit show in Figure 11 is suggested. 22 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 RESETN C1 R1 JN516x VDD 18k 470nF Figure 11: External Reset Generation The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin but are not neccessary. 6.2 External Reset An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The JN516x is held in reset while the RESETN pin is low. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the internal reset process starts. The JN516x has an internal 500kΩ pull-up resistor connect to the RESETN pin. The pin is an input for an external reset only. By holding the RESETN pin low, the JN516x is held in reset, resulting in a typical current of 6uA. Internal Reset RESETN pin Reset Figure 12: External Reset 6.3 Software Reset A system reset can be triggered at any time through software control, causing a full chip reset and invalidating the RAM contents. For example this can be executed within a user’s application upon detection of a system failure. 6.4 Supply Voltage Monitor (SVM) An internal Supply Voltage Monitor (SVM) is used to monitor the supply voltage to the JN516x; this can be used whilst the device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN516x to perform a chip reset. Equally, dips in the supply voltage can be © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 23 detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it. The supply voltage detect is enabled by default from power-up and can extend the reset during power-up. This will keep the CPU in reset until the voltage exceeds the SVM threshold voltage. The threshold voltage is configurable to 1.95V, 2.0V, 2.1V, 2.2V, 2.3V, 2.4V, 2.7V and 3.0V and is controllable by software. From power-up the threshold is set by a setting within the flash and the default chip configuration is for the 2.0V threshold. It is expected that the threshold is set to the minimum needed by the system.. 6.5 Watchdog Timer A watchdog timer is provided to guard against software lockups. It operates by counting cycles of the high-speed RC system clock. A pre-scaler is provided to allow the expiry period to be set between typically 8ms and 16.4 seconds (dependent on high-speed RC accuracy: +30%, -15%). Failure to restart the watchdog timer within the pre-configured timer period will cause a chip reset to be performed. A status bit is set if the watchdog was triggered so that the software can differentiate watchdog initiated resets from other resets, and can perform any required recovery once it restarts. Optionally, the watchdog can cause an exception rather than a reset, this preserves the state of the memory and is useful for debugging. After power up, reset, start from deep sleep or start from sleep, the watchdog is always enabled with the largest timeout period and will commence counting as if it had just been restarted. Under software control the watchdog can be disabled. If it is enabled, the user must regularly restart the watchdog timer to stop it from expiring and causing a reset. The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if enabled once the debugger un-stalls the CPU. 24 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 7 Interrupt System The interrupt system on the JN516x is a hardware-vectored interrupt system. The JN516x provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor mode. Interrupt sources and their vector locations are listed in Table 1 below: Interrupt Source Vector Location Interrupt Definition Bus error 0x08 Typically cause by an attempt to access an invalid address or a disabled peripheral Tick timer 0x0e Tick timer interrupt asserted Alignment error 0x14 Load/store address to non-naturally-aligned location Illegal instruction 0x1a Attempt to execute an unrecognised instruction Hardware interrupt 0x20 interrupt asserted System call 0x26 System call initiated by b.sys instruction Trap 0x2c caused by the b.trap instruction or the debug unit Reset 0x38 Caused by software or hardware reset. Stack Overflow 0x3e Stack overflow Table 1: Interrupt Vectors 7.1 System Calls The b.trap and b.sys instructions allow processor exceptions to be generated by software. A system call exception will be generated when the b.sys instruction is executed. This exception can, for example, be used to enable a task to switch the processor into supervisor mode when a real time operating system is in use. (See Section 3 for further details.) The b.trap instruction is commonly used for trapping errors and for debugging. 7.2 Processor Exceptions 7.2.1 Bus Error A bus error exception is generated when software attempts to access a memory address that does not exist, or is not populated with memory or peripheral registers. 7.2.2 Alignment Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are 0xFFF0, 0xFFF4, 0xFFF8 etc. 7.2.3 Illegal Instruction If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal instruction exception. 7.2.4 Stack Overflow When enabled, a stack overflow exception occurs if the stack pointer reaches a programmable location.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 25 7.3 Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the Peripherals API User Guide [4]. For details of the interrupts generated from each peripheral see the respective section in this datasheet. Interrupts can be used to wake the JN516x from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and analogue comparator interrupts remain powered to bring the JN516x out of sleep. Prioritised external interrupt handling (i.e., interrupts from hardware peripherals) is provided to enable an application to control an events priority to provide for deterministic program execution. The priority Interrupt controller provides 15 levels of prioritised interrupts. The priority level of all interrupts can be set, with value 0 being used to indicate that the source can never produce an external interrupt, 1 for the lowest priority source(s) and 15 for the highest priority source(s). Note that multiple interrupt sources can be assigned the same priority level if desired. If while processing an interrupt, a new event occurs at the same or lower priority level, a new external interrupt will not be triggered. However, if a new higher priority event occurs, the external interrupt will again be asserted, interrupting the current interrupt service routine. Once the interrupt service routine is complete, lower priority events can be serviced. 26 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 8 Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standardsbased wireless transceiver that transmits and receives data over the air in the unlicensed 2.4GHz band. 8.1 Radio Figure 13 shows the single ended radio architecture. LNA synth PA ADC Reference & Bias Switch Radio Calibration Lim1 Lim2 Lim3 Lim4 sigma delta D-Type Figure 13: Radio Architecture The radio comprises a low-IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matching network, which consists of two inductors and a capacitor, this arrangement creates a 50Ω port and removes the need for a balun. A 50Ω single ended antenna can be connected directly to this port. The 32MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop characteristic. The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a digital signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. To improve the performance and reduce current consumption, automatic calibration is applied to various blocks in the RX path. In the transmit direction, the digital stream from the Modem is passed to a digital sigma-delta modulator which controls the feedback dividers in the synthesiser, (dual point modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 27 The JN516x radio when enabled is automatically calibrated for optimum performance. In operating environments with a significant variation in temperature (e.g. greater than 20 deg C) due to diurnal or ambient temperature variation, it is recommended to recalibrate the radio to maintain performance. Recalibration is only required on Routers and End Devices that never sleep. End Devices that sleep when idle are automatically recalibrated when they wake. An Application Note JN516x Temperature-dependent Operating Guidelines [2] describes this in detail and includes a software API function which can be used to test the temperature using the on-chip temperature sensor and trigger a recalibration if there has been a significant temperature change since the previous calibration. 8.1.1 Radio External Components In order to realise the full performance of the radio it is essential that the reference PCB layout and BOM are carefully followed. See Appendix B.4. The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to provide good noise isolation between the digital logic of the JN516x and the analogue blocks. These regulators are also controlled by the baseband controller and protocol software to minimise power consumption. Decoupling for internal regulators is required as described in Section 2.2.1. For single ended antennas or connectors, a balun is not required, however a matching network is needed. The RF matching network requires three external components and the IBIAS pin requires one external component as shown in schematic in B.4.1. These components are critical and should be placed close to the JN516x pins and analogue ground as defined in Table 12. Specifically, the output of the network comprising L2, C1 and L1 is designed to present an accurate match to a 50 ohm resistive network as well as provide a DC path to the final output stage or antenna. Users wishing to match to other active devices such as amplifiers should design their networks to match to 50 ohms at the output of L1 R1 43K IBIAS C20 100nF L2 3.9nH VB_RF VREF VB_RF2 RF_IN C3 100nF C12 47pF VB_RF1 C1 47pF L1 5.1nH To Coaxial Socket or Integrated Antenna VB_RF Figure 14: External Radio Components 8.1.2 Antenna Diversity Support is provided for antenna diversity. Antenna diversity is a technique that maximises the performance of an antenna system. It allows the radio to switch between two antennas that have very low correlation between their received signals. Typically, this is achieved by spacing two antennae around 0.25 wavelengths apart or by using two orthogonal polarisations. So, if a packet is transmitted and no acknowledgement is received, the radio system can switch to the other antenna for the retry, with a different probability of success.28 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Additionally antenna diversity can be enabled whilst in receive mode waiting for a packet. The JN516x measures the received energy in the relevant radio channel every 40μs and the measured energy level is compared with a pre-set energy threshold, which can be set by the application program. The JN516x device will automatically switch the antennae if the measurement is below this threshold, except if waiting for an acknowledgement from a previous transmission or if the process of receiving a packet, when it will wait until this has finished. Also, it will not switch if a preamble symbol having a signal quality above a minimum specified threshold has not been detected in the last 40μs Both modes can be used at once and use the same ADO and ADE outputs to control the switch. The JN516x provides an output (ADO) on DIO12 that is asserted on odd numbered retries and optionally its complement (ADE) on DIO13, that can be used to control an antenna switch; this enables antenna diversity to be implemented easily (see Figure 15 and Figure 16). Antenna A Antenna B A B COM SEL SELB ADO (DIO[12]) ADE (DIO[13]) Device RF Port RF Switch: Single-Pole, Double-Throw (SPDT) Figure 15: Simple Antenna Diversity Implementation using External RF Switch ADO (DIO[12]) TX Active RX Active ADE (DIO[13]) 1st TX-RX Cycle 2nd TX-RX Cycle (1st Retry) Figure 16: Antenna Diversity ADO Signal for TX with Acknowledgement If two DIO pins cannot be spared, DIO13 can be configured to be a normal DIO pin, and the inverse of ADO generated with an inverter on the PCB. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 29 8.2 Modem The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard. AGC Demodulation Symbol Detection (Despreading) Modulation Spreading TX RX TX Data Interface RX Data Interface VCO Sigma-Delta Modulator IF Signal Gain Figure 17: Modem Architecture Features provided to support network channel selection algorithms include Energy Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel Assessment (CCA). The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the IEEE 802.15.4 ED function and LQI function. The ED and LQI are both related to receiver power in the same way, as shown in Figure 18. LQI is associated with a received packet, whereas ED is an indication of signal power on air at a particular moment. The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold. Figure 18: Energy Detect Value vs Receive Power Level30 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 8.3 Baseband Processor The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to implement the sequencing of events required by the protocol and to schedule timed events with millisecond resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software layer performs the higher-layer aspects of the protocol, sending management and data messages between endpoint and coordinator nodes, using the services provided by the baseband processor. Supervisor Append Checksum Serialiser DMA Engine TX Stream Radio Protocol Timing Engine CSMA CCA Backoff Control Control RX Stream Verify Checksum Deserialiser Protocol Timers Security Coprocessor AES Codec Encrypt Port Decrypt Port Status Processor Bus Figure 19: Baseband Processor 8.3.1 Transmit A transmission is performed by software writing the data to be transferred into the Tx Frame Buffer in RAM, together with parameters such as the destination address and the number of retries allowed, and programming one of the protocol timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor controls the sequencing of the radio and modem to perform the type of transmission required, fetching the packet data directly from RAM. It can perform all the algorithms required by IEEE802.15.4 such as CSMA/CA without processor intervention including retries and random backoffs. When the transmission begins, the header of the frame is constructed from the parameters programmed by the software and sent with the frame data through the serialiser to the Modem. At the same time, the radio is prepared for transmission. During the passage of the bitstream to the modem, it passes through a CRC checksum generator that calculates the checksum on-the-fly, and appends it to the end of the frame. 8.3.2 Reception During reception, the radio is set to receive on a particular channel. On receipt of data from the modem, the frame is directed into the Rx Frame Buffer in RAM where both header and frame data can be read by the protocol software. An interrupt may be provided on receipt of the frame header. As the frame data is being received from the modem it is passed through a checksum generator; at the end of the reception the checksum result is compared with the checksum at the end of the message to ensure that the data has been received correctly. An interrupt may be provided to indicate successful packet reception. During reception, the modem determines the Link Quality, which is made available at the end of the reception as part of the requirements of IEEE802.15.4.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 31 8.3.3 Auto Acknowledge Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The JN516x baseband processor can automatically construct and send the acknowledgement packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence. The JN516x baseband processor can also request an acknowledge for packets being transmitted and handle the reception of acknowledged packets without processor intervention. 8.3.4 Beacon Generation In beaconing networks, the baseband processor can automatically generate and send beacon frames; the repetition rate of the beacons is programmed by the CPU, and the baseband then constructs the beacon contents from data delivered by the CPU. The baseband processor schedules the beacons and transmits them without CPU intervention. 8.3.5 Security The transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm is handled by the security coprocessor and the stack software. The application software must provide the appropriate encrypt/decrypt keys for the transmission or reception. On transmission, the key can be programmed at the same time as the rest of the frame data and setup information. 8.4 Security Coprocessor The security coprocessor is available to the application software to perform encryption/decryption operations. A hardware implementation of the encryption engine significantly speeds up the processing of the encrypted packets over a pure software implementation. The AES library for the JN516x provides operations that utilise the encryption engine in the device and allow the contents of memory buffers to be transformed. Information such as the type of security operation to be performed and the encrypt/decrypt key to be used must also be provided. Processor Interface AES Block Encryption Controller AES Encoder Key Generation Figure 20: Security Coprocessor Architecture 8.5 Time of Flight Engine The JN516x family includes unique hardware functions to enable measurement of the distance between two nodes using a “Time of Flight” (ToF) function. This function uses dedicated timers and interpolation of the timing of correlation peaks in the demodulator to measure the delays introduced by the time taken for the radio signals to travel between nodes. It is also possible to use the received signal strength (RSSI) to indicate the distance. Due to the characteristics of the transmitted signal and the baseband circuitry, ToF offers a significant improvement in accuracy for distance measurements above 10m compared with RSSI, while RSSI provides better ranging results below 10m. Hence, ToF is best suited to long range distance measurement. The raw timing results are made available through an API function, but the responsibility for converting these into location information lies with the user. For more information, see the Time-of-flight API User Guide [10]32 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 9 Digital Input/Output There are 20 Digital I/O (DIO) pins which when used as general-purpose pins can be configured as either an input or an output, with each having a selectable internal pull-up resistor. In addition, there are 2 Digital Output (DO) pins. Most DIO pins are shared with the digital and analogue peripherals of the device. When a peripheral is enabled, it takes control over the device pins allocated to it. However, note that most peripherals have 2 alternative pin allocations to alleviate clashes between uses, and many peripherals can disable the use of specific pins if not required. Refer to Section 2.1 and the individual peripheral descriptions for full details of the available pinout arrangements. Following a reset (and whilst the RESETN input is held low), all peripherals are forced off and the DIO pins are configured as inputs with the internal pull-ups turned on.When a peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or outputs. Each pin can be controlled individually by setting the direction and then reading or writing to the pin. The individual pull-up resistors, RPU, can also be enabled or disabled as needed and the setting is held through sleep cycles. The pull-ups are generally configured once after reset depending on the external components and functionality. For instance, outputs should generally have the pull-ups disabled. An input that is always driven should also have the pull-up disabled. When configured as an input each pin can be used to generate an interrupt upon a change of state (selectable transition either from low to high or high to low); the interrupt can be enabled or disabled. When the device is sleeping, these interrupts become events that can be used to wake the device up. Equally the status of the interrupt may be read. See Section 18 for further details on sleep and wakeup. The state of all DIO pins can be read, irrespective of whether the DIO is configured as an input or an output. Throughout a sleep cycle the direction of the DIO, and the state of the outputs, is held. This is based on the resultant of the GPIO Data/Direction registers and the effect of any enabled peripherals at the point of entering sleep. Following a wake-up these directions and output values are maintained under control of the GPIO data/direction registers. Any peripherals enabled before the sleep cycle are not automatically re-enabled, this must be done through software after the wake-up. For example, if DIO0 is configured to be SPISEL1 then it becomes an output. The output value is controlled by the SPI functional block. If the device then enters a sleep cycle, the DIO will remain an output and hold the value being output when entering sleep. After wake-up the DIO will still be an output with the same value but controlled from the GPIO Data/Direction registers. It can be altered with the software functions that adjust the DIO, or the application may re-configure it to be SPISEL1. Unused DIO pins are recommended to be set as inputs with the pull-up enabled. Two DIO pins can optionally be used to provide control signals for RF circuitry (e.g. switches and PA) in high power range extenders. DIO3/RFTX is asserted when the radio is in the transmit state and similarly, DIO2/RFRX is asserted when the radio is in the receiver state.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 33 MUX SPI Slave DIO0/SPISEL1/ADC3 DIO1/SPISEL2/ADC4/PC0 DIO2/RFRX/TIM0CK_GT DIO3/RFTX/TIM0CAP DIO4/CTS0/TIM0OUT/PC0 DIO5/RTS0/PWM1/PC1 DIO6/TXD0/PWM2 DIO7/RXD0/PWM3 DIO8/TIM0CK_GT/PC1/PWM4 DIO9/TIM0CAP/32KXTALIN/RXD1/32KIN DIO10/TIM0OUT/32KXTALOUT DIO11/PWM1/TXD1 DIO12/PWM2/CTS0/ADO/SPISMOSI DIO13/PWM3/RTS0/ADE/SPISMISO DIO14/SIF_CLK/TXD0/TXD1/SPISEL1/SPISSEL DIO15/SIF_D/RXD0/RXD1/SPISEL2/SPISCLK DIO16/COMP1P/SIF_CLK/SPISMOSI DIO17/COMP1M/SIF_D/SPISMISO DIO18/SPIMOSI DIO19/SPISEL0 DO0/SPICLK/PWM2 DO1/SPIMISO/PWM3 TXD0 SPI Master UART0 UART1 RXD0 RTS0 CTS0 TxD1 RxD1 TIM0CK_GT TIM0OUT TIM0CAP PWM1 PWM2 PWM3 PWM4 SIF_D SIF_CLK PC0 PC1 JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO ADO ADE Timer0 PWMs 2-wire Interface Pulse Counters JTAG Debug Antenna Diversity SPICLK SPIMOSI SPIMISO SPISEL0 SPICLK SPIMOSI SPIMISO SPISEL0 SPISEL1 SPISEL2 Figure 21 DIO Block Diagram34 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 10 Serial Peripheral Interface 10.1 Serial Peripheral Interface Master The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN516x and peripheral devices. The JN516x operates as a master on the SPI bus and all other devices connected to the SPI are expected to be slave devices under the control of the JN516x CPU. The SPI includes the following features: • Full-duplex, three-wire synchronous data transfer • Programmable bit rates (up to 16Mbit/s) • Programmable transaction size up to 32-bits • Standard SPI modes 0,1,2 and 3 • Manual or Automatic slave select generation (up to 3 slaves) • Maskable transaction complete interrupt • LSB First or MSB First Data Transfer • Supports delayed read edges Clock Divider SPI Bus Cycle Controller Data Buffer DIV Clock Edge Select Data CHAR_LEN LSB SPIMISO SPIMOSI SPICLK Select Latch SPISEL [2..0] 16 MHz Figure 22: SPI Master Block Diagram The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously. Master-Out-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN516x. The JN516x provides three slave selects, SPISEL0 to SPISEL2 to allow three SPI peripherals on the bus. SPISEL0 is accessed on DI019. SPISEL1 is accessed, depending upon the configuration, on DIO0 or DIO14. SPISEL2 is accessed on DIO1 or DIO15. This is enabled under software control. The following table details which DIO are used for the SPISEL signals depending upon the configuration. Signal DIO Assignment Standard pins Alternative pins SPISEL1 DIO0 DIO14 SPISEL2 DIO1 DIO15 SPICLK DO0 SPIMISO DO1 SPIMOSI DIO18 SPISEL0 DIO19 Table 2: SPI Master IO© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 35 The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted between transfers when required, to enable longer transfers to be performed. When the device reset is active, all the SPI Master pins are configured as inputs with their pull-up resistors active. The pins stay in this state until the SPI Master block is enabled, or the pins are configured for some other use. SS Slave 0 Flash/ EEPROM Memory JN5142 SPISE L0 SPISE L1 SPIMOSI SPICLK SPIMISO SS Slave 1 User Defined SS Slave 2 User Defined SPISE L2 SI C SO SI C SO SI C SO JN516X Figure 23: Typical JN516x SPI Peripheral Connection The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN516x supports transfers at selectable data rates from 16MHz to 125kHz selected by a clock divider. Both SPICLK clock phase and polarity are configurable. The clock phase determines which edge of SPICLK is used by the JN516x to present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The interface should be configured appropriately for the SPI slave being accessed. SPICLK Polarity Mode Description (CPOL) Phase (CPHA) 0 0 0 SPICLK is low when idle – the first edge is positive. Valid data is output on SPIMOSI before the first clock and changes every negative edge. SPIMISO is sampled every positive edge. 0 1 1 SPICLK is low when idle – the first edge is positive. Valid data is output on SPIMOSI every positive edge. SPIMISO is sampled every negative edge. 1 0 2 SPICLK is high when idle – the first edge is negative. Valid data is output on SPIMOSI before the first clock edge and is changed every positive edge. SPIMISO is sampled every negative edge. 1 1 3 SPICLK is high when idle – the first edge is negative. Valid data is output on SPIMOSI every negative edge. SPIMISO is sampled every positive edge. Table 3: SPI Configurations36 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 If more than one SPISEL line is to be used in a system they must be used in numerical order starting from SPISEL0. A SPISEL line can be automatically de-asserted between transactions if required, or it may stay asserted over a number of transactions. For devices such as memories where a large amount of data can be received by the master by continually providing SPICLK transitions, the ability for the select line to stay asserted is an advantage since it keeps the slave enabled over the whole of the transfer. A transaction commences with the SPI bus being set to the correct configuration, and then the slave device is selected. Upon commencement of transmission (1 to 32 bits) data is placed in the FIFO data buffer and clocked out, at the same time generating the corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of data bits is being received from the slave as it transmits. The data that is received during this transmission can be read (1 to 32 bits). If the master simply needs to provide a number of SPICLK transitions to allow data to be sent from a slave, it should perform transmit using dummy data. An interrupt can be generated when the transaction has completed or alternatively the interface can be polled. If a slave device wishes to signal the JN516x indicating that it has data to provide, it may be connected to one of the DIO pins that can be enabled as an interrupt. Figure 24 shows a complex SPI transfer, reading data from a FLASH device that can be achieved using the SPI master interface. The slave select line must stay low for many separate SPI accesses, and therefore manual slave select mode must be used. The required slave select can then be asserted (active low) at the start of the transfer. A sequence 8 and 32 bit transfers can be used to issue the command and address to the FLASH device and then to read data back. Finally, the slave select can be deselected to end the transaction. 0 1 2 3 4 5 6 7 Instruction (0x03) 23 22 21 3 2 1 0 8 9 10 28 29 30 31 24-bit Address MSB Instruction Transaction 7 6 5 4 3 2 1 0 MSB 0 1 2 3 4 5 7 8N-1 3 2 1 0 LSB Read Data Bytes Transaction(s) 1-N SPISEL SPICLK SPIMOSI SPIMISO SPISEL SPICLK SPIMOSI SPIMISO 8 9 10 7 6 5 MSB Byte 1 Byte 2 Byte N value unused by peripherals 6 Figure 24: Example SPI Waveforms – Reading from FLASH Device using Mode 0© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 37 10.2 Serial Peripheral Interface Slave The Serial Peripheral Interface (SPI) Slave Interface allows high-speed synchronous data transfer between the JN516x and a peripheral device. The JN516x operates as a slave on the SPI bus and an external device connected to the SPI bus operates as the master. The pins are different from the SPI master interface and are shown in the following table. Signal DIO Assignment Standard pins Alternative pins SPISCLK DIO15 SPISMISO DIO13 DIO17 SPISMOSI DIO12 DIO16 SPISSEL DIO14 Table 4: SPI Slave IO The SPI bus employs a simple shift register data transfer scheme, with SPISSEL acting as the active low select control. Data is clocked out of and into the active devices in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously. Master-Out-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPISCLK generated by the external master. The SPI slave includes the following features: • Full-duplex synchronous data transfer • Slaves to external clock up to 8MHz • Supports 8 bit transfers (MSB or LSB first configurable), with SPISSEL deselected between each transfer • Internal FIFO up to 255 bytes for transmit and receive • Standard SPI mode 0, data is sampled on positive clock edge • Maskable interrupts for receive FIFO not empty, transmit FIFO empty, receive FIFO fill level above threshold, transmit FIFO fill level below threshold, transmit FIFO overflow, receive FIFO overflow, receive FIFO underflow, transmit FIFO underflow, receive timeout • Programmable receive timeout period allows an interrupt to be generated to prompt the receive FIFO to be read if no further data arrives within the timeout period38 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 11 Timers 11.1 Peripheral Timer/Counters A general-purpose timer/counter unit, Timer0, is available that can be configured to operate in one of five possible modes. This has: • Clocked from internal system clock (16MHz) • 5-bit prescaler, divides system clock by 2 prescale value as the clock to the timer (prescaler range is 0 to 16) • 16-bit counter, 16-bit Rise and Fall (period) registers • Timer: can generate interrupts off Rise and Fall counts. Can be gated by external signal • Counter: counts number of transitions on external event signal. Can use low-high, high-low or both transitions • PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse. Can set period and mark-space ratio • Capture: measures times between transitions of an applied signal • Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes • Timer usage of external IO can be controlled on a pin by pin basis Four further timers are also available that support the same functionality but have no Counter or Capture mode. These are referred to as PWM timers. Additionally, is not possible to gate these four timers with an external signal. >= D Q Rise = < Fall Delta Sigma Interrupt Generator Counter Interrupt Enable Capture Generator Prescaler SYSCLK TIMxCK_GT TIMxCAP Interrupt PWM/∆Σ PWM/∆Σ PWM/∆Σ Reset Generator Edge Select EN EN TIMxOut Sw Reset System Reset Single Shot -1 Figure 25: Timer Unit Block Diagram© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 39 The clock source for the Timer0 unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler where a value of 0 leaves the clock unmodified and other values divide it by 2 prescale value. For example, a prescale value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz. The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the gate function is selected, then the counter is frozen when the clock/gate input is high. An interrupt can be generated whenever the counter is equal to the value in either of the High or Low registers. The following table details which DIO are used for timer0 and the PWM depending upon the configuration. Signal DIO Assignment Standard pins Alternative pins TIM0CK_GT DIO8 DIO2 TIM0CAP DIO9 DIO3 TIM0OUT DIO10 DIO4 PWM1 DIO11 DIO5 PWM2 DIO12 DIO6 PWM3 DIO13 DIO7 PWM4 DIO17 DIO8 Table 5: Timer and PWM IO The alternative pin locations can be configured separately for each counter/timer under software control, without affecting the operation or location of the others If operating in timer mode, it is not necessary to use any of the DIO pins, allowing the standard DIO functionality to be available to the application. 11.1.1 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode, as used by PWM timers 1,2 3 and 4 and optionally by Timer0, allows the user to specify an overall cycle time and pulse length within the cycle. The pulse can be generated either as a single shot or as a train of pulses with a repetition rate determined by the cycle time. In this mode, the cycle time and low periods of the PWM output signal can be set by the values of two independent 16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset and the cycle repeats. If either the cycle time or low periods are changed while in continuous mode, the new values are not used until a full cycle has completed. The PWM waveform is available on PWM1,2,3,4 or TIM0OUT when the output driver is enabled. Rise Fall Figure 26 PWM Output Timings 11.1.2 Capture Mode The capture mode can be used to measure the time between transitions of a signal applied to the capture input (TIM0CAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register. The pulse width is the difference in counts in the two registers multiplied by the period of the prescaled clock. Upon reading the capture registers the counter is stopped. The values in the High and Low registers will be updated whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the mode was started. Therefore, if multiple pulses are seen on TIM0CAP before the counter is stopped only the last pulse width will be stored. 40 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 CLK CAPT x 9 3 x 14 t RISE t RISE t FALL t FALL Rise Fall 9 5 3 4 7 Capture Mode Enabled Figure 27: Capture Mode 11.1.3 Counter/Timer Mode The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use. As a timer the clock source is from the system clock, prescaled if required. The timer period is programmed into the fall register and the Fall register match interrupt enabled. The timer is started as either a single-shot or a repeating timer, and generates an interrupt when the counter reaches the Fall register value. When used to count external events on TIM0CK_GT the clock source is selected from the input pin and the number of events programmed into the Fall register. The Fall register match interrupt is enabled and the counter started, usually in single shot mode. An interrupt is generated when the programmed number of transitions is seen on the input pin. The transitions counted can configured to be rising, falling or both rising and falling edges. Edges on the event signal must be at least 100nsec apart, i.e. pulses must be wider than 100nsec. 11.1.4 Delta-Sigma Mode A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be implemented with up to 16-bit resolution. This requires that a resistor-capacitor network is placed between the output DIO pin and digital ground. A stream of pulses with digital voltage levels is generated which is integrated by the RC network to give an analogue voltage. A conversion time is defined in terms of a number of clock cycles. The width of the pulses generated is the period of a clock cycle. The number of pulses output in the cycle, together with the integrator RC values, will determine the resulting analogue voltage. For example, generating approximately half the number of pulses that make up a complete conversion period will produce a voltage on the RC output of VDD1/2, provided the RC time constant is chosen correctly. During a conversion, the pulses will be pseudo-randomly dispersed throughout the cycle in order to produce a steady voltage on the output of the RC network. The output signal is asserted for the number of clock periods defined in the High register, with the total period being 216 cycles. For the same value in the High register, the pattern of pulses on subsequent cycles is different, due to the pseudo-random distribution. The delta-sigma converter output can operate in a Return-To-Zero (RTZ) or a Non-Return-to-Zero (NRZ) mode. The NRZ mode will allow several pulses to be output next to each other. The RTZ mode ensures that each pulse is separated from the next by at least one period. This improves linearity if the rise and fall times of the output are different to one another. Essentially, the output signal is low on every other output clock period, and the conversion cycle time is twice the NRZ cycle time i.e. 217 clocks. The integrated output will only reach half VDD2 in RTZ mode, since even at full scale only half the cycle contains pulses. Figure 28 and Figure 29 illustrate the difference between RTZ and NRZ for the same programmed number of pulses.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 41 1 2 3 1 2 N Conversion cycle 1 217 N Conversion cycle 2 3 Figure 28: Return To Zero Mode in Operation 1 2 3 1 2 N Conversion cycle 1 N 3 216 Conversion cycle 2 Figure 29: Non-Return to Zero Mode 11.1.5 Infra-Red Transmission Mode Infra-red transmission mode is a special feature of Timer 2 that is used to facilitate the generation of waveforms for infra-red remote control transmission. Remote control protocols, such as Philips RC-6, apply On-Off Key (OOK) modulation to a carrier signal using an encoded bit stream. The infra-red transmission mode supports a variety of remote control protocols that have different carrier frequency, carrier duty-cycle and data bit encoding requirements. In this mode, Timer 2 is configured to produce a carrier waveform that is OOK modulated by a programmable bit sequence of up to 4096 bits stored in RAM. The resultant waveform is output to the associated Timer 2 output pin. The JN516x Integrated Peripherals API User Guide [4] includes some examples. 11.1.6 Example Timer/Counter Application Figure 30 shows an application of the JN516x timers to provide closed loop speed control. PWM1 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls the power in the DC motor. Timer 0 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application software executing the control algorithm. If required for other functionality, then the unused IO associated with the timers could be used as general purpose DIO. JN516x PWM1 Timer0 CLK/GATE CAPTURE PWM M Tacho 1N4007 +12V IRF521 1 pulse/rev Figure 30: Closed Loop PWM Speed Control Using JN516x Timers42 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 11.2 Tick Timer The JN516x contains a hardware timer that can be used for generating timing interrupts to software. It may be used to implement regular events such as ticks for software timers or an operating system, as a high-precision timing reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include: • 32-bit counter • 28-bit match value • Maskable timer interrupt • Single-shot, Restartable or Continuous modes of operation Match Value Counter = Mode Control & & SysClk Run Match Int Enable Tick Timer Interrupt Reset Mode Figure 31 Tick Timer The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated by a signal from the mode control block. A match register allows comparison between the counter and a programmed value. The match value, measured in 16MHz clock cycles is programmed through software, in the range 0 to 0x0FFFFFFF. The output of the comparison can be used to generate an interrupt if the interrupt is enabled and used in controlling the counter in the different modes. Upon configuring the timer mode, the counter is also reset. If the mode is programmed as single shot, the counter begins to count from zero until the match value is reached. The match signal will be generated which will cause an interrupt if enabled, and the counter will stop counting. The counter is restarted by reprogramming the mode. If the mode is programmed as restartable, the operation of the counter is the same as for the single shot mode, except that when the match value is reached the counter is reset and begins counting from zero. An interrupt will be generated when the match value is reached if it is enabled. Continuous mode operation is similar to restartable, except that when the match value is reached, the counter is not reset but continues to count. An interrupt will be generated when the match value is reached if enabled. 11.3 Wakeup Timers Two -41 bit wakeup timers are available in the JN516x driven from the 32kHz internal clock. They may run during sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period timings that may be required by the application. The wakeup timers do not run during deep sleep and may optionally © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 43 be disabled in sleep mode through software control. When a wakeup timer expires it typically generates an interrupt, if the device is asleep then the interrupt may be used as an event to end the sleep period. See Section 18 for further details on how they are used during sleep periods. Features include: • 41-bit down-counter • Optionally runs during sleep periods • Clocked by 32kHz system clock; either 32kHz RC oscillator, 32kHz XTAL oscillator or 32kHz clock input A wakeup timer consists of a 41-bit down counter clocked from the selected 32 kHz clock. An interrupt or wakeup event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wakeup event is required, the timer interrupt should be enabled before loading the count value for the period. Once the count value is loaded and counter started, the counter begins to count down; the counter can be stopped at any time through software control. The counter will remain at the value it contained when the timer was stopped and no interrupt will be generated. The status of the timers can be read to indicate if the timers are running and/or have expired; this is useful when the timer interrupts are masked. This operation will reset any expired status flags. 11.3.1 32 KHZ RC Oscillator Calibration The 32 KHZ RC oscillator that can be used to time sleep periods is designed to require very little power to operate and be self-contained, requiring no external timing components and hence is lower cost. As a consequence of using on-chip resistors and capacitors, the inherent absolute accuracy and temperature coefficient is lower than that of a crystal oscillator, but once calibrated the accuracy approaches that of a crystal oscillator. Sleep time periods should be as close to the desired time as possible in order to allow the device to wake up in time for important events, for example beacon transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can be programmed to wake up very close to the calculated time of the event and so keep current consumption to a minimum. If the sleep time is less accurate, it will be necessary to wake up earlier in order to be certain the event will be captured. If the device wakes earlier, it will be awake for longer and so reduce battery life. Please note, that oscillator has a default current consumption of around 0.5uA, optionally this can be reduced to 0.375uA, which can improve battery life, however, the calibrated accuracy and temperature coefficient will be worse as a consequence. For detailed electrical specifications, see Section 19.3.9. In order to allow sleep time periods to be as close to the desired length as possible, the true frequency of the RC oscillator needs to be determined to better than the initial 30% accuracy. The calibration factor can then be used to calculate the true number of nominal 32kHz periods needed to make up a particular sleep time. A calibration reference counter, clocked from the 16MHz system clock, is provided to allow comparisons to be made between the 32kHz RC clock and the 16MHz system clock when the JN516x is awake and running from the 32MHZ crystal. Wakeup timer0 counts for a set number of 32kHz clock periods during which time the reference counter runs. When the wakeup timer reaches zero the reference counter is stopped, allowing software to read the number of 16MHz clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer. The true period of the 32kHz clock can thus be determined and used when programming a wakeup timer to achieve a better accuracy and hence more accurate sleep periods For a RC oscillator running at exactly 32,000Hz the value returned by the calibration procedure should be 10000, for a calibration period of twenty 32,000Hz clock periods. If the oscillator is running faster than 32,000Hz the count will be less than 10000, if running slower the value will be higher. For a calibration count of 9000, indicating that the RC oscillator period is running at approximately 35kHz, to time for a period of 2 seconds the timer should be loaded with 71,111 ((10000/9000) x (32000 x 2)) rather than 64000.44 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 12 Pulse Counters Two 16-bit counters are provided that can increment during all modes of operation (including sleep). The first, PC0, increments from pulses received on DIO1 or DIO4. The other pulse counter, PC1 operates from DIO5 or DIO8 depending upon the configuration. This is enabled under software control. The pulses can be de-bounced using the 32kHz clock to guard against false counting on slow or noisy edges. Increments occur from a configurable rising or falling edge on the respective DIO input. Each counter has an associated 16-bit reference that is loaded by the user. An interrupt (and wakeup event if asleep) may be generated when a counter reaches its pre-configured reference value. The two counters may optionally be cascaded together to provide a single 32-bit counter, linked to any of the four DIO’s. The counters do not saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues when the reference value is reached without software interaction so that pulses are not missed even if there is a long delay before an interrupt is serviced or during the wakeup process. The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be used.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 45 13 Serial Communications The JN516x has two Universal Asynchronous Receiver/Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. The interfaces perform serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices. In both directions, a configurable FIFO buffer (with a default depth of 16-bytes) allows the CPU to read and write multiple characters on each transaction. This means that the CPU is freed from handling data on a character-by-character basis, with the associated high processor overhead. The UARTs have the following features: • Emulates behaviour of industry standard NS16450 and NS16550A UARTs • Configurable transmit and receive FIFO buffers (with default depths of 16-bytes for each), with direct access to fill levels of each. Adds/deletes standard start, stop and parity bits to or from the serial data • Independently controlled transmit, receive, status and data sent interrupts • Optional modem flow control signals CTS and RTS on UART0. • Fully programmable data formats: baud rate, start, stop and parity settings • False start bit detection, parity, framing and FIFO overrun error detect and break indication • Internal diagnostic capabilities: loop-back controls for communications link fault isolation • Flow control by software or automatically by hardware Processor Bus Divisor Latch Registers Line Status Register Line Control Register FIFO Control Register Receiver FIFO Transmitter FIFO Baud Generator Logic Transmitter Shift Register Receiver Shift Register Transmitter Logic Receiver Logic RXD TXD Modem Control Register Modem Status Register Modem Signals Logic RTS CTS Interrupt ID Register Interrupt Enable Register Interrupt Logic Internal Interrupt Figure 32: UART Block Diagram The serial interfaces contain programmable fields that can be used to set number of data bits (5, 6,7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation of single or multiple stop bit, (for 5 bit data, multiple is 1.5 stop bits; for 6, 7 or 8 data bits, multiple is 2 bits). The baud rate is programmable up to 1Mbps, standard baud rates such as 4800, 9600, 19.2k, 38.4k etc. can be configured. For applications requiring hardware flow control, UART0 provides two control signals: Clear-To-Send (CTS) and Request-To-Send (RTS). CTS is an indication sent by an external device to the UART that it is ready to receive data. RTS is an indication sent by the UART to the external device that it is ready to receive data. RTS is controlled from software, while the value of CTS can be read. Monitoring and control of CTS and RTS is a software activity, normally performed as part of interrupt processing. The signals do not control parts of the UART hardware, but simply indicate to software the state of the UART external interfaces. Alternatively, the Automatic Flow Control mode can be set 46 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted. Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO, one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The status of the Transmit FIFO can be checked to see if it is empty, and if there is a character being transmitted. The status of the Receive FIFO can also be checked, indicating if conditions such as parity error, framing error or break indication have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if there is data held in the receive FIFO. UART0 and UART1 can both be configured to use standard or alternative DIO lines, as shown in Table 5. Additionally, UART0 can be configured to be used in 2-wire mode (where CTS0 and RTS0 are not configured), and UART1 can be configured in 1-wire mode (where RXD1 is not configured). These freed up DIO pins can then be used for other purposes. Signal DIO Assignment Standard pins Alternative pins CTS0 DIO4 DIO12 RTS0 DIO5 DIO13 TXD0 DIO6 DIO14 RXD0 DIO7 DIO15 TXD1 DIO14 DIO11 RXD1 DIO15 DIO9 Table 6: UART IO . Note: With the automatic flow control threshold set to 15, the hardware flow control within the UART’s block negates RTS when they receive FIFO that is about to become full. In some instances it has been observed that remote devices that are transmitting data do not respond quickly enough to the de-asserted CTS and continue to transmit data. In these instances the data will be lost in a receive FIFO overflow. 13.1 Interrupts Interrupt generation can be controlled for the UART’s block, and is divided into four categories: • Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times. • Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted. • Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an entire character. • Modem Status: Generated when the CTS (Clear To Send) input control line changes. 13.2 UART Application The following example shows the UART0 connected to a 9-pin connector compatible with a PC. As the JN516x device pins do not provide the RS232 line voltage, a level shifter is used.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 47 JN516x RTS CTS TXD RXD UART0 RS232 Level Shifter 1 2 3 4 5 6 7 8 9 CD RD TD DTR SG DSR RTS CTS RI PC COM Port 1 5 Pin Signal 6 9 Figure 33: JN516x Serial Communication Link48 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 14 JTAG Test Interface The JN516x includes an IEEE1149.1 compliant JTAG port for the purpose of manufacturing test. The software debugger is not supported with this product. The JTAG interface does not support boundary scan testing. It is recommended that the JN516x is not connected as part of the board scan chain.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 49 15 Two-Wire Serial Interface (I2 C) The JN516x includes industry standard I 2 C two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following features: Common to both master and slave: • Compatible with both I2 C and SMbus peripherals • Support for 7 and 10-bit addressing modes • Optional pulse suppression on signal inputs (60ns guaranteed, 125ns typical) Master only: • Multi-master operation • Software programmable clock frequency • Supports Slave clock stretching • Software programmable acknowledge bit • Interrupt or bit-polling driven byte-by-byte data-transfers • Bus busy detection Slave only: • Programmable slave address • Simple byte level transfer protocol • Write data flow control using acknowledge mechanism • Read data flow control using clock stretching • Read data preloaded or provided as required The Serial Interface is accessed, depending upon the configuration, DIO14 and DIO15 or DIO16 and DIO17. This is enabled under software control. The following table details which DIO are used for the Serial Interface depending upon the configuration. Signal DIO Assignment Standard pins Alternative pins SIF_CLK DIO14 DIO16 SIF_D DIO15 DIO17 Table 7: Two-Wire Serial Interface IO 15.1 Connecting Devices The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial interface function of these pins is selected when the interface is enabled. They are both bi-directional lines, connected internally to the positive supply voltage via weak (50kΩ) programmable pull-up resistors. However, it is recommended that external 4.7kΩ pull-ups be used for reliable operation at high bus speeds, as shown in Figure 34. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an opendrain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is solely dependent on the bus capacitance limit of 400pF. As this is an optional interface with two alternate positions, the DIO cells have not been customised for I 2 C operation. In particular, note that there are ESD diodes to the nominal 3 volt supply (VDD2) from the SIF_CLK and SIF_D pins. Therefore, if the VDD supply is removed from the JN5168 and this then discharges to ground, a path would exist that could pull down the bus lines (see 2.2.6).50 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 SIF_CLK SIF_D VDD D1_OUT D1_I N CLK1_I N CLK1_OUT D2_I N CLK2_I N CLK2_OUT DEVICE 1 DEVICE 2 RP RP Pullup Resistors D2_OUT JN516x SI F DIO14 DIO15 Figure 34: Connection Details 15.2 Clock Stretching Slave devices can use clock stretching to slow down the read transfer bit rate. After the master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period and then release it. If the slave’s SIF_CLK low period is greater than the master’s low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait states – see section 15.4 for further details. SIF_CLK SIF_CLK SIF_CLK Master SIF_CLK Slave SIF_CLK Wired-AND SIF_CLK Clock held low by Slave Figure 35: Clock Stretching 15.3 Master Two-wire Serial Interface When operating as a master device, it provides the clock signal and a prescale register determines the clock rate, allowing operation up to 400kbit/s. Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for indicating when start, stop, read, write and acknowledge control should be generated. Write data written into a transmit buffer will be written out across the two-wire interface when indicated, and read data received on the interface is made available in a receive buffer. Indication of when a particular transfer has completed may be indicated by means of an interrupt or by polling a status bit. The first byte of data transferred by the device after a start bit is the slave address. The JN516x supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address will respond by returning an acknowledge bit. The master interface provides a true multi-master bus including collision detection and arbitration that prevents data corruption. If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock. Because of the wired-AND connection of the interface, a high-to-low transition on the bus affects all connected devices. This means a high-to-low transition on the SIF_CLK line causes all concerned devices to count off their low period. Once the clock input of a device has gone low, it will hold the SIF_CLK line in that state until the clock high state is reached when it releases the SIF_CLK line. Due to the wired-AND connection, the SIF_CLK line will therefore be held low by the device with the longest low period, and held high by the device with the shortest high period.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 51 SIF_CLK1 SIF_CLK2 SIF_CLK Master1 SIF_CLK Master2 SIF_CLK Wired-AND SIF_CLK Start counting low period Start counting high period Wait State Figure 36: Multi-Master Clock Synchronisation After each transfer has completed, the status of the device must be checked to ensure that the data has been acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost.52 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 15.4 Slave Two-wire Serial Interface When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal low if it is required to apply clock stretching during read transfers. Only transfers whose address matches the value programmed into the interface’s address register are accepted. The interface allows both 7 and 10 bit addresses to be programmed, but only responds with an acknowledge to a single address. Addresses defined as “reserved” will not be responded to, and should not be programmed into the address register. A list of reserved addresses is shown in Table 8. Address Name Behaviour 0000 000 General Call/Start Byte Ignored 0000 001 CBUS address Ignored 0000 010 Reserved Ignored 0000 011 Reserved Ignored 0000 1XX Hs-mode master code Ignored 1111 1XX Reserved Ignored 1111 0XX 10-bit address Only responded to if 10 bit address set in address register Table 8 : List of two-wire serial interface reserved addresses Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for taking write data from a receive buffer and providing read data to a transmit buffer when indicated. A series of interrupt status bits are provided to control the flow of data. For writes, in to the slave interface, it is important that data is taken from the receive buffer by the processor before the next byte of data arrives. To enable this, the interface returns a Not Acknowledge (NACK) to the master if more data is received before the previous data has been taken. This will lead to the termination of the current data transfer. For reads, from the slave interface, the data may be preloaded into the transmit buffer when it is empty (i.e. at the start of day, or when the last data has been read), or fetched each time a read transfer is requested. When using data preload, read data in the buffer must be replenished following a data write, as the transmit and received data is contained in a shared buffer. The interface will hold the bus using clock stretching when the transmit buffer is empty. Interrupts may be triggered when: • Data Buffer read data is required – a byte of data to be read should be provided to avoid the interface from clock stretching • Data Buffer read data has been taken – this indicates when the next data may be preloaded into the data buffer • Data Buffer write data is available – a byte of data should be taken from the data buffer to avoid data backoff as defined above • The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop or Restart is seen • A protocol error has been spotted on the interface© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 53 16 Random Number Generator A random number generator is provided which creates a 16-bit random number each time it is invoked. Consecutive calls can be made to build up any length of random number required. Each call takes approximately 0.25msec to complete. Alternatively, continuous generation mode can be used where a new number is generated approximately every 0.25msec. In either mode of operation an interrupt can be generated to indicate when the number is available, or a status bit can be polled. The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these clocks are asynchronous to each other, each sampled bit is unpredictable and hence random.54 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 17 Analogue Peripherals The JN516x contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors and switches. ADC Supply Voltage (VDD1) COMP1M (DIO17) Comparator 1 COMP1P (DIO16) ADC1 VREF/ADC2 ADC3 (DIO0) ADC4 (DIO1) Vref Internal Reference Vref Select Chip Boundary Temp Sensor Figure 37: Analogue Peripherals In order to provide good isolation from digital noise, the analogue peripherals and radio are powered by the radio regulator, which is supplied from the analogue supply VDD1 and referenced to analogue ground VSSA. A reference signal Vref for the ADC can be selected between an internal bandgap reference or an external voltage reference supplied to the VREF pin. ADC input 2 cannot be used if an external reference is required, as this uses the same pin as VREF. Note also that ADC3 and ADC4 use the same pins as DIO0 and DIO1 respectively. These pins can only be used for the ADC if they are not required for any of their alternative functions. Similarly, the comparator inputs are shared with DIO16 and DIO17. If used for their analogue functions, these DIOs must be put into a passive state by setting them to Inputs with their pull-ups disabled. The ADC is clocked from a common clock source derived from the 16MHz clock. 17.1 Analogue to Digital Converter The 10-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input channels: four available externally, one connected to an internal temperature sensor, and one connected to an internal supply monitoring circuit.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 55 17.1.1 Operation The input range of the ADC can be set between 0V to either the reference voltage or twice the reference voltage. The reference can be either taken from the internal voltage reference or from the external voltage applied to the VREF pin. For example, an external reference of 1.2V supplied to VREF may be used to set the ADC range between 0V and 2.4V. VREF Gain Setting Maximum Input Range Supply Voltage Range (VDD) 1.2V 1.6V 1.2V 1.6V 0 0 1 1 1.2V 1.6V 2.4V 3.2V 2.2V - 3.6V 2.2V - 3.6V 2.6V - 3.6V 3.4V - 3.6V Table 9: ADC Maximum Input Range The input clock to the ADC is 16MHz and can be divided down to 2MHz, 1MHz, 500kHz and 250kHz. During an ADC conversion the selected input channel is sampled for a fixed period and then held. This sampling period is defined as a number of ADC clock periods and can be programmed to 2, 4, 6 or 8. The conversion rate is ((3 x Sample period) + 13) clock periods. For example for 500kHz conversion with sample period of 2 will be (3 x 2) + 13 = 19 clock periods, 38µsecs or 26.32kHz. The ADC can be operated in either a single conversion mode or alternatively a new conversion can be started as soon as the previous one has completed, to give continuous conversions. If the source resistance of the input voltage is 1kΩ or less, then the default sampling time of 2 clocks should be used. The input to the ADC can be modelled as a resistor of 5kΩ(typ) and 10kΩ (max) to represent the on-resistance of the switches and the sampling capacitor 8pF. The sampling time required can then be calculated, by adding the sensor source resistance to the switch resistance, multiplying by the capacitance giving a time constant. Assuming normal exponential RC charging, the number of time constants required to give an acceptable error can be calculated, 7 time constants gives an error of 0.091%, so for 10-bit accuracy 7 time constants should be the target. For a source with zero resistance, 7 time constants is 640 nsecs, hence the smallest sampling window of 2 clock periods can be used. ADC pin 5 K 8 pF Sample Switch ADC front end Figure 38: ADC Input Equivalent Circuit The ADC sampling period, input range and mode (single shot or continuous) are controlled through software. When the ADC conversion is complete, an interrupt is generated. Alternatively the conversion status can be polled. When operating in continuous mode, it is recommended that the interrupt is used to signal the end of a conversion, since conversion times may range from 9.5 to 148 µsecs. Polling over this period would be wasteful of processor bandwidth. To facilitate averaging of the ADC values, which is a common practice in microcontrollers, a dedicated accumulator has been added, the user can define the accumulation to occur over 2,4,8 or 16 samples. The end of conversion interrupt can be modified to occur at the end of the chosen accumulation period, alternatively polling can still be used. Software can then be used to apply the appropriate rounding and shifting to generate the average value, as well as setting up the accumulation function. For detailed electrical specifications, see Section 19.3.7.56 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 17.1.2 Supply Monitor The internal supply monitor allows the voltage on the analogue supply pin VDD1 to be measured. This is achieved with a potential divider that reduces the voltage by a factor of 0.666, allowing it to fall inside the input range of the ADC when set with an input range twice the internal voltage reference. The resistor chain that performs the voltage reduction is disabled until the measurement is made to avoid a continuous drain on the supply. 17.1.3 Temperature Sensor The on chip temperature sensor can be used either to provide an absolute measure of the device temperature or to detect changes in the ambient temperature. In common with most on chip temperature sensors, it is not trimmed and so the absolute accuracy variation is large; the user may wish to calibrate the sensor prior to use. The sensor forces a constant current through a forward biased diode to provide a voltage output proportional to the chip die temperature which can then be measured using the ADC. The measured voltage has a linear relationship to temperature as described in Section 19.3.13. Because this sensor is on chip, any measurements taken must account for the thermal time constants. For example, if the device just came out of sleep mode the user application should wait until the temperature has stabilised before taking a measurement. 17.1.4 ADC Sample Buffer Mode In this mode, the ADC operates in conjunction with a DMA (Direct Memory Access) engine as follows: • ADC sampling is triggered at a configurable rate using one of the on-chip Timers (Timer 0, 1, 2, 3 or 4) • ADC samples are automatically stored in a buffer located in RAM using a DMA mechanism • ADC inputs may be multiplexed between different analogue sources The 10-bit ADC data samples are transferred into the buffer in RAM as 16-bit words. The maximum number of 16-bit words that may allocated in RAM for ADC sample storage is 2047. The buffer may be configured to automatically wrap around to the start when full. Interrupts may be configured to indicate when the buffer is half-full, full and has overflowed. The CPU may perform other tasks while the data transfer and storage is being managed independently by the DMA engine - the CPU only needs to configure the ADC sample buffer mode and deal with the stored samples in the buffer when an interrupt occurs. ADC sample buffer mode allows up to six analogue inputs to be multiplexed in combination. These inputs comprise four external inputs (ADC1-4, corresponding to IO pins), an on-chip temperature sensor and an internal voltage monitor. Samples from all the selected inputs will be produced on each timer trigger and stored in consecutive RAM locations. 17.2 Comparator The JN516x contains one analogue comparator, COMP1, that is designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level can be set to a nominal value of 0mV, 10mV, 20mV or 40mV. The source of the negative input signal for the comparator can be set to the internal voltage reference, the negative external pin (COMP1M, which uses the same pin as DIO17) or the positive external pin (COMP1P, on the same pin as DIO16). The source of the positive input signal can be COMP1P or COMP1M. DIO16 and DIO17 cannot be used if the external comparator inputs are needed. The comparator output is routed to an internal register and can be polled, or can be used to generate interrupts. The comparator can be disabled to reduce power consumption. DIO16 and DIO17 should be set to inputs with pull-ups disabled, when using the comparator. The comparator also has a low power mode where the response time of the comparator is slower than the normal mode, but the current required is greatly reduced. These figures are specified in Section 19.3.8. It is the only mode that may be used during sleep, where a transition of the comparator output will wake the device. The wakeup action and the configuration for which edge of the comparator output will be active are controlled through software. In sleep mode the negative input signal source must be configured to be driven from the external pins.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 57 18 Power Management and Sleep Modes 18.1 Operating Modes Three operating modes are provided in the JN516x that enable the system power consumption to be controlled carefully to maximise battery life. • Active Processing Mode • Sleep Mode • Deep Sleep Mode The variation in power consumption of the three modes is a result of having a series of power domains within the chip that may be controllably powered on or off. 18.1.1 Power Domains The JN516x has the following power domains: • VDD Supply Domain: supplies the wake-up timers and controller, DIO blocks, Comparator, SVM and BOR plus Fast RC, 32kHz RC and crystal oscillators. This domain is driven from the external supply (battery) and is always powered. The wake-up timers and controller, and the 32kHz RC and crystal oscillators may be powered on or off in sleep mode through software control. • Digital Logic Domain: supplies the digital peripherals, CPU, Flash, RAM when in Active Processing Mode, Baseband controller, Modem and Encryption processor. It is powered off during sleep mode. • RAM Domain: supplies the RAM when in Active Processing Mode. Also supplies the Ram during sleep mode to retain the memory contents. It may be powered on or off for sleep mode through software control. • Radio Domain: supplies the radio interface, ADCs and temperature sensor. It is powered during transmit and receive and when the analogue peripherals are enabled. It is controlled by the baseband processor and is powered off during sleep mode. The current consumption figures for the different modes of operation of the device is given in Section 19.2.2. 18.2 Active Processing Mode Active processing mode in the JN516x is where all of the application processing takes place. By default, the CPU will execute at the selected clock speed executing application firmware. All of the peripherals are available to the application, as are options to actively enable or disable them to control power consumption; see specific peripheral sections for details. Whilst in Active processing mode there is the option to doze the CPU but keep the rest of the chip active; this is particularly useful for radio transmit and receive operations, where the CPU operation is not required therefore saving power. 18.2.1 CPU Doze Whilst in doze mode, CPU operation is stopped but the chip remains powered and the digital peripherals continue to run. Doze mode is entered through software and is terminated by any interrupt request. Once the interrupt service routine has been executed, normal program execution resumes. Doze mode uses more power than sleep and deep sleep modes but requires less time to restart and can therefore be used as a low power alternative to an idle loop. Whilst in CPU doze the current associated with the CPU is not consumed, therefore the basic device current is reduced as shown in the figures in Section 19.2.2.1. 18.3 Sleep Mode The JN516x enters sleep mode through software control. In this mode most of the internal chip functions are shutdown to save power, however the state of DIO pins are retained, including the output values and pull-up enables, and this therefore preserves any interface to the outside world. 58 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period. If the wakeup timers are not to be used for a wakeup event and the application does not require them to run continually, then power can be saved by switching off the 32kHz oscillator if selected as the 32kHz system clock through software control. The oscillator will be restarted when a wakeup event occurs. Whilst in sleep mode one of four possible events can cause a wakeup to occur: transitions on DIO inputs, expiry of wakeup timers, pulse counters maturing or comparator events. If any of these events occur, and the relevant interrupt is enabled, then an interrupt is generated that will cause a wakeup from sleep. It is possible for multiple wakeup sources to trigger an event at the same instant and only one of them will be accountable for the wakeup period. It is therefore necessary in software to remove all other pending wakeup events prior to requesting entry back into sleep mode; otherwise, the device will re-awaken immediately. When wakeup occurs, a similar sequence of events to the reset process described in Section 6.1 happens, including the checking of the supply voltage by the Supply Voltage Monitor 6.4. The High-Speed RC oscillator is started up, once stable the power to CPU system is enabled and the reset is removed. Software determines that this is a reset from sleep and so commences with the wakeup process. If RAM contents were held through sleep, wakeup is quicker as the software does not have to initialise RAM contents meaning the application can recommence more quickly. See Section 19.3.5 for wake-up timings. 18.3.1 Wakeup Timer Event The JN516x contains two 41-bit wakeup timers that are counters clocked from the 32kHz oscillator, and can be programmed to generate a wake-up event. Following a wakeup event, the timers continue to run. These timers are described in Section 11.3. Timer events can be generated from both of the two timers; one is intended for use by the 802.15.4 protocol, the other being available for use by the Application running on the CPU. These timers are available to run at any time, even during sleep mode. 18.3.2 DIO Event Any DIO pin when used as an input has the capability, by detecting a transition, to generate a wake-up event. Once this feature has been enabled the type of transition can be specified (rising or falling edge). Even when groups of DIO lines are configured as alternative functions such as the UARTs or Timers etc, any input line in the group can still be used to provide a wakeup event. This means that an external device communicating over the UART can wakeup a sleeping device by asserting its RTS signal pin (which is the CTS input of the JN516x). 18.3.3 Comparator Event The comparator can generate a wakeup interrupt when a change in the relative levels of the positive and negative inputs occurs. The ability to wakeup when continuously monitoring analogue signals is useful in ultra-low power applications. For example, the JN516x can remain in sleep mode until the voltage drops below a threshold and then be woken up to deal with the alarm condition and the comparator has a low current mode to facilitate this. 18.3.4 Pulse Counter The JN516x contains two 16 bit pulse counters that can be programmed to generate a wake-up event. Following the wakeup event the counters will continue to operate and therefore no pulse will be missed during the wake-up process. These counters are described in Section 12.To minimize sleep current it is possible to disable the 32K RC oscillator and still use the pulse counters to cause a wake-up event, provided debounce mode is not required. 18.4 Deep Sleep Mode Deep sleep mode gives the lowest power consumption. All switchable power domains are off and most functions in the VDD supply power domain are stopped, including the 32kHz RC oscillator. However, the Brown-Out Reset remains active as well as all the DIO cells. This mode can be exited by a hardware reset on the RESETN pin, or an enabled DIO or comparator wakeup event. In all cases, the wakeup sequence is equivalent to a power-up sequence, with no knowledge retained from the previous time the device was awake.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 59 19 Electrical Characteristics 19.1 Maximum Ratings Exceeding these conditions may result in damage to the device. Parameter Min Max Device supply voltage VDD1, VDD2 -0.3V 3.6V Supply voltage at voltage regulator bypass pins VB_xxx -0.3V 1.98V Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RF_IN. -0.3V VB_xxx + 0.3V Voltage on analogue pins VREF, ADC1, IBIAS -0.3V VDD1 + 0.3V Voltage on any digital pin -0.3V VDD2 + 0.3V Storage temperature -40ºC 150ºC Reflow soldering temperature according to IPC/JEDEC J-STD-020C 260ºC ESD rating Human Body Model 1 2.0kV Charged Device Model 2 500V 1) Testing for Human Body Model discharge is performed as specified in JEDEC Standard JESD22-A114. 2) Testing for Charged Device Model discharge is performed as specified in JEDEC Standard JESD22-C101. 19.2 DC Electrical Characteristics 19.2.1 Operating Conditions Supply Min Max VDD1, VDD2 2.0V 3.6V Standard Ambient temperature range -40ºC 85ºC Extended Ambient temperature range -40ºC 125ºC In the following sections typical is defined as 25ºC and VDD1,2 = 3V Most parameter values cover the extended temperature range up to 125 ºC, where this is not the case, two values are given, the value in italics type face is for standard temperature range up to 85ºC and the value in bold is for the extended range.60 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 19.2.2 DC Current Consumption VDD = 2.0 to 3.6V, -40 to +125º C 19.2.2.1 Active Processing Mode: Min Typ Max Unit Notes CPU processing 32,16,8,4,2 or 1MHz 1700 + 205/MHz µA GPIOs enabled. When in CPU doze the current related to CPU speed is not consumed. Radio transmit 15.3 mA CPU in software doze – radio transmitting Radio receive 17.0 mA CPU in software doze – radio in receive mode The following current figures should be added to those above if the feature is being used ADC 550 µA Temperature sensor and battery measurements require ADC Comparator 73/0.8 µA Normal/low-power UART 60 µA For each UART Timer 21 µA For each Timer 2-wire serial interface (I2 C) 46 µA 19.2.2.2 Sleep Mode Mode: Min Typ Max Unit Notes Sleep mode with I/O wakeup 0.12 µA Waiting on I/O event Sleep mode with I/O and RC Oscillator timer wakeup – measured at 25ºC 0.64 µA As above, but also waiting on timer event. If both wakeup timers are enabled then add another 0.05µA 32kHz crystal oscillator 1.4 µA As alternative sleep timer The following current figures should be added to those above if the feature is being used RAM retention– measured at 25ºC 0.9 µA Comparator (low-power mode) 0.8 µA Reduced response time 19.2.2.3 Deep Sleep Mode Mode: Min Typ Max Unit Notes Deep sleep mode– measured at 25ºC 100 nA Waiting on chip RESET or I/O event© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 61 19.2.3 I/O Characteristics VDD = 2.0 to 3.6V, -40 to +125º C, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Internal DIO pullup resistors 40 50 60 kΩ Internal RESETN pullup resistor 267 325 455 605 410 500 700 930 615. 636 750, 775 1050, 1085 1395, 1441 kΩ VDD2 = 3.6V VDD2 = 3.0V VDD2 = 2.2V VDD2 = 2.0V Digital I/O High Input VDD2 x 0.7 VDD2 V Digital I/O low Input -0.3 VDD2 x 0.27 V Digital I/O input hysteresis 200 310 400 mV DIO High O/P (2.7-3.6V) VDD2 x 0.8 VDD2 V With 4mA load DIO Low O/P (2.7-3.6V) 0 0.4 V With 4mA load DIO High O/P (2.2-2.7V) VDD2 x 0.8 VDD2 V With 3mA load DIO Low O/P (2.2-2.7V) 0 0.4 V With 3mA load DIO High O/P (2.0-2.2V) VDD2 x 0.8 VDD2 V With 2.5mA load DIO Low O/P (2.0-2.2V) 0 0.4 V With 2.5mA load Current sink/source capability 4 3 2.5 mA VDD2 = 2.7V to 3.6V VDD2 = 2.2V to 2.7V VDD2 = 2.0V to 2.2V IIL - Input Leakage Current 20, 30 nA Vcc = 3.6V, pin low IIH - Input Leakage Current 20, 60 nA Vcc = 3.6V, pin high 19.3 AC Characteristics 19.3.1 Reset and Supply Voltage Monitor Internal RESET VDD VPOT t STAB Figure 39: Internal Power-on Reset without Showing Brown-Out62 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Internal RESET RESETN VRST t STAB t RST Figure 40: Externally Applied Reset VDD = 2.0 to 3.6V, -40 to +125º C Parameter Min Typ Max Unit Notes External Reset pulse width to initiate reset sequence (tRST) 1 µs Assumes internal pullup resistor value of 100K worst case and ~5pF external capacitance External Reset threshold voltage (VRST) VDD2 x 0.7 V Minimum voltage to avoid being reset Internal Power-on Reset threshold voltage (VPOT) Rise/fall time > 10mS 1.44 1.41 V Rising Falling Spike Rejection Square wave pulse 1us Triangular wave pulse 10us 1.2 1.3 V Depth of pulse to trigger reset Reset stabilisation time (tSTAB) 180 µs Note 1 Chip current when held in reset (IRESET) 6 uA Brown-Out Reset Current Consumption 80 nA Supply Voltage Monitor Threshold Voltage (VTH) 1.86 1.92 2.02 2.11 2.21 2.30 2.59 2.88 1.94 2.00 2.10 2.20 2.30 2.40 2.70 3.00 2.00 2.06 2.16 2.27 2.37 2.47 2.78 3.09 V Configurable threshold with 8 levels Supply Voltage Monitor Hysteresis (VHYS) 37 38 45 52 58 65 82 100 mV Corresponding to the 8 threshold levels 1 Time from release of reset to start of executing of bootloader code from internal flash. An extra 15us is incurred if the BOR circuit has been activated (e.g., if the supply voltage has been ramped up from 0V)".© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 63 VTH + VHYS VTH DVDD Internal BORest Internal SVM VPOT Figure 41 Brown-out Reset Followed By Supply Voltage Montior trigger 19.3.2 SPI Master Timing t t SSH SSS t CK t SI t HI MOSI (mode=1,3) SS MOSI (mode=0,2) MISO (mode=0,2) MISO (mode=1,3) t VO t VO CLK (mode=0,1) t SI t HI CLK (mode=2,3) Figure 42: SPI Master Timing Parameter Symbol Min Max Unit Clock period tCK 62.5 - ns Data setup time tSI 16.7 @ 3.3V 18.2 @ 2.7V 21.0 @ 2.0V - ns Data hold time tHI 0 ns Data invalid period tVO - 15 ns Select set-up period tSSS 60 - ns Select hold period tSSH 30 (SPICLK = 16MHz) 0 (SPICLK<16MHz, mode=0 or 2) 60 (SPICLK<16MHz, mode=1 or 3) - ns64 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 19.3.3 SPI Slave Timing Parameter Symbol Min Max Unit Clock period tCK 125 - ns Idle time tIDLE 125 - ns Data input setup time tSI 10 - ns Data input hold time tHI 10 - ns Data output invalid period from SPISCLK falling edge tCKVO - 30 ns Data output invalid period from SPISSEL falling edge tSELVO 30 ns Delay from SPISSEL falling edge to SPISCLK rising edge tSELA 30 - ns Delay from SPISCLK falling edge to SPISSEL rising edge tSELN 30 - ns … … SPISCLK SPISSEL SPISMOSI SPISMISO … … t tSELN IDLE tSI tHI tSELA tCK tSELVO tCKVO Figure 43: SPI Slave Timing© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 65 19.3.4 Two-wire Serial Interface t BUF S Sr P S t LOW t HD;STA t F t R t HD;DAT t HIGH t SU;DAT t SU;STA t HD;STA t SU;STO t SP t R t F SIF_D SIF_CLK Figure 44: Two-wire Serial Interface Timing Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SIF_CLK clock frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD:STA 4 - 0.6 - µs LOW period of the SIF_CLK clock tLOW 4.7 - 1.3 - µs HIGH period of the SIF_CLK clock tHIGH 4 - 0.6 - µs Set-up time for repeated START condition tSU:STA 4.7 - 0.6 - µs Data setup time SIF_D tSU:DAT 0.25 - 0.1 - µs Rise Time SIF_D and SIF_CLK tR - 1000 20+0.1Cb 300 ns Fall Time SIF_D and SIF_CLK tF - 300 20+0.1Cb 300 ns Set-up time for STOP condition tSU:STO 4 - 0.6 - µs Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - µs Pulse width of spikes that will be suppressed by input filters (Note 1) tSP - 60 - 60 ns Capacitive load for each bus line Cb - 400 - 400 pF Noise margin at the LOW level for each connected device (including hysteresis) Vnl 0.1VDD - 0.1VDD - V Noise margin at the HIGH level for each connected device (including hysteresis) Vnh 0.2VDD - 0.2VDD - V Note 1: This figure indicates the pulse width that is guaranteed to be suppressed. Pulse with widths up to 125nsec may also get suppressed. 19.3.5 Wakeup Timings Parameter Min Typ Max Unit Notes Time for crystal to stabilise ready to run CPU 0.74 ms Reached oscillator amplitude threshold. Default bias current Time for crystal to stabilise ready for radio activity 1.0 ms Wake up from Deep Sleep or from Sleep 170 µs Time to CPU release Start-up time from reset RESETN pin, BOR or SVM 180 µs Time to CPU release Wake up from CPU Doze mode 0.2 µs 66 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 19.3.6 Bandgap Reference VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Voltage 1.198 1.235 1.260 V DC power supply rejection 58 dB at 25ºC Temperature coefficient +40 +135 +65 +93 ppm/ºC 20 to 85ºC -40ºC to 20ºC 20 to 125 ºC -40ºC to 85ºC Point of inflexion +80 ºC 19.3.7 Analogue to Digital Converters VDD = 3.0V, VREF = 1.2V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Resolution 10 bits 500kHz Clock Current consumption 550 µA Integral nonlinearity ± 1.6, 1.8 LSB Differential nonlinearity -0.5 +0.5 LSB Guaranteed monotonic Offset error -10 -20 mV 0 to Vref range 0 to 2Vref range Gain error +10 +20 mV 0 to Vref range 0 to 2Vref range Internal clock 0.25,0.5 or 1.0 MHz 16MHz input clock, ÷16,32or 64 No. internal clock periods to sample input 2, 4, 6 or 8 Programmable Conversion time 9.5 148 µs Programmable Input voltage range 0.04 Vref or 2*Vref V Switchable. Refer to 17.1.1 Vref (Internal) See Section 19.3.6 Vref (External) 1.15 1.2 1.6 V Allowable range into VREF pin Input capacitance 8 pF In series with 5K ohms© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 67 19.3.8 Comparator VDD = 2.0 to 3.6V -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Analogue response time (normal) 90 125,130 ns +/- 250mV overdrive 10pF load Total response time (normal) including delay to Interrupt controller 125 + 125,130 ns Digital delay can be up to a max. of two 16MHz clock periods Analogue response time (low power) 2.2 2.8 µs +/- 250mV overdrive No digital delay Hysteresis 7 14 28 10 20 40 16, 17 28, 30 53, 57 mV Programmable in 3 steps and zero Vref (Internal) See Section 19.3.6 V Common Mode input range 0 Vdd V Current (normal mode) 56 73 96, 100 µA Current (low power mode) 0.8 1.0, 1.1 µA 19.3.9 32kHz RC Oscillator VDD = 2.0 to 3.6V, -40 to +125 ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Current consumption of cell and counter logic (default) 590 520 465 720, 800 660, 740 600, 650 nA 3.6V 3.0V 2.0V Current consumption of cell and counter logic (low power) 465 375 290 500,550 425,460 330,370 nA 3.6V 3.0V 2.0V 32kHz clock un-calibrated accuracy -10% 32kHz +40% Without temperature & voltage variation (note1) Calibrated 32kHz accuracy (default) Low power ±300 ±600 ppm For a 1 second sleep period calibrating over 20 x 32kHz clock periods Variation with temperature -0.010 -0.020 %/°C Default Low power Variation with VDD2 -3.0 %/V Note1: Measured at 3v and 25 deg C 68 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 19.3.10 32kHz Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Current consumption of cell and counter logic 1.4 1.75, 2.0 µA This is sensitive to the ESR of the crystal, Vdd and total capacitance at each pin Start – up time 0.6 s Assuming xtal with ESR of less than 40kohms and CL= 9pF External caps = 15pF (Vdd/2mV pk-pk) see Appendix B Input capacitance 1.4 pF Bondpad and package Transconductance 18.5 µA/V External Capacitors (CL=9pF) 15 pF Total external capacitance needs to be 2*CL, allowing for stray capacitance from chip, package and PCB Amplitude at Xout Vdd-0.2 Vp-p 19.3.11 32MHz Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Current consumption 300 375 450, 500 µA Excluding bandgap ref. Start – up time 0.74 ms Assuming xtal with ESR of less than 40ohms and CL= 9pF External caps = 15pF see Appendix B Input capacitance 1.4 pF Bondpad and package Transconductance 3.65, 3.55 4.30 5.16 mA/V DC voltages, XTALIN/XTALOUT 390/432 375/412 425/472 470/527 mV External Capacitors (CL=9pF) 15 pF Total external capacitance needs to be 2*CL, allowing for stray capacitance from chip, package and PCB Amplitude detect threshold 320 mVp-p Threshold detection accessible via API© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 69 19.3.12 High-Speed RC Oscillator VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Current consumption of cell 81 145 250, 275 µA Clock native accuracy -16% +18% Un-calibrated frequency 26.1 MHz Calibrated centre frequency accuracy -1.6% 32.1 +1.6% MHz Without temperature & voltage variation Calibrated centre frequency accuracy -4% 32.1 +5% MHz Including temperature & voltage variation Variation with temperature -0.024, -0.015 +0.009, +0.006 %/°C Variation with VDD2 -0.25 +0.25 +0.5, +0.6 %/V Startup time 2.4 us 19.3.13 Temperature Sensor VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Operating Range -40 - 125 °C Sensor Gain -1.56 -1.66 -1.76 mV/°C Accuracy - - ±7 °C Non-linearity - - 2.0, 3.0 °C Output Voltage 610, 540 840 mV Includes absolute variation due to manufacturing & temp Typical Voltage 730 mV Typical at 3.0V 25°C Resolution 0.666 0.706 0.751 °C/LSB 0 to Vref ADC I/P Range 19.3.14 Non-Volatile Memory VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Flash endurance 10K 100/50K Cycle Program/erase Flash erase time 100 ms One or more sectors Flash programming time 1.0 ms 256 bytes EEPROM endurance 100K 1M/500K °C Program/erase (see 4.4 ) EEPROM erase time 1.8 ms One 64 bytes page EEPROM programming time 1.1 ms Between 1 & 64 bytes Retention time powered unpowered 10 20 Years Flash & EEPROM70 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 19.3.15 Radio Transceiver This JN516x meets all the requirements of the IEEE802.15.4 standard over 2.0 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with NXP’s Module Reference Designs. Compliant with FCC part 15, rules, IC Canada, ETSI ETS 300-328 and Japan ARIB STD-T66 The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN516x failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. Parameter Min Typical Max Notes RF Port Characteristics Type Single Ended Impedance 1 50ohm 2.4-2.5GHz Frequency range 2.400 GHz 2.485GHz ESD levels (pin 17) 2KV (HBM) 500v (CDM) 1) With external matching inductors and assuming PCB layout as in Appendix B.4.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 71 Radio Parameters: 2.0-3.6V, +25ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -92 -95 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 Maximum input signal +10 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 19/34 [27/49] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2/+2 ch) [CW Interferer] 40/44 [54/54] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 48 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 52 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -65 <-70 -60 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 40 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power +0.5 +2.5 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -40 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 3.0 4.5 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, Section 6.5.3.172 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Radio Parameters: 2.0-3.6V, -40ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -93.0 -96.0 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 Maximum input signal +10 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 19/34 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2/+2 ch) [CW Interferer] 40/44 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 47 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 49 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -64 <-70 -60 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 39 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power 0 +2.00 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -40 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 3.0 4.5 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, Section 6.5.3.1© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 73 Radio Parameters: 2.0-3.6V, +85ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -90 -93 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 Maximum input signal +10 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 19/34 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2/+2 ch) [CW Interferer] 40/44 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 49 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 53 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -66 <-70 -61 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 41 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power 0 +2.0 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -40 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 3.0 4.5 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, Section 6.5.3.174 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Radio Parameters: 2.0-3.6V, +125ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -89 -92 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 Maximum input signal +5 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) [CW Interferer] 20/34 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Alternate channel rejection (-2/+2 ch) [CW Interferer] 40/44 [TBC] dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels 49 dBc For 1% PER with wanted signal 3dB above sensitivity. (Note1) Out of band rejection 53 dBc For 1% PER with wanted signal 3dB above sensitivity. All frequencies except wanted/2 which is 8dB lower. (Note1) Spurious emissions (RX) -66 <-70 -61 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 41 dB For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation (Note1) RSSI linearity -4 +4 dB -95 to -10dBm. Available through Hardware API Transmitter Characteristics Transmit power -0.5 +1.5 dBm Output power control range -35 dB In three 12dB steps (Note3) Spurious emissions (TX) -40 <-70 <-70 dBm Measured conducted into 50ohms 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz EVM [Offset] 3.0 4.5 % At maximum output power Transmit Power Spectral Density -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, Section 6.5.3.1© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 75 Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 Section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3: Up to an extra 2.5dB of attenuation is available if required.76 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Appendix A Mechanical and Ordering Information A.1 SOT618-1 HVQFN40 40-pin QFN Package Drawing Figure 45: 40-pin QFN Package Drawings UNIT A max. A1 b c D Dh E Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 6.1 5.9 4.75 4.45 6.1 5.9 4.75 4.45 0.5 4.5 4.5 0.5 0.3 0.1 0.05 0.05 0.1 Table 10: Package Dimensions Plastic or metal protrusions of 0.075 mm maximum per side are not included.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 77 A.2 Footprint Information Information for reflow soldering. All dimensions are given in the table underneath and are in millimeters Solder land Solder land plus solder paste A B C D E F G Figure 46: PCB Decal The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN516x failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. A B C D E F G 0.5 0.45 0.3 0.25 1.53x1.53 4.1x4.1 1.0x0.25 Table 11: Footprint Dimensions78 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 A.3 Ordering Information The standard qualification for the JN516x is extended industrial temperature range: -40ºC to +125ºC, packaged in a 40-pin QFN package. The device is available in two different reel quantities • Tape mounted 4000 devices on a 330mm reel • Tape mounted 1000 devices on a 180mm reel Order Codes: Part Number Ordering Code Description JN5161-001 JN5161/001 JN5161 microcontroller JN5164-001 JN5164/001 JN5164 microcontroller JN5168-001 JN5168/001 JN5168 microcontroller The Standard Supply Multiple (SSM) for Engineering Samples or Prototypes is 50 units with a maximum of 250 units. If the quantity of Engineering Samples or Prototypes ordered is less than a reel quantity, then these will be shipped in tape form only, with no reel and will not be dry packaged in a moisture sensitive environment. The SSM for Production status devices is one reel, all reels are dry packaged in a moisture barrier bag see A.5.3.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 79 A.4 Device Package Marking The diagram below shows the package markings for JN516x. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the specific markings for a JN5168 device, that came from assembly build number 01 and was manufactured week 25 of 2011. J N 5168 A XXXXXX XXXXFF XXXYWWXX J N 5168 A RUL 280 0 0 Y U 0 1 qSD 125 -X NXP NXP Figure 47: Device Package Marking Legend: JN Family part code XXXX 4 digit part number FF 2 digit assembly build number Y 1 digit year number WW 2 digit week number Ordering Code Part Marking JN5161/001 JN5161A JN5164/001 JN5164A JN5168/001 JN5168A80 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientation of the 40QFN package in the tape is as shown in Figure 48. Figure 48: Tape and Reel Orientation Figure 49 shows the detailed dimensions of the tape used for 6x6mm 40QFN devices. Reference Dimensions (mm) Ao 6.30 ±0.10 Bo 6.30 ±0.10 Ko 1.10 ±0.10 F 7.500 ±0.10 P1 12.0 ±0.10 W 16.00 +0.30/-0.3 (I) Measured from centreline of sprocket hole to centreline of pocket (II) Cumulative tolerance of 10 sprocket holes is ±0.20mm (III) Measured from centreline of sprocket hole to centreline of pocket (IV) Other material available Figure 49: Tape Dimensions© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 81 A.5.2 Reel Information: 180mm Reel Surface Resistivity Between 1x1010 – 1x1012 Ohms Square Material High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space. Figure 50: Reel Dimensions82 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 A.5.3 Reel Information: 330mm Reel Surface Resistivity Between 10e9 – 10e11 Ohms Square Material High Impact Polystyrene with Antistatic Additive All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 3 window design to allow adequate labelling space. Figure 51: 330mm Reel Dimensions A.5.4 Dry Pack Requirement for Moisture Sensitive Material Moisture sensitive material, as classified by JEDEC standard J-STD-033, must be dry packed. The 40 lead QFN package is MSL2A/260° C, and is dried before sealing in a moisture barrier bag (MBB) with desiccant bag weighing at 67.5 grams of activated clay and a humidity indicator card (HIC) meeting MIL-L-8835 specification. The MBB has a moisture-sensitivity caution label to indicate the moisture-sensitive classification of the enclosed devices.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 83 Appendix B Development Support B.1 Crystal Oscillators This Section covers some of the general background to crystal oscillators, to help the user make informed decisions concerning the choice of crystal and the associated capacitors. B.1.1 Crystal Equivalent Circuit Cs Lm Rm Cm C1 C2 Where Cm is the motional capacitance Lm is the motional inductance. This together with Cm defines the oscillation frequency (series) Rm is the equivalent series resistance ( ESR ). CS is the shunt or package capacitance and this is a parasitic B.1.2 Crystal Load Capacitance The crystal load capacitance is the total capacitance seen at the crystal pins, from all sources. As the load capacitance (CL) affects the oscillation frequency by a process known as ‘pulling’, crystal manufacturers specify the frequency for a given load capacitance only. A typical pulling coefficient is 15ppm/pF, to put this into context the maximum frequency error in the IEEE802.15.4 specification is +/-40ppm for the transmitted signal. Therefore, it is important for resonance at 32MHz exactly, that the specified load capacitance is provided. The load capacitance can be calculated using: CL = 1 2 1 2 T T T T C C C C + × Total capacitance CT1 = C1 + C1P + C1in Where C1 is the capacitor component C1P is the PCB parasitic capacitance. With the recommended layout this is about 1.6pF C1in is the on-chip parasitic capacitance and is about 1.4pF typically. Similarly for CT 2 Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF84 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 B.1.3 Crystal ESR and Required Transconductance The resistor in the crystal equivalent circuit represents the energy lost. To maintain oscillation, power must be supplied by the amplifier, but how much? Firstly, the Pi connected capacitors C1 and C2 with CS from the crystal, apply an impedance transformation to Rm, when viewed from the amplifier. This new value is given by: 2 ˆ + = L S L m m C C C R R The amplifier is a transconductance amplifier, which takes a voltage and produces an output current. The amplifier together with the capacitors C1 and C2, form a circuit, which provides a negative resistance, when viewed from the crystal. The value of which is given by: 2 1× 2 ×ω = T T m NEG C C g R Where gm is the transconductance ω is the frequency in rad/s Derivations of these formulas can be easily found in textbooks. In order to give quick and reliable oscillator start-up, a common rule of thumb is to set the amplifier negative resistance to be a minimum of 4 times the effective crystal resistance. This gives 2 T1× T 2 ×ω m C C g ≥ 2 4 + L S L m C C C R This can be used to give an equation for the required transconductance. 1 2 2 1 2 1 2 2 4 [ ( ) ] T T m S T T T T m C C R C C C C C g × × + + × ≥ ω Example: Using typical 32MHz crystal parameters of Rm =40Ω, CS =1pF and CT1 =CT 2 =18pF ( for a load capacitance of 9pF), the equation above gives the required transconductance ( gm ) as 2.59mA/V. The JN516x has a typical value for transconductance of 4.4mA/V The example and equation illustrate the trade-off that exists between the load capacitance and crystal ESR. For example, a crystal with a higher load capacitance can be used, but the value of max. ESR that can be tolerated is reduced. Also note, that the circuit sensitivity to external capacitance [ C1 , C2 ] is a square law. Meeting the criteria for start-up is only one aspect of the way these parameters affect performance, they also affect the time taken during start-up to reach a given, (or full), amplitude. Unfortunately, there is no simple mathematical model for this, but the trend is the same. Therefore, both a larger load capacitance and larger crystal ESR will give a longer start-up time, which has the disadvantages of reduced battery life and increased latency. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 85 B.2 32MHz Oscillator The JN516x contains the necessary on-chip components to build a 32 MHz reference oscillator with the addition of an external crystal resonator, two tuning capacitors. The schematic of these components are shown in Figure 52. The two capacitors, C1 and C2, will typically be 15pF ±5% and use a COG dielectric. For a detailed specification of the crystal required and factors affecting C1 and C2 see Appendix B.1. As with all crystal oscillators the PCB layout is especially important, both to keep parasitic capacitors to a minimum and to reduce the possibility of PCB noise being coupled into the oscillator. XTALOUT C1 C2 XTALIN R1 JN516x Figure 52: Crystal Oscillator Connections The clock generated by this oscillator provides the reference for most of the JN516x subsystems, including the transceiver, processor, memory and digital and analogue peripherals. 32MHz Crystal Requirements Parameter Min Typ Max Notes Crystal Frequency 32MHz Crystal Tolerance 40ppm Including temperature and ageing Crystal ESR Range (Rm) 10Ω 60Ω See below for more details Crystal Load Capacitance Range (CL) 6pF 9pF 12pF See below for more details Not all Combinations of Crystal Load Capacitance and ESR are Valid Recommended Crystal Load Capacitance 9pF and max ESR 40 Ω External Capacitors (C1 & C2) For recommended Crystal 15pF CL = 9pF, total external capacitance needs to be 2*CL. , allowing for stray capacitance from chip, package and PCB 86 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 As is stated above, not all combinations of crystal load capacitance and ESR are valid, and as explained in Appendix B.1.3 there is a trade-off that exists between the load capacitance and crystal ESR to achieve reliable performance. For this reason, we recommend that for a 9pF load capacitance crystals be specified with a maximum ESR of 40 ohms. For lower load capacitances the recommended maximum ESR rises, for example, CL=7pF the max ESR is 61 ohms. For the lower cost crystals in the large HC49 package, a load capacitance of 9 or 10pF is widely available and the max ESR of 30 ohms specified by many manufacturers is acceptable. Also available in this package style, are crystals with a load capacitance of 12pF, but in this case the max ESR required is 25 ohms or better. Below is measurement data showing the variation of the crystal oscillator amplifier transconductance with temperature and supply voltage, notice how small the variation is. Circuit techniques have been used to apply compensation, such that the user need only design for nominal conditions. 4.15 4.20 4.25 4.30 4.35 -40 -20 0 20 40 60 80 100 120 Transconductance (mA/V) Temperature (C) 32MHz Crystal Oscillator 4.27 4.28 4.29 4.3 4.31 4.32 4.33 4.34 4.35 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Transconductance (mA/V) Supply Voltage (VDD) 32MHz Crystal Oscillator © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 87 B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN516x contains the necessary on-chip components to build an optional 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between XTAL32K_IN and XTAL32K_OUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. The schematic of these components are shown in Figure 53. The two capacitors, C1 and C2, will typically be in the range 10 to 22pF ±5% and use a COG dielectric. As with all crystal oscillators the PCB layout is especially important, both to keep parasitic capacitors to a minimum and to reduce the possibility of PCB noise being coupled into the oscillator. 32KXTALIN 32KXTALOUT JN516x Figure 53: 32kHz Crystal Oscillator Connections The electrical specification of the oscillator can be found in 19.3.10. The oscillator cell is flexible and can operate with a range of commonly available 32kHz crystals with load capacitances from 6 to 12.5p, and ESR up to 80KΩ. It achieves this by using automatic gain control (AGC), which senses the signal swing. As explained in Appendix B.1.3 there is a trade-off that exists between the load capacitance and crystal ESR to achieve reliable performance. The use of an AGC function allows a wider range of crystal load capacitors and ESR’s to be accommodated than would otherwise be possible. However, this benefit does mean the supply current varies with the supply voltage (VDD), value of the total capacitance at each pin, and the crystal ESR. This is described in the table and graphs below. 32kHz Crystal Requirements Parameter Min Typ Max Notes Crystal Frequency 32kHz Supply Current 1.4µA Vdd=3v, temp=25 C, load cap =9pF, Rm=25K Supply Current Temp. Coeff. 0.1%/C Vdd=3v Crystal ESR Range (Rm) 10KΩ 25KΩ 80KΩ See below for more details Crystal Load Capacitance Range (CL) 6pF 9pF 12.5pF See below for more details Not all Combinations of Crystal Load Capacitance and ESR are Valid 88 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Three examples of typical crystals are given, each with the value of external capacitors to use, plus the likely supply current and start-up time that can be expected. Also given is the maximum recommended ESR based on the start-up criteria given in Appendix B.1.3. The values of the external capacitors can be calculated using the equation in Appendix B.1.2 . Load Capacitance Ext Capacitors Current Start-up Time Max ESR 9pF 15pF 1.4µA 0.5sec 70KΩ 6pF 9pF 1.1µA 0.4sec 80KΩ 12.5pF 22pF 2.2µA 1.0sec 35KΩ Below is measurement data showing the variation of the crystal oscillator supply current with voltage and with crystal ESR, for two load capacitances. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Current (uA) Supply Voltage (VDD) 32kHz Crystal Oscillator 0.6 0.8 1 1.2 1.4 1.6 10 20 30 40 50 60 70 80 Normalised Current (IDD) Crystal ESR (K ohm) 32KHz Crystal Oscillator Current 9pF 12.5pF© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 89 B.4 JN516x Module Reference Designs For customers wishing to integrate the JN516x device directly into their system, NXP provide a range of Module Reference Designs, covering standard, medium and high-power modules fitted with different Antennae To ensure the correct performance, it is strongly recommended that where possible the design details provided by the reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions, track layouts etc. In order to minimise all risks, it is recommended that the entire layout of the appropriate reference module, if possible, be replicated in the end design. For full details, see [5]. Please contact technical support. B.4.1 Schematic Diagram A schematic diagram of the JN516x PCB antenna reference module is shown in figure 53. Details of component values and PCB layout constraints can be found in Table 12. 1 40 39 38 37 36 35 34 33 32 31 VSSA 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 COMP1P COMP1M RESETN XTAL_OUT XTAL_IN VB_SYNTH VCOTUNE (NC) VB_VCO VDD1 IBIAS VREF VB_RF2 RF_IN VB_RF ADC1 SPISEL1 SPISEL2 DIO2 DIO3 DO0 VSS1 DO1 DIO18 DIO19 VB_RAM CTS0 RTS0 TXD0 RXD0 VDD2 SIF_D VSS2 SIF_CLK DIO13 DIO12 VB_DIG DIO11 TIM0OUT TIM0CAP TIM0CK_GT C7: 100nF 2-wire Serial Port Timer0 C16: 100nF UART0/JTAG C6: 100nF SPI Select Analogue IO C1: 47pF C3: 100nF L1: 5.1nH L2: 3.9nH VB_RF R1: 43kΩ To coaxial socket or integrated antenna C20: 100nF C13: 10µF C14: 100nF VDD C2: 10nF C15: 100nF C10: 15pF C11: 15pF Y1 Analogue IO C4: 47pF Figure 54 JN516x PCB Antenna Module Reference Design 90 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Component Designator Value/Type Function PCB Layout Constraints C13 10µF Power source decoupling C14 100nF Analogue Power decoupling Adjacent to U1 pin 9 C16 100nF Digital power decoupling Adjacent to U1 pin 30 C15 100nF VB Synth decoupling Less than 5mm from U1 pin 6 C2 10nF VB VCO decoupling Less than 5mm from U1 pin 8 C3 100nF VB RF decoupling Less than 5mm from U1 pin 12 and U1 pin 14 C4 47pF VB RF decoupling Less than 5mm from U1 pin 12 and U1 pin 14 C6 100nF VB RAM decoupling Less than 5mm from U1 pin 25 C7 100nF VB Dig decoupling Less than 5mm from U1 pin 35 R1 43k Current Bias Resistor Less than 5mm from U1 pin 10 C20 100nF Vref decoupling (optional) Less than 5mm from U1 pin 11 Y1 32MHz Crystal (AEL X32M000000S039 or Epson Toyocom X1E000021016700) (CL = 9pF, Max ESR 40R) C10 15pF +/-5% COG Crystal Load Capacitor Adjacent to pin 4 and Y1 pin 1 C11 15pF +/-5% COG Crystal Load Capacitor Adjacent to pin 5 and Y1 pin 3 C1 47pF AC Coupling Phycomp 2238-869-15479 Must be copied directly from the reference design. L1 5.1nH RF Matching Inductor MuRata LQP15MN5N1B02 L2 3.9nH Load Inductor MuRata LQP15MN3N9B02 Table 12: JN516x Printed Antenna Reference Module Components and PCB Layout Constraints Note1: For extended temperature operation please contact technical support. The paddle should be connected directly to ground. Any pads that require connection to ground should do so by connecting directly to the paddle.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 91 B.4.2 PCB Design and Reflow Profile PCB and land pattern designs are key to the reliability of any electronic circuit design. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) defines a number of standards for electronic devices. One of these is the "Surface Mount Design and Land Pattern Standard" IPC-SM-782 [3], commonly referred to as “IPC782". This specification defines the physical packaging characteristics and land patterns for a range of surface mounted devices. IPC782 is also a useful reference document for general surface mount design techniques, containing sections on design requirements, reliability and testability. NXP strongly recommends that this be referred to when designing the PCB. NXP also provide application note AN10366, “HVQFN application information” [6], which describes the reflow soldering process. The suggested reflow profile, from that application note, is shown in Figure 55. The specific paste manufacturers guidelines on peak flow temperature, soak times, time above liquids and ramp rates should also be referenced. Figure 55: Recommended Reflow Profile for Lead-free Solder Paste (SNAgCu) or PPF Lead Frame B.4.3 Moisture Sensitivity Level (MSL) If there is moisture trapped inside a package, and the package is exposed to a reflow temperature profile, the moisture may turn into steam, which expands rapidly. This may cause damage to the inside of the package (delamination), and it may result in a cracked semiconductor package body (the popcorn effect). A package’s MSL depends on the package characteristics and on the temperature it is exposed to during reflow soldering. This is explained in more detail in [7]. Depending on the damage after this test, an MSL of 1 (not sensitive to moisture) to 6 (very sensitive to moisture) is attached to the semiconductor package.92 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Related Documents [1] IEEE Std 802.15.4-2006 IEEE Standard for Information Technology – Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs). [2] JN-AN-1186 JN516x Temperature Dependent Operating Guidelines [3] IPC-SM-782 Surface Mount Design and Land Pattern Standard [4] JN-UG-3087 JN516x Integrated Peripherals API User Guide [5] JN-RD-6038 Module Reference Design [6] http://ics.nxp.com/support/documents/logic/pdf/an10366.pdf [7] http://www.nxp.com/documents/application_note/AN10365.pdf [8] JN-AN-1003 Boot Loader Operation [9] JN-UG-3007 Flash Programmer User Guide [10] JN-UG-3068 Time-of-flight API User Guide [11] JN-AN-1143 Time-of-flight [12] JN-UG-3075-JenOS User Guide RoHS Compliance JN516x devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS) and of the China RoHS (SJ/T11363 – 2006) requirements which came into force on 1st March 2007. Status Information The status of this Data Sheet is. Production NXP Low Power RF products progress according to the following format: Advance The Data Sheet shows the specification of a product in planning or in development. The functionality and electrical performance specifications are target values of the design and may be used as a guide to the final specification. NXP reserves the right to make changes to the product specification at anytime without notice. Preliminary The Data Sheet shows the specification of a product that is commercially available, but is not yet fully qualified. The functionality of the product is final. The electrical performance specifications are target values and may used as a guide to the final specification. NXP reserves the right to make changes to the product specification at anytime without notice. Production This is the production Data Sheet for the product. All functional and electrical performance specifications, where included, including min and max values are derived from detailed product characterization. This Data Sheet supersedes all previous document versions. NXP reserves the right to make changes to the product specification at anytime without notice.© NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 93 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet All products are sold subject to NXP Semiconductors’ terms and conditions of sale, supplied at the time of order acknowledgment and published at http://www.nxp.com/profile/terms. Trademarks All trademarks are the property of their respective owners. “JenNet” and “JenNet-IP” are trademarks of NXP B.V.. Version Control Version Notes 1.0 07-01-13 First public version, released as Production 1.1 14-01-13 Minor corrections made 1.2 25-04-13 Additional features included and more information on non-volatile memory 1.3 12-06-13 Minor correction to front page and format of PCB decal diagram94 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Contact Details NXP Laboratories UK Ltd Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 For the contact details of your local NXP office or distributor, refer to the NXP web site: www.nxp.com 1. General description The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x operates at up to 120 MHz CPU frequency. The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more. The analog peripherals include one eight-channel 12-bit ADC and a 10-bit DAC. The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx and LPC23xx. For additional documentation, see Section 18 “References”. 2. Features and benefits Functional replacement for the LPC23xx and LPC24xx family devices. System: ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory Protection Unit (MPU) supporting eight regions is included. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). LPC178x/7x 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 5 — 9 September 2014 Product data sheetLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 2 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, USB, Ethernet, and the General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy. Cortex-M3 system tick timer, including an external clock input option. Standard JTAG test/debug interface as well as Serial Wire Debug and Serial WireTrace Port options. Embedded Trace Macrocell (ETM) module supports real-time trace. Boundary scan for simplified board testing. Non-maskable Interrupt (NMI) input. Memory: Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash. Up to 96 kB on-chip SRAM includes: 64 kB of main SRAM on the CPU with local code/data bus for high-performance CPU access. Two 16 kB peripheral SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for DMA memory as well as for general purpose instruction and data storage. Up to 4032 byte on-chip EEPROM. LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays. Dedicated DMA controller. Selectable display resolution (up to 1024 768 pixels). Supports up to 24-bit true-color mode. External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM with an SDRAM clock of up to 80 MHz. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers. Serial interfaces: Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and associated DMA controller. Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one UART (USART4) supports IrDA, synchronous mode, and a smart card mode conforming to ISO7816-3. Three SSP controllers with FIFO and multi-protocol capabilities. The SSP controllers can be used with the GPDMA.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 3 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Three enhanced I2C-bus interfaces, one with a true open-drain output supporting the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. I 2S-bus (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. CAN controller with two channels. Digital peripherals: SD/MMC memory card interface. Up to 165 General Purpose I/O (GPIO) pins depending on the packaging with configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources. Four general purpose timers/counters with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. Quadrature encoder interface that can monitor one external quadrature encoder. Two standard PWM/timer blocks with external count input option. One motor control PWM with support for three-phase motor control. Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode. Event Recorder that can capture the clock value when an event occurs on any of three inputs. The event identification and the time it occurred are stored in registers. The Event Recorder is located in the RTC power domain and can therefore operate as long as there is RTC power. Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal oscillator, watchdog warning interrupt, and safety features. CRC Engine block can calculate a CRC on supplied data using one of three standard polynomials. The CRC engine can be used in conjunction with the DMA controller to generate a CRC without CPU involvement in the data transfer. Analog peripherals: 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and GPDMA support. Power control: Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 4 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2 pin interrupt, and NMI). Brownout detect with separate threshold for interrupt and forced reset. On-chip Power-On Reset (POR). Clock generation: Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or the watchdog timer clock. On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be used as a system clock. An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator or the internal RC oscillator. A second, dedicated PLL may be used for USB interface in order to allow added flexibility for the Main PLL settings. Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions. Unique device serial number for identification purposes. Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C. Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package. 3. Applications Communications: Point-of-sale terminals, web servers, multi-protocol bridges Industrial/Medical: Automation controllers, application control, robotics control, HVAC, PLC, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom Consumer/Appliance: Audio, MP3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment Automotive: After-market, car alarms, GPS/fleet monitorsLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 5 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1788 LPC1788FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 ´ 15 ´ 0.7 mm SOT950-1 LPC1788FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3 LPC1788FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1 LPC1787 LPC1787FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1786 LPC1786FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1785 LPC1785FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1778 LPC1778FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1778FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 ´ 15 ´ 0.7 mm SOT950-1 LPC1778FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3 LPC1778FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1 LPC1777 LPC1777FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1776 LPC1776FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1776FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3 LPC1774 LPC1774FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC1774FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 6 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller [1] Maximum data bus width of the External Memory Controller (EMC) depends on package size. Smaller widths may be used. [2] USART4 not available. Table 2. LPC178x/7x ordering options All parts include two CAN channels, three SSP interfaces, three I2C interfaces, one I2S interface, DAC, and an 8-channel 12-bit ADC. Type number Flash (kB) Main SRAM (kB) Peripheral SRAM (kB) Total SRAM (kB) EEPROM (byte) Ethernet USB UART EMC bus width (bit) [1] LCD QEI SD/ MMC LPC178x LPC1788FBD208 512 64 16 2 96 4032 Y H/O/D 5 32 Y Y Y LPC1788FET208 512 64 16 2 96 4032 Y H/O/D 5 32 Y Y Y LPC1788FET180 512 64 16 2 96 4032 Y H/O/D 5 16 Y Y Y LPC1788FBD144 512 64 16 2 96 4032 Y H/O/D 5 8 Y Y Y LPC1787FBD208 512 64 16 2 96 4032 N H/O/D 5 32 Y Y Y LPC1786FBD208 256 64 16 80 4032 Y H/O/D 5 32 Y Y Y LPC1785FBD208 256 64 16 80 4032 N H/O/D 5 32 Y N Y LPC177x LPC1778FBD208 512 64 16 2 96 4032 Y H/O/D 5 32 N Y Y LPC1778FET208 512 64 16 2 96 4032 Y H/O/D 5 32 N Y Y LPC1778FET180 512 64 16 2 96 4032 Y H/O/D 5 16 N Y Y LPC1778FBD144 512 64 16 2 96 4032 Y H/O/D 5 8 N Y Y LPC1777FBD208 512 64 16 2 96 4032 N H/O/D 5 32 N Y Y LPC1776FBD208 256 64 16 80 4032 Y H/O/D 5 32 N Y Y LPC1776FET180 256 64 16 80 4032 Y H/O/D 5 16 N Y Y LPC1774FBD208 128 32 8 40 2048 N D 5 32 N N N LPC1774FBD144 128 32 8 40 2048 N D 4[2] 8 N N NLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 7 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 5. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 96/80/40 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128/64 kB GPDMA CONTROLLER I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 4032 B/ 2048 B EEPROM CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls JTAG interface debug port SSP0/2 USART4(1) UART2/3 SYSTEM CONTROL SSP1 UART0/1 I 2C0/1 CAN 0/1 TIMER 0/1 WINDOWED WDT 12-bit ADC PWM0/1 PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS EVENT RECORDER 32 kHz OSCILLATOR APB slave group 1 APB slave group 0 RTC POWER DOMAIN LPC178x/7x master ETHERNET(1) master USB DEVICE/ HOST(1)/OTG(1) master 002aaf528 slave slave CRC slave slave slave slave EMC ROM slave slave LCD(1) slave MULTILAYER AHB MATRIX I 2C2 TIMER2/3 DAC I 2S QUADRATURE ENCODER(1) MOTOR CONTROL PWM MPU SD/MMC(1) = connected to GPDMALPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 8 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 6.1 Pinning Fig 2. Pin configuration (LQFP208) Fig 3. Pin configuration (TFBGA208) LPC178x/7xFBD208 156 53 104 208 157 105 1 52 002aaf518 002aaf529 LPC178x/7x Transparent top view ball A1 index area U T R P N M K H L J G F E D C A B 2 4 6 8 10 12 13 14 15 17 16 1 3 5 7 9 11LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 9 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 6.2 Pin description I/O pins on the LPC178x/7x are 5 V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5 V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin (VREFP). All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 in the order defined by the FUNC bits of the corresponding IOCON register up to the highest used function number. Each port pin can support up to eight multiplexed functions. IOCON register FUNC values which are reserved are noted as ‘R’ in the pin configuration table. Fig 4. Pin configuration (TFBGA180) Fig 5. Pin configuration (LQFP144) 002aaf519 LPC178x/7x 1 3 5 7 9 11 2 4 6 8 10 12 13 14 ball A1 index area P N M L K J G E H F D C B A Transparent top view LPC178x/7x 108 37 72 144 109 73 1 36 002aaf520LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 10 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0[0] 94 U15 M10 66 [3] I; PU I/O P0[0] — General purpose digital input/output pin. I CAN_RD1 — CAN1 receiver input. O U3_TXD — Transmitter output for UART3. I/O I2C1_SDA — I 2C1 data input/output (this pin does not use a specialized I2C pad). O U0_TXD — Transmitter output for UART0. P0[1] 96 T14 N11 67 [3] I; PU I/O P0[1] — General purpose digital input/output pin. O CAN_TD1 — CAN1 transmitter output. I U3_RXD — Receiver input for UART3. I/O I2C1_SCL — I 2C1 clock input/output (this pin does not use a specialized I2C pad). I U0_RXD — Receiver input for UART0. P0[2] 202 C4 D5 141 [3] I; PU I/O P0[2] — General purpose digital input/output pin. O U0_TXD — Transmitter output for UART0. O U3_TXD — Transmitter output for UART3. P0[3] 204 D6 A3 142 [3] I; PU I/O P0[3] — General purpose digital input/output pin. I U0_RXD — Receiver input for UART0. I U3_RXD — Receiver input for UART3. P0[4] 168 B12 A11 116 [3] I; PU I/O P0[4] — General purpose digital input/output pin. I/O I2S_RX_SCK — I 2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. I CAN_RD2 — CAN2 receiver input. I T2_CAP0 — Capture input for Timer 2, channel 0. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[0] — LCD data.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 11 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P0[5] 166 C12 B11 115 [3] I; PU I/O P0[5] — General purpose digital input/output pin. I/O I2S_RX_WS — I 2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. O CAN_TD2 — CAN2 transmitter output. I T2_CAP1 — Capture input for Timer 2, channel 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[1] — LCD data. P0[6] 164 D13 D11 113 [3] I; PU I/O P0[6] — General purpose digital input/output pin. I/O I2S_RX_SDA — I 2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. I/O SSP1_SSEL — Slave Select for SSP1. O T2_MAT0 — Match output for Timer 2, channel 0. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. - R — Function reserved. - R — Function reserved. O LCD_VD[8] — LCD data. P0[7] 162 C13 B12 112 [4] I; IA I/O P0[7] — General purpose digital input/output pin. I/O I2S_TX_SCK — I 2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. I/O SSP1_SCK — Serial Clock for SSP1. O T2_MAT1 — Match output for Timer 2, channel 1. I RTC_EV0 — Event input 0 to Event Monitor/Recorder. - R — Function reserved. - R — Function reserved. O LCD_VD[9] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 12 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P0[8] 160 A15 C12 111 [4] I; IA I/O P0[8] — General purpose digital input/output pin. I/O I2S_TX_WS — I 2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. I/O SSP1_MISO — Master In Slave Out for SSP1. O T2_MAT2 — Match output for Timer 2, channel 2. I RTC_EV1 — Event input 1 to Event Monitor/Recorder. - R — Function reserved. - R — Function reserved. O LCD_VD[16] — LCD data. P0[9] 158 C14 A13 109 [4] I; IA I/O P0[9] — General purpose digital input/output pin. I/O I2S_TX_SDA — I 2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. I/O SSP1_MOSI — Master Out Slave In for SSP1. O T2_MAT3 — Match output for Timer 2, channel 3. I RTC_EV2 — Event input 2 to Event Monitor/Recorder. - R — Function reserved. - R — Function reserved. O LCD_VD[17] — LCD data. P0[10] 98 T15 L10 69 [3] I; PU I/O P0[10] — General purpose digital input/output pin. O U2_TXD — Transmitter output for UART2. I/O I2C2_SDA — I 2C2 data input/output (this pin does not use a specialized I2C pad). O T3_MAT0 — Match output for Timer 3, channel 0. P0[11] 100 R14 P12 70 [3] I; PU I/O P0[11] — General purpose digital input/output pin. I U2_RXD — Receiver input for UART2. I/O I2C2_SCL — I 2C2 clock input/output (this pin does not use a specialized I2C pad). O T3_MAT1 — Match output for Timer 3, channel 1. P0[12] 41 R1 J4 29 [5] I; PU I/O P0[12] — General purpose digital input/output pin. O USB_PPWR2 — Port Power enable signal for USB port 2. I/O SSP1_MISO — Master In Slave Out for SSP1. I ADC0_IN[6] — A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 13 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P0[13] 45 R2 J5 32 [5] I; PU I/O P0[13] — General purpose digital input/output pin. O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. I/O SSP1_MOSI — Master Out Slave In for SSP1. I ADC0_IN[7] — A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled. P0[14] 69 T7 M5 48 [3] I; PU I/O P0[14] — General purpose digital input/output pin. O USB_HSTEN2 — Host Enabled status for USB port 2. I/O SSP1_SSEL — Slave Select for SSP1. O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. P0[15] 128 J16 H13 89 [3] I; PU I/O P0[15] — General purpose digital input/output pin. O U1_TXD — Transmitter output for UART1. I/O SSP0_SCK — Serial clock for SSP0. P0[16] 130 J14 H14 90 [3] I; PU I/O P0[16] — General purpose digital input/output pin. I U1_RXD — Receiver input for UART1. I/O SSP0_SSEL — Slave Select for SSP0. P0[17] 126 K17 J12 87 [3] I; PU I/O P0[17] — General purpose digital input/output pin. I U1_CTS — Clear to Send input for UART1. I/O SSP0_MISO — Master In Slave Out for SSP0. P0[18] 124 K15 J13 86 [3] I; PU I/O P0[18] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1. I/O SSP0_MOSI — Master Out Slave In for SSP0. P0[19] 122 L17 J10 85 [3] I; PU I/O P0[19] — General purpose digital input/output pin. I U1_DSR — Data Set Ready input for UART1. O SD_CLK — Clock output line for SD card interface. I/O I2C1_SDA — I 2C1 data input/output (this pin does not use a specialized I2C pad). Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 14 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P0[20] 120 M17 K14 83 [3] I; PU I/O P0[20] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O SD_CMD — Command line for SD card interface. I/O I2C1_SCL — I 2C1 clock input/output (this pin does not use a specialized I2C pad). P0[21] 118 M16 K11 82 [3] I; PU I/O P0[21] — General purpose digital input/output pin. I U1_RI — Ring Indicator input for UART1. O SD_PWR — Power Supply Enable for external SD card power supply. O U4_OE — RS-485/EIA-485 output enable signal for UART4. I CAN_RD1 — CAN1 receiver input. I/O U4_SCLK — USART 4 clock input or output in synchronous mode. P0[22] 116 N17 L14 80 [6] I; PU I/O P0[22] — General purpose digital input/output pin. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O SD_DAT[0] — Data line 0 for SD card interface. O U4_TXD — Transmitter output for USART4 (input/output in smart card mode). O CAN_TD1 — CAN1 transmitter output. P0[23] 18 H1 F5 13 [5] I; PU I/O P0[23] — General purpose digital input/output pin. I ADC0_IN[0] — A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. I T3_CAP0 — Capture input for Timer 3, channel 0. P0[24] 16 G2 E1 11 [5] I; PU I/O P0[24] — General purpose digital input/output pin. I ADC0_IN[1] — A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. I T3_CAP1 — Capture input for Timer 3, channel 1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 15 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P0[25] 14 F1 E4 10 [5] I; PU I/O P0[25] — General purpose digital input/output pin. I ADC0_IN[2] — A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. O U3_TXD — Transmitter output for UART3. P0[26] 12 E1 D1 8 [7] I; PU I/O P0[26] — General purpose digital input/output pin. I ADC0_IN[3] — A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled. O DAC_OUT — D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled. I U3_RXD — Receiver input for UART3. P0[27] 50 T1 L3 35 [8] I I/O P0[27] — General purpose digital input/output pin. I/O I2C0_SDA — I 2C0 data input/output (this pin uses a specialized I2C pad). I/O USB_SDA1 — I2C serial data for communication with an external USB transceiver. P0[28] 48 R3 M1 34 [8] I I/O P0[28] — General purpose digital input/output pin. I/O I2C0_SCL — I 2C0 clock input/output (this pin uses a specialized I2C pad). I/O USB_SCL1 — I2C serial clock for communication with an external USB transceiver. P0[29] 61 U4 K5 42 [9] I I/O P0[29] — General purpose digital input/output pin. I/O USB_D+1 — USB port 1 bidirectional D+ line. I EINT0 — External interrupt 0 input. P0[30] 62 R6 N4 43 [9] I I/O P0[30] — General purpose digital input/output pin. I/O USB_D1 — USB port 1 bidirectional D line. I EINT1 — External interrupt 1 input. P0[31] 51 T2 N1 36 [9] I I/O P0[31] — General purpose digital input/output pin. I/O USB_D+2 — USB port 2 bidirectional D+ line. P1[0] to P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block P1[0] 196 A3 B5 136 [3] I; PU I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). - R — Function reserved. I T3_CAP1 — Capture input for Timer 3, channel 1. I/O SSP2_SCK — Serial clock for SSP2. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 16 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P1[1] 194 B5 A5 135 [3] I; PU I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). - R — Function reserved. O T3_MAT3 — Match output for Timer 3, channel 3. I/O SSP2_MOSI — Master Out Slave In for SSP2. P1[2] 185 D9 B7 - [3] I; PU I/O P1[2] — General purpose digital input/output pin. O ENET_TXD2 — Ethernet transmit data 2 (MII interface). O SD_CLK — Clock output line for SD card interface. O PWM0[1] — Pulse Width Modulator 0, output 1. P1[3] 177 A10 A9 - [3] I; PU I/O P1[3] — General purpose digital input/output pin. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O SD_CMD — Command line for SD card interface. O PWM0[2] — Pulse Width Modulator 0, output 2. P1[4] 192 A5 C6 133 [3] I; PU I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface). - R — Function reserved. O T3_MAT2 — Match output for Timer 3, channel 2. I/O SSP2_MISO — Master In Slave Out for SSP2. P1[5] 156 A17 B13 - [3] I; PU I/O P1[5] — General purpose digital input/output pin. O ENET_TX_ER — Ethernet Transmit Error (MII interface). O SD_PWR — Power Supply Enable for external SD card power supply. O PWM0[3] — Pulse Width Modulator 0, output 3. P1[6] 171 B11 B10 - [3] I; PU I/O P1[6] — General purpose digital input/output pin. I ENET_TX_CLK — Ethernet Transmit Clock (MII interface). I/O SD_DAT[0] — Data line 0 for SD card interface. O PWM0[4] — Pulse Width Modulator 0, output 4. P1[7] 153 D14 C13 - [3] I; PU I/O P1[7] — General purpose digital input/output pin. I ENET_COL — Ethernet Collision detect (MII interface). I/O SD_DAT[1] — Data line 1 for SD card interface. O PWM0[5] — Pulse Width Modulator 0, output 5. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 17 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P1[8] 190 C7 B6 132 [3] I; PU I/O P1[8] — General purpose digital input/output pin. I ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). - R — Function reserved. O T3_MAT1 — Match output for Timer 3, channel 1. I/O SSP2_SSEL — Slave Select for SSP2. P1[9] 188 A6 D7 131 [3] I; PU I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). - R — Function reserved. O T3_MAT0 — Match output for Timer 3, channel 0. P1[10] 186 C8 A7 129 [3] I; PU I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). - R — Function reserved. I T3_CAP0 — Capture input for Timer 3, channel 0. P1[11] 163 A14 A12 - [3] I; PU I/O P1[11] — General purpose digital input/output pin. I ENET_RXD2 — Ethernet Receive Data 2 (MII interface). I/O SD_DAT[2] — Data line 2 for SD card interface. O PWM0[6] — Pulse Width Modulator 0, output 6. P1[12] 157 A16 A14 - [3] I; PU I/O P1[12] — General purpose digital input/output pin. I ENET_RXD3 — Ethernet Receive Data (MII interface). I/O SD_DAT[3] — Data line 3 for SD card interface. I PWM0_CAP0 — Capture input for PWM0, channel 0. P1[13] 147 D16 D14 - [3] I; PU I/O P1[13] — General purpose digital input/output pin. I ENET_RX_DV — Ethernet Receive Data Valid (MII interface). P1[14] 184 A7 D8 128 [3] I; PU I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error (RMII/MII interface). - R — Function reserved. I T2_CAP0 — Capture input for Timer 2, channel 0. P1[15] 182 A8 A8 126 [3] I; PU I/O P1[15] — General purpose digital input/output pin. I ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). - R — Function reserved. I/O I2C2_SDA — I 2C2 data input/output (this pin does not use a specialized I2C pad). Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 18 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P1[16] 180 D10 B8 125 [3] I; PU I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock. O I2S_TX_MCLK — I2S transmit master clock. P1[17] 178 A9 C9 123 [3] I; PU I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. O I2S_RX_MCLK — I2S receive master clock. P1[18] 66 P7 L5 46 [3] I; PU I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED1 — It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I T1_CAP0 — Capture input for Timer 1, channel 0. - R — Function reserved. I/O SSP1_MISO — Master In Slave Out for SSP1. P1[19] 68 U6 P5 47 [3] I; PU I/O P1[19] — General purpose digital input/output pin. O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). O USB_PPWR1 — Port Power enable signal for USB port 1. I T1_CAP1 — Capture input for Timer 1, channel 1. O MC_0A — Motor control PWM channel 0, output A. I/O SSP1_SCK — Serial clock for SSP1. O U2_OE — RS-485/EIA-485 output enable signal for UART2. P1[20] 70 U7 K6 49 [3] I; PU I/O P1[20] — General purpose digital input/output pin. O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I QEI_PHA — Quadrature Encoder Interface PHA input. I MC_FB0 — Motor control PWM channel 0 feedback input. I/O SSP0_SCK — Serial clock for SSP0. O LCD_VD[6] — LCD data. O LCD_VD[10] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 19 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P1[21] 72 R8 N6 50 [3] I; PU I/O P1[21] — General purpose digital input/output pin. O USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver). O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSP0_SSEL — Slave Select for SSP0. I MC_ABORT — Motor control PWM, active low fast abort. - R — Function reserved. O LCD_VD[7] — LCD data. O LCD_VD[11] — LCD data. P1[22] 74 U8 M6 51 [3] I; PU I/O P1[22] — General purpose digital input/output pin. I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver). I USB_PWRD1 — Power Status for USB port 1 (host power switch). O T1_MAT0 — Match output for Timer 1, channel 0. O MC_0B — Motor control PWM channel 0, output B. I/O SSP1_MOSI — Master Out Slave In for SSP1. O LCD_VD[8] — LCD data. O LCD_VD[12] — LCD data. P1[23] 76 P9 N7 53 [3] I; PU I/O P1[23] — General purpose digital input/output pin. I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver). O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I QEI_PHB — Quadrature Encoder Interface PHB input. I MC_FB1 — Motor control PWM channel 1 feedback input. I/O SSP0_MISO — Master In Slave Out for SSP0. O LCD_VD[9] — LCD data. O LCD_VD[13] — LCD data. P1[24] 78 T9 P7 54 [3] I; PU I/O P1[24] — General purpose digital input/output pin. I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I QEI_IDX — Quadrature Encoder Interface INDEX input. I MC_FB2 — Motor control PWM channel 2 feedback input. I/O SSP0_MOSI — Master Out Slave in for SSP0. O LCD_VD[10] — LCD data. O LCD_VD[14] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 20 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P1[25] 80 T10 L7 56 [3] I; PU I/O P1[25] — General purpose digital input/output pin. O USB_LS1 — Low Speed status for USB port 1 (OTG transceiver). O USB_HSTEN1 — Host Enabled status for USB port 1. O T1_MAT1 — Match output for Timer 1, channel 1. O MC_1A — Motor control PWM channel 1, output A. O CLKOUT — Selectable clock output. O LCD_VD[11] — LCD data. O LCD_VD[15] — LCD data. P1[26] 82 R10 P8 57 [3] I; PU I/O P1[26] — General purpose digital input/output pin. O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I T0_CAP0 — Capture input for Timer 0, channel 0. O MC_1B — Motor control PWM channel 1, output B. I/O SSP1_SSEL — Slave Select for SSP1. O LCD_VD[12] — LCD data. O LCD_VD[20] — LCD data. P1[27] 88 T12 M9 61 [3] I; PU I/O P1[27] — General purpose digital input/output pin. I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver). I USB_OVRCR1 — USB port 1 Over-Current status. I T0_CAP1 — Capture input for Timer 0, channel 1. O CLKOUT — Selectable clock output. - R — Function reserved. O LCD_VD[13] — LCD data. O LCD_VD[21] — LCD data. P1[28] 90 T13 P10 63 [3] I; PU I/O P1[28] — General purpose digital input/output pin. I/O USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver). I PWM1_CAP0 — Capture input for PWM1, channel 0. O T0_MAT0 — Match output for Timer 0, channel 0. O MC_2A — Motor control PWM channel 2, output A. I/O SSP0_SSEL — Slave Select for SSP0. O LCD_VD[14] — LCD data. O LCD_VD[22] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 21 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P1[29] 92 U14 N10 64 [3] I; PU I/O P1[29] — General purpose digital input/output pin. I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver). I PWM1_CAP1 — Capture input for PWM1, channel 1. O T0_MAT1 — Match output for Timer 0, channel 1. O MC_2B — Motor control PWM channel 2, output B. O U4_TXD — Transmitter output for USART4 (input/output in smart card mode). O LCD_VD[15] — LCD data. O LCD_VD[23] — LCD data. P1[30] 42 P2 K3 30 [5] I; PU I/O P1[30] — General purpose digital input/output pin. I USB_PWRD2 — Power Status for USB port 2. I USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH for USB reset to occur. I ADC0_IN[4] — A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2C0_SDA — I 2C0 data input/output (this pin does not use a specialized I2C pad). O U3_OE — RS-485/EIA-485 output enable signal for UART3. P1[31] 40 P1 K2 28 [5] I; PU I/O P1[31] — General purpose digital input/output pin. I USB_OVRCR2 — Over-Current status for USB port 2. I/O SSP1_SCK — Serial Clock for SSP1. I ADC0_IN[5] — A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2C0_SCL — I 2C0 clock input/output (this pin does not use a specialized I2C pad). P2[0] to P2[31] I/O Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. P2[0] 154 B17 D12 107 [3] I; PU I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O U1_TXD — Transmitter output for UART1. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_PWR — LCD panel power enable. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 22 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P2[1] 152 E14 C14 106 [3] I; PU I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I U1_RXD — Receiver input for UART1. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_LE — Line end signal. P2[2] 150 D15 E11 105 [3] I; PU I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I U1_CTS — Clear to Send input for UART1. O T2_MAT3 — Match output for Timer 2, channel 3. - R — Function reserved. O TRACEDATA[3] — Trace data, bit 3. - R — Function reserved. O LCD_DCLK — LCD panel clock. P2[3] 144 E16 E13 100 [3] I; PU I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I U1_DCD — Data Carrier Detect input for UART1. O T2_MAT2 — Match output for Timer 2, channel 2. - R — Function reserved. O TRACEDATA[2] — Trace data, bit 2. - R — Function reserved. O LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). P2[4] 142 D17 E14 99 [3] I; PU I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I U1_DSR — Data Set Ready input for UART1. O T2_MAT1 — Match output for Timer 2, channel 1. - R — Function reserved. O TRACEDATA[1] — Trace data, bit 1. - R — Function reserved. O LCD_ENAB_M — STN AC bias drive or TFT data enable output. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 23 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P2[5] 140 F16 F12 97 [3] I; PU I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. O T2_MAT0 — Match output for Timer 2, channel 0. - R — Function reserved. O TRACEDATA[0] — Trace data, bit 0. - R — Function reserved. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). P2[6] 138 E17 F13 96 [3] I; PU I/O P2[6] — General purpose digital input/output pin. I PWM1_CAP0 — Capture input for PWM1, channel 0. I U1_RI — Ring Indicator input for UART1. I T2_CAP0 — Capture input for Timer 2, channel 0. O U2_OE — RS-485/EIA-485 output enable signal for UART2. O TRACECLK — Trace clock. O LCD_VD[0] — LCD data. O LCD_VD[4] — LCD data. P2[7] 136 G16 G11 95 [3] I; PU I/O P2[7] — General purpose digital input/output pin. I CAN_RD2 — CAN2 receiver input. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[1] — LCD data. O LCD_VD[5] — LCD data. P2[8] 134 H15 G14 93 [3] I; PU I/O P2[8] — General purpose digital input/output pin. O CAN_TD2 — CAN2 transmitter output. O U2_TXD — Transmitter output for UART2. I U1_CTS — Clear to Send input for UART1. O ENET_MDC — Ethernet MIIM clock. - R — Function reserved. O LCD_VD[2] — LCD data. O LCD_VD[6] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 24 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P2[9] 132 H16 H11 92 [3] I; PU I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an external 1.5 k resistor under the software control. Used with the SoftConnect USB feature. I U2_RXD — Receiver input for UART2. I U4_RXD — Receiver input for USART4. I/O ENET_MDIO — Ethernet MIIM data input and output. - R — Function reserved. I LCD_VD[3] — LCD data. I LCD_VD[7] — LCD data. P2[10] 110 N15 M13 76 [10] I; PU I/O P2[10] — General purpose digital input/output pin. This pin includes a 10 ns input . A LOW on this pin while RESET is LOW forces the on-chip boot loader to take over control of the part after a reset and go into ISP mode. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. P2[11] 108 T17 M12 75 [10] I; PU I/O P2[11] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT1 — External interrupt 1 input. I/O SD_DAT[1] — Data line 1 for SD card interface. I/O I2S_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_CLKIN — LCD clock. P2[12] 106 N14 N14 73 [10] I; PU I/O P2[12] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT2 — External interrupt 2 input. I/O SD_DAT[2] — Data line 2 for SD card interface. I/O I2S_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. O LCD_VD[4] — LCD data. O LCD_VD[3] — LCD data. O LCD_VD[8] — LCD data. O LCD_VD[18] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 25 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P2[13] 102 T16 M11 71 [10] I; PU I/O P2[13] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT3 — External interrupt 3 input. I/O SD_DAT[3] — Data line 3 for SD card interface. I/O I2S_TX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. - R — Function reserved. O LCD_VD[5] — LCD data. O LCD_VD[9] — LCD data. O LCD_VD[19] — LCD data. P2[14] 91 R12 - - [3] I; PU I/O P2[14] — General purpose digital input/output pin. O EMC_CS2 — LOW active Chip Select 2 signal. I/O I2C1_SDA — I 2C1 data input/output (this pin does not use a specialized I2C pad). I T2_CAP0 — Capture input for Timer 2, channel 0. P2[15] 99 P13 - - [3] I; PU I/O P2[15] — General purpose digital input/output pin. O EMC_CS3 — LOW active Chip Select 3 signal. I/O I2C1_SCL — I 2C1 clock input/output (this pin does not use a specialized I2C pad). I T2_CAP1 — Capture input for Timer 2, channel 1. P2[16] 87 R11 P9 - [3] I; PU I/O P2[16] — General purpose digital input/output pin. O EMC_CAS — LOW active SDRAM Column Address Strobe. P2[17] 95 R13 P11 - [3] I; PU I/O P2[17] — General purpose digital input/output pin. O EMC_RAS — LOW active SDRAM Row Address Strobe. P2[18] 59 U3 P3 - [6] I; PU I/O P2[18] — General purpose digital input/output pin. O EMC_CLK[0] — SDRAM clock 0. P2[19] 67 R7 N5 - [6] I; PU I/O P2[19] — General purpose digital input/output pin. O EMC_CLK[1] — SDRAM clock 1. P2[20] 73 T8 P6 - [3] I; PU I/O P2[20] — General purpose digital input/output pin. O EMC_DYCS0 — SDRAM chip select 0. P2[21] 81 U11 N8 - [3] I; PU I/O P2[21] — General purpose digital input/output pin. O EMC_DYCS1 — SDRAM chip select 1. P2[22] 85 U12 - - [3] I; PU I/O P2[22] — General purpose digital input/output pin. O EMC_DYCS2 — SDRAM chip select 2. I/O SSP0_SCK — Serial clock for SSP0. I T3_CAP0 — Capture input for Timer 3, channel 0. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 26 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P2[23] 64 U5 - - [3] I; PU I/O P2[23] — General purpose digital input/output pin. O EMC_DYCS3 — SDRAM chip select 3. I/O SSP0_SSEL — Slave Select for SSP0. I T3_CAP1 — Capture input for Timer 3, channel 1. P2[24] 53 P5 P1 - [3] I; PU I/O P2[24] — General purpose digital input/output pin. O EMC_CKE0 — SDRAM clock enable 0. P2[25] 54 R4 P2 - [3] I; PU I/O P2[25] — General purpose digital input/output pin. O EMC_CKE1 — SDRAM clock enable 1. P2[26] 57 T4 - - [3] I; PU I/O P2[26] — General purpose digital input/output pin. O EMC_CKE2 — SDRAM clock enable 2. I/O SSP0_MISO — Master In Slave Out for SSP0. O T3_MAT0 — Match output for Timer 3, channel 0. P2[27] 47 P3 - - [3] I; PU I/O P2[27] — General purpose digital input/output pin. O EMC_CKE3 — SDRAM clock enable 3. I/O SSP0_MOSI — Master Out Slave In for SSP0. O T3_MAT1 — Match output for Timer 3, channel 1. P2[28] 49 P4 M2 - [3] I; PU I/O P2[28] — General purpose digital input/output pin. O EMC_DQM0 — Data mask 0 used with SDRAM and static devices. P2[29] 43 N3 L1 - [3] I; PU I/O P2[29] — General purpose digital input/output pin. O EMC_DQM1 — Data mask 1 used with SDRAM and static devices. P2[30] 31 L4 - - [3] I; PU I/O P2[30] — General purpose digital input/output pin. O EMC_DQM2 — Data mask 2 used with SDRAM and static devices. I/O I2C2_SDA — I 2C2 data input/output (this pin does not use a specialized I2C pad). O T3_MAT2 — Match output for Timer 3, channel 2. P2[31] 39 N2 - - [3] I; PU I/O P2[31] — General purpose digital input/output pin. O EMC_DQM3 — Data mask 3 used with SDRAM and static devices. I/O I2C2_SCL — I 2C2 clock input/output (this pin does not use a specialized I2C pad). O T3_MAT3 — Match output for Timer 3, channel 3. P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 27 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P3[0] 197 B4 D6 137 [3] I; PU I/O P3[0] — General purpose digital input/output pin. I/O EMC_D[0] — External memory data line 0. P3[1] 201 B3 E6 140 [3] I; PU I/O P3[1] — General purpose digital input/output pin. I/O EMC_D[1] — External memory data line 1. P3[2] 207 B1 A2 144 [3] I; PU I/O P3[2] — General purpose digital input/output pin. I/O EMC_D[2] — External memory data line 2. P3[3] 3 E4 G5 2 [3] I; PU I/O P3[3] — General purpose digital input/output pin. I/O EMC_D[3] — External memory data line 3. P3[4] 13 F2 D3 9 [3] I; PU I/O P3[4] — General purpose digital input/output pin. I/O EMC_D[4] — External memory data line 4. P3[5] 17 G1 E3 12 [3] I; PU I/O P3[5] — General purpose digital input/output pin. I/O EMC_D[5] — External memory data line 5. P3[6] 23 J1 F4 16 [3] I; PU I/O P3[6] — General purpose digital input/output pin. I/O EMC_D[6] — External memory data line 6. P3[7] 27 L1 G3 19 [3] I; PU I/O P3[7] — General purpose digital input/output pin. I/O EMC_D[7] — External memory data line 7. P3[8] 191 D8 A6 - [3] I; PU I/O P3[8] — General purpose digital input/output pin. I/O EMC_D[8] — External memory data line 8. P3[9] 199 C5 A4 - [3] I; PU I/O P3[9] — General purpose digital input/output pin. I/O EMC_D[9] — External memory data line 9. P3[10] 205 B2 B3 - [3] I; PU I/O P3[10] — General purpose digital input/output pin. I/O EMC_D[10] — External memory data line 10. P3[11] 208 D5 B2 - [3] I; PU I/O P3[11] — General purpose digital input/output pin. I/O EMC_D[11] — External memory data line 11. P3[12] 1 D4 A1 - [3] I; PU I/O P3[12] — General purpose digital input/output pin. I/O EMC_D[12] — External memory data line 12. P3[13] 7 C1 C1 - [3] I; PU I/O P3[13] — General purpose digital input/output pin. I/O EMC_D[13] — External memory data line 13. P3[14] 21 H2 F1 - [3] I; PU I/O P3[14] — General purpose digital input/output pin. I/O EMC_D[14] — External memory data line 14. P3[15] 28 M1 G4 - [3] I; PU I/O P3[15] — General purpose digital input/output pin. I/O EMC_D[15] — External memory data line 15. P3[16] 137 F17 - - [3] I; PU I/O P3[16] — General purpose digital input/output pin. I/O EMC_D[16] — External memory data line 16. O PWM0[1] — Pulse Width Modulator 0, output 1. O U1_TXD — Transmitter output for UART1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 28 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P3[17] 143 F15 - - [3] I; PU I/O P3[17] — General purpose digital input/output pin. I/O EMC_D[17] — External memory data line 17. O PWM0[2] — Pulse Width Modulator 0, output 2. I U1_RXD — Receiver input for UART1. P3[18] 151 C15 - - [3] I; PU I/O P3[18] — General purpose digital input/output pin. I/O EMC_D[18] — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I U1_CTS — Clear to Send input for UART1. P3[19] 161 B14 - - [3] I; PU I/O P3[19] — General purpose digital input/output pin. I/O EMC_D[19] — External memory data line 19. O PWM0[4] — Pulse Width Modulator 0, output 4. I U1_DCD — Data Carrier Detect input for UART1. P3[20] 167 A13 - - [3] I; PU I/O P3[20] — General purpose digital input/output pin. I/O EMC_D[20] — External memory data line 20. O PWM0[5] — Pulse Width Modulator 0, output 5. I U1_DSR — Data Set Ready input for UART1. P3[21] 175 C10 - - [3] I; PU I/O P3[21] — General purpose digital input/output pin. I/O EMC_D[21] — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. P3[22] 195 C6 - - [3] I; PU I/O P3[22] — General purpose digital input/output pin. I/O EMC_D[22] — External memory data line 22. I PWM0_CAP0 — Capture input for PWM0, channel 0. I U1_RI — Ring Indicator input for UART1. P3[23] 65 T6 M4 45 [3] I; PU I/O P3[23] — General purpose digital input/output pin. I/O EMC_D[23] — External memory data line 23. I PWM1_CAP0 — Capture input for PWM1, channel 0. I T0_CAP0 — Capture input for Timer 0, channel 0. P3[24] 58 R5 N3 40 [3] I; PU I/O P3[24] — General purpose digital input/output pin. I/O EMC_D[24] — External memory data line 24. O PWM1[1] — Pulse Width Modulator 1, output 1. I T0_CAP1 — Capture input for Timer 0, channel 1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 29 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P3[25] 56 U2 M3 39 [3] I; PU I/O P3[25] — General purpose digital input/output pin. I/O EMC_D[25] — External memory data line 25. O PWM1[2] — Pulse Width Modulator 1, output 2. O T0_MAT0 — Match output for Timer 0, channel 0. P3[26] 55 T3 K7 38 [3] I; PU I/O P3[26] — General purpose digital input/output pin. I/O EMC_D[26] — External memory data line 26. O PWM1[3] — Pulse Width Modulator 1, output 3. O T0_MAT1 — Match output for Timer 0, channel 1. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. P3[27] 203 A1 - - [3] I; PU I/O P3[27] — General purpose digital input/output pin. I/O EMC_D[27] — External memory data line 27. O PWM1[4] — Pulse Width Modulator 1, output 4. I T1_CAP0 — Capture input for Timer 1, channel 0. P3[28] 5 D2 - - [3] I; PU I/O P3[28] — General purpose digital input/output pin. I/O EMC_D[28] — External memory data line 28. O PWM1[5] — Pulse Width Modulator 1, output 5. I T1_CAP1 — Capture input for Timer 1, channel 1. P3[29] 11 F3 - - [3] I; PU I/O P3[29] — General purpose digital input/output pin. I/O EMC_D[29] — External memory data line 29. O PWM1[6] — Pulse Width Modulator 1, output 6. O T1_MAT0 — Match output for Timer 1, channel 0. P3[30] 19 H3 - - [3] I; PU I/O P3[30] — General purpose digital input/output pin. I/O EMC_D[30] — External memory data line 30. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. O T1_MAT1 — Match output for Timer 1, channel 1. P3[31] 25 J3 - - [3] I; PU I/O P3[31] — General purpose digital input/output pin. I/O EMC_D[31] — External memory data line 31. - R — Function reserved. O T1_MAT2 — Match output for Timer 1, channel 2. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. P4[0] 75 U9 L6 52 [3] I; PU I/O P4[0] — General purpose digital input/output pin. I/O EMC_A[0] — External memory address line 0. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 30 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P4[1] 79 U10 M7 55 [3] I; PU I/O P4[1] — General purpose digital input/output pin. I/O EMC_A[1] — External memory address line 1. P4[2] 83 T11 M8 58 [3] I; PU I/O P4[2] — General purpose digital input/output pin. I/O EMC_A[2] — External memory address line 2. P4[3] 97 U16 K9 68 [3] I; PU I/O P4[3] — General purpose digital input/output pin. I/O EMC_A[3] — External memory address line 3. P4[4] 103 R15 P13 72 [3] I; PU I/O P4[4] — General purpose digital input/output pin. I/O EMC_A[4] — External memory address line 4. P4[5] 107 R16 H10 74 [3] I; PU I/O P4[5] — General purpose digital input/output pin. I/O EMC_A[5] — External memory address line 5. P4[6] 113 M14 K10 78 [3] I; PU I/O P4[6] — General purpose digital input/output pin. I/O EMC_A[6] — External memory address line 6. P4[7] 121 L16 K12 84 [3] I; PU I/O P4[7] — General purpose digital input/output pin. I/O EMC_A[7] — External memory address line 7. P4[8] 127 J17 J11 88 [3] I; PU I/O P4[8] — General purpose digital input/output pin. I/O EMC_A[8] — External memory address line 8. P4[9] 131 H17 H12 91 [3] I; PU I/O P4[9] — General purpose digital input/output pin. I/O EMC_A[9] — External memory address line 9. P4[10] 135 G17 G12 94 [3] I; PU I/O P4[10] — General purpose digital input/output pin. I/O EMC_A[10] — External memory address line 10. P4[11] 145 F14 F11 101 [3] I; PU I/O P4[11] — General purpose digital input/output pin. I/O EMC_A[11] — External memory address line 11. P4[12] 149 C16 F10 104 [3] I; PU I/O P4[12] — General purpose digital input/output pin. I/O EMC_A[12] — External memory address line 12. P4[13] 155 B16 B14 108 [3] I; PU I/O P4[13] — General purpose digital input/output pin. I/O EMC_A[13] — External memory address line 13. P4[14] 159 B15 E8 110 [3] I; PU I/O P4[14] — General purpose digital input/output pin. I/O EMC_A[14] — External memory address line 14. P4[15] 173 A11 C10 120 [3] I; PU I/O P4[15] — General purpose digital input/output pin. I/O EMC_A[15] — External memory address line 15. P4[16] 101 U17 N12 - [3] I; PU I/O P4[16] — General purpose digital input/output pin. I/O EMC_A[16] — External memory address line 16. P4[17] 104 P14 N13 - [3] I; PU I/O P4[17] — General purpose digital input/output pin. I/O EMC_A[17] — External memory address line 17. P4[18] 105 P15 P14 - [3] I; PU I/O P4[18] — General purpose digital input/output pin. I/O EMC_A[18] — External memory address line 18. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 31 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P4[19] 111 P16 M14 - [3] I; PU I/O P4[19] — General purpose digital input/output pin. I/O EMC_A[19] — External memory address line 19. P4[20] 109 R17 - - [3] I; PU I/O P4[20] — General purpose digital input/output pin. I/O EMC_A[20] — External memory address line 20. I/O I2C2_SDA — I 2C2 data input/output (this pin does not use a specialized I2C pad). I/O SSP1_SCK — Serial Clock for SSP1. P4[21] 115 M15 - - [3] I; PU I/O P4[21] — General purpose digital input/output pin. I/O EMC_A[21] — External memory address line 21. I/O I2C2_SCL — I 2C2 clock input/output (this pin does not use a specialized I2C pad). I/O SSP1_SSEL — Slave Select for SSP1. P4[22] 123 K14 - - [3] I; PU I/O P4[22] — General purpose digital input/output pin. I/O EMC_A[22] — External memory address line 22. O U2_TXD — Transmitter output for UART2. I/O SSP1_MISO — Master In Slave Out for SSP1. P4[23] 129 J15 - - [3] I; PU I/O P4[23] — General purpose digital input/output pin. I/O EMC_A[23] — External memory address line 23. I U2_RXD — Receiver input for UART2. I/O SSP1_MOSI — Master Out Slave In for SSP1. P4[24] 183 B8 C8 127 [3] I; PU I/O P4[24] — General purpose digital input/output pin. O EMC_OE — LOW active Output Enable signal. P4[25] 179 B9 D9 124 [3] I; PU I/O P4[25] — General purpose digital input/output pin. O EMC_WE — LOW active Write Enable signal. P4[26] 119 L15 K13 - [3] I; PU I/O P4[26] — General purpose digital input/output pin. O EMC_BLS0 — LOW active Byte Lane select signal 0. P4[27] 139 G15 F14 - [3] I; PU I/O P4[27] — General purpose digital input/output pin. O EMC_BLS1 — LOW active Byte Lane select signal 1. P4[28] 170 C11 D10 118 [3] I; PU I/O P4[28] — General purpose digital input/output pin. O EMC_BLS2 — LOW active Byte Lane select signal 2. O U3_TXD — Transmitter output for UART3. O T2_MAT0 — Match output for Timer 2, channel 0. - R — Function reserved. O LCD_VD[6] — LCD data. O LCD_VD[10] — LCD data. O LCD_VD[2] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 32 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P4[29] 176 B10 B9 122 [3] I; PU I/O P4[29] — General purpose digital input/output pin. O EMC_BLS3 — LOW active Byte Lane select signal 3. I U3_RXD — Receiver input for UART3. O T2_MAT1 — Match output for Timer 2, channel 1. I/O I2C2_SCL — I 2C2 clock input/output (this pin does not use a specialized I2C pad). O LCD_VD[7] — LCD data. O LCD_VD[11] — LCD data. O LCD_VD[3] — LCD data. P4[30] 187 B7 C7 130 [3] I; PU I/O P4[30] — General purpose digital input/output pin. O EMC_CS0 — LOW active Chip Select 0 signal. P4[31] 193 A4 E7 134 [3] I; PU I/O P4[31] — General purpose digital input/output pin. O EMC_CS1 — LOW active Chip Select 1 signal. P5[0] to P5[4] I/O Port 5: Port 5 is a 5-bit I/O port with individual direction controls for each bit. The operation of port 5 pins depends upon the pin function selected via the pin connect block. P5[0] 9 F4 E5 6 [3] I; PU I/O P5[0] — General purpose digital input/output pin. I/O EMC_A[24] — External memory address line 24. I/O SSP2_MOSI — Master Out Slave In for SSP2. O T2_MAT2 — Match output for Timer 2, channel 2. P5[1] 30 J4 H1 21 [3] I; PU I/O P5[1] — General purpose digital input/output pin. I/O EMC_A[25] — External memory address line 25. I/O SSP2_MISO — Master In Slave Out for SSP2. O T2_MAT3 — Match output for Timer 2, channel 3. P5[2] 117 L14 L12 81 [11] I I/O P5[2] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T3_MAT2 — Match output for Timer 3, channel 2. - R — Function reserved. I/O I2C0_SDA — I 2C0 data input/output (this pin uses a specialized I 2C pad that supports I2C Fast Mode Plus). Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 33 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller P5[3] 141 G14 G10 98 [11] I I/O P5[3] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I U4_RXD — Receiver input for USART4. I/O I2C0_SCL — I 2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus). P5[4] 206 C3 C4 143 [3] I; PU I/O P5[4] — General purpose digital input/output pin. O U0_OE — RS-485/EIA-485 output enable signal for UART0. - R — Function reserved. O T3_MAT3 — Match output for Timer 3, channel 3. O U4_TXD — Transmitter output for USART4 (input/output in smart card mode). JTAG_TDO (SWO) 2 D3 B1 1 [3] O O Test Data Out for JTAG interface. Also used as Serial wire trace output. JTAG_TDI 4 C2 C3 3 [3] I; PU I Test Data In for JTAG interface. JTAG_TMS (SWDIO) 6 E3 C2 4 [3] I; PU I Test Mode Select for JTAG interface. Also used as Serial wire debug data input/output. JTAG_TRST 8 D1 D4 5 [3] I; PU I Test Reset for JTAG interface. JTAG_TCK (SWDCLK) 10 E2 D2 7 [3] i I Test Clock for JTAG interface. This clock must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to operate. Also used as serial wire clock. RESET 35 M2 J1 24 [12] I; PU I External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin also serves as the debug select input. LOW level selects the JTAG boundary scan. HIGH level selects the ARM SWD debug mode. RSTOUT 29 K3 H2 20 [3] OH O Reset status output. A LOW output on this pin indicates that the device is in the reset state for any reason. This reflects the RESET input pin and all internal reset sources. RTC_ALARM 37 N1 H5 26 [13] OL O RTC controlled output. This pin has a low drive strength and is powered by VBAT. It is driven HIGH when an RTC alarm is generated. RTCX1 34 K2 J2 23 [14] [15] - I Input to the RTC 32 kHz ultra-low power oscillator circuit. RTCX2 36 L2 J3 25 [14] [15] - O Output from the RTC 32 kHz ultra-low power oscillator circuit. USB_D2 52 U1 N2 37 [9] - I/O USB port 2 bidirectional D line. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 34 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller VBAT 38 M3 K1 27 - I RTC power supply: 3.0 V on this pin supplies power to the RTC. VDD(REG)(3V3) 26, 86, 174 H4, P11, D11 G1, N9, E9 18, 60, 121 - S 3.3 V regulator supply voltage: This is the power supply for the on-chip voltage regulator that supplies internal logic. VDDA 20 G4 F2 14 - S Analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Note: This pin should be tied to 3.3 V if the ADC and DAC are not used. VDD(3V3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198 G3, P6, P8, U13, P17, K16, C17, B13, C9, D7 E2, L4, K8, L11, J14, E12, E10, C5 41, 62, 77, 102, 114, 138 - S 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the VBAT domain. VREFP 24 K1 G2 17 - S ADC positive reference voltage: This should be the same voltage as VDDA, but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC. Note: This pin should be tied to 3.3 V if the ADC and DAC are not used. VSS 33, 63, 77, 93, 114, 133, 148, 169, 189, 200 L3, T5, R9, P12, N16, H14, E15, A12, B6, A2 H4, P4, L9, L13, G13, D13, C11, B4 44, 65, 79, 103, 117, 139 - G Ground: 0 V reference for digital IO pins. VSSREG 32, 84, 172 D12, K4, P10 H3, L8, A10 22, 59, 119 - G Ground: 0 V reference for internal logic. VSSA 22 J2 F3 15 - G Analog ground: 0 V power supply and reference for the ADC and DAC. This should be the same voltage as VSS, but should be isolated to minimize noise and error. XTAL1 44 M4 L2 31 [14] [16] - I Input to the oscillator circuit and internal clock generator circuits. XTAL2 46 N4 K4 33 [14] [16] - O Output from the oscillator amplifier. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state[1] Type[2] DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 35 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller [1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. [2] I = Input; O = Output; OL = Output driving LOW; G = Ground; S = Supply. [3] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. [4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. This pad can be powered by VBAT. [5] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled. [6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. [7] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V) providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [10] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [12] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [13] This pad can be powered from VBAT. [14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be used to drive the RTCX1 pin. [15] If the RTC is not used, these pins can be left floating. [16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball Symbol Row A 1 P3[27] 2 VSS 3 P1[0] 4 P4[31] 5 P1[4] 6 P1[9] 7 P1[14] 8 P1[15] 9 P1[17] 10 P1[3] 11 P4[15] 12 VSS 13 P3[20] 14 P1[11] 15 P0[8] 16 P1[12] 17 P1[5] - - - Row B 1 P3[2] 2 P3[10] 3 P3[1] 4 P3[0] 5 P1[1] 6 VSS 7 P4[30] 8 P4[24] 9 P4[25] 10 P4[29] 11 P1[6] 12 P0[4] 13 VDD(3V3) 14 P3[19] 15 P4[14] 16 P4[13] 17 P2[0] - - - Row CLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 36 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 1 P3[13] 2 JTAG_TDI 3 P5[4] 4 P0[2] 5 P3[9] 6 P3[22] 7 P1[8] 8 P1[10] 9 VDD(3V3) 10 P3[21] 11 P4[28] 12 P0[5] 13 P0[7] 14 P0[9] 15 P3[18] 16 P4[12] 17 VDD(3V3)- - - Row D 1 JTAG_TRST 2 P3[28] 3 JTAG_TDO (SWO) 4 P3[12] 5 P3[11] 6 P0[3] 7 VDD(3V3) 8 P3[8] 9 P1[2] 10 P1[16] 11 VDD(REG)(3V3) 12 VSSREG 13 P0[6] 14 P1[7] 15 P2[2] 16 P1[13] 17 P2[4] - - - Row E 1 P0[26] 2 JTAG_TCK (SWDCLK) 3 JTAG_TMS (SWDIO) 4 P3[3] 5 - 6- 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 P2[1] 15 VSS 16 P2[3] 17 P2[6] - - - Row F 1 P0[25] 2 P3[4] 3 P3[29] 4 P5[0] 5 - 6- 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 P4[11] 15 P3[17] 16 P2[5] 17 P3[16] - - - Row G 1 P3[5] 2 P0[24] 3 VDD(3V3) 4 VDDA 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 P5[3] 15 P4[27] 16 P2[7] 17 P4[10] - - - Row H 1 P0[23] 2 P3[14] 3 P3[30] 4 VDD(REG)(3V3) 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 VSS 15 P2[8] 16 P2[9] 17 P4[9] - - - Row J 1 P3[6] 2 VSSA 3 P3[31] 4 P5[1] 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 37 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 13 14 P0[16] 15 P4[23] 16 P0[15] 17 P4[8] - - - Row K 1 VREFP 2 RTCX1 3 RSTOUT 4 VSSREG 13 - 14 P4[22] 15 P0[18] 16 VDD(3V3) 17 P0[17] - - - Row L 1 P3[7] 2 RTCX2 3 VSS 4 P2[30] 5 - 6- 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 P5[2] 15 P4[26] 16 P4[7] 17 P0[19] - - - Row M 1 P3[15] 2 RESET 3 VBAT 4 XTAL1 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 P4[6] 15 P4[21] 16 P0[21] 17 P0[20] - - - Row N 1 RTC_ALARM 2 P2[31] 3 P2[29] 4 XTAL2 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 P2[12 15 P2[10] 16 VSS 17 P0[22] - - - Row P 1 P1[31] 2 P1[30] 3 P2[27] 4 P2[28] 5 P2[24] 6 VDD(3V3) 7 P1[18] 8 VDD(3V3) 9 P1[23] 10 VSSREG 11 VDD(REG)(3V3) 12 VSS 13 P2[15] 14 P4[17] 15 P4[18] 16 P4[19] 17 VDD(3V3) --- Row R 1 P0[12] 2 P0[13] 3 P0[28] 4 P2[25] 5 P3[24] 6 P0[30] 7 P2[19] 8 P1[21] 9 VSS 10 P1[26] 11 P2[16] 12 P2[14] 13 P2[17] 14 P0[11] 15 P4[4] 16 P4[5] 17 P4[20] - - - Row T 1 P0[27] 2 P0[31] 3 P3[26] 4 P2[26] 5 VSS 6 P3[23] 7 P0[14] 8 P2[20] 9 P1[24] 10 P1[25] 11 P4[2] 12 P1[27] Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 38 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 13 P1[28] 14 P0[1] 15 P0[10] 16 P2[13] 17 P2[11] - - - Row U 1 USB_D-2 2 P3[25] 3 P2[18] 4 P0[29] 5 P2[23] 6 P1[19] 7 P1[20] 8 P1[22] 9 P4[0] 10 P4[1] 11 P2[21] 12 P2[22] 13 VDD(3V3) 14 P1[29] 15 P0[0] 16 P4[3] 17 P4[16] - - - Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball Symbol Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball Symbol Row A 5 P1[1] 6 P3[8] 7 P1[10] 8 P1[15] 9 P1[3] 10 VSSREG 11 P0[4] 12 P1[11] 13 P0[9] 14 P1[12] - - Row B 1 JTAG_TDO (SWO) 2 P3[11] 3 P3[10] 4 VSS 5 P1[0] 6 P1[8] 7 P1[2] 8 P1[16] 9 P4[29] 10 P1[6] 11 P0[5] 12 P0[7] 13 P1[5] 14 P4[13] - - Row C 1 P3[13] 2 JTAG_TMS (SWDIO) 3 JTAG_TDI 4 P5[4] 5 VDD(3V3) 6 P1[4] 7 P4[30] 8 P4[24] 9 P1[17] 10 P4[15] 11 VSS 12 P0[8] 13 P1[7] 14 P2[1] - - Row D 1 P0[26] 2 JTAG_TCK (SWDCLK) 3 P3[4] 4 JTAG_TRST 5 P0[2] 6 P3[0] 7 P1[9] 8 P1[14] 9 P4[25] 10 P4[28] 11 P0[6] 12 P2[0] 13 VSS 14 P1[13] - - Row E 1 P0[24] 2 VDD(3V3) 3 P3[5] 4 P0[25] 5 P5[0] 6 P3[1] 7 P4[31] 8 P4[14] 9 VDD(REG)(3V3) 10 VDD(3V3) 11 P2[2] 12 VDD(3V3) 13 P2[3] 14 P2[4] - - Row F 1 P3[14] 2 VDDA 3 VSSA 4 P3[6] 5 P0[23] 6 - 7 - 8 - 9 - 10 P4[12] 11 P4[11] 12 P2[5]LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 39 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 13 P2[6] 14 P4[27] - - Row G 1 VDD(REG)(3V3) 2 VREFP 3 P3[7] 4 P3[15] 5 P3[3] 6 - 7 - 8 - 9 - 10 P5[3] 11 P2[7] 12 P4[10] 13 VSS 14 P2[8] - - Row H 1 P5[1] 2 RSTOUT 3 VSSREG 4 VSS 5 RTC_ALARM 6 - 7 - 8 - 9 - 10 P4[5] 11 P2[9] 12 P4[9] 13 P0[15] 14 P0[16] - - Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 40 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. Row J 1 RESET 2 RTCX1 3 RTCX2 4 P0[12] 5 P0[13] 6 - 7 - 8 - 9 - 10 P0[19] 11 P4[8] 12 P0[17] 13 P0[18] 14 VDD(3V3) - - Row K 1 VBAT 2 P1[31] 3 P1[30] 4 XTAL2 5 P0[29] 6 P1[20] 7 P3[26] 8 VDD(3V3) 9 P4[3] 10 P4[6] 11 P0[21] 12 P4[7] 13 P4[26] 14 P0[20] - - Row L 1 P2[29] 2 XTAL1 3 P0[27] 4 VDD(3V3) 5 P1[18] 6 P4[0] 7 P1[25] 8 VSSREG 9 VSS 10 P0[10] 11 VDD(3V3) 12 P5[2] 13 VSS 14 P0[22] - - Row M 1 P0[28] 2 P2[28] 3 P3[25] 4 P3[23] 5 P0[14] 6 P1[22] 7 P4[1] 8 P4[2] 9 P1[27] 10 P0[0] 11 P2[13] 12 P2[11] 13 P2[10] 14 P4[19] - - Row N 1 P0[31] 2 USB_D-2 3 P3[24] 4 P0[30] 5 P2[19] 6 P1[21] 7 P1[23] 8 P2[21] 9 VDD(REG)(3V3) 10 P1[29] 11 P0[1] 12 P4[16] 13 P4[17] 14 P2[12] - - Row P 1 P2[24] 2 P2[25] 3 P2[18] 4 VSS 5 P1[19] 6 P2[20] 7 P1[24] 8 P1[26] 9 P2[16] 10 P1[28] 11 P2[17] 12 P0[11] 13 P4[4] 14 P4[18] - - Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 41 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware division, hardware single-cycle multiply, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 7.3 On-chip flash program memory The LPC178x/7x contain up to 512 kB of on-chip flash program memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 7.4 EEPROM The LPC178x/7x contains up to 4032 byte of on-chip byte-erasable and byte-programmable EEPROM data memory. 7.5 On-chip SRAM The LPC178x/7x contain a total of up to 96 kB on-chip static RAM data memory. This includes the main 64 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 7.6 Memory Protection Unit (MPU) The LPC178x/7x have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 42 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 7.7 Memory map The LPC178x/7x incorporate several distinct memory regions, shown in the following figures. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. Table 6. LPC178x/177x memory usage and details Address range General Use Address range details and description 0x0000 0000 to 0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory. 0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory. 0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory. 0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory. On-chip main SRAM 0x1000 0000 - 0x1000 FFFF For devices with 64 kB of main SRAM. 0x1000 0000 - 0x1000 7FFF For devices with 32 kB of main SRAM. 0x1000 0000 - 0x1000 3FFF For devices with 16 kB of main SRAM. Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services. 0x2000 0000 to 0x3FFF FFFF On-chip SRAM (typically used for peripheral data) 0x2000 0000 - 0x2000 1FFF Peripheral RAM - bank 0 (first 8 kB) 0x2000 2000 - 0x2000 3FFF Peripheral RAM - bank 0 (second 8 kB) 0x2000 4000 - 0x2000 7FFF Peripheral RAM - bank 1 (16 kB) AHB peripherals 0x2008 0000 - 0x200B FFFF See Figure 6 for details 0x4000 0000 to 0x7FFF FFFF APB Peripherals 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of 16 kB each. 0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of 16 kB each. 0x8000 0000 to 0xDFFF FFFF Off-chip Memory via the External Memory Controller Four static memory chip selects: 0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 MB) 0x9000 0000 - 0x93FF FFFF Static memory chip select 1 (up to 64 MB) 0x9800 0000 - 0x9BFF FFFF Static memory chip select 2 (up to 64 MB) 0x9C00 0000 - 0x9FFF FFFF Static memory chip select 3 (up to 64 MB) Four dynamic memory chip selects: 0xA000 0000 - 0xAFFF FFFF Dynamic memory chip select 0 (up to 256MB) 0xB000 0000 - 0xBFFF FFFF Dynamic memory chip select 1 (up to 256MB) 0xC000 0000 - 0xCFFF FFFF Dynamic memory chip select 2 (up to 256MB) 0xD000 0000 - 0xDFFF FFFF Dynamic memory chip select 3 (up to 256MB) 0xE000 0000 to 0xE00F FFFF Cortex-M3 Private Peripheral Bus 0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC and System Tick Timer.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 43 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2 and Table 6. Fig 6. LPC178x/7x memory map 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 0x4000 0000 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC timer 2 timer 3 UART2 UART3 USART4(1) I 2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 SSP2 I 2S 11 12 reserved motor control PWM reserved 30 - 17 reserved 13 14 15 16 31 system control reserved reserved 64 kB main static RAM(1) EMC 4 x static chip select(1) EMC 4 x dynamic chip select(1) reserved private peripheral bus 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x1000 0000 0x1001 0000 0x1FFF 0000 0x2000 0000 0x2000 8000 0x2008 0000 0x2200 0000 0x200A 0000 0x2400 0000 0x2800 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x8000 0000 0xA000 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved reserved reserved reserved reserved APB0 peripherals 0xE004 0000 AHB peripherals APB1 peripherals peripheral SRAM bit-band alias addressing peripheral bit-band alias addressing 16 kB peripheral SRAM1(1) 0x2000 4000 16 kB peripheral SRAM0(1) LPC178x/7x 0x0008 0000 512 kB on-chip flash(1) QEI(1) SD/MMC(1) APB0 peripherals WWDT timer 0 timer 1 UART0 UART1 reserved reserved CAN AF RAM CAN common CAN1 CAN2 CAN AF registers PWM0 I 2C0 RTC/event recorder + backup registers GPIO interrupts pin connect SSP1 ADC 22 - 19 reserved I 2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aaf574 reserved 0x1FFF 2000 0x2900 0000 reserved reserved 0x2008 0000 0x2008 4000 0x2008 8000 0x2008 C000 0x200A 0000 0x2009 C000 AHB peripherals LCD(1) USB(1) Ethernet(1) 0 GPDMA controller 1 2 3 0x2009 0000 4 CRC engine 0x2009 4000 5 0x2009 8000 GPIO EMC registers 6 7LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 44 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.8 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.8.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC178x/7x, the NVIC supports 40 vectored interrupts. • 32 programmable interrupt priority levels, with hardware priority level masking. • Relocatable vector table. • Non-Maskable Interrupt (NMI). • Software interrupt generation. 7.8.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 7.9 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 7.10 External memory controller Remark: Supported memory size and type and EMC bus width vary for different parts (see Table 2). The EMC pin configuration for each part is shown in Table 7.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 45 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 7. External memory controller pin configuration Part Data bus pins Address bus pins Control pins SRAM SDRAM LPC1788FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1788FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1788FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0], EMC_CS[1:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] LPC1788FBD144 EMC_D[7:0] EMC_A[15:0] EMC_BLS[3:2], EMC_CS[1:0], EMC_OE, EMC_WE not available LPC1787FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS_[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1786FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1785FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1778FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1778FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1778FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0], EMC_CS[1:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] LPC1778FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0], EMC_OE, EMC_WE not available LPC1777FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1776FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1776FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] LPC1774FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC1774FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0], EMC_OE, EMC_WE not availableLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 46 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. See Table 6 for EMC memory access. 7.10.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • 8/16/32 data and 16/20/26 address lines wide static memory support. • 16 bit and 32 bit wide chip select SDRAM memory support. • Static memory features include: – Asynchronous page mode read. – Programmable Wait States. – Bus turnaround delay. – Output enable and write enable delays. – Extended wait. • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.11 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master. The GPDMA controller allows data transfers between the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the I 2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be triggered by selected timer match conditions. Memory-to-memory transfers and transfers to or from GPIO are supported. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 47 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.11.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.12 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 7.12.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO or DMA back-to-back transfer.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 48 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). 7.13 LCD controller Remark: The LCD controller is available on parts LPC1788/87/86/85. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024 768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.13.1 Features • AHB master interface to access frame buffer. • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320 200, 320 240, 640 200, 640 240, 640 480, 800 600, and 1024 768. • Hardware cursor support for single-panel displays. • 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. • 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. • 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. • 16 bpp true-color non-palettized, for color STN and TFT. • 24 bpp true-color non-palettized, for color TFT. • Programmable timing for different display panels. • 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. • LCD panel clock may be generated from the peripheral clock, or from a clock input pin.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 49 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.14 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.14.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support – . • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 50 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.15 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85 and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. Details on typical USB interfacing solutions can be found in Section 14.1. 7.15.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM. 7.15.1.1 Features • Fully compliant with USB 2.0 Specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC178x/7x can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.15.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. 7.15.2.1 Features • OHCI compliant.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 51 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Two downstream ports. • Supports per-port power switching. 7.15.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.15.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 7.16 SD/MMC card interface Remark: The SD/MMC card interface is available on parts LPC1788/87/86/85 and parts LPC1778/77/76. The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.16.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.17 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC178x/7x use accelerated GPIO functions:LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 52 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller. Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.17.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.18 12-bit ADC The LPC178x/7x contain one ADC. It is a single 12-bit successive approximation ADC with eight channels and DMA support. 7.18.1 Features • 12-bit successive approximation ADC. • Input multiplexing among eight pins. • Power-down mode. • Measurement range VSS to VREFP. • 12-bit conversion rate: up to 400 kHz. • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 7.19 10-bit DAC The LPC178x/7x contain one DAC. The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 53 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.19.1 Features • 10-bit DAC. • Resistor string architecture. • Buffered output. • Power-down mode. • Selectable output drive. • Dedicated conversion timer. • DMA support. 7.20 UARTs Remark: USART4 is not available on part LPC1774FBD144. The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.20.1 Features • Maximum UART data bit rate of 7.5 MBit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto-baud capability. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing. • All UARTs have DMA support for both transmit and receive. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • USART4 includes an IrDA mode to support infrared communication. • USART4 supports synchronous mode and a smart card mode conforming to ISO7816-3. 7.21 SSP serial I/O controller The LPC178x/7x contain three SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 54 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.21.1 Features • Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave). • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses. • Synchronous serial communication. • Master or slave operation. • 8-frame FIFOs for both transmit and receive. • 4-bit to 16-bit frame. • DMA transfers supported by GPDMA. 7.22 I2C-bus serial I/O controllers The LPC178x/7x contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.22.1 Features • All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s (Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of up to 400 kbit/s. • The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0 using pins P5[2] and P5[3]. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • Both I2C-bus controllers support multiple address recognition and a bus monitor mode.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 55 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.23 I2S-bus serial I/O controllers The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC178x/7x provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.23.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • Configurable word select period in master mode (separately for I2S input and output). • Two 8 word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. 7.24 CAN controller and acceptance filters The LPC178x/7x contain one CAN controller with two channels. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.24.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 56 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.25 General purpose 32-bit timers/external event counters The LPC178x/7x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.25.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 7.26 Pulse Width Modulator (PWM) The LPC178x/7x contain two standard PWMs. The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC178x/7x. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 57 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.26.1 Features • LPC178x/7x has two PWM blocks with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 7.27 Motor control PWM The LPC178x/7x contain one motor control PWM. The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 58 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2n (see Table 8). 7.28 Quadrature Encoder Interface (QEI) Remark: The QEI is available on parts LPC1788/87/86 and LPC1778/77/76 A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.28.1 Features • Tracks encoder position. • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 7.29 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC178x/7x, this timer can be clocked from the internal AHB clock or from a device pin. Table 8. PWM speed at operating frequency 120 MHz PWM resolution PWM speed 6 bit 1.875 MHz 8 bit 0.468 MHz 10 bit 0.117 MHzLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 59 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.30 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.30.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect feed sequence causes reset or interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in multiples of Tcy(WDCLK) 4. • The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is always running if the watchdog timer is enabled. 7.31 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC178x/7x is designed to have very low power consumption. The RTC will typically run from the main chip power supply conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V lithium button cell. An ultra-low power 32 kHz oscillator provides a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC178x/7x is powered off. The RTC includes an alarm function that can wake up the LPC178x/7x from all reduced power modes with a time resolution of 1 s. 7.31.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 60 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 7.32 Event monitor/recorder The event monitor/recorder allows recording of tampering events in sealed product enclosures. Sensors report any attempt to open the enclosure, or to tamper with the device in any other way. The event monitor/recorder stores records of such events when the device is powered only by the backup battery. 7.32.1 Features • Supports three digital event inputs in the VBAT power domain. • An event is defined as a level change at the digital event inputs. • For each event channel, two timestamps mark the first and the last occurrence of an event. Each channel also has a dedicated counter tracking the total number of events. Timestamp values are taken from the RTC. • Runs in VBAT power domain, independent of system power supply. The event/recorder/monitor can therefore operate in Deep power-down mode. • Very low power consumption. • Interrupt available if system is running. • A qualified event can be used as a wake-up trigger. • State of event interrupts accessible by software through GPIO. 7.33 Clocking and power control 7.33.1 Crystal oscillators The LPC178x/7x include four independent oscillators. These are the main oscillator, the IRC oscillator, the watchdog oscillator, and the RTC oscillator. Following reset, the LPC178x/7x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. See Figure 7 for an overview of the LPC178x/7x clock generation.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 61 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.33.1.1 Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC178x/7x use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.33.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the alternate PLL1. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.33.2 for additional information. Fig 7. LPC178x/7x clock generation block diagram MAIN PLL0 IRC oscillator main oscillator (osc_clk) CLKSRCSEL (system clock select) sysclk pll_clk CCLKSEL (CPU clock select) 002aaf531 pll_clk ALT PLL1 CPU CLOCK DIVIDER alt_pll_clk cclk PERIPHERAL CLOCK DIVIDER pclk EMC CLOCK DIVIDER emc_clk sysclk alt_pll_clk pll_clk USBCLKSEL (USB clock select) USB CLOCK DIVIDER usb_clk sysclk LPC178x/7xLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 62 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.33.1.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.33.1.4 Watchdog oscillator The Watchdog Timer has a dedicated watchdog oscillator that provides a 500 kHz clock to the Watchdog Timer. The watchdog oscillator is always running if the Watchdog Timer is enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency. In order to allow Watchdog Timer operation with minimum power consumption, which can be important in reduced power modes, the Watchdog oscillator frequency is not tightly controlled. The Watchdog oscillator frequency will vary over temperature and power supply within a particular part, and may vary by processing across different parts. This variation should be taken into account when determining Watchdog reload values. Within a particular part, temperature and power supply variations can produce up to a 17 % frequency variation. Frequency variation between devices under the same operating conditions can be up to 30 %. 7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1) PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally identical but have somewhat different input possibilities and output connections. These possibilities are shown in Figure 7. The Main PLL can receive its input from either the IRC or the main oscillator and can potentially be used to provide the clocks to nearly everything on the device. The Alternate PLL receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the USB. The USB has timing needs that may not always be filled by the Main PLL. Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB clock through that route. The source for each clock must be selected via the CLKSEL registers and can be further reduced by clock dividers as needed. PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only the Main PLL is used, then its output frequency must be an integer multiple of all other clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional dividers to bring the output down to the desired frequencies. The minimum output divider value is 2, insuring that the output of the PLLs have a 50 % duty cycle. If the USB is used, the possibilities for the CPU clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the PLL0 output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in conjunction with the PLL can meet the precision and jitter specifications for USB. It is due to these limitations that the Alternate PLL is provided.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 63 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied up to a multiple of 48 MHz (192 MHz or 288 MHz as described above). 7.33.3 Wake-up timer The LPC178x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.33.4 Power control The LPC178x/7x support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, the peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. The LPC178x/7x also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 7.33.4.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence other than re-enabling the clock to the ARM core.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 64 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The DMA controller can continue to work in Sleep mode and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. 7.33.4.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The clock divider registers are automatically reset to zero. The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 7.33.4.3 Power-down mode Power-down mode does everything that Deep-sleep mode does but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and the clock selection multiplexers are set to use the system clock sysclk (the reset state). The clock divider control registers are automatically reset to zero. If the Watchdog timer is running, it will continue running in Power-down mode.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 65 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this, four IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 7.33.4.4 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before device operation can be restarted. The LPC178x/7x can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.33.4.5 Wake-up Interrupt Controller (WIC) The WIC allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 7.33.5 Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.33.6 Power domains The LPC178x/7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers. On the LPC178x/7x, I/O pads are powered by VDD(3V3), while VDD(REG)(3V3) powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC178x/7x application, a design can use two power options to manage power consumption.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 66 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly” while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC operates at very low power, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. There is no power drain from the RTC battery when VDD(REG)(3V3) is at nominal levels and VDD(REG)(3V3) > VBAT. Fig 8. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR POWER SELECTOR ULTRA-LOW POWER REGULATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aaf530 RTCX1 VBAT (typical 3.0 V) VDD(REG)(3V3) (typical 3.3 V) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VSSA LPC178x/7xLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 67 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.34 System control 7.34.1 Reset Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.33.3), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.34.2 Brownout detection The LPC178x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts a reset to inactivate the LPC178x/7x when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V (typical). This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.34.3 Code security (Code Read Protection - CRP) This feature of the LPC178x/7x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 68 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.34.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 7.34.5 AHB multilayer matrix The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (64 kB) SRAM, and the Boot ROM. The GPDMA can also access all of these memories. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 7.34.6 External interrupt inputs The LPC178x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode. 7.34.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC178x/7x is configured for 128 total interrupts. 7.35 Debug control Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 69 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 8. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on the required shelf lifetime. Please refer to the JEDEC spec for further details. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP 0.5 +4.6 V VIA analog input voltage on ADC related pins 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD(3V3) 2.4V [2] 0.5 +5.5 V VDD(3V3) 0 V 0.5 +3.6 V other I/O pins [2][3] 0.5 VDD(3V3) + 0.5 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature non-operating [4] 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [5] - 4000 VLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 70 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation Table 10. Thermal characteristics VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Parameter Min Typ Max Unit Tj(max) maximum junction temperature - - 125 C Table 11. Thermal resistance (LQFP packages) Tamb = 40 C to +85 C unless otherwise specified. Symbol Conditions Thermal resistance in C/W ±15 % LQFP208 LQFP144 ja JEDEC (4.5 in 4 in) 0 m/s 27.4 31.5 1 m/s 25.7 28.1 2.5 m/s 24.4 26.2 Single-layer (4.5 in 3 in) 0 m/s 35.4 43.2 1 m/s 31.2 35.7 2.5 m/s 29.2 32.8 jc - 8.8 7.8 jb - 15.4 13.8 Table 12. Thermal resistance value (TFBGA packages) Tamb = 40 C to +85 C unless otherwise specified. Symbol Conditions Thermal resistance in C/W ±15 % TFBGA208 TFBGA180 ja JEDEC (4.5 in 4 in) 0 m/s 41 45.5 1 m/s 35 38.3 2.5 m/s 31 33.8 8-layer (4.5 in 3 in) 0 m/s 34.9 38 1 m/s 30.9 33.5 2.5 m/s 28 29.8 jc - 8.3 8.9 jb - 13.6 12 Tj Tamb PD Rth j a – += LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 71 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 13. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3] 2.7 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [4] 2.1 3.0 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.7 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled [5][6] - 7- mA CCLK = 120 MHz; PLL enabled [5][7] - 51- mA active mode; code while(1){} executed from flash; all peripherals enabled; PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled [5][6] 14 CCLK = 120 MHz; PLL enabled [5][7] 100 mA Sleep mode [5][8] - 5- mA Deep-sleep mode [5][9] - 550 - A Power-down mode [5][9] - 280 - A IBAT battery supply current RTC running; part powered down; VDD(REG)(3V3) =0 V; Vi(VBAT) = 3.0 V; VDD(3V3) = 0 V. [10] - 1 - A part powered; VDD(REG)(3V3) = 3.3 V; Vi(VBAT) = 3.0 V [11] <10 nALPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 9 September 2014 72 of 122 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [15][16] [17] 0- 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3) --V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3) 0.4 --V VOL LOW-level output voltage IOL = 4 mA --0.4 V IOH HIGH-level output current VOH = VDD(3V3) 0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4- - mA IOHS HIGH-level short-circuit output current VOH =0V [18] - - 45 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [18] --50 mA Ipd pull-down current VI =5V 10 50 150 A Ipu pull-up current VI =0V 15 50 85 A VDD(3V3) < VI <5V 0 0 0 A I 2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3) --V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05 VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA --0.4 V ILI input leakage current VI = VDD(3V3) [19] - 24 A VI =5V - 10 22 A USB pins IOZ OFF-state output current 0V
