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1 1 1 0 0 BaudRate SelectedClock   8 2  – OVER CD = ----------------------------------------------- 438 32142D–06/2013 ATUC64/128/256L3/4U The baud rate is calculated with the following formula (OVER=0): The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. 20.6.1.3 Fractional Baud Rate in Asynchronous Mode The baud rate generator has a limitation: the source frequency is always a multiple of the baud rate. An approach to this problem is to integrate a high resolution fractional N clock generator, outputting fractional multiples of the reference source clock. This fractional part is selected with the Fractional Part field (BRGR.FP), and is activated by giving it a non-zero value. The resolution is one eighth of CD. The resulting baud rate is calculated using the following formula: The modified architecture is presented below: Table 20-3. Baud Rate Example (OVER=0) Source Clock (Hz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% BaudRate CLKUSART =      CD  16 Error 1 ExpectedBaudRate ActualBaudRate --------------------------------------------------     = – BaudRate SelectedClock 8 2  – OVER CD FP 8 + -------         = -------------------------------------------------------------------- 439 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-3. Fractional Baud Rate Generator 20.6.1.4 Baud Rate in Synchronous and SPI Mode If the USART is configured to operate in synchronous mode, the selected clock is divided by the BRGR.CD field. This does not apply when CLK is selected. When CLK is selected the external frequency must be at least 4.5 times lower than the system clock, and when either CLK or CLK_USART/DIV are selected, CD must be even to ensure a 50/50 duty cycle. If CLK_USART is selected, the generator ensures this regardless of value. 20.6.2 Receiver and Transmitter Control After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to either the Receiver Enable, or Transmitter Enable bit in the Control Register (CR.RXEN, or CR.TXEN). They may be enabled together and can be configured both before and after they have been enabled. The user can reset the USART receiver/transmitter at any time by writing a one to either the Reset Receiver (CR.RSTRX), or Reset Transmitter (CR.RSTTX) bit. This software reset clears status bits and resets internal state machines, immediately halting any communication. The user interface configuration registers will retain their values. The user can disable the receiver/transmitter by writing a one to either the Receiver Disable, or Transmitter Disable bit (CR.RXDIS, or CR.TXDIS). If the receiver is disabled during a character reception, the USART will wait for the current character to be received before disabling. If the transmitter is disabled during transmission, the USART will wait until both the current character and the character stored in the Transmitter Holding Register (THR) are transmitted before disabling. If a timeguard has been implemented it will remain functional during the transaction. USCLKS CD Modulus Control FP FP CD glitch-free logic 16-bit Counter OVER FIDI SYNC Sampling Divider CLK_USART CLK_USART/DIV Reserved CLK CLK BaudRate Clock Sampling Clock SYNC USCLKS = 3 >1 1 2 3 0 0 1 0 1 1 0 0 BaudRate SelectedClock CD = ------------------------------------- 440 32142D–06/2013 ATUC64/128/256L3/4U 20.6.3 Synchronous and Asynchronous Modes 20.6.3.1 Transmitter Operations The transmitter performs equally in both synchronous and asynchronous operating modes (MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the serial clock. The number of data bits is selected by the Character Length field (MR.CHRL) and the MR.MODE9 bit. Nine bits are selected by writing a one to MODE9, overriding any value in CHRL. The parity bit configuration is selected in the MR.PAR field. The Most Significant Bit First bit (MR.MSBF) selects which data bit to send first. The number of stop bits is selected by the MR.NBSTOP field. The 1.5 stop bit configuration is only supported in asynchronous mode. Figure 20-4. Character Transmit The characters are sent by writing to the Character to be Transmitted field (THR.TXCHR). The transmitter reports status with the Transmitter Ready (TXRDY) and Transmitter Empty (TXEMPTY) bits in the Channel Status Register (CSR). TXRDY is set when THR is empty. TXEMPTY is set when both THR and the transmit shift register are empty (transmission complete). Both TXRDY and TXEMPTY are cleared when the transmitter is disabled. Writing a character to THR while TXRDY is zero has no effect and the written character will be lost. Figure 20-5. Transmitter Status 20.6.3.2 Asynchronous Receiver If the USART is configured in an asynchronous operating mode (MR.SYNC = 0), the receiver will oversample the RXD input line by either 8 or 16 times the baud rate clock, as selected by the Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight consecutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample will determine the logical value on the line, in effect resulting in bit values being determined at the middle of the bit period. D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Start Bit Write THR D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit TXRDY TXEMPTY 441 32142D–06/2013 ATUC64/128/256L3/4U The number of data bits, endianess, parity mode, and stop bits are selected by the same bits and fields as for the transmitter (MR.CHRL, MODE9, MSBF, PAR, and NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the used protocol, and when the first stop bit has been sampled, the receiver will automatically begin looking for a new start bit, enabling resynchronization even if there is a protocol miss-match. Figure 20-6 and Figure 20-7 illustrate start bit detection and character reception in asynchronous mode. Figure 20-6. Asynchronous Start Bit Detection Figure 20-7. Asynchronous Character Reception 20.6.3.3 Synchronous Receiver In synchronous mode (SYNC=1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start bit. Configuration bits and fields are the same as in asynchronous mode. Sampling Clock (x16) RXD Start Detection Sampling Baud Rate Clock RXD Start Rejection Sampling 12345678 12345670 1234 12345678 9 10 11 12 13 14 15 16 D0 Sampling D0 D1 D2 D3 D4 D5 D6 D7 RXD Parity Bit Stop Bit Example: 8-bit, Parity Enabled Baud Rate Clock Start Detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 442 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-8. Synchronous Mode Character Reception 20.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Received Character field in the Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status Register (CSR.RXRDY) is set. If RXRDY is already set, RHR will be overwritten and the Overrun Error bit (CSR.OVRE) is set. Reading RHR will clear RXRDY, and writing a one to the Reset Status bit in the Control Register (CR.RSTSTA) will clear OVRE. Figure 20-9. Receiver Status 20.6.3.5 Parity The USART supports five parity modes selected by MR.PAR. The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 443. If even parity is selected, the parity bit will be a zero if there is an even number of ones in the data character, and if there is an odd number it will be a one. For odd parity the reverse applies. If space or mark parity is chosen, the parity bit will always be a zero or one, respectively. See Table 20-4. D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Sampling Parity Bit Stop Bit Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write CR RXRDY OVRE D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Parity Bit Stop Bit RSTSTA = 1 Read RHR Table 20-4. Parity Bit Examples Alphanum Character Hex Bin Parity Mode Odd Even Mark Space None A 0x41 0100 0001 1 0 1 0 - V 0x56 0101 0110 1 0 1 0 - R 0x52 0101 0010 0 1 1 0 - 443 32142D–06/2013 ATUC64/128/256L3/4U The receiver will report parity errors in CSR.PARE, unless parity is disabled. Writing a one to CR.RSTSTA will clear PARE. See Figure 20-10 Figure 20-10. Parity Error 20.6.3.6 Multidrop Mode If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one. By writing a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be transmitted as an address. Receiving a character with a one as parity bit will set PARE. 20.6.3.7 Transmitter Timeguard The timeguard feature enables the USART to interface slow devices by inserting an idle state on the TXD line in between two characters. This idle state corresponds to a long stop bit, whose duration is selected by the Timeguard Value field in the Transmitter Timeguard Register (TTGR.TG). The transmitter will hold the TXD line high for TG bit periods, in addition to the number of stop bits. As illustrated in Figure 20-11, the behavior of TXRDY and TXEMPTY is modified when TG has a non-zero value. If a pending character has been written to THR, the TXRDY bit will not be set until this characters start bit has been sent. TXEMPTY will remain low until the timeguard transmission has completed. Figure 20-11. Timeguard Operation D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Bad Parity Bit Stop Bit Baud Rate Clock Write CR PARE RXRDY RSTSTA = 1 D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Start Bit TG = 4 Write THR D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit TXRDY TXEMPTY TG = 4 444 32142D–06/2013 ATUC64/128/256L3/4U Table 20-5. Maximum Baud Rate Dependent Timeguard Durations 20.6.3.8 Receiver Time-out The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of variable-length frames by detection of selectable idle durations on the RXD line. The value written to TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the amount of inactive bit periods match the initial counter value. If a time-out has not occurred, the counter will reload and restart every time a new character arrives. A time-out sets the TIMEOUT bit in CSR. Clearing TIMEOUT can be done in two ways: • Writing a one to the Start Time-out bit (CR.STTTO). This also aborts count down until the next character has been received. • Writing a one to the Reload and Start Time-out bit (CR.RETTO). This also reloads the counter and restarts count down immediately. Figure 20-12. Receiver Time-out Block Diagram Table 20-6. Maximum Time-out Period Baud Rate (bit/sec) Bit time (µs) Timeguard (ms) 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 Baud Rate (bit/sec) Bit Time (µs) Time-out (ms) 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 16-bit Time-out Counter 0 TO TIMEOUT Baud Rate Clock = Character Received RETTO Load Clock 16-bit Value STTTO 1 D Q Clear 445 32142D–06/2013 ATUC64/128/256L3/4U 20.6.3.9 Framing Error The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit. Figure 20-13. Framing Error Status 20.6.3.10 Transmit Break When TXRDY is set, the user can request the transmitter to generate a break condition on the TXD line by writing a one to The Start Break bit (CR.STTBRK). The break is treated as a normal 0x00 character transmission, clearing TXRDY and TXEMPTY, but with zeroes for preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit (CR.STBRK) will stop the generation of new break characters, and send ones for TG duration or at least 12 bit periods, ensuring that the receiver detects end of break, before resuming normal operation. Figure 20-14 illustrates STTBRK and STPBRK effect on the TXD line. Writing to STTBRK and STPBRK simultaneously can lead to unpredictable results. Writes to THR before a pending break has started will be ignored. 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 Baud Rate (bit/sec) Bit Time (µs) Time-out (ms) D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write CR FRAME RXRDY RSTSTA = 1 446 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-14. Break Transmission 20.6.3.11 Receive Break A break condition is assumed when incoming data, parity, and stop bits are zero. This corresponds to a framing error, but FRAME will remain zero while the Break Received/End Of Break bit (CSR.RXBRK) is set. Writing a one to CR.RSTSTA will clear RXBRK. An end of break will also set RXBRK, and is assumed when TX is high for at least 2/16 of a bit period in asynchronous mode, or when a high level is sampled in synchronous mode. 20.6.3.12 Hardware Handshaking The USART features an out-of-band hardware handshaking flow control mechanism, implementable by connecting the RTS and CTS pins with the remote device, as shown in Figure 20- 15. Figure 20-15. Connection with a Remote Device for Hardware Handshaking Writing 0x2 to the MR.MODE field configures the USART to operate in this mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the receivers RTS pin is high, the transmitters CTS pin will also be high and only the active character transactions will be completed. Allocating a new buffer to the DMA controller by clearing RXBUFF, will drive the RTS pin low, allowing the transmitter to resume transmission. Detected level changes on the CTS pin can trigger interrupts, and are reported by the CTS Input Change bit in the Channel Status Register (CSR.CTSIC). Figure 20-16 illustrates receiver functionality, and Figure 20-17 illustrates transmitter functionality. D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write CR TXRDY TXEMPTY STTBRK = 1 STPBRK = 1 Break Transmission End of Break USART TXD CTS Remote Device RXD RXD TXD RTS RTS CTS 447 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-16. Receiver Behavior when Operating with Hardware Handshaking Figure 20-17. Transmitter Behavior when Operating with Hardware Handshaking Figure 20-18. 20.6.4 SPI Mode The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting synchronous, full-duplex communication, in both master and slave mode. Writing 0xE (master) or 0xF (slave) to MR.MODE will enable this mode. A SPI in master mode controls the data flow to and from the other SPI devices, who are in slave mode. It is possible to let devices take turns being masters (aka multi-master protocol), and one master may shift data simultaneously into several slaves, but only one slave may respond at a time. A slave is selected when its slave select (NSS) signal has been raised by the master. The USART can only generate one NSS signal, and it is possible to use standard I/O lines to address more than one slave. 20.6.4.1 Modes of Operation The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In master mode this is connected to TXD, and in slave mode to RXD. • Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In master mode this is connected to RXD, and in slave mode to TXD. • Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both modes this is connected to CLK. • Slave Select (NSS): This control line allows the master to select or deselect a slave. In master mode this is connected to RTS, and in slave mode to CTS. Changing SPI mode after initial configuration has to be followed by a transceiver software reset in order to avoid unpredictable behavior. 20.6.4.2 Baud Rate The baud rate generator operates as described in ”Baud Rate in Synchronous and SPI Mode” on page 439, with the following requirements: In SPI Master Mode: RTS RXBUFF Write CR RXEN = 1 RXD RXDIS = 1 CTS TXD 448 32142D–06/2013 ATUC64/128/256L3/4U • The Clock Selection field (MR.USCLKS) must not equal 0x3 (external clock, CLK). • The Clock Output Select bit (MR.CLKO) must be one. • The BRGR.CD field must be at least 0x4. • If USCLKS is one (internal divided clock, CLK_USART/DIV), the value in CD has to be even, ensuring a 50:50 duty cycle. CD can be odd if USCLKS is zero (internal clock, CLK_USART). In SPI Slave Mode: • CLK frequency must be at least four times lower than the system clock. 20.6.4.3 Data Transfer • Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL), and SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits are shifted and sampled, resulting in four non-interoperable protocol modes see Table 20-7. A master/slave pair must use the same configuration, and the master must be reconfigured if it is to communicate with slaves using different configurations. See Figures 20-19 and 20-20. Figure 20-19. SPI Transfer Format (CPHA=1, 8 bits per transfer) Table 20-7. SPI Bus Protocol Modes SPI Bus Protocol Mode CPOL CPHA 0 01 1 00 2 11 3 10 CLK cycle (for reference) CLK (CPOL= 1) MOSI SPI Master ->TXD SPI Slave ->RXD MISO SPI Master ->RXD SPI Slave ->TXD NSS SPI Master ->RTS SPI Slave ->CTS MSB MSB 1 CLK (CPOL= 0) 3 5 6 7 8 4 3 2 1 LSB 6 6 5 5 4 3 2 1 LSB 2 4 449 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-20. SPI Transfer Format (CPHA=0, 8 bits per transfer) 20.6.4.4 Receiver and Transmitter Control See ”Transmitter Operations” on page 440, and ”Receiver Operations” on page 442. 20.6.4.5 Character Transmission and Reception In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of transmission, and released high one bit period after every character transmission. A delay for at least three bit periods is always inserted in between characters. In order to address slave devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS is one, is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS). In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent while THR is empty, and TXD will be high during character transmission, as if 0xFF was being sent. If a new character is written to THR it will be sent correctly during the next transmission slot. Writing a one to CR.RSTSTA will clear UNRE. To ensure correct behavior of the receiver in SPI slave mode, the master device sending the frame must ensure a minimum delay of one bit period in between each character transmission. 20.6.4.6 Receiver Time-out Receiver Time-out’s are not possible in SPI mode as the baud rate clock is only active during data transfers. 20.6.5 LIN Mode The USART features a LIN (Local Interconnect Network) 1.3 and 2.0 compliant mode, embedding full error checking and reporting, automatic frame processing with up to 256 data bytes, CLK cycle (for reference) CLK (CPOL= 0) CLK (CPOL= 1) MOSI SPI Master -> TXD SPI Slave -> RXD MISO SPI Master -> RXD SPI Slave -> TXD NSS SPI Master -> RTS SPI Slave -> CTS MSB 6 5 MSB 6 5 4 4 3 3 2 2 1 1 LSB LSB 1 2 3 4 5 6 7 8 450 32142D–06/2013 ATUC64/128/256L3/4U customizable response data lengths, and requires minimal CPU resources. Writing 0xA (master) or 0xB (slave) to MR.MODE enables this mode. 20.6.5.1 Modes of operation Changing LIN mode after initial configuration has to be followed by a transceiver software reset in order to avoid unpredictable behavior. 20.6.5.2 Receiver and Transmitter Control See Section “20.6.2” on page 439. 20.6.5.3 Baud Rate Configuration The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR), See Section “20.6.1.1” on page 437. 20.6.5.4 Character Transmission and Reception See ”Transmitter Operations” on page 440, and ”Receiver Operations” on page 442. 20.6.5.5 Header Transmission (Master Node Configuration) All LIN frames start with a header sent by the master. As soon as the identifier has been written to the Identifier Character field in the LIN Identifier Register (LINIR.IDCHR), TXRDY is cleared and the header is sent. The header consists of a Break, Sync, and Identifier field. TXRDY is set when the identifier has been transferred into the transmitters shift register. The Break field consists of 13 dominant bits, the break, and one recessive bit, the break delimiter. The Sync field is the character 0x55. The Identifier field contains the Identifier as written to IDCHR. The identifier parity bits can be generated automatically (see Section 20.6.5.8). Figure 20-21. Header Transmission 20.6.5.6 Header Reception (Slave Node Configuration) The USART stays idle until it detects a break field, consisting of at least 11 consecutive dominant bits (zeroes) on the bus. A received break will set the Lin Break bit (CSR.LINBK). The Sync field is used to synchronize the baud rate (see Section 20.6.5.7). IDCHR is updated and the LIN Identifier bit (CSR.LINID) is set when the Identifier has been received. The Identifier parity bits can be automatically checked (see Section 20.6.5.8). Writing a one to RSTSTA will clear LINBK and LINID. TXD Baud Rate Clock Start Bit Write LINIR 10101010 TXRDY Stop Bit Start Bit Break Field ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 13 dominant bits (at 0) Stop Bit Break Delimiter 1 recessive bit (at 1) Synch Byte = 0x55 LINIR ID 451 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-22. Header Reception 20.6.5.7 Slave Node Synchronization Synchronization is only done by the slave. If the Sync field is not 0x55, an Inconsistent Sync Field error (CSR.LINISFE) is generated. The time between falling edges is measured by a 19-bit counter, driven by the sampling clock (see Section 20.6.1). Figure 20-23. Sync Field The counter starts when the Sync field start bit is detected, and continues for eight bit periods. The 16 most significant bits (counter value divided by 8) becomes the new clock divider (BRGR.CD), and the three least significant bits (the remainder) becomes the new fractional part (BRGR.FP). Figure 20-24. Slave Node Synchronization The synchronization accuracy depends on: • The theoretical slave node clock frequency; nominal clock frequency (FNom) • The baud rate Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start Bit 10101010 Stop Bit Start Bit ID0 ID1 ID2 ID4 ID3 ID6 ID5 ID7 Stop Bit Synch Byte = 0x55 Baud Rate Clock RXD Write US_CR With RSTSTA=1 US_LINIR LINID Start bit Stop bit Synch Field 8 Tbit 2 Tbit 2 Tbit 2 Tbit 2 Tbit RXD Baud Rate Clock LINIDRX Synchro Counter 000_0011_0001_0110_1101 BRGR Clcok Divider (CD) 0000_0110_0010_1101 BRGR Fractional Part (FP) 101 Initial CD Initial FP Reset Start Bit 10101010 Stop Bit Start Bit Break Field ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 13 dominant bits (at 0) Stop Bit Break Delimiter 1 recessive bit (at 1) Synch Byte = 0x55 452 32142D–06/2013 ATUC64/128/256L3/4U • The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x) The following formula is used to calculate synchronization deviation, where FSLAVE is the real slave node clock frequency, and FTOL_UNSYNC is the difference between FNom and FSLAVE According to the LIN specification, FTOL_UNSYNCH may not exceed ±15%, and the bit rates between two nodes must be within ±2% of each other, resulting in a maximal BaudRate_deviation of ±1%. Minimum nominal clock frequency with a fractional part: Examples: • Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 2.64 MHz • Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 1.47 MHz • Baud rate = 1 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 132 kHz • Baud rate = 1 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 74 kHz If the fractional part is not used, the synchronization accuracy is much lower. The 16 most significant bits, added with the first least significant bit, becomes the new clock divider (CD). The equation of the baud rate deviation is the same as above, but the constants are: Minimum nominal clock frequency without a fractional part: Examples: • Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 19.12 MHz • Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 9.71 MHz • Baud rate = 1 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 956 kHz • Baud rate = 1 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 485 kHz 20.6.5.8 Identifier Parity An identifier field consists of two sub-fields; the identifier and its parity. Bits 0 to 5 are assigned to the identifier, while bits 6 and 7 are assigned to parity. Automatic parity management is disabled by writing a one to the Parity Disable bit in the LIN Mode register (LINMR.PARDIS). BaudRate_deviation 100   8 2 OVER    – +   BaudRate 8 FSLAVE   --------------------------------------------------------------------------------------------------   =   % BaudRate_deviation 100   8 2 OVER    – +   BaudRate 8 FTOL_UNSYNC 100 -----------------------------------     xFNom   --------------------------------------------------------------------------------------------------       = % –0.5    +0.5 -1    +1 FNom  min 100   0.5 8 2 OVER     – + 1  BaudRate 8 –15 100 --------- + 1       1%  ------------------------------------------------------------------------------------------------------       = Hz –4    +4 -1    +1 FNom  min 100   4 8 2 OVER     – + 1  Baudrate 8 –15 100 --------- + 1       1%  -----------------------------------------------------------------------------------------------       = Hz 453 32142D–06/2013 ATUC64/128/256L3/4U • PARDIS=0: During header transmission, the parity bits are computed and in the shift register they replace bits six and seven from IDCHR. During header reception, the parity bits are checked and can generate a LIN Identifier Parity Error (see Section 20.6.6). Bits six and seven in IDCHR read as zero when receiving. • PARDIS=1: During header transmission, all the bits in IDCHR are sent on the bus. During header reception, all the bits in IDCHR are updated with the received Identifier. 20.6.5.9 Node Action After an identifier transaction, a LIN response mode has to be selected. This is done in the Node Action field (LINMR.NACT). Below are some response modes exemplified in a small LIN cluster: • Response, from master to slave1: Master: NACT=PUBLISH Slave1: NACT=SUBSCRIBE Slave2: NACT=IGNORE • Response, from slave1 to master: Master: NACT=SUBSCRIBE Slave1: NACT=PUBLISH Slave2: NACT=IGNORE • Response, from slave1 to slave2: Master: NACT=IGNORE Slave1: NACT=PUBLISH Slave2: NACT=SUBSCRIBE 20.6.5.10 LIN Response Data Length The response data length is the number of data fields (bytes), excluding the checksum. Figure 20-25. Response Data Length The response data length can be configured, either by the user, or automatically by bits 4 and 5 in the Identifier (IDCHR), in accordance to LIN 1.1. The user selects mode by writing to the Data Length Mode bit (LINMR.DML): • DLM=0: the response data length is configured by the user by writing to the 8-bit Data Length Control field (LINMR.DLC). The response data length equals DLC + 1 bytes. User configuration: 1 - 256 data fields (DLC+1) Identifier configuration: 2/4/8 data fields Sync Break Sync Field Identifier Field Checksum Field Data Field Data Field Data Field Data Field 454 32142D–06/2013 ATUC64/128/256L3/4U • DLM=1: the response data length is defined by the Identifier bits according to the table below. 20.6.5.11 Checksum The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP), and the Checksum Disable (LINMR.CHKDIS) bits. TXRDY will not be set after the last THR data write if enabled. Writing a one to CHKDIS will disable the automatic checksum generation/checking, and the user may send/check this last byte manually, disguised as a normal data. The checksum is an inverted 8-bit sum with carry, either: • over all data bytes, called a classic checksum. This is used for LIN 1.3 compliant slaves, and automatically managed when CHKDIS=0, and CHKTYP=1. • over all data bytes and the protected identifier, called an enhanced checksum. This is used for LIN 2.0 compliant slaves, and automatically managed when CHKDIS=0, and CHKTYP=0. 20.6.5.12 Frame Slot Mode A LIN master can be configured to use frame slots with a pre-defined minimum length. Writing a one to the Frame Slot Mode Disable bit (LINMR.FSDIS) disables this mode. This mode will not allow TXRDY to be set after a frame transfer until the entire frame slot duration has elapsed, in effect preventing the master from sending a new header. The LIN Transfer Complete bit (CSR.LINTC) will still be set after the checksum has been sent. Writing a one to CR.RSTST clears LINTC. Figure 20-26. Frame Slot Mode with Automatic Checksum The minimum frame slot size is determined by TFrame_Maximum, and calculated below (all values in bit periods): • THeader_Nominal = 34 Table 20-8. Response Data Length if DLM = 1 IDCHR[5] IDCHR[4] Response Data Length [bytes] 00 2 01 2 10 4 11 8 Break Synch Protected Identifier Data N Checksum Header Interframe space Response space Frame Frame slot = TFrame_Maximum Response TXRDY Write THR Write LINID Data 1 Data 2 Data 3 Data3 Data N-1 Data N Frame Slot Mode Disabled Frame Slot Mode Enabled LINTC Data 1 455 32142D–06/2013 ATUC64/128/256L3/4U • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)(Note:) Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3) If the Checksum is sent (CHKDIS=0): • TResponse_Nominal = 10 x (NData + 1) • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1) • TFrame_Maximum = 77 + 14 x DLC If the Checksum is not sent (CHKDIS=1): • TResponse_Nominal = 10 x NData • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1) • TFrame_Maximum = 63 + 14 x DLC 20.6.6 LIN Errors These error bits are cleared by writing a one to CSR.RSTSTA. 20.6.6.1 Slave Not Responding Error (CSR.LINSNRE) This error is generated if no valid message appears within the TFrame_Maximum time frame slot, while the USART is expecting a response from another node (NACT=SUBSCRIBE). 20.6.6.2 Checksum Error (CSR.LINCE) This error is generated if the received checksum is wrong. This error can only be generated if the checksum feature is enabled (CHKDIS=0). 20.6.6.3 Identifier Parity Error (CSR.LINIPE) This error is generated if the identifier parity is wrong. This error can only be generated if parity is enabled (PARDIS=0). 20.6.6.4 Inconsistent Sync Field Error (CSR.LINISFE) This error is generated in slave mode if the Sync Field character received is not 0x55. Synchronization procedure is aborted. 20.6.6.5 Bit Error (CSR.LINBE) This error is generated if the value transmitted by the USART on Tx differs from the value sampled on Rx. If a bit error is detected, the transmission is aborted at the next byte border. 20.6.7 LIN Frame Handling 20.6.7.1 Master Node Configuration • Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver • Select LIN mode and master node by writing to MR.MODE • Configure the baud rate by writing to CD and FP in BRGR • Configure the frame transfer by writing to NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FSDIS, and DLC in LINMR • Check that CSR.TXRDY is one • Send the header by writing to LINIR.IDCHR The following procedure depends on the NACT setting: 456 32142D–06/2013 ATUC64/128/256L3/4U • Case 1: NACT=PUBLISH, the USART sends a response – Wait until TXRDY is a one – Send a byte by writing to THR.TXCHR – Repeat the two previous steps until there is no more data to send – Wait until CSR.LINTC is a one – Check for LIN errors • Case 2: NACT=SUBSCRIBE, the USART receives a response – Wait until RXRDY is a one – Read RHR.RXCHR – Repeat the two previous steps until there is no more data to read – Wait until LINTC is a one – Check for LIN errors • Case 3: NACT=IGNORE, the USART is not concerned by a response – Wait until LINTC is a one – Check for LIN errors Figure 20-27. Master Node Configuration, NACT=PUBLISH Frame Break Synch Protected Identifier Data 1 Data N Checksum TXRDY Write THR Write LINIR Data 1 Data 2 Data 3 Data N-1 Data N RXRDY Header Interframe space Response space Frame slot = TFrame_Maximum Data3 Response LINTC FSDIS=1 FSDIS=0 457 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-28. Master Node Configuration, NACT=SUBSCRIBE Figure 20-29. Master Node Configuration, NACT=IGNORE 20.6.7.2 Slave Node Configuration This is identical to the master node configuration above, except for: • LIN mode selected in MR.MODE is slave • When the baud rate is configured, wait until CSR.LINID is a one, then; • Check for LINISFE and LINPE errors, clear errors and LINIDby writing a one to RSTSTA • Read IDCHR • Configure the frame transfer by writing to NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, and DLC in LINMR IMPORTANT: if NACT=PUBLISH, and this field is already correct, the LINMR register must still be written with this value in order to set TXRDY, and to request the corresponding Peripheral DMA Controller write transfer. The different NACT settings result in the same procedure as for the master node, see page 455. Break Synch Protected Identifier Data 1 Data N Checksum TXRDY Read RHR Write LINIR Data 1 Data N-1 Data N-1 RXRDY Data N-2 Data N Header Interframe Response space space Frame Frame slot = TFrame_Maximum Data3 Response LINTC FSDIS=1 FSDIS=0 TXRDY Write LINIR RXRDY LINTC Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Header Interframe Response space space Frame Frame slot = TFrame_Maximum Data3 Response FSDIS=1 FSDIS=0 458 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-30. Slave Node Configuration, NACT=PUBLISH Figure 20-31. Slave Node Configuration, NACT=SUBSCRIBE Figure 20-32. Slave Node Configuration, NACT=IGNORE 20.6.8 LIN Frame Handling With The Peripheral DMA Controller The USART can be used together with the Peripheral DMA Controller in order to transfer data without processor intervention. The DMA Controller uses the TXRDY and RXRDY bits, to trigger one byte writes or reads. It always writes to THR, and it always reads RHR. Break Synch Protected Identifier Data 1 Data N Checksum TXRDY Write THR Read LINID Data 1 Data 3 Data N-1 Data N RXRDY LINIDRX Data 2 LINTC TXRDY Read RHR Read LINID RXRDY LINIDRX LINTC Break Synch Protected Identifier Data 1 Data N Checksum Data 1 Data N-1 Data N-2 Data N-1 Data N TXRDY Read RHR Read LINID RXRDY LINIDRX LINTC Break Synch Protected Identifier Data 1 Data N Checksum Data N-1 459 32142D–06/2013 ATUC64/128/256L3/4U 20.6.8.1 Master Node Configuration The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration: • PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write buffer. • PDCM=1: LIN configuration is written by the DMA Controller to THR, and is stored in the write buffer. Since data transfer size is a byte, the transfer is split into two accesses. The first writes the NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS bits, while the second writes the DLC field. If NACT=PUBLISH, the write buffer will also contain the Identifier. When NACT=SUBSCRIBE, the read buffer contains the data. Figure 20-33. Master Node with Peripheral DMA Controller (PDCM=0) Figure 20-34. Master Node with Peripheral DMA Controller (PDCM=1) | | | | RXRDY TXRDY Peripheral bus USART LIN CONTROLLER DATA 0 DATA N | | | | READ BUFFER NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE Peripheral DMA Controller RXRDY Peripheral bus DATA 0 DATA 1 DATA N WRITE BUFFER Peripheral DMA Controller USART LIN CONTROLLER | | | | | | | | NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC IDENTIFIER DATA 0 DATA N WRITE BUFFER RXRDY Peripheral bus DLC IDENTIFIER DATA 0 DATA N WRITE BUFFER RXRDY READ BUFFER NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE Peripheral DMA Controller Peripheral DMA Controller USART LIN CONTROLLER NACT PARDIS CHKDIS CHKTYP DLM FSDIS USART LIN CONTROLLER TXRDY Peripheral bus 460 32142D–06/2013 ATUC64/128/256L3/4U 20.6.8.2 Slave Node Configuration In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the write buffer, while the read buffer contains the data when NACT=SUBSCRIBE. IMPORTANT: if in slave mode, NACT is already configured correctly as PUBLISH, the LINMR register must still be written with this value in order to set TXRDY, and to request the corresponding Peripheral DMA Controller write transfer. Figure 20-35. Slave Node with Peripheral DMA Controller 20.6.9 Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. By writing to the Wakeup Signal Type bit (LINMR.WKUPTYP), the user can choose to send either a LIN 1.3 (WKUPTYP=1), or a LIN 2.0 (WKUPTYP=0) compliant wakeup request. Writing a one to the Send LIN Wakeup Signal bit (CR.LINWKUP), transmits a wakeup, and when completed sets LINTC. According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order to impose eight successive dominant bits. According to LIN 2.0, the wakeup request is issued by forcing the bus into the dominant state for 250µs to 5ms. Sending the character 0xF0 does this, regardless of baud rate. • Baud rate max = 20 kbit/s -> one bit period = 50µs -> five bit periods = 250µs • Baud rate min = 1 kbit/s -> one bit period = 1ms -> five bit periods = 5ms 20.6.10 Bus Idle Time-out LIN bus inactivity should eventually cause slaves to time-out and enter sleep mode. LIN 1.3 specifies this to 25000 bit periods, whilst LIN 2.0 specifies 4seconds. For the time-out counter operation see Section 20.6.3.8 ”Receiver Time-out” on page 444. | | | | | | | | DATA 0 DATA N RXRDY Peripheral Bus READ BUFFER NACT = SUBSCRIBE DATA 0 DATA N TXRDY Peripheral bus WRITE BUFFER USART LIN CONTROLLER USART LIN CONTROLLER Peripheral DMA Controller Peripheral DMA Controller Table 20-9. Receiver Time-out Values (RTOR.TO) LIN Specification Baud Rate Time-out period TO 2.0 1 000 bit/s 4s 4 000 2 400 bit/s 9 600 9 600 bit/s 38 400 19 200 bit/s 76 800 20 000 bit/s 80 000 1.3 - 25 000 bit periods 25 000 461 32142D–06/2013 ATUC64/128/256L3/4U 20.6.11 Test Modes The internal loopback feature enables on-board diagnostics, and allows the USART to operate in three different test modes, with reconfigured pin functionality, as shown below. 20.6.11.1 Normal Mode During normal operation, a receivers RXD pin is connected to a transmitters TXD pin. Figure 20-36. Normal Mode Configuration 20.6.11.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is also sent to the TXD pin, as shown in Figure 20-37. Transmitter configuration has no effect. Figure 20-37. Automatic Echo Mode Configuration 20.6.11.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 20-38. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 20-38. Local Loopback Mode Configuration 20.6.11.4 Remote Loopback Mode Remote loopback mode connects the RXD pin to the TXD pin, as shown in Figure 20-39. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Receiver Transmitter RXD TXD Receiver Transmitter RXD TXD Receiver Transmitter RXD TXD 1 462 32142D–06/2013 ATUC64/128/256L3/4U Figure 20-39. Remote Loopback Mode Configuration 20.6.12 Write Protection Registers To prevent single software errors from corrupting USART behavior, certain address spaces can be write-protected by writing the correct Write Protect KEY and a one to the Write Protect Enable bit in the Write Protect Mode Register (WPMR.WPKEY, and WPMR.WPEN). Disabling the write protection is done by writing the correct key, and a zero to WPEN. Write attempts to a write protected register are detected and the Write Protect Violation Status bit in the Write Protect Status Register (WPSR.WPVS) is set, while the Write Protect Violation Source field (WPSR.WPVSRC) indicates the targeted register. Writing the correct key to the Write Protect KEY bit (WPMR.WPKEY) clears WPVSRC and WPVS. The protected registers are: • ”Mode Register” on page 466 • ”Baud Rate Generator Register” on page 476 • ”Receiver Time-out Register” on page 477 • ”Transmitter Timeguard Register” on page 478 Receiver Transmitter RXD TXD 1 463 32142D–06/2013 ATUC64/128/256L3/4U 20.7 User Interface Note: 1. Values in the Version Register vary with the version of the IP block implementation. Table 20-10. USART Register Memory Map Offset Register Name Access Reset 0x0000 Control Register CR Write-only 0x00000000 0x0004 Mode Register MR Read-write 0x00000000 0x0008 Interrupt Enable Register IER Write-only 0x00000000 0x000C Interrupt Disable Register IDR Write-only 0x00000000 0x0010 Interrupt Mask Register IMR Read-only 0x00000000 0x0014 Channel Status Register CSR Read-only 0x00000000 0x0018 Receiver Holding Register RHR Read-only 0x00000000 0x001C Transmitter Holding Register THR Write-only 0x00000000 0x0020 Baud Rate Generator Register BRGR Read-write 0x00000000 0x0024 Receiver Time-out Register RTOR Read-write 0x00000000 0x0028 Transmitter Timeguard Register TTGR Read-write 0x00000000 0x0054 LIN Mode Register LINMR Read-write 0x00000000 0x0058 LIN Identifier Register LINIR Read-write 0x00000000 0x00E4 Write Protect Mode Register WPMR Read-write 0x00000000 0x00E8 Write Protect Status Register WPSR Read-only 0x00000000 0x00FC Version Register VERSION Read-only 0x–(1) 464 32142D–06/2013 ATUC64/128/256L3/4U 20.7.1 Control Register Name: CR Access Type: Write-only Offset: 0x0 Reset Value: 0x00000000 • LINWKUP: Send LIN Wakeup Signal Writing a zero to this bit has no effect. Writing a one to this bit will sends a wakeup signal on the LIN bus. • LINABT: Abort LIN Transmission Writing a zero to this bit has no effect. Writing a one to this bit will abort the current LIN transmission. • RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select Writing a zero to this bit has no effect. Writing a one to this bit when USART is not in SPI master mode drives RTS pin high. Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin). • RTSEN/FCS: Request to Send Enable/Force SPI Chip Select Writing a zero to this bit has no effect. Writing a one to this bit when USART is not in SPI master mode drives RTS low. Writing a one to this bit when USART is in SPI master mode when; FCS=0: has no effect. FCS=1: forces NSS (RTS pin) low, even if USART is not transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). • RETTO: Rearm Time-out Writing a zero to this bit has no effect. Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT. • RSTNACK: Reset Non Acknowledge Writing a zero to this bit has no effect. Writing a one to this bit clears CSR.NACK. • SENDA: Send Address Writing a zero to this bit has no effect. Writing a one to this bit will in multidrop mode send the next character written to THR as an address. • STTTO: Start Time-out Writing a zero to this bit has no effect. Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has been received. CSR.TIMEOUT is also cleared. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 – – LINWKUP LINABT RTSDIS/RCS RTSEN/FCS – – 15 14 13 12 11 10 9 8 RETTO RSTNACK – SENDA STTTO STPBRK STTBRK RSTSTA 76543210 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – 465 32142D–06/2013 ATUC64/128/256L3/4U • STPBRK: Stop Break Writing a zero to this bit has no effect. Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least 12 bit periods. No effect if no break is being transmitted. • STTBRK: Start Break Writing a zero to this bit has no effect. Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift register have been sent. No effect if a break signal is already being generated. • RSTSTA: Reset Status Bits Writing a zero to this bit has no effect. Writing a one to this bit will clear the following bits in CSR: PARE, FRAME, OVRE, LINBE, LINSFE, LINIPE, LINCE, LINSNRE, and RXBRK. • TXDIS: Transmitter Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the transmitter. • TXEN: Transmitter Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the transmitter if TXDIS is zero. • RXDIS: Receiver Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the receiver. • RXEN: Receiver Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the receiver if RXDIS is zero. • RSTTX: Reset Transmitter Writing a zero to this bit has no effect. Writing a one to this bit will reset the transmitter. • RSTRX: Reset Receiver Writing a zero to this bit has no effect. Writing a one to this bit will reset the receiver. 466 32142D–06/2013 ATUC64/128/256L3/4U 20.7.2 Mode Register Name: MR Access Type: Read-write Offset: 0x4 Reset Value: 0x00000000 This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • OVER: Oversampling Mode 0: Oversampling at 16 times the baud rate. 1: Oversampling at 8 times the baud rate. • CLKO: Clock Output Select 0: The USART does not drive the CLK pin. 1: The USART drives the CLK pin unless USCLKS selects the external clock. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode: MSBF=0: Least Significant Bit is sent/received first. MSBF=1: Most Significant Bit is sent/received first. If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices. CPOL=0: The inactive state value of CLK is logic level zero. CPOL=1: The inactive state value of CLK is logic level one. 31 30 29 28 27 26 25 24 ––––– – 23 22 21 20 19 18 17 16 – – – INACK OVER CLKO MODE9 MSBF/CPOL 15 14 13 12 11 10 9 8 CHMODE NBSTOP PAR SYNC/CPHA 76543210 CHRL USCLKS MODE 467 32142D–06/2013 ATUC64/128/256L3/4U • CHMODE: Channel Mode • NBSTOP: Number of Stop Bits • PAR: Parity Type • SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase If USART does not operate in SPI Mode (MODE is  0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode. If USART operates in SPI Mode, CPHA determines which edge of CLK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. CPHA = 0: Data is changed on the leading edge of CLK and captured on the following edge of CLK. CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK. Table 20-11. CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo. Receiver input is connected to the TXD pin. 1 0 Local Loopback. Transmitter output is connected to the Receiver input. 1 1 Remote Loopback. RXD pin is internally connected to the TXD pin. Table 20-12. NBSTOP Asynchronous (SYNC=0) Synchronous (SYNC=1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved Table 20-13. PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode 468 32142D–06/2013 ATUC64/128/256L3/4U • CHRL: Character Length. • USCLKS: Clock Selection Note: 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter. • MODE Table 20-14. CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits Table 20-15. USCLKS Selected Clock 0 0 CLK_USART 0 1 CLK_USART/DIV(1) 1 0 Reserved 1 1 CLK Table 20-16. MODE Mode of the USART 0 0 0 0 Normal 0 0 1 0 Hardware Handshaking 1 0 1 0 LIN Master 1 0 1 1 LIN Slave 1 1 1 0 SPI Master 1 1 1 1 SPI Slave Others Reserved 469 32142D–06/2013 ATUC64/128/256L3/4U 20.7.3 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x8 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 – – LINSNRE LINCE LINIPE LINISFE LINBE – 23 22 21 20 19 18 17 16 – – – – CTSIC – – – 15 14 13 12 11 10 9 8 LINTC LINID NACK/LINBK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE – – RXBRK TXRDY RXRDY 470 32142D–06/2013 ATUC64/128/256L3/4U 20.7.4 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0xC Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 – – LINSNRE LINCE LINIPE LINISFE LINBE – 23 22 21 20 19 18 17 16 – – – – CTSIC – – – 15 14 13 12 11 10 9 8 LINTC LINID NACK/LINBK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE – – RXBRK TXRDY RXRDY 471 32142D–06/2013 ATUC64/128/256L3/4U 20.7.5 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 – – LINSNRE LINCE LINIPE LINISFE LINBE – 23 22 21 20 19 18 17 16 – – – – CTSIC – – – 15 14 13 12 11 10 9 8 LINTC LINID NACK/LINBK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE – – RXBRK TXRDY RXRDY 472 32142D–06/2013 ATUC64/128/256L3/4U 20.7.6 Channel Status Register Name: CSR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 • LINSNRE: LIN Slave Not Responding Error 0: No LIN Slave Not Responding Error has been detected since the last RSTSTA. 1: A LIN Slave Not Responding Error has been detected since the last RSTSTA. • LINCE: LIN Checksum Error 0: No LIN Checksum Error has been detected since the last RSTSTA. 1: A LIN Checksum Error has been detected since the last RSTSTA. • LINIPE: LIN Identifier Parity Error 0: No LIN Identifier Parity Error has been detected since the last RSTSTA. 1: A LIN Identifier Parity Error has been detected since the last RSTSTA. • LINISFE: LIN Inconsistent Sync Field Error 0: No LIN Inconsistent Sync Field Error has been detected since the last RSTSTA 1: The USART is configured as a Slave node and a LIN Inconsistent Sync Field Error has been detected since the last RSTSTA. • LINBE: LIN Bit Error 0: No Bit Error has been detected since the last RSTSTA. 1: A Bit Error has been detected since the last RSTSTA. • CTS: Image of CTS Input 0: CTS is low. 1: CTS is high. • CTSIC: Clear to Send Input Change Flag 0: No change has been detected on the CTS pin since the last CSR read. 1: At least one change has been detected on the CTS pin since the last CSR read. • LINTC: LIN Transfer Completed 0: The USART is either idle or a LIN transfer is ongoing. 1: A LIN transfer has been completed since the last RSTSTA. • LINID: LIN Identifier 0: No LIN Identifier has been sent or received. 1: A LIN Identifier has been sent (master) or received (slave), since the last RSTSTA. • NACK: Non Acknowledge 0: No Non Acknowledge has been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • RXBUFF: Reception Buffer Full 0: The Buffer Full signal from the Peripheral DMA Controller channel is inactive. 31 30 29 28 27 26 25 24 – – LINSNRE LINCE LINIPE LINISFE LINBE – 23 22 21 20 19 18 17 16 CTS – – – CTSIC – – – 15 14 13 12 11 10 9 8 LINTC LINID NACK/LINBK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE – – RXBRK TXRDY RXRDY 473 32142D–06/2013 ATUC64/128/256L3/4U 1: The Buffer Full signal from the Peripheral DMA Controller channel is active. • ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error If USART does not operate in SPI Slave Mode: ITER=0: Maximum number of repetitions has not been reached since the last RSTSTA. ITER=1: Maximum number of repetitions has been reached since the last RSTSTA. If USART operates in SPI Slave Mode: UNRE=0: No SPI underrun error has occurred since the last RSTSTA. UNRE=1: At least one SPI underrun error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0: The transmitter is either disabled or there are characters in THR, or in the transmit shift register. 1: There are no characters in neither THR, nor in the transmit shift register. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (CR.STTTO), or RTOR.TO is zero. 1: There has been a time-out since the last Start Time-out command. • PARE: Parity Error 0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA. 1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA. • FRAME: Framing Error 0: No stop bit has been found as low since the last RSTSTA. 1: At least one stop bit has been found as low since the last RSTSTA. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break received or End of Break detected since the last RSTSTA. • TXRDY: Transmitter Ready 0: The transmitter is either disabled, or a character in THR is waiting to be transferred to the transmit shift register, or an STTBRK command has been requested. As soon as the transmitter is enabled, TXRDY becomes one. 1: There is no character in the THR. • RXRDY: Receiver Ready 0: The receiver is either disabled, or no complete character has been received since the last read of RHR. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and RHR has not yet been read. 474 32142D–06/2013 ATUC64/128/256L3/4U 20.7.7 Receiver Holding Register Name: RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 • RXCHR: Received Character Last received character. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 –––––––– 15 14 13 12 11 10 9 8 – – – – – – – RXCHR[8] 76543210 RXCHR[7:0] 475 32142D–06/2013 ATUC64/128/256L3/4U 20.7.8 Transmitter Holding Register Name: THR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 • TXCHR: Character to be Transmitted If TXRDY is zero this field contains the next character to be transmitted. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 –––––––– 15 14 13 12 11 10 9 8 – – – – – – – TXCHR[8] 76543210 TXCHR[7:0] 476 32142D–06/2013 ATUC64/128/256L3/4U 20.7.9 Baud Rate Generator Register Name: BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 482. • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baud rate resolution, defined by FP x 1/8. • CD: Clock Divider 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 – – – – – FP 15 14 13 12 11 10 9 8 CD[15:8] 76543210 CD[7:0] Table 20-17. CD SYNC = 0 SYNC = 1 or MODE = SPI (Master or Slave) OVER = 0 OVER = 1 0 Baud Rate Clock Disabled 1 to 65535 Baud Rate = Selected Clock/16/CD Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD 477 32142D–06/2013 ATUC64/128/256L3/4U 20.7.10 Receiver Time-out Register Name: RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 482. • TO: Time-out Value 0: The receiver Time-out is disabled. 1 - 131071: The receiver Time-out is enabled and the time-out delay is TO x bit period. Note that the size of the TO counter is device dependent, see the Module Configuration section. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 – – – – – – – TO[16] 15 14 13 12 11 10 9 8 TO[15:8] 76543210 TO[7:0] 478 32142D–06/2013 ATUC64/128/256L3/4U 20.7.11 Transmitter Timeguard Register Name: TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 482. • TG: Timeguard Value 0: The transmitter Timeguard is disabled. 1 - 255: The transmitter timeguard is enabled and the timeguard delay is TG x bit period. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 –––––––– 15 14 13 12 11 10 9 8 –––––––– 76543210 TG 479 32142D–06/2013 ATUC64/128/256L3/4U 20.7.12 LIN Mode Register Name: LINMR Access Type: Read-write Offset: 0x54 Reset Value: 0x00000000 • PDCM: Peripheral DMA Controller Mode 0: The LIN mode register is not written by the Peripheral DMA Controller. 1: The LIN mode register is, except for this bit, written by the Peripheral DMA Controller. • DLC: Data Length Control 0 - 255: If DLM=0 this field defines the response data length to DLC+1 bytes. • WKUPTYP: Wakeup Signal Type 0: Writing a one to CR.LINWKUP will send a LIN 2.0 wakeup signal. 1: Writing a one to CR.LINWKUP will send a LIN 1.3 wakeup signal. • FSDIS: Frame Slot Mode Disable 0: The Frame Slot mode is enabled. 1: The Frame Slot mode is disabled. • DLM: Data Length Mode 0: The response data length is defined by DLC. 1: The response data length is defined by bits 4 and 5 of the Identifier (LINIR.IDCHR). • CHKTYP: Checksum Type 0: LIN 2.0 “Enhanced” checksum 1: LIN 1.3 “Classic” checksum • CHKDIS: Checksum Disable 0: Checksum is automatically computed and sent when master, and checked when slave. 1: Checksum is not computed and sent, nor checked. • PARDIS: Parity Disable 0: Identifier parity is automatically computed and sent when master, and checked when slave. 1: Identifier parity is not computed and sent, nor checked. • NACT: LIN Node Action 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 – – – – – – – PDCM 15 14 13 12 11 10 9 8 DLC 76543210 WKUPTYP FSDIS DLM CHKTYP CHKDIS PARDIS NACT Table 20-18. NACT Mode Description 0 0 PUBLISH: The USART transmits the response. 480 32142D–06/2013 ATUC64/128/256L3/4U 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response. 1 1 Reserved Table 20-18. 481 32142D–06/2013 ATUC64/128/256L3/4U 20.7.13 LIN Identifier Register Name: LINIR Access Type: Read-write or Read-only Offset: 0x58 Reset Value: 0x00000000 • IDCHR: Identifier Character If USART is in LIN master mode, the IDCHR field is read-write, and its value is the Identifier character to be transmitted. If USART is in LIN slave mode, the IDCHR field is read-only, and its value is the last received Identifier character. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 –––––––– 15 14 13 12 11 10 9 8 –––––––– 76543210 IDCHR 482 32142D–06/2013 ATUC64/128/256L3/4U 20.7.14 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: See Table 20-10 • WPKEY: Write Protect KEY Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. Always reads as zero. • WPEN: Write Protect Enable 0 = Write protection disabled. 1 = Write protection enabled. Protects the registers: • ”Mode Register” on page 466 • ”Baud Rate Generator Register” on page 476 • ”Receiver Time-out Register” on page 477 • ”Transmitter Timeguard Register” on page 478 31 30 29 28 27 26 25 24 WPKEY[23:16] 23 22 21 20 19 18 17 16 WPKEY[15:8] 15 14 13 12 11 10 9 8 WPKEY[7:0] 76543210 — — — — — — — WPEN 483 32142D–06/2013 ATUC64/128/256L3/4U 20.7.15 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: See Table 20-10 • WPVSRC: Write Protect Violation Source If WPVS=1 this field indicates which write-protected register was unsuccessfully written to, either by address offset or code. • WPVS: Write Protect Violation Status 0= No write protect violation has occurred since the last WPSR read. 1= A write protect violation has occurred since the last WPSR read. Note: Reading WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 ———————— 23 22 21 20 19 18 17 16 WPVSRC[15:8] 15 14 13 12 11 10 9 8 WPVSRC[7:0] 76543210 — — — — — — — WPVS 484 32142D–06/2013 ATUC64/128/256L3/4U 20.7.16 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated. 31 30 29 28 27 26 25 24 –––––––– 23 22 21 20 19 18 17 16 – – – – MFN 15 14 13 12 11 10 9 8 – – – – VERSION[11:8] 76543210 VERSION[7:0] 485 32142D–06/2013 ATUC64/128/256L3/4U 20.8 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 20-19. USART Configuration Feature USART0 USART1 USART2 USART3 Receiver Time-out Counter Size (Size of the RTOR.TO field) 17 bit 17 bit 17 bit 17 bit DIV Value for divided CLK_USART 8 8 8 8 Table 20-20. USART Clocks Module Name Clock Name Description USART0 CLK_USART0 Clock for the USART0 bus interface USART1 CLK_USART1 Clock for the USART1 bus interface USART2 CLK_USART2 Clock for the USART2 bus interface USART3 CLK_USART3 Clock for the USART3 bus interface Table 20-21. Register Reset Values Register Reset Value VERSION 0x00000440 486 32142D–06/2013 ATUC64/128/256L3/4U 21. Serial Peripheral Interface (SPI) Rev: 2.1.1.3 21.1 Features • Compatible with an embedded 32-bit microcontroller • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors – External co-processors • Master or Slave Serial Peripheral Bus Interface – 4 - to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Connection to Peripheral DMA Controller channel capabilities optimizes data transfers – One channel for the receiver, one channel for the transmitter – Next buffer support – Four character FIFO in reception 21.2 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): this data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): this data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): this control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): this control line allows slaves to be turned on and off by hardware. 487 32142D–06/2013 ATUC64/128/256L3/4U 21.3 Block Diagram Figure 21-1. SPI Block Diagram 21.4 Application Block Diagram Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation Spi Interface Interrupt Control Peripheral DMA Controller I/O Controller CLK_SPI Peripheral Bus SPI Interrupt SPCK NPCS3 NPCS2 NPCS1 NPCS0/NSS MOSI MISO Slave 0 Slave 2 Slave 1 SPCK NPCS3 NPCS2 NPCS1 NPCS0 MOSI MISO Spi Master SPCK NSS MOSI MISO SPCK NSS MOSI MISO SPCK NSS MOSI MISO NC 488 32142D–06/2013 ATUC64/128/256L3/4U 21.5 I/O Lines Description 21.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first configure the I/O Controller to assign the SPI pins to their peripheral functions. 21.6.2 Clocks The clock for the SPI bus interface (CLK_SPI) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SPI before disabling the clock, to avoid freezing the SPI in an undefined state. 21.6.3 Interrupts The SPI interrupt request line is connected to the interrupt controller. Using the SPI interrupt requires the interrupt controller to be programmed first. 21.7 Functional Description 21.7.1 Modes of Operation The SPI operates in master mode or in slave mode. Operation in master mode is configured by writing a one to the Master/Slave Mode bit in the Mode Register (MR.MSTR). The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MR.MSTR bit is written to zero, the SPI operates in slave mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in master mode. Table 21-1. I/O Lines Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 489 32142D–06/2013 ATUC64/128/256L3/4U 21.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled. Each of the two bits has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 21-2 on page 489 shows the four modes and corresponding parameter settings. Figure 21-3 on page 489 and Figure 21-4 on page 490 show examples of data transfers. Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) Table 21-2. SPI modes SPI Mode CPOL NCPHA 0 01 1 00 2 11 3 10 SPCK cycle (for reference) 1 4 2 3 5 8 6 7 SPCK (CPOL = 0) NSS (to slave) MISO (from slave) MOSI (from master) SPCK (CPOL = 1) MSB 6 4 5 LSB 3 2 1 MSB 6 5 4 3 2 1 LSB *** *** Not Defined, but normaly MSB of previous character received 490 32142D–06/2013 ATUC64/128/256L3/4U Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 21.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register (TDR) and the Receive Data Register (RDR), and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the TDR register. The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing to the TDR, the Peripheral Chip Select field in TDR (TDR.PCS) must be written in order to select a slave. If new data is written to TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in TDR in the Shift Register is indicated by the Transmit Data Register Empty bit in the Status Register (SR.TDRE). When new data is written in TDR, this bit is cleared. The SR.TDRE bit is used to trigger the Transmit Peripheral DMA Controller channel. The end of transfer is indicated by the Transmission Registers Empty bit in the SR register (SR.TXEMPTY). If a transfer delay (CSRn.DLYBCT) is greater than zero for the last transfer, SR.TXEMPTY is set after the completion of said delay. The CLK_SPI can be switched off at this time. During reception, received data are transferred from the Shift Register to the reception FIFO. The FIFO can contain up to 4 characters (both Receive Data and Peripheral Chip Select fields). While a character of the FIFO is unread, the Receive Data Register Full bit in SR remains high (SR.RDRF). Characters are read through the RDR register. If the four characters stored in the FIFO are not read and if a new character is stored, this sets the Overrun Error Status bit in the SR register (SR.OVRES). The procedure to follow in such a case is described in Section 21.7.3.8. SPCK cycle (for reference) 1 4 2 3 5 8 6 7 SPCK (CPOL = 0) NSS (to slave) MISO (from slave) MOSI (from master) SPCK (CPOL = 1) MSB 6 4 5 LSB 3 2 1 6 5 4 3 2 1 LSB *** Not Defined, but normaly LSB of previous character transmitted *** MSB 491 32142D–06/2013 ATUC64/128/256L3/4U Figure 21-5 on page 491shows a block diagram of the SPI when operating in master mode. Figure 21-6 on page 492 shows a flow chart describing how transfers are handled. 21.7.3.1 Master mode block diagram Figure 21-5. Master Mode Block Diagram Baud Rate Generator RXFIFOEN 4 – Character FIFO Shift Register TDRE RXFIFOEN 4 – Character FIFO PS PCSDEC Current Peripheral MODF MODFDIS MSTR SCBR CSR0..3 CSR0..3 CPOL NCPHA BITS RDR RD RDRF OVRES TD TDR RDR CSAAT CSNAAT CSR0..3 PCS MR PCS TDR SPCK CLK_SPI MISO MOSI LSB MSB NPCS1 NPCS2 NPCS3 NPCS0 SPI Clock 0 1 0 1 0 1 NPCS0 492 32142D–06/2013 ATUC64/128/256L3/4U 21.7.3.2 Master mode flow diagram Figure 21-6. Master Mode Flow Diagram SPI Enable CSAAT ? PS ? 1 0 0 1 1 NPCS = TDR(PCS) NPCS = MR(PCS) Delay DLYBS Serializer = TDR(TD) TDRE = 1 Data Transfer RDR(RD) = Serializer RDRF = 1 TDRE ? NPCS = 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT 0 1 CSAAT ? 0 TDRE ? 1 0 PS ? 0 1 TDR(PCS) = NPCS ? no yes MR(PCS) = NPCS ? no NPCS = 0xF Delay DLYBCS NPCS = TDR(PCS) NPCS = 0xF Delay DLYBCS NPCS = MR(PCS), TDR(PCS) Fixed peripheral Variable peripheral - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 493 32142D–06/2013 ATUC64/128/256L3/4U 21.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be configured in the CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 21.7.3.4 Transfer delays Figure 21-7 on page 493 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be configured to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing to the Delay Between Chip Selects field in the MR register (MR.DLYBCS). Allows insertion of a delay between release of one chip select and before assertion of a new one. • The delay before SPCK, independently programmable for each chip select by writing the Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to be delayed after the chip select has been asserted. • The delay between consecutive transfers, independently programmable for each chip select by writing the Delay Between Consecutive Transfers field in the CSRn registers (CSRn.DLYBCT). Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 21-7. Programmable Delays DLYBCS DLYBS DLYBCT DLYBCT Chip Select 1 Chip Select 2 SPCK 494 32142D–06/2013 ATUC64/128/256L3/4U 21.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing a zero to the Peripheral Select bit in MR (MR.PS). In this case, the current peripheral is defined by the MR.PCS field and the TDR.PCS field has no effect. Variable Peripheral Select is activated by writing a one to the MR.PS bit . The TDR.PCS field is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the Peripheral DMA Controller is an optimal means, as the size of the data transfer between the memory and the SPI is either 4 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the MR register. Data written to TDR is 32-bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the Peripheral DMA Controller in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the CSRn registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 21.7.3.6 Peripheral chip select decoding The user can configure the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing a one to the Chip Select Decode bit in the MR register (MR.PCSDEC). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the MR register or the TDR register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at one) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, the CRS0 register defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 21.7.3.7 Peripheral deselection When operating normally, as soon as the transfer of the last data written in TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding 495 32142D–06/2013 ATUC64/128/256L3/4U to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.CSAAT bit is written to qero, the NPCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the SR.TDRE bit rises as soon as the content of the TDR is transferred into the internal shifter. When this bit is detected the TDR can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Not Active After Transfer bit (CSRn.CSNAAT) written to one. This allows to de-assert systematically the chip select lines during a time DLYBCS. (The value of the CSRn.CSNAAT bit is taken into account only if the CSRn.CSAAT bit is written to zero for the same Chip Select). Figure 21-8 on page 496 shows different peripheral deselection cases and the effect of the CSRn.CSAAT and CSRn.CSNAAT bits. 21.7.3.8 FIFO management A FIFO has been implemented in Reception FIFO (both in master and in slave mode), in order to be able to store up to 4 characters without causing an overrun error. If an attempt is made to store a fifth character, an overrun error rises. If such an event occurs, the FIFO must be flushed. There are two ways to Flush the FIFO: • By performing four read accesses of the RDR (the data read must be ignored) • By writing a one to the Flush Fifo Command bit in the CR register (CR.FLUSHFIFO). After that, the SPI is able to receive new data. 496 32142D–06/2013 ATUC64/128/256L3/4U Figure 21-8. Peripheral Deselection Figure 21-8 on page 496 shows different peripheral deselection cases and the effect of the CSRn.CSAAT and CSRn.CSNAAT bits. 21.7.3.9 Mode fault detection The SPI is capable of detecting a mode fault when it is configured in master mode and NPCS0, MOSI, MISO, and SPCK are configured as open drain through the I/O Controller with either internal or external pullup resistors. If the I/O Controller does not have open-drain capability, mode fault detection must be disabled by writing a one to the Mode Fault Detection bit in the MR A NPCS[0..3] Write TDR TDRE NPCS[0..3] Write TDR TDRE NPCS[0..3] Write TDR TDRE DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS DLYBCT PCS=A A DLYBCS DLYBCT A PCS = A A A DLYBCT A A CSAAT = 0 and CSNAAT = 0 DLYBCT A A CSAAT = 1 and CSNAAT= 0 / 1 A DLYBCS PCS = A DLYBCT A A CSAAT = 0 and CSNAAT = 1 NPCS[0..3] Write TDR TDRE PCS = A DLYBCT A A CSAAT = 0 and CSNAAT = 0 497 32142D–06/2013 ATUC64/128/256L3/4U register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled. The user can disable mode fault detection by writing a one to the Mode Fault Detection bit in the MR register (MR.MODFDIS). 21.7.4 SPI Slave Mode When operating in slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the Bits Per Transfer field of the Chip Select Register 0 (CSR0.BITS). These bits are processed following a phase and a polarity defined respectively by the CSR0.NCPHA and CSR0.CPOL bits. Note that the BITS, CPOL, and NCPHA bits of the other Chip Select Registers have no effect when the SPI is configured in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the SR.RDRF bit rises. If the RDR register has not been read before new data is received, the SR.OVRES bit is set. Data is loaded in RDR even if this flag is set. The user has to read the SR register to clear the SR.OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the TDR register, the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets to zero. When a first data is written in TDR, it is transferred immediately in the Shift Register and the SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to be transmitted, i.e. no character has been written in TDR since the last load from TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. In this case the Underrun Error Status bit is set in SR (SR.UNDES). Figure 21-9 on page 498 shows a block diagram of the SPI when operating in slave mode. 498 32142D–06/2013 ATUC64/128/256L3/4U Figure 21-9. Slave Mode Functional Block Diagram Shift Register SPCK SPIENS LSB MSB NSS MOSI SPI Clock TDRE TDR TD RDRF OVRES CSR0 CPOL NCPHA BITS SPIEN SPIDIS MISO UNDES RDR RD 4 - Character FIFO 0 1 RXFIFOEN 499 32142D–06/2013 ATUC64/128/256L3/4U 21.8 User Interface Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 21-3. SPI Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Write-only 0x00000000 0x04 Mode Register MR Read/Write 0x00000000 0x08 Receive Data Register RDR Read-only 0x00000000 0x0C Transmit Data Register TDR Write-only 0x00000000 0x10 Status Register SR Read-only 0x00000000 0x14 Interrupt Enable Register IER Write-only 0x00000000 0x18 Interrupt Disable Register IDR Write-only 0x00000000 0x1C Interrupt Mask Register IMR Read-only 0x00000000 0x30 Chip Select Register 0 CSR0 Read/Write 0x00000000 0x34 Chip Select Register 1 CSR1 Read/Write 0x00000000 0x38 Chip Select Register 2 CSR2 Read/Write 0x00000000 0x3C Chip Select Register 3 CSR3 Read/Write 0x00000000 0x E4 Write Protection Control Register WPCR Read/Write 0X00000000 0xE8 Write Protection Status Register WPSR Read-only 0x00000000 0xF8 Features Register FEATURES Read-only - (1) 0xFC Version Register VERSION Read-only - (1) 500 32142D–06/2013 ATUC64/128/256L3/4U 21.8.1 Control Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 0: Writing a zero to this bit has no effect. • FLUSHFIFO: Flush Fifo Command 1: If The FIFO Mode is enabled (MR.FIFOEN written to one) and if an overrun error has been detected, this command allows to empty the FIFO. 0: Writing a zero to this bit has no effect. • SWRST: SPI Software Reset 1: Writing a one to this bit will reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. Peripheral DMA Controller channels are not affected by software reset. 0: Writing a zero to this bit has no effect. • SPIDIS: SPI Disable 1: Writing a one to this bit will disable the SPI. As soon as SPIDIS is written to one, the SPI finishes its transfer, all pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the CR register is written, the SPI is disabled. 0: Writing a zero to this bit has no effect. • SPIEN: SPI Enable 1: Writing a one to this bit will enable the SPI to transfer and receive data. 0: Writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - - - FLUSHFIFO 76543210 SWRST - - - - - SPIDIS SPIEN 501 32142D–06/2013 ATUC64/128/256L3/4U 21.8.2 Mode Register Name: MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default. Otherwise, the following equation determines the delay: • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • LLB: Local Loopback Enable 1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is internally connected on MOSI). 0: Local loopback path disabled. • RXFIFOEN: FIFO in Reception Enable 1: The FIFO is used in reception (four characters can be stored in the SPI). 31 30 29 28 27 26 25 24 DLYBCS 23 22 21 20 19 18 17 16 - - - - PCS 15 14 13 12 11 10 9 8 -------- 76543210 LLB RXFIFOEN - MODFDIS - PCSDEC PS MSTR Delay Between Chip Selects DLYBCS CLKSPI = ----------------------- 502 32142D–06/2013 ATUC64/128/256L3/4U 0: The FIFO is not used in reception (only one character can be stored in the SPI). • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be disabled for proper operation of the SPI. 0: Mode fault detection is enabled. • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The CSRn registers define the characteristics of the 15 chip selects according to the following rules: CSR0 defines peripheral chip select signals 0 to 3. CSR1 defines peripheral chip select signals 4 to 7. CSR2 defines peripheral chip select signals 8 to 11. CSR3 defines peripheral chip select signals 12 to 14. • PS: Peripheral Select 1: Variable Peripheral Select. 0: Fixed Peripheral Select. • MSTR: Master/Slave Mode 1: SPI is in master mode. 0: SPI is in slave mode. 503 32142D–06/2013 ATUC64/128/256L3/4U 21.8.3 Receive Data Register Name: RDR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 RD[15:8] 76543210 RD[7:0] 504 32142D–06/2013 ATUC64/128/256L3/4U 21.8.4 Transmit Data Register Name: TDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 0: Writing a zero to this bit has no effect. This field is only used if Variable Peripheral Select is active (MR.PS = 1). • PCS: Peripheral Chip Select If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS This field is only used if Variable Peripheral Select is active (MR.PS = 1). • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the TDR register in a right-justified format. 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - PCS 15 14 13 12 11 10 9 8 TD[15:8] 76543210 TD[7:0] 505 32142D–06/2013 ATUC64/128/256L3/4U 21.8.5 Status Register Name: SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled. • UNDES: Underrun Error Status (Slave Mode Only) 1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register. 0: This bit is cleared when the SR register is read. • TXEMPTY: Transmission Registers Empty 1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. 0: This bit is cleared as soon as data is written in TDR. • NSSR: NSS Rising 1: A rising edge occurred on NSS pin since last read. 0: This bit is cleared when the SR register is read. • OVRES: Overrun Error Status 1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR. 0: This bit is cleared when the SR register is read. • MODF: Mode Fault Error 1: This bit is set when a Mode Fault occurred. 0: This bit is cleared when the SR register is read. • TDRE: Transmit Data Register Empty 1: This bit is set when the last data written in the TDR register has been transferred to the serializer. 0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • RDRF: Receive Data Register Full 1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR. 0: No data has been received since the last read of RDR 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - - SPIENS 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 76543210 - - - - OVRES MODF TDRE RDRF 506 32142D–06/2013 ATUC64/128/256L3/4U 21.8.6 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 76543210 - - - - OVRES MODF TDRE RDRF 507 32142D–06/2013 ATUC64/128/256L3/4U 21.8.7 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 76543210 - - - - OVRES MODF TDRE RDRF 508 32142D–06/2013 ATUC64/128/256L3/4U 21.8.8 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 76543210 - - - - OVRES MODF TDRE RDRF 509 32142D–06/2013 ATUC64/128/256L3/4U 21.8.9 Chip Select Register 0 Name: CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct access will be possible on other CS. 31 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS CSAAT CSNAAT NCPHA CPOL Delay Between Consecutive Transfers 32  DLYBCT CLKSPI = ------------------------------------ Delay Before SPCK DLYBS CLKSPI = --------------------- SPCK Baudrate CLKSPI SCBR = --------------------- 510 32142D–06/2013 ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: (if DLYBCT field is different from 0) (if DLYBCT field equals 0) • NCPHA: Clock Phase 1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of SPCK. 0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved DLYBCS CLKSPI ----------------------- DLYBCS + 1 CLKSPI -------------------------------- 511 32142D–06/2013 ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 512 32142D–06/2013 ATUC64/128/256L3/4U 21.8.10 Chip Select Register 1 Name: CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct access will be possible on other CS. 31 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS CSAAT CSNAAT NCPHA CPOL Delay Between Consecutive Transfers 32  DLYBCT CLKSPI = ------------------------------------ Delay Before SPCK DLYBS CLKSPI = --------------------- SPCK Baudrate CLKSPI SCBR = --------------------- 513 32142D–06/2013 ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: (if DLYBCT field is different from 0) (if DLYBCT field equals 0) • NCPHA: Clock Phase 1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of SPCK. 0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved DLYBCS CLKSPI ----------------------- DLYBCS + 1 CLKSPI -------------------------------- 514 32142D–06/2013 ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 515 32142D–06/2013 ATUC64/128/256L3/4U 21.8.11 Chip Select Register 2 Name: CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct access will be possible on other CS. 31 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS CSAAT CSNAAT NCPHA CPOL Delay Between Consecutive Transfers 32  DLYBCT CLKSPI = ------------------------------------ Delay Before SPCK DLYBS CLKSPI = --------------------- SPCK Baudrate CLKSPI SCBR = --------------------- 516 32142D–06/2013 ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: (if DLYBCT field is different from 0) (if DLYBCT field equals 0) • NCPHA: Clock Phase 1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of SPCK. 0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved DLYBCS CLKSPI ----------------------- DLYBCS + 1 CLKSPI -------------------------------- 517 32142D–06/2013 ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 518 32142D–06/2013 ATUC64/128/256L3/4U 21.8.12 Chip Select Register 3 Name: CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct access will be possible on other CS. 31 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS CSAAT CSNAAT NCPHA CPOL Delay Between Consecutive Transfers 32  DLYBCT CLKSPI = ------------------------------------ Delay Before SPCK DLYBS CLKSPI = --------------------- SPCK Baudrate CLKSPI SCBR = --------------------- 519 32142D–06/2013 ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: (if DLYBCT field is different from 0) (if DLYBCT field equals 0) • NCPHA: Clock Phase 1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of SPCK. 0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved DLYBCS CLKSPI ----------------------- DLYBCS + 1 CLKSPI -------------------------------- 520 32142D–06/2013 ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 521 32142D–06/2013 ATUC64/128/256L3/4U 21.8.13 Write Protection Control Register Register Name: WPCR Access Type: Read-write Offset: 0xE4 Reset Value: 0x00000000 • SPIWPKEY: SPI Write Protection Key Password If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with “SPI” (SPI written in ASCII Code, i.e. 0x535049 in hexadecimal). • SPIWPEN: SPI Write Protection Enable 1: The Write Protection is Enabled 0: The Write Protection is Disabled 31 30 29 28 27 26 25 24 SPIWPKEY[23:16] 23 22 21 20 19 18 17 16 SPIWPKEY[15:8] 15 14 13 12 11 10 9 8 SPIWPKEY[7:0] 76543210 - - - - - - - SPIWPEN 522 32142D–06/2013 ATUC64/128/256L3/4U 21.8.14 Write Protection Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: 0x00000000 • SPIWPVSRC: SPI Write Protection Violation Source This Field indicates the Peripheral Bus Offset of the register concerned by the violation (MR or CSRx) • SPIWPVS: SPI Write Protection Violation Status 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 SPIWPVSRC 76543210 - - - - - SPIWPVS SPIWPVS value Violation Type 1 The Write Protection has blocked a Write access to a protected register (since the last read). 2 Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). 3 Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. 4 Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. 5 The Write Protection has blocked a Write access to a protected register and write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. 6 Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx) and some write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. 7 - The Write Protection has blocked a Write access to a protected register. and - Software Reset has been performed while Write Protection was enabled. and - Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. 523 32142D–06/2013 ATUC64/128/256L3/4U 21.8.15 Features Register Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: – • SWIMPL: Spurious Write Protection Implemented 0: Spurious write protection is not implemented. 1: Spurious write protection is implemented. • FIFORIMPL: FIFO in Reception Implemented 0: FIFO in reception is not implemented. 1: FIFO in reception is implemented. • BRPBHSB: Bridge Type is PB to HSB 0: Bridge type is not PB to HSB. 1: Bridge type is PB to HSB. • CSNAATIMPL: CSNAAT Features Implemented 0: CSNAAT (Chip select not active after transfer) features are not implemented. 1: CSNAAT features are implemented. • EXTDEC: External Decoder True 0: External decoder capability is not implemented. 1: External decoder capability is implemented. • LENNCONF: Character Length if not Configurable If the character length is not configurable, this field specifies the fixed character length. • LENCONF: Character Length Configurable 0: The character length is not configurable. 1: The character length is configurable. • PHZNCONF: Phase is Zero if Phase not Configurable 0: If phase is not configurable, phase is non-zero. 1: If phase is not configurable, phase is zero. • PHCONF: Phase Configurable 0: Phase is not configurable. 1: Phase is configurable. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - SWIMPL FIFORIMPL BRPBHSB CSNAATIMPL EXTDEC 15 14 13 12 11 10 9 8 LENNCONF LENCONF 76543210 PHZNCONF PHCONF PPNCONF PCONF NCS 524 32142D–06/2013 ATUC64/128/256L3/4U • PPNCONF: Polarity Positive if Polarity not Configurable 0: If polarity is not configurable, polarity is negative. 1: If polarity is not configurable, polarity is positive. • PCONF: Polarity Configurable 0: Polarity is not configurable. 1: Polarity is configurable. • NCS: Number of Chip Selects This field indicates the number of chip selects implemented. 525 32142D–06/2013 ATUC64/128/256L3/4U 21.8.16 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - MFN 15 14 13 12 11 10 9 8 VERSION[11:8] 76543210 VERSION[7:0] 526 32142D–06/2013 ATUC64/128/256L3/4U 21.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 21-4. SPI Clock Name Module Name Clock Name Description SPI CLK_SPI Clock for the SPI bus interface Table 21-5. Register Reset Value FEATURES 0x001F0154 VERSION 0x00000211 527 32142D–06/2013 ATUC64/128/256L3/4U 22. Two-wire Master Interface (TWIM) Rev.: 1.1.0.1 22.1 Features • Compatible with I²C standard – Multi-master support – Transfer speeds of 100 and 400 kbit/s – 7- and 10-bit and General Call addressing • Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK control – SMBus ALERT interface – 25 ms clock low timeout delay – 10 ms master cumulative clock low extend time – 25 ms slave cumulative clock low extend time • Compatible with PMBus • Compatible with Atmel Two-wire Interface Serial Memories • DMA interface for reducing CPU load • Arbitrary transfer lengths, including 0 data bytes • Optional clock stretching if transmit or receive buffers not ready for data transfer 22.2 Overview The Atmel Two-wire Master Interface (TWIM) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD controller, and temperature sensor, to name a few. The TWIM is always a bus master and can transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus is performed internally and relinquishes the bus automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.Table 22-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I²C compatible device. Note: 1. START + b000000001 + Ack + Sr Table 22-1. Atmel TWIM Compatibility with I²C Standard I²C Standard Atmel TWIM Standard-mode (100 kbit/s) Supported Fast-mode (400 kbit/s) Supported Fast-mode Plus (1 Mbit/s) Supported 7- or 10-bits Slave Addressing Supported START BYTE(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Slope Control and Input Filtering (Fast mode) Supported Clock Stretching Supported 528 32142D–06/2013 ATUC64/128/256L3/4U Table 22-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. 22.3 List of Abbreviations 22.4 Block Diagram Figure 22-1. Block Diagram Table 22-2. Atmel TWIM Compatibility with SMBus Standard SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Host Functionality Supported Packet Error Checking Supported Table 22-3. Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Peripheral Bus Bridge Two-wire Interface I/O Controller TWCK TWD INTC TWI Interrupt Power Manager CLK_TWIM TWALM 529 32142D–06/2013 ATUC64/128/256L3/4U 22.5 Application Block Diagram Figure 22-2. Application Block Diagram 22.6 I/O Lines Description 22.7 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 22.7.1 I/O Lines TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 22-4 on page 531). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWALM is used to implement the optional SMBus SMBALERT signal. The TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the TWIM, the user must perform the following steps: • Program the I/O Controller to: – Dedicate TWD, TWCK, and optionally TWALM as peripheral lines. – Define TWD, TWCK, and optionally TWALM as open-drain. 22.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIM, the TWIM will stop functioning and resume operation after the system wakes up from sleep mode. TWI Master TWD TWCK Atmel TWI serial EEPROM I 2 C RTC I 2 C LCD controller I 2 C temp sensor Slave 2 Slave 3 Slave 4 VDD Rp: pull-up value as given by the I2C Standard TWALM Slave 1 Rp Rp Rp Table 22-4. I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 530 32142D–06/2013 ATUC64/128/256L3/4U 22.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 22.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIM. 22.7.5 Interrupts The TWIM interrupt request lines are connected to the interrupt controller. Using the TWIM interrupts requires the interrupt controller to be programmed first. 22.7.6 Debug Operation When an external debugger forces the CPU into debug mode, the TWIM continues normal operation. If the TWIM is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 531 32142D–06/2013 ATUC64/128/256L3/4U 22.8 Functional Description 22.8.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 22-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 22-4). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 22-3. START and STOP Conditions Figure 22-4. Transfer Format 22.8.2 Operation The TWIM has two modes of operation: • Master transmitter mode • Master receiver mode The master is the device which starts and stops a transfer and generates the TWCK clock. These modes are described in the following chapters. TWD TWCK Start Stop TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 532 32142D–06/2013 ATUC64/128/256L3/4U 22.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR (CWGR.EXP). CWGR has the following fields: LOW: Prescaled clock cycles in clock low count. Used to time TLOW and TBUF. HIGH: Prescaled clock cycles in clock high count. Used to time THIGH. STASTO: Prescaled clock cycles in clock high count. Used to time THD_STA, TSU_STA, TSU_STO. DATA: Prescaled clock cycles for data setup and hold count. Used to time THD_DAT, TSU_DAT. EXP: Specifies the clock prescaler setting. Note that the total clock low time generated is the sum of THD_DAT + TSU_DAT + TLOW. Any slave or other bus master taking part in the transfer may extend the TWCK low period at any time. The TWIM hardware monitors the state of the TWCK line as required by the I²C specification. The clock generation counters are started when a high/low level is detected on the TWCK line, not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR settings alone do not determine the TWCK frequency. The CWGR settings determine the clock low time and the clock high time, but the TWCK rise and fall times are determined by the external circuitry (capacitive load, etc.). Figure 22-5. Bus Timing Diagram f PRESCALER f CLK_TWIM 2  EXP 1 + = ------------------------- S t HD:STA t LOW t SU:DAT t HIGH t HD:DAT t LOW P t SU:STO Sr t SU:STA t SU:DAT 533 32142D–06/2013 ATUC64/128/256L3/4U 22.8.2.2 Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Clock Waveform Generator Register (CWGR). If operating in SMBus mode, the SMBus Timing Register (SMBTR) register must also be configured. 2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up. 3. CMDR or NCMDR must be written with a value describing the transfer to be performed. The interrupt system can be set up to give interrupt requests on specific events or error conditions in the SR, for example when the transfer is complete or if arbitration is lost. The Interrupt Enable Register (IER) and Interrupt Disable Register (IDR) can be written to specify which bits in the SR will generate interrupt requests. The SR.BUSFREE bit is set when activity is completed on the two-wire bus. The SR.CRDY bit is set when CMDR and/or NCMDR is ready to receive one or more commands. The controller will refuse to start a new transfer while ANAK, DNAK, or ARBLST in the Status Register (SR) is one. This is necessary to avoid a race when the software issues a continuation of the current transfer at the same time as one of these errors happen. Also, if ANAK or DNAK occurs, a STOP condition is sent automatically. The user will have to restart the transmission by clearing the error bits in SR after resolving the cause for the NACK. After a data or address NACK from the slave, a STOP will be transmitted automatically. Note that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR. When a data or address NACK is returned by the slave while the master is transmitting, it is possible that new data has already been written to the THR register. This data will be transferred out as the first data byte of the next transfer. If this behavior is to be avoided, the safest approach is to perform a software reset of the TWIM. 22.8.3 Master Transmitter Mode A START condition is transmitted and master transmitter mode is initiated when the bus is free and CMDR has been written with START=1 and READ=0. START and SADR+W will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) 1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY indicates the state of THR. Software or the Peripheral DMA Controller must write the data byte to THR. 2. Transmit this data byte 3. Decrement NBYTES 4. If (NBYTES==0) and STOP=1, transmit STOP condition Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, SADR+W, STOP. 534 32142D–06/2013 ATUC64/128/256L3/4U TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER). TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of a command is marked when the TWIM sets the SR.CCOMP bit. See Figure 22-6 and Figure 22-7. Figure 22-6. Master Write with One Data Byte Figure 22-7. Master Write with Multiple Data Bytes 22.8.4 Master Receiver Mode A START condition is transmitted and master receiver mode is initiated when the bus is free and CMDR has been written with START=1 and READ=1. START and SADR+R will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) TWD SR.IDLE TXRDY Write THR (DATA) NBYTES set to 1 STOP sent automatically (ACK received and NBYTES=0) S DADR W A DATA A P TWD SR.IDLE TXRDY Write THR (DATAn) NBYTES set to n STOP sent automatically (ACK received and NBYTES=0) S DADR W A DATAn A DATAn+5 A A DATAn+m P Write THR (DATAn+1) Write THR (DATAn+m) Last data sent 535 32142D–06/2013 ATUC64/128/256L3/4U 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition. Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, DADR+R, STOP The TWI transfers require the master to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. All data bytes except the last are acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer is finished. RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 22-8. Master Read with One Data Byte Figure 22-9. Master Read with Multiple Data Bytes TWD SR.IDLE RXRDY Write START & STOP bit NBYTES set to 1 Read RHR S DADR R A DATA N P TWD SR.IDLE RXRDY Write START + STOP bit NBYTES set to m S DADR R A DATAn A DATAn+m-1 A N DATAn+m P Read RHR DATAn DATAn+1 Read RHR DATAn+m-2 Read RHR DATAn+m-1 Read RHR DATAn+m Send STOP When NBYTES=0 536 32142D–06/2013 ATUC64/128/256L3/4U 22.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 22.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIM (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to transmit. 4. Wait for the Peripheral DMA Controller end-of-transmit flag. 5. Disable the Peripheral DMA Controller. 22.8.5.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIM (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to receive. 4. Wait for the Peripheral DMA Controller end-of-receive flag. 5. Disable the Peripheral DMA Controller. 22.8.6 Multi-master Mode More than one master may access the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master who lost arbitration may reinitiate the data transfer. Arbitration is illustrated in Figure 22-11. If the user starts a transfer and if the bus is busy, the TWIM automatically waits for a STOP condition on the bus before initiating the transfer (see Figure 22-10). Note: The state of the bus (busy or free) is not indicated in the user interface. 537 32142D–06/2013 ATUC64/128/256L3/4U Figure 22-10. User Sends Data While the Bus is Busy Figure 22-11. Arbitration Cases 22.8.7 Combined Transfers CMDR and NCMDR may be used to generate longer sequences of connected transfers, since generation of START and/or STOP conditions is programmable on a per-command basis. Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause a REPEATED START on the bus. The ability to generate such connected transfers allows arbitrary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is done in master receiver mode, the CMDR.ACKLAST bit must also be controlled. TWCK TWD DATA sent by a master STOP sent by the master START sent by the TWI DATA sent by the TWI Bus is busy Bus is free A transfer is programmed (DADR + W + START + Write THR) Transfer is initiated TWI DATA transfer Transfer is kept Bus is considered as free TWCK Bus is busy Bus is free A transfer is programmed (DADR + W + START + Write THR) Transfer is initiated TWI DATA transfer Transfer is kept Bus is considered as free Data from a Master Data from TWI S 0 S 0 0 1 1 1 ARBLST S 0 S 0 0 1 1 1 TWD S 1 0 0 1 1 1 1 Arbitration is lost TWI stops sending data P P S 1 0 0 1 1 Data from the master 1 1 Data from the TWI Arbitration is lost The master stops sending data Transfer is stopped Transfer is programmed again (DADR + W + START + Write THR) TWCK TWD 538 32142D–06/2013 ATUC64/128/256L3/4U As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 22.8.5 22.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5. Wait until SR.TXRDY==1, then write third data byte to transfer to THR. 6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR. 22.8.7.2 Read Followed by Read Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.RXRDY==1, then read third data byte received from RHR. 6. Wait until SR.RXRDY==1, then read fourth data byte received from RHR. If combining several transfers, without any STOP or REPEATED START between them, remember to write a one to the ACKLAST bit in CMDR to keep from ending each of the partial transfers with a NACK. 22.8.7.3 Write Followed by Read Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. 539 32142D–06/2013 ATUC64/128/256L3/4U Figure 22-12. Combining a Write and Read Transfer To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5. Wait until SR.RXRDY==1, then read first data byte received from RHR. 6. Wait until SR.RXRDY==1, then read second data byte received from RHR. 22.8.7.4 Read Followed by Write Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+W, DATA+A, DATA+A, STOP. Figure 22-13. Combining a Read and Write Transfer To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. TWD SR.IDLE TXRDY S DADR W A DATA0 A DATA1 NA Sr DADR R A DATA2 A DATA3 A P THR DATA0 DATA1 RXRDY 1 RHR DATA2 DATA3 TWD SR.IDLE TXRDY S SADR R A DATA0 A DATA1 Sr DADR W A DATA2 A DATA3 NA P THR DATA2 RXRDY RHR DATA0 DATA3 A 1 2 DATA3 Read TWI_RHR 540 32142D–06/2013 ATUC64/128/256L3/4U 22.8.8 Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. In Figure 22-14 and Figure 22-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 22.8.8.1 Master Transmitter To perform a master transmitter transfer: 1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the desired address and NBYTES value. Figure 22-14. A Write Transfer with 10-bit Addressing 22.8.8.2 Master Receiver When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be controlled. CMDR.REPSAME must be written to one when the address phase of the transfer should consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard specifies that such addressing is required when addressing a slave for reads using 10-bit addressing. To perform a master receiver transfer: 1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0, NBYTES=0 and the desired address. 2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the desired address and NBYTES value. Figure 22-15. A Read Transfer with 10-bit Addressing 22.8.9 SMBus Mode SMBus mode is enabled and disabled by writing to the SMEN and SMDIS bits in CR. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be written into SMBTR. • Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). • A dedicated bus line, SMBALERT, allows a slave to get a master’s attention. • A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. S SLAVE ADDRESS 1st 7 bits RW A1 A2 DATA A P SLAVE ADDRESS 2nd byte DATA AA 11110XX0 S SLAVE ADDRESS 1st 7 bits RW A1 A2 DATA A P SLAVE ADDRESS 2nd byte DATA A 11110XX0 Sr SLAVE ADDRESS 1st 7 bits RW A3 11110XX1 541 32142D–06/2013 ATUC64/128/256L3/4U 22.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct. In master transmitter mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NACK value. The DNAK bit in SR reflects the state of the last received ACK/NACK value. Some slaves may not be able to check the received PEC in time to return a NACK if an error occurred. In this case, the slave should always return an ACK after the PEC byte, and some other mechanism must be implemented to verify that the transmission was received correctly. In master receiver mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and SR.PECERR is set. In master receiver mode, the PEC byte is always followed by a NACK transmitted by the master, since it is the last byte in the transfer. The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled when NBYTES reaches zero. The PEC byte is identified in a master receiver transmission if PEC is enabled when NBYTES reaches zero. NBYTES must therefore be written with the total number of data bytes in the transmission, including the PEC byte. In combined transfers, the PECEN bit should only be written to one in the last of the combined transfers. Consider the following transfer: S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P This transfer is generated by writing two commands to the command registers. The first command is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and PECEN=1. Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current byte. No PEC byte will be sent in this case. 22.8.9.2 Timeouts The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is set. 22.8.9.3 SMBus ALERT Signal A slave can get the master’s attention by pulling the TWALM line low. The TWIM will then set the SR.SMBALERT bit. This can be set up to trigger an interrupt, and software can then take the appropriate action, as defined in the SMBus standard. 542 32142D–06/2013 ATUC64/128/256L3/4U 22.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 22-5. Bus Events Event Effect Master transmitter has sent a data byte SR.THR is cleared. Master receiver has received a data byte SR.RHR is set. Start+Sadr sent, no ack received from slave SR.ANAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Data byte sent to slave, no ack received from slave SR.DNAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Arbitration lost SR.ARBLST is set. SR.CCOMP not set. CMDR.VALID remains set. TWCK and TWD immediately released to a pulled-up state. SMBus Alert received SR.SMBALERT is set. SMBus timeout received SR.SMBTOUT is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Master transmitter receives SMBus PEC Error SR.DNAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Master receiver discovers SMBus PEC Error SR.PECERR is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. CR.STOP is written by user SR.STOP is set. SR.CCOMP set. CMDR.VALID remains set. STOP transmitted on bus after current byte transfer has finished. 543 32142D–06/2013 ATUC64/128/256L3/4U 22.9 User Interface Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 22-6. TWIM Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Write-only 0x00000000 0x04 Clock Waveform Generator Register CWGR Read/Write 0x00000000 0x08 SMBus Timing Register SMBTR Read/Write 0x00000000 0x0C Command Register CMDR Read/Write 0x00000000 0x10 Next Command Register NCMDR Read/Write 0x00000000 0x14 Receive Holding Register RHR Read-only 0x00000000 0x18 Transmit Holding Register THR Write-only 0x00000000 0x1C Status Register SR Read-only 0x00000002 0x20 Interrupt Enable Register IER Write-only 0x00000000 0x24 Interrupt Disable Register IDR Write-only 0x00000000 0x28 Interrupt Mask Register IMR Read-only 0x00000000 0x2C Status Clear Register SCR Write-only 0x00000000 0x30 Parameter Register PR Read-only -(1) 0x34 Version Register VR Read-only -(1) 544 32142D–06/2013 ATUC64/128/256L3/4U 22.9.1 Control Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully sent. Writing a zero to this bit has no effect. • SWRST: Software Reset If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly violating the bus semantics. If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit. Writing a zero to this bit has no effect. • SMDIS: SMBus Disable Writing a one to this bit disables SMBus mode. Writing a zero to this bit has no effect. • SMEN: SMBus Enable Writing a one to this bit enables SMBus mode. Writing a zero to this bit has no effect. • MDIS: Master Disable Writing a one to this bit disables the master interface. Writing a zero to this bit has no effect. • MEN: Master Enable Writing a one to this bit enables the master interface. Writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - - - STOP 76543210 SWRST - SMDIS SMEN - - MDIS MEN 545 32142D–06/2013 ATUC64/128/256L3/4U 22.9.2 Clock Waveform Generator Register Name: CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula • DATA: Data Setup and Hold Cycles Clock cycles for data setup and hold count. Prescaled by CWGR.EXP. Used to time THD_DAT, TSU_DAT. • STASTO: START and STOP Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THD_STA, TSU_STA, TSU_STO • HIGH: Clock High Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THIGH. • LOW: Clock Low Cycles Clock cycles in clock low count. Prescaled by CWGR.EXP. Used to time TLOW, TBUF. 31 30 29 28 27 26 25 24 - EXP DATA 23 22 21 20 19 18 17 16 STASTO 15 14 13 12 11 10 9 8 HIGH 76543210 LOW f PRESCALER f CLK_TWIM 2  EXP 1 + = ------------------------- 546 32142D–06/2013 ATUC64/128/256L3/4U 22.9.3 SMBus Timing Register Name: SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are prescaled according to the following formula • THMAX: Clock High Maximum Cycles Clock cycles in clock high maximum count. Prescaled by SMBTR.EXP. Used for bus free detection. Used to time THIGH:MAX. NOTE: Uses the prescaler specified by CWGR, NOT the prescaler specified by SMBTR. • TLOWM: Master Clock Stretch Maximum Cycles Clock cycles in master maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:MEXT • TLOWS: Slave Clock Stretch Maximum Cycles Clock cycles in slave maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:SEXT. 31 30 29 28 27 26 25 24 EXP - - - - 23 22 21 20 19 18 17 16 THMAX 15 14 13 12 11 10 9 8 TLOWM 76543210 TLOWS f prescaled SMBus  f CLKTWIM 2  EXP + 1 = ------------------------ 547 32142D–06/2013 ATUC64/128/256L3/4U 22.9.4 Command Register Name: CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of ending a master receiver transfer. 1: Causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more than 255 bytes are to be received in one single transmission. • PECEN: Packet Error Checking Enable 0: Causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit transmitted or received. Must be used if SMBus mode is disabled. 1: Causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will be performed. • NBYTES: Number of Data Bytes in Transfer The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is transmitted if CMDR.STOP is one. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, i.e. there are NBYTES-1 data bytes and a PEC byte. • VALID: CMDR Valid 0: Indicates that CMDR does not contain a valid command. 1: Indicates that CMDR contains a valid command. This bit is cleared when the command is finished. • STOP: Send STOP Condition 0: Do not transmit a STOP condition after the data bytes have been transmitted. 1: Transmit a STOP condition after the data bytes have been transmitted. • START: Send START Condition 0: The transfer in CMDR should not commence with a START or REPEATED START condition. 1: The transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the command is executed, a START condition is used. If the bus is busy, a REPEATED START is used. • REPSAME: Transfer is to Same Address as Previous Address Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode. 31 30 29 28 27 26 25 24 - - - - ACKLAST PECEN 23 22 21 20 19 18 17 16 NBYTES 15 14 13 12 11 10 9 8 VALID STOP START REPSAME TENBIT SADR[9:7] 76543210 SADR[6:0] READ 548 32142D–06/2013 ATUC64/128/256L3/4U Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode. 1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode. • SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used. • READ: Transfer Direction 0: Allow the master to transmit data. 1: Allow the master to receive data. 549 32142D–06/2013 ATUC64/128/256L3/4U 22.9.5 Next Command Register Name: NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR. If the VALID bit in CMDR is cleared when NCMDR is written, the content is copied immediately. 31 30 29 28 27 26 25 24 - - - - ACKLAST PECEN 23 22 21 20 19 18 17 16 NBYTES 15 14 13 12 11 10 9 8 VALID STOP START REPSAME TENBIT SADR[9:7] 76543210 SADR[6:0] READ 550 32142D–06/2013 ATUC64/128/256L3/4U 22.9.6 Receive Holding Register Name: RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 RXDATA 551 32142D–06/2013 ATUC64/128/256L3/4U 22.9.7 Transmit Holding Register Name: THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 TXDATA 552 32142D–06/2013 ATUC64/128/256L3/4U 22.9.8 Status Register Name: SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled. • STOP: Stop Request Accepted This bit is one when a STOP request caused by writing a one to CR.STOP has been accepted, and transfer has stopped. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • PECERR: PEC Error This bit is one when a SMBus PEC error occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • TOUT: Timeout This bit is one when a SMBus timeout occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • SMBALERT: SMBus Alert This bit is one when an SMBus Alert was received. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • ARBLST: Arbitration Lost This bit is one when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority transmission in progress by a different master. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • DNAK: NAK in Data Phase Received This bit is one when no ACK was received form slave during data transmission. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • ANAK: NAK in Address Phase Received This bit is one when no ACK was received from slave during address phase This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • BUSFREE: Two-wire Bus is Free This bit is one when activity has completed on the two-wire bus. Otherwise, this bit is cleared. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - - MENB 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 76543210 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 553 32142D–06/2013 ATUC64/128/256L3/4U • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • CRDY: Ready for More Commands This bit is one when CMDR and/or NCMDR is ready to receive one or more commands. This bit is cleared when this is no longer true. • TXRDY: THR Data Ready This bit is one when THR is ready for one or more data bytes. This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped). • RXRDY: RHR Data Ready This bit is one when RX data are ready to be read from RHR. This bit is cleared when this is no longer true. 554 32142D–06/2013 ATUC64/128/256L3/4U 22.9.9 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 76543210 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 555 32142D–06/2013 ATUC64/128/256L3/4U 22.9.10 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 76543210 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 556 32142D–06/2013 ATUC64/128/256L3/4U 22.9.11 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 76543210 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 557 32142D–06/2013 ATUC64/128/256L3/4U 22.9.12 Status Clear Register Name: SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 76543210 - - - - CCOMP - - - 558 32142D–06/2013 ATUC64/128/256L3/4U 22.9.13 Parameter Register (PR) Name: PR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------- 559 32142D–06/2013 ATUC64/128/256L3/4U 22.9.14 Version Register (VR) Name: VR Access Type: Read-only Offset: 0x34 Reset Value: - • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION [11:8] 76543210 VERSION [7:0] 560 32142D–06/2013 ATUC64/128/256L3/4U 22.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 22-7. Module Clock Name Module Name Clock Name Description TWIM0 CLK_TWIM0 Clock for the TWIM0 bus interface TWIM1 CLK_TWIM1 Clock for the TWIM1 bus interface Table 22-8. Register Reset Values Register Reset Value VERSION 0x00000110 PARAMETER 0x00000000 561 32142D–06/2013 ATUC64/128/256L3/4U 23. Two-wire Slave Interface (TWIS) Rev.: 1.2.0.1 23.1 Features • Compatible with I²C standard – Transfer speeds of 100 and 400 kbit/s – 7 and 10-bit and General Call addressing • Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK response – SMBALERT interface – 25 ms clock low timeout delay – 25 ms slave cumulative clock low extend time • Compatible with PMBus • DMA interface for reducing CPU load • Arbitrary transfer lengths, including 0 data bytes • Optional clock stretching if transmit or receive buffers not ready for data transfer • 32-bit Peripheral Bus interface for configuration of the interface 23.2 Overview The Atmel Two-wire Slave Interface (TWIS) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus, I²C, or SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or single bytes. Below, Table 23-1 lists the compatibility level of the Atmel Two-wire Slave Interface and a full I²C compatible device. Note: 1. START + b000000001 + Ack + Sr Table 23-1. Atmel TWIS Compatibility with I²C Standard I²C Standard Atmel TWIS Standard-mode (100 kbit/s) Supported Fast-mode (400 kbit/s) Supported 7 or 10 bits Slave Addressing Supported START BYTE(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NAK Management Supported Slope control and input filtering (Fast mode) Supported Clock stretching Supported 562 32142D–06/2013 ATUC64/128/256L3/4U Below, Table 23-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. 23.3 List of Abbreviations 23.4 Block Diagram Figure 23-1. Block Diagram Table 23-2. Atmel TWIS Compatibility with SMBus Standard SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Packet Error Checking Supported Table 23-3. Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Peripheral Bus Bridge Two-wire Interface I/O Controller TWCK TWD Interrupt Controller TWI Interrupt Power Manager CLK_TWIS TWALM 563 32142D–06/2013 ATUC64/128/256L3/4U 23.5 Application Block Diagram Figure 23-2. Application Block Diagram 23.6 I/O Lines Description 23.7 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 23.7.1 I/O Lines TWDand TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 23-5 on page 565). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWALM is used to implement the optional SMBus SMBALERT signal. TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the TWIS, the user must perform the following steps: • Program the I/O Controller to: – Dedicate TWD, TWCK, and optionally TWALM as peripheral lines. – Define TWD, TWCK, and optionally TWALM as open-drain. Host with TWI Interface TWD TWCK Atmel TWI serial EEPROM I²C RTC I²C LCD controller Slave 1 Slave 2 Slave 3 VDD I²C temp. sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp Table 23-4. I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 564 32142D–06/2013 ATUC64/128/256L3/4U 23.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. The TWIS is able to wake the system from sleep mode upon address match, see Section 23.8.8 on page 572. 23.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 23.7.4 DMA The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIS. 23.7.5 Interrupts The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS interrupts requires the interrupt controller to be programmed first. 23.7.6 Debug Operation When an external debugger forces the CPU into debug mode, the TWIS continues normal operation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 23.8 Functional Description 23.8.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 23-4 on page 565). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 23-3). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 23-3. START and STOP Conditions TWD TWCK Start Stop 565 32142D–06/2013 ATUC64/128/256L3/4U Figure 23-4. Transfer Format 23.8.2 Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 23-5. Typical Application Block Diagram 23.8.2.1 Bus Timing The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling can be selected through TR.EXP. TR has the following fields: TLOWS: Prescaled clock cycles used to time SMBUS timeout TLOW:SEXT. TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I²C RTC I²C LCD Controller Slave 1 Slave 2 Slave 3 VDD I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp fPRESCALED f CLK_TWIS 2  EXP 1 + = ------------------------ 566 32142D–06/2013 ATUC64/128/256L3/4U TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. Figure 23-6. Bus Timing Diagram 23.8.2.2 Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR). The following list presents the main steps in a typical communication: 3. Before any transfers can be performed, bus timings must be configured by writing to the Timing Register (TR).If the Peripheral DMA Controller is to be used for the transfers, it must be set up. 4. The Control Register (CR) must be configured with information such as the slave address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and which addresses to match. The interrupt system can be set up to generate interrupt request on specific events or error conditions, for example when a byte has been received. The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to zero. NBYTES is updated by hardware, so in order to avoid hazards, software updates of NBYTES can only be done through writes to the NBYTES register. 23.8.2.3 Address Matching The TWIS can be set up to match several different addresses. More than one address match may be enabled simultaneously, allowing the TWIS to be assigned to several addresses. The address matching phase is initiated after a START or REPEATED START condition. When the TWIS receives an address that generates an address match, an ACK is automatically returned to the master. S t HD:STA t LOW t SU:DAT t HIGH t HD:DAT t LOW P t SU:STO Sr t SU:STA t SU:DAT 567 32142D–06/2013 ATUC64/128/256L3/4U In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The General Call address is checked for address match if CR.GCMATCH is one. In SMBus mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The Alert Response Address is checked for address match if CR.SMAL is one. • The Default Address is checked for address match if CR.SMDA is one. • The Host Header Address is checked for address match if CR.SMHH is one. 23.8.2.4 Clock Stretching Any slave or bus master taking part in a transfer may extend the TWCK low period at any time. The TWIS may extend the TWCK low period after each byte transfer if CR.STREN is one and: • Module is in slave transmitter mode, data should be transmitted, but THR is empty, or • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but the Receive Holding Register (RHR) is full, or • Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains stretched until all address match bits in the Status Register (SR) have been cleared. If CR.STREN is zero and: • Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit the value present in THR (the last transmitted byte or reset value), and set SR.URUN. • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full: Discard the received byte and set SR.ORUN. 23.8.2.5 Bus Errors If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and the TWIS waits for a new START condition. 23.8.3 Slave Transmitter Mode If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it will enter slave transmitter mode and set the SR.TRA bit (note that SR.TRA is set one CLK_TWIS cycle after the relevant address match bit in the same register is set). After the address phase, the following actions are performed: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to transmit. This is necessary in order to know when to transmit the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Byte to transmit depends on I²C/SMBus mode and CR.PEC: – If in I²C mode or CR.PEC is zero or NBYTES is non-zero: The TWIS waits until THR contains a valid data byte, possibly stretching the low period of TWCK. After THR contains a valid data byte, the data byte is transferred to a shifter, and then SR.TXRDY is changed to one because the THR is empty again. – SMBus mode and CR.PEC is one: If NBYTES is zero, the generated PEC byte is automatically transmitted instead of a data byte from THR. TWCK will not be stretched by the TWIS. 3. The data byte in the shifter is transmitted. 568 32142D–06/2013 ATUC64/128/256L3/4U 4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be HIGH (see Figure 23-9). The NAK indicates that the transfer is finished, and the TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, the SR.NAK bit remains LOW. The ACK indicates that more data should be transmitted, jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer Finished (SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be LOW (see Figure 23-9). Also note that in the event that SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to ensure correct TWIS behavior. 6. If STOP is received, SR.TCOMP and SR.STO will be set. 7. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. The slave polls the data line during this clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK means that the master does not wish to receive additional data bytes. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER). SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one. See Figure 23-7 and Figure 23-8. Figure 23-7. Slave Transmitter with One Data Byte TCOMP TXRDY Write THR (DATA) STOP sent by master TWD S DADR R P A DATA N NBYTES set to 1 569 32142D–06/2013 ATUC64/128/256L3/4U Figure 23-8. Slave Transmitter with Multiple Data Bytes Figure 23-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF 23.8.4 Slave Receiver Mode If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one CLK_TWIS cycle after the relevant address match bit in the same register is set). After the address phase, the following is repeated: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to receive. This is necessary in order to know which of the received bytes is the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Receive a byte. Set SR.BTF when done. 3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is used. 4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordinary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC is enabled and the last byte received was a PEC byte (indicated by NBYTES equal to zero), The TWIS will automatically return an ACK if the PEC value was correct, otherwise a NAK will be returned. 5. If STOP is received, SR.TCOMP will be set. 6. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the S DADR R DATA n+5 A P A DATA n A DATA n+m N TCOMP TXRDY Write THR (Data n) NBYTES set to m STOP sent by master TWD Write THR (Data n+1) Write THR (Data n+m) Last data sent DATA (LSB) N P TWCK SR.NAK SR.BTF t1 t1 t1: (CLK_TWIS period) x 2 TWD 570 32142D–06/2013 ATUC64/128/256L3/4U slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 23-10. Slave Receiver with One Data Byte Figure 23-11. Slave Receiver with Multiple Data Bytes 23.8.5 Interactive ACKing Received Data Bytes When implementing a register interface over TWI, it may sometimes be necessary or just useful to report reads and writes to invalid register addresses by sending a NAK to the host. To be able to do this, one must first receive the register address from the TWI bus, and then tell the TWIS whether to ACK or NAK it. In normal operation of the TWIS, this is not possible because the controller will automatically ACK the byte at about the same time as the RXRDY bit changes from zero to one. Writing a one to the Stretch on Data Byte Received bit (CR.SODR) will stretch the clock allowing the user to update CR.ACK bit before returning the desired value. After the last bit in the data byte is received, the TWI bus clock is stretched, the received data byte is transferred to the RHR register, and SR.BTF is set. At this time, the user can examine the received byte and write the desired ACK or NACK value to CR.ACK. When the user clears SR.BTF, the desired ACK value is transferred on the TWI bus. This makes it possible to look at the byte received, determine if it is valid, and then decide to ACK or NAK it. 23.8.6 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. By initializing NBYTES to zero before a transfer, and writing a one to CR.CUP, NBYTES is incremented by one each time a data has been transmitted or received. This allows the user to detect how much data was actually transferred by the DMA system. S DADR W DATA A P A TCOMP RXRDY Read RHR TWD TWD S DADR W DATA n A A A DATA (n+1) A DATA (n+m) DATA (n+m)-1 P A TCOMP RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) 571 32142D–06/2013 ATUC64/128/256L3/4U To assure correct behavior, respect the following programming sequences: 23.8.6.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to transmit. 4. Wait for the Peripheral DMA Controller end-of-transmit flag. 5. Disable the Peripheral DMA Controller. 23.8.6.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to receive. 4. Wait for the Peripheral DMA Controller end-of-receive flag. 5. Disable the Peripheral DMA Controller. 23.8.7 SMBus Mode SMBus mode is enabled by writing a one to the SMBus Mode Enable (SMEN) bit in CR. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be written to TR. • Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). • A dedicated bus line, SMBALERT, allows a slave to get a master’s attention. • A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. Address matching on these addresses can be enabled by configuring CR appropriately. 23.8.7.1 Packet Error Checking (PEC) Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to the Packet Error Checking Enable (PECEN) bit in CR enables automatic PEC handling in the current transfer. The PEC generator is always updated on every bit transmitted or received, so that PEC handling on following linked transfers will be correct. In slave receiver mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC error occurred. In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the master must take appropriate action. The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled when NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if PEC 572 32142D–06/2013 ATUC64/128/256L3/4U enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. 23.8.7.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave will leave the bus. The SR.SMBTOUT bit is also set. 23.8.7.3 SMBALERT A slave can get the master’s attention by pulling the SMBALERT line low. This is done by writing a one to the SMBus Alert (SMBALERT) bit in CR. This will also enable address match on the Alert Response Address (ARA). 23.8.8 Wakeup from Sleep Modes by TWI Address Match The TWIS is able to wake the device up from a sleep mode upon an address match, including sleep modes where CLK_TWIS is stopped. After detecting the START condition on the bus, The TWIS will stretch TWCK until CLK_TWIS has started. The time required for starting CLK_TWIS depends on which sleep mode the device is in. After CLK_TWIS has started, the TWIS releases its TWCK stretching and receives one byte of data on the bus. At this time, only a limited part of the device, including the TWIS, receives a clock, thus saving power. The TWIS goes on to receive the slave address. If the address phase causes a TWIS address match, the entire device is wakened and normal TWIS address matching actions are performed. Normal TWI transfer then follows. If the TWIS is not addressed, CLK_TWIS is automatically stopped and the device returns to its original sleep mode. 23.8.9 Identifying Bus Events This chapter lists the different bus events, and how these affects the bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 23-5. Bus Events Event Effect Slave transmitter has sent a data byte SR.THR is cleared. SR.BTF is set. The value of the ACK bit sent immediately after the data byte is given by CR.ACK. Slave receiver has received a data byte SR.RHR is set. SR.BTF is set. SR.NAK updated according to value of ACK bit received from master. Start+Sadr on bus, but address is to another slave None. Start+Sadr on bus, current slave is addressed, but address match enable bit in CR is not set None. Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set Correct address match bit in SR is set. SR.TRA updated according to transfer direction (updating is done one CLK_TWIS cycle after address match bit is set) Slave enters appropriate transfer direction mode and data transfer can commence. 573 32142D–06/2013 ATUC64/128/256L3/4U Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set, SR.STREN and SR.SOAM are set. Correct address match bit in SR is set. SR.TRA updated according to transfer direction (updating is done one CLK_TWIS cycle after address match bit is set). Slave stretches TWCK immediately after transmitting the address ACK bit. TWCK remains stretched until all address match bits in SR have been cleared. Slave enters appropriate transfer direction mode and data transfer can commence. Repeated Start received after being addressed SR.REP set. SR.TCOMP unchanged. Stop received after being addressed SR.STO set. SR.TCOMP set. Start, Repeated Start, or Stop received in illegal position on bus SR.BUSERR set. SR.STO and SR.TCOMP may or may not be set depending on the exact position of an illegal stop. Data is to be received in slave receiver mode, SR.STREN is set, and RHR is full TWCK is stretched until RHR has been read. Data is to be transmitted in slave receiver mode, SR.STREN is set, and THR is empty TWCK is stretched until THR has been written. Data is to be received in slave receiver mode, SR.STREN is cleared, and RHR is full TWCK is not stretched, read data is discarded. SR.ORUN is set. Data is to be transmitted in slave receiver mode, SR.STREN is cleared, and THR is empty TWCK is not stretched, previous contents of THR is written to bus. SR.URUN is set. SMBus timeout received SR.SMBTOUT is set. TWCK and TWD are immediately released. Slave transmitter in SMBus PEC mode has transmitted a PEC byte, that was not identical to the PEC calculated by the master receiver. Master receiver will transmit a NAK as usual after the last byte of a master receiver transfer. Master receiver will retry the transfer at a later time. Slave receiver discovers SMBus PEC Error SR.SMBPECERR is set. NAK returned after the data byte. Table 23-5. Bus Events Event Effect 574 32142D–06/2013 ATUC64/128/256L3/4U 23.9 User Interface Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 23-6. TWIS Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Read/Write 0x00000000 0x04 NBYTES Register NBYTES Read/Write 0x00000000 0x08 Timing Register TR Read/Write 0x00000000 0x0C Receive Holding Register RHR Read-only 0x00000000 0x10 Transmit Holding Register THR Write-only 0x00000000 0x14 Packet Error Check Register PECR Read-only 0x00000000 0x18 Status Register SR Read-only 0x00000002 0x1C Interrupt Enable Register IER Write-only 0x00000000 0x20 Interrupt Disable Register IDR Write-only 0x00000000 0x24 Interrupt Mask Register IMR Read-only 0x00000000 0x28 Status Clear Register SCR Write-only 0x00000000 0x2C Parameter Register PR Read-only -(1) 0x30 Version Register VR Read-only -(1) 575 32142D–06/2013 ATUC64/128/256L3/4U 23.9.1 Control Register Name: CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match. • ADR: Slave Address Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise. • SODR: Stretch Clock on Data Byte Reception 0: Does not stretch bus clock immediately before ACKing a received data byte. 1: Stretches bus clock immediately before ACKing a received data byte. • SOAM: Stretch Clock on Address Match 0: Does not stretch bus clock after address match. 1: Stretches bus clock after address match. • CUP: NBYTES Count Up 0: Causes NBYTES to count down (decrement) per byte transferred. 1: Causes NBYTES to count up (increment) per byte transferred. • ACK: Slave Receiver Data Phase ACK Value 0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode. 1: Causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode. • PECEN: Packet Error Checking Enable 0: Disables SMBus PEC (CRC) generation and check. 1: Enables SMBus PEC (CRC) generation and check. • SMHH: SMBus Host Header 0: Causes the TWIS not to acknowledge the SMBus Host Header. 1: Causes the TWIS to acknowledge the SMBus Host Header. • SMDA: SMBus Default Address 0: Causes the TWIS not to acknowledge the SMBus Default Address. 1: Causes the TWIS to acknowledge the SMBus Default Address. • SMBALERT: SMBus Alert 0: Causes the TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA). 1: Causes the TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA). 31 30 29 28 27 26 25 24 - - - - - TENBIT ADR[9:8] 23 22 21 20 19 18 17 16 ADR[7:0] 15 14 13 12 11 10 9 8 SODR SOAM CUP ACK PECEN SMHH SMDA SMBALERT 76543210 SWRST - - STREN GCMATCH SMATCH SMEN SEN 576 32142D–06/2013 ATUC64/128/256L3/4U • SWRST: Software Reset This bit will always read as 0. Writing a zero to this bit has no effect. Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address. • SMATCH: Slave Address Match 0: Causes the TWIS not to acknowledge the Slave Address. 1: Causes the TWIS to acknowledge the Slave Address. • SMEN: SMBus Mode Enable 0: Disables SMBus mode. 1: Enables SMBus mode. • SEN: Slave Enable 0: Disables the slave interface. 1: Enables the slave interface. 577 32142D–06/2013 ATUC64/128/256L3/4U 23.9.2 NBYTES Register Name: NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer. NBYTES can be incremented or decremented automatically by hardware. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 NBYTES 578 32142D–06/2013 ATUC64/128/256L3/4U 23.9.3 Timing Register Name: TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled according to the following formula: • SUDAT: Data Setup Cycles Non-prescaled clock cycles for data setup count. Used to time TSU_DAT. Data is driven SUDAT cycles after TWCK low detected. This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode. • TTOUT: SMBus TTIMEOUT Cycles Prescaled clock cycles used to time SMBus TTIMEOUT. • TLOWS: SMBus TLOW:SEXT Cycles Prescaled clock cycles used to time SMBus TLOW:SEXT. 31 30 29 28 27 26 25 24 EXP - - - - 23 22 21 20 19 18 17 16 SUDAT 15 14 13 12 11 10 9 8 TTOUT 76543210 TLOWS f PRESCALED f CLK_TWIS 2  EXP 1 + = ------------------------ 579 32142D–06/2013 ATUC64/128/256L3/4U 23.9.4 Receive Holding Register Name: RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 RXDATA 580 32142D–06/2013 ATUC64/128/256L3/4U 23.9.5 Transmit Holding Register Name: THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 TXDATA 581 32142D–06/2013 ATUC64/128/256L3/4U 23.9.6 Packet Error Check Register Name: PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition. Provided if the user manually wishes to control when the PEC byte is transmitted, or wishes to access the PEC value for other reasons. In ordinary operation, the PEC handling is done automatically by hardware. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 PEC 582 32142D–06/2013 ATUC64/128/256L3/4U 23.9.7 Status Register Name: SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when byte transfer has completed. • REP: Repeated Start Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a REPEATED START condition is received. • STO: Stop Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the STOP condition is received. • SMBDAM: SMBus Default Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the SMBus Default Address. • SMBHHM: SMBus Host Header Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the SMBus Host Header Address. • SMBALERTM: SMBus Alert Response Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the SMBus Alert Response Address. • GCM: General Call Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the General Call Address. • SAM: Slave Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the Slave Address. • BUSERR: Bus Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a misplaced START or STOP condition has occurred. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 76 5 43210 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY 583 32142D–06/2013 ATUC64/128/256L3/4U • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation. • ORUN: Overrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an overrun has occurred in slave receiver mode. Can only occur if CR.STREN is zero. • URUN: Underrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an underrun has occurred in slave transmitter mode. Can only occur if CR.STREN is zero. • TRA: Transmitter Mode 0: The slave is in slave receiver mode. 1: The slave is in slave transmitter mode. • TCOMP: Transmission Complete This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when transmission is complete. Set after receiving a STOP after being addressed. • SEN: Slave Enabled 0: The slave interface is disabled. 1: The slave interface is enabled. • TXRDY: TX Buffer Ready 0: The TX buffer is full and should not be written to. 1: The TX buffer is empty, and can accept new data. • RXRDY: RX Buffer Ready 0: No RX data ready in RHR. 1: RX data is ready to be read from RHR. 584 32142D–06/2013 ATUC64/128/256L3/4U 23.9.8 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will write a one to the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 76 5 43210 ORUN URUN - - TCOMP - TXRDY RXRDY 585 32142D–06/2013 ATUC64/128/256L3/4U 23.9.9 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 76 5 43210 ORUN URUN - - TCOMP - TXRDY RXRDY 586 32142D–06/2013 ATUC64/128/256L3/4U 23.9.10 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 76 5 43210 ORUN URUN - - TCOMP - TXRDY RXRDY 587 32142D–06/2013 ATUC64/128/256L3/4U 23.9.11 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 76 5 43210 ORUN URUN - - TCOMP - - - 588 32142D–06/2013 ATUC64/128/256L3/4U 23.9.12 Parameter Register Name: PR Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------- 589 32142D–06/2013 ATUC64/128/256L3/4U 23.9.13 Version Register (VR) Name: VR Access Type: Read-only Offset: 0x30 Reset Value: - • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION [11:8] 76543210 VERSION [7:0] 590 32142D–06/2013 ATUC64/128/256L3/4U 23.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 23-7. Module Clock Name Module Name Clock Name Description TWIS0 CLK_TWIS0 Clock for the TWIS0 bus interface TWIS1 CLK_TWIS1 Clock for the TWIS1 bus interface Table 23-8. Register Reset Values Register Reset Value VERSION 0x00000120 PARAMETER 0x00000000 591 32142D–06/2013 ATUC64/128/256L3/4U 24. Inter-IC Sound Controller (IISC) Rev: 1.0.0.0 24.1 Features • Compliant with Inter-IC Sound (I2 S) bus specification • Master, slave, and controller modes: – Slave: data received/transmitted – Master: data received/transmitted and clocks generated – Controller: clocks generated • Individual enable and disable of receiver, transmitter, and clocks • Configurable clock generator common to receiver and transmitter: – Suitable for a wide range of sample frequencies (fs), including 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, and 192kHz – 16fs to 1024fs Master Clock generated for external oversampling ADCs • Several data formats supported: – 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format – 16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data transfers • DMA interfaces for receiver and transmitter to reduce processor overhead: – Either one DMA channel for both audio channels, or – One DMA channel per audio channel • Smart holding registers management to avoid audio channels mix after overrun or underrun 24.2 Overview The Inter-IC Sound Controller (IISC) provides a 5-wire, bidirectional, synchronous, digital audio link with external audio devices: ISDI, ISDO, IWS, ISCK, and IMCK pins. This controller is compliant with the Inter-IC Sound (I2 S) bus specification. The IISC consists of a Receiver, a Transmitter, and a common Clock Generator, that can be enabled separately, to provide Master, Slave, or Controller modes with Receiver, Transmitter, or both active. Peripheral DMA channels, separate for the Receiver and for the Transmitter, allow a continuous high bitrate data transfer without processor intervention to the following: • Audio CODECs in Master, Slave, or Controller mode • Stereo DAC or ADC through dedicated I2 S serial interface The IISC can use either a single DMA channel for both audio channels or one DMA channel per audio channel. The 8- and 16-bit compact stereo format allows reducing the required DMA bandwidth by transferring the left and right samples within the same data word. In Master Mode, the IISC allows outputting a 16 fs to 1024fs Master Clock, in order to provide an oversampling clock to an external audio codec or digital signal processor (DSP). 592 32142D–06/2013 ATUC64/128/256L3/4U 24.3 Block Diagram Figure 24-1. IISC Block Diagram 24.4 I/O Lines Description 24.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 24.5.1 I/O lines The IISC pins may be multiplexed with I/O Controller lines. The user must first program the I/O Controller to assign the desired IISC pins to their peripheral function. If the IISC I/O lines are not used by the application, they can be used for other purposes by the I/O Controller. It is required to enable only the IISC inputs and outputs actually in use. 24.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the IISC, the IISC will stop functioning and resume operation after the system wakes up from sleep mode.I/O Controller ISCK IWS ISDI ISDO IMCK Receiver Clocks Transmitter Peripheral Bus interface Generic clock PB Peripheral Bus Bridge Interrupt Controller SCIF Power Manager PB clock IRQ Peripheral DMA Controller Rx Tx IISC Table 24-1. I/O Lines Description Pin Name Pin Description Type IMCK Master Clock Output ISCK Serial Clock Input/Output IWS I2 S Word Select Input/Output ISDI Serial Data Input Input ISDO Serial Data Output Output 593 32142D–06/2013 ATUC64/128/256L3/4U 24.5.3 Clocks The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the IISC before disabling the clock, to avoid freezing the IISC in an undefined state. One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and configured before use. Refer to the module configuration section for details on the GCLK_IISC used for the IISC. The frequency for this clock has to be set as described in Table. 24.5.4 DMA The IISC DMA handshake interfaces are connected to the Peripheral DMA Controller. Using the IISC DMA functionality requires the Peripheral DMA Controller to be programmed first. 24.5.5 Interrupts The IISC interrupt line is connected to the Interrupt Controller. Using the IISC interrupt requires the Interrupt Controller to be programmed first. 24.5.6 Debug Operation When an external debugger forces the CPU into debug mode, the IISC continues normal operation. If this module is configured in a way that requires it to be periodically serviced by the CPU through interrupt requests or similar, improper operation or data loss may result during debugging. 24.6 Functional Description 24.6.1 Initialization The IISC features a Receiver, a Transmitter, and, for Master and Controller modes, a Clock Generator. Receiver and Transmitter share the same Serial Clock and Word Select. Before enabling the IISC, the chosen configuration must be written to the Mode Register (MR). The IMCKMODE, MODE, and DATALENGTH fields in the MR register must be written. If the IMCKMODE field is written as one, then the IMCKFS field should be written with the chosen ratio, as described in Section 24.6.5 ”Serial Clock and Word Select Generation” on page 595. Once the Mode Register has been written, the IISC Clock Generator, Receiver, and Transmitter can be enabled by writing a one to the CKEN, RXEN, and TXEN bits in the Control Register (CR). The Clock Generator can be enabled alone, in Controller Mode, to output clocks to the IMCK, ISCK, and IWS pins. The Clock Generator must also be enabled if the Receiver or the Transmitter is enabled. The Clock Generator, Receiver, and Transmitter can be disabled independently by writing a one to CR.CXDIS, CR.RXDIS and/or CR.TXDIS respectively. Once requested to stop, they will only stop when the transmission of the pending frame transmission will be completed. 24.6.2 Basic Operation The Receiver can be operated by reading the Receiver Holding Register (RHR), whenever the Receive Ready (RXRDY) bit in the Status Register (SR) is set. Successive values read from RHR will correspond to the samples from the left and right audio channels for the successive frames. 594 32142D–06/2013 ATUC64/128/256L3/4U The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), whenever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values written to THR should correspond to the samples from the left and right audio channels for the successive frames. The Receive Ready and Transmit Ready bits can be polled by reading the Status Register. The IISC processor load can be reduced by enabling interrupt-driven operation. The RXRDY and/or TXRDY interrupt requests can be enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER). The interrupt service routine associated to the IISC interrupt request will then be executed whenever the Receive Ready or the Transmit Ready status bit is set. 24.6.3 Master, Controller, and Slave Modes In Master and Controller modes, the IISC provides the Master Clock, the Serial Clock and the Word Select. IMCK, ISCK, and IWS pins are outputs. In Controller mode, the IISC Receiver and Transmitter are disabled. Only the clocks are enabled and used by an external receiver and/or transmitter. In Slave mode, the IISC receives the Serial Clock and the Word Select from an external master. ISCK and IWS pins are inputs. The mode is selected by writing the MODE field of the Mode Register (MR). Since the MODE field changes the direction of the IWS and ISCK pins, the Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS and ISCK pins. 24.6.4 I2 S Reception and Transmission Sequence As specified in the I2 S protocol, data bits are left-adjusted in the Word Select time slot, with the MSB transmitted first, starting one clock period after the transition on the Word Select line. Figure 24-2. I 2 S Reception and Transmission Sequence Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel. The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the MR.DATALENGTH field. If the time slot allows for more data bits than written in the MR.DATALENGTH field, zeroes are appended to the transmitted data word or extra received bits are discarded. If the time slot allows for less data bits than written, the extra bits to be transmitted are not sent or the missing bits are set to zero in the received data word. Serial Clock ISCK Word Select IWS Data ISDI/ISDO MSB Left Channel LSB MSB Right Channel 595 32142D–06/2013 ATUC64/128/256L3/4U 24.6.5 Serial Clock and Word Select Generation The generation of clocks in the IISC is described in Figure 24-3 on page 596. In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK and IWS pins are inputs and no generic clock is required by the IISC. In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock through the Mode Register (MR). IMCK, ISCK, and IWS pins are outputs and a generic clock is used to derive the IISC clocks. Audio codecs connected to the IISC pins may require a Master Clock signal with a frequency multiple of the audio sample frequency (fs), such as 256fs. When the IISC is in Master mode, writing a one to MR.IMCKMODE will output GCLK_IISC as Master Clock to the IMCK pin, and will divide GCLK_IISC to create the internal bit clock, output on the ISCK pin. The clock division factor is defined by writing to MR.IMCKFS and MR.DATALENGTH, as described ”IMCKFS: Master Clock to fs Ratio” on page 602. The Master Clock (IMCK) frequency is 16*(IMCKFS+1) times the sample frequency (fs), i.e. IWS frequency. The Serial Clock (ISCK) frequency is 2*Slot Length times the sample frequency (fs), where Slot Length is defined in Table 24-2 on page 595. Warning: MR.IMCKMODE should only be written as one if the Master Clock frequency is strictly higher than the Serial Clock. If a Master Clock output is not required, the GCLK_IISC generic clock is used as ISCK, by writing a zero to MR.IMCKMODE. Alternatively, if the frequency of the generic clock used is a multiple of the required ISCK frequency, the IMCK to ISCK divider can be used with the ratio defined by writing the MR.IMCKFS field. The IWS pin is used as Word Select as described in Section 24.6.4. Table 24-2. Slot Length MR.DATALENGTH Word Length Slot Length 0 32 bits 32 1 24 bits 32 if MR.IWS24 is zero 24 if MR.IWS24 is one 2 20 bits 3 18 bits 4 16 bits 16 5 16 bits compact stereo 6 8 bits 8 7 8 bits compact stereo 596 32142D–06/2013 ATUC64/128/256L3/4U Figure 24-3. IISC Clocks Generation 24.6.6 Mono When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel is duplicated to the right output channel. When the Receive Mono (RXMONO) in the Mode Register is set, data received from the left channel is duplicated to the right channel. 24.6.7 Holding Registers The IISC user interface includes a Receive Holding Register (RHR) and a Transmit Holding Register (THR). RHR and THR are used to access audio samples for both audio channels. When a new data word is available in the RHR register, the Receive Ready bit (RXRDY) in the Status Register (SR) is set. Reading the RHR register will clear this bit. A receive overrun condition occurs if a new data word becomes available before the previous data word has been read from the RHR register. Then, the Receive Overrun bit in the Status Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the current receive channel number. When the THR register is empty, the Transmit Ready bit (TXRDY) in the Status Register (SR) is set. Writing into the THR register will clear this bit. A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is transmitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current transmit channel number is transmitted. MR.MODE = SLAVE Clock divider MR.DATALENGTH GCLK_IISC Clock enable Clock divider CR.CKEN/CKDIS MR.IMCKMODE MR.DATALENGTH MR.IMCKFS MR.IMCKMODE 0 1 IMCK pin output Clock enable CR.CKEN/CKDIS Internal bit clock ISCK pin input 1 0 ISCK pin output Internal word clock IWS pin input 1 0 IWS pin output 597 32142D–06/2013 ATUC64/128/256L3/4U Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses bits 15 through 8 of the same data word. 24.6.8 DMA Operation The Receiver and the Transmitter can each be connected either to one single Peripheral DMA channel or to one Peripheral DMA channel per data channel. This is selected by writing to the MR.RXDMA and MR.TXDMA bits. If a single Peripheral DMA channel is selected, all data samples use IISC Receiver or Transmitter DMA channel 0. The Peripheral DMA reads from the RHR register and writes to the RHR register for both audio channels, successively. The Peripheral DMA transfers may use 32-bit word, 16-bit halfword, or 8-bit byte according to the value of the MR.DATALENGTH field. 24.6.9 Loop-back Mode For debugging purposes, the IISC can be configured to loop back the Transmitter to the Receiver. Writing a one to the MR.LOOP bit will internally connect ISDO to ISDI, so that the transmitted data is also received. Writing a zero to MR.LOOP will restore the normal behavior with independent Receiver and Transmitter. As for other changes to the Receiver or Transmitter configuration, the IISC Receiver and Transmitter must be disabled before writing to the MR register to update MR.LOOP. 24.6.10 Interrupts An IISC interrupt request can be triggered whenever one or several of the following bits are set in the Status Register (SR): Receive Ready (RXRDY), Receive Overrun (RXOR), Transmit Ready (TXRDY), or Transmit Underrun (TXOR). The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one the corresponding bit in the Status Clear Register (SCR). For debugging purposes, interrupt requests can be simulated by writing a one to the corresponding bit in the Status Set Register (SSR). 598 32142D–06/2013 ATUC64/128/256L3/4U Figure 24-4. Interrupt Block Diagram 24.7 IISC Application Examples The IISC can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the IISC are not listed here. Figure 24-5. Audio Application Block Diagram IER IDR IMR Set Clear Interrupt Control IISC Interrupt Request TXRDY TXUR Transmitter Receiver RXRDY RXOR Serial Clock Word Select Serial Data Out MSB LSB MSB Serial Data Out Word Select Serial Clock IISC ISCK IWS ISDO ISDI EXTERNAL I 2 S RECEIVER 599 32142D–06/2013 ATUC64/128/256L3/4U Figure 24-6. Codec Application Block Diagram Figure 24-7. Time Slot Application Block Diagram IISC Word Select Serial Data Out Serial Data In EXTERNAL AUDIO CODEC IMCK IWS ISDO ISDI Serial Clock Master Clock ISCK Right Time Slot Serial Clock Word Select Serial Data Out Serial Data In Dstart Dend Left Time Slot EXTERNAL AUDIO CODEC for Left Time Slot EXTERNAL AUDIO CODEC for Right Time Slot Serial Data In Serial Data Out Word Select Serial Clock Serial Clock Word Select Serial Data Out Serial Data In Dstart Left Time Slot Right Time Slot Dend IISC ISCK IWS ISDO ISDI Master Clock IMCK 600 32142D–06/2013 ATUC64/128/256L3/4U 24.8 User Interface Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 24-3. IISC Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Write-only 0x00000000 0x04 Mode Register MR Read/Write 0x00000000 0x08 Status Register SR Read-only 0x00000000 0x0C Status Clear Register SCR Write-only 0x00000000 0x10 Status Set Register SSR Write-only 0x00000000 0x14 Interrupt Enable Register IER Write-only 0x00000000 0x18 Interrupt Disable Register IDR Write-only 0x00000000 0x1C Interrupt Mask Register IMR Read-only 0x00000000 0x20 Receiver Holding Register RHR Read-only 0x00000000 0x24 Transmitter Holding Register THR Write-only 0x00000000 0x28 Version Register VERSION Read-only - (1) 0x2C Parameter Register PARAMETER Read-only - (1) 601 32142D–06/2013 ATUC64/128/256L3/4U 24.8.1 Control Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 The Control Register should only be written to enable the IISC after the chosen configuration has been written to the Mode Register, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR. • SWRST: Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all the registers in the module. The module will be disabled after the reset. This bit always reads as zero. • TXDIS: Transmitter Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the IISC Transmitter. SR.TXEN will be cleared when the Transmitter is effectively stopped. • TXEN: Transmitter Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the IISC Transmitter, if TXDIS is not one. SR.TXEN will be set when the Transmitter is effectively started. • CKDIS: Clocks Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the IISC clocks generation. • CKEN: Clocks Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the IISC clocks generation, if CKDIS is not one. • RXDIS: Receiver Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the IISC Receiver. SR.TXEN will be cleared when the Transmitter is effectively stopped. • RXEN: Receiver Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the IISC Receiver, if RXDIS is not one. SR.RXEN will be set when the Receiver is effectively started. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 SWRST - TXDIS TXEN CKDIS CKEN RXDIS RXEN 602 32142D–06/2013 ATUC64/128/256L3/4U 24.8.2 Mode Register Name: MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR. • IWS24: IWS TDM Slot Width 0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit 1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit Refer to Table 24-2, “Slot Length,” on page 595. • IMCKMODE: Master Clock Mode 0: No Master Clock generated (generic clock is used as ISCK output) 1: Master Clock generated (generic clock is used as IMCK output) Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to Section 24.6.5 ”Serial Clock and Word Select Generation” on page 595 and Table 24-2, “Slot Length,” on page 595. • IMCKFS: Master Clock to fs Ratio Master Clock frequency is 16*(IMCKFS+1) times the sample rate, i.e. IWS frequency: 31 30 29 28 27 26 25 24 IWS24 IMCKMODE IMCKFS 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO 76543210 - - - DATALENGTH - MODE Table 24-4. Master Clock to Sample Frequency (fs) Ratio fs Ratio IMCKFS 16 fs 0 32 fs 1 48fs 2 64 fs 3 96fs 5 128 fs 7 192fs 11 256 fs 15 603 32142D–06/2013 ATUC64/128/256L3/4U • TXSAME: Transmit Data when Underrun 0: Zero sample transmitted when underrun 1: Previous sample transmitted when underrun • TXDMA: Single or multiple DMA Channels for Transmitter 0: Transmitter uses a single DMA channel for both audio channels 1: Transmitter uses one DMA channel per audio channel • TXMONO: Transmit Mono 0: Stereo 1: Mono, with left audio samples duplicated to right audio channel by the IISC • RXLOOP: Loop-back Test Mode 0: Normal mode 1: ISDO output of IISC is internally connected to ISDI input • RXMONO: Receive Mono 0: Stereo 1: Mono, with left audio samples duplicated to right audio channel by the IISC • RXDMA: Single or multiple DMA Channels for Receiver 0: Receiver uses a single DMA channel for both audio channels 1: Receiver uses one DMA channel per audio channel- • DATALENGTH: Data Word Length • MODE: Mode 384 fs 23 512 fs 31 768 fs 47 1024 fs 63 Table 24-5. Data Word Length DATALENGTH Word Length Comments 0 32 bits 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo Left sample in bits 15 through 0 and right sample in bits 31 through 16 of the same word 6 8 bits 7 8 bits compact stereo Left sample in bits 7 through 0 and right sample in bits 15 through 8 of the same word Table 24-6. Mode MODE Comments 0 SLAVE ISCK and IWS pin inputs used as Bit Clock and Word Select/Frame Sync. 1 MASTER Bit Clock and Word Select/Frame Sync generated by IISC from GCLK_IISC and output to ISCK and IWS pins. GCLK_IISC is output as Master Clock on IMCK if MR.IMCKMODE is one. Table 24-4. Master Clock to Sample Frequency (fs) Ratio fs Ratio IMCKFS 604 32142D–06/2013 ATUC64/128/256L3/4U 24.8.3 Status Register Name: SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 • TXURCH: Transmit Underrun Channel This field is cleared when SCR.TXUR is written to one Bit i of this field is set when a transmit underrun error occurred in channel i (i=0 for first channel of the frame) • RXORCH: Receive Overrun Channel This field is cleared when SCR.RXOR is written to one Bit i of this field is set when a receive overrun error occurred in channel i (i=0 for first channel of the frame) • TXUR: Transmit Underrun This bit is cleared when the corresponding bit in SCR is written to one This bit is set when an underrun error occurs on the THR register or when the corresponding bit in SSR is written to one • TXRDY: Transmit Ready This bit is cleared when data is written to THR This bit is set when the THR register is empty and can be written with new data to be transmitted • TXEN: Transmitter Enabled This bit is cleared when the Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request This bit is set when the Transmitter is effectively enabled, following a CR.TXEN request • RXOR: Receive Overrun This bit is cleared when the corresponding bit in SCR is written to one This bit is set when an overrun error occurs on the RHR register or when the corresponding bit in SSR is written to one • RXRDY: Receive Ready This bit is cleared when the RHR register is read This bit is set when received data is present in the RHR register • RXEN: Receiver Enabled This bit is cleared when the Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request This bit is set when the Receiver is effectively enabled, following a CR.RXEN request 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - TXURCH - - - - 15 14 13 12 11 10 9 8 - - - - - - RXORCH 76543210 - TXUR TXRDY TXEN - RXOR RXRDY RXEN 605 32142D–06/2013 ATUC64/128/256L3/4U 24.8.4 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - TXURCH - - - - 15 14 13 12 11 10 9 8 - - - - - - RXORCH 76543210 - TXUR - - - RXOR - - 606 32142D–06/2013 ATUC64/128/256L3/4U 24.8.5 Status Set Register Name: SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in SR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - TXURCH - - - - 15 14 13 12 11 10 9 8 - - - - - - RXORCH 76543210 - TXUR - - - RXOR - - 607 32142D–06/2013 ATUC64/128/256L3/4U 24.8.6 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - TXUR TXRDY - - RXOR RXRDY - 608 32142D–06/2013 ATUC64/128/256L3/4U 24.8.7 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - TXUR TXRDY - - RXOR RXRDY - 609 32142D–06/2013 ATUC64/128/256L3/4U 24.8.8 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - TXUR TXRDY - - RXOR RXRDY - 610 32142D–06/2013 ATUC64/128/256L3/4U 24.8.9 Receive Holding Register Name: RHR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 • RHR: Received Word This field is set by hardware to the last received data word. If MR.DATALENGTH specifies less than 32 bits, data shall be rightjustified into the RHR field. 31 30 29 28 27 26 25 24 RHR[31:24] 23 22 21 20 19 18 17 16 RHR[23:16] 15 14 13 12 11 10 9 8 RHR[15:8] 76543210 RHR[7:0] 611 32142D–06/2013 ATUC64/128/256L3/4U 24.8.10 Transmit Holding Register Name: THR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 • THR: Data Word to Be Transmitted Next data word to be transmitted after the current word if TXRDY is not set. If MR.DATALENGTH specifies less than 32 bits, data shall be right-justified into the THR field. 31 30 29 28 27 26 25 24 THR[31:24] 23 22 21 20 19 18 17 16 THR[23:16] 15 14 13 12 11 10 9 8 THR[15:8] 76543210 THR[7:0] 612 32142D–06/2013 ATUC64/128/256L3/4U 24.8.11 Module Version Name: VERSION Access Type: Read-only Offset: 0x28 Reset Value: - • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 613 32142D–06/2013 ATUC64/128/256L3/4U 24.8.12 Module Parameters Name: PARAMETER Access Type: Read-only Offset: 0x2C Reset Value: - Reserved. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------- 614 32142D–06/2013 ATUC64/128/256L3/4U 24.9 Module configuration The specific configuration for each IISC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 24-7. IISC Clocks Clock Name Description CLK_IISC Clock for the IISC bus interface GCLK The generic clock used for the IISC is GCLK6 Table 24-8. Register Reset Values Register Reset Value VERSION 0x00000100 615 32142D–06/2013 ATUC64/128/256L3/4U 25. Pulse Width Modulation Controller (PWMA) Rev: 2.0.1.0 25.1 Features • Left-aligned non-inverted 12-bit PWM • Common 12-bit timebase counter – Asynchronous clock source supported – Spread-spectrum counter to allow a constantly varying duty cycle • Separate 12-bit duty cycle register per channel • Synchronized channel updates – No glitches when changing the duty cycles • Interlinked operation supported – Up to 32 channels can be updated with the same duty cycle value at a time – Up to 4 channels can be updated with different duty cycle values at a time • Interrupt on PWM timebase overflow • Incoming peripheral events supported – Pre-defined channels support incoming (increase/decrease) peripheral events from the Peripheral Event System – Incoming increase/decrease event can either increase or decrease the duty cycle by one • One output peripheral event supported – Connected to channel 0 and asserted when the common timebase counter is equal to the programmed duty cycle for channel 0 • Output PWM waveforms – Support normal waveform output for each channel – Support composite waveform generation (XOR’ed) for each pair channels • Open drain driving on selected pins for 5V PWM operation 25.2 Overview The Pulse Width Modulation Controller (PWMA) controls several pulse width modulation (PWM) channels. The number of channels is specific to the device. Each channel controls one square output PWM waveform. Characteristics of the output PWM waveforms such as period and duty cycle are configured through the user interface. All user interface registers are mapped on the peripheral bus. The duty cycle value for each channel can be set independently, while the period is determined by a common timebase counter (TC). The timebase for the counter is selected by using the allocated asynchronous Generic Clock (GCLK). The user interface for the PWMA contains handshake and synchronizing logic to ensure that no glitches occur on the output PWM waveforms while changing the duty cycle values. PWMA duty cycle values can be changed using two approaches, either an interlinked singlevalue mode or an interlinked multi-value mode. In the interlinked single-value mode, any set of channels, up to 32 channels, can be updated simultaneously with the same value while the other channels remain unchanged. There is also an interlinked multi-value mode, where the 8 least significant bits of up to 4 channels can be updated with 4 different values while the other channels remain unchanged. Some pins can be driven in open drain mode, allowing the PWMA to generate a 5V waveform using an external pullup resistor. 616 32142D–06/2013 ATUC64/128/256L3/4U 25.3 Block Diagram Figure 25-1. PWMA Block Diagram 25.4 I/O Lines Description Each channel outputs one PWM waveform on one external I/O line. 25.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. PWM Blocks Channel m Channel 1 Channel 0 Duty Cycle Register COMP PWMA[m:0] Interrupt Handling IRQ PB TOP Timebase Counter SPREAD Adjust TOFL READY Channel_0 CLK_PWMA GCLK Domain PB Clock Domain Spread Spectrum Counter Sync GCLK ETV Control Duty Cycle Channel Select WAVEXOR CWG TCLR CHERR Table 25-1. I/O Line Description Pin Name Pin Description Type PWMA[n] Output PWM waveform for one channel n Output PWMMOD[n] Output PWM waveform for one channel n, open drain mode Output 617 32142D–06/2013 ATUC64/128/256L3/4U 25.5.1 I/O Lines The pins used for interfacing the PWMA may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired PWMA pins to their peripheral function. It is only required to enable the PWMA outputs actually in use. 25.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the PWMA, the PWMA will stop functioning and resume operation after the system wakes up from sleep mode. 25.5.3 Clocks The clock for the PWMA bus interface (CLK_PWMA) is controlled by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the PWMA before disabling the clock, to avoid freezing the PWMA in an undefined state. Additionally, the PWMA depends on a dedicated Generic Clock (GCLK). The GCLK can be set to a wide range of frequencies and clock sources and must be enabled in the System Control Interface (SCIF) before the PWMA can be used. 25.5.4 Interrupts The PWMA interrupt request lines are connected to the interrupt controller. Using the PWMA interrupts requires the interrupt controller to be programmed first. 25.5.5 Peripheral Events The PWMA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 25.5.6 Debug Operation When an external debugger forces the CPU into debug mode, the PWMA continues normal operation. If the PWMA is configured in a way that requires it to be periodically serviced by the CPU through interrupts, improper operation or data loss may result during debugging. 25.6 Functional Description The PWMA embeds a number of PWM channel submodules, each providing an output PWM waveform. Each PWM channel contains a duty cycle register and a comparator. A common timebase counter for all channels determines the frequency and the period for all the PWM waveforms. 25.6.1 Enabling the PWMA Once the GCLK has been enabled, the PWMA is enabled by writing a one to the EN bit in the Control Register (CR). 25.6.2 Timebase Counter The top value of the timebase counter defines the period of the PWMA output waveform. The timebase counter starts at zero when the PWMA is enabled and counts upwards until it reaches its effective top value (ETV). The effective top value is defined by specifying the desired number of GCLK clock cycles in the TOP field of Top Value Register (TVR.TOP) in normal operation (the 618 32142D–06/2013 ATUC64/128/256L3/4U SPREAD field of CR (CR.SPREAD) is zero). When the timebase counter reaches its effective top value, it restarts counting from zero. The period of the PWMA output waveform is then: The timebase counter can be reset by writing a one to the Timebase Clear bit in CR (CR.TCLR). Note that this can cause a glitch to the output PWM waveforms in use. 25.6.3 Spread Spectrum Counter The spread spectrum counter allows the generation of constantly varying duty cycles on the output PWM waveforms. This is achieved by varying the effective top value of the timebase counter in a range defined by the spread spectrum counter value. When CR.SPREAD is not zero, the spread spectrum counter is enabled. Its range is defined by CR.SPREAD. It starts to count from -CR.SPREAD when the PWMA is enabled or after reset and counts upwards. When it reaches CR.SPREAD, it restarts to count from -CR.SPREAD again. The spread spectrum counter will cause the effective top value to vary from TOPSPREAD to TOP+SPREAD. Figure 25-2 on page 618 illustrates this. This leads to a constantly varying duty cycle on the PWM output waveforms though the duty cycle values stored are unchanged. Figure 25-2. PWMA Adjusting Top Value for Timebase Counter 25.6.3.1 Special considerations The maximum value of the timebase counter is 0x0FFF. If SPREAD is written to a value that will cause the ETV to exceed this value, the spread spectrum counter’s range will be limited to prevent the timebase counter to exceed its maximum value. If SPREAD is written to a value causing (TOP-SPREAD) to be below zero, the spread spectrum counter’s range will be limited to prevent the timebase counter to count below zero. In both cases, the SPREAD value read from the Control Register will be the same value as written to the SPREAD field. TPWMA   ETV + 1 TGCLK =  0x0 0x0FFF Duty Cycle -SPREAD SPREAD TOP Adjusting top value range for the timerbase counter 619 32142D–06/2013 ATUC64/128/256L3/4U When writing a one to CR.TCLR, the timebase counter and the spread spectrum counter are reset at their lower limit values and the effective top value of the timebase counter will also be reset. 25.6.4 Duty Cycle and Waveform Properties Each PWM channel has its own duty cycle value (DCV) which is write-only and cannot be read out. The duty cycle value can be changed in two approaches as described in Section25.6.6. When the duty cycle value is zero, the PWM output is zero. Otherwise, the PWM output is set when the timebase counter is zero, and cleared when the timebase counter reaches the duty cycle value. This is summarized as: Note that when increasing the duty cycle value for one channel from 0 to 1, the number of GCLK cycles when the PWM waveform is high will jump from 0 to 2. When incrementing the duty cycle value by one for any other values, the number of GCLK cycle when the waveform is high will increase by one. This is summarized in Table 25-2. 25.6.5 Waveform Output PWMA waveforms are output to I/O lines. The output waveform properties are controlled by Composite Waveform Generation (CWG) register(s). If this register is cleared (by default), the channel waveforms are out directly to the I/O lines. To avoid too many I/O toggling simultaneously on the output I/O lines, every other output PWM waveform toggles on the negative edge of the GCLK instead of the positive edge. In CWG mode, all channels are paired and their outputs are XOR’ed together if the corresponding bit of CWG register is set. The even number of output is the XOR’ed output and the odd number of output is the inverse of its. Each bit of CWG register controls one pair channels and the least significant bit refers to the lowest number of pair channels. 25.6.6 Updating Duty Cycle Values 25.6.6.1 Interlinked Single Value PWM Operation The PWM channels can be interlinked to allow multiple channels to be updated simultaneously with the same duty cycle value. This value must be written to the Interlinked Single Value Duty Table 25-2. PMW Waveform Duty Cycles Duty Cycle Value #Clock Cycles When Waveform is High #Clock Cycles When Waveform is Low 0 0 ETV+1 1 2 ETV-1 2 3 ETV-2 ... ... ... ETV-1 ETV 1 ETV ETV+1 0 PWM Waveform = low when DCV = 0 or TC DCV  high when TC DCV  and DCV  0   620 32142D–06/2013 ATUC64/128/256L3/4U (ISDUTY) register. Each channel has a corresponding enabling bit in the Interlinked Single Value Channel Set (ISCHSET) register(s). When a bit is written to one in the ISCHSET register, the duty cycle register for the corresponding channel will be updated with the value stored in the ISDUTY register. It can only be updated when the READY bit in the Status Register (SR.READY) is one, indicating that the PWMA is ready for writing. Figure 25-3 on page 620 shows the writing procedure. It is thus possible to update the duty cycle values for up to 32 PWM channels within one ISCHSET register at a time. Figure 25-3. Interlinked Single Value PWM Operation Flow 25.6.6.2 Interlinked Multiple Value PWM Operation The interlinked multiple value PWM operation allows up to four channels to be updated simultaneously with different duty cycle values. The four duty cycle values are required to be written to the four registers, DUTY3, DUTY2, DUTY1 and DUTY0 , respectively. The index number of the four channels to be updated is written to the four SEL fields in the Interlinked Multiple Value Channel Select (IMCHSEL) register (IMCHSEL.SEL). When the IMCHSEL register is written, the values stored in the DUTY0/1/2/3 registers are synchronized to the duty cycle registers for the channels selected by the SEL fields. Figure 25-4 on page 620 shows the writing procedure. Note that only writes to the implemented channels will be effective. If one of the IMCHSEL.SEL fields points to a non-existing channel, the corresponding value in the DUTYx register will not be written. If the same channel is specified multiple times in the IMCHSEL.SEL fields, the channel will be updated with the value referred by the upper IMCHSEL.SEL field. When only the least significant 8-bits duty cycle value are considered for updating, the four duty cycle values can be written to the IMDUTY register once. This is equivalent to writing the four duty cycle values to the four DUTY registers one by one. Figure 25-4. Interlinked Multiple Value PWM Operation Flow ISCHSETm ... Write Enable Channeln DUTY Channel1 DUTY Channel0 DUTY ISDUTY Channel2 DUTY DUTY3/2/1/0 IMDUTY IMCHSEL Channeln DUTY ... MUX Channel1 DUTY Channel0 DUTY 621 32142D–06/2013 ATUC64/128/256L3/4U 25.6.7 Open Drain Mode Some pins can be used in open drain mode, allowing the PWMA waveform to toggle between 0V and up to 5V on these pins. In this mode the PWMA will drive the pin to zero or leave the output open. An external pullup can be used to pull the pin up to the desired voltage. To enable open drain mode on a pin the PWMAOD function must be selected instead of the PWMA function in the I/O Controller. Please refer to the Module Configuration chapter for information about which pins are available in open drain mode. 25.6.8 Synchronization Both the timebase counter and the spread spectrum counter can be reset and the duty cycle registers can be written through the user interface of the module. This requires a synchronization between the PB and GCLK clock domains, which takes a few clock cycles of each clock domain. The BUSY bit in SR indicates when the synchronization is ongoing. Writing to the module while the BUSY bit is set will result in discarding the new value. Note that the duty cycle registers will not be updated with the new values until the timebase counter reaches its top value, in order to avoid glitches. The BUSY bit in SR will always be set during this updating and synchronization period. 25.6.9 Interrupts When the timebase counter overflows, the Timebase Overflow bit in the Status Register (SR.TOFL) is set. If the corresponding bit in the Interrupt Mask Register (IMR) is set, an interrupt request will be generated. Since the user needs to wait until the user interface is available between each write due to synchronization, a READY bit is provided in SR, which can be used to generate an interrupt request. The interrupt request will be generated if the corresponding bit in IMR is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one to the corresponding bit in the Status Clear Register (SCR). 25.6.10 Peripheral Events 25.6.10.1 Input Peripheral Events The pre-defined channels support input peripheral events from the Peripheral Event System. Input peripheral events must be enabled by writing a one to the corresponding bit in the Channel Event Enable Registers (CHEERs) before peripheral events can be used to control the duty cycle value. Each bit in the register corresponds to one channel, where bit 0 corresponds to channel 0 and so on. Both the increase and decrease events are enabled for the corresponding channel when a bit in the CHEER register is set. An increase or decrease event (event_incr/event_decr) can either increase or decrease the duty cycle value by one in a PWM period. The events are taken into account when the common timebase counter reaches its top. The behavior is defined by the Channel Event Response Register (CHERR). Each bit in the register corresponds to one channel, where bit 0 corresponds to channel 0 and so on. If the bit in CHERR is set to 0 (default) for a channel, the increase event will increase the duty cycle value and the decrease event will decrease the duty cycle value for that channel. If the bit is set to 1, the increase and decrease event will have reverse function so that 622 32142D–06/2013 ATUC64/128/256L3/4U the increase event will decrease the duty cycle value and decrease event will increase the duty cycle value. If both the increase event and the decrease event occur at the same time for a channel, the duty cycle value will not be changed. The number of channels supporting input peripheral events is device specific. Please refer to the Module Configuration section at the end of this chapter for details. 25.6.10.2 Output Peripheral Event The PWMA also supports one output peripheral event (event_ch0) to the Peripheral Event System. This output peripheral event is connected to channel 0 and will be asserted when the timebase counter reaches the duty cycle value for channel 0. This output event is always enabled. 623 32142D–06/2013 ATUC64/128/256L3/4U 25.7 User Interface Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 25-3. PWMA Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Read/Write 0x00000000 0x04 Interlinked Single Value Duty Register ISDUTY Write-only 0x00000000 0x08 Interlinked Multiple Value Duty Register IMDUTY Write-only 0x00000000 0x0C Interlinked Multiple Value Channel Select IMCHSEL Write-only 0x00000000 0x10 Interrupt Enable Register IER Write-only 0x00000000 0x14 Interrupt Disable Register IDR Write-only 0x00000000 0x18 Interrupt Mask Register IMR Read-only 0x00000000 0x1C Status Register SR Read-only 0x00000000 0x20 Status Clear Register SCR Write-only 0x00000000 0x24 Parameter Register PARAMETER Read-only - (1) 0x28 Version Register VERSION Read-only - (1) 0x2C Top Value Register TVR Read/Write 0x00000000 0x30+m*0x10 Interlinked Single Value Channel Set m ISCHSETm Write-only 0x00000000 0x34+m*0x10 Channel Event Response Register m CHERRm Read/Write 0x00000000 0x38+m*0x10 Channel Event Enable Register m CHEERm Read/Write 0x00000000 0x3C+k*0x10 CWG Register CWGk Read/Write 0x00000000 0x80 Interlinked Multiple Value Duty0 Register DUTY0 Write-only 0x00000000 0x84 Interlinked Multiple Value Duty1 Register DUTY1 Write-only 0x00000000 0x88 Interlinked Multiple Value Duty2 Register DUTY2 Write-only 0x00000000 0x8C Interlinked Multiple Value Duty3 Register DUTY3 Write-only 0x00000000 624 32142D–06/2013 ATUC64/128/256L3/4U 25.7.1 Control Register Name: CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • SPREAD: Spread Spectrum Limit Value The spread spectrum limit value, together with the TOP field, defines the range for the spread spectrum counter. It is introduced in order to achieve constant varying duty cycles on the output PWM waveforms. Refer to Section25.6.3 for more information. • TOP: Timebase Counter Top Value The top value for the timebase counter. The value written to this field will update the least significant 8 bits of the TVR.TOP field in case only 8-bits resolution is required. The 4 most significant bits of TVR.TOP will be written to 0. When the TVR.TOP field is written, this CR.TOP field will also be updated with only the least significant 8 bits of TVR.TOP field. • TCLR: Timebase Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the timebase counter. This bit is always read as zero. • EN: Module Enable 0: The PWMA is disabled 1: The PWMA is enabled 31 30 29 28 27 26 25 24 - - - - - - - SPREAD[8] 23 22 21 20 19 18 17 16 SPREAD[7:0] 15 14 13 12 11 10 9 8 TOP 76543210 - - - - - - TCLR EN 625 32142D–06/2013 ATUC64/128/256L3/4U 25.7.2 Interlinked Single Value Duty Register Name: ISDUTY Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 • DUTY: Duty Cycle Value The duty cycle value written to this field is written simultaneously to all channels selected in the ISCHSETm register. If the value zero is written to DUTY all affected channels will be disabled. In this state the output waveform will be zero all the time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - DUTY[11:8] 76543210 DUTY[7:0] 626 32142D–06/2013 ATUC64/128/256L3/4U 25.7.3 Interlinked Multiple Value Duty Register Name: IMDUTY Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 • DUTYn: Duty Cycle The value written to DUTY field n will be automatically written to the least significant 8 bits of the DUTYn register for a PWMA channel while the most significant 4bits of the DUTYn register are unchanged. Which channel is selected for updating is defined by the corresponding SEL field in the IMCHSEL register. To write mulitple channels at a time with more than 8 bits of the duty cycle value, refer to DUTY3/2/1/0 registers. If the value zero is written to DUTY all affected channels will be disabled. In this state the output waveform will be zero all the time. 31 30 29 28 27 26 25 24 DUTY3 23 22 21 20 19 18 17 16 DUTY2 15 14 13 12 11 10 9 8 DUTY1 76543210 DUTY0 627 32142D–06/2013 ATUC64/128/256L3/4U 25.7.4 Interlinked Multiple Value Channel Select Name: IMCHSEL Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 • SELn: Channel Select The duty cycle of the PWMA channel SELn will be updated with the value stored in the DUTYn register when IMCHSEL is written. If SELn points to a non-implemented channel, the write will be discarded. Note: The duty registers will be updated with the value stored in the DUTY3, DUTY2, DUTY1 and DUTY0 registers when the IMCHSEL register is written. Synchronization takes place immediately when an IMCHSEL register is written. The duty cycle registers will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches. When only 8 bits duty cycle value are considered for updating, the four duty cycle values can be written to the IMDUTY register once. This is equivalent to writing the 8 bits four duty cycle values to the four DUTY registers one by one while the upper 4 bits remain unchanged. 31 30 29 28 27 26 25 24 SEL3 23 22 21 20 19 18 17 16 SEL2 15 14 13 12 11 10 9 8 SEL1 76543210 SEL0 628 32142D–06/2013 ATUC64/128/256L3/4U 25.7.5 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - READY - TOFL 629 32142D–06/2013 ATUC64/128/256L3/4U 25.7.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - READY - TOFL 630 32142D–06/2013 ATUC64/128/256L3/4U 25.7.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - READY - TOFL 631 32142D–06/2013 ATUC64/128/256L3/4U 25.7.8 Status Register Name: SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 • BUSY: Interface Busy This bit is automatically cleared when the interface is no longer busy. This bit is set when the user interface is busy and will not respond to new write operations. • READY: Interface Ready This bit is cleared by writing a one to the corresponding bit in the SCR register. This bit is set when the BUSY bit has a 1-to-0 transition. • TOFL: Timebase Overflow This bit is cleared by writing a one to corresponding bit in the SCR register. This bit is set when the timebase counter has wrapped at its top value. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - BUSY READY - TOFL 632 32142D–06/2013 ATUC64/128/256L3/4U 25.7.9 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. This register always reads as zero. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 1 10 9 8 -------- 76543210 - - - - - READY - TOFL 633 32142D–06/2013 ATUC64/128/256L3/4U 25.7.10 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x24 Reset Value: - • CHANNELS: Channels Implemented This field contains the number of channels implemented on the device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 CHANNELS 634 32142D–06/2013 ATUC64/128/256L3/4U 25.7.11 Version Register Name: VERSION Access Type: Read-only Offset: 0x28 Reset Value: - • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 635 32142D–06/2013 ATUC64/128/256L3/4U 25.7.12 Top Value Register Name: TVR Access Type: Read/Write Offset: 0x2C Reset Value: 0x00000000 • TOP: Timebase Counter Top Value The top value for the timebase counter. The value written to the CR.TOP field will automatically be written to the 8 least significant bits of this field while the 4 most significant bits will be 0. When this register is written, it will also automatically update the CR.TOP field with the 8 least significant bits. The effective top value of the timebase counter is defined by both TVR.TOP and the CR.SPREAD. Refer to Section25.6.2 for more information. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - TOP[11:8] 76543210 TOP[7:0] 636 32142D–06/2013 ATUC64/128/256L3/4U 25.7.13 Interlinked Single Value Channel Set Name: ISCHSETm Access Type: Write-only Offset: 0x30+m*0x10 Reset Value: 0x00000000 • SET: Single Value Channel Set If the bit n in SET is one, the duty cycle of PWMA channel n will be updated with the value written to ISDUTY. If more than one ISCHSET register is present, ISCHSET0 controls channels 31 to 0 and ISCHSET1 controls channels 63 to 32. Note: The duty registers will be updated with the value stored in the ISDUTY register when any ISCHSETm register is written. Synchronization takes place immediately when an ISCHSET register is written. The duty cycle registers will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches. 31 30 29 28 27 26 25 24 SET 23 22 21 20 19 18 17 16 SET 15 14 13 12 11 10 9 8 SET 76543210 SET 637 32142D–06/2013 ATUC64/128/256L3/4U 25.7.14 Channel Event Response Register Name: CHERRm Access Type: Read/Write Offset: 0x34+m*0x10 Reset Value: 0x00000000 • CHER: Channel Event Response 0: The increase event will increase the duty cycle value by one in a PWM period for the corresponding channel and the decrease event will decrease the duty cycle value by one. 1: The increase event will decrease the duty cycle value by one in a PWM period for the corresponding channel and the decrease event will increase the duty cycle value by one. The events are taken into account when the common timebase counter reaches its top. If more than one CHERR register is present, CHERR0 controls channels 31-0 and CHERR1 controls channels 64-32 and so on. 31 30 29 28 27 26 25 24 CHER 23 22 21 20 19 18 17 16 CHER 15 14 13 12 11 10 9 8 CHER 76543210 CHER 638 32142D–06/2013 ATUC64/128/256L3/4U 25.7.15 Channel Event Enable Register Name: CHEERm Access Type: Read/Write Offset: 0x38+m*0x10 Reset Value: 0x00000000 • CHEE: Channel Event Enable 0: The input peripheral event for the corresponding channel is disabled. 1: The input peripheral event for the corresponding channel is enabled. Both increase and decrease events for channel n are enabled if bit n is one. If more than one CHEER register is present, CHEER0 controls channels 31-0 and CHEER1 controls channels 64-32 and so on. 31 30 29 28 27 26 25 24 CHEE 23 22 21 20 19 18 17 16 CHEE 15 14 13 12 11 10 9 8 CHEE 76543210 CHEE 639 32142D–06/2013 ATUC64/128/256L3/4U 25.7.16 Composite Waveform Generation Name: CWG Access Type: Read/Write Offset: 0x3C+k*0x10 Reset Value: 0x00000000 • XOR: Pair Waveform XOR’ed If the bit n in XOR field is one, the pair of PWMA output waveforms will be XORed before output. The even number output will be the XOR’ed output and the odd number output will be reverse of it. For example, if bit 0 in XOR is one, the pair of PWMA output waveforms for channel 0 and 1 will be XORed together. If bit n in XOR is zero, normal waveforms are output for that pair. Note that If more than one CWG register is present, CWG0 controls the first 32 pairs, corresponding to channels 63 downto 0, and CWG1 controls the second 32 pairs, corresponding to channels 127 downto 64. 31 30 29 28 27 26 25 24 XOR 23 22 21 20 19 18 17 16 XOR 15 14 13 12 11 10 9 8 XOR 76543210 XOR 640 32142D–06/2013 ATUC64/128/256L3/4U 25.7.17 Interlinked Multiple Value Duty0/1/2/3 Register Name: DUTY0/1/2/3 Access Type: Write-only Offset: 0x80-0x8C Reset Value: 0x00000000 These registers allows up to 4 channels to be updated with a common 12-bits duty cycle value at a time. They are the extension of the IMDUTY register which only supports updating the least significant 8 bits of the duty registers for up to 4 channels. • DUTY: Duty Cycle Value The duty cycle value written to this field will be updated to the channel specified by IMCHSEL. DUTY0 is specified by IMCHSEL.SEL0, DUTY1 is specified by IMCHSEL.SEL1, and so on. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - DUTY[11:8] 76543210 DUTY[7:0] 641 32142D–06/2013 ATUC64/128/256L3/4U 25.8 Module Configuration The specific configuration for each PWMA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 25-4. PWMA Configuration Feature PWMA Number of PWM channels 36 Channels supporting incoming peripheral events 0, 6, 8, 9, 11, 14, 19, and 20 PWMA channels with Open Drain mode 21, 27, and 28 Table 25-5. PWMA Clocks Clock Name Descripton CLK_PWMA Clock for the PWMA bus interface GCLK The generic clock used for the PWMA is GCLK3 Table 25-6. Register Reset Values Register Reset Value VERSION 0x00000201 PARAMETER 0x00000024 642 32142D–06/2013 ATUC64/128/256L3/4U 26. Timer/Counter (TC) Rev: 2.2.3.1.3 26.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse width modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Internal interrupt signal • Two global registers that act on all three TC channels • Peripheral event input on all A lines in capture mode 26.2 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC block has two global registers which act upon all three TC channels. The Block Control Register (BCR) allows the three channels to be started simultaneously with the same instruction. The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing them to be chained. 643 32142D–06/2013 ATUC64/128/256L3/4U 26.3 Block Diagram Figure 26-1. TC Block Diagram 26.4 I/O Lines Description 26.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 26.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first program the I/O Controller to assign the TC pins to their peripheral functions. I/O Controller TC2XC2S INT0 INT1 INT2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA1 Interrupt Controller CLK0 CLK1 CLK2 A0 B0 A1 B1 A2 B2 Timer Count er TIOB TIOA TIOB SYNC TIMER_CLOCK1 TIOA SYNC SYNC TIOA TIOB TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC1 XC0 XC0 XC2 XC1 XC0 XC1 XC2 Timer/Counter Channel 2 Timer/Counter Channel 1 Timer/Counter Channel 0 TC1XC1S TC0XC0S TIOA0 Table 26-1. I/O Lines Description Pin Name Description Type CLK0-CLK2 External Clock Input Input A0-A2 I/O Line A Input/Output B0-B2 I/O Line B Input/Output 644 32142D–06/2013 ATUC64/128/256L3/4U When using the TIOA lines as inputs the user must make sure that no peripheral events are generated on the line. Refer to the Peripheral Event System chapter for details. 26.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 26.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 26.5.4 Interrupts The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt requires the interrupt controller to be programmed first. 26.5.5 Peripheral Events The TC peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 26.5.6 Debug Operation The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 26.6 Functional Description 26.6.1 TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Figure 26-3 on page 659. 26.6.1.1 Channel I/O Signals As described in Figure 26-1 on page 643, each Channel has the following I/O signals. 26.6.1.2 16-bit counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set. Table 26-2. Channel I/O Signals Description Block/Channel Signal Name Description Channel Signal XC0, XC1, XC2 External Clock Inputs TIOA Capture mode: Timer Counter Input Waveform mode: Timer Counter Output TIOB Capture mode: Timer Counter Input Waveform mode: Timer Counter Input/Output INT Interrupt Signal Output SYNC Synchronization Input Signal 645 32142D–06/2013 ATUC64/128/256L3/4U The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 26.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 26-2 on page 645. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about the connection of these clock sources. • External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details about the connection of these clock sources. This selection is made by the Clock Selection field in the Channel n Mode Register (CMRn.TCCLKS). The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The Burst Signal Selection field in the CMRn register (CMRn.BURST) defines this signal. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC. Figure 26-2. Clock Selection TIMER_CLOCK5 XC2 TCCLKS CLKI BURST 1 Selected Clock XC1 XC0 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 646 32142D–06/2013 ATUC64/128/256L3/4U 26.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 26-3 on page 646. • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA). • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. In Capture mode the clock can be stopped by an RB load event if the Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop commands have effect only if the clock is enabled. Figure 26-3. Clock Control 26.6.1.5 TC operating modes Each channel can independently operate in two different modes: • Capture mode provides measurement on signals. • Waveform mode provides wave generation. The TC operating mode selection is done by writing to the Wave bit in the CCRn register (CCRn.WAVE). In Capture mode, TIOA and TIOB are configured as inputs. Q S R S R Q CLKSTA CLKEN CLKDIS Stop Event Disable Counter Clock Selected Clock Trigger Event 647 32142D–06/2013 ATUC64/128/256L3/4U In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 26.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). • SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing a one to the Synchro Command bit in the BCR register (BCR.SYNC). • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn (CMRn.CPCTRG) is written to one. The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG). If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 26.6.1.7 Peripheral events on TIOA inputs The TIOA input lines are ored internally with peripheral events from the Peripheral Event System. To capture using events the user must ensure that the corresponding pin functions for the TIOA line are disabled. When capturing on the external TIOA pin the user must ensure that no peripheral events are generated on this pin. 26.6.2 Capture Operating Mode This mode is entered by writing a zero to the CMRn.WAVE bit. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 26-4 on page 649 shows the configuration of the TC channel when programmed in Capture mode. 26.6.2.1 Capture registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. 648 32142D–06/2013 ATUC64/128/256L3/4U The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in SRn (SRn.LOVRS). In this case, the old value is overwritten. 26.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled. 649 32142D–06/2013 ATUC64/128/256L3/4U Figure 26-4. Capture Mode TIMER_CLOCK1 XC0 XC1 XC2 TCCLKS CLKI Q S R S R Q CLKSTA CLKEN CLKDIS BURST TIOB Capture Register A Compare RC = 16-bit Counter ABETRG SWTRG ETRGEDG CPCTRG IMR Trig LDRBS LDRAS ETRGS SR LOVRS COVFS SYNC 1 MTIOB TIOA MTIOA LDRA LDBSTOP If RA is not Loaded or RB is Loaded If RA is Loaded LDBDIS CPCS INT Edge Detector LDRB CLK OVF RESET Timer/Counter Channel Edge Detector Edge Detector Capture Register B Register C TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 650 32142D–06/2013 ATUC64/128/256L3/4U 26.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event. Figure 26-5 on page 651 shows the configuration of the TC channel when programmed in Waveform operating mode. 26.6.3.1 Waveform selection Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 651 32142D–06/2013 ATUC64/128/256L3/4U Figure 26-5. Waveform Mode TCCLKS CLKI Q S R S R Q CLKSTA CLKEN CLKDIS CPCDIS BURST TIOB Register A Compare RC = CPCSTOP 16-bit Counter EEVT EEVTEDG SYNC SWTRG ENETRG WAVSEL IMR Trig ACPC ACPA AEEVT ASWTRG BCPC BCPB BEEVT BSWTRG TIOA MTIOA TIOB MTIOB CPAS COVFS ETRGS SR CPCS CPBS CLK OVF RESET Output Contr oller O utput Cont r oller INT 1 Edge Detector Timer/Counter Channel TIMER_CLOCK1 XC0 XC1 XC2 WAVSEL Register B Register C Compare RB = Compare RA = TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 652 32142D–06/2013 ATUC64/128/256L3/4U 26.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 26-6 on page 652. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 26-7 on page 653. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 26-6. WAVSEL= 0 Without Trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Examples 653 32142D–06/2013 ATUC64/128/256L3/4U Figure 26-7. WAVSEL= 0 With Trigger 26.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 26-8 on page 654. It is important to note that CVn can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 26-9 on page 654. In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the counter clock (CMRn.CPCDIS = 1). Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Examples Counter cleared by trigger 654 32142D–06/2013 ATUC64/128/256L3/4U Figure 26-8. WAVSEL = 2 Without Trigger Figure 26-9. WAVSEL = 2 With Trigger 26.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 26-10 on page 655. Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples Counter cleared by trigger 655 32142D–06/2013 ATUC64/128/256L3/4U A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 26-11 on page 655. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 26-10. WAVSEL = 1 Without Trigger Figure 26-11. WAVSEL = 1 With Trigger Time Counter Value RC RB RA TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples Time Counter Value TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples Counter decremented by trigger RC RB RA Counter incremented by trigger 656 32142D–06/2013 ATUC64/128/256L3/4U 26.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 26-12 on page 656. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 26-13 on page 657. RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 26-12. WAVSEL = 3 Without Trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples 657 32142D–06/2013 ATUC64/128/256L3/4U Figure 26-13. WAVSEL = 3 With Trigger 26.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to zero, no external event is defined. If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by writing a one to the CMRn.ENETRG bit. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the CMRn.WAVSEL field. 26.6.3.7 Output controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: • software trigger • external event • RC compare RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the following fields in CMRn: • RC Compare Effect on TIOB (CMRn.BCPC) Time Counter Value TIOB TIOA Counter decremented by compare match with RC 0xFFFF Waveform Examples RC RB RA Counter decremented by trigger Counter incremented by trigger 658 32142D–06/2013 ATUC64/128/256L3/4U • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.ACPA) 659 32142D–06/2013 ATUC64/128/256L3/4U 26.7 User Interface Table 26-3. TC Register Memory Map Offset Register Register Name Access Reset 0x00 Channel 0 Control Register CCR0 Write-only 0x00000000 0x04 Channel 0 Mode Register CMR0 Read/Write 0x00000000 0x10 Channel 0 Counter Value CV0 Read-only 0x00000000 0x14 Channel 0 Register A RA0 Read/Write(1) 0x00000000 0x18 Channel 0 Register B RB0 Read/Write(1) 0x00000000 0x1C Channel 0 Register C RC0 Read/Write 0x00000000 0x20 Channel 0 Status Register SR0 Read-only 0x00000000 0x24 Interrupt Enable Register IER0 Write-only 0x00000000 0x28 Channel 0 Interrupt Disable Register IDR0 Write-only 0x00000000 0x2C Channel 0 Interrupt Mask Register IMR0 Read-only 0x00000000 0x40 Channel 1 Control Register CCR1 Write-only 0x00000000 0x44 Channel 1 Mode Register CMR1 Read/Write 0x00000000 0x50 Channel 1 Counter Value CV1 Read-only 0x00000000 0x54 Channel 1 Register A RA1 Read/Write(1) 0x00000000 0x58 Channel 1 Register B RB1 Read/Write(1) 0x00000000 0x5C Channel 1 Register C RC1 Read/Write 0x00000000 0x60 Channel 1 Status Register SR1 Read-only 0x00000000 0x64 Channel 1 Interrupt Enable Register IER1 Write-only 0x00000000 0x68 Channel 1 Interrupt Disable Register IDR1 Write-only 0x00000000 0x6C Channel 1 Interrupt Mask Register IMR1 Read-only 0x00000000 0x80 Channel 2 Control Register CCR2 Write-only 0x00000000 0x84 Channel 2 Mode Register CMR2 Read/Write 0x00000000 0x90 Channel 2 Counter Value CV2 Read-only 0x00000000 0x94 Channel 2 Register A RA2 Read/Write(1) 0x00000000 0x98 Channel 2 Register B RB2 Read/Write(1) 0x00000000 0x9C Channel 2 Register C RC2 Read/Write 0x00000000 0xA0 Channel 2 Status Register SR2 Read-only 0x00000000 0xA4 Channel 2 Interrupt Enable Register IER2 Write-only 0x00000000 0xA8 Channel 2 Interrupt Disable Register IDR2 Write-only 0x00000000 0xAC Channel 2 Interrupt Mask Register IMR2 Read-only 0x00000000 0xC0 Block Control Register BCR Write-only 0x00000000 0xC4 Block Mode Register BMR Read/Write 0x00000000 0xF8 Features Register FEATURES Read-only -(2) 0xFC Version Register VERSION Read-only -(2) 660 32142D–06/2013 ATUC64/128/256L3/4U Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 661 32142D–06/2013 ATUC64/128/256L3/4U 26.7.1 Channel Control Register Name: CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started. 0: Writing a zero to this bit has no effect. • CLKDIS: Counter Clock Disable Command 1: Writing a one to this bit will disable the clock. 0: Writing a zero to this bit has no effect. • CLKEN: Counter Clock Enable Command 1: Writing a one to this bit will enable the clock if CLKDIS is not one. 0: Writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - SWTRG CLKDIS CLKEN 662 32142D–06/2013 ATUC64/128/256L3/4U 26.7.2 Channel Mode Register: Capture Mode Name: CMR Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 • LDRB: RB Loading Selection • LDRA: RA Loading Selection • WAVE 1: Capture mode is disabled (Waveform mode is enabled). 0: Capture mode is enabled. • CPCTRG: RC Compare Trigger Enable 1: RC Compare resets the counter and starts the counter clock. 0: RC Compare has no effect on the counter and its clock. • ABETRG: TIOA or TIOB External Trigger Selection 1: TIOA is used as an external trigger. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG - - - ABETRG ETRGEDG 76543210 LDBDIS LDBSTOP BURST CLKI TCCLKS LDRB Edge 0 none 1 rising edge of TIOA 2 falling edge of TIOA 3 each edge of TIOA LDRA Edge 0 none 1 rising edge of TIOA 2 falling edge of TIOA 3 each edge of TIOA 663 32142D–06/2013 ATUC64/128/256L3/4U 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs. • BURST: Burst Signal Selection • CLKI: Clock Invert 1: The counter is incremented on falling edge of the clock. 0: The counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge BURST Burst Signal Selection 0 The clock is not gated by an external signal 1 XC0 is ANDed with the selected clock 2 XC1 is ANDed with the selected clock 3 XC2 is ANDed with the selected clock TCCLKS Clock Selected 0 TIMER_CLOCK1 1 TIMER_CLOCK2 2 TIMER_CLOCK3 3 TIMER_CLOCK4 4 TIMER_CLOCK5 5 XC0 6 XC1 7 XC2 664 32142D–06/2013 ATUC64/128/256L3/4U 26.7.3 Channel Mode Register: Waveform Mode Name: CMR Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 • BSWTRG: Software Trigger Effect on TIOB • BEEVT: External Event Effect on TIOB 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE WAVSEL ENETRG EEVT EEVTEDG 76543210 CPCDIS CPCSTOP BURST CLKI TCCLKS BSWTRG Effect 0 none 1 set 2 clear 3 toggle BEEVT Effect 0 none 1 set 2 clear 3 toggle 665 32142D–06/2013 ATUC64/128/256L3/4U • BCPC: RC Compare Effect on TIOB • BCPB: RB Compare Effect on TIOB • ASWTRG: Software Trigger Effect on TIOA • AEEVT: External Event Effect on TIOA • ACPC: RC Compare Effect on TIOA BCPC Effect 0 none 1 set 2 clear 3 toggle BCPB Effect 0 none 1 set 2 clear 3 toggle ASWTRG Effect 0 none 1 set 2 clear 3 toggle AEEVT Effect 0 none 1 set 2 clear 3 toggle ACPC Effect 0 none 1 set 2 clear 3 toggle 666 32142D–06/2013 ATUC64/128/256L3/4U • ACPA: RA Compare Effect on TIOA • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled). • WAVSEL: Waveform Selection • ENETRG: External Event Trigger Enable 1: The external event resets the counter and starts the counter clock. 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. • EEVT: External Event Selection Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • EEVTEDG: External Event Edge Selection • CPCDIS: Counter Clock Disable with RC Compare 1: Counter clock is disabled when counter reaches RC. 0: Counter clock is not disabled when counter reaches RC. ACPA Effect 0 none 1 set 2 clear 3 toggle WAVSEL Effect 0 UP mode without automatic trigger on RC Compare 1 UPDOWN mode without automatic trigger on RC Compare 2 UP mode with automatic trigger on RC Compare 3 UPDOWN mode with automatic trigger on RC Compare EEVT Signal selected as external event TIOB Direction 0 TIOB input(1) 1 XC0 output 2 XC1 output 3 XC2 output EEVTEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge 667 32142D–06/2013 ATUC64/128/256L3/4U • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock. 0: Counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. TCCLKS Clock Selected 0 TIMER_CLOCK1 1 TIMER_CLOCK2 2 TIMER_CLOCK3 3 TIMER_CLOCK4 4 TIMER_CLOCK5 5 XC0 6 XC1 7 XC2 668 32142D–06/2013 ATUC64/128/256L3/4U 26.7.4 Channel Counter Value Register Name: CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 • CV: Counter Value CV contains the counter value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 CV[15:8] 76543210 CV[7:0] 669 32142D–06/2013 ATUC64/128/256L3/4U 26.7.5 Channel Register A Name: RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 • RA: Register A RA contains the Register A value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 RA[15:8] 76543210 RA[7:0] 670 32142D–06/2013 ATUC64/128/256L3/4U 26.7.6 Channel Register B Name: RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 • RB: Register B RB contains the Register B value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 RB[15:8] 76543210 RB[7:0] 671 32142D–06/2013 ATUC64/128/256L3/4U 26.7.7 Channel Register C Name: RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 • RC: Register C RC contains the Register C value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 RC[15:8] 76543210 RC[7:0] 672 32142D–06/2013 ATUC64/128/256L3/4U 26.7.8 Channel Status Register Name: SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts. • MTIOB: TIOB Mirror 1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven high. 0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven low. • MTIOA: TIOA Mirror 1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven high. 0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven low. • CLKSTA: Clock Enabling Status 1: This bit is set when the clock is enabled. 0: This bit is cleared when the clock is disabled. • ETRGS: External Trigger Status 1: This bit is set when an external trigger has occurred. 0: This bit is cleared when the SR register is read. • LDRBS: RB Loading Status 1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • LDRAS: RA Loading Status 1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • CPCS: RC Compare Status 1: This bit is set when an RC Compare has occurred. 0: This bit is cleared when the SR register is read. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 -------- 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 673 32142D–06/2013 ATUC64/128/256L3/4U • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • COVFS: Counter Overflow Status 1: This bit is set when a counter overflow has occurred. 0: This bit is cleared when the SR register is read. 674 32142D–06/2013 ATUC64/128/256L3/4U 26.7.9 Channel Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 675 32142D–06/2013 ATUC64/128/256L3/4U 26.7.10 Channel Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 676 32142D–06/2013 ATUC64/128/256L3/4U 26.7.11 Channel Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 677 32142D–06/2013 ATUC64/128/256L3/4U 26.7.12 Block Control Register Name: BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0: Writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - - - SYNC 678 32142D–06/2013 ATUC64/128/256L3/4U 26.7.13 Block Mode Register Name: BMR Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 • TC2XC2S: External Clock Signal 2 Selection • TC1XC1S: External Clock Signal 1 Selection 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - TC2XC2S TC1XC1S TC0XC0S TC2XC2S Signal Connected to XC2 0 TCLK2 1 none 2 TIOA0 3 TIOA1 TC1XC1S Signal Connected to XC1 0 TCLK1 1 none 2 TIOA0 3 TIOA2 679 32142D–06/2013 ATUC64/128/256L3/4U • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 680 32142D–06/2013 ATUC64/128/256L3/4U 26.7.14 Features Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented. 0: Up/down counter capability is not implemented. • CTRSIZE: Counter size This field indicates the size of the counter in bits. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ------- 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 76543210 CTRSIZE 681 32142D–06/2013 ATUC64/128/256L3/4U 26.7.15 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 682 32142D–06/2013 ATUC64/128/256L3/4U 26.8 Module Configuration The specific configuration for each Timer/Counter instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. 26.8.1 Clock Connections There are two Timer/Counter modules, TC0 and TC1, with three channels each, giving a total of six Timer/Counter channels. Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 26-4. TC Bus Interface Clocks Module name Clock Name Description TC0 CLK_TC0 Clock for the TC0 bus interface TC1 CLK_TC1 Clock for the TC1 bus interface Table 26-5. Timer/Counter Clock Connections Module Source Name Connection TC0 Internal TIMER_CLOCK1 32 KHz oscillator clock (CLK_32K) TIMER_CLOCK2 PBA Clock / 2 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 32 TIMER_CLOCK5 PBA Clock / 128 External XC0 See Section on page 10 XC1 XC2 TC1 Internal TIMER_CLOCK1 32 KHz oscillator clock (CLK_32K) TIMER_CLOCK2 PBA Clock / 2 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 32 TIMER_CLOCK5 PBA Clock / 128 External XC0 See Section on page 10 XC1 XC2 683 32142D–06/2013 ATUC64/128/256L3/4U 27. Peripheral Event System Rev: 1.0.0.1 27.1 Features • Direct peripheral to peripheral communication system • Allows peripherals to receive, react to, and send peripheral events without CPU intervention • Cycle deterministic event communication • Asynchronous interrupts allow advanced peripheral operation in low power sleep modes 27.2 Overview Several peripheral modules can be configured to emit or respond to signals known as peripheral events. The exact condition to trigger a peripheral event, or the action taken upon receiving a peripheral event, is specific to each module. Peripherals that respond to peripheral events are called peripheral event users and peripherals that emit peripheral events are called peripheral event generators. A single module can be both a peripheral event generator and user. The peripheral event generators and users are interconnected by a network known as the Peripheral Event System. This allows low latency peripheral-to-peripheral signaling without CPU intervention, and without consuming system resources such as bus or RAM bandwidth. This offloads the CPU and system resources compared to a traditional interrupt-based software driven system. 27.3 Peripheral Event System Block Diagram Figure 27-1. Peripheral Event System Block Diagram 27.4 Functional Description 27.4.1 Configuration The Peripheral Event System in the ATUC64/128/256L3/4U has a fixed mapping of peripheral events between generators and users, as described in Table 27-1 to Table 27-4. Thus, the user does not need to configure the interconnection between the modules, although each peripheral event can be enabled or disabled at the generator or user side as described in the peripheral chapter for each module. Peripheral Event System Generator Generator User Generator/ User 684 32142D–06/2013 ATUC64/128/256L3/4U Table 27-1. Peripheral Event Mapping from ACIFB to PWMA Generator Generated Event User Effect Asynchronous ACIFB channel 0 AC0 VINP > AC0 VINN PWMA channel 0 PWMA duty cycle value increased by one No AC0 VINN > AC0 VINP PWMA duty cycle value decreased by one ACIFB channel 1 AC1 VINP > AC1 VINN PWMA channel 6 PWMA duty cycle value increased by one AC1 VINN > AC1 VINP PWMA duty cycle value decreased by one ACIFB channel 2 AC2 VINP > AC2 VINN PWMA channel 8 PWMA duty cycle value increased by one AC2 VINN > AC2 VINP PWMA duty cycle value decreased by one ACIFB channel 3 AC3 VINP > AC3 VINN PWMA channel 9 PWMA duty cycle value increased by one AC3 VINN > AC3 VINP PWMA duty cycle value decreased by one ACIFB channel 4 AC4 VINP > AC4 VINN PWMA channel 11 PWMA duty cycle value increased by one AC4 VINN > AC4 VINP PWMA duty cycle value decreased by one ACIFB channel 5 AC5 VINP > AC5 VINN PWMA channel 14 PWMA duty cycle value increased by one AC5 VINN > AC5 VINP PWMA duty cycle value decreased by one ACIFB channel 6 AC6 VINP > AC6 VINN PWMA channel 19 PWMA duty cycle value increased by one AC6 VINN > AC6 VINP PWMA duty cycle value decreased by one ACIFB channel 7 AC7 VINP > AC7 VINN PWMA channel 20 PWMA duty cycle value increased by one AC7 VINN > AC7 VINP PWMA duty cycle value decreased by one ACIFB channel n ACn VINN > ACn VINP CAT Automatically used by the CAT when performing QMatrix acquisition. No Table 27-2. Peripheral Event Mapping from GPIO to TC Generator Generated Event User Effect Asynchronous GPIO Pin change on PA00-PA07 TC0 A0 capture No Pin change on PA08-PA15 A1 capture Pin change on PA16-PA23 A2 capture Pin change on PB00-PB07 TC1 A1 capture Pin change on PB08-PB15 A2 capture 685 32142D–06/2013 ATUC64/128/256L3/4U 27.4.2 Peripheral Event Connections Each generated peripheral event is connected to one or more users. If a peripheral event is connected to multiple users, the peripheral event can trigger actions in multiple modules. A peripheral event user can likewise be connected to one or more peripheral event generators. If a peripheral event user is connected to multiple generators, the peripheral events are OR’ed together to a single peripheral event. This means that peripheral events from either one of the generators will result in a peripheral event to the user. To configure a peripheral event, the peripheral event must be enabled at both the generator and user side. Even if a generator is connected to multiple users, only the users with the peripheral event enabled will trigger on the peripheral event. 27.4.3 Low Power Operation As the peripheral events do not require CPU intervention, they are available in Idle mode. They are also available in deeper sleep modes if both the generator and user remain clocked in that mode. Certain events are known as asynchronous peripheral events, as identified in Table 27-1 to Table 27-4. These can be issued even when the system clock is stopped, and revive unclocked user peripherals. The clock will be restarted for this module only, without waking the system from sleep mode. The clock remains active only as long as required by the triggered function, before being switched off again, and the system remains in the original sleep mode. The CPU and sysTable 27-3. Peripheral Event Mapping from AST Generator Generated Event User Effect Asynchronous AST Overflow event ACIFB Comparison is triggered if the ACIFB.CONFn register is written to 11 (Event Triggered Single Measurement Mode) and the EVENTEN bit in the ACIFB.CTRL register is written to 1. Yes Periodic event Alarm event Overflow event ADCIFB Conversion is triggered if the TRGMOD bit in the ADCIFB.TRGR register is written to 111 (Peripheral Event Trigger). Periodic event Alarm event Overflow event CAT Trigger one iteration of autonomous touch detection. Periodic event Alarm event Table 27-4. Peripheral Event Mapping from PWMA Generator Generated Event User Effect Asynchronous PWMA channel 0 Timebase counter reaches the duty cycle value. ACIFB Comparison is triggered if the ACIFB.CONFn register is written to 11 (Event Triggered Single Measurement Mode) and the EVENTEN bit in the ACIFB.CTRL register is written to 1. No ADCIFB Conversion is triggered if the TRGMOD bit in the ADCIFB.TRGR register is written to 111 (Peripheral Event Trigger). 686 32142D–06/2013 ATUC64/128/256L3/4U tem will only be woken up if the user peripheral generates an interrupt as a result of the operation. This concept is known as SleepWalking and is described in further detail in the Power Manager chapter. Note that asynchronous peripheral events may be associated with a delay due to the need to restart the system clock source if this has been stopped in the sleep mode. 27.5 Application Example This application example shows how the Peripheral Event System can be used to program the ADC Interface to perform ADC conversions at selected intervals. Conversions of the active analog channels are started with a software or a hardware trigger. One of the possible hardware triggers is a peripheral event trigger, allowing the Peripheral Event System to synchronize conversion with some configured peripheral event source. From Table 27-3 and Table 27-4, it can be read that this peripheral event source can be either an AST peripheral event, or an event from the PWM Controller. The AST can generate periodic peripheral events at selected intervals, among other types of peripheral events. The Peripheral Event System can then be used to set up the ADC Interface to sample an analog signal at regular intervals. The user must enable peripheral events in the AST and in the ADC Interface to accomplish this. The periodic peripheral event in the AST is enabled by writing a one to the corresponding bit in the AST Event Enable Register (EVE). To select the peripheral event trigger for the ADC Interface, the user must write the value 0x7 to the Trigger Mode (TRGMOD) field in the ADC Interface Trigger Register (TRGR). When the peripheral events are enabled, the AST will generate peripheral events at the selected intervals, and the Peripheral Event System will route the peripheral events to the ADC Interface, which will perform ADC conversions at the selected intervals. Figure 27-2. Application Example Since the AST peripheral event is asynchronous, the description above will also work in sleep modes where the ADC clock is stopped. In this case, the ADC clock (and clock source, if needed) will be restarted during the ADC conversion. After the conversion, the ADC clock and clock source will return to the sleep state, unless the ADC generates an interrupt, which in turn will wake up the system. Using asynchronous interrupts thus allows ADC operation in much lower power states than would otherwise be possible. Peripheral Event System AST ADC Interface Trigger conversion Periodic peripheral event 687 32142D–06/2013 ATUC64/128/256L3/4U 28. Audio Bit Stream DAC (ABDACB) Rev.: 1.0.0.0 28.1 Features • 16 bit digital stereo DAC • Oversampling D/A conversion architecture – Adjustable oversampling ratio – 3rd order Sigma-Delta D/A converters • Digital bitstream output • Parallel interface • Connects to DMA for background transfer without CPU intervention • Supported sampling frequencies – 8000Hz, 11025Hz, 12000Hz, 16000Hz, 22050Hz, 24000Hz, 32000Hz, 44100Hz, and 48000Hz • Supported data formats – 32-, 24-, 20-, 18-, 16-, and 8-bit stereo format – 16- and 8-bit compact stereo format, with left and right sample packed in the same word to reduce data transfers • Common mode offset control • Volume control 28.2 Overview The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with an average value proportional to the sample value. Two channels are supported making the Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of complementary digital outputs, DAC and DACN, which can be connected to an external high input impedance amplifier. The Audio Bitstream DAC is made up of several signal processing blocks and a 3rd order Sigma Delta D/A converter for each channel. The Sigma Delta modulator converts the parallel data to a bitstream, while the signal processing blocks perform volume control, offset control, upsampling, and filtering to compensate for the upsampling process. The upsampling is performed by a Cascaded Integrator-Comb (CIC) filter, and the compensation filter is a Finite Impulse Response (FIR) CIC compensation filter. 28.3 Block Diagram Figure 28-1. ABDACB Block Diagram User Inter af ce Synchronizer Volume control Offset control CIC Compensation filter (FIR) CIC Comb Section CIC Integrator section Clock divider Sigma Delta Modulator Sigma Delta Modulator clk_abdacb gclk Signal processing (before up-sampling) CLK DAC[0] DACN[0] DAC[1] DACN[1] PB 688 32142D–06/2013 ATUC64/128/256L3/4U 28.4 I/O Lines Description 28.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 28.5.1 I/O lines The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed with I/O Controller lines. Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode. 28.5.2 Clocks The clock for the ABDACB bus interface (CLK_ABDACB) is generated by the Power Manager. This clock is turned on by default, and can be enabled and disabled in the Power Manager. It is recommended to disable the ABDACB before disabling the clock, to avoid freezing the ABDACB in an undefined state. Before using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is enabled in the Power Manager. The Audio Bitstream DAC requires a separate clock for the D/A conversion. This clock is provided by a generic clock which has to be set up in the System Control Interface (SCIF). The frequency for this clock has to be set as described in Table 28-3 on page 697. It is important that this clock is accurate and has low jitter. Incorrect frequency will result in too fast or too slow playback (frequency shift), and too high jitter will add noise to the D/A conversion. For best performance one should trade frequency accuracy (within some limits) for low jitter to obtain the best performance as jitter will have large impact on the quality of the converted signal. 28.5.3 DMA The ABDACB is connected to the Peripheral DMA controller. Using DMA to transfer data samples requires the Peripheral DMA controller to be programmed before enabling the ABDACB. 28.5.4 Interrupts The ABDACB interrupt request line is connected to the interrupt controller. Using the ABDACB interrupt requires the interrupt controller to be programmed first. Table 28-1. I/O Lines Description Pin Name Pin Description Type DAC[0] Output for channel 0 Output DACN[0] Inverted output for channel 0 Output DAC[1] Output for channel 1 Output DACN[1] Inverted output for channel 1 Output CLK Clock output for DAC Output 689 32142D–06/2013 ATUC64/128/256L3/4U 28.6 Functional Description 28.6.1 Construction The Audio Bitstream DAC is divided into several parts, the user interface, the signal processing blocks, and the Sigma Delta modulator blocks. See Figure 28-1 on page 687. The user interface is used to configure the signal processing blocks and to input new data samples to the converter.The signal processing blocks manages volume control, offset control, and upsampling. The Sigma Delta blocks converts the parallel data to1-bit bitstreams. 28.6.1.1 CIC Interpolation Filter The interpolation filter in the system is a Cascaded Integrator-Comb (CIC) interpolation filter which interpolates from Fs to {125, 128, 136}xFs depending on the control settings. This filter is a 4th order CIC filter, and the basic building blocks of the filter is a comb part and an integrator part. Since the CIC interpolator has a sinc-function frequency response it is compensated by a linear phase CIC compensation filter to make the passband response more flat in the range 0- 20kHz, see figure Figure 28-4 on page 693. The frequency response of this type of interpolator has the first zero at the input sampling frequency. This means that the first repeated specters created by the upsampling process will not be fully rejected and the output signal will contain signals from these repeated specters. See Figure 28-6 on page 694. Since the human ear can not hear frequencies above 20kHz, we should not be affected by this when the sample rate is above 40kHz, but digital measurement equipment will be affected. This need to be accounted for when doing measurements on the system to prevent aliasing and incorrect measurement results. 28.6.1.2 Sigma Delta Modulator The Sigma Delta modulator is a 3rd order modulator consisting of three differentiators (delta blocks), three integrators (sigma blocks), and a one bit quantizer. The purpose of the integrators is to shape the noise, so that the noise is reduced in the audio passband and increased at the higher frequencies, where it can be filtered out by an analog low-pass filter. To be able to filter out all the noise at high frequencies the analog low-pass filter must be one order larger than the Sigma Delta modulator. 28.6.1.3 Recreating the Analog Signal Since the DAC and DACN outputs from the ABDAC are digital square wave signals, they have to be passed through a low pass filter to recreate the analog signal. This also means that noise on the IO voltage will couple through to the analog signal. To remove some of the IO noise the ABDAC can output a clock signal, CLK, which can be used to resample the DAC and DACN signals on external Flip-Flops powered by a clean supply. 28.6.2 Initialization Before enabling the ABDACB the correct configuration must be applied to the Control Register (CR). Configuring the Alternative Upsampling Ratio bit (CR.ALTUPR), Common Mode Offset Control bit (CR.CMOC), and the Sampling Frequency field (CR.FS) according to the sampling rate of the data that is converted and the type of amplifier the outputs are connected to is required to get the correct behavior of the system. When the correct configuration is applied the ABDACB can be enabled by writing a one to the Enable bit in the Control Register (CR.EN). The module is disabled by writing a zero to the Enable bit. The module should be disabled before entering sleep modes to ensure that the outputs are not left in an undesired state. 690 32142D–06/2013 ATUC64/128/256L3/4U 28.6.3 Basic operation To convert audio data to a digital bitstream the user must first initialize the ABDACB as described in Section 28.6.2. When the ABDACB is initialized and enabled it will indicate that it is ready to receive new data by setting the Transmit Ready bit in the Status Register (SR.TXRDY). When the TXRDY bit is set in the Status Register the user has to write new samples to Sample Data Register 0 (SDR0) and Sample Data Register 1 (SDR1). If the Mono Mode (MONO) bit in the Control Register (CR) is set, or one of the compact stereo formats are used by configuring the Data Word Format (DATAFORMAT) in the Control Register, only SDR0 has to be written. Failing to write to the sample data registers will result in an underrun indicated by the Transmit Underrun (TXUR) bit in the Status Register (SR.TXUR). When new samples are written to the sample data registers the TXRDY bit will be cleared. To increase performance of the system an interrupt handler or DMA transfer can be used to write new samples to the sample data registers. See Section 28.6.10 for details on DMA, and Section 28.6.11 for details on interrupt. 28.6.4 Data Format The input data type is two’s complement. The Audio Bitstream DAC can be configured to accept different audio formats. The format must be configured in the Data Word Format field in the Control Register. In regular operation data for the two channels are written to the sample data registers SDR0 and SDR1. If the data format field specifies a format using less than 32 bits, data must be written right-justified in SDR0 and SDR1. Sign extension into the unused bits is not necessary. Only the 16 most significant bits in the data will be used by the ABDACB. For data formats larger than 16 bits the least significant bits are ignored. For 8-bit data formats the 8 bits will be used as the most significant bits in the 16-bit samples, the additional bits will be zeros. The ABDACB also supports compact data formats for 16- and 8-bit samples. For 16-bit samples the sample for channel 0 must be written to bits 15 through 0 and the sample for channel 1 must be written to bits 31 through 16 in SDR0. For 8-bit samples the sample for channel 0 must be written to bits 7 through 0 and the sample for channel 1 must be written to bits 15 through 8 in SDR0. SDR1 is not used in this mode. See Table 28-5 on page 699. 28.6.5 Data Swapping When the Swap Channels (SWAP) bit in the Control Register (CR.SWAP) is one, writing to the Sample Data Register 0 (SDR0) will put the data in Sample Data Register 1 (SDR1). Writing SDR1 will put the data in SDR0. If one of the two compact stereo formats is used the lower and upper halfword of SDR0 will be swapped when writing to SDR0. 28.6.6 Common Mode Offset Control When the Common Mode Offset Control (CMOC) bit in the Control Register is one the input data will get a DC value applied to it and the amplitude will be scaled. This will make the common mode offset of the two corresponding outputs, DAC and DACN, to move away from each other so that the output signals are not overlapping. The result is that the two signals can be applied to a differential analog filter, and the difference will always be a positive value, removing the need for a negative voltage supply for the filter. The cost of doing this a 3dB loss in dynamic range. On the left side of Figure 28-2 one can see the filtered output from the DAC and DACN pins when a sine wave is played when CR.CMOC is zero. The waveform on the right side shows the output of the differential filter when the two outputs on the left side are used as inputs to the differential filter. Figure 28-3 show the corresponding outputs when CR.CMOC is one. 691 32142D–06/2013 ATUC64/128/256L3/4U Figure 28-2. Output signals with CMOC=0 Figure 28-3. Output signals with CMOC=1 28.6.7 Volume Control The Audio Bitstream DAC have two volume control registers, Volume Control Register 0 (VCR0) and Volume Control Register 1 (VCR1), that can be used to adjust the volume for the corresponding channel. The volume control is linear and will only scale each sample according to the value in the Volume Control (VOLUME) field in the volume control registers. The register also has a Mute bit (MUTE) which can be used to mute the corresponding channel. The filtered out- 692 32142D–06/2013 ATUC64/128/256L3/4U put of the DAC pins will have a voltage given by the following equation, given that it is configured to run at the default upsampling ratio of 128: If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN outputs or invert the sign of the input data by software. 28.6.8 Mono When the Mono bit (MONO) in the Control Register is set, data written to SDR0 will be used for both output channels. If one of the compact stereo formats are used only the data written to the part of SDR0 that corresponds with channel 0 is used. 28.6.9 Alternative Upsampling Ratio The digital filters and Sigma Delta modulators requires its own clock to perform the conversion at the correct speed, and this clock is provided by a generic clock in the SCIF. The frequency of this clock depends on the input sample rate and the upsampling ratio which is controlled by the Alternative Upsampling Ratio bit (ALTUPR) in the Control Register. The ABDACB supports three upsampling ratios, 125, 128, and 136. The default setting is a ratio of 128, and is used when CR.ALTUPR is zero. Using this ratio gives a clock frequency requirement that is common for audio products. In some cases one may want to use other clock frequencies that already are available in the system. By writing a one to CR.ALTUPR a upsampling ratio of 125 or 136 is used depending on the configuration of the Sampling Frequency field in the Control Register. Refer to Table 28-3 for required clock frequency and settings. The required clock frequency of the generic clock can be calculated from the following equation: R is the upsampling ratio of the converter. If CR.ALTUPR is zero the upsampling ratio is 128. If CR.ALTUPR is one, R will change to 125 when CR.FS is configured for 8kHz, 12kHz, 16kHz, 24kHz, 32kHz, and 48kHz. For the other configurations of CR.FS, 11.025kHz, 22.050kHz, and 44.100kHz, it will change to 136. 28.6.10 DMA operation The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA Controller can be programmed to automatically transfer samples to the Sample Data Registers (SDR0 and SDR1) when the Audio Bitstream DAC is ready for new samples. Two DMA channels are used, one for each sample data register. If the Mono Mode bit in the Control Register (CR.MONO) is one, or one of the compact stereo formats is used, only the DMA channel connected to SDR0 will be used. When using DMA only the Control Register needs to be written in the Audio Bitstream DAC. This enables the Audio Bitstream DAC to operate without any CPU intervention such as polling the Status Register (SR) or using interrupts. See the Peripheral DMA Controller documentation for details on how to setup Peripheral DMA transfers. 28.6.11 Interrupts The ABDACB requires new data samples at a rate of FS. The interrupt status bits are used to indicate when the system is ready to receive new samples. The Transmit Ready Interrupt Status bit in the Status Register (SR.TXRDY) will be set whenever the ABDACB is ready to receive a new sample. A new sample value must be written to the sample data registers (SDR0 and VOUT 1 2 -- 33 128 – --------- SDR 215 ------------ VOLUME 215 – 1   ------------------------     VVDDIO =  GCLK[Hz] F = S   R 8 693 32142D–06/2013 ATUC64/128/256L3/4U SDR1) before 1/FS second, or an underrun will occur, as indicated by the Underrun Interrupt bit in SR (SR.TXUR). The interrupt bits in SR are cleared by writing a one to the corresponding bit in the Status Clear Register (SCR). 28.6.12 Frequency Response Figure Figure 28-4 to Figure 28-7 show the frequency response for the system. The sampling frequency used is 48kHz, but the response will be the same for other sampling frequencies, always having the first zero at FS. Figure 28-4. Passband Frequency Response 694 32142D–06/2013 ATUC64/128/256L3/4U Figure 28-5. Frequency Response up to Sampling Frequency Figure 28-6. Frequency Response up to 3x Sampling Frequency 695 32142D–06/2013 ATUC64/128/256L3/4U Figure 28-7. Frequency Response up to 128x Sampling Frequency 696 32142D–06/2013 ATUC64/128/256L3/4U 28.7 User Interface Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 28-2. ABDACB Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Read/Write 0x00000000 0x04 Sample Data Register 0 SDR0 Read/Write 0x00000000 0x08 Sample Data Register 1 SDR1 Read/Write 0x00000000 0x0C Volume Control Register 0 VCR0 Read/Write 0x00000000 0x10 Volume Control Register 1 VCR1 Read/Write 0x00000000 0x14 Interrupt Enable Register IER Write-only 0x00000000 0x18 Interrupt Disable Register IDR Write-only 0x00000000 0x1C Interrupt Mask Register IMR Read-only 0x00000000 0x20 Status Register SR Read-only 0x00000000 0x24 Status Clear Register SCR Write-only 0x00000000 0x28 Parameter Register PARAMETER Read-only - (1) 0x2C Version Register VERSION Read-only - (1) 697 32142D–06/2013 ATUC64/128/256L3/4U 28.7.1 Control Register Name: CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • FS: Sampling Frequency Must be set to the matching data sampling frequency, see Table 28-3. Note: 1. The actual clock requirement are 11.9952MHz, 23.9904MHz, and 47.9808MHz, but this is very close to the suggested clock frequencies, and will only result in a very small frequency shift. This need to be accounted for during testing if comparing to a reference signal. Notes: 1. 31 30 29 28 27 26 25 24 - - - - FS 23 22 21 20 19 18 17 16 - - - - - DATAFORMAT 15 14 13 12 11 10 9 8 -------- 76543210 SWRST - MONO CMOC ALTUPR - SWAP EN Table 28-3. Generic Clock Requirements CR.FS Description GCLK (CR.ALTUPR=1) GCLK (CR.ALTUPR=0) 0 8000Hz sampling frequency 8.0MHz 8.1920MHz 1 11025Hz sampling frequency 12.0MHz(1) 11.2896MHz 2 12000Hz sampling frequency 12.0MHz 12.2880MHz 3 16000Hz sampling frequency 16.0MHz 16.3840MHz 4 22050Hz sampling frequency 24.0MHz(1) 22.5792MHz 5 24000Hz sampling frequency 24.0MHz 24.5760MHz 6 32000Hz sampling frequency 32.0MHz 32.7680MHz 7 44100Hz sampling frequency 48.0MHz(1) 45.1584MHz 8 48000Hz sampling frequency 48.0MHz 49.1520MHz Other Reserved - - 698 32142D–06/2013 ATUC64/128/256L3/4U • DATAFORMAT: Data Word Format • SWRST: Software Reset Writing a zero to this bit does not have any effect. Writing a one to this bit will reset the ABDACB as if a hardware reset was done. • MONO: Mono Mode 0: Mono mode is disabled. 1: Mono mode is enabled. • CMOC: Common Mode Offset Control 0: Common mode adjustment is disabled. 1: Common mode adjustment is enabled. • ALTUPR: Alternative Upsampling Ratio 0: Alternative upsampling is disabled. 1: Alternative upsampling is enabled. • SWAP: Swap Channels 0: Channel swap is disabled. 1: Channel swap is enabled. • EN: Enable 0: The ABDACB is disabled. 1: The ABDACB is enabled. Table 28-4. Data Word Format DATAFORMAT Word length Comment 0 32 bits 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo Channel 1 sample in bits 31 through 16, channel 0 sample in bits 15 through 0 in SDR0 6 8 bits 7 8 bits compact stereo Channel 1 sample in bits 15 through 8, channel 0 sample in bits 7through 0 in SDR0 699 32142D–06/2013 ATUC64/128/256L3/4U 28.7.2 Sample Data Register 0 Name: SDR0 Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • DATA: Sample Data Sample Data for channel 0 in two’s complement format. Data must be right-justified, see Table 28-5. 31 30 29 28 27 26 25 24 DATA[31:24] 23 22 21 20 19 18 17 16 DATA[23:16] 15 14 13 12 11 10 9 8 DATA[15:8] 76543210 DATA[7:0] Table 28-5. Sample Data Register Formats Data Format SDR0 SDR1 Comment 32 bits CH0 sample in DATA[31:0] CH1 sample in DATA[31:0] 24 bits CH0 sample in DATA[23:0] CH1 sample in DATA[23:0] Remaining bits are ignored. 20 bits CH0 sample in DATA[19:0] CH1 sample in DATA[19:0] Remaining bits are ignored. 18 bits CH0 sample in DATA[17:0] CH1 sample in DATA[17:0] Remaining bits are ignored. 16 bits CH0 sample in DATA[15:0] CH1 sample in DATA[15:0] Remaining bits are ignored. 16 bits compact stereo CH0 sample in DATA[15:0] CH1 sample in DATA[31:16] Not used 8 bits CH0 sample in DATA[7:0] CH1 sample in DATA[7:0] Remaining bits are ignored. 8 bits compact stereo CH0 sample in DATA[7:0] CH1 sample in DATA[15:8] Not used Remaining bits are ignored. 700 32142D–06/2013 ATUC64/128/256L3/4U 28.7.3 Sample Data Register 1 Name: SDR1 Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • DATA: Sample Data Sample Data for channel 1 in two’s complement format. Data must be right-justified, see Table 28-5 on page 699. 31 30 29 28 27 26 25 24 DATA[31:24] 23 22 21 20 19 18 17 16 DATA[23:16] 15 14 13 12 11 10 9 8 DATA[15:8] 76543210 DATA[7:0] 701 32142D–06/2013 ATUC64/128/256L3/4U 28.7.4 Volume Control Register 0 Name: VCR0 Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • MUTE: Mute 0: Channel 0 is not muted. 1: Channel 0 is muted. • VOLUME: Volume Control 15-bit value adjusting the volume for channel 0. 31 30 29 28 27 26 25 24 MUTE - - - - - - - 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - VOLUME[14:8] 76543210 VOLUME[7:0] 702 32142D–06/2013 ATUC64/128/256L3/4U 28.7.5 Volume Control Register 1 Name: VCR1 Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 • MUTE: Mute 0: Channel 1 is not muted. 1: Channel 1 is muted. • VOLUME: Volume Control 15-bit value adjusting the volume for channel 1. 31 30 29 28 27 26 25 24 MUTE - - - - - - - 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - VOLUME[14:8] 76543210 VOLUME[7:0] 703 32142D–06/2013 ATUC64/128/256L3/4U 28.7.6 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - TXUR TXRDY - 704 32142D–06/2013 ATUC64/128/256L3/4U 28.7.7 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - TXUR TXRDY - 705 32142D–06/2013 ATUC64/128/256L3/4U 28.7.8 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - TXUR TXRDY - 706 32142D–06/2013 ATUC64/128/256L3/4U 28.7.9 Status Register Name: SR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 • TXUR: Transmit Underrun This bit is cleared when no underrun has occurred since the last time this bit was cleared (by reset or by writing to SCR). This bit is set when at least one underrun has occurred since the last time this bit was cleared (by reset or by writing to SCR). • TXRDY: Transmit Ready This bit is cleared when the ABDACB is not ready to receive a new data in SDR. This bit is set when the ABDACB is ready to receive a new data in SDR. • BUSY: ABDACB Busy This bit is set when the ABDACB is busy doing a data transfer between clock domains. CR, SDR0, and SDR1 can not be written during this time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - TXUR TXRDY BUSY 707 32142D–06/2013 ATUC64/128/256L3/4U 28.7.10 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - TXUR TXRDY - 708 32142D–06/2013 ATUC64/128/256L3/4U 28.7.11 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 Reserved. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------- 709 32142D–06/2013 ATUC64/128/256L3/4U 28.7.12 Version Register Name: VERSION Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 710 32142D–06/2013 ATUC64/128/256L3/4U 28.8 Module Configuration The specific configuration for each ABDACB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 28-6. ABDACB Clocks Clock Name Description CLK_ABDACB Clock for the ABDACB bus interface GCLK The generic clock used for the ABDACB is GCLK6 Table 28-7. Register Reset Values Register Reset Value VERSION 0x00000100 PARAMETER 0x00000000 711 32142D–06/2013 ATUC64/128/256L3/4U 29. ADC Interface (ADCIFB) Rev:1.0.1.1 29.1 Features • Multi-channel Analog-to-Digital Converter with up to 12-bit resolution • Enhanced Resolution Mode – 11-bit resolution obtained by interpolating 4 samples – 12-bit resolution obtained by interpolating 16 samples • Glueless interface with resistive touch screen panel, allowing – Resistive Touch Screen position measurement – Pen detection and pen loss detection • Integrated enhanced sequencer – ADC Mode – Resistive Touch Screen Mode • Numerous trigger sources – Software – Embedded 16-bit timer for periodic trigger – Pen detect trigger – Continuous trigger – External trigger, rising, falling, or any-edge trigger – Peripheral event trigger • ADC Sleep Mode for low power ADC applications • Programmable ADC timings – Programmable ADC clock – Programmable startup time 29.2 Overview The ADC Interface (ADCIFB) converts analog input voltages to digital values. The ADCIFB is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). The conversions extend from 0V to ADVREFP. The ADCIFB supports 8-bit and 10-bit resolution mode, in addition to enhanced resolution mode with 11-bit and 12-bit resolution. Conversion results are reported in a common register for all channels. The 11-bit and 12-bit resolution modes are obtained by interpolating multiple samples to acquire better accuracy. For 11-bit mode 4 samples are used, which gives an effective sample rate of 1/4 of the actual sample frequency. For 12-bit mode 16 samples are used, giving a effective sample rate of 1/16 of actual. This arrangement allows conversion speed to be traded for better accuracy. Conversions can be started for all enabled channels, either by a software trigger, by detection of a level change on the external trigger pin (TRIGGER), or by an integrated programmable timer. When the Resistive Touch Screen Mode is enabled, an integrated sequencer automatically configures the pad control signals and performs resistive touch screen conversions. The ADCIFB also integrates an ADC Sleep Mode, a Pen-Detect Mode, and an Analog Compare Mode, and connects with one Peripheral DMA Controller channel. These features reduce both power consumption and processor intervention. 712 32142D–06/2013 ATUC64/128/256L3/4U 29.3 Block Diagram Figure 29-1. ADCIFB Block Diagram ADVREFP Analog Multiplexer Successive Approximation Register Analog-to-Digital Converter Trigger ADC Control Logic Timer User Interface AD0 AD1 AD3 ADn AD2 Resisitve Touch Screen Sequencer CLK_ADCIFB .... ADCIFB ADP0 ADP1 I/O Controller TRIGGER Peripheral Bus DMA Request Interrupt Request CLK_ADC 713 32142D–06/2013 ATUC64/128/256L3/4U 29.4 I/O Lines Description 29.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 29.5.1 I/O Lines The analog input pins can be multiplexed with I/O Controller lines. The user must make sure the I/O Controller is configured correctly to allow the ADCIFB access to the AD pins before the ADCIFB is instructed to start converting data. If the user fails to do this the converted data may be wrong. The number of analog inputs is device dependent, please refer to the ADCIFB Module Configuration chapter for the number of available AD inputs on the current device. The ADVREFP pin must be connected correctly prior to using the ADCIFB. Failing to do so will result in invalid ADC operation. See the Electrical Characteristics chapter for details. If the TRIGGER, ADP0, and ADP1 pins are to be used in the application, the user must configure the I/O Controller to assign the needed pins to the ADCIFB function. 29.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the ADCIFB, the ADCIFB will stop functioning and resume operation after the system wakes up from sleep mode. If the Peripheral Event System is configured to send asynchronous peripheral events to the ADCIFB and the clock used by the ADCIFB is stopped, a local and temporary clock will automatically be requested so the event can be processed. Refer to Section 29.6.13, Section 29.6.12, and the Peripheral Event System chapter for details. Before entering a sleep mode where the clock to the ADCIFB is stopped, make sure the Analogto-Digital Converter cell is put in an inactive state. Refer to Section 29.6.13 for more information. 29.5.3 Clocks The clock for the ADCIFB bus interface (CLK_ADCIFB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ADCIFB before disabling the clock, to avoid freezing the ADCIFB in an undefined state. Table 29-1. I/O Lines Description Pin Name Description Type ADVREFP Reference voltage Analog TRIGGER External trigger Digital ADP0 Drive Pin 0 for Resistive Touch Screen top channel (Xp) Digital ADP1 Drive Pin 1 for Resistive Touch Screen right channel (Yp) Digital AD0-ADn Analog input channels 0 to n Analog 714 32142D–06/2013 ATUC64/128/256L3/4U 29.5.4 DMA The ADCIFB DMA handshake interface is connected to the Peripheral DMA Controller. Using the ADCIFB DMA functionality requires the Peripheral DMA Controller to be programmed first. 29.5.5 Interrupts The ADCIFB interrupt request line is connected to the interrupt controller. Using the ADCIFB interrupt request functionality requires the interrupt controller to be programmed first. 29.5.6 Peripheral Events The ADCIFB peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details 29.5.7 Debug Operation When an external debugger forces the CPU into debug mode, this module continues normal operation. If this module is configured in a way that requires it to be periodically serviced by the CPU through interrupt requests or similar, improper operation or data loss may result during debugging. 29.6 Functional Description The ADCIFB embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC supports 8-bit or 10-bit resolution, which can be extended to 11 or 12 bits by the Enhanced Resolution Mode. The conversion is performed on a full range between 0V and the reference voltage pin ADVREFP. Analog inputs between these voltages converts to digital values (codes) based on a linear conversion. This linear conversion is described in the expression below where M is the number of bits used to represent the analog value, Vin is the voltage of the analog value to convert, Vref is the maximum voltage, and Code is the converted digital value. 29.6.1 Initializing the ADCIFB The ADC Interface is enabled by writing a one to the Enable bit in the Control Register (CR.EN). After the ADC Interface is enabled, the ADC timings needs to be configured by writing the correct values to the RES, PRESCAL, and STARTUP fields in the ADC Configuration Register (ACR). See Section 29.6.5, and Section 29.6.7 for details. Before the ADCIFB can be used, the I/O Controller must be configured correctly and the Reference Voltage (ADVREFP) signal must be connected. Refer to Section 29.5.1 for details. 29.6.2 Basic Operation To convert analog values to digital values the user must first initialize the ADCIFB as described in Section 29.6.1. When the ADCIFB is initialized the channels to convert must be enabled by writing a one the corresponding bits in the Channel Enable Register (CHER). Enabling channel N instructs the ADCIFB to convert the analog voltage applied to AD pin N at each conversion sequence. Multiple channels can be enabled resulting in multiple AD pins being converted at each conversion sequence. Code 2M Vin  Vref = ------------------- 715 32142D–06/2013 ATUC64/128/256L3/4U To start converting data the user can either manually start a conversion sequence by writing a one to the START bit in the Control Register (CR.START) or configure an automatic trigger to initiate the conversions. The automatic trigger can be configured to trig on many different conditions. Refer to Section 29.8.1 for details. The result of the conversion is stored in the Last Converted Data Register (LCDR) as they become available, overwriting the result from the previous conversion. To avoid data loss if more than one channel is enabled, the user must read the conversion results as they become available either by using an interrupt handler or by using a Peripheral DMA channel to copy the results to memory. Failing to do so will result in an Overrun Error condition, indicated by the OVRE bit in the Status Register (SR). To use an interrupt handler the user must enable the Data Ready (DRDY) interrupt request by writing a one to the corresponding bit in the Interrupt Enable Register (IER). To clear the interrupt after the conversion result is read, the user must write a one to the corresponding bit in the Interrupt Clear Register (ICR). See Section 29.6.11 for details. To use a Peripheral DMA Controller channel the user must configure the Peripheral DMA Controller appropriately. The Peripheral DMA Controller will, when configured, automatically read converted data as they become available. There is no need to manually clear any bits in the Interrupt Status Register as this is performed by the hardware. If an Overrun Error condition happens during DMA operation, the OVRE bit in the SR will be set. 29.6.3 ADC Resolution The Analog-to-Digital Converter cell supports 8-bit or 10-bit resolution, which can be extended to 11-bit and 12-bit with the Enhanced Resolution Mode. The resolution is selected by writing the selected resolution value to the RES field in the ADC Configuration Register (ACR). See Section 29.9.3. By writing a zero to the RES field, the ADC switches to the lowest resolution and the conversion results can be read in the eight lowest significant bits of the Last Converted Data Register (LCDR). The four highest bits of the Last Converted Data (LDATA) field in the LCDR register reads as zero. Writing a one to the RES field enables 10-bit resolution, the optimal resolution for both sampling speed and accuracy. Writing two or three automatically enables Enhanced Resolution Mode with 11-bit or 12-bit resolution, see Section 29.6.4 for details. When a Peripheral DMA Controller channel is connected to the ADCIFB in 10-bit, 11-bit, or 12- bit resolution mode, a transfer size of 16 bits must be used. By writing a zero to the RES field, the destination buffers can be optimized for 8-bit transfers. 29.6.4 Enhanced Resolution Mode The Enhanced Resolution Mode is automatically enabled when 11-bit or 12-bit mode is selected in the ADC Configuration Register (ACR). In this mode the ADCIFB will trade conversion performance for accuracy by averaging multiple samples. To be able to increase the accuracy by averaging multiple samples it is important that some noise is present in the input signal. The noise level should be between one and two LSB peakto-peak to get good averaging performance. The performance cost of enabling 11-bit mode is 4 ADC samples, which reduces the effective ADC performance by a factor 4. For 12-bit mode this factor is 16. For 12-bit mode the effective sample rate is maximum ADC sample rate divided by 16. 716 32142D–06/2013 ATUC64/128/256L3/4U 29.6.5 ADC Clock The ADCIFB generates an internal clock named CLK_ADC that is used by the Analog-to-Digital Converter cell to perform conversions. The CLK_ADC frequency is selected by writing to the PRESCAL field in the ADC Configuration Register (ACR). The CLK_ADC range is between CLK_ADCIFB/2, if PRESCAL is 0, and CLK_ADCIFB/128, if PRESCAL is 63 (0x3F). A sensible PRESCAL value must be used in order to provide an ADC clock frequency according to the maximum sampling rate parameter given in the Electrical Characteristics section. Failing to do so may result in incorrect Analog-to-Digital Converter operation. 29.6.6 ADC Sleep Mode The ADC Sleep Mode maximizes power saving by automatically deactivating the Analog-to-Digital Converter cell when it is not being used for conversions. The ADC Sleep Mode is enabled by writing a one to the SLEEP bit in the ADC Configuration Register (ACR). When a trigger occurs while the ADC Sleep Mode is enabled, the Analog-to-Digital Converter cell is automatically activated. As the analog cell requires a startup time, the logic waits during this time and then starts the conversion of the enabled channels. When conversions of all enabled channels are complete, the ADC is deactivated until the next trigger. 29.6.7 Startup Time The Analog-to-Digital Converter cell has a minimal startup time when the cell is activated. This startup time is given in the Electrical Characteristics chapter and must be written to the STARTUP field in the ADC Configuration Register (ACR) to get correct conversion results. The STARTUP field expects the startup time to be represented as the number of CLK_ADC cycles between 8 and 1024 and in steps of 8 that is needed to cover the ADC startup time as specified in the Electrical Characteristics chapter. The Analog-to-Digital Converter cell is activated at the first conversion after reset and remains active if ACR.SLEEP is zero. If ACR.SLEEP is one, the Analog-to-Digital Converter cell is automatically deactivated when idle and thus each conversion sequence will have a initial startup time delay. 29.6.8 Sample and Hold Time A minimal Sample and Hold Time is necessary for the ADCIFB to guarantee the best converted final value when switching between ADC channels. This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier. The Sample and Hold time has to be programmed through the SHTIM field in the ADC Configuration Register (ACR). This field can define a Sample and Hold time between 1 and 16 CLK_ADC cycles. 29.6.9 ADC Conversion ADC conversions are performed on all enabled channels when a trigger condition is detected. For details regarding trigger conditions see Section 29.8.1. The term channel is used to identify a specific analog input pin so it can be included or excluded in an Analog-to-Digital conversion sequence and to identify which AD pin was used to convert the current value in the Last Converted Data Register (LCDR). Channel number N corresponding to AD pin number N. 717 32142D–06/2013 ATUC64/128/256L3/4U Channels are enabled by writing a one to the corresponding bit in the Channel Enable Register (CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register (CHDR). Active channels are listed in the Channel Status Register (CHSR). When a conversion sequence is started, all enabled channels will be converted in one sequence and the result will be placed in the Last Converted Data Register (LCDR) with the channel number used to produce the result. It is important to read out the results while the conversion sequence is ongoing, as new values will automatically overwrite any old value and the old value will be lost if not previously read by the user. If the Analog-to-Digital Converter cell is inactive when starting a conversion sequence, the conversion logic will wait a configurable number of CLK_ADC cycles as defined in the startup time field in the ADC Configuration Register (ACR). After the cell is activated all enabled channels is converted one by one until no more enabled channels exist. The conversion sequence converts each enabled channel in order starting with the channel with the lowest channel number. If the ACR.SLEEP bit is one, the Analog-to-Digital Converter cell is deactivated after the conversion sequence has finished. For each channel converted, the ADCIFB waits a Sample and Hold number of CLK_ADC cycles as defined in the SHTIM field in ACR, and then instructs the Analog-to-Digital Converter cell to start converting the analog voltage. The ADC cell requires 10 CLK_ADC cycles to actually convert the value, so the total time to convert a channel is Sample and Hold + 10 CLK_ADC cycles. 29.6.10 Analog Compare Mode The ADCIFB can test if the converted values, as they become available, are below, above, or inside a specified range and generate interrupt requests based on this information. This is useful for applications where the user wants to monitor some external analog signal and only initiate actions if the value is above, below, or inside some specified range. The Analog Compare mode is enabled by writing a one to the Analog Compare Enable (ACE) bit in the Mode Register (MR). The values to compare must be written to the Low Value (LV) field and the High Value (HV) field in the Compare Value Register (CVR). The Analog Compare mode will, when enabled, check all enabled channels against the pre-programmed high and low values and set status bits. To generate an interrupt request if a converted value is below a limit, write the limit to the CVR.LV field and enable interrupt request on the Compare Lesser Than (CLT) bit by writing a one to the corresponding bit in the Interrupt Enable Register (IER). To generate an interrupt request if a converted value is above a limit, write the limit to the CVR.HV field and enable interrupt for Compare Greater Than (CGT) bit. To generate an interrupt request if a converted value is inside a range, write the low and high limit to the LV and HV fields and enable the Compare Else (CELSE) interrupt. To generate an interrupt request if a value is outside a range, write the LV and HV fields to the low and high limits of the range and enable CGT and CLT interrupts. Note that the values written to LV and HV must match the resolution selected in the ADC Configuration Register (ACR). 29.6.11 Interrupt Operation Interrupt requests are enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). Enabled interrupts can be read from the Interrupt Mask Register (IMR). Active interrupt requests, but potentially masked, are visible in the Interrupt Status Register (ISR). To 718 32142D–06/2013 ATUC64/128/256L3/4U clear an active interrupt request, write a one to the corresponding bit in the Interrupt Clear Register (ICR). The source for the interrupt requests are the status bits in the Status Register (SR). The SR shows the ADCIFB status at the time the register is read. The Interrupt Status Register (ISR) shows the status since the last write to the Interrupt Clear Register. The combination of ISR and SR allows the user to react to status change conditions but also allows the user to read the current status at any time. 29.6.12 Peripheral Events The Peripheral Event System can be used together with the ADCIFB to allow any peripheral event generator to be used as a trigger source. To enable peripheral events to trigger a conversion sequence the user must write the Peripheral Event Trigger value (0x7) to the Trigger Mode (TRGMOD) field in the Trigger Register (TRGR). Refer to Table 29-4 on page 730. The user must also configure a peripheral event generator to emit peripheral events for the ADCIFB to trigger on. Refer to the Peripheral Event System chapter for details. 29.6.13 Sleep Mode Before entering sleep modes the user must make sure the ADCIFB is idle and that the Analogto-Digital Converter cell is inactive. To deactivate the Analog-to-Digital Converter cell the SLEEP bit in the ADC Configuration Register (ACR) must be written to one and the ADCIFB must be idle. To make sure the ADCIFB is idle, write a zero the Trigger Mode (TRGMOD) field in the Trigger Register (TRGR) and wait for the READY bit in the Status Register (SR) to be set. Note that by deactivating the Analog-to-Digital Converter cell, a startup time penalty as defined in the STARTUP field in the ADC Configuration Register (ACR) will apply on the next conversion. 29.6.14 Conversion Performances For performance and electrical characteristics of the ADCIFB, refer to the Electrical Characteristics chapter. 29.7 Resistive Touch Screen The ADCIFB embeds an integrated Resistive Touch Screen Sequencer that can be used to calculate contact coordinates on a resistive touch screen film. When instructed to start, the integrated Resistive Touch Screen Sequencer automatically applies a sequence of voltage patterns to the resistive touch screen films and the Analog-to-Digital Conversion cell is used to measure the effects. The resulting measurements can be used to calculate the horizontal and vertical contact coordinates. It is recommended to use a high resistance touch screen for optimal resolution. The resistive touch screen film is connected to the ADCIFB using the AD and ADP pins. See Section 29.7.3 for details. Resistive Touch Screen Mode is enabled by writing a one to the Touch Screen ADC Mode field in the Mode Register (MR.TSAMOD). In this mode, channels TSPO+0 though TSPO+3 are automatically enabled where TSPO refers to the Touch Screen Pin Offset field in the Mode Register (MR.TSPO). For each conversion sequence, all enabled channels before TSPO+0 and after TSPO+3 are converted as ordinary ADC channels, producing 1 conversion result each. When the sequencer enters the TSPO+0 channel the Resistive Touch Screen Sequencer will take over control and convert the next 4 channels as described in Section 29.7.4. 719 32142D–06/2013 ATUC64/128/256L3/4U 29.7.1 Resistive Touch Screen Principles A resistive touch screen is based on two resistive films, each one fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. Between the two, there is a layer that acts as an insulator, but makes a connection when pressure is applied to the screen. This is illustrated in Figure 29-2 on page 719. Figure 29-2. Resistive Touch Screen Position Measurement 29.7.2 Position Measurement Method As shown in Figure 29-2 on page 719, to detect the position of a contact, voltage is first applied to XP (top) and Xm (bottom) leaving Yp and Ym tristated. Due to the linear resistance of the film, there is a voltage gradient from top to bottom on the first film. When a contact is performed on the screen, the voltage at the contact point propagates to the second film. If the input impedance on the YP (right) and Ym (left) electrodes are high enough, no current will flow, allowing the voltage at the contact point to be measured at Yp. The value measured represents the vertical position component of the contact point. For the horizontal direction, the same method is used, but by applying voltage from YP (right) to Ym (left) and measuring at XP. In an ideal world (linear, with no loss), the vertical position is equal to: VYP / VDD To compensate for some of the real world imperfections, VXP and VXm can be measured and used to improve accuracy at the cost of two more conversions per axes. The new expression for the vertical position then becomes: (VYP - VXM) / (VXP - VXM) XM XP YM YP XP XM YP VDD GND Volt Horizontal Position Detection YP YM XP VDD GND Volt Vertical Position Detection Pen Contact 720 32142D–06/2013 ATUC64/128/256L3/4U 29.7.3 Resistive Touch Screen Pin Connections The resistive touch screen film signals connects to the ADCIFB using the AD and ADP pins. The XP (top) and XM (bottom) film signals are connected to ADtspo+0 and ADtspo+1 pins, and the YP (right) and YM (left) signals are connected to ADtspo+2 and ADtspo+3 pins. The tspo index is configurable through the Touch Screen Pin Offset (TSPO) field in the Mode Register (MR) and allows the user to configure which AD pins to use for resistive touch screen applications. Writing a zero to the TSPO field instructs the ADCIFB to use AD0 through AD3, where AD0 is connected to XP, AD1 is connected to XM and so on. Writing a one to the TSPO field instructs the ADCIFB to use AD1 through AD4 for resistive touch screen sequencing, where AD1 is connected to XP and AD0 is free to be used as an ordinary ADC channel. When the Analog Pin Output Enable (APOE) bit in the Mode Register (MR) is zero, the AD pins are used to measure input voltage and drive the GND sequences, while the ADP pins are used to drive the VDD sequences. This arrangement allows the user to reduce the voltage seen at the AD input pins by inserting external resistors between ADP0 and XP and ADP1 and YP signals which are again directly connected to the AD pins. It is important that the voltages observed at the AD pins are not higher than the maximum allowed ADC input voltage. See Figure 29-3 on page 721 for details regarding how to connect the resistive touch screen films to the AD and ADP pins. By adding a resistor between ADP0 and XP, and ADP1 and YP, the maximum voltage observed at the AD pins can be controlled by the following voltage divider expressions: The Rfilmx parameter is the film resistance observed when measuring between XP and XM. The Rresistorx parameter is the resistor size inserted between ADP0 and XP. The definition of Rfilmy and Rresistory is the same but for ADP1, YP, and YM instead. Table 29-2. Resistive Touch Screen Pin Connections ADCIFB Pin TS Signal, APOE == 0 TS Signal, APOE == 1 ADP0 Xp through a resistor No Connect ADP1 Yp through a resistor No Connect ADtspo+0 Xp Xp ADtspo+1 Xm Xm ADtspo+2 Yp Yp ADtspo+3 Ym Ym V ADtspo + 0   Rfilmx Rfilmx Rresistorx + -------------------------------------------- V DP0 =    721 32142D–06/2013 ATUC64/128/256L3/4U The ADP pins are used by default, as the APOE bit is zero after reset. Writing a one to the APOE bit instructs the ADCIFB Resistive Touch Screen Sequencer to use the already connected ADtspo+0 and ADtspo+2 pins to drive VDD to XP and YP signals directly. In this mode the ADP pins can be used as general purpose I/O pins. Before writing a one to the APOE bit the user must make sure that the I/O voltage is compatible with the ADC input voltage. If the I/O voltage is higher than the maximum input voltage of the ADC, permanent damage may occur. Refer to the Electrical Characteristics chapter for details. Figure 29-3. Resistive Touch Screen Pin Connections V ADtspo + 2   Rfilmy Rfilmy Rresistory + -------------------------------------------- V DP1 =    ADtspo+1 XM XP YM YP ADtspo+0 DP1 DP0 ADtspo+3 ADtspo+2 Analog Pin Output Enable (MR.APOE) == 0 ADtspo+1 XM XP YM YP ADtspo+0 DP1 DP0 ADtspo+3 ADtspo+2 Analog Pin Output Enable (MR.APOE) == 1 NC NC 722 32142D–06/2013 ATUC64/128/256L3/4U 29.7.4 Resistive Touch Screen Sequencer The Resistive Touch Screen Sequencer is responsible for applying voltage to the resistive touch screen films as described in Section 29.7.2. This is done by controlling the output enable and the output value of the ADP and AD pins. This allows the Resistive Touch Screen Sequencer to add a voltage gradient on one film while keeping the other film floating so a touch can be measured. The Resistive Touch Screen Sequencer will when measuring the vertical position, apply VDD and GND to the pins connected to XP and XM. The YP and YM pins are put in tristate mode so the measurement of YP can proceed without interference. To compensate for ADC offset errors and non ideal pad drivers, the actual voltage of XP and XM is measured as well, so the real values for VDD and GND can be used in the contact point calculation to increase accuracy. See second formula in Section 29.7.2. When the vertical values are converted the same setup is applies for the second axes, by setting XP and XM in tristate mode and applying VDD and GND to YP and YM. Refer to Section 29.8.3 for details. 29.7.5 Pen Detect If no contact is applied to the resistive touch screen films, any resistive touch screen conversion result will be undefined as the film being measured is floating. This can be avoided by enabling Pen Detect and only trigger resistive touch screen conversions when the Pen Contact (PENCNT) status bit in the Status Register (SR) is one. Pen Detect is enabled by writing a one to the Pen Detect (PENDET) bit in the Mode Register (MR). When Pen Detect is enabled, the ADCIFB grounds the vertical panel by applying GND to XP and XM and polarizes the horizontal panel by enabling pull-up on the pin connected to YP. The YM pin will in this mode be tristated. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, GND will propagate to YM by pulling down YP, allowing the contact to be registered by the ADCIFB. A programmable debouncing filter can be used to filter out false pen detects because of noise. The debouncing filter is programmable from one CLK_ADC period and up to 215 CLK_ADC periods. The debouncer length is set by writing to the PENDBC field in MR. 723 32142D–06/2013 ATUC64/128/256L3/4U Figure 29-4. Resistive Touch Screen Pen Detect The Resistive Touch Screen Pen Detect can be used to generate an ADCIFB interrupt request or it can be used to trig a conversion, so that a position can be measured as soon as a contact is detected. The Pen Detect Mode generates two types of status signals, reported in the Status Register (SR): • The bit PENCNT is set when current flows and remains set until current stops. • The bit NOCNT is set when no current flows and remains set until current flows. Before a current change is reflected in the SR, the new status must be stable for the duration of the debouncing time. Both status conditions can generate an interrupt request if the corresponding bit in the Interrupt Mask Register (IMR) is one. Refer to Section 29.6.11 on page 717. XP XM YM YP Tristate GND Pullup T o the ADC Debouncer Pen Interrupt PENDBC GND Resistive Touch Screen Sequencer 724 32142D–06/2013 ATUC64/128/256L3/4U 29.8 Operating Modes The ADCIFB features two operating modes, each defining a separate conversion sequence: • ADC Mode: At each trigger, all the enabled channels are converted. • Resistive Touch Screen Mode: At each trigger, all enabled channels plus the resistive touch screen channels are converted as described in Section 29.8.3. If channels except the dedicated resistive touch screen channels are enabled, they are converted normally before and after the resistive touch screen channels are converted. The operating mode is selected by the TSAMOD field in the Mode Register (MR). 29.8.1 Conversion Triggers A conversion sequence is started either by a software or by a hardware trigger. When a conversion sequence is started, all enabled channels will be converted and made available in the shared Last Converted Register (LCDR). The software trigger is asserted by writing a one to the START field in the Control Register (CR). The hardware trigger can be selected by the TRGMOD field in the Trigger Register (TRGR). Different hardware triggers exist: • External trigger, either rising or falling or any, detected on the external trigger pin TRIGGER • Pen detect trigger, depending the PENDET bit in the Mode Register (MR) • Continuous trigger, meaning the ADCIFB restarts the next sequence as soon as it finishes the current one • Periodic trigger, which is defined by the TRGR.TRGPER field • Peripheral event trigger, allowing the Peripheral Event System to synchronize conversion with some configured peripheral event source. Enabling a hardware trigger does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can still be initiated by the software trigger. 29.8.2 ADC Mode In the ADC Mode, the active channels are defined by the Channel Status Register (CHSR). A channel is enabled by writing a one to the corresponding bit in the Channel Enable Register (CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register (CHDR). The conversion results are stored in the Last Converted Data Register (LCDR) as they become available, overwriting old conversions. At each trigger, the following sequence is performed: 1. If ACR.SLEEP is one, wake up the ADC and wait for the startup time. 2. If Channel 0 is enabled, convert Channel 0 and store result in LCDR. 3. If Channel 1 is enabled, convert Channel 1 and store result in LCDR. 4. If Channel N is enabled, convert Channel N and store result in LCDR. 5. If ACR.SLEEP is one, place the ADC cell in a low-power state. If the Peripheral DMA Controller is enabled, all converted values are transferred continuously into the memory buffer. 29.8.3 Resistive Touch Screen Mode Writing a one to the TSAMOD field in the Mode Register (MR) enables Resistive Touch Screen Mode. In this mode the channels TSPO+0 to TSPO+3, corresponding to the resistive touch 725 32142D–06/2013 ATUC64/128/256L3/4U screen inputs, are automatically activated. In addition, if any other channels are enabled, they will be converted before and after the resistive touch screen conversion. At each trigger, the following sequence is performed: 1. If ACR.SLEEP is one, wake up the ADC cell and wait for the startup time. 2. Convert all enabled channels before TSPO and store the results in the LCDR. 3. Apply supply on the inputs XP and XM during the Sample and Hold Time. 4. Convert Channel XM and store the result in TMP. 5. Apply supply on the inputs XP and XM during the Sample and Hold Time. 6. Convert Channel XP, subtract TMP from the result and store the subtracted result in LCDR. 7. Apply supply on the inputs XP and XM during the Sample and Hold Time. 8. Convert Channel YP, subtract TMP from the result and store the subtracted result in LCDR. 9. Apply supply on the inputs YP and YM during the Sample and Hold Time. 10. Convert Channel YM and store the result in TMP. 11. Apply supply on the inputs YP and YM during the Sample and Hold Time. 12. Convert Channel YP, subtract TMP from the result and store the subtracted result in LCDR. 13. Apply supply on the inputs YP and YM during the Sample and Hold Time. 14. Convert Channel XP, subtract TMP from the result and store the subtracted result in LCDR. 15. Convert all enabled channels after TSPO + 3 and store results in the LCDR. 16. If ACR.SLEEP is one, place the ADC cell in a low-power state. The resulting buffer structure stored in memory is: 1. XP - XM 2. YP - XM 3. YP - YM 4. XP - YM. The vertical position can be easily calculated by dividing the data at offset 1(XP - XM) by the data at offset 2(YP - XM). The horizontal position can be easily calculated by dividing the data at offset 3(YP - YM) by the data at offset 4(XP - YM). 726 32142D–06/2013 ATUC64/128/256L3/4U 29.9 User Interface Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 29-3. ADCIFB Register Memory Map Offset Register Name Access Reset 0x00 Control Register CR Write-only - 0x04 Mode Register MR Read/Write 0x00000000 0x08 ADC Configuration Register ACR Read/Write 0x00000000 0x0C Trigger Register TRGR Read/Write 0x00000000 0x10 Compare Value Register CVR Read/Write 0x00000000 0x14 Status Register SR Read-only 0x00000000 0x18 Interrupt Status Register ISR Read-only 0x00000000 0x1C Interrupt Clear Register ICR Write-only - 0x20 Interrupt Enable Register IER Write-only - 0x24 Interrupt Disable Register IDR Write-only - 0x28 Interrupt Mask Register IMR Read-only 0x00000000 0x2C Last Converted Data Register LCDR Read-only 0x00000000 0x30 Parameter Register PARAMETER Read-only -(1) 0x34 Version Register VERSION Read-only -(1) 0x40 Channel Enable Register CHER Write-only - 0x44 Channel Disable Register CHDR Write-only - 0x48 Channel Status Register CHSR Read-only 0x00000000 727 32142D–06/2013 ATUC64/128/256L3/4U 29.9.1 Control Register Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 • DIS: ADCDIFB Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the ADCIFB. Note: Disabling the ADCIFB effectively stops all clocks in the module so the user must make sure the ADCIFB is idle before disabling the ADCIFB. • EN: ADCIFB Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the ADCIFB. Note: The ADCIFB must be enabled before use. • START: Start Conversion Writing a zero to this bit has no effect. Writing a one to this bit starts an Analog-to-Digital conversion. • SWRST: Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets the ADCIFB, simulating a hardware reset. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - - DIS EN 76543210 - - - - - - START SWRST 728 32142D–06/2013 ATUC64/128/256L3/4U 29.9.2 Mode Register Name: MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • PENDBC: Pen Detect Debouncing Period Period = 2PENDBC*TCLK_ADC • TSPO: Touch Screen Pin Offset The Touch Screen Pin Offset field is used to indicate which AD pins are connected to the resistive touch screen film edges. Only an offset is specified and it is assumed that the resistive touch screen films are connected sequentially from the specified offset pin and up to and including offset + 3 (4 pins). • APOE: Analog Pin Output Enable 0: AD pins are not used to drive VDD in resistive touch screen sequence. 1: AD pins are used to drive VDD in resistive touch screen sequence. Note: If the selected I/O voltage configuration is incompatible with the Analog-to-Digital converter cell voltage specification, this bit must stay cleared to avoid damaging the ADC. In this case the ADP pins must be used to drive VDD instead, as described in Section 29.7.3. If the I/O and ADC voltages are compatible, the AD pins can be used directly by writing a one to this bit. In this case the ADP pins can be ignored. • ACE: Analog Compare Enable 0: The analog compare functionality is disabled. 1: The analog compare functionality is enabled. • PENDET: Pen Detect 0: The pen detect functionality is disabled. 1: The pen detect functionality is enabled. Note: Touch detection logic can only be enabled when the ADC sequencer is idle. For successful pen detection the user must make sure there is enough idle time between consecutive scans for the touch detection logic to settle. • TSAMOD: Touch Screen ADC Mode 0: Touch Screen Mode is disabled. 1: Touch Screen Mode is enabled. 31 30 29 28 27 26 25 24 PENDBC - - - - 23 22 21 20 19 18 17 16 TSPO 15 14 13 12 11 10 9 8 -------- 76543210 - APOE ACE PENDET - - - TSAMOD 729 32142D–06/2013 ATUC64/128/256L3/4U 29.9.3 ADC Configuration Register Name: ACR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • SHTIM: Sample & Hold Time for ADC Channels • STARTUP: Startup Time • PRESCAL: Prescaler Rate Selection • RES: Resolution Selection 0: 8-bit resolution. 1: 10-bit resolution. 2: 11-bit resolution, interpolated. 3: 12-bit resolution, interpolated. • SLEEP: ADC Sleep Mode 0: ADC Sleep Mode is disabled. 1: ADC Sleep Mode is enabled. 31 30 29 28 27 26 25 24 - - - - SHTIM 23 22 21 20 19 18 17 16 - STARTUP 15 14 13 12 11 10 9 8 - - PRESCAL 76543210 - - RES - - - SLEEP TSAMPLE&HOLD   SHTIM + 2 TCLK_ADC =  TARTUP   STARTUP + 1  8 TCLK_AD =  TCLK_ADC =   PRESCAL + 1  2 TCLK_ADCIFB  730 32142D–06/2013 ATUC64/128/256L3/4U 29.9.4 Trigger Register Name: TRGR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • TRGPER: Trigger Period Effective only if TRGMOD defines a Periodic Trigger. Defines the periodic trigger period, with the following equations: Trigger Period = TRGPER *TCLK_ADC • TRGMOD: Trigger Mode 31 30 29 28 27 26 25 24 TRGPER[15:8] 23 22 21 20 19 18 17 16 TRGPER[7:0] 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - TRGMOD Table 29-4. Trigger Modes TRGMOD Selected Trigger Mode 0 0 0 No trigger, only software trigger can start conversions 0 0 1 External Trigger Rising Edge 0 1 0 External Trigger Falling Edge 0 1 1 External Trigger Any Edge 100 Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touch Screen mode) 1 0 1 Periodic Trigger (TRGPER shall be initiated appropriately) 1 1 0 Continuous Mode 1 1 1 Peripheral Event Trigger 731 32142D–06/2013 ATUC64/128/256L3/4U 29.9.5 Compare Value Register Name: CVR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 • HV: High Value Defines the high value used when comparing analog input. • LV: Low Value Defines the low value used when comparing analog input. 31 30 29 28 27 26 25 24 - - - - HV[11:8] 23 22 21 20 19 18 17 16 HV[7:0] 15 14 13 12 11 10 9 8 - - - - LV[11:8] 76543210 LV[7:0] 732 32142D–06/2013 ATUC64/128/256L3/4U 29.9.6 Status Register Name: SR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 • EN: Enable Status 0: The ADCIFB is disabled. 1: The ADCIFB is enabled. This bit is cleared when CR.DIS is written to one. This bit is set when CR.EN is written to one. • CELSE: Compare Else Status This bit is cleared when either CLT or CGT are detected or when analog compare is disabled. This bit is set when no CLT or CGT are detected on the last converted data and analog compare is enabled. • CGT: Compare Greater Than Status This bit is cleared when no compare greater than CVR.HV is detected on the last converted data or when analog compare is disabled. This bit is set when compare greater than CVR.HV is detected on the last converted data and analog compare is enabled. • CLT: Compare Lesser Than Status This bit is cleared when no compare lesser than CVR.LV is detected on the last converted data or when analog compare is disabled. This bit is set when compare lesser than CVR.LV is detected on the last converted data and analog compare is enabled. • BUSY: Busy Status This bit is cleared when the ADCIFB is ready to perform a conversion sequence. This bit is set when the ADCIFB is busy performing a convention sequence. • READY: Ready Status This bit is cleared when the ADCIFB is busy performing a conversion sequence This bit is set when the ADCIFB is ready to perform a conversion sequence. • NOCNT: No Contact Status This bit is cleared when no contact loss is detected or pen detect is disabled This bit is set when contact loss is detected and pen detect is enabled. • PENCNT: Pen Contact Status This bit is cleared when no contact is detected or pen detect is disabled. 31 30 29 28 27 26 25 24 - - - - - - - EN 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 76543210 - - NOCNT PENCNT - - OVRE DRDY 733 32142D–06/2013 ATUC64/128/256L3/4U This bit is set when pen contact is detected and pen detect is enabled. • OVRE: Overrun Error Status This bit is cleared when no Overrun Error has occurred since the start of a conversion sequence. This bit is set when one or more Overrun Error has occurred since the start of a conversion sequence. • DRDY: Data Ready Status 0: No data has been converted since the last reset. 1: One or more conversions have completed since the last reset and data is available in LCDR. This bit is cleared when CR.SWRST is written to one. This bit is set when one or more conversions have completed and data is available in LCDR. 734 32142D–06/2013 ATUC64/128/256L3/4U 29.9.7 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 • CELSE: Compare Else Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • CGT: Compare Greater Than Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • CLT: Compare Lesser Than Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • BUSY: Busy Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • READY: Ready Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • NOCNT: No Contact Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • PENCNT: Pen Contact Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • OVRE: Overrun Error Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding bit in SR has a zero-to-one transition. • DRDY: Data Ready Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when a conversion has completed and new data is available in LCDR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 76543210 - - NOCNT PENCNT - - OVRE DRDY 735 32142D–06/2013 ATUC64/128/256L3/4U 29.9.8 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 76543210 - - NOCNT PENCNT - - OVRE DRDY 736 32142D–06/2013 ATUC64/128/256L3/4U 29.9.9 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 76543210 - - NOCNT PENCNT - - OVRE DRDY 737 32142D–06/2013 ATUC64/128/256L3/4U 29.9.10 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 76543210 - - NOCNT PENCNT - - OVRE DRDY 738 32142D–06/2013 ATUC64/128/256L3/4U 29.9.11 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared by writing a one to the corresponding bit in Interrupt Disable Register (IDR). A bit in this register is set by writing a one to the corresponding bit in Interrupt Enable Register (IER). 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 76543210 - - NOCNT PENCNT - - OVRE DRDY 739 32142D–06/2013 ATUC64/128/256L3/4U 29.9.12 Last Converted Data Register Name: LCDR Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 • LCCH: Last Converted Channel This field indicates what channel was last converted, i.e. what channel the LDATA represents. • LDATA: Last Data Converted The analog-to-digital conversion data is placed in this register at the end of a conversion on any analog channel and remains until a new conversion on any analog channel is completed. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 LCCH 15 14 13 12 11 10 9 8 - - - - LDATA[11:8] 76543210 LDATA[7:0] 740 32142D–06/2013 ATUC64/128/256L3/4U 29.9.13 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: 0x00000000 • CHn: Channel n Implemented 0: The corresponding channel is not implemented. 1: The corresponding channel is implemented. 31 30 29 28 27 26 25 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 23 22 21 20 19 18 17 16 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 76543210 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 741 32142D–06/2013 ATUC64/128/256L3/4U 29.9.14 Version Register Name: VERSION Access Type: Read-only Offset: 0x34 Reset Value: 0x00000000 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the Module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 742 32142D–06/2013 ATUC64/128/256L3/4U 29.9.15 Channel Enable Register Name: CHER Access Type: Write-only Offset: 0x40 Reset Value: 0x00000000 • CHn: Channel n Enable Writing a zero to a bit in this register has no effect Writing a one to a bit in this register enables the corresponding channel The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this chapter for information regarding which channels are implemented. 31 30 29 28 27 26 25 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 23 22 21 20 19 18 17 16 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 76543210 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 743 32142D–06/2013 ATUC64/128/256L3/4U 29.9.16 Channel Disable Register Name: CHDR Access Type: Write-only Offset: 0x44 Reset Value: 0x00000000 • CHn: Channel N Disable Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion, or if it is disabled and then re-enabled during a conversion, its associated data and its corresponding DRDY and OVRE bits in SR are unpredictable. The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this chapter for information regarding how many channels are implemented. 31 30 29 28 27 26 25 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 23 22 21 20 19 18 17 16 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 76543210 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 744 32142D–06/2013 ATUC64/128/256L3/4U 29.9.17 Channel Status Register Name: CHSR Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 • CHn: Channel N Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. A bit in this register is cleared by writing a one to the corresponding bit in Channel Disable Register (CHDR). A bit in this register is set by writing a one to the corresponding bit in Channel Enable Register (CHER). The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this chapter for information regarding how many channels are implemented. 31 30 29 28 27 26 25 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 23 22 21 20 19 18 17 16 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 76543210 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 745 32142D–06/2013 ATUC64/128/256L3/4U 29.10 Module Configuration The specific configuration for each ADCIFB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Note: 1. AD3 does not exist Table 29-5. Module Configuration Feature ADCIFB Number of ADC channels 9 (8 + 1 internal temperature sensor channel) Table 29-6. ADCIFB Clocks Clock Name Description CLK_ADCIFB Clock for the ADCIFB bus interface Table 29-7. Register Reset Values Register Reset Value VERSION 0x00000110 PARAMETER 0x000003FF Table 29-8. ADC Input Channels(1) Channel Input CH0 AD0 CH1 AD1 CH2 AD2 CH4 AD4 CH5 AD5 CH6 AD6 CH7 AD7 CH8 AD8 CH9 Temperature sensor 746 32142D–06/2013 ATUC64/128/256L3/4U 30. Analog Comparator Interface (ACIFB) Rev: 2.0.2.2 30.1 Features • Controls an array of Analog Comparators • Low power option – Single shot mode support • Selectable settings for filter option – Filter length and hysteresis • Window Mode – Detect inside/outside window – Detect above/below window • Interrupt – On comparator result rising edge, falling edge, toggle – Inside window, outside window, toggle – When startup time has passed • Can generate events to the peripheral event system 30.2 Overview The Analog Comparator Interface (ACIFB) is able to control a number of Analog Comparators (AC) with identical behavior. An Analog Comparator compares two voltages and gives a compare output depending on this comparison. The ACIFB can be configured in normal mode using each comparator independently or in window mode using defined comparator pairs to observe a window. The number of channels implemented is device specific. Refer to the Module Configuration section at the end of this chapter for details. 747 32142D–06/2013 ATUC64/128/256L3/4U 30.3 Block Diagram Figure 30-1. ACIFB Block Diagram 30.4 I/O Lines Description There are two groups of analog comparators, A and B, as shown in Table 30-1. In normal mode, this grouping does not have any meaning. In window mode, two analog comparators, one from group A and the corresponding comparator from group B, are paired. ……………... TRIGGER EVENTS IRQ GCLK Peripheral Bus ACIFB Analog Comparators PERIPHERAL EVENT GENERATION - + AC INN INP CONF0.INSELN - + AC INN INP CONFn.INSELN FILTER FILTER INTERRUPT GENERATION CLK_ACIFB CTRL.ACTEST TR.ACTESTn TR.ACTEST0 ACOUT0 ACOUTn ACP0 ACN0 ACREFN ACPn ACNn Table 30-1. Analog Comparator Groups for Window Mode Group A Group B Pair Number AC0 AC1 0 AC2 AC3 1 AC4 AC5 2 AC6 AC7 3 Table 30-2. I/O Line Description Pin Name Pin Description Type ACAPn Positive reference pin for Analog Comparator A n Analog ACANn Negative reference pin for Analog Comparator A n Analog 748 32142D–06/2013 ATUC64/128/256L3/4U The signal names corresponds to the groups A and B of analog comparators. For normal mode, the mapping from input signal names in the block diagram to the signal names is given in Table 30-3. 30.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines The ACIFB pins are multiplexed with other peripherals. The user must first program the I/O Controller to give control of the pins to the ACIFB. 30.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the ACIFB, the ACIFB will stop functioning and resume operation after the system wakes up from sleep mode. 30.5.3 Clocks The clock for the ACIFB bus interface (CLK_ACIFB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ACIFB before disabling the clock, to avoid freezing the ACIFB in an undefined state. The ACIFB uses a GCLK as clock source for the Analog Comparators. The user must set up this GCLK at the right frequency. The CLK_ACIFB clock of the interface must be at least 4x the GCLK frequency used in the comparators. The GCLK is used both for measuring the startup time of a comparator, and to give a frequency for the comparisons done in Continuous Measurement Mode, see Section 30.6. Refer to the Electrical Characteristics chapter for GCLK frequency limitations. ACBPn Positive reference pin for Analog Comparator B n Analog ACBNn Negative reference pin for Analog Comparator B n Analog ACREFN Reference Voltage for all comparators selectable for INN Analog Table 30-3. Signal Name Mapping Pin Name Channel Number Normal Mode ACAP0/ACAN0 0 ACP0/ACN0 ACBP0/ACBN0 1 ACP1/ACN1 ACAP1/ACAN1 2 ACP2/ACN2 ACBP1/ACBN1 3 ACP3/ACN3 ACAP2/ACAN2 4 ACP4/ACN4 ACBP2/ACBN2 5 ACP5/ACN5 ACAP3/ACAN3 6 ACP6/ACN6 ACBP3/ACBN3 7 ACP7/ACN7 Table 30-2. I/O Line Description Pin Name Pin Description Type 749 32142D–06/2013 ATUC64/128/256L3/4U 30.5.4 Interrupts The ACIFB interrupt request line is connected to the interrupt controller. Using the ACIFB interrupt requires the interrupt controller to be programmed first. 30.5.5 Peripheral Events The ACIFB peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 30.5.6 Debug Operation When an external debugger forces the CPU into debug mode, the ACIFB continues normal operation. If the ACIFB is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 30.6 Functional Description The ACIFB is enabled by writing a one to the Control Register Enable bit (CTRL.EN). Additionally, the comparators must be individually enabled by programming the MODE field in the AC Configuration Register (CONFn.MODE). The results from the individual comparators can either be used directly (normal mode), or the results from two comparators can be grouped to generate a comparison window (window mode). All comparators need not be in the same mode, some comparators may be in normal mode, while others are in window mode. There are restrictions on which AC channels that can be grouped together in a window pair, see Section 30.6.5. 30.6.1 Analog Comparator Operation Each AC channel can be in one of four different modes, determined by CONFn.MODE: • Off • Continuous Measurement Mode (CM) • User Triggered Single Measurement Mode (UT) • Event Triggered Single Measurement Mode (ET) After being enabled, a startup time defined in CTRL.SUT is required before the result of the comparison is ready. The GCLK is used for measuring the startup time of a comparator, During the startup time the AC output is not available. When the ACn Ready bit in the Status Register (SR.ACRDYn) is one, the output of ACn is ready. In window mode the result is available when both the comparator outputs are ready (SR.ACRDYn=1 and SR.ACRDYn+1=1). 30.6.1.1 Continuous Measurement Mode In CM, the Analog Comparator is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always available in the ACn Current Comparison Status bit in the Status Register (SR.ACCSn). Comparisons are done on every positive edge of GCLK. CM is enabled by writing CONFn.MODE to 1. After the startup time has passed, a comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. New comparisons are performed continuously until the CONFn.MODE field is written to 0. 750 32142D–06/2013 ATUC64/128/256L3/4U 30.6.1.2 User Triggered Single Measurement Mode In the UT mode, the user starts a single comparison by writing a one to the User Start Single Comparison bit (CTRL.USTART). This mode is enabled by writing CONFn.MODE to 2. After the startup time has passed, a single comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. CTRL.USTART is cleared automatically by hardware when the single comparison has been done. 30.6.1.3 Event Triggered Single Measurement Mode This mode is enabled by writing CONFn.MODE to 3 and Peripheral Event Trigger Enable (CTRL.EVENTEN) to one. The ET mode is similar to the UT mode, the difference is that a peripheral event from another hardware module causes the hardware to automatically set the Peripheral Event Start Single Comparison bit (CTRL.ESTART). After the startup time has passed, a single comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. CTRL.ESTART is cleared automatically by hardware when the single comparison has been done. 30.6.1.4 Selecting Comparator Inputs Each Analog Comparator has one positive (INP) and one negative (INN) input. The positive input is fed from an external input pin (ACPn). The negative input can either be fed from an external input pin (ACNn) or from a reference voltage common to all ACs (ACREFN). The user selects the input source as follows: • In normal mode with the Negative Input Select and Positive Input Select fields (CONFn.INSELN and CONFn.INSELP). • In window mode with CONFn.INSELN, CONFn.INSELP and CONFn+1.INSELN, CONFn+1,INSELP. The user must configure CONFn.INSELN and CONFn+1.INSELP to the same source. 30.6.2 Interrupt Generation The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in ISR is cleared by writing a one to the corresponding bit in the Interrupt Status Clear Register (ICR). 30.6.3 Peripheral Event Generation The ACIFB can be set up so that certain comparison results notify other parts of the device via the Peripheral Event system. Refer to Section 30.6.4.3 and Section 30.6.5.3 for information on which comparison results can generate events, and how to configure the ACIFB to achieve this. Zero or one event will be generated per comparison. 30.6.4 Normal Mode In normal mode all Analog Comparators are operating independently. 30.6.4.1 Normal Mode Output Each Analog Comparator generates one output ACOUT according to the input voltages on INP (AC positive input) and INN (AC negative input): 751 32142D–06/2013 ATUC64/128/256L3/4U • ACOUT = 1 if VINP > VINN • ACOUT = 0 if VINP < VINN • ACOUT = 0 if the AC output is not available (SR.ACRDY = 0) The output can optionally be filtered, as described in Section 30.6.6. 30.6.4.2 Normal Mode Interrupt The AC channels can generate interrupts. The Interrupt Settings field in the Configuration Register (CONFn.IS) can be configured to select when the AC will generate an interrupt: • When VINP > VINN • When VINP < VINN • On toggle of the AC output (ACOUT) • When comparison has been done 30.6.4.3 Normal Mode Peripheral Events The ACIFB can generate peripheral events according to the configuration of CONFn.EVENN and CONFn.EVENP. • When VINP > VINN or • When VINP < VINN or • On toggle of the AC output (ACOUT) 30.6.5 Window Mode In window mode, two ACs (an even and the following odd build up a pair) are grouped. The negative input of ACn (even) and the positive input of ACn+1 (odd) has to be connected together externally to the device and are controlled by the Input Select fields in the AC Configuration Registers (CONFn.INSELN and CONFn+1.INSELP). The positive input of ACn (even) and the negative input of ACn+1 (odd) can still be configured independently by CONFn.INSELP and CONFn+1.INSELN, respectively. 752 32142D–06/2013 ATUC64/128/256L3/4U Figure 30-2. Analog Comparator Interface in Window Mode 30.6.5.1 Window Mode Output When operating in window mode, each channel generates the same ACOUT outputs as in normal mode, see Section 30.6.4.1. Additionally, the ACIFB generates a window mode signal (acwout) according to the common input voltage to be compared: • ACWOUT = 1 if the common input voltage is inside the window, VACN(N+1) < Vcommon < VACP(N) • ACWOUT = 0 if the common input voltage is outside the window, Vcommon < VACN(N+1) or Vcommon > VACP(N) • ACWOUT = 0 if the window mode output is not available (SR.ACRDYn=0 or SR.ACRDYn+1=0) 30.6.5.2 Window Mode Interrupts When operating in window mode, each channel can generate the same interrupts as in normal mode, see Section 30.6.4.2. Additionally, when channels operate in window mode, programming Window Mode Interrupt Settings in the Window Mode Configuration Register (CONFWn.WIS) can cause interrupts to be generated when: • As soon as the common input voltage is inside the window. • As soon as the common input voltage is outside the window. • On toggle of the window compare output (ACWOUT). • When the comparison in both channels in the window pair is ready. Comparator pair 0 - + AC0 Interrupt Generator Window Module ACOUT0 Peripheral Event Generator Window window event - + AC1 Filter Filter SR.ACCS0 SR.WFCS0 ACAP0 ACAN0 ACBP0 COMMON ACWOUT ACBN0 IRQ ACOUT1 753 32142D–06/2013 ATUC64/128/256L3/4U 30.6.5.3 Window Mode Peripheral Events When operating in window mode, each channel can generate the same peripheral events as in normal mode, see Section 30.6.4.3. Additionally, when channels operate in window mode, programming Window Mode Event Selection Source (CONFWn.WEVSRC) can cause peripheral events to be generated when: • As soon as the common input voltage is inside the window. • As soon as the common input voltage is outside the window. • On toggle of the window compare output (ACWOUT) • Whenever a comparison is ready and the common input voltage is inside the window. • Whenever a comparison is ready and the common input voltage is outside the window. • When the comparison in both channels in the window pair is ready. 30.6.6 Filtering The output of the comparator can be filtered to reduce noise. The filter length is determined by the Filter Length field in the CONFn register (CONFn.FLEN). The filter samples the Analog Comparator output at the GCLK frequency for 2CONFn.FLEN samples. A separate counter (CNT) counts the number of cycles the AC output was one. This filter is deactivated if CONFn.FLEN equals 0. If the filter is enabled, the Hysteresis Value field HYS in the CONFn register (CONFn.HYS) can be used to define a hysteresis value. The hysteresis value should be chosen so that: The filter function is defined by: The filtering algorithm is explained in Figure 30-3. 2FLEN measurements are sampled. If the number of measurements that are zero is less than (2FLEN/2 - HYS), the filtered result is zero. If the number of measurements that are one is more than (2FLEN/2 + HYS), the filtered result is one. Otherwise, the result is unchanged. 2FLEN 2 ----------------  HYS CNT 2FLEN 2 ---------------- + HYS       comp = 1 2FLEN 2 ---------------- + HYS     CNT 2FLEN 2 ----------------–HYS        comp unchanged CNT 2FLEN 2 ----------------–HYS       comp = 0 754 32142D–06/2013 ATUC64/128/256L3/4U Figure 30-3. The Filtering Algorithm 30.7 Peripheral Event Triggers Peripheral events from other modules can trigger comparisons in the ACIFB. All channels that are set up in Event Triggered Single Measurement Mode will be started simultaneously when a peripheral event is received. Channels that are operating in Continuous Measurement Mode or User Triggered Single Measurement Mode will be unaffected by the received event. The software can still operate these channels independently of channels in Event Triggered Single Measurement Mode. A peripheral event will trigger one or more comparisons, in normal or window mode. 30.8 AC Test mode By writing the Analog Comparator Test Mode (CR.ACTEST) bit to one, the outputs from the ACs are overridden by the value in the Test Register (TR), see Figure 30-1. This is useful for software development. 2 FLEN 2 FLEN 2 HYS HYS ”Result=0" ”Result=1" Result = UNCHANGED 0 755 32142D–06/2013 ATUC64/128/256L3/4U 30.9 User Interface Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 30-4. ACIFB Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CTRL Read/Write 0x00000000 0x04 Status Register SR Read-only 0x00000000 0x10 Interrupt Enable Register IER Write-only 0x00000000 0x14 Interrupt Disable Register IDR Write-only 0x00000000 0x18 Interrupt Mask Register IMR Read-only 0x00000000 0x1C Interrupt Status Register ISR Read-only 0x00000000 0x20 Interrupt Status Clear Register ICR Write-only 0x00000000 0x24 Test Register TR Read/Write 0x00000000 0x30 Parameter Register PARAMETER Read-only -(1) 0x34 Version Register VERSION Read-only -(1) 0x80 Window0 Configuration Register CONFW0 Read/Write 0x00000000 0x84 Window1 Configuration Register CONFW1 Read/Write 0x00000000 0x88 Window2 Configuration Register CONFW2 Read/Write 0x00000000 0x8C Window3 Configuration Register CONFW3 Read/Write 0x00000000 0xD0 AC0 Configuration Register CONF0 Read/Write 0x00000000 0xD4 AC1 Configuration Register CONF1 Read/Write 0x00000000 0xD8 AC2 Configuration Register CONF2 Read/Write 0x00000000 0xDC AC3 Configuration Register CONF3 Read/Write 0x00000000 0xE0 AC4 Configuration Register CONF4 Read/Write 0x00000000 0xE4 AC5 Configuration Register CONF5 Read/Write 0x00000000 0xE8 AC6 Configuration Register CONF6 Read/Write 0x00000000 0xEC AC7 Configuration Register CONF7 Read/Write 0x00000000 756 32142D–06/2013 ATUC64/128/256L3/4U 30.9.1 Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • SUT: Startup Time Analog Comparator startup time = . Each time an AC is enabled, the AC comparison will be enabled after the startup time of the AC. • ACTEST: Analog Comparator Test Mode 0: The Analog Comparator outputs feeds the channel logic in ACIFB. 1: The Analog Comparator outputs are bypassed with the AC Test Register. • ESTART: Peripheral Event Start Single Comparison Writing a zero to this bit has no effect. Writing a one to this bit starts a comparison and can be used for test purposes. This bit is cleared when comparison is done. This bit is set when an enabled peripheral event is received. • USTART: User Start Single Comparison Writing a zero to this bit has no effect. Writing a one to this bit starts a Single Measurement Mode comparison. This bit is cleared when comparison is done. • EVENTEN: Peripheral Event Trigger Enable 0: A peripheral event will not trigger a comparison. 1: Enable comparison triggered by a peripheral event. • EN: ACIFB Enable 0: The ACIFB is disabled. 1: The ACIFB is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - SUT[9:8] 15 14 13 12 11 10 9 8 SUT[7:0] 76543210 ACTEST - ESTART USTART - - -EVENTEN EN SUT FGCLK ---------------- 757 32142D–06/2013 ATUC64/128/256L3/4U 30.9.2 Status Register Name: SR Access Type: Read-only Offset: 0x04 Reset Value: 0x00000000 • WFCSn: Window Mode Current Status This bit is cleared when the common input voltage is outside the window. This bit is set when the common input voltage is inside the window. • ACRDYn: ACn Ready This bit is cleared when the AC output (ACOUT) is not ready. This bit is set when the AC output (ACOUT) is ready, AC is enabled and its startup time is over. • ACCSn: ACn Current Comparison Status This bit is cleared when VINP is currently lower than VINN This bit is set when VINP is currently greater than VINN. 31 30 29 28 27 26 25 24 - - - - WFCS3 WFCS2 WFCS1 WFCS0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ACRDY7 ACCS7 ACRDY6 ACCS6 ACRDY5 ACCS5 ACRDY4 ACCS4 76543210 ACRDY3 ACCS3 ACRDY2 ACCS2 ACRDY1 ACCS1 ACRDY0 ACCS0 758 32142D–06/2013 ATUC64/128/256L3/4U 30.9.3 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 76543210 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 759 32142D–06/2013 ATUC64/128/256L3/4U 30.9.4 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 76543210 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 760 32142D–06/2013 ATUC64/128/256L3/4U 30.9.5 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 • WFINTn: Window Mode Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. • SUTINTn: ACn Startup Time Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. • ACINTn: ACn Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 76543210 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 761 32142D–06/2013 ATUC64/128/256L3/4U 30.9.6 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 • WFINTn: Window Mode Interrupt Status 0: No Window Mode Interrupt is pending. 1: Window Mode Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding channel pair operating in window mode generated an interrupt. • SUTINTn: ACn Startup Time Interrupt Status 0: No Startup Time Interrupt is pending. 1: Startup Time Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the startup time of the corresponding AC has passed. • ACINTn: ACn Interrupt Status 0: No Normal Mode Interrupt is pending. 1: Normal Mode Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding channel generated an interrupt. 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 76543210 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 762 32142D–06/2013 ATUC64/128/256L3/4U 30.9.7 Interrupt Status Clear Register Name: ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 76543210 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 763 32142D–06/2013 ATUC64/128/256L3/4U 30.9.8 Test Register Name: TR Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 • ACTESTn: AC Output Override Value If CTRL.ACTEST is set, the ACn output is overridden with the value of ACTESTn. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ACTEST7 ACTEST6 ACTEST5 ACTEST4 ACTEST3 ACTEST2 ACTEST1 ACTEST0 764 32142D–06/2013 ATUC64/128/256L3/4U 30.9.9 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: - • WIMPLn: Window Pair n Implemented 0: Window Pair not implemented. 1: Window Pair implemented. • ACIMPLn: Analog Comparator n Implemented 0: Analog Comparator not implemented. 1: Analog Comparator implemented. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - WIMPL3 WIMPL2 WIMPL1 WIMPL0 15 14 13 12 11 10 9 8 -------- 76543210 ACIMPL7 ACIMPL6 ACIMPL5 ACIMPL4 ACIMPL3 ACIMPL2 ACIMPL1 ACIMPL0 765 32142D–06/2013 ATUC64/128/256L3/4U 30.9.10 Version Register Name: VERSION Access Type: Read-only Offset: 0x34 Reset Value: - • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 766 32142D–06/2013 ATUC64/128/256L3/4U 30.9.11 Window Configuration Register Name: CONFWn Access Type: Read/Write Offset: 0x80,0x84,0x88,0x8C Reset Value: 0x00000000 • WFEN: Window Mode Enable 0: The window mode is disabled. 1: The window mode is enabled. • WEVEN: Window Event Enable 0: Event from awout is disabled. 1: Event from awout is enabled. • WEVSRC: Event Source Selection for Window Mode 000: Event on acwout rising edge. 001: Event on acwout falling edge. 010: Event on awout rising or falling edge. 011: Inside window. 100: Outside window. 101: Measure done. 110-111: Reserved. • WIS: Window Mode Interrupt Settings 00: Window interrupt as soon as the input voltage is inside the window. 01: Window interrupt as soon as the input voltage is outside the window. 10: Window interrupt on toggle of window compare output. 11: Window interrupt when evaluation of input voltage is done. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - - WFEN 15 14 13 12 11 10 9 8 - - - - WEVEN WEVSRC 7654321 0 - - - - - - WIS 767 32142D–06/2013 ATUC64/128/256L3/4U 30.9.12 AC Configuration Register Name: CONFn Access Type: Read/Write Offset: 0xD0,0xD4,0xD8,0xDC,0xE0,0xE4,0xE8,0xEC Reset Value: 0x00000000 • FLEN: Filter Length 000: Filter off. n: Number of samples to be averaged =2n . • HYS: Hysteresis Value 0000: No hysteresis. 1111: Max hysteresis. • EVENN: Event Enable Negative 0: Do not output event when ACOUT is zero. 1: Output event when ACOUT is zero. • EVENP: Event Enable Positive 0: Do not output event when ACOUT is one. 1: Output event when ACOUT is one. • INSELP: Positive Input Select 00: ACPn pin selected. 01: Reserved. 10: Reserved. 11: Reserved. • INSELN: Negative Input Select 00: ACNn pin selected. 01: ACREFN pin selected. 10: Reserved. 11: Reserved. • MODE: Mode 00: Off. 01: Continuous Measurement Mode. 10: User Triggered Single Measurement Mode. 11: Event Triggered Single Measurement Mode. 31 30 29 28 27 26 25 24 - FLEN HYS 23 22 21 20 19 18 17 16 - - - - - - EVENP EVENN 15 14 13 12 11 10 9 8 - - - - INSELP INSELN 7654321 0 - - MODE - - IS 768 32142D–06/2013 ATUC64/128/256L3/4U • IS: Interrupt Settings 00: Comparator interrupt when as VINP > VINN. 01: Comparator interrupt when as VINP < VINN. 10: Comparator interrupt on toggle of Analog Comparator output. 11: Comparator interrupt when comparison of VINP and VINN is done. 769 32142D–06/2013 ATUC64/128/256L3/4U 30.10 Module Configuration The specific configuration for each ACIFB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 30-5. ACIFB Configuration Feature ACIFB Number of channels 8 Table 30-6. ACIFB Clocks Clock Name Description CLK_ACIFB Clock for the ACIFB bus interface GCLK The generic clock used for the ACIFB is GCLK4 Table 30-7. Register Reset Values Register Reset Value VERSION 0x00000202 PARAMETER 0x000F00FF 770 32142D–06/2013 ATUC64/128/256L3/4U 31. Capacitive Touch Module (CAT) Rev: 4.0.0.0 31.1 Features • QTouch® method allows N touch sensors to be implemented using 2N physical pins • QMatrix method allows X by Y matrix of sensors to be implemented using (X+2Y) physical pins • One autonomous QTouch sensor operates without DMA or CPU intervention • All QTouch sensors can operate in DMA-driven mode without CPU intervention • External synchronization to reduce 50 or 60 Hz mains interference • Spread spectrum sensor drive capability 31.2 Overview The Capacitive Touch Module (CAT) senses touch on external capacitive touch sensors. Capacitive touch sensors use no external mechanical components, and therefore demand less maintenance in the user application. The module implements the QTouch method of capturing signals from capacitive touch sensors. The QTouch method is generally suitable for small numbers of sensors since it requires 2 physical pins per sensor. The module also implements the QMatrix method, which is more appropriate for large numbers of sensors since it allows an X by Y matrix of sensors to be implemented using only (X+2Y) physical pins. The module allows methods to function together, so N touch sensors and an X by Y matrix of sensors can be implemented using (2N+X+2Y) physical pins. In addition, the module allows sensors using the QTouch method to be divided into two groups. Each QTouch group can be configured with different properties. This eases the implementation of multiple kinds of controls such as push buttons, wheels, and sliders. All of the QTouch sensors can operate in a DMA-driven mode, known as DMATouch, that allows detection of touch without CPU intervention. The module also implements one autonomous QTouch sensor that is capable of detecting touch without DMA or CPU intervention. This allows proximity or activation detection in low-power sleep modes. 771 32142D–06/2013 ATUC64/128/256L3/4U 31.3 Block Diagram Figure 31-1. CAT Block Diagram 31.4 I/O Lines Description Interface Registers Peripheral Bus Finite State Machine Capacitor Charge and Discharge Sequence Generator Counters CSAn SMP I/O Controller Pins Discharge Current Sources DIS Yn Analog Comparators Peripheral Event System CLK_CAT Analog Comparator Interface SYNC Capacitive Touch Module (CAT) CSBn GCLK_CAT VDIVEN NOTE: Italicized signals and blocks are used only for QMatrix operation Table 31-1. I/O Lines Description Name Description Type CSAn Capacitive sense A line n I/O CSBn Capacitive sense B line n I/O DIS Discharge current control (only used for QMatrix) Analog 772 32142D–06/2013 ATUC64/128/256L3/4U 31.5 Product Dependencies In order to use the CAT module, other parts of the system must be configured correctly, as described below. 31.5.1 I/O Lines The CAT pins may be multiplexed with other peripherals. The user must first program the I/O Controller to give control of the pins to the CAT module. In QMatrix mode, the Y lines must be driven by the CAT and analog comparators sense the voltage on the Y lines. Thus, the CAT (not the Analog Comparator Interface) must be the selected function for the Y lines in the I/O Controller. By writing ones and zeros to bits in the Pin Mode Registers (PINMODEx), most of the CAT pins can be individually selected to implement the QTouch method or the QMatrix method. Each pin has a different name and function depending on whether it is implementing the QTouch method or the QMatrix method. The following table shows the pin names for each method and the bits in the PINMODEx registers which control the selection of the QTouch or QMatrix method. SMP SMP line (only used for QMatrix) Output SYNC Synchronize signal Input VDIVEN Voltage divider enable (only used for QMatrix) Output Table 31-1. I/O Lines Description Name Description Type Table 31-2. Pin Selection Guide CAT Module Pin Name QTouch Method Pin Name QMatrix Method Pin Name Selection Bit in PINMODEx Register CSA0 SNS0 X0 SP0 CSB0 SNSK0 X1 SP0 CSA1 SNS1 Y0 SP1 CSB1 SNSK1 YK0 SP1 CSA2 SNS2 X2 SP2 CSB2 SNSK2 X3 SP2 CSA3 SNS3 Y1 SP3 CSB3 SNSK3 YK1 SP3 CSA4 SNS4 X4 SP4 CSB4 SNSK4 X5 SP4 CSA5 SNS5 Y2 SP5 CSB5 SNSK5 YK2 SP5 CSA6 SNS6 X6 SP6 CSB6 SNSK6 X7 SP6 CSA7 SNS7 Y3 SP7 CSB7 SNSK7 YK3 SP7 CSA8 SNS8 X8 SP8 773 32142D–06/2013 ATUC64/128/256L3/4U 31.5.2 Clocks The clock for the CAT module, CLK_CAT, is generated by the Power Manager (PM). This clock is turned on by default, and can be enabled and disabled in the PM. The user must ensure that CLK_CAT is enabled before using the CAT module. QMatrix operations also require the CAT generic clock, GCLK_CAT. This generic clock is generated by the System Control Interface (SCIF), and is shared between the CAT and the Analog Comparator Interface. The user must ensure that the GCLK_CAT is enabled in the SCIF before using QMatrix functionality in the CAT module. For proper QMatrix operation, the frequency of GCLK_CAT must be less than half the frequency of CLK_CAT. If only QTouch functionality is used, then GCLK_CAT is unnecessary. 31.5.3 Interrupts The CAT interrupt request line is connected to the interrupt controller. Using CAT interrupts requires the interrupt controller to be programmed first. 31.5.4 Peripheral Events The CAT peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 31.5.5 Peripheral Direct Memory Access The CAT module provides handshake capability for a Peripheral DMA Controller. One handshake controls transfers from the Acquired Count Register (ACOUNT) to memory. A second handshake requests burst lengths for each (X,Y) pair to the Matrix Burst Length Register CSB8 SNSK8 X9 SP8 CSA9 SNS9 Y4 SP9 CSB9 SNSK9 YK4 SP9 CSA10 SNS10 X10 SP10 CSB10 SNSK10 X11 SP10 CSA11 SNS11 Y5 SP11 CSB11 SNSK11 YK5 SP11 CSA12 SNS12 X12 SP12 CSB12 SNSK12 X13 SP12 CSA13 SNS13 Y6 SP13 CSB13 SNSK13 YK6 SP13 CSA14 SNS14 X14 SP14 CSB14 SNSK14 X15 SP14 CSA15 SNS15 Y7 SP15 CSB15 SNSK15 YK7 SP15 CSA16 SNS16 X16 SP16 CSB16 SNSK16 X17 SP16 Table 31-2. Pin Selection Guide CAT Module Pin Name QTouch Method Pin Name QMatrix Method Pin Name Selection Bit in PINMODEx Register 774 32142D–06/2013 ATUC64/128/256L3/4U (MBLEN) when using the QMatrix acquisition method. Two additional handshakes support DMATouch by regulating transfers from memory to the DMATouch State Write Register (DMATSW) and from the DMATouch State Read Register (DMATSR) to memory. The Peripheral DMA Controller must be configured properly and enabled in order to perform direct memory access transfers to/from the CAT module. 31.5.6 Analog Comparators When the CAT module is performing QMatrix acquisition, it requires that on-chip analog comparators be used as part of the process. These analog comparators are not controlled directly by the CAT module, but by a separate Analog Comparator (AC) Interface. This interface must be configured properly and enabled before the CAT module is used. This includes configuring the generic clock input for the analog comparators to the proper sampling frequency. The CAT will automatically use the negative peripheral events from the AC Interface on every Y pin in QMatrix mode. When QMatrix acquisition is used the analog comparator corresponding to the selected Y pins must be enabled and converting continuously, using the Y pin as the positive reference and the ACREFN as negative reference. 31.5.7 Debug Operation When an external debugger forces the CPU into debug mode, the CAT continues normal operation. If the CAT is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 31.6 Functional Description 31.6.1 Acquisition Types The CAT module can perform several types of QTouch acquisition from capacitive touch sensors: autonomous QTouch (one sensor only), DMATouch, QTouch group A, and QTouch group B. The CAT module can also perform QMatrix acquisition. Each type of acquisition has an associated set of pin selection and configuration registers that allow a large degree of flexibility. The following schematic diagrams show typical hardware connections for QTouch and QMatrix sensors, respectively: Figure 31-2. CAT Touch Connections AVR32 Chip QTouch Sensor Cs (Sense Capacitor) SNSKn SNSn 775 32142D–06/2013 ATUC64/128/256L3/4U Figure 31-3. CAT Matrix Connections In order to use the autonomous QTouch detection capability, the user must first set up the Autonomous Touch Pin Select Register (ATPINS) and Autonomous/DMA Touch Configuration Registers (ATCFG0 through 3) with appropriate values. The module can then be enabled using the Control Register (CTRL). After the module is enabled, the module will acquire data from the autonomous QTouch sensor and use it to determine whether the sensor is activated. The active/inactive status of the autonomous QTouch sensor is reported in the Status Register (SR), and it is also possible to configure the CAT to generate an interrupt whenever the status changes. The module will continue acquiring autonomous QTouch sensor data and updating autonomous QTouch status until the module is disabled or reset. In order to use the DMATouch capability, it is first necessary to set up the pin mode registers (PINMODE0, PINMODE1, and PINMODE2) so that the desired pins are specified as DMATouch. The Autonomous/DMA Touch Configuration Registers (ATCFG0 through 3) must also be configured with appropriate values. One channel of the Peripheral DMA Controller must be set up to transfer state words from a block of memory to the DMATSW register, and another channel must be set up to transfer state words from the DMATSR register back to the same block of memory. The module can then be enabled using the CTRL register. After the module is enabled, the module will acquire count values from each DMATouch sensor. Once the module has acquired a count value for a sensor, it will use a handshake interface to signal the Peripheral DMA controller to transfer a state word to the DMATSW register. The module will use the count value to update the state word, and then the updated state word will be transferred to the DMATSR register. Another handshake interface will signal the Peripheral DMA controller to transfer the contents of the DMATSR register back to memory. The status of the DMATouch sensors can be determined at any time by reading the DMATouch Sensor Status Register (DMATSS). AVR32 Chip Cs0 (Sense Capacitor) X3 YK0 X6 QMatrix Sensor Array X7 X2 Y0 YK1 Y1 Cs1 (Sense Capacitor) SMP Rsmp1 Rsmp0 VDIVEN DIS Rdis ACREFN Ra Rb NOTE: If the CAT internal current sources will be enabled, the SMP signal and Rsmp resistors should NOT be included in the design. If the CAT internal current sources will NOT be enabled, the DIS signal and Rdis resistor should NOT be included in the design. 776 32142D–06/2013 ATUC64/128/256L3/4U In order to use the QMatrix, QTouch group A, or QTouch group B acquisition capabilities, it is first necessary to set up the pin mode registers (PINMODE0, PINMODE1, and PINMODE2) and configuration registers (MGCFG0, MGCFG1, TGACFG0, TGACFG1, TGBCFG0, and TGBCFG1). The module must then be enabled using the CTRL register. In order to initiate acquisition, it is necessary to perform a write to the Acquisition Initiation and Selection Register (AISR). The specific value written to AISR determines which type of acquisition will be performed: QMatrix, QTouch group A, or QTouch group B. The CPU can initiate acquisition by writing to the AISR. While QMatrix, QTouch group A, or QTouch group B acquisition is in progress, the module collects count values from the sensors and buffers them. Availability of acquired count data is indicated by the Acquisition Ready (ACREADY) bit in the Status Register (SR). The CPU or the Peripheral DMA Controller can then read the acquired counts from the ACOUNT register. Because the CAT module is configured with Peripheral DMA Controller capability that can transfer data from memory to MBLEN and from ACOUNT to memory, the Peripheral DMA Controller can perform long acquisition sequences and store results in memory without CPU intervention. 31.6.2 Prescaler and Charge Length Each QTouch acquisition type (autonomous QTouch, QTouch group A, and QTouch group B) has its own prescaler. Each QTouch prescaler divides down the CLK_CAT clock to an appropriate sampling frequency for its particular acquisition type. Typical frequencies are 1MHz for QTouch acquisition and 4MHz for QMatrix burst timing control. Each QTouch prescaler is controlled by the DIV field in the appropriate Configuration Register 0 (ATCFG0, TGACFG0, or TGBCFG0). The QMatrix burst timing prescaler is controlled by the DIV field in MGCFG0. Each prescaler uses the following formula to generate the sampling clock: Sampling clock = CLK_CAT / (2(DIV+1)) The capacitive sensor charge length, discharge length, and settle length can be determined for each acquisition type using the CHLEN, DILEN, and SELEN fields in Configuration Registers 0 and 1. The lengths are specified in terms of prescaler clocks. In addition, the QMatrix Cx discharge length can be determined using the CXDILEN field in MGCFG2. For QMatrix acquisition, the duration of CHLEN should not be set to the same value as the period of any periodic signal on any other pin. If the duration of CHLEN is the same as the period of a signal on another pin, it is likely that the other signal will significantly affect measurements due to stray capacitive coupling. For example, if a 1 MHz signal is generated on another pin of the chip, then CHLEN should not be 1 microsecond. For the QMatrix method, burst and capture lengths are set for each (X,Y) pair by writing the desired length values to the MBLEN register. The write must be done before each X line can start its acquisition and is indicated by the status bit MBLREQ in the Status Register (SR). A DMA handshake interface is also connected to this status bit to reduce CPU overhead during QMatrix acquisitions. Four burst lengths (BURST0..3) can be written at one time into the MBLEN register. If the current configuration uses Y lines larger than Y3 the register has to be written a second time. The first write to MBLEN specifies the burst length for Y lines 0 to 3 in the BURST0 to BURST3 fields, respectively. The second write specifies the burst length for Y lines 4 to 7 in fields BURST0 to BURST3, respectively, and so on. 777 32142D–06/2013 ATUC64/128/256L3/4U The Y and YK pins remain clamped to ground apart from the specified number of burst pulses, when charge is transferred and captured into the sampling capacitor. 31.6.3 Capacitive Count Acquisition For the QMatrix, QTouch group A, and QTouch group B types of acquisition, the module acquires count values from the sensors, buffers them, and makes them available for reading in the ACOUNT register. Further processing of the count values must be performed by the CPU. When the module performs QMatrix acquisition using multiple Y lines, it starts the capture for each Y line at the appropriate time in the burst sequence so that all captures finish simultaneously. For example, suppose that an acquisition is performed on Y0 and Y1 with BURST0=53 and BURST1=60. The module will first toggle the X line 7 times while capturing on Y1 while Y0 and YK0 are clamped to ground. The module will then toggle the X line 53 times while capturing on both Y1 and Y0. 31.6.4 Autonomous QTouch and DMATouch For autonomous QTouch and DMATouch, a complete detection algorithm is implemented within the CAT module. The additional parameters needed to control the detection algorithm must be specified by the user in the ATCFG2 and ATCFG3 registers. Autonomous QTouch and DMATouch sensitivity and out-of-touch sensitivity can be adjusted with the SENSE and OUTSENS fields, respectively, in ATCFG2. Each field accepts values from one to 255 where 255 is the least sensitive setting. The value in the OUTSENS field should be smaller than the value in the SENSE field. To avoid false positives a detect integration filtering technique can be used. The number of successive detects required is specified in the FILTER field of the ATCFG2 register. To compensate for changes in capacitance the CAT can recalibrate the autonomous QTouch sensor periodically. The timing of this calibration is done with the NDRIFT and PDRIFT fields in the Configuration register, ATCFG3. It is recommended that the PDRIFT value is smaller than the NDRIFT value. The autonomous QTouch sensor and DMATouch sensors will also recalibrate if the count value goes too far positive beyond a threshold. This positive recalibration threshold is specified by the PTHR field in the ATCFG3 register. The following block diagram shows the sequence of acquisition and processing operations used by the CAT module. The AISR written bit is internal and not visible in the user interface. 778 32142D–06/2013 ATUC64/128/256L3/4U Figure 31-4. CAT Acquisition and Processing Sequence 31.6.5 Spread Spectrum Sensor Drive To reduce electromagnetic compatibility issues, the capacitive sensors can be driven with a spread spectrum signal. To enable spread spectrum drive for a specific acquisition type, the user must write a one to the SPREAD bit in the appropriate Configuration Register 1 (MGCFG1, ATCFG1, TGACFG1, or TGBCFG1). During spread spectrum operation, the length of each pulse within a burst is varied in a deterministic pattern, so that the exact same burst pattern is used for a specific burst length. The maximum spread is determined by the MAXDEV field in the Spread Spectrum Configuration Register (SSCFG) register. The prescaler divisor is varied in a sawtooth pattern from (2(DIV+1))-MAXDEV to (2(DIV+1))+MAXDEV and then back to (2(DIV+1))-MAXDEV. For example, if DIV is 2 and MAXDEV is 3, the prescaler divisor will have the following sequence: 6, 7, 8, Idle Acquire autonomous touch count Acquire counts Update autonomous touch detection algorithm Wait for all acquired counts to be transferred AISR written flag set? No Yes Clear AISR written flag No Yes Autonomous touch enabled (ATEN)? 779 32142D–06/2013 ATUC64/128/256L3/4U 9, 3, 4, 5, 6, 7, 8, 9, 3, 4, etc. MAXDEV must not exceed the value of (2(DIV+1)), or undefined behavior will occur. 31.6.6 Synchronization To prevent interference from the 50 or 60 Hz mains line the CAT can trigger acquisition on the SYNC signal. The SYNC signal should be derived from the mains line. The acquisition will trigger on a falling edge of this signal. To enable synchronization for a specific acquisition type, the user must write a one to the SYNC bit in the appropriate Configuration Register 1 (MGCFG1, ATCFG1, TGACFG1, or TGBCFG1). For QMatrix acquisition, all X lines must be sampled at a specific phase of the noise signal for the synchronization to be effective. This can be accomplished by the synchronization timer, which is enabled by writing a non-zero value to the SYNCTIM field in the MGCFG2 register. This ensures that the start of the acquisition of each X line is spaced at regular intervals, defined by the SYNCTIM field. 31.6.7 Resistive Drive By default, the CAT pins are driven with normal I/O drive properties. Some of the CSA and CSB pins can optionally drive with a 1k output resistance for improved EMC. The pins that have this capability are listed in the Module Configuration section. 31.6.8 Discharge Current Sources The device integrates discharge current sources, which can be used to discharge the sampling capacitors during the QMatrix measurement phase. The discharge current sources are enabled by writing the GLEN bit in the Discharge Current Source (DICS) register to one. This enables an internal reference voltage, which can be either the internal 1.1V band gap voltage or VDDIO/3, as selected by the INTVREFSEL bit in the DICS register. If the DICS.INTREFSEL bit is one, the reference voltage is applied across an internal resistor, Rint. Otherwise, the voltage is applied to the DIS pin, and an external reference resistor must be connected between DIS and ground. The nominal discharge current is given by the following formula, where Vref is the reference voltage, Rref is the value of the reference resistor, trim is the value written to the DICS.TRIM field, and k is a constant of proportionality: I = (Vref/Rref)*(1+(k*trim)) The values for the internal reference resistor, Rint, and the constant, k, may be found in the Electrical Characteristics section. The nominal discharge current may be programmed between 2 and 20 µA. The reference current can be fine-tuned by adjusting the trim value in the DICS.TRIM field. The reference current is mirrored to each Y-pin if the corresponding bit is written to one in the DICS.SOURCES field. 31.6.9 Voltage Divider Enable (VDIVEN) Capability In many QMatrix applications, the sense capacitors will be charged to 50 mV or more and the negative reference pin (ACREFN) of the analog comparators can be tied directly to ground. In that case, the relatively small input offset voltage of the comparators will not cause acquisition problems. However, in certain specialized QMatrix applications such as interpolated touch screens, it may be desirable for the sense capacitors to be charged to less than 25 mV. When such small voltages are used on the sense capacitors, the input offset voltage of the comparators becomes an issue and can cause QMatrix acquisition problems. 780 32142D–06/2013 ATUC64/128/256L3/4U Problems with QMatrix acquisition of small sense capacitor voltages can be solved by connecting the negative reference pin (ACREFN) to a voltage divider that produces a small positive voltage (20 mV, typically) to cancel any negative input offset voltage. With a 3.3V supply, recommended values for the voltage divider are Ra (resistor from positive supply to ACREFN) of 8200 ohm and Rb (resistor from ACREFN to ground) of 50 ohm. These recommended values will produce 20 mV on the ACREFN pin, which should generally be enough to compensate for the worst-case negative input offset of the analog comparators. Unfortunately, such a voltage divider constantly draws a small current from the power supply, reducing battery life in portable applications. In order to prevent this constant power drain, the CAT module provides a voltage divider enable pin (VDIVEN) that can be used for driving the voltage divider. The VDIVEN pin provides power to the voltage divider only when the comparators are actually performing QMatrix comparisons. When the comparators are inactive, the VDIVEN output is zero. This minimizes the power consumed by the voltage divider. 781 32142D–06/2013 ATUC64/128/256L3/4U 31.7 User Interface Table 31-3. CAT Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CTRL Read/Write 0x00000000 0x04 Autonomous Touch Pin Selection Register ATPINS Read/Write 0x00000000 0x08 Pin Mode Register 0 PINMODE0 Read/Write 0x00000000 0x0C Pin Mode Register 1 PINMODE1 Read/Write 0x00000000 0x10 Autonomous/DMA Touch Configuration Register 0 ATCFG0 Read/Write 0x00000000 0x14 Autonomous/DMA Touch Configuration Register 1 ATCFG1 Read/Write 0x00000000 0x18 Autonomous/DMA Touch Configuration Register 2 ATCFG2 Read/Write 0x00000000 0x1C Autonomous/DMA Touch Configuration Register 3 ATCFG3 Read/Write 0x00000000 0x20 Touch Group A Configuration Register 0 TGACFG0 Read/Write 0x00000000 0x24 Touch Group A Configuration Register 1 TGACFG1 Read/Write 0x00000000 0x28 Touch Group B Configuration Register 0 TGBCFG0 Read/Write 0x00000000 0x2C Touch Group B Configuration Register 1 TGBCFG1 Read/Write 0x00000000 0x30 Matrix Group Configuration Register 0 MGCFG0 Read/Write 0x00000000 0x34 Matrix Group Configuration Register 1 MGCFG1 Read/Write 0x00000000 0x38 Matrix Group Configuration Register 2 MGCFG2 Read/Write 0x00000000 0x3C Status Register SR Read-only 0x00000000 0x40 Status Clear Register SCR Write-only - 0x44 Interrupt Enable Register IER Write-only - 0x48 Interrupt Disable Register IDR Write-only - 0x4C Interrupt Mask Register IMR Read-only 0x00000000 0x50 Acquisition Initiation and Selection Register AISR Read/Write 0x00000000 0x54 Acquired Count Register ACOUNT Read-only 0x00000000 0x58 Matrix Burst Length Register MBLEN Write-only - 0x5C Discharge Current Source Register DICS Read/Write 0x00000000 0x60 Spread Spectrum Configuration Register SSCFG Read/Write 0x00000000 0x64 CSA Resistor Control Register CSARES Read/Write 0x00000000 0x68 CSB Resistor Control Register CSBRES Read/Write 0x00000000 0x6C Autonomous Touch Base Count Register ATBASE Read-only 0x00000000 0x70 Autonomous Touch Current Count Register ATCURR Read-only 0x00000000 0x74 Pin Mode Register 2 PINMODE2 Read/Write 0x00000000 0x78 DMATouch State Write Register DMATSW Write-only 0x00000000 0x7C DMATouch State Read Register DMATSR Read-only 0x00000000 0x80 Analog Comparator Shift Offset Register 0 ACSHI0 Read/Write 0x00000000 0x84 Analog Comparator Shift Offset Register 1 ACSHI1 Read/Write 0x00000000 0x88 Analog Comparator Shift Offset Register 2 ACSHI2 Read/Write 0x00000000 782 32142D–06/2013 ATUC64/128/256L3/4U Note: 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter. 0x8C Analog Comparator Shift Offset Register 3 ACSHI3 Read/Write 0x00000000 0x90 Analog Comparator Shift Offset Register 4 ACSHI4 Read/Write 0x00000000 0x94 Analog Comparator Shift Offset Register 5 ACSHI5 Read/Write 0x00000000 0x98 Analog Comparator Shift Offset Register 6 ACSHI6 Read/Write 0x00000000 0x9C Analog Comparator Shift Offset Register 7 ACSHI7 Read/Write 0x00000000 0xA0 DMATouch Sensor Status Register DMATSS Read-only 0x00000000 0xF8 Parameter Register PARAMETER Read-only -(1) 0xFC Version Register VERSION Read-only -(1) Table 31-3. CAT Register Memory Map Offset Register Register Name Access Reset 783 32142D–06/2013 ATUC64/128/256L3/4U 31.7.1 Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • SWRST: Software reset Writing a zero to this bit has no effect. Writing a one to this bit resets the module. The module will be disabled after the reset. This bit always reads as zero. • EN: Module enable 0: Module is disabled. 1: Module is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 SWRST - - - - - - EN 784 32142D–06/2013 ATUC64/128/256L3/4U 31.7.2 Autonomous Touch Pin Selection Register Name: ATPINS Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • ATEN: Autonomous Touch Enable 0: Autonomous QTouch acquisition and detection is disabled. 1: Autonomous QTouch acquisition and detection is enabled using the sense pair specified in ATSP. • ATSP: Autonomous Touch Sense Pair Selects the sense pair that will be used by the autonomous QTouch sensor. A value of n will select sense pair n (CSAn and CSBn pins). 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - - - ATEN 76543210 - - - ATSP 785 32142D–06/2013 ATUC64/128/256L3/4U 31.7.3 Pin Mode Registers 0, 1, and 2 Name: PINMODE0, PINMODE1, and PINMODE2 Access Type: Read/Write Offset: 0x08, 0x0C, 0x74 Reset Value: 0x00000000 • SP: Sense Pair Mode Selection Each SP[n] bit determines the operation mode of sense pair n (CSAn and CSBn pins). The (PINMODE2.SP[n] PINMODE1.SP[n] PINMODE0.SP[n]) bits have the following definitions: 000: Sense pair n disabled. 001: Sense pair n is assigned to QTouch Group A. 010: Sense pair n is assigned to QTouch Group B. 011: Sense pair n is assigned to the QMatrix Group. 100: Sense pair n is assigned to the DMATouch Group. 101: Reserved. 110: Reserved. 111: Reserved. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - SP[16] 15 14 13 12 11 10 9 8 SP[15:8] 76543210 SP[7:0] 786 32142D–06/2013 ATUC64/128/256L3/4U 31.7.4 Autonomous/DMA Touch Configuration Register 0 Name: ATCFG0 Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.The prescaler uses the following formula to generate the sampling clock: Sampling clock = CLK_CAT / (2(DIV+1)) • CHLEN: Charge Length For the autonomous QTouch sensor and DMATouch sensors, specifies how many sample clock cycles should be used for transferring charge to the sense capacitor. • SELEN: Settle Length For the autonomous QTouch sensor and DMATouch sensors, specifies how many sample clock cycles should be used for settling after charge transfer. 31 30 29 28 27 26 25 24 DIV[15:8] 23 22 21 20 19 18 17 16 DIV[7:0] 15 14 13 12 11 10 9 8 CHLEN 76543210 SELEN 787 32142D–06/2013 ATUC64/128/256L3/4U 31.7.5 Autonomous/DMA Touch Configuration Register 1 Name: ATCFG1 Access Type: Read/Write Offset: 0x14 Reset Value: 0x00000000 • DISHIFT: Discharge Shift For the autonomous QTouch sensor and DMATouch sensors, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time. • SYNC: Sync Pin For the autonomous QTouch sensor and DMATouch sensors, specifies that acquisition shall begin when a falling edge is received on the SYNC line. • SPREAD: Spread Spectrum Sensor Drive For the autonomous QTouch sensor and DMATouch sensors, specifies that spread spectrum sensor drive shall be used. • DILEN: Discharge Length For the autonomous QTouch sensor and DMATouch sensors, specifies how many sample clock cycles the CAT should use to discharge the capacitors before charging them. • MAX: Maximum Count For the autonomous QTouch sensor and DMATouch sensors, specifies how many counts the maximum acquisition should be. 31 30 29 28 27 26 25 24 - DISHIFT - SYNC SPREAD 23 22 21 20 19 18 17 16 DILEN 15 14 13 12 11 10 9 8 MAX[15:8] 76543210 MAX[7:0] 788 32142D–06/2013 ATUC64/128/256L3/4U 31.7.6 Autonomous/DMA Touch Configuration Register 2 Name: ATCFG2 Access Type: Read/Write Offset: 0x18 Reset Value: 0x00000000 • FILTER: Autonomous Touch Filter Setting For the autonomous QTouch sensor and DMATouch sensors, specifies how many positive detects in a row the CAT needs to have on the sensor before reporting it as a touch. A FILTER value of 0 is not allowed and will result in undefined behavior. • OUTSENS: Out-of-Touch Sensitivity For the autonomous QTouch sensor and DMATouch sensors, specifies how sensitive the out-of-touch detector should be. • SENSE: Sensitivity For the autonomous QTouch sensor and DMATouch sensors, specifies how sensitive the touch detector should be. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - FILTER 15 14 13 12 11 10 9 8 OUTSENS 76543210 SENSE 789 32142D–06/2013 ATUC64/128/256L3/4U 31.7.7 Autonomous/DMA Touch Configuration Register 3 Name: ATCFG3 Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 • PTHR: Positive Recalibration Threshold For the autonomous QTouch sensor and DMATouch sensors, specifies how far a sensor’s signal must move in a positive direction from the reference in order to cause a recalibration. • PDRIFT: Positive Drift Compensation For the autonomous QTouch sensor and DMATouch sensors, specifies how often a positive drift compensation should be performed. When this field is zero, positive drift compensation will never be performed. When this field is non-zero, the positive drift compensation time interval is given by the following formula: Tpdrift = PDRIFT * 65536 * (sample clock period) • NDRIFT: Negative Drift Compensation For the autonomous QTouch sensor and DMATouch sensors, specifies how often a negative drift compensation should be performed. When this field is zero, negative drift compensation will never be performed. When this field is non-zero, the negative drift compensation time interval is given by the following formula: Tndrift = NDRIFT * 65536 * (sample clock period) With the typical sample clock frequency of 1 MHz, PDRIFT and NDRIFT can be set from 0.066 seconds to 16.7 seconds with 0.066 second resolution. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 PTHR 15 14 13 12 11 10 9 8 PDRIFT 76543210 NDRIFT 790 32142D–06/2013 ATUC64/128/256L3/4U 31.7.8 Touch Group x Configuration Register 0 Name: TGxCFG0 Access Type: Read/Write Offset: 0x20, 0x28 Reset Value: 0x00000000 • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.The prescaler uses the following formula to generate the sampling clock: Sampling clock = CLK_CAT / (2(DIV+1)) • CHLEN: Charge Length For the QTouch method, specifies how many sample clock cycles should be used for transferring charge to the sense capacitor. • SELEN: Settle Length For the QTouch method, specifies how many sample clock cycles should be used for settling after charge transfer. 31 30 29 28 27 26 25 24 DIV[15:8] 23 22 21 20 19 18 17 16 DIV[7:0] 15 14 13 12 11 10 9 8 CHLEN 76543210 SELEN 791 32142D–06/2013 ATUC64/128/256L3/4U 31.7.9 Touch Group x Configuration Register 1 Name: TGxCFG1 Access Type: Read/Write Offset: 0x24, 0x2C Reset Value: 0x00000000 • DISHIFT: Discharge Shift For the sensors in QTouch group x, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time. • SYNC: Sync Pin For sensors in QTouch group x, specifies that acquisition shall begin when a falling edge is received on the SYNC line. • SPREAD: Spread Spectrum Sensor Drive For sensors in QTouch group x, specifies that spread spectrum sensor drive shall be used. • DILEN: Discharge Length For sensors in QTouch group x, specifies how many clock cycles the CAT should use to discharge the capacitors before charging them. • MAX: Touch Maximum Count For sensors in QTouch group x, specifies how many counts the maximum acquisition should be. 31 30 29 28 27 26 25 24 - - DISHIFT - - SYNC SPREAD 23 22 21 20 19 18 17 16 DILEN 15 14 13 12 11 10 9 8 MAX[15:8] 76543210 MAX[7:0] 792 32142D–06/2013 ATUC64/128/256L3/4U 31.7.10 Matrix Group Configuration Register 0 Name: MGCFG0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 4 MHz to produce the burst timing clock.The prescaler uses the following formula to generate the burst timing clock: Burst timing clock = CLK_CAT / (2(DIV+1)) • CHLEN: Charge Length For QMatrix sensors, specifies how many burst prescaler clock cycles should be used for transferring charge to the sense capacitor. • SELEN: Settle Length For QMatrix sensors, specifies how many burst prescaler clock cycles should be used for settling after charge transfer. 31 30 29 28 27 26 25 24 DIV[15:8] 23 22 21 20 19 18 17 16 DIV[7:0] 15 14 13 12 11 10 9 8 CHLEN 76543210 SELEN 793 32142D–06/2013 ATUC64/128/256L3/4U 31.7.11 Matrix Group Configuration Register 1 Name: MGCFG1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 • DISHIFT: Discharge Shift For QMatrix sensors, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time. • SYNC: Sync Pin For QMatrix sensors, specifies that acquisition shall begin when a falling edge is received on the SYNC line. • SPREAD: Spread Spectrum Sensor Drive For QMatrix sensors, specifies that spread spectrum sensor drive shall be used. • DILEN: Discharge Length For QMatrix sensors, specifies how many burst prescaler clock cycles the CAT should use to discharge the capacitors at the beginning of a burst sequence. • MAX: Maximum Count For QMatrix sensors, specifies how many counts the maximum acquisition should be. 31 30 29 28 27 26 25 24 - DISHIFT - SYNC SPREAD 23 22 21 20 19 18 17 16 DILEN 15 14 13 12 11 10 9 8 MAX[15:8] 76543210 MAX[7:0] 794 32142D–06/2013 ATUC64/128/256L3/4U 31.7.12 Matrix Group Configuration Register 2 Name: MGCFG2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 • ACCTRL: Analog Comparator Control When written to one, allows the CAT to disable the analog comparators when they are not needed. When written to zero, the analog comparators are always enabled. • CONSEN: Consensus Filter Length For QMatrix sensors, specifies that discharge will be terminated when CONSEN out of the most recent 5 comparator samples are positive. For example, a value of 3 in the CONSEN field will terminate discharge when 3 out of the most recent 5 comparator samples are positive. When CONSEN has the default value of 0, discharge will be terminated immediately when the comparator output goes positive. • CXDILEN: Cx Capacitor Discharge Length For QMatrix sensors, specifies how many burst prescaler clock cycles the CAT should use to discharge the Cx capacitor at the end of each burst cycle. • SYNCTIM: Sync Time Interval When non-zero, determines the number of prescaled clock cycles between the start of the acquisition on each X line for QMatrix acquisition. 31 30 29 28 27 26 25 24 ACCTRL CONSEN - 23 22 21 20 19 18 17 16 CXDILEN 15 14 13 12 11 10 9 8 - SYNCTIM[11:8] 76543210 SYNCTIM[7:0] 795 32142D–06/2013 ATUC64/128/256L3/4U 31.7.13 Status Register Name: SR Access Type: Read-only Offset: 0x3C Reset Value: 0x00000000 • DMATSC: DMATouch Sensor State Change 0: No change in the DMATSS register. 1: One or more bits have changed in the DMATSS register. • DMATSR: DMATouch State Read Register Ready 0: A new state word is not available in the DMATSR register. 1: A new state word is available in the DMATSR register. • DMATSW: DMATouch State Write Register Request 0: The DMATouch algorithm is not requesting that a state word be written to the DMATSW register. 1: The DMATouch algorithm is requesting that a state word be written to the DMATSW register. • ACQDONE: Acquisition Done 0: Acquisition is not done (still in progress). 1: Acquisition is complete. • ACREADY: Acquired Count Data is Ready 0: Acquired count data is not available in the ACOUNT register. 1: Acquired count data is available in the ACOUNT register. • MBLREQ: Matrix Burst Length Required 0: The QMatrix acquisition does not require any burst lengths. 1: The QMatrix acquisition requires burst lengths for the current X line. • ATSTATE: Autonomous Touch Sensor State 0: The autonomous QTouch sensor is not active. 1: The autonomous QTouch sensor is active. • ATSC: Autonomous Touch Sensor Status Interrupt 0: No status change in the autonomous QTouch sensor. 1: Status change in the autonomous QTouch sensor. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 DMATSC - - - - - DMATSR DMATSW 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 76543210 - - - MBLREQ ATSTATE ATSC ATCAL ENABLED 796 32142D–06/2013 ATUC64/128/256L3/4U • ATCAL: Autonomous Touch Calibration Ongoing 0: The autonomous QTouch sensor is not calibrating. 1: The autonomous QTouch sensor is calibrating. • ENABLED: Module Enabled 0: The module is disabled. 1: The module is enabled. 797 32142D–06/2013 ATUC64/128/256L3/4U 31.7.14 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x40 Reset Value: - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 76543210 - - - - - ATSC ATCAL - 798 32142D–06/2013 ATUC64/128/256L3/4U 31.7.15 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x44 Reset Value: - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 76543210 - - - - - ATSC ATCAL - 799 32142D–06/2013 ATUC64/128/256L3/4U 31.7.16 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x48 Reset Value: - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 76543210 - - - - - ATSC ATCAL - 800 32142D–06/2013 ATUC64/128/256L3/4U 31.7.17 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 76543210 - - - - - ATSC ATCAL - 801 32142D–06/2013 ATUC64/128/256L3/4U 31.7.18 Acquisition Initiation and Selection Register Name: AISR Access Type: Read/Write Offset: 0x50 Reset Value: 0x00000000 • ACQSEL: Acquisition Type Selection A write to this register initiates an acquisition of the following type: 00: QTouch Group A. 01: QTouch Group B. 10: QMatrix Group. 11: Undefined behavior. A read of this register will return the value that was previously written. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 - 76543210 - ACQSEL 802 32142D–06/2013 ATUC64/128/256L3/4U 31.7.19 Acquired Count Register Name: ACOUNT Access Type: Read-only Offset: 0x54 Reset Value: 0x00000000 • Y: Y index The Y index (for QMatrix method) associated with this count value. • SPORX: Sensor pair or X index The sensor pair index (for QTouch method) or X index (for QMatrix method) associated with this count value. • COUNT: Count value The signal (number of counts) acquired on the channel specified in the SPORX and Y fields. When multiple acquired count values are read from a QTouch acquisition, the Y field will always be 0 and the SPORX value will increase monotonically. For example, suppose a QTouch acquisition is performed using sensor pairs SP1, SP4, and SP9. The first count read will have SPORX=1, the second read will have SPORX=4, and the third read will have SPORX=9. When multiple acquired count values are read from a QMatrix acquisition, the SPORX value will stay the same while Y increases monotonically through all Y values in the group. Then SPORX will increase to the next X value in the group. For example, a QMatrix acquisition with X=2,3 and Y=4,7 would provide count values in the following order: X=2 and Y=4, then X=2 and Y=7, then X=3 and Y=4, and finally X=3 and Y=7. 31 30 29 28 27 26 25 24 Y 23 22 21 20 19 18 17 16 SPORX 15 14 13 12 11 10 9 8 COUNT[15:8] 76543210 COUNT[7:0] 803 32142D–06/2013 ATUC64/128/256L3/4U 31.7.20 Matrix Burst Length Register Name: MBLEN Access Type: Write-only Offset: 0x58 Reset Value: - • BURSTx: Burst Length x For QMatrix sensors, specifies how many times the switching sequence should be repeated before acquisition begins for each channel. Each count in the BURSTx field specifies 1 repeat of the switching sequence, so the actual burst length will be BURST. Before doing a QMatrix acquisition on one X line this register has to be written with the burst values for the current XY pairs. For each X line this register needs to be programmed with all the Y values. If Y values larger than 3 are used the register has to be written several times in order to specify all burst lengths. The Status Register bit MBLREQ is set to 1 when the CAT is waiting for values to be written into this register. 31 30 29 28 27 26 25 24 BURST0 23 22 21 20 19 18 17 16 BURST1 15 14 13 12 11 10 9 8 BURST2 76543210 BURST3 804 32142D–06/2013 ATUC64/128/256L3/4U 31.7.21 Discharge Current Source Register Name: DICS Access Type: Read/Write Offset: 0x5C Reset Value: 0x00000000 • FSOURCES: Force Discharge Current Sources When FSOURCES[n] is 0, the corresponding discharge current source behavior depends on SOURCES[n]. When FSOURCES[n] is 1, the corresponding discharge current source is forced to be enabled continuously. This is useful for testing or debugging but should not be done during normal acquisition. • GLEN: Global Enable 0: The current source module is globally disabled. 1: The current source module is globally enabled. • INTVREFSEL: Internal Voltage Reference Select 0: The voltage for the reference resistor is generated from the internal band gap circuit. 1: The voltage for the reference resistor is VDDIO/3. • INTREFSEL: Internal Reference Select 0: The reference current flows through an external resistor on the DIS pin. 1: The reference current flows through the internal reference resistor. • TRIM: Reference Current Trimming This field is used to trim the discharge current. 0x00 corresponds to the minimum current value, and 0x1F corresponds to the maximum current value. • SOURCES: Enable Discharge Current Sources When SOURCES[n] is 0, the corresponding discharge current source is disabled. When SOURCES[n] is 1, the corresponding discharge current source is enabled at appropriate times during acquisition. 31 30 29 28 27 26 25 24 FSOURCES[7:0] 23 22 21 20 19 18 17 16 GLEN - - - - - INTVREFSEL INTREFSEL 15 14 13 12 11 10 9 8 - - - TRIM 76543210 SOURCES[7:0] 805 32142D–06/2013 ATUC64/128/256L3/4U 31.7.22 Spread Spectrum Configuration Register Name: SSCFG Access Type: Read/Write Offset: 0x60 Reset Value: 0x00000000 • MAXDEV: Maximum Deviation When spread spectrum burst is enabled, MAXDEV indicates the maximum number of prescaled clock cycles the burst pulse will be extended or shortened. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 MAXDEV 806 32142D–06/2013 ATUC64/128/256L3/4U 31.7.23 CSA Resistor Control Register Name: CSARES Access Type: Read/Write Offset: 0x64 Reset Value: 0x00000000 • RES: Resistive Drive Enable When RES[n] is 0, CSA[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSA[n] has a nominal output resistance of 1kOhm during the burst phase. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - RES[16] 15 14 13 12 11 10 9 8 RES[15:8] 76543210 RES[7:0] 807 32142D–06/2013 ATUC64/128/256L3/4U 31.7.24 CSB Resistor Control Register Name: CSBRES Access Type: Read/Write Offset: 0x68 Reset Value: 0x00000000 • RES: Resistive Drive Enable When RES[n] is 0, CSB[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSB[n] has a nominal output resistance of 1kOhm during the burst phase. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - RES[16] 15 14 13 12 11 10 9 8 RES[15:8] 76543210 RES[7:0] 808 32142D–06/2013 ATUC64/128/256L3/4U 31.7.25 Autonomous Touch Base Count Register Name: ATBASE Access Type: Read-only Offset: 0x6C Reset Value: 0x00000000 • COUNT: Count value The base count currently stored by the autonomous touch sensor. This is useful for autonomous touch debugging purposes. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 COUNT[15:8] 76543210 COUNT[7:0] 809 32142D–06/2013 ATUC64/128/256L3/4U 31.7.26 Autonomous Touch Current Count Register Name: ATCURR Access Type: Read-only Offset: 0x70 Reset Value: 0x00000000 • COUNT: Count value The current count acquired by the autonomous touch sensor. This is useful for autonomous touch debugging purposes. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 COUNT[15:8] 76543210 COUNT[7:0] 810 32142D–06/2013 ATUC64/128/256L3/4U 31.7.27 DMATouch State Write Register Name: DMATSW Access Type: Write-only Offset: 0x78 Reset Value: 0x00000000 • NOTINCAL: Not in Calibration Mode 0: Calibration should be performed on the next iteration of the DMATouch algorithm. 1: Calibration should not be performed on the next iteration of the DMATouch algorithm. • DETCNT: Detection Count This count value is updated and used by the DMATouch algorithm in order to detect when a button has been pushed. • BASECNT: Base Count This count value represents the average expected acquired count when the sensor/button is not pushed. 31 30 29 28 27 26 25 24 - - - - - - - NOTINCAL 23 22 21 20 19 18 17 16 DETCNT[23:16] 15 14 13 12 11 10 9 8 BASECNT[15:8] 76543210 BASECNT[7:0] 811 32142D–06/2013 ATUC64/128/256L3/4U 31.7.28 DMA Touch State Read Register Name: DMATSR Access Type: Read/Write Offset: 0x7C Reset Value: 0x00000000 • NOTINCAL: Not in Calibration Mode 0: Calibration should be performed on the next iteration of the DMATouch algorithm. 1: Calibration should not be performed on the next iteration of the DMATouch algorithm. • DETCNT: Detection Count This count value is updated and used by the DMATouch algorithm in order to detect when a button has been pushed. • BASECNT: Base Count This count value represents the average expected acquired count when the sensor/button is not pushed. 31 30 29 28 27 26 25 24 - - - - - - - NOTINCAL 23 22 21 20 19 18 17 16 DETCNT[23:16] 15 14 13 12 11 10 9 8 BASECNT[15:8] 76543210 BASECNT[7:0] 812 32142D–06/2013 ATUC64/128/256L3/4U 31.7.29 Analog Comparator Shift Offset Register x Name: ACSHIx Access Type: Read/Write Offset: 0x80, 0x84, 0x88, 0x8C, 0x90, 0x94, 0x98, and 0x9C Reset Value: 0x00000000 • SHIVAL: Shift Offset Value Specifies the amount to shift the count value from each comparator. This allows the offset of each comparator to be compensated. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 - SHIVAL[11:8] 76543210 SHIVAL[7:0] 813 32142D–06/2013 ATUC64/128/256L3/4U 31.7.30 DMATouch Sensor Status Register Name: DMATSS Access Type: Read-only Offset: 0xA0 Reset Value: 0x00000000 • SS: Sensor Status 0: The DMATouch sensor is not active, i.e. the button is currently not pushed. 1: The DMATouch sensor is active, i.e. the button is currently pushed. 31 30 29 28 27 26 25 24 SS[31:24] 23 22 21 20 19 18 17 16 SS[23:16] 15 14 13 12 11 10 9 8 SS[15:8] 76543210 SS[7:0] 814 32142D–06/2013 ATUC64/128/256L3/4U 31.7.31 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0xF8 Reset Value: - • SP[n]: Sensor pair implemented 0: The corresponding sensor pair is not implemented 1: The corresponding sensor pair is implemented. 31 30 29 28 27 26 25 24 SP[31:24] 23 22 21 20 19 18 17 16 SP[23:16] 15 14 13 12 11 10 9 8 SP[15:8] 76543210 SP[7:0] 815 32142D–06/2013 ATUC64/128/256L3/4U 31.7.32 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 816 32142D–06/2013 ATUC64/128/256L3/4U 31.8 Module Configuration The specific configuration the CAT module is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. 31.8.1 Resistive Drive By default, the CAT pins are driven with normal I/O drive properties. Some of the CSA and CSB pins can optionally drive with a 1k output resistance for improved EMC. To enable resistive drive on a pin, the user must write a one to the corresponding bit in the CSA Resistor Control Register (CSARES) or CSB Resistor Control Register (CSBRES) register. Table 31-4. CAT Configuration Feature CAT Number of touch sensors/Size of matrix Allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. Table 31-5. CAT Clocks Clock Name Description CLK_CAT Clock for the CAT bus interface GCLK The generic clock used for the CAT is GCLK4 Table 31-6. Register Reset Values Register Reset Value VERSION 0x00000400 PARAMETER 0x0001FFFF 817 32142D–06/2013 ATUC64/128/256L3/4U 32. Glue Logic Controller (GLOC) Rev: 1.0.0.0 32.1 Features • Glue logic for general purpose PCB design • Programmable lookup table • Up to four inputs supported per lookup table • Optional filtering of output 32.2 Overview The Glue Logic Controller (GLOC) contains programmable logic which can be connected to the device pins. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. The GLOC consists of a number of lookup table (LUT) units. Each LUT can generate an output as a user programmable logic expression with four inputs. Inputs can be individually masked. The output can be combinatorially generated from the inputs, or filtered to remove spikes. 32.3 Block Diagram Figure 32-1. GLOC Block Diagram PERIPHERAL BUS TRUTH FILTER OUT[0] ... OUT[n] FILTEN IN[3:0] … IN[(4n+3):4n] AEN CLK_GLOC GCLK 818 32142D–06/2013 ATUC64/128/256L3/4U 32.4 I/O Lines Description Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to IN[4n+3] and OUTn. 32.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 32.5.1 I/O Lines The pins used for interfacing the GLOC may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired GLOC pins to their peripheral function. If I/O lines of the GLOC are not used by the application, they can be used for other purposes by the I/O Controller. It is only required to enable the GLOC inputs and outputs actually in use. Pullups for pins configured to be used by the GLOC will be disabled. 32.5.2 Clocks The clock for the GLOC bus interface (CLK_GLOC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the GLOC before disabling the clock, to avoid freezing the module in an undefined state. Additionally, the GLOC depends on a dedicated Generic Clock (GCLK). The GCLK can be set to a wide range of frequencies and clock sources, and must be enabled by the System Control Interface (SCIF) before the GLOC filter can be used. 32.5.3 Debug Operation When an external debugger forces the CPU into debug mode, the GLOC continues normal operation. 32.6 Functional Description 32.6.1 Enabling the Lookup Table Inputs Since the inputs to each lookup table (LUT) unit can be multiplexed with other peripherals, each input must be explicitly enabled by writing a one to the corresponding enable bit (AEN) in the corresponding Control Register (CR). If no inputs are enabled, the output OUTn will be the least significant bit in the TRUTHn register. Table 32-1. I/O Lines Description Pin Name Pin Description Type IN0-INm Inputs to lookup tables Input OUT0-OUTn Output from lookup tables Output 819 32142D–06/2013 ATUC64/128/256L3/4U 32.6.2 Configuring the Lookup Table The lookup table in each LUT unit can generate any logic expression OUT as a function of up to four inputs, IN[3:0]. The truth table for the expression is written to the TRUTH register for the LUT. Table 32-2 shows the truth table for LUT0. The truth table for LUTn is written to TRUTHn, and the corresponding input and outputs will be IN[4n] to IN[4n+3] and OUTn. 32.6.3 Output Filter By default, the output OUTn is a combinatorial function of the inputs IN[4n] to IN[4n+3]. This may cause some short glitches to occur when the inputs change value. It is also possible to clock the output through a filter to remove glitches. This requires that the corresponding generic clock (GCLK) has been enabled before use. The filter can then be enabled by writing a one to the Filter Enable (FILTEN) bit in CRn. The OUTn output will be delayed by three to four GCLK cycles when the filter is enabled. Table 32-2. Truth Table for the Lookup Table in LUT0 IN[3] IN[2] IN[1] IN[0] OUT[0] 0 0 0 0 TRUTH0[0] 0 0 0 1 TRUTH0[1] 0 0 1 0 TRUTH0[2] 0 0 1 1 TRUTH0[3] 0 1 0 0 TRUTH0[4] 0 1 0 1 TRUTH0[5] 0 1 1 0 TRUTH0[6] 0 1 1 1 TRUTH0[7] 1 0 0 0 TRUTH0[8] 1 0 0 1 TRUTH0[9] 1 0 1 0 TRUTH0[10] 1 0 1 1 TRUTH0[11] 1 1 0 0 TRUTH0[12] 1 1 0 1 TRUTH0[13] 1 1 1 0 TRUTH0[14] 1 1 1 1 TRUTH0[15] 820 32142D–06/2013 ATUC64/128/256L3/4U 32.7 User Interface Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 32-3. GLOC Register Memory Map Offset Register Register Name Access Reset 0x00+n*0x08 Control Register n CRn Read/Write 0x00000000 0x04+n*0x08 Truth Table Register n TRUTHn Read/Write 0x00000000 0x38 Parameter Register PARAMETER Read-only - (1) 0x3C Version Register VERSION Read-only - (1) 821 32142D–06/2013 ATUC64/128/256L3/4U 32.7.1 Control Register n Name: CRn Access Type: Read/Write Offset: 0x00+n*0x08 Reset Value: 0x00000000 • FILTEN: Filter Enable 1: The output is glitch filtered 0: The output is not glitch filtered • AEN: Enable IN Inputs Input IN[n] is enabled when AEN[n] is one. Input IN[n] is disabled when AEN[n] is zero, and will not affect the OUT value. 31 30 29 28 27 26 25 24 FILTEN - - - - - - - 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - AEN 822 32142D–06/2013 ATUC64/128/256L3/4U 32.7.2 Truth Table Register n Name: TRUTHn Access Type: Read/Write Offset: 0x04+n*0x08 Reset Value: 0x00000000 • TRUTH: Truth Table Value This value defines the output OUT as a function of inputs IN: OUT = TRUTH[IN] 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 TRUTH[15:8] 76543210 TRUTH[7:0] 823 32142D–06/2013 ATUC64/128/256L3/4U 32.7.3 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x38 Reset Value: - • LUTS: Lookup Table Units Implemented This field contains the number of lookup table units implemented in this device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 LUTS 824 32142D–06/2013 ATUC64/128/256L3/4U 32.7.4 VERSION Register Name: VERSION Access Type: Read-only Offset: 0x3C Reset Value: - • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - VARIANT 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 825 32142D–06/2013 ATUC64/128/256L3/4U 32.8 Module Configuration The specific configuration for each GLOC instance is listed in the following tables.The GLOC bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 32-4. GLOC Configuration Feature GLOC Number of LUT units 2 Table 32-5. GLOC Clocks Clock Name Description CLK_GLOC Clock for the GLOC bus interface GCLK The generic clock used for the GLOC is GCLK5 Table 32-6. Register Reset Values Register Reset Value VERSION 0x00000100 PARAMETER 0x00000002 826 32142D–06/2013 ATUC64/128/256L3/4U 33. aWire UART (AW) Rev: 2.3.0.0 33.1 Features • Asynchronous receiver or transmitter when the aWire system is not used for debugging. • One- or two-pin operation supported. 33.2 Overview If the AW is not used for debugging, the aWire UART can be used by the user to send or receive data with one start bit, eight data bits, no parity bits, and one stop bit. This can be controlled through the aWire UART user interface. This chapter only describes the aWire UART user interface. For a description of the aWire Debug Interface, please see the Programming and Debugging chapter. 33.3 Block Diagram Figure 33-1. aWire Debug Interface Block Diagram UART Reset filter External reset AW_ENABLE RESET_N Baudrate Detector RW SZ ADDR DATA CRC AW CONTROL AW User Interface SAB interface RESET command Power Manager HALT command CPU Flash Controller CHIP_ERASE command aWire Debug Interface PB SAB 827 32142D–06/2013 ATUC64/128/256L3/4U 33.4 I/O Lines Description 33.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 33.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable the aWire UART user interface. 33.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the aWire UART user interface, the aWire UART user interface will stop functioning and resume operation after the system wakes up from sleep mode. 33.5.3 Clocks The aWire UART uses the internal 120 MHz RC oscillator (RC120M) as clock source for its operation. When using the aWire UART user interface RC120M must enabled using the Clock Request Register (see Section 33.6.1). The clock for the aWire UART user interface (CLK_AW) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the aWire UART user interface before disabling the clock, to avoid freezing the aWire UART user interface in an undefined state. 33.5.4 Interrupts The aWire UART user interface interrupt request line is connected to the interrupt controller. Using the aWire UART user interface interrupt requires the interrupt controller to be programmed first. 33.5.5 Debug Operation If the AW is used for debugging the aWire UART user interface will not be usable. When an external debugger forces the CPU into debug mode, the aWire UART user interface continues normal operation. If the aWire UART user interface is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 33.5.6 External Components The AW needs an external pullup on the RESET_N pin to ensure that the pin is pulled up when the bus is not driven. 33.6 Functional Description The aWire UART user interface can be used as a spare Asynchronous Receiver or Transmitter when AW is not used for debugging. Table 33-1. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin. Input/Output 828 32142D–06/2013 ATUC64/128/256L3/4U 33.6.1 How to Initialize The Module To initialize the aWire UART user interface the user must first enable the clock by writing a one to the Clock Enable bit in the Clock Request Register (CLKR.CLKEN) and wait for the Clock Enable bit in the Status Register (SR.CENABLED) to be set. After doing this either receive, transmit or receive with resync must be selected by writing the corresponding value into the Mode field of the Control (CTRL.MODE) Register. Due to the RC120M being asynchronous with the system clock values must be allowed to propagate in the system. During this time the aWire master will set the Busy bit in the Status Register (SR.BUSY). After the SR.BUSY bit is cleared the Baud Rate field in the Baud Rate Register (BRR.BR) can be written with the wanted baudrate ( ) according to the following formula ( is the RC120M clock frequency): After this operation the user must wait until the SR.BUSY is cleared. The interface is now ready to be used. 33.6.2 Basic Asynchronous Receiver Operation The aWire UART user interface must be initialized according to the sequence above, but the CTRL.MODE field must be written to one (Receive mode). When a data byte arrives the aWire UART user interface will indicate this by setting the Data Ready Interrupt bit in the Status Register (SR.DREADYINT). The user must read the Data in the Receive Holding Register (RHR.RXDATA) and clear the Interrupt bit by writing a one to the Data Ready Interrupt Clear bit in the Status Clear Register (SCR.DREADYINT). The interface is now ready to receive another byte. 33.6.3 Basic Asynchronous Transmitter Operation The aWire UART user interface must be initialized according to the sequence above, but the CTRL.MODE field must be written to two (Transmit mode). To transmit a data byte the user must write the data to the Transmit Holding Register (THE.TXDATA). Before the next byte can be written the SR.BUSY must be cleared. 33.6.4 Basic Asynchronous Receiver with Resynchronization By writing three into CTRL.MODE the aWire UART user interface will assume that the first byte it receives is a sync byte (0x55) and set BRR.BR according to this. All subsequent transfers will assume this baudrate, unless BRR.BR is rewritten by the user. To make the aWire UART user interface accept a new sync resynchronization the aWire UART user interface must be disabled by writing zero to CTRL.MODE and then reenable the interface. 33.6.5 Overrun In Receive mode an overrun can occur if the user has not read the previous received data from the RHR.RXDATA when the newest data should be placed there. Such a condition is flagged by setting the Overrun bit in the Status Register (SR.OVERRUN). If SR.OVERRUN is set the newest data received is placed in RHR.RXDATA and the data that was there before is overwritten. f br f aw f br 8f aw BR = ----------- 829 32142D–06/2013 ATUC64/128/256L3/4U 33.6.6 Interrupts To make the CPU able to do other things while waiting for the aWire UART user interface to finish its operations the aWire UART user interface supports generating interrupts. All status bits in the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED bits. To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable Register (IER). Upon the next zero to one transition of this SR bit the aWire UART user interface will flag this interrupt to the CPU. To clear the interrupt the user must write a one to the corresponding bit in the Status Clear Register (SCR). Interrupts can be disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt Mask Register (IMR) can be read to check if an interrupt is enabled or disabled. 33.6.7 Using the Peripheral DMA Controller To relieve the CPU of data transfers the aWire UART user interface support using the Peripheral DMA controller. To transmit using the Peripheral DMA Controller do the following: 1. Setup the aWire UART user interface in transmit mode. 2. Setup the Peripheral DMA Controller with buffer address and length, use byte as transfer size. 3. Enable the Peripheral DMA Controller. 4. Wait until the Peripheral DMA Controller is done. To receive using the Peripheral DMA Controller do the following: 1. Setup the aWire UART user interface in receive mode 2. Setup the Peripheral DMA Controller with buffer address and length, use byte as transfer size. 3. Enable the Peripheral DMA Controller. 4. Wait until the Peripheral DMA Controller is ready. 830 32142D–06/2013 ATUC64/128/256L3/4U 33.7 User Interface Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. Table 33-2. aWire UART user interface Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CTRL Read/Write 0x00000000 0x04 Status Register SR Read-only 0x00000000 0x08 Status Clear Register SCR Write-only - 0x0C Interrupt Enable Register IER Write-only - 0x10 Interrupt Disable Register IDR Write-only - 0x14 Interrupt Mask Register IMR Read-only 0x00000000 0x18 Receive Holding Register RHR Read-only 0x00000000 0x1C Transmit Holding Register THR Read/Write 0x00000000 0x20 Baud Rate Register BRR Read/Write 0x00000000 0x24 Version Register VERSION Read-only -(1) 0x28 Clock Request Register CLKR Read/Write 0x00000000 831 32142D–06/2013 ATUC64/128/256L3/4U 33.7.1 Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • MODE: aWire UART user interface mode 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - - MODE Table 33-3. aWire UART user interface Modes MODE Mode Description 0 Disabled 1 Receive 2 Transmit 3 Receive with resync. 832 32142D–06/2013 ATUC64/128/256L3/4U 33.7.2 Status Register Name: SR Access Type: Read-only Offset: 0x04 Reset Value: 0x00000000 • TRMIS: Transmit Mismatch 0: No transfers mismatches. 1: The transceiver was active when receiving. This bit is set when the transceiver is active when receiving. This bit is cleared when corresponding bit in SCR is written to one. • OVERRUN: Data Overrun 0: No data overwritten in RHR. 1: Data in RHR has been overwritten before it has been read. This bit is set when data in RHR is overwritten before it has been read. This bit is cleared when corresponding bit in SCR is written to one. • DREADYINT: Data Ready Interrupt 0: No new data in the RHR. 1: New data received and placed in the RHR. This bit is set when new data is received and placed in the RHR. This bit is cleared when corresponding bit in SCR is written to one. • READYINT: Ready Interrupt 0: The interface has not generated an ready interrupt. 1: The interface has had a transition from busy to not busy. This bit is set when the interface has transition from busy to not busy. This bit is cleared when corresponding bit in SCR is written to one. • CENABLED: Clock Enabled 0: The aWire clock is not enabled. 1: The aWire clock is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 76543210 - - - - - CENABLED - BUSY 833 32142D–06/2013 ATUC64/128/256L3/4U This bit is set when the clock is disabled. This bit is cleared when the clock is enabled. • BUSY: Synchronizer Busy 0: The asynchronous interface is ready to accept more data. 1: The asynchronous interface is busy and will block writes to CTRL, BRR, and THR. This bit is set when the asynchronous interface becomes busy. This bit is cleared when the asynchronous interface becomes ready. 834 32142D–06/2013 ATUC64/128/256L3/4U 33.7.3 Status Clear Register Name: SCR Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 76543210 -------- 835 32142D–06/2013 ATUC64/128/256L3/4U 33.7.4 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 76543210 -------- 836 32142D–06/2013 ATUC64/128/256L3/4U 33.7.5 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 76543210 -------- 837 32142D–06/2013 ATUC64/128/256L3/4U 33.7.6 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 76543210 -------- 838 32142D–06/2013 ATUC64/128/256L3/4U 33.7.7 Receive Holding Register Name: RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 • RXDATA: Received Data The last byte received. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 RXDATA 839 32142D–06/2013 ATUC64/128/256L3/4U 33.7.8 Transmit Holding Register Name: THR Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 • TXDATA: Transmit Data The data to send. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 TXDATA 840 32142D–06/2013 ATUC64/128/256L3/4U 33.7.9 Baud Rate Register Name: BRR Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 • BR: Baud Rate The baud rate ( ) of the transmission, calculated using the following formula ( is the RC120M frequency): BR should not be set to a value smaller than 32. Writing a value to this field will update the baud rate of the transmission. Reading this field will give the current baud rate of the transmission. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 BR[15:8] 76543210 BR[7:0] f br f aw f br 8f aw BR = ----------- 841 32142D–06/2013 ATUC64/128/256L3/4U 33.7.10 Version Register Name: VERSION Access Type: Read-only Offset: 0x24 Reset Value: 0x00000200 • VERSION: Version Number Version number of the module. No functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - VERSION[11:8] 76543210 VERSION[7:0] 842 32142D–06/2013 ATUC64/128/256L3/4U 33.7.11 Clock Request Register Name: CLKR Access Type: Read/Write Offset: 0x28 Reset Value: 0x00000000 • CLKEN: Clock Enable 0: The aWire clock is disabled. 1: The aWire clock is enabled. Writing a zero to this bit will disable the aWire clock. Writing a one to this bit will enable the aWire clock. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - - - CLKEN 843 32142D–06/2013 ATUC64/128/256L3/4U 33.8 Module Configuration The specific configuration for each aWire instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 33-4. AW Clocks Clock Name Description CLK_AW Clock for the AW bus interface Table 33-5. Register Reset Values Register Reset Value VERSION 0x00000230 844 32142D–06/2013 ATUC64/128/256L3/4U 34. Programming and Debugging 34.1 Overview The ATUC64/128/256L3/4U supports programming and debugging through two interfaces, JTAG or aWire. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved. Either interface provides access to the internal Service Access Bus (SAB), which offers a bridge to the High Speed Bus, giving access to memories and peripherals in the device. By using this bridge to the bus system, the flash and fuses can thus be programmed by accessing the Flash Controller in the same manner as the CPU. The SAB also provides access to the Nexus-compliant On-chip Debug (OCD) system in the device, which gives the user non-intrusive run-time control of the program execution. Additionally, trace information can be output on the Auxiliary (AUX) debug port or buffered in internal RAM for later retrieval by JTAG or aWire. 34.2 Service Access Bus The AVR32 architecture offers a common interface for access to On-chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG and aWire port through a bus master module, which also handles synchronization between the debugger and SAB clocks. When accessing the SAB through the debugger there are no limitations on debugger frequency compared to chip frequency, although there must be an active system clock in order for the SAB accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger will restart the system clock automatically, without waking the device from sleep. Debuggers may optimize the transfer rate by adjusting the frequency in relation to the system clock. This ratio can be measured with debug protocol specific instructions. The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. 34.2.1 SAB Address Map The SAB gives the user access to the internal address space and other features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32 LSBs are decoded within the slave’s address space. The SAB slaves are shown in Table 34-1. Table 34-1. SAB Slaves, Addresses and Descriptions Slave Address [35:32] Description Unallocated 0x0 Intentionally unallocated OCD 0x1 OCD registers HSB 0x4 HSB memory space, as seen by the CPU 845 32142D–06/2013 ATUC64/128/256L3/4U 34.2.2 SAB Security Restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. 34.2.2.1 Security measure and control location A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure. These security measures can be used to prevent an end user from reading out the code programmed in the flash, for instance. Below follows a more in depth description of what locations are accessible when the security measures are active. Note: 1. Second Word of the User Page, refer to the Fuses Settings section for details. HSB 0x5 Alternative mapping for HSB space, for compatibility with other 32-bit AVR devices. Memory Service Unit 0x6 Memory Service Unit registers Reserved Other Unused Table 34-1. SAB Slaves, Addresses and Descriptions Slave Address [35:32] Description Table 34-2. SAB Security Measures Security Measure Control Location Description Secure mode FLASHCDW SECURE bits set Allocates a portion of the flash for secure code. This code cannot be read or debugged. The User page is also locked. Security bit FLASHCDW security bit set Programming and debugging not possible, very restricted access. User code programming FLASHCDW UPROT + security bit set Restricts all access except parts of the flash and the flash controller for programming user code. Debugging is not possible unless an OS running from the secure part of the flash supports it. Table 34-3. Secure Mode SAB Restrictions Name Address Start Address End Access Secure flash area 0x580000000 0x580000000 + (USERPAGE[15:0] << 10) Blocked Secure RAM area 0x500000000 0x500000000 + (USERPAGE[31:16] << 10) Blocked User page 0x580800000 0x581000000 Read Other accesses - - As normal 846 32142D–06/2013 ATUC64/128/256L3/4U Table 34-4. Security Bit SAB Restrictions Name Address start Address end Access OCD DCCPU, OCD DCEMU, OCD DCSR 0x100000110 0x100000118 Read/Write User page 0x580800000 0x581000000 Read Other accesses - - Blocked Table 34-5. User Code Programming SAB Restrictions Name Address start Address end Access OCD DCCPU, OCD DCEMU, OCD DCSR 0x100000110 0x100000118 Read/Write User page 0x580800000 0x581000000 Read FLASHCDW PB interface 0x5FFFE0000 0x5FFFE0400 Read/Write FLASH pages outside BOOTPROT 0x580000000 + BOOTPROT size 0x580000000 + Flash size Read/Write Other accesses - - Blocked 847 32142D–06/2013 ATUC64/128/256L3/4U 34.3 On-Chip Debug Rev: 2.1.2.0 34.3.1 Features • Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ • JTAG or aWire access to all on-chip debug functions • Advanced Program, Data, Ownership, and Watchpoint trace supported • NanoTrace aWire- or JTAG-based trace access • Auxiliary port for high-speed trace information • Hardware support for 6 Program and 2 Data breakpoints • Unlimited number of software breakpoints supported • Automatic CRC check of memory regions 34.3.2 Overview Debugging on the ATUC64/128/256L3/4U is facilitated by a powerful On-Chip Debug (OCD) system. The user accesses this through an external debug tool which connects to the JTAG or aWire port and the Auxiliary (AUX) port if implemented. The AUX port is primarily used for trace functions, and an aWire- or JTAG-based debugger is sufficient for basic debugging. The debug system is based on the Nexus 2.0 standard, class 2+, which includes: • Basic run-time control • Program breakpoints • Data breakpoints • Program trace • Ownership trace • Data trace In addition to the mandatory Nexus debug features, the ATUC64/128/256L3/4U implements several useful OCD features, such as: • Debug Communication Channel between CPU and debugger • Run-time PC monitoring • CRC checking • NanoTrace • Software Quality Assurance (SQA) support The OCD features are controlled by OCD registers, which can be accessed by the debugger, for instance when the NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical Reference Manual. 34.3.3 I/O Lines Description The OCD AUX trace port contains a number of pins, as shown in Table 34-6 on page 848. These are multiplexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before the debug session starts. The AUX port is mapped to two different locations, 848 32142D–06/2013 ATUC64/128/256L3/4U selectable by OCD Registers, minimizing the chance that the AUX port will need to be shared with an application. 34.3.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 34.3.4.1 Power Management The OCD clock operates independently of the CPU clock. If enabled in the Power Manager, the OCD clock (CLK_OCD) will continue running even if the CPU enters a sleep mode that disables the CPU clock. 34.3.4.2 Clocks The OCD has a clock (CLK_OCD) running synchronously with the CPU clock. This clock is generated by the Power Manager. The clock is enabled at reset, and can be disabled by writing to the Power Manager. 34.3.4.3 Interrupt The OCD system interrupt request lines are connected to the interrupt controller. Using the OCD interrupts requires the interrupt controller to be programmed first. Table 34-6. Auxiliary Port Signals Pin Name Pin Description Direction Active Level Type MCKO Trace data output clock Output Digital MDO[5:0] Trace data output Output Digital MSEO[1:0] Trace frame control Output Digital EVTI_N Event In Input Low Digital EVTO_N Event Out Output Low Digital 849 32142D–06/2013 ATUC64/128/256L3/4U 34.3.5 Block Diagram Figure 34-1. On-Chip Debug Block Diagram 34.3.6 SAB-based Debug Features A debugger can control all OCD features by writing OCD registers over the SAB interface. Many of these do not depend on output on the AUX port, allowing an aWire- or JTAG-based debugger to be used. A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector as described in the AVR32UC Technical Reference Manual. An aWire-based debugger should connect to the device through the RESET_N pin. On-Chip Debug JTAG Debug PC Debug Instruction CPU Breakpoints Program Trace Data Trace Ownership Trace Transmit Queue Watchpoints AUX JTAG Internal SRAM Service Access Bus Memory Service Unit HSB Bus Matrix Memories and peripherals aWire aWire 850 32142D–06/2013 ATUC64/128/256L3/4U Figure 34-2. JTAG-based Debugger Figure 34-3. aWire-based Debugger 34.3.6.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and debugger. The registers can be used to exchange data between the CPU and the debugmaster, both runtime as well as in debug mode. 32-bit AVR JTAG-based debug tool PC JTAG 10-pin IDC 32-bit AVR aWire-based debug tool PC aWire 851 32142D–06/2013 ATUC64/128/256L3/4U The OCD system can generate an interrupt to the CPU when DCCPU is read and when DCEMU is written. This enables the user to build a custum debug protocol using only these registers. The DCCPU and DCEMU registers are available even when the security bit in the flash is active. For more information refer to the AVR32UC Technical Reference Manual. 34.3.6.2 Breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system. This is accomplished by breakpoints, of which many types are available: • Unconditional breakpoints are set by writing OCD registers by the debugger, halting the CPU immediately. • Program breakpoints halt the CPU when a specific address in the program is executed. • Data breakpoints halt the CPU when a specific memory address is read or written, allowing variables to be watched. • Software breakpoints halt the CPU when the breakpoint instruction is executed. When a breakpoint triggers, the CPU enters debug mode, and the D bit in the status register is set. This is a privileged mode with dedicated return address and return status registers. All privileged instructions are permitted. Debug mode can be entered as either OCD Mode, running instructions from the debugger, or Monitor Mode, running instructions from program memory. 34.3.6.3 OCD Mode When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the Debug Instruction OCD register. Each time this register is written by the debugger, the instruction is executed, allowing the debugger to execute CPU instructions directly. The debug master can e.g. read out the register file by issuing mtdr instructions to the CPU, writing each register to the Debug Communication Channel OCD registers. 34.3.6.4 Monitor Mode Since the OCD registers are directly accessible by the CPU, it is possible to build a softwarebased debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development Control register causes the CPU to enter Monitor Mode instead of OCD mode when a breakpoint triggers. Monitor Mode is similar to OCD mode, except that instructions are fetched from the debug exception vector in regular program memory, instead of issued by the debug master. 34.3.6.5 Program Counter Monitoring Normally, the CPU would need to be halted for a debugger to examine the current PC value. However, the ATUC64/128/256L3/4U also proves a Debug Program Counter OCD register, where the debugger can continuously read the current PC without affecting the CPU. This allows the debugger to generate a simple statistic of the time spent in various areas of the code, easing code optimization. 34.3.7 Memory Service Unit The Memory Service Unit (MSU) is a block dedicated to test and debug functionality. It is controlled through a dedicated set of registers addressed through the Service Access Bus. 852 32142D–06/2013 ATUC64/128/256L3/4U 34.3.7.1 Cyclic Redundancy Check (CRC) The MSU can be used to automatically calculate the CRC of a block of data in memory. The MSU will then read out each word in the specified memory block and report the CRC32-value in an MSU register. 34.3.7.2 NanoTrace The MSU additionally supports NanoTrace. This is a 32-bit AVR-specific feature, in which trace data is output to memory instead of the AUX port. This allows the trace data to be extracted by the debugger through the SAB, enabling trace features for aWire- or JTAG-based debuggers. The user must write MSU registers to configure the address and size of the memory block to be used for NanoTrace. The NanoTrace buffer can be anywhere in the physical address range, including internal and external RAM, through an EBI, if present. This area may not be used by the application running on the CPU. 34.3.8 AUX-based Debug Features Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of prime importance are the trace features, which allow an external debugger to receive continuous information on the program execution in the CPU. Additionally, Event In and Event Out pins allow external events to be correlated with the program flow. Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mictor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device. 853 32142D–06/2013 ATUC64/128/256L3/4U Figure 34-4. AUX+JTAG Based Debugger 34.3.8.1 Trace Operation Trace features are enabled by writing OCD registers by the debugger. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard. The messages are buffered in a 16-frame transmit queue, and are output on the AUX port one frame at a time. The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 34.3.8.2 Program Trace Program trace allows the debugger to continuously monitor the program execution in the CPU. Program trace messages are generated for every branch in the program, and contains compressed information, which allows the debugger to correlate the message with the source code to identify the branch instruction and target address. 34.3.8.3 Data Trace Data trace outputs a message every time a specific location is read or written. The message contains information about the type (read/write) and size of the access, as well as the address and data of the accessed location. The ATUC64/128/256L3/4U contains two data trace chanAVR32 AUX+JTAG debu g tool JTAG AUX h ig h s p e e d M ic to r3 8 T ra ce b u ffe r P C 854 32142D–06/2013 ATUC64/128/256L3/4U nels, each of which are controlled by a pair of OCD registers which determine the range of addresses (or single address) which should produce data trace messages. 34.3.8.4 Ownership Trace Program and data trace operate on virtual addresses. In cases where an operating system runs several processes in overlapping virtual memory segments, the Ownership Trace feature can be used to identify the process switch. When the O/S activates a process, it will write the process ID number to an OCD register, which produces an Ownership Trace Message, allowing the debugger to switch context for the subsequent program and data trace messages. As the use of this feature depends on the software running on the CPU, it can also be used to extract other types of information from the system. 34.3.8.5 Watchpoint Messages The breakpoint modules normally used to generate program and data breakpoints can also be used to generate Watchpoint messages, allowing a debugger to monitor program and data events without halting the CPU. Watchpoints can be enabled independently of breakpoints, so a breakpoint module can optionally halt the CPU when the trigger condition occurs. Data trace modules can also be configured to produce watchpoint messages instead of regular data trace messages. 34.3.8.6 Event In and Event Out Pins The AUX port also contains an Event In pin (EVTI_N) and an Event Out pin (EVTO_N). EVTI_N can be used to trigger a breakpoint when an external event occurs. It can also be used to trigger specific program and data trace synchronization messages, allowing an external event to be correlated to the program flow. When the CPU enters debug mode, a Debug Status message is transmitted on the trace port. All trace messages can be timestamped when they are received by the debug tool. However, due to the latency of the transmit queue buffering, the timestamp will not be 100% accurate. To improve this, EVTO_N can toggle every time a message is inserted into the transmit queue, allowing trace messages to be timestamped precisely. EVTO_N can also toggle when a breakpoint module triggers, or when the CPU enters debug mode, for any reason. This can be used to measure precisely when the respective internal event occurs. 34.3.8.7 Software Quality Analysis (SQA) Software Quality Analysis (SQA) deals with two important issues regarding embedded software development. Code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. Performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized. Program trace must be used to accomplish these tasks without instrumenting (altering) the code to be examined. However, traditional program trace cannot reconstruct the current PC value without correlating the trace information with the source code, which cannot be done on-the-fly. This limits program trace to a relatively short time segment, determined by the size of the trace buffer in the debug tool. The OCD system in ATUC64/128/256L3/4U extends program trace with SQA capabilities, allowing the debug tool to reconstruct the PC value on-the-fly. Code coverage and performance analysis can thus be reported for an unlimited execution sequence. 855 32142D–06/2013 ATUC64/128/256L3/4U 34.4 JTAG and Boundary-scan (JTAG) Rev: 2.2.2.4 34.4.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 34.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. Figure 34-5 on page 856 shows how the JTAG is connected in an 32-bit AVR device. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift register) between the TDI-input and TDO-output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The Device Identification Register, Bypass Register, and the boundary-scan chain are the Data Registers used for board-level testing. The Reset Register can be used to keep the device reset during test or programming. The Service Access Bus (SAB) interface contains address and data registers for the Service Access Bus, which gives access to On-Chip Debug, programming, and other functions in the device. The SAB offers several modes of access to the address and data registers, as described in Section 34.4.11. Section 34.5 lists the supported JTAG instructions, with references to the description in this document. 856 32142D–06/2013 ATUC64/128/256L3/4U 34.4.3 Block Diagram Figure 34-5. JTAG and Boundary-scan Access 34.4.4 I/O Lines Description 34.4.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. Table 34-7. I/O Line Description Pin Name Pin Description Type Active Level RESET_N External reset pin. Used when enabling and disabling the JTAG. Input Low TCK Test Clock Input. Fully asynchronous to system clock frequency. Input TMS Test Mode Select, sampled on rising TCK. Input TDI Test Data In, sampled on rising TCK. Input TDO Test Data Out, driven on falling TCK. Output 32-bit AVR device JTAG data registers TAP Controller Instruction Register Device Identification Register By-pass Register Reset Register Service Access Bus interface Boundary Scan Chain Pins and analog blocks Data register scan enable JTAG Pins Boundary scan enable 2nd JTAG device JTAG master TDO TDI Part specific registers ... TMS TDO TDI TMS TCK TCK Instruction register scan enable SAB Internal I/O lines JTAG TMS TDI TDO TCK 857 32142D–06/2013 ATUC64/128/256L3/4U 34.4.5.1 I/O Lines The TMS, TDI, TDO, and TCK pins are multiplexed with I/O lines. When the JTAG is used the associated pins must be enabled. To enable the JTAG pins, refer to Section 34.4.7. While using the multiplexed JTAG lines all normal peripheral activity on these lines is disabled. The user must make sure that no external peripheral is blocking the JTAG lines while debugging. 34.4.5.2 Power Management When an instruction that accesses the SAB is loaded in the instruction register, before entering a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This can lead to a program behaving differently when debugging. 34.4.5.3 Clocks The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by the JTAG master. Instructions that use the SAB bus requires the internal main clock to be running. 34.4.6 JTAG Interface The JTAG Interface is accessed through the dedicated JTAG pins shown in Table 34-7 on page 856. The TMS control line navigates the TAP controller, as shown in Figure 34-6 on page 858. The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data is scanned into the selected instruction or data register on TDI, and out of the register on TDO, in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is highZ in other states than Shift-IR and Shift-DR. The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions defined by the JTAG standard are supported, as described in Section 34.5.2, as well as a number of 32-bit AVR-specific private JTAG instructions described in Section 34.5.3. Each instruction selects a specific data register for the Shift-DR path, as described for each instruction. 858 32142D–06/2013 ATUC64/128/256L3/4U Figure 34-6. TAP Controller State Diagram Test-LogicReset Run-Test/ Idle Select-DR Scan Select-IR Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 1 859 32142D–06/2013 ATUC64/128/256L3/4U 34.4.7 How to Initialize the Module To enable the JTAG pins the TCK pin must be held low while the RESET_N pin is released. After enabling the JTAG interface the halt bit is set automatically to prevent the system from running code after the interface is enabled. To make the CPU run again set halt to zero using the HALT command.. JTAG operation when RESET_N is pulled low is not possible. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied at the start of a JTAG session and after enabling the JTAG pins to bring the TAP Controller into a defined state before applying JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the Run-Test/Idle state, which is the starting point for JTAG operations. 34.4.8 How to disable the module To disable the JTAG pins the TCK pin must be held high while RESET_N pin is released. 34.4.9 Typical Sequence Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG Interface follows. 34.4.9.1 Scanning in JTAG Instruction At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register (Shift-IR) state. While in this state, shift the 5 bits of the JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. During shifting, the JTAG outputs status bits on TDO, refer to Section 34.5 for a description of these. The TMS input must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. Figure 34-7. Scanning in JTAG Instruction 34.4.9.2 Scanning in/out Data At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register (Shift-DR) state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge TCK TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI TMS TDI Instruction TDO ImplDefined 860 32142D–06/2013 ATUC64/128/256L3/4U of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers. 34.4.10 Boundary-scan The boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long shift register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the 4 TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the 32-bit AVR device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESETn pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG Interface for boundary-scan, the JTAG TCK clock is independent of the internal chip clock. The internal chip clock is not required to run during boundary-scan operations. NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one using boundary-scan, as this will create a current flowing from the 3,3V driver to the 5V pull-up on the line. Optionally a series resistor can be added between the line and the pin to reduce the current. Details about the boundary-scan chain can be found in the BSDL file for the device. This can be found on the Atmel website. 34.4.11 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), 861 32142D–06/2013 ATUC64/128/256L3/4U which is linked to the JTAG through a bus master module, which also handles synchronization between the TCK and SAB clocks. For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 34.4.11.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any 36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruction for accessing the 32-bit OCD registers in the 7-bit address space reserved for these. These instructions require two passes through the Shift-DR TAP state: one for the address and control information, and one for data. 34.4.11.2 Block Transfer To increase the transfer rate, consecutive memory accesses can be accomplished by the MEMORY_BLOCK_ACCESS instruction, which only requires a single pass through Shift-DR for data transfer only. The address is automatically incremented according to the size of the last SAB transfer. 34.4.11.3 Canceling a SAB Access It is possible to abort an ongoing SAB access by the CANCEL_ACCESS instruction, to avoid hanging the bus due to an extremely slow slave. 34.4.11.4 Busy Reporting As the time taken to perform an access may vary depending on system activity and current chip frequency, all the SAB access JTAG instructions can return a busy indicator. This indicates whether a delay needs to be inserted, or an operation needs to be repeated in order to be successful. If a new access is requested while the SAB is busy, the request is ignored. The SAB becomes busy when: • Entering Update-DR in the address phase of any read operation, e.g., after scanning in a NEXUS_ACCESS address with the read bit set. • Entering Update-DR in the data phase of any write operation, e.g., after scanning in data for a NEXUS_ACCESS write. • Entering Update-DR during a MEMORY_BLOCK_ACCESS. • Entering Update-DR after scanning in a counter value for SYNC. • Entering Update-IR after scanning in a MEMORY_BLOCK_ACCESS if the previous access was a read and data was scanned after scanning the address. The SAB becomes ready again when: • A read or write operation completes. • A SYNC countdown completed. • A operation is cancelled by the CANCEL_ACCESS instruction. What to do if the busy bit is set: • During Shift-IR: The new instruction is selected, but the previous operation has not yet completed and will continue (unless the new instruction is CANCEL_ACCESS). You may 862 32142D–06/2013 ATUC64/128/256L3/4U continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy. • During Shift-DR of an address: The new address is ignored. The SAB stays in address mode, so no data must be shifted. Repeat the address until the busy bit clears. • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears. • During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat scanning until the busy bit clears. 34.4.11.5 Error Reporting The Service Access Bus may not be able to complete all accesses as requested. This may be because the address is invalid, the addressed area is read-only or cannot handle byte/halfword accesses, or because the chip is set in a protected mode where only limited accesses are allowed. The error bit is updated when an access completes, and is cleared when a new access starts. What to do if the error bit is set: • During Shift-IR: The new instruction is selected. The last operation performed using the old instruction did not complete successfully. • During Shift-DR of an address: The previous operation failed. The new address is accepted. If the read bit is set, a read operation is started. • During Shift-DR of read data: The read operation failed, and the read data is invalid. • During Shift-DR of write data: The previous write operation failed. The new data is accepted and a write operation started. This should only occur during block writes or stream writes. No error can occur between scanning a write address and the following write data. • While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not have actually completed. • After power-up: The error bit is set after power up, but there has been no previous SAB instruction so this error can be discarded. 34.4.11.6 Protected Reporting A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security bit in the Flash Controller is set and that the chip is locked for access, according to Section 34.5.1. The protected state is reported when: • The Flash Controller is under reset. This can be due to the AVR_RESET command or the RESET_N line. • The Flash Controller has not read the security bit from the flash yet (This will take a a few ms). Happens after the Flash Controller reset has been released. • The security bit in the Flash Controller is set. What to do if the protected bit is set: • Release all active AVR_RESET domains, if any. • Release the RESET_N line. • Wait a few ms for the security bit to clear. It can be set temporarily due to a reset. 863 32142D–06/2013 ATUC64/128/256L3/4U • Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the non-volatile memory. 34.5 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. 34.5.1 Security Restrictions When the security fuse in the Flash is programmed, the following JTAG instructions are restricted: • NEXUS_ACCESS • MEMORY_WORD_ACCESS • MEMORY_BLOCK_ACCESS • MEMORY_SIZED_ACCESS For description of what memory locations remain accessible, please refer to the SAB address map. Full access to these instructions is re-enabled when the security fuse is erased by the CHIP_ERASE JTAG instruction. Table 34-8. JTAG Instruction Summary Instruction OPCODE Instruction Description 0x01 IDCODE Select the 32-bit Device Identification register as data register. 0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation. 0x03 EXTEST Select boundary-scan chain as data register for testing circuitry external to the device. 0x04 INTEST Select boundary-scan chain for internal testing of the device. 0x06 CLAMP Bypass device through Bypass register, while driving outputs from boundaryscan register. 0x0C AVR_RESET Apply or remove a static reset to the device 0x0F CHIP_ERASE Erase the device 0x10 NEXUS_ACCESS Select the SAB Address and Data registers as data register for the TAP. The registers are accessed in Nexus mode. 0x11 MEMORY_WORD_ACCESS Select the SAB Address and Data registers as data register for the TAP. 0x12 MEMORY_BLOCK_ACCESS Select the SAB Data register as data register for the TAP. The address is auto-incremented. 0x13 CANCEL_ACCESS Cancel an ongoing Nexus or Memory access. 0x14 MEMORY_SERVICE Select the SAB Address and Data registers as data register for the TAP. The registers are accessed in Memory Service mode. 0x15 MEMORY_SIZED_ACCESS Select the SAB Address and Data registers as data register for the TAP. 0x17 SYNC Synchronization counter 0x1C HALT Halt the CPU for safe programming. 0x1F BYPASS Bypass this device through the bypass register. Others N/A Acts as BYPASS 864 32142D–06/2013 ATUC64/128/256L3/4U Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 34.5.1.1 Notation Table 34-10 on page 864 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability. The least significantbit is always shifted first, and the most significant bit shifted last. The symbols used are shown in Table 34-9. In many cases, it is not required to shift all bits through the data register. Bit patterns are shown using the full width of the shift register, but the suggested or required bits are emphasized using bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is 34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar". The following describes how to interpret the fields in the instruction description tables: Table 34-9. Symbol Description Symbol Description 0 Constant low value - always reads as zero. 1 Constant high value - always reads as one. a An address bit - always scanned with the least significant bit first b A busy bit. Reads as one if the SAB was busy, or zero if it was not. See Section 34.4.11.4 for details on how the busy reporting works. d A data bit - always scanned with the least significant bit first. e An error bit. Reads as one if an error occurred, or zero if not. See Section 34.4.11.5 for details on how the error reporting works. p The chip protected bit. Some devices may be set in a protected state where access to chip internals are severely restricted. See the documentation for the specific device for details. On devices without this possibility, this bit always reads as zero. r A direction bit. Set to one to request a read, set to zero to request a write. s A size bit. The size encoding is described where used. x A don’t care bit. Any value can be shifted in, and output data should be ignored. Table 34-10. Instruction Description Instruction Description IR input value Shows the bit pattern to shift into IR in the Shift-IR state in order to select this instruction. The pattern is show both in binary and in hexadecimal form for convenience. Example: 10000 (0x10) IR output value Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is active. Example: peb01 865 32142D–06/2013 ATUC64/128/256L3/4U 34.5.2 Public JTAG Instructions The JTAG standard defines a number of public JTAG instructions. These instructions are described in the sections below. 34.5.2.1 IDCODE This instruction selects the 32 bit Device Identification register (DID) as Data Register. The DID register consists of a version number, a device number, and the manufacturer code chosen by JEDEC. This is the default instruction after a JTAG reset. Details about the DID register can be found in the module configuration section at the end of this chapter. Starting in Run-Test/Idle, the Device Identification register is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The IDCODE value is latched into the shift register. 7. In Shift-DR: The IDCODE scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. 34.5.2.2 SAMPLE_PRELOAD This instruction takes a snap-shot of the input/output pins without affecting the system operation, and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is selected as Data Register. Starting in Run-Test/Idle, the Device Identification register is accessed in the following way: DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes. Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx DR output value Shows the bit pattern shifted out of the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes. Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb Table 34-10. Instruction Description (Continued) Instruction Description Table 34-11. IDCODE Details Instructions Details IR input value 00001 (0x01) IR output value p0001 DR Size 32 DR input value xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx DR output value Device Identification Register 866 32142D–06/2013 ATUC64/128/256L3/4U 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. 34.5.2.3 EXTEST This instruction selects the boundary-scan chain as Data Register for testing circuitry external to the 32-bit AVR package. The contents of the latched outputs of the boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction. Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the output pins. 5. Return to Run-Test/Idle. 6. Select the DR Scan path. 7. In Capture-DR: The data on the external pins is sampled into the boundary-scan chain. 8. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 9. In Update-DR: The data from the scan chain is applied to the output pins. 10. Return to Run-Test/Idle. Table 34-12. SAMPLE_PRELOAD Details Instructions Details IR input value 00010 (0x02) IR output value p0001 DR Size Depending on boundary-scan chain, see BSDL-file. DR input value Depending on boundary-scan chain, see BSDL-file. DR output value Depending on boundary-scan chain, see BSDL-file. Table 34-13. EXTEST Details Instructions Details IR input value 00011 (0x03) IR output value p0001 DR Size Depending on boundary-scan chain, see BSDL-file. DR input value Depending on boundary-scan chain, see BSDL-file. DR output value Depending on boundary-scan chain, see BSDL-file. 867 32142D–06/2013 ATUC64/128/256L3/4U 34.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the INTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the internal logic inputs. 5. Return to Run-Test/Idle. 6. Select the DR Scan path. 7. In Capture-DR: The data on the internal logic is sampled into the boundary-scan chain. 8. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 9. In Update-DR: The data from the boundary-scan chain is applied to internal logic inputs. 10. Return to Run-Test/Idle. 34.5.2.5 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the output pins. 5. Return to Run-Test/Idle. 6. Select the DR Scan path. 7. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register. 8. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register. Table 34-14. INTEST Details Instructions Details IR input value 00100 (0x04) IR output value p0001 DR Size Depending on boundary-scan chain, see BSDL-file. DR input value Depending on boundary-scan chain, see BSDL-file. DR output value Depending on boundary-scan chain, see BSDL-file. 868 32142D–06/2013 ATUC64/128/256L3/4U 9. Return to Run-Test/Idle. 34.5.2.6 BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register. 7. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register. 8. Return to Run-Test/Idle. 34.5.3 Private JTAG Instructions The 32-bit AVR defines a number of private JTAG instructions, not defined by the JTAG standard. Each instruction is briefly described in text, with details following in table form. 34.5.3.1 NEXUS_ACCESS This instruction allows Nexus-compliant access to the On-Chip Debug registers through the SAB. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the JTAG port. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. NOTE: The polarity of the direction bit is inverse of the Nexus standard. Table 34-15. CLAMP Details Instructions Details IR input value 00110 (0x06) IR output value p0001 DR Size 1 DR input value x DR output value x Table 34-16. BYPASS Details Instructions Details IR input value 11111 (0x1F) IR output value p0001 DR Size 1 DR input value x DR output value x 869 32142D–06/2013 ATUC64/128/256L3/4U Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the OCD register. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. 34.5.3.2 MEMORY_SERVICE This instruction allows access to registers in an optional Memory Service Unit. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the JTAG port. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, Memory Service registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the Memory Service register. Table 34-17. NEXUS_ACCESS Details Instructions Details IR input value 10000 (0x10) IR output value peb01 DR Size 34 bits DR input value (Address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 870 32142D–06/2013 ATUC64/128/256L3/4U 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. 34.5.3.3 MEMORY_SIZED_ACCESS This instruction allows access to the entire Service Access Bus data area. Data is accessed through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units mapped on the SAB bus may support all sizes of accesses, e.g., some may only support word accesses. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Table 34-18. MEMORY_SERVICE Details Instructions Details IR input value 10100 (0x14) IR output value peb01 DR Size 34 bits DR input value (Address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 871 32142D–06/2013 ATUC64/128/256L3/4U The size field is encoded as i Table 34-19. Starting in Run-Test/Idle, SAB data is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write), 2-bit access size, and the 36-bit address of the data to access. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a write operation, scan in the new contents of the area. 9. Return to Run-Test/Idle. For any operation, the full 36 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-19. Size Field Semantics Size field value Access size Data alignment 00 Byte (8 bits) Address modulo 4 : data alignment 0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx 1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx 2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx 3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd 01 Halfword (16 bits) Address modulo 4 : data alignment 0: dddddddd dddddddd xxxxxxxx xxxxxxxx 1: Not allowed 2: xxxxxxxx xxxxxxxx dddddddd dddddddd 3: Not allowed 10 Word (32 bits) Address modulo 4 : data alignment 0: dddddddd dddddddd dddddddd dddddddd 1: Not allowed 2: Not allowed 3: Not allowed 11 Reserved N/A Table 34-20. MEMORY_SIZED_ACCESS Details Instructions Details IR input value 10101 (0x15) IR output value peb01 DR Size 39 bits DR input value (Address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xxxxxxx 872 32142D–06/2013 ATUC64/128/256L3/4U 34.5.3.4 MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area. Data is accessed through the 34 MSB of the SAB address, a direction bit, and 32 bits of data. This instruction is identical to MEMORY_SIZED_ACCESS except that it always does word sized accesses. The size field is implied, and the two lowest address bits are removed and not scanned in. Note: This instruction was previously known as MEMORY_ACCESS, and is provided for backwards compatibility. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, SAB data is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 34-bit address of the data to access. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a write operation, scan in the new contents of the area. 9. Return to Run-Test/Idle. For any operation, the full 34 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb Table 34-20. MEMORY_SIZED_ACCESS Details (Continued) Instructions Details Table 34-21. MEMORY_WORD_ACCESS Details Instructions Details IR input value 10001 (0x11) IR output value peb01 DR Size 35 bits DR input value (Address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xxx 873 32142D–06/2013 ATUC64/128/256L3/4U 34.5.3.5 MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area. Up to 32 bits of data is accessed at a time, while the address is sequentially incremented from the previously used address. In this mode, the SAB address, size, and access direction is not provided with each access. Instead, the previous address is auto-incremented depending on the specified size and the previous operation repeated. The address must be set up in advance with MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to shift data after shifting the address. This instruction is primarily intended to speed up large quantities of sequential word accesses. It is possible to use it also for byte and halfword accesses, but the overhead in this is case much larger as 32 bits must still be shifted for each access. The following sequence should be used: 1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the first location. 2. Return to Run-Test/Idle. 3. Select the IR Scan path. 4. In Capture-IR: The IR output value is latched into the shift register. 5. In Shift-IR: The instruction register is shifted by the TCK input. 6. Return to Run-Test/Idle. 7. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corresponding to the next byte, halfword, or word location). 8. In Shift-DR: For a read operation, scan out the contents of the next addressed location. For a write operation, scan in the new contents of the next addressed location. 9. Go to Update-DR. 10. If the block access is not complete, return to Select-DR Scan and repeat the access. 11. If the block access is complete, return to Run-Test/Idle. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb Table 34-21. MEMORY_WORD_ACCESS Details (Continued) Instructions Details Table 34-22. MEMORY_BLOCK_ACCESS Details Instructions Details IR input value 10010 (0x12) IR output value peb01 DR Size 34 bits DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx 874 32142D–06/2013 ATUC64/128/256L3/4U The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 34.5.3.6 CANCEL_ACCESS If a very slow memory location is accessed during a SAB memory access, it could take a very long time until the busy bit is cleared, and the SAB becomes ready for the next operation. The CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a timeout to the JTAG master. When the CANCEL_ACCESS instruction is selected, the current access will be terminated as soon as possible. There are no guarantees about how long this will take, as the hardware may not always be able to cancel the access immediately. The SAB is ready to respond to a new command when the busy bit clears. Starting in Run-Test/Idle, CANCEL_ACCESS is accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 34.5.3.7 SYNC This instruction allows external debuggers and testers to measure the ratio between the external JTAG clock and the internal system clock. The SYNC data register is a 16-bit counter that counts down to zero using the internal system clock. The busy bit stays high until the counter reaches zero. Starting in Run-Test/Idle, SYNC instruction is used in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb Table 34-22. MEMORY_BLOCK_ACCESS Details (Continued) Instructions Details Table 34-23. CANCEL_ACCESS Details Instructions Details IR input value 10011 (0x13) IR output value peb01 DR Size 1 DR input value x DR output value 0 875 32142D–06/2013 ATUC64/128/256L3/4U 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined. When reading status, shifting may be terminated once the required number of bits have been acquired. 34.5.3.8 AVR_RESET This instruction allows a debugger or tester to directly control separate reset domains inside the chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain. The AVR_RESET instruction can be used in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the value corresponding to the reset domains the JTAG master wants to reset into the data register. 7. Return to Run-Test/Idle. 8. Stay in run test idle for at least 10 TCK clock cycles to let the reset propagate to the system. See the device specific documentation for the number of reset domains, and what these domains are. For any operation, all bits must be provided or the result will be undefined. Table 34-24. SYNC_ACCESS Details Instructions Details IR input value 10111 (0x17) IR output value peb01 DR Size 16 bits DR input value dddddddd dddddddd DR output value xxxxxxxx xxxxxxeb Table 34-25. AVR_RESET Details Instructions Details IR input value 01100 (0x0C) IR output value p0001 876 32142D–06/2013 ATUC64/128/256L3/4U 34.5.3.9 CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately. The erasing of non-volatile memories starts as soon as the CHIP_ERASE instruction is selected. The CHIP_ERASE instruction selects a 1 bit bypass data register. A chip erase operation should be performed as: 1. Reset the system and stop the CPU from executing. 2. Select the IR Scan path. 3. In Capture-IR: The IR output value is latched into the shift register. 4. In Shift-IR: The instruction register is shifted by the TCK input. 5. Check the busy bit that was scanned out during Shift-IR. If the busy bit was set goto 2. 6. Return to Run-Test/Idle. 34.5.3.10 HALT This instruction allows a programmer to easily stop the CPU to ensure that it does not execute invalid code during programming. This instruction selects a 1-bit halt register. Setting this bit to one halts the CPU. Setting this bit to zero releases the CPU to run normally. The value shifted out from the data register is one if the CPU is halted. Before releasing the halt command the CPU needs to be reset to ensure that it will start at the reset startup address. The HALT instruction can be used in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. DR Size Device specific. DR input value Device specific. DR output value Device specific. Table 34-25. AVR_RESET Details (Continued) Instructions Details Table 34-26. CHIP_ERASE Details Instructions Details IR input value 01111 (0x0F) IR output value p0b01 Where b is the busy bit. DR Size 1 bit DR input value x DR output value 0 877 32142D–06/2013 ATUC64/128/256L3/4U 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 34-27. HALT Details Instructions Details IR input value 11100 (0x1C) IR output value p0001 DR Size 1 bit DR input value d DR output value d 878 32142D–06/2013 ATUC64/128/256L3/4U 34.5.4 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. 34.5.4.1 Device Identification Register The Device Identification Register contains a unique identifier for each product. The register is selected by the IDCODE instruction, which is the default instruction after a JTAG reset. Device specific ID codes The different device configurations have different JTAG ID codes, as shown in Table 34-28. Note that if the flash controller is statically reset, the ID code will be undefined. 34.5.4.2 Reset Register The reset register is selected by the AVR_RESET instruction and contains one bit for each reset domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared. MSB LSB Bit 31 28 27 12 11 1 0 Device ID Revision Part Number Manufacturer ID 1 4 bits 16 bits 11 bits 1 bit Revision This is a 4 bit number identifying the revision of the component. Rev A = 0x0, B = 0x1, etc. Part Number The part number is a 16 bit code identifying the component. Manufacturer ID The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is 0x01F. Table 34-28. Device and JTAG ID Device Name JTAG ID Code (R is the revision number) ATUC256L3U 0xr21C303F ATUC128L3U 0xr21C403F ATUC64L3U 0xr21C503F ATUC256L4U 0xr21C603F ATUC128L4U 0xr21C703F ATUC64L4U 0xr21C803F Bit 0 Reset domain System 879 32142D–06/2013 ATUC64/128/256L3/4U 34.5.4.3 Boundary--scan Chain The boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the internal logic. Typically, output value, output enable, and input data are all available in the boundary-scan chain. The boundary-scan chain is described in the BSDL (Boundary Scan Description Language) file available at the Atmel web site. System Resets the whole chip, except the JTAG itself. 880 32142D–06/2013 ATUC64/128/256L3/4U 34.6 aWire Debug Interface (AW) Rev.: 2.3.0.1 34.6.1 Features • Single pin debug system. • Half Duplex asynchronous communication (UART compatible). • Full duplex mode for direct UART connection. • Compatible with JTAG functionality, except boundary scan. • Failsafe packet-oriented protocol. • Read and write on-chip memory and program on-chip flash and fuses through SAB interface. • On-Chip Debug access through SAB interface. • Asynchronous receiver or transmitter when the aWire system is not used for debugging. 34.6.2 Overview The aWire Debug Interface (AW) offers a single pin debug solution that is fully compatible with the functionality offered by the JTAG interface, except boundary scan. This functionality includes memory access, programming capabilities, and On-Chip Debug access. Figure 34-8 on page 881 shows how the AW is connected in a 32-bit AVR device. The RESET_N pin is used both as reset and debug pin. A special sequence on RESET_N is needed to block the normal reset functionality and enable the AW. The Service Access Bus (SAB) interface contains address and data registers for the Service Access Bus, which gives access to On-Chip Debug, programming, and other functions in the device. The SAB offers several modes of access to the address and data registers, as discussed in Section 34.6.6.8. Section 34.6.7 lists the supported aWire commands and responses, with references to the description in this document. If the AW is not used for debugging, the aWire UART can be used by the user to send or receive data with one stop bit, eight data bits, no parity bits, and one stop bit. This can be controlled through the aWire user interface. 881 32142D–06/2013 ATUC64/128/256L3/4U 34.6.3 Block Diagram Figure 34-8. aWire Debug Interface Block Diagram 34.6.4 I/O Lines Description 34.6.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. Table 34-29. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin. Input/Output DATAOUT aWire data output in 2-pin mode. Output UART Reset filter External reset AW_ENABLE RESET_N Baudrate Detector RW SZ ADDR DATA CRC AW CONTROL AW User Interface SAB interface RESET command Power Manager HALT command CPU Flash Controller CHIP_ERASE command aWire Debug Interface PB SAB 882 32142D–06/2013 ATUC64/128/256L3/4U 34.6.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable the AW either by sending the enable sequence over the RESET_N pin from an external aWire master or by enabling the aWire user interface. In 2-pin mode data is received on the RESET_N line, but transmitted on the DATAOUT line. After sending the 2_PIN_MODE command the DATAOUT line is automatically enabled. All other peripheral functions on this pin is disabled. 34.6.5.2 Power Management When debugging through AW the system clocks are automatically turned on to allow debugging in sleep modes. 34.6.5.3 Clocks The aWire UART uses the internal 120 MHz RC oscillator (RC120M) as clock source for its operation. When enabling the AW the RC120M is automatically started. 34.6.5.4 External Components The AW needs an external pullup on the RESET_N pin to ensure that the pin is pulled up when the bus is not driven. 34.6.6 Functional Description 34.6.6.1 aWire Communication Protocol The AW is accessed through the RESET_N pin shown in Table 34-29 on page 881. The AW communicates through a UART operating at variable baud rate (depending on a sync pattern) with one start bit, 8 data bits (LSB first), one stop bit, and no parity bits. The aWire protocol is based upon command packets from an externalmaster and response packets from the slave (AW). The master always initiates communication and decides the baud rate. The packet contains a sync byte (0x55), a command/response byte, two length bytes (optional), a number of data bytes as defined in the length field (optional), and two CRC bytes. If the command/response has the most significant bit set, the command/response also carries the optional length and data fields. The CRC field is not checked if the CRC value transmitted is 0x0000. Table 34-30. aWire Packet Format Field Number of bytes Description Comment Optional SYNC 1 Sync pattern (0x55). Used by the receiver to set the baud rate clock. No COMMAND/ RESPONSE 1 Command from the master or response from the slave. When the most significant bit is set the command/response has a length field. A response has the next most significant bit set. A command does not have this bit set. No 883 32142D–06/2013 ATUC64/128/256L3/4U CRC calculation The CRC is calculated from the command/response, length, and data fields. The polynomial used is the FCS16 (or CRC-16-CCIT) in reverse mode (0x8408) and the starting value is 0x0000. Example command Below is an example command from the master with additional data. Figure 34-9. Example Command Example response Below is an example response from the slave with additional data. Figure 34-10. Example Response LENGTH 2 The number of bytes in the DATA field. Yes DATA LENGTH Data according to command/ response. Yes CRC 2 CRC calculated with the FCS16 polynomial. CRC value of 0x0000 makes the aWire disregard the CRC if the master does not support it. No Table 34-30. aWire Packet Format Field Number of bytes Description Comment Optional baud_rate_clk data_pin ... field sync(0x55) command(0x81) length(MSB) length(lsb) ... data(MSB) data(LSB) CRC(MSB) CRC(lsb) baud_rate_clk data_pin ... field sync(0x55) response(0xC1) length(MSB) length(lsb) ... data(MSB) data(LSB) CRC(MSB) CRC(lsb) 884 32142D–06/2013 ATUC64/128/256L3/4U Avoiding drive contention when changing direction The aWire debug protocol uses one dataline in both directions. To avoid both the master and the slave to drive this line when changing direction the AW has a built in guard time before it starts to drive the line. At reset this guard time is set to maximum (128 bit cycles), but can be lowered by the master upon command. The AW will release the line immediately after the stop character has been transmitted. During the direction change there can be a period when the line is not driven. An external pullup has to be added to RESET_N to keep the signal stable when neither master or slave is actively driving the line. 34.6.6.2 The RESET_N pin Normal reset functionality on the RESET_N pin is disabled when using aWire. However, the user can reset the system through the RESET aWire command. During aWire operation the RESET_N pin should not be connected to an external reset circuitry, but disconnected via a switch or a jumper to avoid drive contention and speed problems. Figure 34-11. Reset Circuitry and aWire. 34.6.6.3 Initializing the AW To enable AW, the user has to send a 0x55 pattern with a baudrate of 1 kHz on the RESET_N pin. The AW is enabled after transmitting this pattern and the user can start transmitting commands. This pattern is not the sync pattern for the first command. After enabling the aWire debug interface the halt bit is set automatically to prevent the system from running code after the interface is enabled. To make the CPU run again set halt to zero using the HALT command. 34.6.6.4 Disabling the AW To disable AW, the user can keep the RESET_N pin low for 100 ms. This will disable the AW, return RESET_N to its normal function, and reset the device. An aWire master can also disable aWire by sending the DISABLE command. After acking the command the AW will be disabled and RESET_N returns to its normal function. RESET_N AW Debug Interface Jumper MCU Power Manager aWire master connector Board Reset Circuitry 885 32142D–06/2013 ATUC64/128/256L3/4U 34.6.6.5 Resetting the AW The aWire master can reset the AW slave by pulling the RESET_N pin low for 20 ms. This is equivalent to disabling and then enabling AW. 34.6.6.6 2-pin Mode To avoid using special hardware when using a normal UART device as aWire master, the aWire slave has a 2-pin mode where one pin is used as input and on pin is used as output. To enable this mode the 2_PIN_MODE command must be sent. After sending the command, all responses will be sent on the DATAOUT pin instead of the RESET_N pin. Commands are still received on the RESET_N pin. 34.6.6.7 Baud Rate Clock The communication speed is set by the master in the sync field of the command. The AW will use this to resynchronize its baud rate clock and reply on this frequency. The minimum frequency of the communication is 1 kHz. The maximum frequency depends on the internal clock source for the AW (RC120M). The baud rate clock is generated by AW with the following formula: Where is the baud rate frequency and is the frequency of the internal RC120M. TUNE is the value returned by the BAUD_RATE response. To find the max frequency the user can issue the TUNE command to the AW to make it return the TUNE value. This value can be used to compute the . The maximum operational frequency ( ) is then: 34.6.6.8 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the aWire through a bus master module, which also handles synchronization between the aWire and SAB clocks. For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. SAB Clock When accessing the SAB through the aWire there are no limitations on baud rate frequency compared to chip frequency, although there must be an active system clock in order for the SAB accesses to complete. If the system clock (CLK_SYS) is switched off in sleep mode, activity on the aWire pin will restart the CLK_SYS automatically, without waking the device from sleep. aWire masters may optimize the transfer rate by adjusting the baud rate frequency in relation to the CLK_SYS. This ratio can be measured with the MEMORY_SPEED_REQUEST command. When issuing the MEMORY_SPEED_REQUEST command a counter value CV is returned. CV can be used to calculate the SAB speed ( ) using this formula: f aw TUNE f  br 8 = ---------------------------- f br f aw f aw f brmax f brmax f aw 4 = ------- f sab 886 32142D–06/2013 ATUC64/128/256L3/4U SAB Address Mode The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. Two instructions exist to access the SAB: MEMORY_WRITE and MEMORY_READ. These two instructions write and read words, halfwords, and bytes from the SAB. Busy Reporting If the aWire master, during a MEMORY_WRITE or a MEMORY_READ command, transmit another byte when the aWire is still busy sending the previous byte to the SAB, the AW will respond with a MEMORY_READ_WRITE_STATUS error. See chapter Section 34.6.8.5 for more details. The aWire master should adjust its baudrate or delay between bytes when doing SAB accesses to ensure that the SAB is not overwhelmed with data. Error Reporting If a write is performed on a non-existing memory location the SAB interface will respond with an error. If this happens, all further writes in this command will not be performed and the error and number of bytes written is reported in the MEMORY_READWRITE_STATUS message from the AW after the write. If a read is performed on a non-existing memory location, the SAB interface will respond with an error. If this happens, the data bytes read after this event are not valid. The AW will include three extra bytes at the end of the transfer to indicate if the transfer was successful, or in the case of an error, how many valid bytes were received. 34.6.6.9 CRC Errors/NACK Response The AW will calculate a CRC value when receiving the command, length, and data fields of the command packets. If this value differs from the value from the CRC field of the packet, the AW will reply with a NACK response. Otherwise the command is carried out normally. An unknown command will be replied with a NACK response. In worst case a transmission error can happen in the length or command field of the packet. This can lead to the aWire slave trying to receive a command with or without length (opposite of what the master intended) or receive an incorrect number of bytes. The aWire slave will then either wait for more data when the master has finished or already have transmitted the NACK response in congestion with the master. The master can implement a timeout on every command and reset the slave if no response is returned after the timeout period has ended. f sab 3f aw CV – 3 = ---------------- 887 32142D–06/2013 ATUC64/128/256L3/4U 34.6.7 aWire Command Summary The implemented aWire commands are shown in the table below. The responses from the AW are listed in Section 34.6.8. All aWire commands are described below, with a summary in table form. 34.6.7.1 AYA This command asks the AW: “Are you alive”, where the AW should respond with an acknowledge. Table 34-31. aWire Command Summary COMMAND Instruction Description 0x01 AYA “Are you alive”. 0x02 JTAG_ID Asks AW to return the JTAG IDCODE. 0x03 STATUS_REQUEST Request a status message from the AW. 0x04 TUNE Tell the AW to report the current baud rate. 0x05 MEMORY_SPEED_REQUEST Reports the speed difference between the aWire control and the SAB clock domains. 0x06 CHIP_ERASE Erases the flash and all volatile memories. 0x07 DISABLE Disables the AW. 0x08 2_PIN_MODE Enables the DATAOUT pin and puts the aWire in 2-pin mode, where all responses are sent on the DATAOUT pin. 0x80 MEMORY_WRITE Writes words, halfwords, or bytes to the SAB. 0x81 MEMORY_READ Reads words, halfwords, or bytes from the SAB. 0x82 HALT Issues a halt command to the device. 0x83 RESET Issues a reset to the Reset Controller. 0x84 SET_GUARD_TIME Sets the guard time for the AW. Table 34-32. Command/Response Description Notation Command/Response Description Command/Response value Shows the command/response value to put into the command/response field of the packet. Additional data Shows the format of the optional data field if applicable. Possible responses Shows the possible responses for this command. Table 34-33. AYA Details Command Details Command value 0x01 Additional data N/A Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) 888 32142D–06/2013 ATUC64/128/256L3/4U 34.6.7.2 JTAG_ID This command instructs the AW to output the JTAG idcode in the following response. 34.6.7.3 STATUS_REQUEST Asks the AW for a status message. 34.6.7.4 TUNE Asks the AW for the current baud rate counter value. 34.6.7.5 MEMORY_SPEED_REQUEST Asks the AW for the relative speed between the aWire clock (RC120M) and the SAB interface. 34.6.7.6 CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in the chip. This will also clear any security bits that are set, so the device can be accessed normally. The command is acked immediately, but the status of the command can be monitored by checking Table 34-34. JTAG_ID Details Command Details Command value 0x02 Additional data N/A Possible responses 0xC0: IDCODE (Section 34.6.8.3) 0x41: NACK (Section 34.6.8.2) Table 34-35. STATUS_REQUEST Details Command Details Command value 0x03 Additional data N/A Possible responses 0xC4: STATUS_INFO (Section 34.6.8.7) 0x41: NACK (Section 34.6.8.2) Table 34-36. TUNE Details Command Details Command value 0x04 Additional data N/A Possible responses 0xC3: BAUD_RATE (Section 34.6.8.6) 0x41: NACK (Section 34.6.8.2) Table 34-37. MEMORY_SPEED_REQUEST Details Command Details Command value 0x05 Additional data N/A Possible responses 0xC5: MEMORY_SPEED (Section 34.6.8.8) 0x41: NACK (Section 34.6.8.2) 889 32142D–06/2013 ATUC64/128/256L3/4U the Chip Erase ongoing bit in the status bytes received after the STATUS_REQUEST command. 34.6.7.7 DISABLE Disables the AW. The AW will respond with an ACK response and then disable itself. 34.6.7.8 2_PIN_MODE Enables the DATAOUT pin as an output pin. All responses sent from the aWire slave will be sent on this pin, instead of the RESET_N pin, starting with the ACK for the 2_PIN_MODE command. 34.6.7.9 MEMORY_WRITE This command enables programming of memory/writing to registers on the SAB. The MEMORY_WRITE command allows words, halfwords, and bytes to be programmed to a continuous sequence of addresses in one operation. Before transferring the data, the user must supply: 1. The number of data bytes to write + 5 (size and starting address) in the length field. 2. The size of the transfer: words, halfwords, or bytes. 3. The starting address of the transfer. Table 34-38. CHIP_ERASE Details Command Details Command value 0x06 Additional data N/A Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) Table 34-39. DISABLE Details Command Details Command value 0x07 Additional data N/A Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) Table 34-40. DISABLE Details Command Details Command value 0x07 Additional data N/A Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) 890 32142D–06/2013 ATUC64/128/256L3/4U The 4 MSB of the 36 bit SAB address are submitted together with the size field (2 bits). Then follows the 4 remaining address bytes and finally the data bytes. The size of the transfer is specified using the values from the following table: Below is an example write command: 1. 0x55 (sync) 2. 0x80 (command) 3. 0x00 (length MSB) 4. 0x09 (length LSB) 5. 0x25 (size and address MSB, the two MSB of this byte are unused and set to zero) 6. 0x00 7. 0x00 8. 0x00 9. 0x04 (address LSB) 10. 0xCA 11. 0xFE 12. 0xBA 13. 0xBE 14. 0xXX (CRC MSB) 15. 0xXX (CRC LSB) The length field is set to 0x0009 because there are 9 bytes of additional data: 5 address and size bytes and 4 bytes of data. The address and size field indicates that words should be written to address 0x500000004. The data written to 0x500000004 is 0xCAFEBABE. 34.6.7.10 MEMORY_READ This command enables reading of memory/registers on the Service Access Bus (SAB). The MEMORY_READ command allows words, halfwords, and bytes to be read from a continuous sequence of addresses in one operation. The user must supply: Table 34-41. Size Field Decoding Size field Description 00 Byte transfer 01 Halfword transfer 10 Word transfer 11 Reserved Table 34-42. MEMORY_WRITE Details Command Details Command value 0x80 Additional data Size, Address and Data Possible responses 0xC2: MEMORY_READWRITE_STATUS (Section 34.6.8.5) 0x41: NACK (Section 34.6.8.2) 891 32142D–06/2013 ATUC64/128/256L3/4U 1. The size of the data field: 7 (size and starting address + read length indicator) in the length field. 2. The size of the transfer: Words, halfwords, or bytes. 3. The starting address of the transfer. 4. The number of bytes to read (max 65532). The 4 MSB of the 36 bit SAB address are submitted together with the size field (2 bits). The 4 remaining address bytes are submitted before the number of bytes to read. The size of the transfer is specified using the values from the following table: Below is an example read command: 1. 0x55 (sync) 2. 0x81 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0x25 (size and address MSB, the two MSB of this byte are unused and set to zero) 6. 0x00 7. 0x00 8. 0x00 9. 0x04 (address LSB) 10. 0x00 11. 0x04 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The length field is set to 0x0007 because there are 7 bytes of additional data: 5 bytes of address and size and 2 bytes with the number of bytes to read. The address and size field indicates one word (four bytes) should be read from address 0x500000004. Table 34-43. Size Field Decoding Size field Description 00 Byte transfer 01 Halfword transfer 10 Word transfer 11 Reserved Table 34-44. MEMORY_READ Details Command Details Command value 0x81 Additional data Size, Address and Length Possible responses 0xC1: MEMDATA (Section 34.6.8.4) 0xC2: MEMORY_READWRITE_STATUS (Section 34.6.8.5) 0x41: NACK (Section 34.6.8.2) 892 32142D–06/2013 ATUC64/128/256L3/4U 34.6.7.11 HALT This command tells the CPU to halt code execution for safe programming. If the CPU is not halted during programming it can start executing partially loaded programs. To halt the processor, the aWire master should send 0x01 in the data field of the command. After programming the halting can be released by sending 0x00 in the data field of the command. 34.6.7.12 RESET This command resets different domains in the part. The aWire master sends a byte with the reset value. Each bit in the reset value byte corresponds to a reset domain in the chip. If a bit is set the reset is activated and if a bit is not set the reset is released. The number of reset domains and their destinations are identical to the resets described in the JTAG data registers chapter under reset register. 34.6.7.13 SET_GUARD_TIME Sets the guard time value in the AW, i.e. how long the AW will wait before starting its transfer after the master has finished. The guard time can be either 0x00 (128 bit lengths), 0x01 (16 bit lengths), 0x2 (4 bit lengths) or 0x3 (1 bit length). Table 34-45. HALT Details Command Details Command value 0x82 Additional data 0x01 to halt the CPU 0x00 to release the halt and reset the device. Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) Table 34-46. RESET Details Command Details Command value 0x83 Additional data Reset value for each reset domain. The number of reset domains is part specific. Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) Table 34-47. SET_GUARD_TIME Details Command Details Command value 0x84 Additional data Guard time Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) 893 32142D–06/2013 ATUC64/128/256L3/4U 34.6.8 aWire Response Summary The implemented aWire responses are shown in the table below. 34.6.8.1 ACK The AW has received the command successfully and performed the operation. 34.6.8.2 NACK The AW has received the command, but got a CRC mismatch. 34.6.8.3 IDCODE The JTAG idcode for this device. 34.6.8.4 MEMDATA The data read from the address specified by the MEMORY_READ command. The last 3 bytes are status bytes from the read. The first status byte is the status of the command described in the table below. The last 2 bytes are the number of remaining data bytes to be sent in the data field of the packet when the error occurred. If the read was not successful all data bytes after the failure are undefined. A successful word read (4 bytes) will look like this: Table 34-48. aWire Response Summary RESPONSE Instruction Description 0x40 ACK Acknowledge. 0x41 NACK Not acknowledge. Sent after CRC errors and after unknown commands. 0xC0 IDCODE The JTAG idcode. 0xC1 MEMDATA Values read from memory. 0xC2 MEMORY_READWRITE_STATUS Status after a MEMORY_WRITE or a MEMORY_READ command. OK, busy, error. 0xC3 BAUD_RATE The current baudrate. 0xC4 STATUS_INFO Status information. 0xC5 MEMORY_SPEED SAB to aWire speed information. Table 34-49. ACK Details Response Details Response value 0x40 Additional data N/A Table 34-50. NACK Details Response Details Response value 0x41 Additional data N/A Table 34-51. IDCODE Details Response Details Response value 0xC0 Additional data JTAG idcode 894 32142D–06/2013 ATUC64/128/256L3/4U 1. 0x55 (sync) 2. 0xC1 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0xCA (Data MSB) 6. 0xFE 7. 0xBA 8. 0xBE (Data LSB) 9. 0x00 (Status byte) 10. 0x00 (Bytes remaining MSB) 11. 0x00 (Bytes remaining LSB) 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The status is 0x00 and all data read are valid. An unsuccessful four byte read can look like this: 1. 0x55 (sync) 2. 0xC1 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0xCA (Data MSB) 6. 0xFE 7. 0xXX (An error has occurred. Data read is undefined. 5 bytes remaining of the Data field) 8. 0xXX (More undefined data) 9. 0x02 (Status byte) 10. 0x00 (Bytes remaining MSB) 11. 0x05 (Bytes remaining LSB) 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The error occurred after reading 2 bytes on the SAB. The rest of the bytes read are undefined. The status byte indicates the error and the bytes remaining indicates how many bytes were remaining to be sent of the data field of the packet when the error occurred. Table 34-52. MEMDATA Status Byte status byte Description 0x00 Read successful 0x01 SAB busy 0x02 Bus error (wrong address) Other Reserved Table 34-53. MEMDATA Details Response Details Response value 0xC1 Additional data Data read, status byte, and byte count (2 bytes) 895 32142D–06/2013 ATUC64/128/256L3/4U 34.6.8.5 MEMORY_READWRITE_STATUS After a MEMORY_WRITE command this response is sent by AW. The response can also be sent after a MEMORY_READ command if AW encountered an error when receiving the address. The response contains 3 bytes, where the first is the status of the command and the 2 next contains the byte count when the first error occurred. The first byte is encoded this way: 34.6.8.6 BAUD_RATE The current baud rate in the AW. See Section 34.6.6.7 for more details. 34.6.8.7 STATUS_INFO A status message from AW. Table 34-54. MEMORY_READWRITE_STATUS Status Byte status byte Description 0x00 Write successful 0x01 SAB busy 0x02 Bus error (wrong address) Other Reserved Table 34-55. MEMORY_READWRITE_STATUS Details Response Details Response value 0xC2 Additional data Status byte and byte count (2 bytes) Table 34-56. BAUD_RATE Details Response Details Response value 0xC3 Additional data Baud rate Table 34-57. STATUS_INFO Contents Bit number Name Description 15-9 Reserved 8 Protected The protection bit in the internal flash is set. SAB access is restricted. This bit will read as one during reset. 7 SAB busy The SAB bus is busy with a previous transfer. This could indicate that the CPU is running on a very slow clock, the CPU clock has stopped for some reason or that the part is in constant reset. 6 Chip erase ongoing The Chip erase operation has not finished. 5 CPU halted This bit will be set if the CPU is halted. This bit will read as zero during reset. 4-1 Reserved 0 Reset status This bit will be set if AW has reset the CPU using the RESET command. 896 32142D–06/2013 ATUC64/128/256L3/4U 34.6.8.8 MEMORY_SPEED Counts the number of RC120M clock cycles it takes to sync one message to the SAB interface and back again. The SAB clock speed ( ) can be calculated using the following formula: 34.6.9 Security Restrictions When the security fuse in the Flash is programmed, the following aWire commands are limited: • MEMORY_WRITE • MEMORY_READ Unlimited access to these instructions is restored when the security fuse is erased by the CHIP_ERASE aWire command. Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Table 34-58. STATUS_INFO Details Response Details Response value 0xC4 Additional data 2 status bytes Table 34-59. MEMORY_SPEED Details Response Details Response value 0xC5 Additional data Clock cycle count (MS) f sab f sab 3f aw CV – 3 = ---------------- 897 32142D–06/2013 ATUC64/128/256L3/4U 35. Electrical Characteristics 35.1 Absolute Maximum Ratings* Notes: 1. 5V tolerant pins, see Section ”Peripheral Multiplexing on I/O lines” on page 10 2. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section on page 10 for details. 35.2 Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are valid for a junction temperature up to TJ = 100°C. Please refer to Section 6. ”Supply and Startup Considerations” on page 39. Table 35-1. Absolute Maximum Ratings Operating temperature..................................... -40C to +85C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage temperature...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.3V to VVDD(2)+0.3V Voltage on 5V tolerant(1) pins with respect to ground ............... .............................................................................-0.3V to 5.5V Total DC output current on all I/O pins - VDDIO, 64-pin package ............... ......................................................................141 mA Total DC output current on all I/O pins - VDDIN, 64-pin package ....................................................................................... 42 mA Total DC output current on all I/O pins - VDDIO, 48-pin package ........... ...........................................................................120mA Total DC output current on all I/O pins - VDDIN, 48-pin package ....................................................................................... 39 mA Maximum operating voltage VDDCORE......................... 1.98V Maximum operating voltage VDDIO, VDDIN .................... 3.6V Table 35-2. Supply Characteristics Symbol Parameter Voltage Min Max Unit VVDDIO DC supply peripheral I/Os 1.62 3.6 V VVDDIN DC supply peripheral I/Os, 1.8V single supply mode 1.62 1.98 V DC supply peripheral I/Os and internal regulator, 3.3V supply mode 1.98 3.6 V VVDDCORE DC supply core 1.62 1.98 V VVDDANA Analog supply voltage 1.62 1.98 V 898 32142D–06/2013 ATUC64/128/256L3/4U Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.3 Maximum Clock Frequencies These parameters are given in the following conditions: • VVDDCORE = 1.62V to 1.98V • Temperature = -40°C to 85°C 35.4 Power Consumption The values in Table 35-5 are measured values of power consumption under the following conditions, except where noted: • Operating conditions, internal core supply (Figure 35-1) - this is the default configuration – VVDDIN = 3.0V Table 35-3. Supply Rise Rates and Order(1) Symbol Parameter Rise Rate Min Max Unit Comment VVDDIO DC supply peripheral I/Os 0 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.002 2.5 V/µs Slower rise time requires external power-on reset circuit. VVDDCORE DC supply core 0 2.5 V/µs Rise before or at the same time as VDDIO VVDDANA Analog supply voltage 0 2.5 V/µs Rise together with VDDCORE Table 35-4. Clock Frequencies Symbol Parameter Description Min Max Units fCPU CPU clock frequency 50 MHz fPBA PBA clock frequency 50 fPBB PBB clock frequency 50 fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 50 fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSG reference, GCLK1 pin 50 fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 20 fGCLK3 GCLK3 clock frequency PWMA, GCLK3 pin 140 fGCLK4 GCLK4 clock frequency CAT, ACIFB, GCLK4 pin 50 fGCLK5 GCLK5 clock frequency GLOC and GCLK5 pin 80 fGCLK6 GCLK6 clock frequency ABDACB, IISC, and GCLK6 pin 50 fGCLK7 GCLK7 clock frequency USBC and GCLK7 pin 50 fGCLK8 GCLK8 clock frequency PLL0 source clock and GCLK8 pin 50 fGCLK9 GCLK9 clock frequency FREQM, GCLK0-8, GCLK9 pin 150 899 32142D–06/2013 ATUC64/128/256L3/4U – VVDDCORE = 1.62V, supplied by the internal regulator – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details • Equivalent to the 3.3V single supply mode • Consumption in 1.8V single supply mode can be estimated by subtracting the regulator static current • Operating conditions, external core supply (Figure 35-2) - used only when noted – VVDDIN = VVDDCORE = 1.8V – Corresponds to the 1.8V single supply mode, please refer to the Supply and Startup Considerations section for more details • TA = 25C • Oscillators – OSC0 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) running with external 32KHz crystal – DFLL running at 50MHz with OSC32K as reference • Clocks – DFLL used as main clock source – CPU, HSB, and PBB clocks undivided – PBA clock divided by 4 – The following peripheral clocks running • PM, SCIF, AST, FLASHCDW, PBA bridge – All other peripheral clocks stopped • I/Os are inactive with internal pull-up • Flash enabled in high speed mode • POR18 enabled • POR33 disabled 900 32142D–06/2013 ATUC64/128/256L3/4U Note: 1. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies. Figure 35-1. Measurement Schematic, Internal Core Supply Table 35-5. Power Consumption for Different Operating Modes Mode Conditions Measured on Consumption Typ Unit Active(1) CPU running a recursive Fibonacci algorithm Amp0 300 µA/MHz CPU running a division algorithm 174 Idle(1) 96 Frozen(1) 57 Standby(1) 46 Stop 38 µA DeepStop 25 Static -OSC32K and AST stopped -Internal core supply 14 -OSC32K running -AST running at 1KHz -External core supply (Figure 35-2) 7.3 -OSC32K and AST stopped -External core supply (Figure 35-2) 6.7 Shutdown -OSC32K running -AST running at 1KHz 800 nA AST and OSC32K stopped 220 Amp0 VDDIN VDDCORE VDDANA VDDIO 901 32142D–06/2013 ATUC64/128/256L3/4U Figure 35-2. Measurement Schematic, External Core Supply Amp0 VDDIN VDDCORE VDDANA VDDIO 902 32142D–06/2013 ATUC64/128/256L3/4U 35.5 I/O Pin Characteristics Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section on page 10 for details. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Table 35-6. Normal I/O Pin Characteristics(1) Symbol Parameter Condition Min Typ Max Units RPULLUP Pull-up resistance 75 100 145 kOhm VIL Input low-level voltage VVDD = 3.0V -0.3 0.3 * VVDD V VVDD = 1.62V -0.3 0.3 * VVDD VIH Input high-level voltage VVDD = 3.6V 0.7 * VVDD VVDD + 0.3 V VVDD = 1.98V 0.7 * VVDD VVDD + 0.3 VOL Output low-level voltage VVDD = 3.0V, IOL = 3mA 0.4 V VVDD = 1.62V, IOL = 2mA 0.4 VOH Output high-level voltage VVDD = 3.0V, IOH = 3mA VVDD - 0.4 V VVDD = 1.62V, IOH = 2mA VVDD - 0.4 fMAX Output frequency(2) VVDD = 3.0V, load = 10pF 45 MHz VVDD = 3.0V, load = 30pF 23 tRISE Rise time(2) VVDD = 3.0V, load = 10pF 4.7 ns VVDD = 3.0V, load = 30pF 11.5 tFALL Fall time(2) VVDD = 3.0V, load = 10pF 4.8 VVDD = 3.0V, load = 30pF 12 ILEAK Input leakage current Pull-up resistors disabled 1 µA CIN Input capacitance, all normal I/O pins except PA05, PA07, PA17, PA20, PA21, PB04, PB05 TQFP48 package 1.4 pF QFN48 package 1.1 TLLGA48 package 1.1 TQFP64 package 1.5 QFN64 package 1.1 CIN Input capacitance, PA20 TQFP48 package 2.7 QFN48 package 2.4 TLLGA48 package 2.4 TQFP64 package 2.8 QFN64 package 2.4 CIN Input capacitance, PA05, PA07, PA17, PA21, PB04, PB05 TQFP48 package 3.8 QFN48 package 3.5 TLLGA48 package 3.5 TQFP64 package 3.9 QFN64 package 3.5 903 32142D–06/2013 ATUC64/128/256L3/4U Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section on page 10 for details. Table 35-7. High-drive I/O Pin Characteristics(1) Symbol Parameter Condition Min Typ Max Units RPULLUP Pull-up resistance PA06 30 50 110 PA02, PB01, RESET 75 100 145 kOhm PA08, PA09 10 20 45 VIL Input low-level voltage VVDD = 3.0V -0.3 0.3 * VVDD V VVDD = 1.62V -0.3 0.3 * VVDD VIH Input high-level voltage VVDD = 3.6V 0.7 * VVDD VVDD + 0.3 V VVDD = 1.98V 0.7 * VVDD VVDD + 0.3 VOL Output low-level voltage VVDD = 3.0V, IOL = 6mA 0.4 V VVDD = 1.62V, IOL = 4mA 0.4 VOH Output high-level voltage VVDD = 3.0V, IOH = 6mA VVDD - 0.4 V VVDD = 1.62V, IOH = 4mA VVDD - 0.4 fMAX Output frequency, all High-drive I/O pins, except PA08 and PA09(2) VVDD = 3.0V, load = 10pF 45 MHz VVDD = 3.0V, load = 30pF 23 tRISE Rise time, all High-drive I/O pins, except PA08 and PA09(2) VVDD = 3.0V, load = 10pF 4.7 ns VVDD = 3.0V, load = 30pF 11.5 tFALL Fall time, all High-drive I/O pins, except PA08 and PA09(2) VVDD = 3.0V, load = 10pF 4.8 VVDD = 3.0V, load = 30pF 12 fMAX Output frequency, PA08 and PA09(2) VVDD = 3.0V, load = 10pF 54 MHz VVDD = 3.0V, load = 30pF 40 tRISE Rise time, PA08 and PA09(2) VVDD = 3.0V, load = 10pF 2.8 ns VVDD = 3.0V, load = 30pF 4.9 tFALL Fall time, PA08 and PA09(2) VVDD = 3.0V, load = 10pF 2.4 VVDD = 3.0V, load = 30pF 4.6 ILEAK Input leakage current Pull-up resistors disabled 1 µA CIN Input capacitance, all High-drive I/O pins, except PA08 and PA09 TQFP48 package 2.2 pF QFN48 package 2.0 TLLGA48 package 2.0 TQFP64 package 2.3 QFN64 package 2.0 CIN Input capacitance, PA08 and PA09 TQFP48 package 7.0 QFN48 package 6.7 TLLGA48 package 6.7 TQFP64 package 7.1 QFN64 package 6.7 904 32142D–06/2013 ATUC64/128/256L3/4U 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section on page 10 for details. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Table 35-8. High-drive I/O, 5V Tolerant, Pin Characteristics(1) Symbol Parameter Condition Min Typ Max Units RPULLUP Pull-up resistance 30 50 110 kOhm VIL Input low-level voltage VVDD = 3.0V -0.3 0.3 * VVDD V VVDD = 1.62V -0.3 0.3 * VVDD VIH Input high-level voltage VVDD = 3.6V 0.7 * VVDD 5.5 V VVDD = 1.98V 0.7 * VVDD 5.5 VOL Output low-level voltage VVDD = 3.0V, IOL = 6mA 0.4 V VVDD = 1.62V, IOL = 4mA 0.4 VOH Output high-level voltage VVDD = 3.0V, IOH = 6mA VVDD - 0.4 V VVDD = 1.62V, IOH = 4mA VVDD - 0.4 fMAX Output frequency(2) VVDD = 3.0V, load = 10pF 87 MHz VVDD = 3.0V, load = 30pF 58 tRISE Rise time(2) VVDD = 3.0V, load = 10pF 2.3 ns VVDD = 3.0V, load = 30pF 4.3 tFALL Fall time(2) VVDD = 3.0V, load = 10pF 1.9 VVDD = 3.0V, load = 30pF 3.7 ILEAK Input leakage current 5.5V, pull-up resistors disabled 10 µA CIN Input capacitance TQFP48 package 4.5 pF QFN48 package 4.2 TLLGA48 package 4.2 TQFP64 package 4.6 QFN64 package 4.2 Table 35-9. TWI Pin Characteristics(1) Symbol Parameter Condition Min Typ Max Units RPULLUP Pull-up resistance 25 35 60 kOhm VIL Input low-level voltage VVDD = 3.0V -0.3 0.3 * VVDD V VVDD = 1.62V -0.3 0.3 * VVDD VIH Input high-level voltage VVDD = 3.6V 0.7 * VVDD VVDD + 0.3 V VVDD = 1.98V 0.7 * VVDD VVDD + 0.3 Input high-level voltage, 5V tolerant SMBUS compliant pins VVDD = 3.6V 0.7 * VVDD 5.5 V VVDD = 1.98V 0.7 * VVDD 5.5 905 32142D–06/2013 ATUC64/128/256L3/4U Note: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section on page 10 for details. 35.6 Oscillator Characteristics 35.6.1 Oscillator 0 (OSC0) Characteristics 35.6.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.6.1.2 Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 35-3. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL VOL Output low-level voltage IOL = 3mA 0.4 V ILEAK Input leakage current Pull-up resistors disabled 1 IIL Input low leakage 1 µA IIH Input high leakage 1 CIN Input capacitance TQFP48 package 3.8 pF QFN48 package 3.5 TLLGA48 package 3.5 TQFP64 package 3.9 QFN64 package 3.5 tFALL Fall time Cbus = 400pF, VVDD > 2.0V 250 ns Cbus = 400pF, VVDD > 1.62V 470 fMAX Max frequency Cbus = 400pF, VVDD > 2.0V 400 kHz Table 35-9. TWI Pin Characteristics(1) Symbol Parameter Condition Min Typ Max Units Table 35-10. Digital Clock Characteristics Symbol Parameter Conditions Min Typ Max Units fCPXIN XIN clock frequency 50 MHz tCPXIN XIN clock duty cycle(1) 40 60 % tSTARTUP Startup time 0 cycles CIN XIN input capacitance TQFP48 package 7.0 pF QFN48 package 6.7 TLLGA48 package 6.7 TQFP64 package 7.1 QFN64 package 6.7 906 32142D–06/2013 ATUC64/128/256L3/4U can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: where CPCB is the capacitance of the PCB and Ci is the internal equivalent load capacitance. Notes: 1. Please refer to the SCIF chapter for details. 2. Nominal crystal cycles. 3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Figure 35-3. Oscillator Connection CLEXT 2 CL Ci   – CPCB = – Table 35-11. Crystal Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Crystal oscillator frequency(3) 0.45 10 16 MHz CL Crystal load capacitance(3) 6 18 pF Ci Internal equivalent load capacitance 2 tSTARTUP Startup time SCIF.OSCCTRL.GAIN = 2(1) 30 000(2) cycles IOSC Current consumption Active mode, f = 0.45MHz, SCIF.OSCCTRL.GAIN = 0 30 µA Active mode, f = 10MHz, SCIF.OSCCTRL.GAIN = 2 220 XIN XOUT CLEXT CLEXT CL Ci UC3L 907 32142D–06/2013 ATUC64/128/256L3/4U 35.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 35-3 and the equation above also applies to the 32KHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. Notes: 1. Nominal crystal cycles. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.6.3 Phase Locked Loop (PLL) Characteristics Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Table 35-12. 32 KHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Crystal oscillator frequency 32 768 Hz tSTARTUP Startup time RS = 60kOhm, CL = 9pF 30 000(1) cycles CL Crystal load capacitance(2) 6 12.5 pF Ci Internal equivalent load capacitance 2 IOSC32 Current consumption 0.6 µA RS Equivalent series resistance(2) 32 768Hz 35 85 kOhm Table 35-13. Phase Locked Loop Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency(1) 40 240 MHz fIN Input frequency(1) 4 16 IPLL Current consumption 8 µA/MHz tSTARTUP Startup time, from enabling the PLL until the PLL is locked fIN= 4MHz 200 µs fIN= 16MHz 155 908 32142D–06/2013 ATUC64/128/256L3/4U 35.6.4 Digital Frequency Locked Loop (DFLL) Characteristics Notes: 1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the DFLL0SSG register. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 3. The FINE and COARSE values are selected by wrirting to the DFLL0VAL.FINE and DFLL0VAL.COARSE field respectively. Table 35-14. Digital Frequency Locked Loop Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency(2) 20 150 MHz fREF Reference frequency(2) 8 150 kHz FINE resolution step FINE > 100, all COARSE values (3) 0.38 % Frequency drift over voltage and temperature Open loop mode See Figure 35-4 Accuracy(2) FINE lock, fREF = 32kHz, SSG disabled 0.1 0.5 % ACCURATE lock, fREF = 32kHz, dither clk RCSYS/2, SSG disabled 0.06 0.5 FINE lock, fREF = 8-150kHz, SSG disabled 0.2 1 ACCURATE lock, fREF = 8-150kHz, dither clk RCSYS/2, SSG disabled 0.1 1 IDFLL Power consumption 25 µA/MHz tSTARTUP Startup time(2) Within 90% of final values 100 µs tLOCK Lock time fREF = 32kHz, FINE lock, SSG disabled 8 ms fREF = 32kHz, ACCURATE lock, dithering clock = RCSYS/2, SSG disabled 28 909 32142D–06/2013 ATUC64/128/256L3/4U Figure 35-4. DFLL Open Loop Frequency Variation(1)(2) Notes: 1. The plot shows a typical open loop mode behavior with COARSE= 99 and FINE= 255. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.6.5 120MHz RC Oscillator (RC120M) Characteristics Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. DFLL Open Loop Frequency variation 80 90 100 110 120 130 140 150 160 -40 -20 0 20 40 60 80 Temperature Frequencies (MHz) 1,98V 1,8V 1.62V Table 35-15. Internal 120MHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency(1) 88 120 152 MHz IRC120M Current consumption 1.2 mA tSTARTUP Startup time(1) VVDDCORE = 1.8V 3 µs 910 32142D–06/2013 ATUC64/128/256L3/4U 35.6.6 32kHz RC Oscillator (RC32K) Characteristics Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.6.7 System RC Oscillator (RCSYS) Characteristics 35.7 Flash Characteristics Table 35-18 gives the device maximum operating frequency depending on the number of flash wait states and the flash read mode. The FSW bit in the FLASHCDW FSR register controls the number of wait states used when accessing the flash memory. Table 35-16. 32kHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency(1) 20 32 44 kHz IRC32K Current consumption 0.7 µA tSTARTUP Startup time(1) 100 µs Table 35-17. System RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency Calibrated at 85C 111.6 115 118.4 kHz Table 35-18. Maximum Operating Frequency Flash Wait States Read Mode Maximum Operating Frequency 1 High speed read mode 50MHz 0 25MHz 1 Normal read mode 30MHz 0 15MHz Table 35-19. Flash Characteristics Symbol Parameter Conditions Min Typ Max Unit tFPP Page programming time fCLK_HSB = 50MHz 5 ms tFPE Page erase time 5 tFFP Fuse programming time 1 tFEA Full chip erase time (EA) 6 tFCE JTAG chip erase time (CHIP_ERASE) fCLK_HSB = 115kHz 310 911 32142D–06/2013 ATUC64/128/256L3/4U 35.8 ABDACB Electrical Characteristics. Notes: 1. Test Condition: Common Mode Offset Control disabled (CR.CMOC = 0). Alternative Upsampling Ratio disabled (CR.ALTUPR = 0). Volume at maximum level (VCR0.VOLUME = 0x7FFF and VCR1.VOLUME = 0x7FFF). Device is battery powered (9V) through an LDO, VDDIO at 3.3V. Analog low pass filter as shown in Figure 35-5(1. order differential low pass filter followed by a 4. order low-pass), +VCC at +9V and -VCC at -9V. Test signal stored on a SD card and read by the SPI Interface. 2. Performance numbers for dynamic range, SNR, and THD performance are very dependent on the application and circuit board design. Since the design has 0dB Power Supply Rejection Ratio (PSRR), noise on the IO power supply will couple directly through to the output and be present in the audio signal. To get the best performance one should reduce toggling of other IO pins as much as possible and make sure the device has sufficient decoupling on the IO supply pins. 3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Figure 35-5. Differential Analog Low-pass Filter Table 35-20. Flash Endurance and Data Retention Symbol Parameter Conditions Min Typ Max Unit NFARRAY Array endurance (write/page) 100k cycles NFFUSE General Purpose fuses endurance (write/bit) 10k tRET Data retention 15 years Table 35-21. ABDACB Electrical Characteristics Symbol Parameter Conditions MIN TYP MAX Unit Resolution 16 Bits Dynamic range(1)(2)(3) FS = 48.000kHz > 76 dB SNR(1)(2)(3) FS = 48.000kHz > 46 dB THD(1)(2)(3) FS = 48.000kHz < 0.02 % PSRR 0 dB VOut maximum CR.CMOC = 0 97/128 * VDDIO V VOut minimum CR.CMOC = 0 31/128 * VDDIO V Common mode CR.CMOC = 0 CR.CMOC = 1, DAC_0 and DAC_1 pins CR.CMOC = 1, DACN_0 and DACN_1 pins 64/128 * VDDIO 80/128 * VDDIO 48/128 * VDDIO V R1, 22K C2 140p R2, 22K R4, 22K C1, 140p R3, 22K R6, 22K R5, 22K R7, 22K C4 270p C3 310p -Vcc +Vcc -Vcc +Vcc DAC DACN R8, 22K R9, 22K C6 110p C5 750p -Vcc +Vcc GND GND GND GND GND Out 912 32142D–06/2013 ATUC64/128/256L3/4U 35.9 Analog Characteristics 35.9.1 Voltage Regulator Characteristics Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Note: 1. Refer to Section 6.1.2 on page 39. Table 35-22. VREG Electrical Characteristics Symbol Parameter Condition Min Typ Max Units VVDDIN Input voltage range 1.98 3.3 3.6 V VVDDCORE Output voltage, calibrated value VVDDIN >= 1.98V 1.8 Output voltage accuracy(1) IOUT = 0.1mA to 60mA, VVDDIN > 1.98V 2 % IOUT = 0.1mA to 60mA, VVDDIN <1.98V 4 IOUT DC output current(1) Normal mode 60 mA Low power mode 1 IVREG Static current of internal regulator Normal mode 13 µA Low power mode 4 Table 35-23. Decoupling Requirements Symbol Parameter Condition Typ Techno. Units CIN1 Input regulator capacitor 1 33 nF CIN2 Input regulator capacitor 2 100 CIN3 Input regulator capacitor 3 10 µF COUT1 Output regulator capacitor 1 100 nF COUT2 Output regulator capacitor 2 2.2 Tantalum 0.5 3.0V, fADC = 6MHz, 12-bit resolution mode, low impedance source 28 kSPS VVDD > 3.0V, fADC = 6MHz, 10-bit resolution mode, low impedance source 460 VVDD > 3.0V, fADC = 6MHz, 8-bit resolution mode, low impedance source 460 VADVREFP Reference voltage range VADVREFP = VVDDANA 1.62 1.98 V IADC Current consumption on VVDDANA ADC Clock = 6MHz 350 µA IADVREFP Current consumption on ADVREFP pin fADC = 6MHz 150 Table 35-30. Analog Inputs Symbol Parameter Conditions Min Typ Max Units VADn Input Voltage Range 12-bit mode 10-bit mode 0 VADVREFP V 8-bit mode CONCHIP Internal Capacitance(1) 22.5 pF RONCHIP Internal Resistance(1) VVDDIO = 3.0V to 3.6V, VVDDCORE = 1.8V 3.15 kOhm VVDDIO = VVDDCORE = 1.62V to 1.98V 55.9 RONCHIP CONCHIP RSOURCE 917 32142D–06/2013 ATUC64/128/256L3/4U ( ) of the PCB and source must be taken into account when calculating the required sample and hold time. Figure 35-8 shows the ADC input channel equivalent circuit. Figure 35-8. ADC Input The minimum sample and hold time (in ns) can be found using this formula: Where n is the number of bits in the conversion. is defined by the SHTIM field in the ADCIFB ACR register. Please refer to the ADCIFB chapter for more information. 35.9.6.2 Applicable Conditions and Derating Data Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. CSOURCE ADCVREFP/2 CONCHIP RONCHIP R Positive Input SOURCE CSOURCE VIN t SAMPLEHOLD RONCHIP + RSOURCE   CONCHIP CSOURCE    + 2n + 1   ln  t SAMPLEHOLD Table 35-31. Transfer Characteristics 12-bit Resolution Mode(1) Parameter Conditions Min Typ Max Units Resolution 12 Bit Integral non-linearity ADC clock frequency = 6MHz, Input Voltage Range = 0 - VADVREFP +/-4 LSB ADC clock frequency = 6MHz, Input Voltage Range = (10% VADVREFP) - (90% VADVREFP) +/-2 Differential non-linearity ADC clock frequency = 6MHz -1.5 1.5 Offset error +/-3 Gain error +/-5 Table 35-32. Transfer Characteristics, 10-bit Resolution Mode(1) Parameter Conditions Min Typ Max Units Resolution 10 Bit Integral non-linearity ADC clock frequency = 6MHz +/-1 LSB Differential non-linearity -1.0 1.0 Offset error +/-1 Gain error +/-2 918 32142D–06/2013 ATUC64/128/256L3/4U Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.9.7 Temperature Sensor Characteristics Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy. Table 35-33. Transfer Characteristics, 8-bit Resolution Mode(1) Parameter Conditions Min Typ Max Units Resolution 8 Bit Integral non-linearity ADC clock frequency = 6MHz +/-0.5 LSB Differential non-linearity -0.3 0.3 Offset error +/-1 Gain error +/-1 Table 35-34. Temperature Sensor Characteristics(1) Symbol Parameter Condition Min Typ Max Units Gradient 1 mV/°C ITS Current consumption 1 µA tSTARTUP Startup time 0 µs 919 32142D–06/2013 ATUC64/128/256L3/4U 35.9.8 Analog Comparator Characteristics Notes: 1. AC.CONFn.FLEN and AC.CONFn.HYS fields, refer to the Analog Comparator Interface chapter. 2. Referring to fAC. 3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.9.9 Capacitive Touch Characteristics 35.9.9.1 Discharge Current Source Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Table 35-35. Analog Comparator Characteristics Symbol Parameter Condition Min Typ Max Units Positive input voltage range(3) -0.2 VVDDIO + 0.3 V Negative input voltage range(3) -0.2 VVDDIO - 0.6 Statistical offset(3) VACREFN = 1.0V, fAC = 12MHz, filter length = 2, hysteresis = 0(1) 20 mV fAC Clock frequency for GCLK4(3) 12 MHz Throughput rate(3) fAC = 12MHz 12 000 000 Comparisons per second Propagation delay Delay from input change to Interrupt Status Register Changes ns IAC Current consumption(3) All channels, VDDIO = 3.3V, fA = 3MHz 420 µA tSTARTUP Startup time 3 cycles Input current per pin(3) 0.2 µA/MHz(2) Table 35-36. DICS Characteristics Symbol Parameter Min Typ Max Unit RREF Internal resistor 170 kOhm k Trim step size(1) 0.7 % 1 t CLKACIFB f AC  ---------------------------------------- + 3     t CLKACIFB  920 32142D–06/2013 ATUC64/128/256L3/4U 35.9.9.2 Strong Pull-up Pull-down 35.9.10 USB Transceiver Characteristics The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications. 35.9.10.1 Electrical Characteristics Table 35-37. Strong Pull-up Pull-down Parameter Min Typ Max Unit Pull-down resistor 1 kOhm Pull-up resistor 1 Table 35-38. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit REXT Recommended external USB series resistor In series with each USB pin with ±5% 39 Ohm 921 32142D–06/2013 ATUC64/128/256L3/4U 35.10 Timing Characteristics 35.10.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula: Where and are found in Table 35-39. is the period of the CPU clock. If a clock source other than RCSYS is selected as the CPU clock, the oscillator startup time, , must be added to the wake-up time from the stop, deepstop, and static sleep modes. Please refer to the source for the CPU clock in the ”Oscillator Characteristics” on page 905 for more details about oscillator startup times. Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.10.2 RESET_N Timing Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. t tCONST NCPU t CPU = +  t CONST NCPU t CPU t OSCSTART Table 35-39. Maximum Reset and Wake-up Timing(1) Parameter Measuring Max (in µs) Max Startup time from power-up, using regulator Time from VDDIN crossing the VPOT+ threshold of POR33 to the first instruction entering the decode stage of CPU. VDDCORE is supplied by the internal regulator. 2210 0 Startup time from power-up, no regulator Time from VDDIN crossing the VPOT+ threshold of POR33 to the first instruction entering the decode stage of CPU. VDDCORE is connected to VDDIN. 1810 0 Startup time from reset release Time from releasing a reset source (except POR18, POR33, and SM33) to the first instruction entering the decode stage of CPU. 170 0 Wake-up Idle From wake-up event to the first instruction of an interrupt routine entering the decode stage of the CPU. 0 19 Frozen 0 110 Standby 0 110 Stop 27 + 116 Deepstop 27 + 116 Static 97 + 116 Wake-up from shutdown From wake-up event to the first instruction entering the decode stage of the CPU. 1180 0 t CONST NCPU t OSCSTART t OSCSTART t OSCSTART Table 35-40. RESET_N Waveform Parameters(1) Symbol Parameter Conditions Min Max Units tRESET RESET_N minimum pulse length 10 ns 922 32142D–06/2013 ATUC64/128/256L3/4U 35.10.3 USART in SPI Mode Timing 35.10.3.1 Master mode Figure 35-9. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) Figure 35-10. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 2. Where: USPI0 USPI1 MISO SPCK MOSI USPI2 USPI3 USPI4 MISO SPCK MOSI USPI5 Table 35-41. USART in SPI Mode Timing, Master Mode(1) Symbol Parameter Conditions Min Max Units USPI0 MISO setup time before SPCK rises VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 28.7 + tSAMPLE(2) ns USPI1 MISO hold time after SPCK rises 0 USPI2 SPCK rising to MOSI delay 16.5 USPI3 MISO setup time before SPCK falls 25.8 + tSAMPLE(2) USPI4 MISO hold time after SPCK falls 0 USPI5 SPCK falling to MOSI delay 21.19 t SAMPLE t SPCK t SPCK 2 t CLKUSART  ------------------------------------ 1 2 --     t CLKUSART = –  923 32142D–06/2013 ATUC64/128/256L3/4U Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock. Maximum SPI Frequency, Master Input The maximum SPI master input frequency is given by the following formula: Where is the MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending on CPOL and NCPHA. is the SPI slave response time. Please refer to the SPI slave datasheet for . is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock. 35.10.3.2 Slave mode Figure 35-11. USART in SPI Slave Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) f SPCKMAX MIN fPINMAX 1 SPIn ------------ f CLKSPI  2 9 = (, )  ---------------------------- SPIn fPINMAX f CLKSPI f SPCKMAX MIN 1 SPIn tVALID + ----------------------------------- f CLKSPI  2 9 = ( ,) ----------------------------- SPIn TVALID TVALID f CLKSPI USPI7 USPI8 MISO SPCK MOSI USPI6 924 32142D–06/2013 ATUC64/128/256L3/4U Figure 35-12. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) Figure 35-13. USART in SPI Slave Mode, NPCS Timing Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 2. Where: USPI10 USPI11 MISO SPCK MOSI USPI9 USPI14 USPI12 USPI15 USPI13 NSS SPCK, CPOL=0 SPCK, CPOL=1 Table 35-42. USART in SPI mode Timing, Slave Mode(1) Symbol Parameter Conditions Min Max Units USPI6 SPCK falling to MISO delay VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 37.3 ns USPI7 MOSI setup time before SPCK rises 2.6 + tSAMPLE(2) + tCLK_USART USPI8 MOSI hold time after SPCK rises 0 USPI9 SPCK rising to MISO delay 37.0 USPI10 MOSI setup time before SPCK falls 2.6 + tSAMPLE(2) + tCLK_USART USPI11 MOSI hold time after SPCK falls 0 USPI12 NSS setup time before SPCK rises 27.2 USPI13 NSS hold time after SPCK falls 0 USPI14 NSS setup time before SPCK falls 27.2 USPI15 NSS hold time after SPCK rises 0 t SAMPLE t SPCK t SPCK 2 tCLKUSART  ------------------------------------ 1 2 + --     t CLKUSART = –  925 32142D–06/2013 ATUC64/128/256L3/4U Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: Where is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending on CPOL and NCPHA. is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave output frequency is given by the following formula: Where is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. is the SPI master setup time. Please refer to the SPI master datasheet for . is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock. is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. 35.10.4 SPI Timing 35.10.4.1 Master mode Figure 35-14. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) f SPCKMAX MIN f CLKSPI  2 9 ----------------------------- 1 SPIn = ( ,) ------------ SPIn f CLKSPI f SPCKMAX MIN f CLKSPI  2 9 ---------------------------- f PINMAX  1 SPIn tSETUP + = ( ,) ------------------------------------ SPIn TSETUP TSETUP f CLKSPI f PINMAX SPI0 SPI1 MISO SPCK MOSI SPI2 926 32142D–06/2013 ATUC64/128/256L3/4U Figure 35-15. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. Maximum SPI Frequency, Master Input The maximum SPI master input frequency is given by the following formula: Where is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on CPOL and NCPHA. is the SPI slave response time. Please refer to the SPI slave datasheet for . SPI3 SPI4 MISO SPCK MOSI SPI5 Table 35-43. SPI Timing, Master Mode(1) Symbol Parameter Conditions Min Max Units SPI0 MISO setup time before SPCK rises VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 33.4 + (tCLK_SPI)/2 ns SPI1 MISO hold time after SPCK rises 0 SPI2 SPCK rising to MOSI delay 7.1 SPI3 MISO setup time before SPCK falls 29.2 + (tCLK_SPI)/2 SPI4 MISO hold time after SPCK falls 0 SPI5 SPCK falling to MOSI delay 8.63 f SPCKMAX MIN fPINMAX 1 SPIn = ( ,) ------------ SPIn f PINMAX f SPCKMAX 1 SPIn tVALID + = ----------------------------------- SPIn t VALID tVALID 927 32142D–06/2013 ATUC64/128/256L3/4U 35.10.4.2 Slave mode Figure 35-16. SPI Slave Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) Figure 35-17. SPI Slave Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) Figure 35-18. SPI Slave Mode, NPCS Timing SPI7 SPI8 MISO SPCK MOSI SPI6 SPI10 SPI11 MISO SPCK MOSI SPI9 SPI14 SPI12 SPI15 SPI13 NPCS SPCK, CPOL=0 SPCK, CPOL=1 928 32142D–06/2013 ATUC64/128/256L3/4U Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: Where is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on CPOL and NCPHA. is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave output frequency is given by the following formula: Where is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. is the SPI master setup time. Please refer to the SPI master datasheet for . is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. 35.10.5 TWIM/TWIS Timing Figure 35-45 shows the TWI-bus timing requirements and the compliance of the device with them. Some of these requirements (tr and tf ) are met by the device without requiring user intervention. Compliance with the other requirements (tHD-STA, tSU-STA, tSU-STO, tHD-DAT, tSU-DAT-TWI, tLOWTWI, tHIGH, and fTWCK) requires user intervention through appropriate programming of the relevant Table 35-44. SPI Timing, Slave Mode(1) Symbol Parameter Conditions Min Max Units SPI6 SPCK falling to MISO delay VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 29.4 ns SPI7 MOSI setup time before SPCK rises 0 SPI8 MOSI hold time after SPCK rises 6.0 SPI9 SPCK rising to MISO delay 29.0 SPI10 MOSI setup time before SPCK falls 0 SPI11 MOSI hold time after SPCK falls 5.5 SPI12 NPCS setup time before SPCK rises 3.4 SPI13 NPCS hold time after SPCK falls 1.1 SPI14 NPCS setup time before SPCK falls 3.3 SPI15 NPCS hold time after SPCK rises 0.7 f SPCKMAX MIN fCLKSPI 1 SPIn = ( ,) ------------ SPIn f CLKSPI f SPCKMAX MIN fPINMAX 1 SPIn tSETUP + = (, ) ------------------------------------ SPIn t SETUP t SETUP fPINMAX 929 32142D–06/2013 ATUC64/128/256L3/4U TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information. Notes: 1. Standard mode: ; fast mode: . 2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK. Notations: Cb = total capacitance of one bus line in pF tclkpb = period of TWI peripheral bus clock tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW-TWI) of TWCK. Table 35-45. TWI-Bus Timing Requirements Symbol Parameter Mode Minimum Maximum Uni Requirement Device Requirement Device t tr TWCK and TWD rise time Standard( 1) - 1000 ns Fast(1) 20 + 0.1Cb 300 tf TWCK and TWD fall time Standard - 300 ns Fast 20 + 0.1Cb 300 tHD-STA (Repeated) START hold time Standard 4 tclkpb - s Fast 0.6 tSU-STA (Repeated) START set-up time Standard 4.7 tclkpb - s Fast 0.6 tSU-STO STOP set-up time Standard 4.0 4tclkpb - s Fast 0.6 tHD-DAT Data hold time Standard 0.3(2) 2tclkpb 3.45() 15tprescaled + tclkpb s Fast 0.9() tSU-DATTWI Data set-up time Standard 250 2tclkpb - ns Fast 100 tSU-DAT - -tclkpb - - tLOW-TWI TWCK LOW period Standard 4.7 4tclkpb - s Fast 1.3 tLOW - -tclkpb - - tHIGH TWCK HIGH period Standard 4.0 8tclkpb - s Fast 0.6 fTWCK TWCK frequency Standard - 100 kHz Fast 400 1 12tclkpb ----------------------- fTWCK  100 kHz f TWCK  100 kHz 930 32142D–06/2013 ATUC64/128/256L3/4U 35.10.6 JTAG Timing Figure 35-19. JTAG Interface Signals Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. JTAG2 JTAG3 JTAG1 JTAG4 JTAG0 TMS/TDI TCK TDO JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Boundary Scan Inputs Boundary Scan Outputs Table 35-46. JTAG Timings(1) Symbol Parameter Conditions Min Max Units JTAG0 TCK Low Half-period VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 21.8 ns JTAG1 TCK High Half-period 8.6 JTAG2 TCK Period 30.3 JTAG3 TDI, TMS Setup before TCK High 2.0 JTAG4 TDI, TMS Hold after TCK High 2.3 JTAG5 TDO Hold Time 9.5 JTAG6 TCK Low to TDO Valid 21.8 JTAG7 Boundary Scan Inputs Setup Time 0.6 JTAG8 Boundary Scan Inputs Hold Time 6.9 JTAG9 Boundary Scan Outputs Hold Time 9.3 JTAG10 TCK to Boundary Scan Outputs Valid 32.2 931 32142D–06/2013 ATUC64/128/256L3/4U 36. Mechanical Characteristics 36.1 Thermal Considerations 36.1.1 Thermal Data Table 36-1 summarizes the thermal resistance data depending on the package. 36.1.2 Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. 2. where: • JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 36-1. • JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 36-1. • HEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in Section 35.4 on page 898. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. Table 36-1. Thermal Resistance Data Symbol Parameter Condition Package Typ Unit JA Junction-to-ambient thermal resistance Still Air TQFP48 54.4 C/W JC Junction-to-case thermal resistance TQFP48 15.7 JA Junction-to-ambient thermal resistance Still Air QFN48 26.0 C/W JC Junction-to-case thermal resistance QFN48 1.6 JA Junction-to-ambient thermal resistance Still Air TLLGA48 25.4 C/W JC Junction-to-case thermal resistance TLLGA48 12.7 JA Junction-to-ambient thermal resistance Still Air TQFP64 52.9 C/W JC Junction-to-case thermal resistance TQFP64 15.5 JA Junction-to-ambient thermal resistance Still Air QFN64 22.9 C/W JC Junction-to-case thermal resistance QFN64 1.6 TJ TA PD JA = +    TJ TA PD  HEATSINK  JC = + +   932 32142D–06/2013 ATUC64/128/256L3/4U 36.2 Package Drawings Figure 36-1. TQFP-48 Package Drawing Table 36-2. Device and Package Maximum Weight 140 mg Table 36-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-4. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 933 32142D–06/2013 ATUC64/128/256L3/4U Figure 36-2. QFN-48 Package Drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 36-5. Device and Package Maximum Weight 140 mg Table 36-6. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-7. Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification E3 934 32142D–06/2013 ATUC64/128/256L3/4U Figure 36-3. TLLGA-48 Package Drawing Table 36-8. Device and Package Maximum Weight 39.3 mg Table 36-9. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-10. Package Reference JEDEC Drawing Reference N/A JESD97 Classification E4 935 32142D–06/2013 ATUC64/128/256L3/4U Figure 36-4. TQFP-64 Package Drawing Table 36-11. Device and Package Maximum Weight 300 mg Table 36-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-13. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 936 32142D–06/2013 ATUC64/128/256L3/4U Figure 36-5. QFN-64 Package Drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 36-14. Device and Package Maximum Weight 200 mg Table 36-15. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-16. Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification E3 937 32142D–06/2013 ATUC64/128/256L3/4U 36.3 Soldering Profile Table 36-17 gives the recommended soldering profile from J-STD-20. A maximum of three reflow passes is allowed per component. Table 36-17. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/s max Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C 60-150 s Time within 5C of Actual Peak Temperature 30 s Peak Temperature Range 260°C Ramp-down Rate 6°C/s max Time 25C to Peak Temperature 8 minutes max 938 32142D–06/2013 ATUC64/128/256L3/4U 37. Ordering Information Table 37-1. Ordering Information Device Ordering Code Carrier Type Package Package Type Temperature Operating Range ATUC256L3U ATUC256L3U-AUTES ES TQFP 64 JESD97 Classification E3 N/A ATUC256L3U-AUT Tray Industrial (-40C to 85C) ATUC256L3U-AUR Tape & Reel ATUC256L3U-Z3UTES ES QFN 64 N/A ATUC256L3U-Z3UT Tray Industrial (-40C to 85C) ATUC256L3U-Z3UR Tape & Reel ATUC128L3U ATUC128L3U-AUT Tray TQFP 64 JESD97 Classification E3 Industrial (-40C to 85C) ATUC128L3U-AUR Tape & Reel ATUC128L3U-Z3UT Tray QFN 64 ATUC128L3U-Z3UR Tape & Reel ATUC64L3U ATUC64L3U-AUT Tray TQFP 64 JESD97 Classification E3 Industrial (-40C to 85C) ATUC64L3U-AUR Tape & Reel ATUC64L3U-Z3UT Tray QFN 64 ATUC64L3U-Z3UR Tape & Reel 939 32142D–06/2013 ATUC64/128/256L3/4U ATUC256L4U ATUC256L4U-AUTES ES TQFP 48 JESD97 Classification E3 N/A ATUC256L4U-AUT Tray Industrial (-40C to 85C) ATUC256L4U-AUR Tape & Reel ATUC256L4U-ZAUTES ES QFN 48 N/A ATUC256L4U-ZAUT Tray Industrial (-40C to 85C) ATUC256L4U-ZAUR Tape & Reel ATUC256L4U-D3HES ES TLLGA 48 JESD97 Classification E4 N/A ATUC256L4U-D3HT Tray Industrial (-40C to 85C) ATUC256L4U-D3HR Tape & Reel ATUC128L4U ATUC128L4U-AUT Tray TQFP 48 JESD97 Classification E3 ATUC128L4U-AUR Tape & Reel ATUC128L4U-ZAUT Tray QFN 48 ATUC128L4U-ZAUR Tape & Reel ATUC128L4U-D3HT Tray TLLGA 48 JESD97 Classification E4 ATUC128L4U-D3HR Tape & Reel ATUC64L4U ATUC64L4U-AUT Tray TQFP 48 JESD97 Classification E3 ATUC64L4U-AUR Tape & Reel ATUC64L4U-ZAUT Tray QFN 48 ATUC64L4U-ZAUR Tape & Reel ATUC64L4U-D3HT Tray TLLGA 48 JESD97 Classification E4 ATUC64L4U-D3HR Tape & Reel Table 37-1. Ordering Information Device Ordering Code Carrier Type Package Package Type Temperature Operating Range 940 32142D–06/2013 ATUC64/128/256L3/4U 38. Errata 38.1 Rev. C 38.1.1 SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any location in the SCIF memory range. Fix/Workaround None. 38.1.2 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 941 32142D–06/2013 ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 38.1.3 TWI 1. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. 2. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 38.1.4 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 38.1.5 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph- 942 32142D–06/2013 ATUC64/128/256L3/4U eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2. Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST source clock is larger than one CAT acquisition. One AST clock period after the AST trigger, the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely, ruining the result. Fix/Workaround Always ensure that the ATCFG1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the AST source clock. 38.1.6 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 38.2 Flash 1. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xFFFF_FFFF content at any address in the page. 38.3 Rev. B 38.3.1 SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one f sab 7f aw CV – 3 = ---------------- 943 32142D–06/2013 ATUC64/128/256L3/4U - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any location in the SCIF memory range. Fix/Workaround None. 38.3.2 WDT 1. WDT Control Register does not have synchronization feedback When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN), Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchronizer is started to propagate the values to the WDT clcok domain. This synchronization takes a finite amount of time, but only the status of the synchronization of the EN bit is reflected back to the user. Writing to the synchronized fields during synchronization can lead to undefined behavior. Fix/Workaround -When writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the WDT peripheral bus clock and the selected WDT clock source. -When doing writes that changes the EN bit, the EN bit can be read back until it reflects the written value. 38.3.3 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 944 32142D–06/2013 ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 38.3.4 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus events. 2. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. 3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 38.3.5 PWMA 1. The SR.READY bit cannot be cleared by writing to SCR.READY The Ready bit in the Status Register will not be cleared when writing a one to the corresponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is set. Fix/Workaround 945 32142D–06/2013 ATUC64/128/256L3/4U Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 38.3.6 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 38.3.7 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the peripheral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2. Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST source clock is larger than one CAT acquisition. One AST clock period after the AST trigger, the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely, ruining the result. Fix/Workaround Always ensure that the ATCFG1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the AST source clock. 3. CAT consumes unnecessary power when disabled or when autonomous touch not used A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT module is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. Fix/Workaround If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT module is used but the autonomous touch feature is not used, the power consumption of the CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field. 38.3.8 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround 946 32142D–06/2013 ATUC64/128/256L3/4U Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 38.4 Flash 2. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xFFFF_FFFF content at any address in the page. 38.5 Rev. A 38.5.1 Device 3. JTAGID is wrong The JTAGID reads 0x021DF03F for all devices. Fix/Workaround None. 38.5.2 FLASHCDW 1. General-purpose fuse programming does not work The general-purpose fuses cannot be programmed and are stuck at 1. Please refer to the Fuse Settings chapter in the FLASHCDW for more information about what functions are affected. Fix/Workaround None. 2. Set Security Bit command does not work The Set Security Bit (SSB) command of the FLASHCDW does not work. The device cannot be locked from external JTAG, aWire, or other debug accesses. Fix/Workaround None. 3. Flash programming time is longer than specified f sab 7f aw CV – 3 = ---------------- 947 32142D–06/2013 ATUC64/128/256L3/4U The flash programming time is now: Fix/Workaround None. 4. Power Manager 5. Clock Failure Detector (CFD) can be issued while turning off the CFD While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will change the main clock source to RCSYS. Fix/Workaround Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch back to original main clock source. Solution 2: Only turn off the CFD while running the main clock on RCSYS. 6. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walking, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock requests in the PM.PPCR register before going into idle or frozen mode. 4. Unused PB clocks are running Three unused PBA clocks are enabled by default and will cause increased active power consumption. Fix/Workaround Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register. 38.5.3 SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLL lock might not clear after disable Table 38-1. Flash Characteristics Symbol Parameter Conditions Min Typ Max Unit TFPP Page programming time fCLK_HSB= 50MHz 7.5 ms TFPE Page erase time 7.5 TFFP Fuse programming time 1 TFEA Full chip erase time (EA) 9 TFCE JTAG chip erase time (CHIP_ERASE) fCLK_HSB= 115kHz 250 948 32142D–06/2013 ATUC64/128/256L3/4U Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator may not go back to zero after the PLL oscillator has been disabled. This can cause the propagation of clock signals with the wrong frequency to parts of the system that use the PLL clock. Fix/Workaround PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL has been turned off, a delay of 30us must be observed after the PLL has been enabled again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is locked. 3. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 4. RCSYS is not calibrated The RCSYS is not calibrated and will run faster than 115.2kHz. Frequencies around 150kHz can be expected. Fix/Workaround If a known clock source is available the RCSYS can be runtime calibrated by using the frequency meter (FREQM) and tuning the RCSYS by writing to the RCCR register in SCIF. 5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any location in the SCIF memory range. Fix/Workaround None. 38.5.4 WDT 1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immediately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time before the reset will be twice as long as needed. 2. WDT Control Register does not have synchronization feedback When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN), Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchronizer is started to propagate the values to the WDT clcok domain. This synchronization takes a finite amount of time, but only the status of the synchronization of the EN bit is reflected back to the user. Writing to the synchronized fields during synchronization can lead to undefined behavior. Fix/Workaround -When writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the WDT peripheral bus clock and the selected WDT clock source. -When doing writes that changes the EN bit, the EN bit can be read back until it reflects the written value. 949 32142D–06/2013 ATUC64/128/256L3/4U 38.5.5 GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 38.5.6 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 950 32142D–06/2013 ATUC64/128/256L3/4U 38.5.7 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus events. 2. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. 3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 4. TWIS stretch on Address match error When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD at the same time. This can cause a TWI timing violation. Fix/Workaround None. 5. TWIM TWALM polarity is wrong The TWALM signal in the TWIM is active high instead of active low. Fix/Workaround Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the TWALM cannot be used. 38.5.8 PWMA 1. The SR.READY bit cannot be cleared by writing to SCR.READY The Ready bit in the Status Register will not be cleared when writing a one to the corresponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is set. Fix/Workaround Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 38.5.9 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. 951 32142D–06/2013 ATUC64/128/256L3/4U Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 38.5.10 ADCIFB 1. ADCIFB DMA transfer does not work with divided PBA clock DMA requests from the ADCIFB will not be performed when the PBA clock is slower than the HSB clock. Fix/Workaround Do not use divided PBA clock when the PDCA transfers from the ADCIFB. 38.5.11 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the peripheral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2. Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST source clock is larger than one CAT acquisition. One AST clock period after the AST trigger, the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely, ruining the result. Fix/Workaround Always ensure that the ATCFG1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the AST source clock. 3. CAT consumes unnecessary power when disabled or when autonomous touch not used A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT module is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. Fix/Workaround If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT module is used but the autonomous touch feature is not used, the power consumption of the CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field. 4. CAT module does not terminate QTouch burst on detect The CAT module does not terminate a QTouch burst when the detection voltage is reached on the sense capacitor. This can cause the sense capacitor to be charged more than necessary. Depending on the dielectric absorption characteristics of the capacitor, this can lead to unstable measurements. Fix/Workaround Use the minimum possible value for the MAX field in the ATCFG1, TG0CFG1, and TG1CFG1 registers. 952 32142D–06/2013 ATUC64/128/256L3/4U 38.5.12 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 38.5.13 Flash 5. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xFFFF_FFFF content at any address in the page. 38.5.14 I/O Pins 1. PA05 is not 3.3V tolerant. PA05 should be grounded on the PCB and left unused if VDDIO is above 1.8V. Fix/Workaround None. 2. No pull-up on pins that are not bonded PB13 to PB27 are not bonded on UC3L0256/128, but has no pull-up and can cause current consumption on VDDIO/VDDIN if left undriven. Fix/Workaround Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the GPIO. 3. PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB design. f sab 7f aw CV – 3 = ---------------- 953 32142D–06/2013 ATUC64/128/256L3/4U 39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 Rev. D – 06/2013 39.2 Rev. C – 01/2012 39.3 Rev. B – 12/2011 39.4 Rev. A – 12/2011 1. Updated the datasheet with a new ATmel blue logo and the last page. 2. Added Flash errata. 1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz. 2. Block Diagram: GCLK_IN is input, not output. CAT SMP corrected from I/O to output. SPI NPCS corrected from output to I/O. 3, Package and Pinout: EXTINT0 in Signal Descriptions table is NMI. 4, Supply and Startup Considerations: In 1.8V single supply mode figure, the input voltage is 1.62-1.98V, not 1.98-3.6V. “On system start-up, the DFLL is disabled” is replaced by “On system start-up, all high-speed clocks are disabled”. 5, ADCIFB: PRND signal removed from block diagram. 6, Electrical Charateristics: Added 64-pin package information to I/O Pin Characteristics tables and Digital Clock Characteristics table. 7, Mechanical Characteristics: QFN48 Package Drawing updated. Note that the package drawing for QFN48 is correct in datasheet rev A, but wrong in rev B. Added notes to package drawings. 8. Summary: Removed Programming and Debugging chapter, added Processor and Architecture chapter. 1. JTAG Data Registers subchapter added in the Programming and Debugging chapter, containing JTAG IDs. 1. Initial revision. i 32142D–06/2013 ATUC64/128/256L3/4U Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 2.1 Block Diagram ...................................................................................................5 2.2 Configuration Summary .....................................................................................6 3 Package and Pinout ................................................................................. 7 3.1 Package .............................................................................................................7 3.2 See Section 3.3 for a description of the various peripheral signals. ................12 3.3 Signal Descriptions ..........................................................................................15 3.4 I/O Line Considerations ...................................................................................18 4 Processor and Architecture .................................................................. 21 4.1 Features ..........................................................................................................21 4.2 AVR32 Architecture .........................................................................................21 4.3 The AVR32UC CPU ........................................................................................22 4.4 Programming Model ........................................................................................26 4.5 Exceptions and Interrupts ................................................................................30 5 Memories ................................................................................................ 35 5.1 Embedded Memories ......................................................................................35 5.2 Physical Memory Map .....................................................................................35 5.3 Peripheral Address Map ..................................................................................36 5.4 CPU Local Bus Mapping .................................................................................37 6 Supply and Startup Considerations ..................................................... 39 6.1 Supply Considerations .....................................................................................39 6.2 Startup Considerations ....................................................................................44 7 Peripheral DMA Controller (PDCA) ...................................................... 45 7.1 Features ..........................................................................................................45 7.2 Overview ..........................................................................................................45 7.3 Block Diagram .................................................................................................46 7.4 Product Dependencies ....................................................................................46 7.5 Functional Description .....................................................................................47 7.6 Performance Monitors .....................................................................................49 7.7 User Interface ..................................................................................................51 ii 32142D–06/2013 ATUC64/128/256L3/4U 7.8 Module Configuration ......................................................................................79 8 USB Interface (USBC) ............................................................................ 81 8.1 Features ..........................................................................................................81 8.2 Overview ..........................................................................................................81 8.3 Block Diagram .................................................................................................81 8.4 I/O Lines Description .......................................................................................83 8.5 Product Dependencies ....................................................................................84 8.6 Functional Description .....................................................................................85 8.7 User Interface ...............................................................................................101 8.8 Module Configuration ....................................................................................134 9 Flash Controller (FLASHCDW) ........................................................... 135 9.1 Features ........................................................................................................135 9.2 Overview ........................................................................................................135 9.3 Product Dependencies ..................................................................................135 9.4 Functional Description ...................................................................................136 9.5 Flash Commands ..........................................................................................141 9.6 General-purpose Fuse Bits ............................................................................143 9.7 Security Bit ....................................................................................................146 9.8 User Interface ................................................................................................147 9.9 Fuse Settings .................................................................................................157 9.10 Serial Number ................................................................................................160 9.11 Module Configuration ....................................................................................160 10 Secure Access Unit (SAU) .................................................................. 162 10.1 Features ........................................................................................................162 10.2 Overview ........................................................................................................162 10.3 Block Diagram ...............................................................................................163 10.4 Product Dependencies ..................................................................................164 10.5 Functional Description ...................................................................................164 10.6 User Interface ................................................................................................168 10.7 Module Configuration ....................................................................................183 11 HSB Bus Matrix (HMATRIXB) .............................................................. 184 11.1 Features ........................................................................................................184 11.2 Overview ........................................................................................................184 11.3 Product Dependencies ..................................................................................184 11.4 Functional Description ...................................................................................184 iii 32142D–06/2013 ATUC64/128/256L3/4U 11.5 User Interface ................................................................................................188 11.6 Module Configuration ....................................................................................196 12 Interrupt Controller (INTC) .................................................................. 198 12.1 Features ........................................................................................................198 12.2 Overview ........................................................................................................198 12.3 Block Diagram ...............................................................................................198 12.4 Product Dependencies ..................................................................................199 12.5 Functional Description ...................................................................................199 12.6 User Interface ................................................................................................202 12.7 Module Configuration ....................................................................................206 12.8 Interrupt Request Signal Map ........................................................................206 13 Power Manager (PM) ............................................................................ 209 13.1 Features ........................................................................................................209 13.2 Overview ........................................................................................................209 13.3 Block Diagram ...............................................................................................210 13.4 I/O Lines Description .....................................................................................210 13.5 Product Dependencies ..................................................................................210 13.6 Functional Description ...................................................................................211 13.7 User Interface ................................................................................................220 13.8 Module Configuration ....................................................................................243 14 System Control Interface (SCIF) ......................................................... 244 14.1 Features ........................................................................................................244 14.2 Overview ........................................................................................................244 14.3 I/O Lines Description .....................................................................................244 14.4 Product Dependencies ..................................................................................244 14.5 Functional Description ...................................................................................245 14.6 User Interface ................................................................................................265 14.7 Module Configuration ....................................................................................318 15 Asynchronous Timer (AST) ................................................................ 322 15.1 Features ........................................................................................................322 15.2 Overview ........................................................................................................322 15.3 Block Diagram ...............................................................................................323 15.4 Product Dependencies ..................................................................................323 15.5 Functional Description ...................................................................................324 15.6 User Interface ................................................................................................330 iv 32142D–06/2013 ATUC64/128/256L3/4U 15.7 Module Configuration ....................................................................................351 16 Watchdog Timer (WDT) ....................................................................... 352 16.1 Features ........................................................................................................352 16.2 Overview ........................................................................................................352 16.3 Block Diagram ...............................................................................................352 16.4 Product Dependencies ..................................................................................352 16.5 Functional Description ...................................................................................353 16.6 User Interface ................................................................................................358 16.7 Module Configuration ....................................................................................364 17 External Interrupt Controller (EIC) ..................................................... 365 17.1 Features ........................................................................................................365 17.2 Overview ........................................................................................................365 17.3 Block Diagram ...............................................................................................365 17.4 I/O Lines Description .....................................................................................366 17.5 Product Dependencies ..................................................................................366 17.6 Functional Description ...................................................................................366 17.7 User Interface ................................................................................................370 17.8 Module Configuration ....................................................................................386 18 Frequency Meter (FREQM) .................................................................. 387 18.1 Features ........................................................................................................387 18.2 Overview ........................................................................................................387 18.3 Block Diagram ...............................................................................................387 18.4 Product Dependencies ..................................................................................387 18.5 Functional Description ...................................................................................388 18.6 User Interface ................................................................................................390 18.7 Module Configuration ....................................................................................401 19 General-Purpose Input/Output Controller (GPIO) ............................. 403 19.1 Features ........................................................................................................403 19.2 Overview ........................................................................................................403 19.3 Block Diagram ...............................................................................................403 19.4 I/O Lines Description .....................................................................................404 19.5 Product Dependencies ..................................................................................404 19.6 Functional Description ...................................................................................405 19.7 User Interface ................................................................................................410 19.8 Module Configuration ....................................................................................433 v 32142D–06/2013 ATUC64/128/256L3/4U 20 Universal Synchronous Asynchronous Receiver Transmitter (USART) 434 20.1 Features ........................................................................................................434 20.2 Overview ........................................................................................................434 20.3 Block Diagram ...............................................................................................435 20.4 I/O Lines Description ....................................................................................436 20.5 Product Dependencies ..................................................................................436 20.6 Functional Description ...................................................................................437 20.7 User Interface ................................................................................................463 20.8 Module Configuration ....................................................................................485 21 Serial Peripheral Interface (SPI) ......................................................... 486 21.1 Features ........................................................................................................486 21.2 Overview ........................................................................................................486 21.3 Block Diagram ...............................................................................................487 21.4 Application Block Diagram .............................................................................487 21.5 I/O Lines Description .....................................................................................488 21.6 Product Dependencies ..................................................................................488 21.7 Functional Description ...................................................................................488 21.8 User Interface ................................................................................................499 21.9 Module Configuration ....................................................................................526 22 Two-wire Master Interface (TWIM) ...................................................... 527 22.1 Features ........................................................................................................527 22.2 Overview ........................................................................................................527 22.3 List of Abbreviations ......................................................................................528 22.4 Block Diagram ...............................................................................................528 22.5 Application Block Diagram .............................................................................529 22.6 I/O Lines Description .....................................................................................529 22.7 Product Dependencies ..................................................................................529 22.8 Functional Description ...................................................................................531 22.9 User Interface ................................................................................................543 22.10 Module Configuration ....................................................................................560 23 Two-wire Slave Interface (TWIS) ......................................................... 561 23.1 Features ........................................................................................................561 23.2 Overview ........................................................................................................561 23.3 List of Abbreviations ......................................................................................562 vi 32142D–06/2013 ATUC64/128/256L3/4U 23.4 Block Diagram ...............................................................................................562 23.5 Application Block Diagram .............................................................................563 23.6 I/O Lines Description .....................................................................................563 23.7 Product Dependencies ..................................................................................563 23.8 Functional Description ...................................................................................564 23.9 User Interface ................................................................................................574 23.10 Module Configuration ....................................................................................590 24 Inter-IC Sound Controller (IISC) .......................................................... 591 24.1 Features ........................................................................................................591 24.2 Overview ........................................................................................................591 24.3 Block Diagram ...............................................................................................592 24.4 I/O Lines Description .....................................................................................592 24.5 Product Dependencies ..................................................................................592 24.6 Functional Description ...................................................................................593 24.7 IISC Application Examples ............................................................................598 24.8 User Interface ................................................................................................600 24.9 Module configuration .....................................................................................614 25 Pulse Width Modulation Controller (PWMA) ..................................... 615 25.1 Features ........................................................................................................615 25.2 Overview ........................................................................................................615 25.3 Block Diagram ...............................................................................................616 25.4 I/O Lines Description .....................................................................................616 25.5 Product Dependencies ..................................................................................616 25.6 Functional Description ...................................................................................617 25.7 User Interface ................................................................................................623 25.8 Module Configuration ....................................................................................641 26 Timer/Counter (TC) .............................................................................. 642 26.1 Features ........................................................................................................642 26.2 Overview ........................................................................................................642 26.3 Block Diagram ...............................................................................................643 26.4 I/O Lines Description .....................................................................................643 26.5 Product Dependencies ..................................................................................643 26.6 Functional Description ...................................................................................644 26.7 User Interface ................................................................................................659 26.8 Module Configuration ....................................................................................682 vii 32142D–06/2013 ATUC64/128/256L3/4U 27 Peripheral Event System ..................................................................... 683 27.1 Features ........................................................................................................683 27.2 Overview ........................................................................................................683 27.3 Peripheral Event System Block Diagram .......................................................683 27.4 Functional Description ...................................................................................683 27.5 Application Example ......................................................................................686 28 Audio Bit Stream DAC (ABDACB) ...................................................... 687 28.1 Features ........................................................................................................687 28.2 Overview ........................................................................................................687 28.3 Block Diagram ...............................................................................................687 28.4 I/O Lines Description .....................................................................................688 28.5 Product Dependencies ..................................................................................688 28.6 Functional Description ...................................................................................689 28.7 User Interface ................................................................................................696 28.8 Module Configuration ....................................................................................710 29 ADC Interface (ADCIFB) ...................................................................... 711 29.1 Features ........................................................................................................711 29.2 Overview ........................................................................................................711 29.3 Block Diagram ...............................................................................................712 29.4 I/O Lines Description .....................................................................................713 29.5 Product Dependencies ..................................................................................713 29.6 Functional Description ...................................................................................714 29.7 Resistive Touch Screen .................................................................................718 29.8 Operating Modes ...........................................................................................724 29.9 User Interface ................................................................................................726 29.10 Module Configuration ....................................................................................745 30 Analog Comparator Interface (ACIFB) ............................................... 746 30.1 Features ........................................................................................................746 30.2 Overview ........................................................................................................746 30.3 Block Diagram ...............................................................................................747 30.4 I/O Lines Description .....................................................................................747 30.5 Product Dependencies ..................................................................................748 30.6 Functional Description ...................................................................................749 30.7 Peripheral Event Triggers ..............................................................................754 30.8 AC Test mode ................................................................................................754 viii 32142D–06/2013 ATUC64/128/256L3/4U 30.9 User Interface ................................................................................................755 30.10 Module Configuration ....................................................................................769 31 Capacitive Touch Module (CAT) ......................................................... 770 31.1 Features ........................................................................................................770 31.2 Overview ........................................................................................................770 31.3 Block Diagram ...............................................................................................771 31.4 I/O Lines Description .....................................................................................771 31.5 Product Dependencies ..................................................................................772 31.6 Functional Description ...................................................................................774 31.7 User Interface ................................................................................................781 31.8 Module Configuration ....................................................................................816 32 Glue Logic Controller (GLOC) ............................................................ 817 32.1 Features ........................................................................................................817 32.2 Overview ........................................................................................................817 32.3 Block Diagram ...............................................................................................817 32.4 I/O Lines Description .....................................................................................818 32.5 Product Dependencies ..................................................................................818 32.6 Functional Description ...................................................................................818 32.7 User Interface ................................................................................................820 32.8 Module Configuration ....................................................................................825 33 aWire UART (AW) ................................................................................. 826 33.1 Features ........................................................................................................826 33.2 Overview ........................................................................................................826 33.3 Block Diagram ...............................................................................................826 33.4 I/O Lines Description .....................................................................................827 33.5 Product Dependencies ..................................................................................827 33.6 Functional Description ...................................................................................827 33.7 User Interface ................................................................................................830 33.8 Module Configuration ....................................................................................843 34 Programming and Debugging ............................................................ 844 34.1 Overview ........................................................................................................844 34.2 Service Access Bus .......................................................................................844 34.3 On-Chip Debug ..............................................................................................847 34.4 JTAG and Boundary-scan (JTAG) .................................................................855 34.5 JTAG Instruction Summary ...........................................................................863 ix 32142D–06/2013 ATUC64/128/256L3/4U 34.6 aWire Debug Interface (AW) .........................................................................880 35 Electrical Characteristics .................................................................... 897 35.1 Absolute Maximum Ratings* .........................................................................897 35.2 Supply Characteristics ...................................................................................897 35.3 Maximum Clock Frequencies ........................................................................898 35.4 Power Consumption ......................................................................................898 35.5 I/O Pin Characteristics ...................................................................................902 35.6 Oscillator Characteristics ...............................................................................905 35.7 Flash Characteristics .....................................................................................910 35.8 ABDACB Electrical Characteristics. .............................................................911 35.9 Analog Characteristics ...................................................................................912 35.10 Timing Characteristics ...................................................................................921 36 Mechanical Characteristics ................................................................. 931 36.1 Thermal Considerations ................................................................................931 36.2 Package Drawings .........................................................................................932 36.3 Soldering Profile ............................................................................................937 37 Ordering Information ........................................................................... 938 38 Errata ..................................................................................................... 940 38.1 Rev. C ............................................................................................................940 38.2 Flash ..............................................................................................................942 38.3 Rev. B ............................................................................................................942 38.4 Flash .............................................................................................................946 38.5 Rev. A ............................................................................................................946 39 Datasheet Revision History ................................................................ 953 39.1 Rev. D – 06/2013 ...........................................................................................953 39.2 Rev. C – 01/2012 ...........................................................................................953 39.3 Rev. B – 12/2011 ...........................................................................................953 39.4 Rev. A – 12/2011 ...........................................................................................953 Table of Contents....................................................................................... i Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81) (3) 6417-0300 Fax: (+81) (3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 32142D–AVR32–06/2013 Atmel®, logo and combinations thereof, AVR®, picoPower®, QTouch®, AKS® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.  2015 Microchip Technology Inc. DS00001625B-page 1 General Description The CAP1133, which incorporates RightTouch® technology, is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains three (3) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1133 also contains three (3) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. The CAP1133 includes Multiple Pattern Touch recognition that allows the user to select a specific set of buttons to be touched simultaneously. If this pattern is detected, then a status bit is set and an interrupt generated. Additionally, the CAP1133 includes circuitry and support for enhanced sensor proximity detection. The CAP1133 offers multiple power states operating at low quiescent currents. In the Standby state of operation, one or more capacitive touch sensor inputs are active and all LEDs may be used. Deep Sleep is the lowest power state available, drawing 5uA (typical) of current. In this state, no sensor inputs are active. Communications will wake the device. Applications • Desktop and Notebook PCs • LCD Monitors • Consumer Electronics • Appliances Features • Three (3) Capacitive Touch Sensor Inputs - Programmable sensitivity - Automatic recalibration - Individual thresholds for each button • Proximity Detection • Multiple Button Pattern Detection • Calibrates for Parasitic Capacitance • Analog Filtering for System Noise Sources • Press and Hold feature for Volume-like Applications • SMBus / I2C Compliant Communication Interface • Low Power Operation - 5uA quiescent current in Deep Sleep - 50uA quiescent current in Standby (1 sensor input monitored) - Samples one or more channels in Standby • Three (3) LED Driver Outputs - Open Drain or Push-Pull - Programmable blink, breathe, and dimness controls - Can be linked to Capacitive Touch Sensor inputs • Available in 10-pin 3mm x 3mm RoHS compliant DFN package CAP1133 3 Channel Capacitive Touch Sensor with 3 LED Drivers CAP1133 DS00001625B-page 2  2015 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2015 Microchip Technology Inc. DS00001625B-page 3 CAP1133 Table of Contents 1.0 Block Diagram ................................................................................................................................................................................. 4 2.0 Pin Description ................................................................................................................................................................................ 5 3.0 Electrical Specifications .................................................................................................................................................................. 9 4.0 Communications ........................................................................................................................................................................... 12 5.0 General Description ...................................................................................................................................................................... 23 6.0 Register Description ...................................................................................................................................................................... 29 7.0 Package Information ..................................................................................................................................................................... 67 Appendix A: Device Delta ................................................................................................................................................................... 72 Appendix B: Data Sheet Revision History ........................................................................................................................................... 74 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77 CAP1133 DS00001625B-page 4  2015 Microchip Technology Inc. 1.0 BLOCK DIAGRAM SMBus Slave Protocol SMCLK SMDATA VDD GND ALERT# Capacitive Touch Sensing Algorithm CS1 CS2 CS3 LED1 LED Driver, Breathe, and Dimness control LED2 LED3  2015 Microchip Technology Inc. DS00001625B-page 5 CAP1133 2.0 PIN DESCRIPTION FIGURE 2-1: CAP1133 Pin Diagram (10-Pin DFN) TABLE 2-1: PIN DESCRIPTION FOR CAP1133 Pin Number Pin Name Pin Function Pin Type Unused Connection 1 ALERT# Active low alert / interrupt output usable for SMBus alert OD (5V) Connect to Ground Active high alert / interrupt output usable for SMBus alert DO leave open 2 SMDATA Bi-directional, open-drain SMBus data - requires pull-up DIOD (5V) n/a 3 SMCLK SMBus clock input - requires pull-up resistor DI (5V) 4 VDD Positive Power supply Power n/a 5 LED1 Open drain LED 1 driver (default) OD (5V) Connect to Ground Push-pull LED 1 driver DO leave open or connect to Ground 6 LED2 Open drain LED 2 driver (default) OD (5V) Connect to Ground Push-pull LED 2 driver DO leave open or connect to Ground 7 LED3 Open drain LED 3 driver (default) OD (5V) Connect to Ground Push-pull LED 3 driver DO leave open or connect to Ground GND CS2 1 CS1 2 3 4 5 CS3 LED1 ALERT# SMDATA VDD SMCLK LED3 LED2 CAP1133 3mm x 3mm DFN 10 9 8 7 6 CAP1133 DS00001625B-page 6  2015 Microchip Technology Inc. APPLICATION NOTE: When the ALERT# pinis configured as an active low output, it will be open drain. When it is configured as an active high output, it will be push-pull. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the CAP1133 is unpowered. The pin types are described in Table 2-2. All pins labeled with (5V) are 5V tolerant. 8 CS3 Capacitive Touch Sensor Input 3 AIO Connect to Ground 9 CS2 Capacitive Touch Sensor Input 2 AIO Connect to Ground 10 CS1 Capacitive Touch Sensor Input 1 AIO Connect to Ground Bottom Pad GND Ground Power n/a TABLE 2-2: PIN TYPES Pin Type Description Power This pin is used to supply power or ground to the device. DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant. AIO Analog Input / Output -This pin is used as an I/O for analog signals. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. DO Push-pull Digital Output - This pin is used as a digital output and can sink and source current. DIO Push-pull Digital Input / Output - This pin is used as an I/O for digital signals. TABLE 2-1: PIN DESCRIPTION FOR CAP1133 (CONTINUED) Pin Number Pin Name Pin Function Pin Type Unused Connection  2015 Microchip Technology Inc. DS00001625B-page 7 CAP1133 3.0 ELECTRICAL SPECIFICATIONS Note 3-1 Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3-2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V5VT_PIN and VDD must never exceed 3.6V. Note 3-3 The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 2x2 matrix of 0.3mm (12mil) vias at 1.0mm pitch connected to the ground plane with a 1.6 x 2.3mm thermal landing. TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Voltage on 5V tolerant pins (V5VT_PIN) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_PIN - VDD|) Note 3-2 0 to 3.6 V Voltage on VDD pin -0.3 to 4 V Voltage on any other pin to GND -0.3 to VDD + 0.3 V Package Power Dissipation up to TA = 85°C for 10 pin DFN (see Note 3-3) 0.7 W Junction to Ambient (θJA) 77.7 °C/W Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 8000 V CAP1133 DS00001625B-page 8  2015 Microchip Technology Inc. TABLE 3-2: ELECTRICAL SPECIFICATIONS VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions DC Power Supply Voltage VDD 3.0 3.3 3.6 V Supply Current ISTBY 120 170 uA Standby state active 1 sensor input monitored No LEDs active Default conditions (8 avg, 70ms cycle time) ISTBY 50 uA Standby state active 1 sensor input monitored No LEDs active 1 avg, 140ms cycle time, IDSLEEP 5 15 uA Deep Sleep state active LEDs at 100% or 0% Duty Cycle No communications TA < 40°C 3.135 < VDD < 3.465V IDD 500 600 uA Capacitive Sensing Active No LEDs active Capacitive Touch Sensor Inputs Maximum Base Capacitance CBASE 50 pF Pad untouched Minimum Detectable Capacitive Shift ΔCTOUCH 20 fF Pad touched - default conditions (1 avg, 35ms cycle time, 1x sensitivity) Recommended Cap Shift ΔCTOUCH 0.1 2 pF Pad touched - Not tested Power Supply Rejection PSR ±3 ±10 counts / V Untouched Current Counts Base Capacitance 5pF - 50pF Maximum sensitivity Negative Delta Counts disabled All other parameters default Timing Time to communications ready tCOMM_DLY 15 ms Time to first conversion ready tCONV_DLY 170 200 ms LED Drivers Duty Cycle DUTYLED 0 100 % Programmable Drive Frequency fLED 2 kHz Sinking Current ISINK 24 mA VOL = 0.4 Sourcing Current ISOURCE 24 mA VOH = VDD - 0.4 Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered I/O Pins Output Low Voltage VOL 0.4 V ISINK_IO = 8mA Output High Voltage VOH VDD - 0.4 V ISOURCE_IO = 8mA Input High Voltage VIH 2.0 V  2015 Microchip Technology Inc. DS00001625B-page 9 CAP1133 Note 3-4 The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage. Note 3-5 The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage. Input Low Voltage VIL 0.8 V Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered SMBus Timing Input Capacitance CIN 5 pF Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 us Start Setup Time tSU:STA 0.6 us Start Hold Time tHD:STA 0.6 us Stop Setup Time tSU:STO 0.6 us Data Hold Time tHD:DAT 0 us When transmitting to the master Data Hold Time tHD:DAT 0.3 us When receiving from the master Data Setup Time tSU:DAT 0.6 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line TABLE 3-2: ELECTRICAL SPECIFICATIONS (CONTINUED) VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions CAP1133 DS00001625B-page 10  2015 Microchip Technology Inc. 4.0 COMMUNICATIONS 4.1 Communications The CAP1133 communicates using the SMBus or I2C protocol. The supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block. In addition, the device supports I2C formatting for block read and block write protocols. 4.2 System Management Bus The CAP1133 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1133 will not stretch the clock signal. 4.2.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.2.2 SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the slave device. The CAP1133 responds to SMBus address 0101_000(r/w). 4.2.3 SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.2.4 SMBUS ACK AND NACK BITS The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives except the last data byte. FIGURE 4-1: SMBus Timing Diagram SMDATA SMCLK TLOW TRISE THIGH TFALL TBUF THD:STA P S S - Start Condition P - Stop Condition THD:DAT TSU:DAT TSU:STA THD:STA P TSU:STO S  2015 Microchip Technology Inc. DS00001625B-page 11 CAP1133 4.2.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1133 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. 4.2.6 SMBUS TIMEOUT The CAP1133 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the SMCLK pin is held low, the device will timeout and reset the SMBus interface. The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register (see Section 6.6, "Configuration Registers"). 4.2.7 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the CAP1133 in an I2C system, refer to AN 14.0 Dedicated Slave Devices in I2C Systems. 1. CAP1133 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2. Minimum frequency for SMBus communications is 10kHz. 3. The SMBus slave protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the CAP1133 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4. The SMBus slave protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200µs (idle condition). This function is disabled by default in the CAP1133 and can be enabled by writing to the TIMEOUT bit. I2C does not have an idle condition. 5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). 6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. The CAP1133 supports I2C formatting only. 4.3 SMBus Protocols The CAP1133 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid protocols as shown below. All of the below protocols use the convention in Table 4-1. 4.3.1 SMBUS WRITE BYTE The Write Byte is used to write one byte of data to a specific register as shown in Table 4-2. 4.3.2 SMBUS READ BYTE The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4-3. TABLE 4-1: PROTOCOL FORMAT Data Sent to Device Data Sent to the HOst Data sent Data sent TABLE 4-2: WRITE BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK Stop 1 ->0 0101_000 0 0 XXh 0 XXh 0 0 -> 1 CAP1133 DS00001625B-page 12  2015 Microchip Technology Inc. 4.3.3 SMBUS SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4-4. APPLICATION NOTE: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.3.4 SMBUS RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4-5. APPLICATION NOTE: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.4 I2C Protocols The CAP1133 supports I2C Block Write and Block Read. The protocols listed below use the convention in Table 4-1. 4.4.1 BLOCK WRITE The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 4-6. APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.4.2 BLOCK READ The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 4-7. APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. TABLE 4-3: READ BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data NACK Stop 1->0 0101_000 0 0 XXh 0 1 ->0 0101_000 1 0 XXh 1 0 -> 1 TABLE 4-4: SEND BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Stop 1 -> 0 0101_000 0 0 XXh 0 0 -> 1 TABLE 4-5: RECEIVE BYTE PROTOCOL Start Slave Address RD ACK Register Data NACK Stop 1 -> 0 0101_000 1 0 XXh 1 0 -> 1 TABLE 4-6: BLOCK WRITE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK 1 ->0 0101_000 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK . . . Register Data ACK Stop XXh 0 XXh 0 . . . XXh 0 0 -> 1  2015 Microchip Technology Inc. DS00001625B-page 13 CAP1133 TABLE 4-7: BLOCK READ PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data 1->0 0101_000 0 0 XXh 0 1 ->0 0101_000 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK . . . Register Data NACK Stop 0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1 CAP1133 DS00001625B-page 14  2015 Microchip Technology Inc. 5.0 GENERAL DESCRIPTION The CAP1133 is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains three (3) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1133 also contains three (3) low side (or push-pull) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. The CAP1133 offers multiple power states. It operates at the lowest quiescent current during its Deep Sleep state. In the low power Standby state, it can monitor one or more channels and respond to communications normally. The device communicates with a host controller using SMBus / I2C. The host controller may poll the device for updated information at any time or it may configure the device to flag an interrupt whenever a touch is detected on any sensor pad. A typical system diagram is shown in Figure 5-1. 5.1 Power States The CAP1133 has three operating states depending on the status of the STBY and DSLEEP bits. When the device transitions between power states, previously detected touches (for inactive channels) are cleared and the status bits reset. 1. Fully Active - The device is fully active. It is monitoring all active capacitive sensor inputs and driving all LED channels as defined. 2. Standby - The device is in a lower power state. It will measure a programmable number of channels using the Standby Configuration controls (see Section 6.20 through Section 6.22). Interrupts will still be generated based on the active channels. The device will still respond to communications normally and can be returned to the Fully Active state of operation by clearing the STBY bit. FIGURE 5-1: System Diagram for CAP1133 CAP1133 LED3 SMDATA SMCLK Embedded Controller VDD ALERT# LED2 LED1 CS3 CS2 CS1 Touch Button Touch Button Touch Button 3.3V – 5V  2015 Microchip Technology Inc. DS00001625B-page 15 CAP1133 3. Deep Sleep - The device is in its lowest power state. It is not monitoring any capacitive sensor inputs and not driving any LEDs. All LEDs will be driven to their programmed non-actuated state and no PWM operations will be done. While in Deep Sleep, the device can be awakened by SMBus communications targeting the device. This will not cause the DSLEEP to be cleared so the device will return to Deep Sleep once all communications have stopped. APPLICATION NOTE: In the Deep Sleep state, the LED output will be either high or low and will not be PWM’d at the min or max duty cycle. 5.2 LED Drivers The CAP1133 contains three (3) LED drivers. Each LED driver can be linked to its respective capacitive touch sensor input or it can be controlled by the host. Each LED driver can be configured to operate in one of the following modes with either push-pull or open drain drive. 1. Direct - The LED is configured to be on or off when the corresponding input stimulus is on or off (or inverted). The brightness of the LED can be programmed from full off to full on (default). Additionally, the LED contains controls to individually configure ramping on, off, and turn-off delay. 2. Pulse 1 - The LED is configured to “Pulse” (transition ON-OFF-ON) a programmable number of times with programmable rate and min / max brightness. This behavior may be actuated when a press is detected or when a release is detected. 3. Pulse 2 - The LED is configured to “Pulse” while actuated and then “Pulse” a programmable number of times with programmable rate and min / max brightness when the sensor pad is released. 4. Breathe - The LED is configured to transition continuously ON-OFF-ON (i.e. to “Breathe”) with a programmable rate and min / max brightness. When an LED is not linked to a sensor and is actuated by the host, there’s an option to assert the ALERT# pin when the initiated LED behavior has completed. 5.2.1 LINKING LEDS TO CAPACITIVE TOUCH SENSOR INPUTS All LEDs can be linked to the corresponding capacitive touch sensor input so that when the sensor input detects a touch, the corresponding LED will be actuated at one of the programmed responses. 5.3 Capacitive Touch Sensing The CAP1133 contains three (3) independent capacitive touch sensor inputs. Each sensor input has dynamic range to detect a change of capacitance due to a touch. Additionally, each sensor input can be configured to be automatically and routinely re-calibrated. 5.3.1 SENSING CYCLE Each capacitive touch sensor input has controls to be activated and included in the sensing cycle. When the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it finishes. The cycle polls through each active sensor input starting with CS1 and extending through CS3. As each capacitive touch sensor input is polled, its measurement is compared against a baseline “Not Touched” measurement. If the delta measurement is large enough, a touch is detected and an interrupt is generated. The sensing cycle time is programmable (see Section 6.10, "Averaging and Sampling Configuration Register"). 5.3.2 RECALIBRATING SENSOR INPUTS There are various options for recalibrating the capacitive touch sensor inputs. Recalibration re-sets the Base Count Registers (Section 6.24, "Sensor Input Base Count Registers") which contain the “not touched” values used for touch detection comparisons. APPLICATION NOTE: The device will recalibrate all sensor inputs that were disabled when it transitions from Standby. Likewise, the device will recalibrate all sensor inputs when waking out of Deep Sleep. CAP1133 DS00001625B-page 16  2015 Microchip Technology Inc. 5.3.2.1 Manual Recalibration The Calibration Activate Registers (Section 6.11, "Calibration Activate Register") force recalibration of selected sensor inputs. When a bit is set, the corresponding capacitive touch sensor input will be recalibrated (both analog and digital). The bit is automatically cleared once the recalibration routine has finished. 5.3.2.2 Automatic Recalibration Each sensor input is regularly recalibrated at a programmable rate (see Section 6.17, "Recalibration Configuration Register"). By default, the recalibration routine stores the average 64 previous measurements and periodically updates the base “not touched” setting for the capacitive touch sensor input. 5.3.2.3 Negative Delta Count Recalibration It is possible that the device loses sensitivity to a touch. This may happen as a result of a noisy environment, an accidental recalibration during a touch, or other environmental changes. When this occurs, the base untouched sensor input may generate negative delta count values. The NEG_DELTA_CNT bits (see Section 6.17, "Recalibration Configuration Register") can be set to force a recalibration after a specified number of consecutive negative delta readings. 5.3.2.4 Delayed Recalibration It is possible that a “stuck button” occurs when something is placed on a button which causes a touch to be detected for a long period. By setting the MAX_DUR_EN bit (see Section 6.6, "Configuration Registers"), a recalibration can be forced when a touch is held on a button for longer than the duration specified in the MAX_DUR bits (see Section 6.8, "Sensor Input Configuration Register"). 5.3.3 PROXIMITY DETECTION Each sensor input can be configured to detect changes in capacitance due to proximity of a touch. This circuitry detects the change of capacitance that is generated as an object approaches, but does not physically touch, the enabled sensor pad(s). When a sensor input is selected to perform proximity detection, it will be sampled from 1x to 128x per sampling cycle. The larger the number of samples that are taken, the greater the range of proximity detection is available at the cost of an increased overall sampling time. 5.3.4 MULTIPLE TOUCH PATTERN DETECTION The multiple touch pattern (MTP) detection circuitry can be used to detect lid closure or other similar events. An event can be flagged based on either a minimum number of sensor inputs or on specific sensor inputs simultaneously exceeding an MTP threshold or having their Noise Flag Status Register bits set. An interrupt can also be generated. During an MTP event, all touches are blocked (see Section 6.15, "Multiple Touch Pattern Configuration Register"). 5.3.5 LOW FREQUENCY NOISE DETECTION Each sensor input has an EMI noise detector that will sense if low frequency noise is injected onto the input with sufficient power to corrupt the readings. If this occurs, the device will reject the corrupted sample and set the corresponding bit in the Noise Status register to a logic ‘1’. Note: During this recalibration routine, the sensor inputs will not detect a press for up to 200ms and the Sensor Base Count Register values will be invalid. In addition, any press on the corresponding sensor pads will invalidate the recalibration. Note: Automatic recalibration only works when the delta count is below the active sensor input threshold. It is disabled when a touch is detected. Note: During this recalibration, the device will not respond to touches. Note: Delayed recalibration only works when the delta count is above the active sensor input threshold. If enabled, it is invoked when a sensor pad touch is held longer than the MAX_DUR bit setting.  2015 Microchip Technology Inc. DS00001625B-page 17 CAP1133 5.3.6 RF NOISE DETECTION Each sensor input contains an integrated RF noise detector. This block will detect injected RF noise on the CS pin. The detector threshold is dependent upon the noise frequency. If RF noise is detected on a CS line, that sample is removed and not compared against the threshold. 5.4 ALERT# Pin The ALERT# pin is an active low (or active high when configured) output that is driven when an interrupt event is detected. Whenever an interrupt is generated, the INT bit (see Section 6.1, "Main Control Register") is set. The ALERT# pin is cleared when the INT bit is cleared by the user. Additionally, when the INT bit is cleared by the user, status bits are only cleared if no touch is detected. 5.4.1 SENSOR INTERRUPT BEHAVIOR The sensor interrupts are generated in one of two ways: 1. An interrupt is generated when a touch is detected and, as a user selectable option, when a release is detected (by default - see Section 6.6). See Figure 5-3. 2. If the repeat rate is enabled then, so long as the touch is held, another interrupt will be generated based on the programmed repeat rate (see Figure 5-2). When the repeat rate is enabled, the device uses an additional control called MPRESS that determines whether a touch is flagged as a simple “touch” or a “press and hold”. The MPRESS[3:0] bits set a minimum press timer. When the button is touched, the timer begins. If the sensor pad is released before the minimum press timer expires, it is flagged as a touch and an interrupt is generated upon release. If the sensor input detects a touch for longer than this timer value, it is flagged as a “press and hold” event. So long as the touch is held, interrupts will be generated at the programmed repeat rate and upon release (if enabled). APPLICATION NOTE: Figure 5-2 and Figure 5-3 show default operation which is to generate an interrupt upon sensor pad release and an active-low ALERT# pin. APPLICATION NOTE: The host may need to poll the device twice to determine that a release has been detected. FIGURE 5-2: Sensor Interrupt Behavior - Repeat Rate Enabled Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Min Press Setting (280ms) Interrupt on Touch Button Repeat Rate (175ms) Button Repeat Rate (175ms) Interrupt on Release (optional) ALERT# pin (active low) CAP1133 DS00001625B-page 18  2015 Microchip Technology Inc. FIGURE 5-3: Sensor Interrupt Behavior - No Repeat Rate Enabled Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Interrupt on Touch Interrupt on Release (optional) ALERT# pin (active low)  2015 Microchip Technology Inc. DS00001625B-page 19 CAP1133 6.0 REGISTER DESCRIPTION The registers shown in Table 6-1 are accessible through the communications protocol. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Address R/W Register Name Function Default Value Page 00h R/W Main Control Controls general power states and power dissipation 00h Page 21 02h R General Status Stores general status bits 00h Page 22 03h R Sensor Input Status Returns the state of the sampled capacitive touch sensor inputs 00h Page 22 04h R LED Status Stores status bits for LEDs 00h Page 22 0Ah R Noise Flag Status Stores the noise flags for sensor inputs 00h Page 23 10h R Sensor Input 1 Delta Count Stores the delta count for CS1 00h Page 23 11h R Sensor Input 2 Delta Count Stores the delta count for CS2 00h Page 23 12h R Sensor Input 3 Delta Count Stores the delta count for CS3 00h Page 23 1Fh R/W Sensitivity Control Controls the sensitivity of the threshold and delta counts and data scaling of the base counts 2Fh Page 24 20h R/W Configuration Controls general functionality 20h Page 25 21h R/W Sensor Input Enable Controls whether the capacitive touch sensor inputs are sampled 07h Page 26 22h R/W Sensor Input Configuration Controls max duration and auto-repeat delay for sensor inputs operating in the full power state A4h Page 27 23h R/W Sensor Input Configuration 2 Controls the MPRESS controls for all sensor inputs 07h Page 28 24h R/W Averaging and Sampling Config Controls averaging and sampling window 39h Page 28 26h R/W Calibration Activate Forces re-calibration for capacitive touch sensor inputs 00h Page 30 27h R/W Interrupt Enable Enables Interrupts associated with capacitive touch sensor inputs 07h Page 30 28h R/W Repeat Rate Enable Enables repeat rate for all sensor inputs 07h Page 30 2Ah R/W Multiple Touch Configuration Determines the number of simultaneous touches to flag a multiple touch condition 80h Page 31 2Bh R/W Multiple Touch Pattern Configuration Determines the multiple touch pattern (MTP) configuration 00h Page 31 2Dh R/W Multiple Touch Pattern Determines the pattern or number of sensor inputs used by the MTP circuitry 07h Page 32 2Fh R/W Recalibration Configuration Determines re-calibration timing and sampling window 8Ah Page 33 30h R/W Sensor Input 1 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 1 40h Page 34 CAP1133 DS00001625B-page 20  2015 Microchip Technology Inc. 31h R/W Sensor Input 2 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 2 40h Page 34 32h R/W Sensor Input 3 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 3 40h Page 34 38h R/W Sensor Input Noise Threshold Stores controls for selecting the noise threshold for all sensor inputs 01h Page 34 Standby Configuration Registers 40h R/W Standby Channel Controls which sensor inputs are enabled while in standby 00h Page 35 41h R/W Standby Configuration Controls averaging and cycle time while in standby 39h Page 35 42h R/W Standby Sensitivity Controls sensitivity settings used while in standby 02h Page 36 43h R/W Standby Threshold Stores the touch detection threshold for active sensor inputs in standby 40h Page 37 44h R/W Configuration 2 Stores additional configuration controls for the device 40h Page 25 Base Count Registers 50h R Sensor Input 1 Base Count Stores the reference count value for sensor input 1 C8h Page 37 51h R Sensor Input 2 Base Count Stores the reference count value for sensor input 2 C8h Page 37 52h R Sensor Input 3 Base Count Stores the reference count value for sensor input 3 C8h Page 37 LED Controls 71h R/W LED Output Type Controls the output type for the LED outputs 00h Page 38 72h R/W Sensor Input LED Linking Controls linking of sensor inputs to LED channels 00h Page 38 73h R/W LED Polarity Controls the output polarity of LEDs 00h Page 38 74h R/W LED Output Control Controls the output state of the LEDs 00h Page 39 77h R/W Linked LED Transition Control Controls the transition when LEDs are linked to CS channels 00h Page 40 79h R/W LED Mirror Control Controls the mirroring of duty cycles for the LEDs 00h Page 41 81h R/W LED Behavior 1 Controls the behavior and response of LEDs 1 - 3 00h Page 41 84h R/W LED Pulse 1 Period Controls the period of each breathe during a pulse 20h Page 43 85h R/W LED Pulse 2 Period Controls the period of the breathing during breathe and pulse operation 14h Page 45 86h R/W LED Breathe Period Controls the period of an LED breathe operation 5Dh Page 46 88h R/W LED Config Controls LED configuration 04h Page 46 90h R/W LED Pulse 1 Duty Cycle Determines the min and max duty cycle for the pulse operation F0h Page 47 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page  2015 Microchip Technology Inc. DS00001625B-page 21 CAP1133 During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. When a bit is “set”, this means that the user writes a logic ‘1’ to it. When a bit is “cleared”, this means that the user writes a logic ‘0’ to it. 6.1 Main Control Register The Main Control register controls the primary power state of the device. Bits 7 - 6 - GAIN[1:0] - Controls the gain used by the capacitive touch sensing circuitry. As the gain is increased, the effective sensitivity is likewise increased as a smaller delta capacitance is required to generate the same delta count values. The sensitivity settings may need to be adjusted along with the gain settings such that data overflow does not occur. APPLICATION NOTE: The gain settings apply to both Standby and Active states. 91h R/W LED Pulse 2 Duty Cycle Determines the min and max duty cycle for breathe and pulse operation F0h Page 47 92h R/W LED Breathe Duty Cycle Determines the min and max duty cycle for the breathe operation F0h Page 47 93h R/W LED Direct Duty Cycle Determines the min and max duty cycle for Direct mode LED operation F0h Page 47 94h R/W LED Direct Ramp Rates Determines the rising and falling edge ramp rates of the LEDs 00h Page 47 95h R/W LED Off Delay Determines the off delay for all LED behaviors 00h Page 48 B1h R Sensor Input 1 Calibration Stores the upper 8-bit calibration value for sensor input 1 00h Page 51 B2h R Sensor Input 2 Calibration Stores the upper 8-bit calibration value for sensor input 2 00h Page 51 B3h R Sensor Input 3 Calibration Stores the upper 8-bit calibration value for sensor input 3 00h Page 51 B9h R Sensor Input Calibration LSB 1 Stores the 2 LSBs of the calibration value for sensor inputs 1 - 3 00h Page 51 FDh R Product ID Stores a fixed value that identifies each product 54h Page 51 FEh R Manufacturer ID Stores a fixed value that identifies Microchip 5Dh Page 52 FFh R Revision Stores a fixed value that represents the revision number 83h Page 52 TABLE 6-2: MAIN CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 00h R/W Main Control GAIN[1:0] STBY DSLEEP - - - INT 00h TABLE 6-3: GAIN BIT DECODE GAIN[1:0] Capacitive Touch Sensor Gain 1 0 0 0 1 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1133 DS00001625B-page 22  2015 Microchip Technology Inc. Bit 5 - STBY - Enables Standby. • ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - Capacitive touch sensor input scanning is limited to the sensor inputs set in the Standby Channel register (see Section 6.20). The status registers will not be cleared until read. LEDs that are linked to capacitive touch sensor inputs will remain linked and active. Sensor inputs that are no longer sampled will flag a release and then remain in a non-touched state. LEDs that are manually controlled will be unaffected. • Bit 4 - DSLEEP - Enables Deep Sleep by deactivating all functions. ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - All sensor input scanning is disabled. All LEDs are driven to their programmed non-actuated state and no PWM operations will be done. The status registers are automatically cleared and the INT bit is cleared. Bit 0 - INT - Indicates that there is an interrupt. When this bit is set, it asserts the ALERT# pin. If a channel detects a touch and its associated interrupt enable bit is not set to a logic ‘1’, no action is taken. This bit is cleared by writing a logic ‘0’ to it. When this bit is cleared, the ALERT# pin will be deasserted and all status registers will be cleared if the condition has been removed. • ‘0’ - No interrupt pending. • ‘1’ - A touch has been detected on one or more channels and the interrupt has been asserted. 6.2 Status Registers All status bits are cleared when the device enters the Deep Sleep (DSLEEP = ‘1’ - see Section 6.1). 6.2.1 GENERAL STATUS - 02H Bit 4 - LED - Indicates that one or more LEDs have finished their programmed activity. This bit is set if any bit in the LED Status register is set. Bit 2 - MULT - Indicates that the device is blocking detected touches due to the Multiple Touch detection circuitry (see Section 6.14). This bit will not cause the INT bit to be set and hence will not cause an interrupt. Bit 1 - MTP - Indicates that the device has detected a number of sensor inputs that exceed the MTP threshold either via the pattern recognition or via the number of sensor inputs (see Section 6.15). This bit will cause the INT bit to be set if the MTP_ALERT bit is also set. This bit will not be cleared until the condition that caused it to be set has been removed. Bit 0 - TOUCH - Indicates that a touch was detected. This bit is set if any bit in the Sensor Input Status register is set. 6.2.2 SENSOR INPUT STATUS - 03H The Sensor Input Status Register stores status bits that indicate a touch has been detected. A value of ‘0’ in any bit indicates that no touch has been detected. A value of ‘1’ in any bit indicates that a touch has been detected. 01 2 10 4 11 8 TABLE 6-4: STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 02h R General Status - - - LED - MULT MTP TOUCH 00h 03h R Sensor Input Status - - - - - CS3 CS2 CS1 00h 04h R LED Status - - - - - LED3_ DN LED2_ DN LED1_ DN 00h TABLE 6-3: GAIN BIT DECODE (CONTINUED) GAIN[1:0] Capacitive Touch Sensor Gain 1 0  2015 Microchip Technology Inc. DS00001625B-page 23 CAP1133 All bits are cleared when the INT bit is cleared and if a touch on the respective capacitive touch sensor input is no longer present. If a touch is still detected, the bits will not be cleared (but this will not cause the interrupt to be asserted - see Section 6.6). Bit 2 - CS3 - Indicates that a touch was detected on Sensor Input 3. This sensor input can be linked to LED3. Bit 1 - CS2 - Indicates that a touch was detected on Sensor Input 2. This sensor input can be linked to LED2. Bit 0 - CS1 - Indicates that a touch was detected on Sensor Input 1. This sensor input can be linked to LED1. 6.2.3 LED STATUS - 04H The LED Status Registers indicate when an LED has completed its configured behavior (see Section 6.31, "LED Behavior Register") after being actuated by the host (see Section 6.28, "LED Output Control Register"). These bits are ignored when the LED is linked to a capacitive sensor input. All LED Status bits are cleared when the INT bit is cleared. Bit 2 - LED3_DN - Indicates that LED3 has finished its behavior after being actuated by the host. Bit 1 - LED2_DN - Indicates that LED2 has finished its behavior after being actuated by the host. Bit 0 - LED1_DN - Indicates that LED1 has finished its behavior after being actuated by the host. 6.3 Noise Flag Status Registers The Noise Flag Status registers store status bits that are generated from the analog block if the detected noise is above the operating region of the analog detector or the RF noise detector. These bits indicate that the most recently received data from the sensor input is invalid and should not be used for touch detection. So long as the bit is set for a particular channel, the delta count value is reset to 00h and thus no touch is detected. These bits are not sticky and will be cleared automatically if the analog block does not report a noise error. APPLICATION NOTE: If the MTP detection circuitry is enabled, these bits count as sensor inputs above the MTP threshold (see Section 5.3.4, "Multiple Touch Pattern Detection") even if the corresponding delta count is not. If the corresponding delta count also exceeds the MTP threshold, it is not counted twice. APPLICATION NOTE: Regardless of the state of the Noise Status bits, if low frequency noise is detected on a sensor input, that sample will be discarded unless the DIS_ANA_NOISE bit is set. As well, if RF noise is detected on a sensor input, that sample will be discarded unless the DIS_RF_NOISE bit is set. 6.4 Sensor Input Delta Count Registers The Sensor Input Delta Count registers store the delta count that is compared against the threshold used to determine if a touch has been detected. The count value represents a change in input due to the capacitance associated with a touch on one of the sensor inputs and is referenced to a calibrated base “Not Touched” count value. The delta is an instantaneous change and is updated once per sensor input per sensing cycle (see Section 5.3.1, "Sensing Cycle"). TABLE 6-5: NOISE FLAG STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 0Ah R Noise Flag Status - - - CS3_ NOISE CS2_ NOISE CS1_ NOISE 00h TABLE 6-6: SENSOR INPUT DELTA COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 10h R Sensor Input 1 Delta Count Sign 64 32 16 8 4 2 1 00h 11h R Sensor Input 2 Delta Count Sign 64 32 16 8 4 2 1 00h 12h R Sensor Input 3 Delta Count Sign 64 32 16 8 4 2 1 00h CAP1133 DS00001625B-page 24  2015 Microchip Technology Inc. The value presented is a standard 2’s complement number. In addition, the value is capped at a value of 7Fh. A reading of 7Fh indicates that the sensitivity settings are too high and should be adjusted accordingly (see Section 6.5). The value is also capped at a negative value of 80h for negative delta counts which may result upon a release. 6.5 Sensitivity Control Register The Sensitivity Control register controls the sensitivity of a touch detection. Bits 6-4 DELTA_SENSE[2:0] - Controls the sensitivity of a touch detection. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta capacitance corresponding to a “lighter” touch. These settings are more sensitive to noise, however, and a noisy environment may flag more false touches with higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely, a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). Bits 3 - 0 - BASE_SHIFT[3:0] - Controls the scaling and data presentation of the Base Count registers. The higher the value of these bits, the larger the range and the lower the resolution of the data presented. The scale factor represents the multiplier to the bit-weighting presented in these register descriptions. APPLICATION NOTE: The BASE_SHIFT[3:0] bits normally do not need to be updated. These settings will not affect touch detection or sensitivity. These bits are sometimes helpful in analyzing the Cap Sensing board performance and stability. TABLE 6-7: SENSITIVITY CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 1Fh R/W Sensitivity Control - DELTA_SENSE[2:0] BASE_SHIFT[3:0] 2Fh TABLE 6-8: DELTA_SENSE BIT DECODE DELTA_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-9: BASE_SHIFT BIT DECODE BASE_SHIFT[3:0] Data Scaling Factor 32 1 0 0 0 0 0 1x 0 0 0 1 2x 0 0 1 0 4x 0 0 1 1 8x  2015 Microchip Technology Inc. DS00001625B-page 25 CAP1133 6.6 Configuration Registers The Configuration registers control general global functionality that affects the entire device. 6.6.1 CONFIGURATION - 20H Bit 7 - TIMEOUT - Enables the timeout and idle functionality of the SMBus protocol. • ‘0’ (default for Functional Revision C) - The SMBus timeout and idle functionality are disabled. The SMBus interface will not time out if the clock line is held low. Likewise, it will not reset if both the data and clock lines are held high for longer than 200us. This is used for I2C compliance. • ‘1’ (default for Functional Revision B) - The SMBus timeout and idle functionality are enabled. The SMBus interface will time out if the clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock lines are held high for longer than 200us. Bit 5 - DIS_DIG_NOISE - Determines whether the digital noise threshold (see Section 6.19, "Sensor Input Noise Threshold Register") is used by the device. Setting this bit disables the feature. • ‘0’ - The digital noise threshold is used. If a delta count value exceeds the noise threshold but does not exceed the touch threshold, the sample is discarded and not used for the automatic re-calibration routine. • ‘1’ (default) - The noise threshold is disabled. Any delta count that is less than the touch threshold is used for the automatic re-calibration routine. Bit 4 - DIS_ANA_NOISE - Determines whether the analog noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If low frequency noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if low frequency noise is detected. Bit 3 - MAX_DUR_EN - Determines whether the maximum duration recalibration is enabled. • ‘0’ (default) - The maximum duration recalibration functionality is disabled. A touch may be held indefinitely and no re-calibration will be performed on any sensor input. • ‘1’ - The maximum duration recalibration functionality is enabled. If a touch is held for longer than the MAX_DUR bit settings, then the re-calibration routine will be restarted (see Section 6.8). 0 1 0 0 16x 0 1 0 1 32x 0 1 1 0 64x 0 1 1 1 128x 1 0 0 0 256x All others 256x (default = 1111b) TABLE 6-10: CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 20h R/W Configuration TIMEOUT - DIS_ DIG_ NOISE DIS_ ANA_ NOISE MAX_ DUR_EN - -- A0h (Rev B) 20h (rev C) 44h R/W Configuration 2 INV_LINK_ TRAN ALT_ POL BLK_PWR_ CTRL BLK_POL_ MIR SHOW_ RF_ NOISE DIS_ RF_ NOISE - INT_ REL_n 40h TABLE 6-9: BASE_SHIFT BIT DECODE (CONTINUED) BASE_SHIFT[3:0] Data Scaling Factor 32 1 0 CAP1133 DS00001625B-page 26  2015 Microchip Technology Inc. 6.6.2 CONFIGURATION 2 - 44H Bit 7 - INV_LINK_TRAN - Determines the behavior of the Linked LED Transition controls (see Section 6.29). • ‘0’ (default) - The Linked LED Transition controls set the min duty cycle equal to the max duty cycle. • ‘1’ - The Linked LED Transition controls will invert the touch signal. For example, a touch signal will be inverted to a non-touched signal. Bit 6 - ALT_POL - Determines the ALERT# pin polarity and behavior. • ‘0’ - The ALERT# pin is active high and push-pull. • ‘1’ (default) - The ALERT# pin is active low and open drain. Bit 5 - BLK_PWR_CTRL - Determines whether the device will reduce power consumption while waiting between conversion time completion and the end of the polling cycle. • ‘0’ (default) - The device will always power down as much as possible during the time between the end of the last conversion and the end of the polling cycle. • ‘1’ - The device will not power down the Cap Sensor during the time between the end of the last conversion and the end of the polling cycle. Bit 4 - BLK_POL_MIR - Determines whether the LED Mirror Control register bits are linked to the LED Polarity bits. Setting this bit blocks the normal behavior which is to automatically set and clear the LED Mirror Control bits when the LED Polarity bits are set or cleared. • ‘0’ (default) - When the LED Polarity controls are set, the corresponding LED Mirror control is automatically set. Likewise, when the LED Polarity controls are cleared, the corresponding LED Mirror control is also cleared. • ‘1’ - When the LED Polarity controls are set, the corresponding LED Mirror control is not automatically set. Bit 3 - SHOW_RF_NOISE - Determines whether the Noise Status bits will show RF Noise as the only input source. • ‘0’ (default) - The Noise Status registers will show both RF noise and low frequency EMI noise if either is detected on a capacitive touch sensor input. • ‘1’ - The Noise Status registers will only show RF noise if it is detected on a capacitive touch sensor input. EMI noise will still be detected and touches will be blocked normally; however, the status bits will not be updated. Bit 2 - DIS_RF_NOISE - Determines whether the RF noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If RF noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if RF noise is detected. Bit 0 - INT_REL_n - Controls the interrupt behavior when a release is detected on a button. • ‘0’ (default) - An interrupt is generated when a press is detected and again when a release is detected and at the repeat rate (if enabled - see Section 6.13). • ‘1’ - An interrupt is generated when a press is detected and at the repeat rate but not when a release is detected. 6.7 Sensor Input Enable Registers The Sensor Input Enable registers determine whether a capacitive touch sensor input is included in the sampling cycle. The length of the sampling cycle is not affected by the number of sensor inputs measured. Bit 2 - CS3_EN - Enables the CS3 input to be included during the sampling cycle. • ‘0’ - The CS3 input is not included in the sampling cycle. • ‘1’ (default) - The CS3 input is included in the sampling cycle. Bit 1 - CS2_EN - Enables the CS2 input to be included during the sampling cycle. Bit 0 - CS1_EN - Enables the CS1 input to be included during the sampling cycle. TABLE 6-11: SENSOR INPUT ENABLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 21h R/W Sensor Input Enable - - - - - CS3_EN CS2_EN CS1_EN 07h  2015 Microchip Technology Inc. DS00001625B-page 27 CAP1133 6.8 Sensor Input Configuration Register The Sensor Input Configuration Register controls timings associated with the Capacitive sensor inputs 1 - 3. Bits 7 - 4 - MAX_DUR[3:0] - (default 1010b) - Determines the maximum time that a sensor pad is allowed to be touched until the capacitive touch sensor input is recalibrated, as shown in Table 6-13. Bits 3 - 0 - RPT_RATE[3:0] - (default 0100b) Determines the time duration between interrupt assertions when auto repeat is enabled. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-14. TABLE 6-12: SENSOR INPUT CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 22h R/W Sensor Input Configuration MAX_DUR[3:0] RPT_RATE[3:0] A4h TABLE 6-13: MAX_DUR BIT DECODE MAX_DUR[3:0] Time Before Recalibration 32 1 0 0 0 0 0 560ms 0 0 0 1 840ms 0 0 1 0 1120ms 0 0 1 1 1400ms 0 1 0 0 1680ms 0 1 0 1 2240ms 0 1 1 0 2800ms 1 1 1 3360ms 1 0 0 0 3920ms 1 0 0 1 4480ms 1 0 1 0 5600ms (default) 1 0 1 1 6720ms 1 1 0 0 7840ms 1 1 0 1 8906ms 1 1 1 0 10080ms 1 1 1 1 11200ms TABLE 6-14: RPT_RATE BIT DECODE RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms (default) 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms CAP1133 DS00001625B-page 28  2015 Microchip Technology Inc. 6.9 Sensor Input Configuration 2 Register Bits 3 - 0 - M_PRESS[3:0] - (default 0111b) - Determines the minimum amount of time that sensor inputs configured to use auto repeat must detect a sensor pad touch to detect a “press and hold” event. If the sensor input detects a touch for longer than the M_PRESS[3:0] settings, a “press and hold” event is detected. If a sensor input detects a touch for less than or equal to the M_PRESS[3:0] settings, a touch event is detected. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-16. 6.10 Averaging and Sampling Configuration Register 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-15: SENSOR INPUT CONFIGURATION 2 REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 23h R/W Sensor Input Configuration 2 - - - - M_PRESS[3:0] 07h TABLE 6-16: M_PRESS BIT DECODE M_PRESS[3:0] M_PRESS SETTINGS 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms (default) 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-17: AVERAGING AND SAMPLING CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 24h R/W Averaging and Sampling Config AVG[2:0] SAMP_TIME[1:0] CYCLE_TIME [1:0] 39h TABLE 6-14: RPT_RATE BIT DECODE (CONTINUED) RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0  2015 Microchip Technology Inc. DS00001625B-page 29 CAP1133 The Averaging and Sampling Configuration register controls the number of samples taken and the total sensor input cycle time for all active sensor inputs while the device is functioning in Active state. Bits 6 - 4 - AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-18. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. For example, if CS1, CS2, and CS3 are sampled during the sensor cycle, and the AVG[2:0] bits are set to take 4 samples per channel, then the full sensor cycle will be: CS1, CS1, CS1, CS1, CS2, CS2, CS2, CS2, CS3, CS3, CS3, CS3. Bits 3 - 2 - SAMP_TIME[1:0] - Determines the time to take a single sample as shown in Table 6-19. Bits 1 - 0 - CYCLE_TIME[1:0] - Determines the overall cycle time for all measured channels during normal operation as shown in Table 6-20. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, then the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. TABLE 6-18: AVG BIT DECODE AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-19: SAMP_TIME BIT DECODE SAMP_TIME[1:0] Sample Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-20: CYCLE_TIME BIT DECODE CYCLE_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms CAP1133 DS00001625B-page 30  2015 Microchip Technology Inc. 6.11 Calibration Activate Register The Calibration Activate register forces the respective sensor inputs to be re-calibrated affecting both the analog and digital blocks. During the re-calibration routine, the sensor inputs will not detect a press for up to 600ms and the Sensor Input Base Count register values will be invalid. During this time, any press on the corresponding sensor pads will invalidate the re-calibration. When finished, the CALX[9:0] bits will be updated (see Section 6.39). When the corresponding bit is set, the device will perform the calibration and the bit will be automatically cleared once the re-calibration routine has finished. Bit 2 - CS3_CAL - When set, the CS3 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 1 - CS2_CAL - When set, the CS2 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 0 - CS1_CAL - When set, the CS1 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. 6.12 Interrupt Enable Register The Interrupt Enable register determines whether a sensor pad touch or release (if enabled) causes the interrupt pin to be asserted. Bit 2 - CS3_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS3 (associated with the CS3 status bit). • ‘0’ - The interrupt pin will not be asserted if a touch is detected on CS3 (associated with the CS6 status bit). • ‘1’ (default) - The interrupt pin will be asserted if a touch is detected on CS3 (associated with the CS6 status bit). Bit 1 - CS2_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS2 (associated with the CS2 status bit). Bit 0 - CS1_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS1 (associated with the CS1 status bit). 6.13 Repeat Rate Enable Register The Repeat Rate Enable register enables the repeat rate of the sensor inputs as described in Section 5.4.1. Bit 2 - CS3_RPT_EN - Enables the repeat rate for capacitive touch sensor input 3. • ‘0’ - The repeat rate for CS3 is disabled. It will only generate an interrupt when a touch is detected and when a release is detected no matter how long the touch is held for. • ‘1’ (default) - The repeat rate for CS3 is enabled. In the case of a “touch” event, it will generate an interrupt when a touch is detected and a release is detected (as determined by the INT_REL_n bit - see Section 6.6). In the case of a “press and hold” event, it will generate an interrupt when a touch is detected and at the repeat rate so long as TABLE 6-21: CALIBRATION ACTIVATE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 26h R/W Calibration Activate --- CS3_ CAL CS2_ CAL CS1_ CAL 00h TABLE 6-22: INTERRUPT ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 27h R/W Interrupt Enable --- CS3_ INT_EN CS2_ INT_EN CS1_ INT_EN 07h TABLE 6-23: REPEAT RATE ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 28h R/W Repeat Rate Enable ---- - CS3_ RPT_EN CS2_ RPT_EN CS1_ RPT_EN 07h  2015 Microchip Technology Inc. DS00001625B-page 31 CAP1133 the touch is held d. Bit 1 - CS2_RPT_EN - Enables the repeat rate for capacitive touch sensor input 2. Bit 0 - CS1_RPT_EN - Enables the repeat rate for capacitive touch sensor input 1. 6.14 Multiple Touch Configuration Register The Multiple Touch Configuration register controls the settings for the multiple touch detection circuitry. These settings determine the number of simultaneous buttons that may be pressed before additional buttons are blocked and the MULT status bit is set. Bit 7 - MULT_BLK_EN - Enables the multiple button blocking circuitry. • ‘0’ - The multiple touch circuitry is disabled. The device will not block multiple touches. • ‘1’ (default) - The multiple touch circuitry is enabled. The device will flag the number of touches equal to programmed multiple touch threshold and block all others. It will remember which sensor inputs are valid and block all others until that sensor pad has been released. Once a sensor pad has been released, the N detected touches (determined via the cycle order of CS1 - CS3) will be flagged and all others blocked. Bits 3 - 2 - B_MULT_T[1:0] - Determines the number of simultaneous touches on all sensor pads before a Multiple Touch Event is detected and sensor inputs are blocked. The bit decode is given by Table 6-25. 6.15 Multiple Touch Pattern Configuration Register The Multiple Touch Pattern Configuration register controls the settings for the multiple touch pattern detection circuitry. This circuitry works like the multiple touch detection circuitry with the following differences: 1. The detection threshold is a percentage of the touch detection threshold as defined by the MTP_TH[1:0] bits whereas the multiple touch circuitry uses the touch detection threshold. 2. The MTP detection circuitry either will detect a specific pattern of sensor inputs as determined by the Multiple Touch Pattern register settings or it will use the Multiple Touch Pattern register settings to determine a minimum number of sensor inputs that will cause the MTP circuitry to flag an event. When using pattern recognition mode, if all of the sensor inputs set by the Multiple Touch Pattern register have a delta count greater than the MTP threshold or have their corresponding Noise Flag Status bits set, the MTP bit will be set. When using the absolute number mode, if the number of sensor inputs with thresholds above the MTP threshold or with Noise Flag Status bits set is equal to or greater than this number, the MTP bit will be set. 3. When an MTP event occurs, all touches are blocked and an interrupt is generated. TABLE 6-24: MULTIPLE TOUCH CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Ah R/W Multiple Touch Config MULT_ BLK_ EN - - - B_MULT_T[1:0] - - 80h TABLE 6-25: B_MULT_T BIT DECODE B_MULT_T[1:0] Number of Simultaneous Touches 1 0 0 0 1 (default) 01 2 10 3 11 3 TABLE 6-26: MULTIPLE TOUCH PATTERN CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Bh R/W Multiple Touch Pattern Config MTP_ EN - - MTP_TH[1:0] COMP_ PTRN MTP_ ALERT 00h CAP1133 DS00001625B-page 32  2015 Microchip Technology Inc. 4. All sensor inputs will remain blocked so long as the requisite number of sensor inputs are above the MTP threshold or have Noise Flag Status bits set. Once this condition is removed, touch detection will be restored. Note that the MTP status bit is only cleared by writing a ‘0’ to the INT bit once the condition has been removed. Bit 7 - MTP_EN - Enables the multiple touch pattern detection circuitry. • ‘0’ (default) - The MTP detection circuitry is disabled. • ‘1’ - The MTP detection circuitry is enabled. Bits 3-2 - MTP_TH[1:0] - Determine the MTP threshold, as shown in Table 6-27. This threshold is a percentage of sensor input threshold (see Section 6.18, "Sensor Input Threshold Registers") when the device is in the Fully Active state or of the standby threshold (see Section 6.23, "Standby Threshold Register") when the device is in the Standby state. Bit 1 - COMP_PTRN - Determines whether the MTP detection circuitry will use the Multiple Touch Pattern register as a specific pattern of sensor inputs or as an absolute number of sensor inputs. • ‘0’ (default) - The MTP detection circuitry will use the Multiple Touch Pattern register bit settings as an absolute minimum number of sensor inputs that must be above the threshold or have Noise Flag Status bits set. The number will be equal to the number of bits set in the register. • ‘1’ - The MTP detection circuitry will use pattern recognition. Each bit set in the Multiple Touch Pattern register indicates a specific sensor input that must have a delta count greater than the MTP threshold or have a Noise Flag Status bit set. If the criteria are met, the MTP status bit will be set. Bit 0 - MTP_ALERT - Enables an interrupt if an MTP event occurs. In either condition, the MTP status bit will be set. • ‘0’ (default) - If an MTP event occurs, the ALERT# pin is not asserted. • ‘1’ - If an MTP event occurs, the ALERT# pin will be asserted. 6.16 Multiple Touch Pattern Register The Multiple Touch Pattern register acts as a pattern to identify an expected sensor input profile for diagnostics or other significant events. There are two methods for how the Multiple Touch Pattern register is used: as specific sensor inputs or number of sensor input that must exceed the MTP threshold or have Noise Flag Status bits set. Which method is used is based on the COMP_PTRN bit (see Section 6.15). The methods are described below. 1. Specific Sensor Inputs: If, during a single polling cycle, the specific sensor inputs above the MTP threshold or with Noise Flag Status bits set match those bits set in the Multiple Touch Pattern register, an MTP event is flagged. 2. Number of Sensor Inputs: If, during a single polling cycle, the number of sensor inputs with a delta count above the MTP threshold or with Noise Flag Status bits set is equal to or greater than the number of pattern bits set, an MTP event is flagged. Bit 2 - CS3_PTRN - Determines whether CS3 is considered as part of the Multiple Touch Pattern. • ‘0’ - CS3 is not considered a part of the pattern. • ‘1’ - CS3 is considered a part of the pattern or the absolute number of sensor inputs that must have a delta count greater than the MTP threshold or have the Noise Flag Status bit set is increased by 1. TABLE 6-27: MTP_TH BIT DECODE MTP_TH[1:0] Threshold Divide Setting 1 0 0 0 12.5% (default) 0 1 25% 1 0 37.5% 1 1 100% TABLE 6-28: MULTIPLE TOUCH PATTERN REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Dh R/W Multiple Touch Pattern --- CS3_ PTRN CS2_ PTRN CS1_ PTRN 07h  2015 Microchip Technology Inc. DS00001625B-page 33 CAP1133 Bit 1 - CS2_PTRN - Determines whether CS2 is considered as part of the Multiple Touch Pattern. Bit 0 - CS1_PTRN - Determines whether CS1 is considered as part of the Multiple Touch Pattern. 6.17 Recalibration Configuration Register The Recalibration Configuration register controls the automatic re-calibration routine settings as well as advanced controls to program the Sensor Input Threshold register settings. Bit 7 - BUT_LD_TH - Enables setting all Sensor Input Threshold registers by writing to the Sensor Input 1 Threshold register. • ‘0’ - Each Sensor Input X Threshold register is updated individually. • ‘1’ (default) - Writing the Sensor Input 1 Threshold register will automatically overwrite the Sensor Input Threshold registers for all sensor inputs (Sensor Input Threshold 1 through Sensor Input Threshold 3). The individual Sensor Input X Threshold registers (Sensor Input 2 Threshold and Sensor Input 3 Threshold) can be individually updated at any time. Bit 6 - NO_CLR_INTD - Controls whether the accumulation of intermediate data is cleared if the noise status bit is set. • ‘0’ (default) - The accumulation of intermediate data is cleared if the noise status bit is set. • ‘1’ - The accumulation of intermediate data is not cleared if the noise status bit is set. APPLICATION NOTE: Bits 5 and 6 should both be set to the same value. Either both should be set to ‘0’ or both should be set to ‘1’. Bit 5 - NO_CLR_NEG - Controls whether the consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘0’ (default) - The consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘1’ - The consecutive negative delta counts counter is not cleared if the noise status bit is set. Bits 4 - 3 - NEG_DELTA_CNT[1:0] - Determines the number of negative delta counts necessary to trigger a digital recalibration as shown in Table 6-30. Bits 2 - 0 - CAL_CFG[2:0] - Determines the update time and number of samples of the automatic re-calibration routine. The settings apply to all sensor inputs universally (though individual sensor inputs can be configured to support re-calibration - see Section 6.11). TABLE 6-29: RECALIBRATION CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Fh R/W Recalibration Configuration BUT_ LD_TH NO_ CLR_ INTD NO_ CLR_ NEG NEG_DELTA_ CNT[1:0] CAL_CFG[2:0] 8Ah TABLE 6-30: NEG_DELTA_CNT BIT DECODE NEG_DELTA_CNT[1:0] Number of Consecutive Negative Delta Count Values 1 0 00 8 0 1 16 (default) 1 0 32 1 1 None (disabled) TABLE 6-31: CAL_CFG BIT DECODE CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210 0 0 0 16 16 0 0 1 32 32 CAP1133 DS00001625B-page 34  2015 Microchip Technology Inc. Note 6-1 Recalibration Samples refers to the number of samples that are measured and averaged before the Base Count is updated however does not control the base count update period. Note 6-2 Update Time refers to the amount of time (in polling cycle periods) that elapses before the Base Count is updated. The time will depend upon the number of channels active, the averaging setting, and the programmed cycle time. 6.18 Sensor Input Threshold Registers The Sensor Input Threshold registers store the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. When the BUT_LD_TH bit is set (see Section 6.17 - bit 7), writing data to the Sensor Input 1 Threshold register will update all of the sensor input threshold registers (31h - 32h inclusive). 6.19 Sensor Input Noise Threshold Register The Sensor Input Noise Threshold register controls the value of a secondary internal threshold to detect noise and improve the automatic recalibration routine. If a capacitive touch sensor input exceeds the Sensor Input Noise Threshold but does not exceed the sensor input threshold, it is determined to be caused by a noise spike. That sample is not used by the automatic re-calibration routine. This feature can be disabled by setting the DIS_DIG_NOISE bit. Bits 1-0 - CS1_BN_TH[1:0] - Controls the noise threshold for all capacitive touch sensor inputs, as shown in Table 6-34. The threshold is proportional to the threshold setting. 0 1 0 64 64 (default) 0 1 1 128 128 1 0 0 256 256 1 0 1 256 1024 1 1 0 256 2048 1 1 1 256 4096 TABLE 6-32: SENSOR INPUT THRESHOLD REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 30h R/W Sensor Input 1 Threshold - 64 32 16 8 4 2 1 40h 31h R/W Sensor Input 2 Threshold - 64 32 16 8 4 2 1 40h 32h R/W Sensor Input 3 Threshold - 64 32 16 8 4 2 1 40h TABLE 6-33: SENSOR INPUT NOISE THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 38h R/W Sensor Input Noise Threshold CS_BN_TH [1:0] 01h TABLE 6-31: CAL_CFG BIT DECODE (CONTINUED) CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210  2015 Microchip Technology Inc. DS00001625B-page 35 CAP1133 6.20 Standby Channel Register The Standby Channel register controls which (if any) capacitive touch sensor inputs are active during Standby. Bit 2 - CS3_STBY - Controls whether the CS3 channel is active in Standby. • ‘0’ (default) - The CS3 channel not be sampled during Standby mode. • ‘1’ - The CS3 channel will be sampled during Standby Mode. It will use the Standby threshold setting, and the standby averaging and sensitivity settings. Bit 1 - CS2_STBY - Controls whether the CS2 channel is active in Standby. Bit 0 - CS1_STBY - Controls whether the CS1 channel is active in Standby. 6.21 Standby Configuration Register The Standby Configuration register controls averaging and cycle time for those sensor inputs that are active in Standby. This register is useful for detecting proximity on a small number of sensor inputs as it allows the user to change averaging and sample times on a limited number of sensor inputs and still maintain normal functionality in the fully active state. Bit 7 - AVG_SUM - Determines whether the active sensor inputs will average the programmed number of samples or whether they will accumulate for the programmed number of samples. • ‘0’ - (default) - The active sensor input delta count values will be based on the average of the programmed number of samples when compared against the threshold. • ‘1’ - The active sensor input delta count values will be based on the summation of the programmed number of samples when compared against the threshold. This bit should only be set when performing proximity detection as a physical touch will overflow the delta count registers and may result in false readings. Bits 6 - 4 - STBY_AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-37. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. TABLE 6-34: CSX_BN_TH BIT DECODE CS_BN_TH[1:0] Percent Threshold Setting 1 0 0 0 25% 0 1 37.5% (default) 1 0 50% 1 1 62.5% TABLE 6-35: STANDBY CHANNEL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 40h R/W Standby Channel - - - - - CS3_ STBY CS2_ STBY CS1_ STBY 00h TABLE 6-36: STANDBY CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 41h R/W Standby Configuration AVG_ SUM STBY_AVG[2:0] STBY_SAMP_ TIME[1:0] STBY_CY_TIME [1:0] 39h TABLE 6-37: STBY_AVG BIT DECODE STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 CAP1133 DS00001625B-page 36  2015 Microchip Technology Inc. Bit 3-2 - STBY SAMP_TIME[1:0] - Determines the time to take a single sample when the device is in Standby as shown in Table 6-38. Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during standby operation as shown in Table 6-39. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.22 Standby Sensitivity Register The Standby Sensitivity register controls the sensitivity for sensor inputs that are active in Standby. 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-38: STBY_SAMP_TIME BIT DECODE STBY_SAMP_TIME[1:0] Sampling Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-39: STBY_CY_TIME BIT DECODE STBY_CY_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-40: STANDBY SENSITIVITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 42h R/W Standby Sensitivity - - - - - STBY_SENSE[2:0] 02h TABLE 6-37: STBY_AVG BIT DECODE (CONTINUED) STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10  2015 Microchip Technology Inc. DS00001625B-page 37 CAP1133 Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensor inputs that are active in Standby. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more sensitive to noise however and a noisy environment may flag more false touches than higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). 6.23 Standby Threshold Register The Standby Threshold register stores the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. 6.24 Sensor Input Base Count Registers The Sensor Input Base Count registers store the calibrated “Not Touched” input value from the capacitive touch sensor inputs. These registers are periodically updated by the re-calibration routine. The routine uses an internal adder to add the current count value for each reading to the sum of the previous readings until sample size has been reached. At this point, the upper 16 bits are taken and used as the Sensor Input Base Count. The internal adder is then reset and the re-calibration routine continues. TABLE 6-41: STBY_SENSE BIT DECODE STBY_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-42: STANDBY THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 43h R/W Standby Threshold - 64 32 16 8 4 2 1 40h TABLE 6-43: SENSOR INPUT BASE COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 50h R Sensor Input 1 Base Count 128 64 32 16 8 4 2 1 C8h 51h R Sensor Input 2 Base Count 128 64 32 16 8 4 2 1 C8h 52h R Sensor Input 3 Base Count 128 64 32 16 8 4 2 1 C8h CAP1133 DS00001625B-page 38  2015 Microchip Technology Inc. The data presented is determined by the BASE_SHIFT[3:0] bits (see Section 6.5). 6.25 LED Output Type Register The LED Output Type register controls the type of output for the LED pins. Each pin is controlled by a single bit. Refer to application note 21.4 CAP1133Family LED Configuration Options for more information about implementing LEDs. Bit 2 - LED3_OT - Determines the output type of the LED3 pin. • ‘0’ (default) - The LED3 pin is an open-drain output with an external pull-up resistor. When the appropriate pin is set to the “active” state (logic ‘1’), the pin will be driven low. Conversely, when the pin is set to the “inactive” state (logic ‘0’), the pin will be left in a High Z state and pulled high via an external pull-up resistor. • ‘1’ - The LED3 pin is a push-pull output. When driving a logic ‘1’, the pin is driven high. When driving a logic ‘0’, the pin is driven low. Bit 1 - LED2_OT - Determines the output type of the LED2 pin. Bit 0 - LED1_OT - Determines the output type of the LED1 pin. 6.26 Sensor Input LED Linking Register The Sensor Input LED Linking register controls whether a capacitive touch sensor input is linked to an LED output. If the corresponding bit is set, then the appropriate LED output will change states defined by the LED Behavior controls (see Section 6.31) in response to the capacitive touch sensor input. Bit 2 - CS3_LED3 - Links the LED3 output to a detected touch on the CS3 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. • ‘0’ (default) - The LED 3 output is not associated with the CS3 input. If a touch is detected on the CS3 input, the LED will not automatically be actuated. The LED is enabled and controlled via the LED Output Control register (see Section 6.28) and the LED Behavior registers (see Section 6.31). • ‘1’ - The LED 3 output is associated with the CS3 input. If a touch is detected on the CS3 input, the LED will be actuated and behave as defined in Table 6-52. Bit 1 - CS2_LED2 - Links the LED2 output to a detected touch on the CS2 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. Bit 0 - CS1_LED1 - Links the LED1 output to a detected touch on the CS1 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. 6.27 LED Polarity Register TABLE 6-44: LED OUTPUT TYPE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 71h R/W LED Output Type ----- LED3_ OT LED2_ OT LED1_ OT 00h TABLE 6-45: SENSOR INPUT LED LINKING REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 72h R/W Sensor Input LED Linking - - - - - CS3_ LED3 CS2_ LED2 CS1_ LED1 00h TABLE 6-46: LED POLARITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 73h R/W LED Polarity - - - - - LED3_ POL LED2_ POL LED1_ POL 00h  2015 Microchip Technology Inc. DS00001625B-page 39 CAP1133 The LED Polarity register controls the logical polarity of the LED outputs. When these bits are set or cleared, the corresponding LED Mirror controls are also set or cleared (unless the BLK_POL_MIR bit is set - see Section 6.6, "Configuration Registers"). Table 6-48, "LED Polarity Behavior" shows the interaction between the polarity controls, output controls, and relative brightness. APPLICATION NOTE: The polarity controls determine the final LED pin drive. A touch on a linked capacitive touch sensor input is treated in the same way as the LED Output Control bit being set to a logic ‘1’. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’ then the LED will be on and that the CAP1133 LED pin is sinking the LED current. Conversely, if the LED pin is driven to a logic ‘1’, the LED will be off and there is no current flow. See Figure 5-1, "System Diagram for CAP1133". APPLICATION NOTE: This application note applies when the LED polarity is inverted (LEDx_POL = ‘0’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘0’ state in. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven low (i.e. maximum % of time that the LED is on) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven low (i.e. minimum % of time that the LED is on). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at the minimum duty cycle setting. Breathe operations will ramp the duty cycle from the minimum duty cycle to the maximum duty cycle. APPLICATION NOTE: This application note applies when the LED polarity is non-inverted (LEDx_POL = ‘1’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘1’ state. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven high (i.e. maximum % of time that the LED is off) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven high (i.e. minimum % of time that the LED is off). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at 100 minus the minimum duty cycle setting. Breathe operations will ramp the duty cycle from 100 minus the minimum duty cycle to 100 minus the maximum duty cycle. APPLICATION NOTE: The LED Mirror controls (see Section 6.30, "LED Mirror Control Register") work with the polarity controls with respect to LED brightness but will not have a direct effect on the output pin drive. Bit 2 - LED3_POL - Determines the polarity of the LED3 output. • ‘0’ (default) - The LED3 output is inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘0’. • ‘1’ - The LED3 output is non-inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘1’ or left in the high-z state as determined by its output type Bit 1 - LED2_POL - Determines the polarity of the LED2 output. Bit 0 - LED1_POL - Determines the polarity of the LED1 output. 6.28 LED Output Control Register The LED Output Control Register controls the output state of the LED pins that are not linked to sensor inputs. TABLE 6-47: LED OUTPUT CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 74h R/W LED Output Control ----- LED3_ DR LED2_ DR LED1_ DR 00h Note: If an LED is linked to a sensor input in the Sensor Input LED Linking Register (Section 6.26, "Sensor Input LED Linking Register"), the corresponding bit in the LED Output Control Register is ignored (i.e. a linked LED cannot be host controlled). CAP1133 DS00001625B-page 40  2015 Microchip Technology Inc. The LED Polarity Control Register will determine the non actuated state of the LED pins. The actuated LED behavior is determined by the LED behavior controls (see Section 6.31, "LED Behavior Register"). Table 6-48 shows the interaction between the polarity controls, output controls, and relative brightness. Bit 2 - LED3_DR - Determines whether LED3 output is driven high or low. • ‘0’ (default) - The LED3 output is driven at the minimum duty cycle or not actuated. • ‘1’ - The LED3 output is driven at the maximum duty cycle or is actuated. Bit 1 - LED2_DR - Determines whether LED2 output is driven high or low. Bit 0 - LED1_DR - Determines whether LED1 output is driven high or low. 6.29 Linked LED Transition Control Register The Linked LED Transition Control register controls the LED drive when the LED is linked to a capacitive touch sensor input. These controls work in conjunction with the INV_LINK_TRAN bit (see Section 6.6.2, "Configuration 2 - 44h") to create smooth transitions from host control to linked LEDs. Bit 2 - LED3_LTRAN - Determines the transition effect when LED3 is linked to CS3. • ‘0’ (default) - When the LED output control bit for LED3 is ‘1’, and then LED3 is linked to CS3 and no touch is detected, the LED will change states. • ‘1’ - If the INV_LINK_TRAN bit is ‘1’, when the LED output control bit for CS3 is ‘1’, and then CS3 is linked to LED3 and no touch is detected, the LED will not change states. In addition, the LED state will change when the sensor pad is touched. If the INV_LINK_TRAN bit is ‘0’, when the LED output control bit for CS3 is ‘1’, and then CS3 is linked to LED3 and no touch is detected, the LED will not change states. However, the LED state will not change TABLE 6-48: LED POLARITY BEHAVIOR LED Output Control Register or Touch Polarity Max Duty Min Duty Brightness LED Appearance 0 inverted (‘0’) not used minimum % of time that the LED is on (logic 0) maximum brightness at min duty cycle on at min duty cycle 1 inverted (‘0’) maximum % of time that the LED is on (logic 0) minimum % of time that the LED is on (logic 0) maximum brightness at max duty cycle. Brightness ramps from min duty cycle to max duty cycle according to LED behavior 0 non-inverted (‘1’) not used minimum % of time that the LED is off (logic 1) maximum brightness at 100 minus min duty cycle. on at 100 - min duty cycle 1 non-inverted (‘1’) maximum % of time that the LED is off (logic 1) minimum % of time that the LED is off (logic 1) For Direct behavior, maximum brightness is 100 minus max duty cycle. When breathing, max brightness is 100 minus min duty cycle. Brightness ramps from 100 - min duty cycle to 100 - max duty cycle. according to LED behavior TABLE 6-49: LINKED LED TRANSITION CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 77h R/W Linked LED Transition Control - ---- LED3_ LTRAN LED2_ LTRAN LED1_ LTRAN 00h  2015 Microchip Technology Inc. DS00001625B-page 41 CAP1133 when the sensor pad is touched. APPLICATION NOTE: If the LED behavior is not “Direct” and the INV_LINK_TRAN bit it ‘0’, the LED will not perform as expected when the LED3_LTRAN bit is set to ‘1’. Therefore, if breathe and pulse behaviors are used, set the INV_LINK_TRAN bit to ‘1’. Bit 1 - LED2_LTRAN - Determines the transition effect when LED2 is linked to CS2. Bit 0 - LED1_LTRAN - Determines the transition effect when LED1 is linked to CS1. 6.30 LED Mirror Control Register The LED Mirror Control Registers determine the meaning of duty cycle settings when polarity is non-inverted for each LED channel. When the polarity bit is set to ‘1’ (non-inverted), to obtain correct steps for LED ramping, pulse, and breathe behaviors, the min and max duty cycles need to be relative to 100%, rather than the default, which is relative to 0%. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’, the LED will be on and the CAP1133 LED pin is sinking the LED current. When the polarity bit is set to ‘1’, it is considered non-inverted. For systems using the opposite LED configuration, mirror controls would apply when the polarity bit is ‘0’. These bits are changed automatically if the corresponding LED Polarity bit is changed (unless the BLK_POL_MIR bit is set - see Section 6.6). Bit 2 - LED3_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. • ‘0’ (default) - The duty cycle settings are determined relative to 0% and are determined directly with the settings. • ‘1’ - The duty cycle settings are determined relative to 100%. Bit 1 - LED2_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. Bit 0 - LED1_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. 6.31 LED Behavior Register The LED Behavior register controls the operation of LEDs. Each LED pin is controlled by a 2-bit field and the behavior is determined by whether the LED is linked to a capacitive touch sensor input or not. If the corresponding LED output is linked to a capacitive touch sensor input, the appropriate behavior will be enabled / disabled based on touches and releases. If the LED output is not associated with a capacitive touch sensor input, the appropriate behavior will be enabled / disabled by the LED Output Control register. If the respective LEDx_DR bit is set to a logic ‘1’, this will be associated as a “touch”, and if the LEDx_DR bit is set to a logic ‘0’, this will be associated as a “release”. Table 6-52, "LEDx_CTL Bit Decode" shows the behavior triggers. The defined behavior will activate when the Start Trigger is met and will stop when the Stop Trigger is met. Note the behavior of the Breathe Hold and Pulse Release option. The LED Polarity Control register will determine the non actuated state of the LED outputs (see Section 6.27, "LED Polarity Register"). APPLICATION NOTE: If an LED is not linked to a capacitive touch sensor input and is breathing (via the Breathe or Pulse behaviors), it must be unactuated and then re-actuated before changes to behavior TABLE 6-50: LED MIRROR CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 79h R/W LED Mirror Control ----- LED3_ MIR_ EN LED2_ MIR _ EN LED1_ MIR _ EN 00h TABLE 6-51: LED BEHAVIOR REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 81h R/W LED Behavior 1 - - LED3_CTL[1:0] LED2_CTL[1:0] LED1_CTL[1:0] 00h CAP1133 DS00001625B-page 42  2015 Microchip Technology Inc. are processed. For example, if the LED output is breathing and the Maximum duty cycle is changed, this change will not take effect until the LED output control register is set to ‘0’ and then re-set to ‘1’. APPLICATION NOTE: If an LED is not linked to the capacitive touch sensor input and configured to operate using Pulse 1 Behavior, then the circuitry will only be actuated when the corresponding output control bit is set. It will not check the bit condition until the Pulse 1 behavior is finished. The device will not remember if the bit was cleared and reset while it was actuated. APPLICATION NOTE: If an LED is actuated and not linked and the desired LED behavior is changed, this new behavior will take effect immediately; however, the first instance of the changed behavior may act incorrectly (e.g. if changed from Direct to Pulse 1, the LED output may ‘breathe’ 4 times and then end at minimum duty cycle). LED Behaviors will operate normally once the LED has been un-actuated and then re-actuated. APPLICATION NOTE: If an LED is actuated and it is switched from linked to a capacitive touch sensor input to unlinked (or vice versa), the LED will respond to the new command source immediately if the behavior was Direct or Breathe. For Pulse behaviors, it will complete the behavior already in progress. For example, if a linked LED was actuated by a touch and the control is changed so that it is unlinked, it will check the status of the corresponding LED Output Control bit. If that bit is ‘0’, then the LED will behave as if a release was detected. Likewise, if an unlinked LED was actuated by the LED Output Control register and the control is changed so that it is linked and no touch is detected, then the LED will behave as if a release was detected. Bits 5 - 4 - LED3_CTL[1:0] - Determines the behavior of LED3 as shown in Table 6-52. Bits 3 - 2 - LED2_CTL[1:0] - Determines the behavior of LED2 as shown in Table 6-52. Bits 1 - 0 - LED1_CTL[1:0] - Determines the behavior of LED1 as shown in Table 6-52. TABLE 6-52: LEDX_CTL BIT DECODE LEDx_CTL [1:0] Operation Description Start TRigger Stop Trigger 1 0 0 0 Direct The LED is driven to the programmed state (active or inactive). See Figure 6-7 Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 0 1 Pulse 1 The LED will “Pulse” a programmed number of times. During each “Pulse” the LED will breathe up to the maximum brightness and back down to the minimum brightness so that the total “Pulse” period matches the programmed value. Touch or Release Detected or LED Output Control bit set or cleared (see Section 6.32) n/a 1 0 Pulse 2 The LED will “Pulse” when the start trigger is detected. When the stop trigger is detected, it will “Pulse” a programmable number of times then return to its minimum brightness. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared  2015 Microchip Technology Inc. DS00001625B-page 43 CAP1133 APPLICATION NOTE: The PWM frequency is determined based on the selected LED behavior, the programmed breathe period, and the programmed min and max duty cycles. For the Direct behavior mode, the PWM frequency is calculated based on the programmed Rise and Fall times. If these are set at 0, then the maximum PWM frequency will be used based on the programmed duty cycle settings. 6.32 LED Pulse 1 Period Register The LED Pulse Period 1 register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 01b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms (24 x 32ms = 768ms). The total range is from 32ms to 4.064 seconds as shown in Table 6-54 with the default being 1024ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. Bit 7 - ST_TRIG - Determines the start trigger for the LED Pulse behavior. • ‘0’ (default) - The LED will Pulse when a touch is detected or the drive bit is set. • ‘1’ - The LED will Pulse when a release is detected or the drive bit is cleared. The Pulse 1 operation is shown in Figure 6-1 when the LED output is configured for non-inverted polarity (LEDx_POL = 1) and in Figure 6-2 for inverted polarity (LEDx_POL = 0). 1 1 Breathe The LED will breathe. It will be driven with a duty cycle that ramps up from the programmed minimum duty cycle (default 0%) to the programmed maximum duty cycle duty cycle (default 100%) and then back down. Each ramp takes up 50% of the programmed period. The total period of each “breath” is determined by the LED Breathe Period controls - see Section 6.34. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared TABLE 6-53: LED PULSE 1 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 84h R/W LED Pulse 1 Period ST_ TRIG P1_ PER6 P1_ PER5 P1_ PER4 P1_ PER3 P1_ PER2 P1_ PER1 P1_ PER0 20h TABLE 6-52: LEDX_CTL BIT DECODE (CONTINUED) LEDx_CTL [1:0] Operation Description Start TRigger Stop Trigger 1 0 CAP1133 DS00001625B-page 44  2015 Microchip Technology Inc. . FIGURE 6-1: Pulse 1 Behavior with Non-Inverted Polarity FIGURE 6-2: Pulse 1 Behavior with Inverted Polarity TABLE 6-54: LED PULSE / BREATHE PERIOD EXAMPLE Setting (HEX) Setting (Decimal) Total Breathe / Pulse Period (MS) 00h 0 32 01h 1 32 02h 2 64 03h 3 96 . . . . . . . . . 7Dh 125 4000 7Eh 126 4032 7Fh 127 4064 Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected (100% - Pulse 1 Max Duty Cycle) * Brightness X pulses after touch or after release Pulse 1 Period (P1_PER) (100% - Pulse 1 Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected Pulse 1 Min Duty Cycle * Brightness X pulses after touch or after release Pulse Period (P1_PER) Pulse 1 Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001625B-page 45 CAP1133 6.33 LED Pulse 2 Period Register The LED Pulse 2 Period register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 10b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 640ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. The Pulse 2 Behavior is shown in Figure 6-3 for non-inverted polarity (LEDx_POL = 1) and in Figure 6-4 for inverted polarity (LEDx_POL = 0). TABLE 6-55: LED PULSE 2 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 85h R/W LED Pulse 2 Period - P2_ PER6 P2_ PER5 P2_ PER4 P2_ PER3 P2_ PER2 P2_ PER1 P2_ PER0 14h FIGURE 6-3: Pulse 2 Behavior with Non-Inverted Polarity FIGURE 6-4: Pulse 2 Behavior with Inverted Polarity . . . Normal – untouched operation Normal – untouched operation Touch Detected (100% - Pulse 2 Min Duty Cycle) * Brightness (100% - Pulse 2 Max Duty Cycle) * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness Normal – untouched operation Normal – untouched operation Touch Detected Pulse 2 Max Duty Cycle * Brightness Pulse 2 Min Duty Cycle * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness . . . CAP1133 DS00001625B-page 46  2015 Microchip Technology Inc. 6.34 LED Breathe Period Register The LED Breathe Period register determines the overall period of a breathe operation as determined by the LED_CTL registers (see Table 6-52 - setting 11b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 2976ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. 6.35 LED Configuration Register The LED Configuration register controls general LED behavior as well as the number of pulses that are sent for the PULSE LED output behavior. Bit 6 - RAMP_ALERT - Determines whether the device will assert the ALERT# pin when LEDs actuated by the LED Output Control register bits have finished their respective behaviors. Interrupts will only be generated if the LED activity is generated by writing the LED Output Control registers. Any LED activity associated with touch detection will not cause an interrupt to be generated when the LED behavior has been finished. • ‘0’ (default) - The ALERT# pin will not be asserted when LEDs actuated by the LED Output Control register have finished their programmed behaviors. • ‘1’ - The ALERT# pin will be asserted whenever any LED that is actuated by the LED Output Control register has finished its programmed behavior. Bits 5 - 3 - PULSE2_CNT[2:0] - Determines the number of pulses used for the Pulse 2 behavior as shown in Table 6-58. Bits 2 - 0 - PULSE1_CNT[2:0] - Determines the number of pulses used for the Pulse 1 behavior as shown in Table 6-58. TABLE 6-56: LED BREATHE PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 86h R/W LED Breathe Period - BR_ PER6 BR_ PER5 BR_ PER4 BR_ PER3 BR_ PER2 BR_ PER1 BR_ PER0 5Dh TABLE 6-57: LED CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 88h R/W LED Config - RAMP_ ALERT PULSE2_CNT[2:0] PULSE1_CNT[2:0] 04h TABLE 6-58: PULSEX_CNT DECODE PULSEX_CNT[2:0] Number of Breaths 21 0 0 0 0 1 (default - Pulse 2) 00 1 2 01 0 3 01 1 4 1 0 0 5 (default - Pulse 1) 10 1 6 11 0 7 11 1 8  2015 Microchip Technology Inc. DS00001625B-page 47 CAP1133 6.36 LED Duty Cycle Registers The LED Duty Cycle registers determine the minimum and maximum duty cycle settings used for the LED for each LED behavior. These settings affect the brightness of the LED when it is fully off and fully on. The LED driver duty cycle will ramp up from the minimum duty cycle to the maximum duty cycle and back down again. APPLICATION NOTE: When operating in Direct behavior mode, changes to the Duty Cycle settings will be applied immediately. When operating in Breathe, Pulse 1, or Pulse 2 modes, the LED must be unactuated and then re-actuated before changes to behavior are processed. Bits 7 - 4 - X_MAX_DUTY[3:0] - Determines the maximum PWM duty cycle for the LED drivers as shown in Table 6-60. Bits 3 - 0 - X_MIN_DUTY[3:0] - Determines the minimum PWM duty cycle for the LED drivers as shown in Table 6-60. 6.37 LED Direct Ramp Rates Register TABLE 6-59: LED DUTY CYCLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 90h R/W LED Pulse 1 Duty Cycle P1_MAX_DUTY[3:0] P1_MIN_DUTY[3:0] F0h 91h R/W LED Pulse 2 Duty Cycle P2_MAX_DUTY[3:0] P2_MIN_DUTY[3:0] F0h 92h R/W LED Breathe Duty Cycle BR_MAX_DUTY[3:0] BR_MIN_DUTY[3:0] F0h 93h R/W Direct Duty Cycle DR_MAX_DUTY[3:0] DR_MIN_DUTY[3:0] F0h TABLE 6-60: LED DUTY CYCLE DECODE x_MAX/MIN_Duty [3:0] Maximum Duty Cycle Minimum Duty Cycle 3 21 0 0 0 0 0 7% 0% 0 0 0 1 9% 7% 0 0 1 0 11% 9% 0 0 1 1 14% 11% 0 1 0 0 17% 14% 0 1 0 1 20% 17% 0 1 1 0 23% 20% 0 1 1 1 26% 23% 1 0 0 0 30% 26% 1 0 0 1 35% 30% 1 0 1 0 40% 35% 1 0 1 1 46% 40% 1 1 0 0 53% 46% 1 1 0 1 63% 53% 1 1 1 0 77% 63% 1 1 1 1 100% 77% TABLE 6-61: LED DIRECT RAMP RATES REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 94h R/W LED Direct Ramp Rates - - RISE_RATE[2:0] FALL_RATE[2:0] 00h CAP1133 DS00001625B-page 48  2015 Microchip Technology Inc. The LED Direct Ramp Rates register control the rising and falling edge time of an LED that is configured to operate in Direct behavior mode. The rising edge time corresponds to the amount of time the LED takes to transition from its minimum duty cycle to its maximum duty cycle. Conversely, the falling edge time corresponds to the amount of time that the LED takes to transition from its maximum duty cycle to its minimum duty cycle. Bits 5 - 3 - RISE_RATE[2:0] - Determines the rising edge time of an LED when it transitions from its minimum drive state to its maximum drive state as shown in Table 6-62. Bits 2 - 0 - FALL_RATE[2:0] - Determines the falling edge time of an LED when it transitions from its maximum drive state to its minimum drive state as shown in Table 6-62. 6.38 LED Off Delay Register The LED Off Delay register determines the amount of time that an LED remains at its maximum duty cycle (or minimum as determined by the polarity controls) before it starts to ramp down. If the LED is operating in Breathe mode, this delay is applied at the top of each “breath”. If the LED is operating in the Direct mode, this delay is applied when the LED is unactuated. Bits 6 - 4 - BR_OFF_DLY[2:0] - Determines the Breathe behavior mode off delay, which is the amount of time an LED in Breathe behavior mode remains inactive after it finishes a breathe pulse (ramp on and ramp off), as shown in Figure 6- 5 (non-inverted polarity LEDx_POL = 1) and Figure 6-6 (inverted polarity LEDx_POL = 0). Available settings are shown in Table 6-64. TABLE 6-62: RISE / FALL RATE DECODE RISE_RATE/ FALL_RATE/ Bit Decode Rise / Fall Time (TRISE / TFALL) 21 0 00 0 0 0 0 1 250ms 0 1 0 500ms 0 1 1 750ms 1 0 0 1s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2s TABLE 6-63: LED OFF DELAY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 95h R/W LED Off Delay Register - BR_OFF_DLY[2:0] DIR_OFF_DLY[3:0] 00h  2015 Microchip Technology Inc. DS00001625B-page 49 CAP1133 FIGURE 6-5: Breathe Behavior with Non-Inverted Polarity FIGURE 6-6: Breathe Behavior with Inverted Polarity TABLE 6-64: BREATHE OFF DELAY SETTINGS BR_OFF_DLY [2:0] OFF Delay 2 10 0 0 0 0 (default) 0 0 1 0.25s 0 1 0 0.5s 0 1 1 0.75s LED Actuated 100% - Breathe Max Min Cycle * Brightness 100% - Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) LED Actuated Breathe Max Duty Cycle * Brightness Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) CAP1133 DS00001625B-page 50  2015 Microchip Technology Inc. Bits 3 - 0 - DIR_OFF_DLY[3:0] - Determines the turn-off delay, as shown in Table 6-65, for all LEDs that are configured to operate in Direct behavior mode. The Direct behavior operation is determined by the combination of programmed Rise Time, Fall Time, Min and Max Duty cycles, Off Delay, and polarity. Figure 6-7 shows the behavior for non-inverted polarity (LEDx_POL = 1) while Figure 6- 8 shows the behavior for inverted polarity (LEDx_POL = 0). 1 0 0 1.0s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2.0s FIGURE 6-7: Direct Behavior for Non-Inverted Polarity FIGURE 6-8: Direct Behavior for Inverted Polarity TABLE 6-65: OFF DELAY DECODE OFF Delay[3:0] Bit Decode OFF Delay (tOFF_DLY) 32 1 0 00 0 0 0 0 0 0 1 250ms 0 0 1 0 500ms 0 0 1 1 750ms TABLE 6-64: BREATHE OFF DELAY SETTINGS (CONTINUED) BR_OFF_DLY [2:0] OFF Delay 2 10 Normal – untouched operation RISE_RATE Setting (tRISE) (100% - Max Duty Cycle) * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation (100% - Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation RISE_RATE Setting (tRISE) Min Duty Cycle * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001625B-page 51 CAP1133 6.39 Sensor Input Calibration Registers The Sensor Input Calibration registers hold the 10-bit value that represents the last calibration value. 6.40 Product ID Register The Product ID register stores a unique 8-bit value that identifies the device. 6.41 Manufacturer ID Register The Vendor ID register stores an 8-bit value that represents Microchip. 0 1 0 0 1s 0 1 0 1 1.25s 0 1 1 0 1.5s 0 1 1 1 2s 1 0 0 0 2.5s 1 0 0 1 3.0s 1 0 1 0 3.5s 1 0 1 1 4.0s 1 1 0 0 4.5s All others 5.0s TABLE 6-66: SENSOR INPUT CALIBRATION REGISTERS ADDR Register R/W B7 B6 B5 B4 B3 B2 B1 B0 Default B1h Sensor Input 1 Calibration R CAL1_9 CAL1_8 CAL1_7 CAL1_6 CAL1_5 CAL1_4 CAL1_3 CAL1_2 00h B2h Sensor Input 2 Calibration R CAL2_9 CAL2_8 CAL2_7 CAL2_6 CAL2_5 CAL2_4 CAL2_3 CAL2_2 00h B3h Sensor Input 3 Calibration R CAL3_9 CAL3_8 CAL3_7 CAL3_6 CAL3_5 CAL3_4 CAL3_3 CAL3_2 00h B9h Sensor Input Calibration LSB 1 R - - CAL3_1 CAL3_0 CAL2_1 CAL2_0 CAL1_1 CAL1_0 00h TABLE 6-67: PRODUCT ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FDh R Product ID 0 1 0 1 0 1 0 0 54h TABLE 6-68: VENDOR ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh TABLE 6-65: OFF DELAY DECODE (CONTINUED) OFF Delay[3:0] Bit Decode OFF Delay (tOFF_DLY) 32 1 0 CAP1133 DS00001625B-page 52  2015 Microchip Technology Inc. 6.42 Revision Register The Revision register stores an 8-bit value that represents the part revision. TABLE 6-69: REVISION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FFh R Revision 1 0 0 0 0 0 1 1 83h  2015 Microchip Technology Inc. DS00001625B-page 53 CAP1133 7.0 PACKAGE INFORMATION 7.1 CAP1133 Package Drawings FIGURE 7-1: 10-Pin DFN 3mm x 3mm Package Drawings (1 of 2) Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging CAP1133 DS00001625B-page 54  2015 Microchip Technology Inc. FIGURE 7-2: 10-Pin DFN 3mm x 3mm Package Drawings (2 of 2) Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging  2015 Microchip Technology Inc. DS00001625B-page 55 CAP1133 7.2 Package Marking FIGURE 7-3: CAP1133 Package Marking 1 A W NNNA e4 TOP BOTTOM Bottom marking not allowed PB-FREE/GREEN SYMBOL PIN 1 (Ni/Pd PP-LF) Line 1 – Device Code, Week 2x 0.6 Line 2 – Alphanumeric Traceability Code W Lines 1-2: Line 3: Center Horizontal Alignment As Shown CAP1133 DS00001625B-page 56  2015 Microchip Technology Inc. APPENDIX A: DEVICE DELTA A.1 Delta from CAP1033 to CAP1133 1. Updated circuitry to improve power supply rejection. 2. Updated LED driver duty cycle decode values to have more distribution at lower values - closer to a logarithmic curve. See Table 6-60, "LED Duty Cycle Decode". 3. Updated bug that breathe periods were not correct above 2.6s. This includes rise / fall time decodes above 1.5s. 4. Added 1 bit to the LED Off Delay register (see Section 6.38, "LED Off Delay Register") to extend times from 2s to 5s in 0.5s intervals. 5. Breathe behavior modified. A breathe off delay control was added to the LED Off Delay Register (see Section 6.38, "LED Off Delay Register") so the LEDs can be configured to remain inactive between breathes. 6. Added controls for the LED transition effects when linking LEDs to capacitive sensor inputs. See Section 6.29, "Linked LED Transition Control Register". 7. Added controls to “mirror” the LED duty cycle outputs so that when polarity changes, the LED brightness levels look right. These bits are automatically set when polarity is set. Added control to break this auto-set behavior. See Section 6.30, "LED Mirror Control Register". 8. Added Multiple Touch Pattern detection circuitry. See Section 6.15, "Multiple Touch Pattern Configuration Register". 9. Added General Status register to flag Multiple touches, Multiple Touch Pattern issues and general touch detections. See Section 6.2, "Status Registers". 10. Added bits 6 and 5 to the Recalibration Configuration register (2Fh - see Section 6.17, "Recalibration Configuration Register"). These bits control whether the accumulation of intermediate data and the consecutive negative delta counts counter are cleared when the noise status bit is set. 11. Added Configuration 2 register for LED linking controls, noise detection controls, and control to interrupt on press but not on release. Added control to change alert pin polarity. See Section 6.6, "Configuration Registers". 12. Updated Deep Sleep behavior so that device does not clear DSLEEP bit on received communications but will wake to communicate. 13. Changed PWM frequency for LED drivers. The PWM frequency was derived from the programmed breathe period and duty cycle settings and it ranged from ~4Hz to ~8000 Hz. The PWM frequency has been updated to be a fixed value of ~2000Hz. 14. Register delta: Table A.1 Register Delta From CAP1033 to CAP1133 Address Register Delta Delta Default 00h Page 21 Changed - Main Status / Control added bits 7-6 to control gain 00h 02h Page 22 New - General Status new register to store MTP, MULT, LED, and general TOUCH bits 00h 44h Page 25 New - Configuration 2 new register to control alert polarity, LED touch linking behavior, LED output behavior, and noise detection, and interrupt on release 40h 24h Page 28 Changed - Averaging Control updated register bits - moved SAMP_AVG[2:0] bits and added SAMP_- TIME bit 1. Default changed 39h 2Bh Page 31 New - Multiple Touch Pattern Configuration new register for Multiple Touch Pattern configuration - enable and threshold settings 80h 2Dh Page 32 New - Multiple Touch Pattern Register new register for Multiple Touch Pattern detection circuitry - pattern or number of sensor inputs 07h  2015 Microchip Technology Inc. DS00001625B-page 57 CAP1133 2Fh Page 33 Changed - Recalibration Configuration updated register - updated CAL_CFG bit decode to add a 128 averages setting and removed highest time setting. Default changed. Added bit 6 NO_CLR_INTD and bit 5 NO_CLR_NEG. 8Ah 38h Page 34 Changed - Sensor Input Noise Threshold updated register bits - removed bits 7 - 3 and consolidated all controls into bits 1 - 0. These bits will set the noise threshold for all channels. Default changed 01h 39h Removed - Noise Threshold Register 2 removed register n/a 41h Page 35 Changed - Standby Configuration updated register bits - moved STBY_AVG[2:0] bits and added STBY_- TIME bit 1. Default changed 39h 77h Page 40 New - Linked LED Transition Control new register to control transition effect when LED linked to sensor inputs 00h 79h Page 41 New - LED Mirror Control new register to control LED output mirroring for brightness control when polarity changed 00h 90h Page 47 Changed - LED Pulse 1 Duty Cycle changed bit decode to be more logarithmic F0h 91h Page 47 Changed - LED Pulse 2 Duty Cycle changed bit decode to be more logarithmic F0h 92h Page 47 Changed - LED Breathe Duty Cycle changed bit decode to be more logarithmic F0h 93h Page 47 Changed - LED Direct Duty Cycle changed bit decode to be more logarithmic F0h 95h Added controls - LED Off Delay Added bits 6-4 BR_OFF_DLY[2:0] Added bit 3 DIR_OFF_DLY[3] 00h FDh Page 51 Changed - Product ID Changed bit decode for CAP1133 54h Table A.1 Register Delta From CAP1033 to CAP1133 (continued) Address Register Delta Delta Default CAP1133 DS00001625B-page 58  2015 Microchip Technology Inc. APPENDIX B: DATA SHEET REVISION HISTORY Revision Section/Figure/Entry Correction DS00001625B (02-09-15) Features, Table 2-2, Table 2- 2, "Pin Types", Section 5.0, "General Description" References to BC-Link Interface, BC_DATA, BC_- CLK, BC-IRQ#, BC-Link bus have been removed Application Note under Table 2-6 [BC-Link] hidden in data sheet Table 3-2, "Electrical Specifications" BC-Link Timing Section hidden in data sheet Table 4-1 Protocol Used for 68K Pull Down Resistor changed from “BC-Link Communications” to “Reserved” Section 4.2.2, "SMBus Address and RD / WR Bit" Replaced “client address” with “slave address” in this section. Section 4.2.4, SMBus ACK and NACK Bits, Section 4.2.5, SMBus Stop Bit,Section 4.2.7, SMBus and I2C Compatibility Replaced “client” with “slave” in these sections. Table 4-3, "Read Byte Protocol" Heading changed from “Client Address” to “Slave Address” Table 6-1 Register Name for Register Address 77h changed from “LED Linked Transition Control” to “Linked LED Transition Control” Section 6.30 changed CS3 to LED3 Section 7.7 Package Marking Updated package drawing Appendix A: Device Delta changed 2Dh to 2Fh in item #12 Product Identification System Removed BC-Link references REV A REV A replaces previous SMSC version Rev. 1.32 (01-05-12) Rev. 1.32 (01-05-12) Table 3-2, "Electrical Specifications" Added conditions for tHD:DAT. Section 4.2.7, "SMBus and I2C Compatibility" Renamed from “SMBus and I2C Compliance.” First paragraph, added last sentence: “For information on using the CAP1188 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I 2C Systems.” Added: CAP1188 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. Section 6.4, "Sensor Input Delta Count Registers" Changed negative value cap from FFh to 80h. Rev. 1.31 (08-18-11) Section 4.3.3, "SMBus Send Byte" Added an application note: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Section 4.3.4, "SMBus Receive Byte" Added an application note: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Section 6.2, "Status Registers" Removed RESET as bit 3 in register 02h. Rev. 1.3 (05-18-11) Section 6.42, "Revision Register" Updated revision ID from 82h to 83h. Section 6.2, "Status Registers" Added RESET as bit 3 in register 02h.  2015 Microchip Technology Inc. DS00001625B-page 59 CAP1133 Rev. 1.2 (02-10-11) Section A.8, "Delta from Rev B (Mask B0) to Rev C (Mask B1)" Added. Table 3-2, "Electrical Specifications" PSR improvements made in functional revision B. Changed PSR spec from ±100 typ and ±200 max counts / V to ±3 and ±10 counts / V. Conditions updated. Section 5.3.2, "Recalibrating Sensor Inputs" Added more detail with subheadings for each type of recalibration. Section 6.6, "Configuration Registers" Added bit 5 BLK_PWR_CTRL to the Configuration 2 Register 44h. The TIMEOUT bit is set to ‘1’ by default for functional revision B and is set to ‘0’ by default for functional revision C. Section 6.42, "Revision Register" Updated revision ID in register FFh from 81h to 82h. Rev. 1.1 (11-17-10) Document Updated for functional revision B. See Section A.7, "Delta from Rev A (Mask A0) to Rev B (Mask B0)". Cover Added to General Description: “includes circuitry and support for enhanced sensor proximity detection.” Added the following Features: Calibrates for Parasitic Capacitance Analog Filtering for System Noise Sources Press and Hold feature for Volume-like Applications Table 3-2, "Electrical Specifications" Conditions for Power Supply Rejection modified adding the following: Sampling time = 2.56ms Averaging = 1 Negative Delta Counts = Disabled All other parameters default Section 6.11, "Calibration Activate Register" Updated register description to indicate which re-calibration routine is used. Section 6.14, "Multiple Touch Configuration Register" Updated register description to indicate what will happen. Table 6-34, "CSx_BN_TH Bit Decode" Table heading changed from “Threshold Divide Setting” to “Percent Threshold Setting”. Rev. 1.0 (06-14-10) Initial release Revision Section/Figure/Entry Correction CAP1133 DS00001625B-page 60  2015 Microchip Technology Inc. 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DS00001625B-page 61 CAP1133 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] - [X] - XXX - [X](1) l l l l l Device Temperature Addressing Package Tape and Reel Range Option Option Example: Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Device: CAP1133 Temperature Range: Blank = 0°C to +85°C (Extended Commercial) Package: AIA = DFN Tape and Reel Option: TR = Tape and Reel(1) CAP1133-1-AIA-TR 10-pin DFN 3mm x 3mm (RoHS compliant) Three capacitive touch sensor inputs, Three LED drivers, SMBus interface Reel size is 4,000 pieces CAP1133 DS00001625B-page 62  2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. 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All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978632770356 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2015 Microchip Technology Inc. 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DS00001624B-page 1 General Description The CAP1106, which incorporates RightTouch® technology, is a multiple channel Capacitive Touch sensor. The CAP1106 contains six (6) individual capacitive touch sensor inputs. The device offers programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1106 includes Multiple Pattern Touch recognition that allows the user to select a specific set of buttons to be touched simultaneously. If this pattern is detected, then a status bit is set and an interrupt generated. Additionally, the CAP1106 includes circuitry and support for enhanced sensor proximity detection. The CAP1106 offers multiple power states operating at low quiescent currents. In the Standby state of operation, one or more capacitive touch sensor inputs are active. Deep Sleep is the lowest power state available, drawing 5uA (typical) of current. In this state, no sensor inputs are active. Communications will wake the device. Applications • Desktop and Notebook PCs • LCD Monitors • Consumer Electronics • Appliances Features • Six (6) Capacitive Touch Sensor Inputs - CAP1106 - Programmable sensitivity - Automatic recalibration - Individual thresholds for each button • Proximity Detection • Multiple Button Pattern Detection • Calibrates for Parasitic Capacitance • Analog Filtering for System Noise Sources • Press and Hold feature for Volume-like Applications • Multiple Communication Interfaces - SMBus / I2C compliant interface • Low Power Operation - 5uA quiescent current in Deep Sleep - 50uA quiescent current in Standby (1 sensor input monitored) - Samples one or more channels in Standby • Available in 10-pin 3mm x 3mm RoHS compliant DFN package CAP1106 6 Channel Capacitive Touch Sensor CAP1106 DS00001624B-page 2  2015 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). 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DS00001624B-page 3 CAP1106 Table of Contents 1.0 Block Diagram ................................................................................................................................................................................. 4 2.0 Pin Description ................................................................................................................................................................................ 5 3.0 Electrical Specifications .................................................................................................................................................................. 9 4.0 Communications ........................................................................................................................................................................... 12 5.0 General Description ...................................................................................................................................................................... 23 6.0 Register Description ...................................................................................................................................................................... 29 7.0 Package Information ..................................................................................................................................................................... 67 Appendix A: Device Delta ................................................................................................................................................................... 72 Appendix B: Data Sheet Revision History ........................................................................................................................................... 74 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77 CAP1106 DS00001624B-page 4  2015 Microchip Technology Inc. 1.0 BLOCK DIAGRAM SMBus / BC-Link Protocol VDD GND Capacitive Touch Sensing Algorithm CS1 CS2 CS3 CS4 CS5 SMCLK1 / BC_CLK2 SMDATA1 / BC_DATA2 ALERT#1 / BC_IRQ#2 1 = CAP1106-1 2 = CAP1106-2 CS6  2015 Microchip Technology Inc. DS00001624B-page 5 CAP1106 2.0 PIN DESCRIPTION FIGURE 2-1: CAP1106 Pin Diagram (10-Pin DFN) TABLE 2-1: PIN DESCRIPTION FOR CAP1106 Pin Number Pin Name Pin Function Pin Type Unused Connection 1 CS1 Capacitive Touch Sensor Input 1 AIO Connect to Ground 2 ALERT# ALERT# - Active low alert / interrupt output for SMBus alert OD (5V) Connect to Ground ALERT# - Active high alert / interrupt output for SMBus alert DO leave open 3 SMDATA SMDATA - Bi-directional, open-drain SMBus data - requires pull-up resistor DIOD (5V) n/a 4 SMCLK SMCLK - SMBus clock input - requires pull-up resistor DI (5V) n/a 5 VDD Positive Power supply Power n/a 6 CS6 Capacitive Touch Sensor Input 6 AIO Connect to Ground 7 CS5 Capacitive Touch Sensor Input 5 AIO Connect to Ground 8 CS4 Capacitive Touch Sensor Input 4 AIO Connect to Ground 9 CS3 Capacitive Touch Sensor Input 3 AIO Connect to Ground GND CS3 1 CS2 2 3 4 5 CS4 CS1 ALERT# / BC_IRQ# SMDATA / BC_DATA VDD SMCLK / BC_CLK CS5 CS6 CAP1106 3mm x 3mm DFN 10 9 8 7 6 CAP1106 DS00001624B-page 6  2015 Microchip Technology Inc. APPLICATION NOTE: When the ALERT# pin is configured as an active low output, it will be open drain. When it is configured as an active high output, it will be push-pull. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the CAP1106 is unpowered. The pin types are described in Table 2-2. All pins labeled with (5V) are 5V tolerant. 10 CS2 Capacitive Touch Sensor Input 2 AIO Connect to Ground Bottom Pad GND Ground Power n/a TABLE 2-2: PIN TYPES Pin Type Description Power This pin is used to supply power or ground to the device. DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant. AIO Analog Input / Output -This pin is used as an I/O for analog signals. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. DO Push-pull Digital Output - This pin is used as a digital output and can sink and source current. DIO Push-pull Digital Input / Output - This pin is used as an I/O for digital signals. TABLE 2-1: PIN DESCRIPTION FOR CAP1106 (CONTINUED) Pin Number Pin Name Pin Function Pin Type Unused Connection  2015 Microchip Technology Inc. DS00001624B-page 7 CAP1106 3.0 ELECTRICAL SPECIFICATIONS Note 3-1 Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3-2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V5VT_PIN and VDD must never exceed 3.6V. Note 3-3 The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 2x2 matrix of 0.3mm (12mil) vias at 1.0mm pitch connected to the ground plane with a 1.6 x 2.3mm thermal landing. TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Voltage on 5V tolerant pins (V5VT_PIN) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_PIN - VDD|) Note 3-2 0 to 3.6 V Voltage on VDD pin -0.3 to 4 V Voltage on any other pin to GND -0.3 to VDD + 0.3 V Package Power Dissipation up to TA = 85°C for 10 pin DFN (see Note 3-3) 0.7 W Junction to Ambient (θJA) 77.7 °C/W Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 8000 V CAP1106 DS00001624B-page 8  2015 Microchip Technology Inc. TABLE 3-2: ELECTRICAL SPECIFICATIONS VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions DC Power Supply Voltage VDD 3.0 3.3 3.6 V Supply Current ISTBY 120 170 uA Standby state active 1 sensor input monitored Default conditions (8 avg, 70ms cycle time) ISTBY 50 uA Standby state active 1 sensor input monitored 1 avg, 140ms cycle time, IDSLEEP 5 15 uA Deep Sleep state active No communications TA < 40°C 3.135 < VDD < 3.465V IDD 500 600 uA Capacitive Sensing Active Capacitive Touch Sensor Inputs Maximum Base Capacitance CBASE 50 pF Pad untouched Minimum Detectable Capacitive Shift ΔCTOUCH 20 fF Pad touched - default conditions (1 avg, 35ms cycle time, 1x sensitivity) Recommended Cap Shift ΔCTOUCH 0.1 2 pF Pad touched - Not tested Power Supply Rejection PSR ±3 ±10 counts / V Untouched Current Counts Base Capacitance 5pF - 50pF Maximum sensitivity Negative Delta Counts disabled All other parameters default Timing Time to communications ready tCOMM_DLY 15 ms Time to first conversion ready tCONV_DLY 170 200 ms I/O Pins Output Low Voltage VOL 0.4 V ISINK_IO = 8mA Output High Voltage VOH VDD - 0.4 V ISOURCE_IO = 8mA Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered SMBus Timing Input Capacitance CIN 5 pF Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 us Start Setup Time tSU:STA 0.6 us  2015 Microchip Technology Inc. DS00001624B-page 9 CAP1106 Note 3-4 The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage. Note 3-5 The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage. Start Hold Time tHD:STA 0.6 us Stop Setup Time tSU:STO 0.6 us Data Hold Time tHD:DAT 0 us When transmitting to the master Data Hold Time tHD:DAT 0.3 us When receiving from the master Data Setup Time tSU:DAT 0.6 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line TABLE 3-2: ELECTRICAL SPECIFICATIONS (CONTINUED) VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions CAP1106 DS00001624B-page 10  2015 Microchip Technology Inc. 4.0 COMMUNICATIONS 4.1 Communications The CAP1106 communicates using the SMBus or I2C protocol. If the proprietary BC-Link protocol is required for your application, please contact your Microchip representative for ordering instructions. Regardless of the communications mechanism, the device functionality remains unchanged. 4.1.1 SMBUS (I2C) COMMUNICATIONS The supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block. In addition, the device supports I2C formatting for block read and block write protocols. See Section 4.2 and Section 4.3 for more information on the SMBus bus and protocols respectively. APPLICATION NOTE: Upon power up, the CAP1106 will not respond to any communications for up to 15ms. After this time, full functionality is available. 4.2 System Management Bus The CAP1106 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1106 will not stretch the clock signal. 4.2.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.2.2 SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the slave device. The CAP1106 responds to SMBus address 0101_000(r/w). 4.2.3 SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.2.4 SMBUS ACK AND NACK BITS The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. FIGURE 4-1: SMBus Timing Diagram SMDATA SMCLK TLOW TRISE THIGH TFALL TBUF THD:STA P S S - Start Condition P - Stop Condition THD:DAT TSU:DAT TSU:STA THD:STA P TSU:STO S  2015 Microchip Technology Inc. DS00001624B-page 11 CAP1106 The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives except the last data byte. 4.2.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1106 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. 4.2.6 SMBUS TIMEOUT The CAP1106 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the SMCLK pin is held low, the device will timeout and reset the SMBus interface. The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register (see Section 6.6, "Configuration Registers"). 4.2.7 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the CAP1106 in an I2C system, refer to AN 14.0 Dedicated Slave Devices in I2C Systems. 1. CAP1106 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2. Minimum frequency for SMBus communications is 10kHz. 3. The SMBus slave protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the CAP1106 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4. The SMBus slave protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200µs (idle condition). This function is disabled by default in the CAP1106 and can be enabled by writing to the TIMEOUT bit. I2C does not have an idle condition. 5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). 6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. The CAP1106 supports I2C formatting only. 4.3 SMBus Protocols The CAP1106 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid protocols as shown below. All of the below protocols use the convention in Table 4-1. 4.3.1 SMBUS WRITE BYTE The Write Byte is used to write one byte of data to a specific register as shown in Table 4-2. 4.3.2 SMBUS READ BYTE The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4-3. TABLE 4-1: PROTOCOL FORMAT Data Sent to Device Data Sent to the HOst Data sent Data sent TABLE 4-2: WRITE BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK Stop 1 ->0 0101_000 0 0 XXh 0 XXh 0 0 -> 1 CAP1106 DS00001624B-page 12  2015 Microchip Technology Inc. 4.3.3 SMBUS SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4-4. APPLICATION NOTE: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.3.4 SMBUS RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4-5. APPLICATION NOTE: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.4 I2C Protocols The CAP1106 supports I2C Block Write and Block Read. The protocols listed below use the convention in Table 4-1. 4.4.1 BLOCK WRITE The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 4-6. APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.4.2 BLOCK READ The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 4-7. APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. TABLE 4-3: READ BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data NACK Stop 1->0 0101_000 0 0 XXh 0 1 ->0 0101_000 1 0 XXh 1 0 -> 1 TABLE 4-4: SEND BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Stop 1 -> 0 0101_000 0 0 XXh 0 0 -> 1 TABLE 4-5: RECEIVE BYTE PROTOCOL Start Slave Address RD ACK Register Data NACK Stop 1 -> 0 0101_000 1 0 XXh 1 0 -> 1 TABLE 4-6: BLOCK WRITE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK 1 ->0 0101_000 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK . . . Register Data ACK Stop XXh 0 XXh 0 . . . XXh 0 0 -> 1  2015 Microchip Technology Inc. DS00001624B-page 13 CAP1106 4.5 BC-Link Interface The BC-Link is a proprietary bus developed to allow communication between a host controller device to a companion device. This device uses this serial bus to read and write registers and for interrupt processing. The interface uses a data port concept, where the base interface has an address register, data register and a control register, defined in the 8051’s SFR space. Refer to documentation for the BC-Link compatible host controller for details on how to access the CAP1106-2 via the BC-Link Interface. TABLE 4-7: BLOCK READ PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data 1->0 0101_000 0 0 XXh 0 1 ->0 0101_000 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK . . . Register Data NACK Stop 0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1 CAP1106 DS00001624B-page 14  2015 Microchip Technology Inc. 5.0 GENERAL DESCRIPTION The CAP1106 is a multiple channel Capacitive Touch sensor. The CAP1106 contains six (6) individual capacitive touch sensor inputs. The device offers programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1106 offers multiple power states. It operates at the lowest quiescent current during its Deep Sleep state. In the low power Standby state, it can monitor one or more channels and respond to communications normally. The device communicates with a host controller using or via SMBus / I2C. The host controller may poll the device for updated information at any time or it may configure the device to flag an interrupt whenever a touch is detected on any sensor pad. A typical system diagram for the CAP1106 is shown in Figure 5-1. FIGURE 5-1: System Diagram for CAP1106 CAP1106 CS6 SMDATA1 / BC_DATA2 SMCLK1 / BC_CLK2 VDD Embedded Controller ALERT#1 / BC_IRQ#2 CS4 CS2 CS5 CS3 CS1 Touch Button Touch Button Touch Button Touch Button Touch Button Touch Button 1 = CAP1106-1 2 = CAP1106-2  2015 Microchip Technology Inc. DS00001624B-page 15 CAP1106 5.1 Power States The CAP1106 has three operating states depending on the status of the STBY and DSLEEP bits. When the device transitions between power states, previously detected touches (for inactive channels) are cleared and the status bits reset. 1. Fully Active - The device is fully active. It is monitoring all active capacitive sensor inputs. 2. Standby - The device is in a lower power state. It will measure a programmable number of channels using the Standby Configuration controls (see Section 6.20 through Section 6.22). Interrupts will still be generated based on the active channels. The device will still respond to communications normally and can be returned to the Fully Active state of operation by clearing the STBY bit. 3. Deep Sleep - The device is in its lowest power state. It is not monitoring any capacitive sensor inputs. While in Deep Sleep, the device can be awakened by SMBus or SPI communications targeting the device. This will not cause the DSLEEP to be cleared so the device will return to Deep Sleep once all communications have stopped. 5.2 Capacitive Touch Sensing The CAP1106 contains six (6) independent capacitive touch sensor inputs. Each sensor input has dynamic range to detect a change of capacitance due to a touch. Additionally, each sensor input can be configured to be automatically and routinely re-calibrated. 5.2.1 SENSING CYCLE Each capacitive touch sensor input has controls to be activated and included in the sensing cycle. When the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it finishes. The cycle polls through each active sensor input starting with CS1 and extending through CS6. As each capacitive touch sensor input is polled, its measurement is compared against a baseline “Not Touched” measurement. If the delta measurement is large enough, a touch is detected and an interrupt is generated. The sensing cycle time is programmable (see Section 6.10, "Averaging and Sampling Configuration Register"). 5.2.2 RECALIBRATING SENSOR INPUTS There are various options for recalibrating the capacitive touch sensor inputs. Recalibration re-sets the Base Count Registers (Section 6.24, "Sensor Input Base Count Registers") which contain the “not touched” values used for touch detection comparisons. APPLICATION NOTE: The device will recalibrate all sensor inputs that were disabled when it transitions from Standby. Likewise, the device will recalibrate all sensor inputs when waking out of Deep Sleep. 5.2.2.1 Manual Recalibration The Calibration Activate Registers (Section 6.11, "Calibration Activate Register") force recalibration of selected sensor inputs. When a bit is set, the corresponding capacitive touch sensor input will be recalibrated (both analog and digital). The bit is automatically cleared once the recalibration routine has finished. 5.2.2.2 Automatic Recalibration Each sensor input is regularly recalibrated at a programmable rate (see Section 6.17, "Recalibration Configuration Register"). By default, the recalibration routine stores the average 64 previous measurements and periodically updates the base “not touched” setting for the capacitive touch sensor input. Note: During this recalibration routine, the sensor inputs will not detect a press for up to 200ms and the Sensor Base Count Register values will be invalid. In addition, any press on the corresponding sensor pads will invalidate the recalibration. Note: Automatic recalibration only works when the delta count is below the active sensor input threshold. It is disabled when a touch is detected. CAP1106 DS00001624B-page 16  2015 Microchip Technology Inc. 5.2.2.3 Negative Delta Count Recalibration It is possible that the device loses sensitivity to a touch. This may happen as a result of a noisy environment, an accidental recalibration during a touch, or other environmental changes. When this occurs, the base untouched sensor input may generate negative delta count values. The NEG_DELTA_CNT bits (see Section 6.17, "Recalibration Configuration Register") can be set to force a recalibration after a specified number of consecutive negative delta readings. 5.2.2.4 Delayed Recalibration It is possible that a “stuck button” occurs when something is placed on a button which causes a touch to be detected for a long period. By setting the MAX_DUR_EN bit (see Section 6.6, "Configuration Registers"), a recalibration can be forced when a touch is held on a button for longer than the duration specified in the MAX_DUR bits (see Section 6.8, "Sensor Input Configuration Register"). 5.2.3 PROXIMITY DETECTION Each sensor input can be configured to detect changes in capacitance due to proximity of a touch. This circuitry detects the change of capacitance that is generated as an object approaches, but does not physically touch, the enabled sensor pad(s). When a sensor input is selected to perform proximity detection, it will be sampled from 1x to 128x per sampling cycle. The larger the number of samples that are taken, the greater the range of proximity detection is available at the cost of an increased overall sampling time. 5.2.4 MULTIPLE TOUCH PATTERN DETECTION The multiple touch pattern (MTP) detection circuitry can be used to detect lid closure or other similar events. An event can be flagged based on either a minimum number of sensor inputs or on specific sensor inputs simultaneously exceeding an MTP threshold or having their Noise Flag Status Register bits set. An interrupt can also be generated. During an MTP event, all touches are blocked (see Section 6.15, "Multiple Touch Pattern Configuration Register"). 5.2.5 LOW FREQUENCY NOISE DETECTION Each sensor input has an EMI noise detector that will sense if low frequency noise is injected onto the input with sufficient power to corrupt the readings. If this occurs, the device will reject the corrupted sample and set the corresponding bit in the Noise Status register to a logic ‘1’. 5.2.6 RF NOISE DETECTION Each sensor input contains an integrated RF noise detector. This block will detect injected RF noise on the CS pin. The detector threshold is dependent upon the noise frequency. If RF noise is detected on a CS line, that sample is removed and not compared against the threshold. 5.3 ALERT# Pin The ALERT# pin is an active low (or active high when configured) output that is driven when an interrupt event is detected. Whenever an interrupt is generated, the INT bit (see Section 6.1, "Main Control Register") is set. The ALERT# pin is cleared when the INT bit is cleared by the user. Additionally, when the INT bit is cleared by the user, status bits are only cleared if no touch is detected. 5.3.1 SENSOR INTERRUPT BEHAVIOR The sensor interrupts are generated in one of two ways: 1. An interrupt is generated when a touch is detected and, as a user selectable option, when a release is detected (by default - see Section 6.6). See Figure 5-3. 2. If the repeat rate is enabled then, so long as the touch is held, another interrupt will be generated based on the programmed repeat rate (see Figure 5-2). Note: During this recalibration, the device will not respond to touches. Note: Delayed recalibration only works when the delta count is above the active sensor input threshold. If enabled, it is invoked when a sensor pad touch is held longer than the MAX_DUR bit setting.  2015 Microchip Technology Inc. DS00001624B-page 17 CAP1106 When the repeat rate is enabled, the device uses an additional control called MPRESS that determines whether a touch is flagged as a simple “touch” or a “press and hold”. The MPRESS[3:0] bits set a minimum press timer. When the button is touched, the timer begins. If the sensor pad is released before the minimum press timer expires, it is flagged as a touch and an interrupt is generated upon release. If the sensor input detects a touch for longer than this timer value, it is flagged as a “press and hold” event. So long as the touch is held, interrupts will be generated at the programmed repeat rate and upon release (if enabled). APPLICATION NOTE: Figure 5-2 and Figure 5-3 show default operation which is to generate an interrupt upon sensor pad release and an active-low ALERT# pin. APPLICATION NOTE: The host may need to poll the device twice to determine that a release has been detected. FIGURE 5-2: Sensor Interrupt Behavior - Repeat Rate Enabled FIGURE 5-3: Sensor Interrupt Behavior - No Repeat Rate Enabled Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Min Press Setting (280ms) Interrupt on Touch Button Repeat Rate (175ms) Button Repeat Rate (175ms) Interrupt on Release (optional) ALERT# pin (active low) Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Interrupt on Touch Interrupt on Release (optional) ALERT# pin (active low) CAP1106 DS00001624B-page 18  2015 Microchip Technology Inc. 6.0 REGISTER DESCRIPTION The registers shown in Table 6-1 are accessible through the communications protocol. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Address R/W Register Name Function Default Value Page 00h R/W Main Control Controls general power states and power dissipation 00h Page 20 02h R General Status Stores general status bits 00h Page 21 03h R Sensor Input Status Returns the state of the sampled capacitive touch sensor inputs 00h Page 21 0Ah R Noise Flag Status Stores the noise flags for sensor inputs 00h Page 22 10h R Sensor Input 1 Delta Count Stores the delta count for CS1 00h Page 22 11h R Sensor Input 2 Delta Count Stores the delta count for CS2 00h Page 22 12h R Sensor Input 3 Delta Count Stores the delta count for CS3 00h Page 22 13h R Sensor Input 4 Delta Count Stores the delta count for CS4 00h Page 22 14h R Sensor Input 5 Delta Count Stores the delta count for CS5 00h Page 22 15h R Sensor Input 6 Delta Count Stores the delta count for CS6 00h Page 22 1Fh R/W Sensitivity Control Controls the sensitivity of the threshold and delta counts and data scaling of the base counts 2Fh Page 22 20h R/W Configuration Controls general functionality 20h Page 24 21h R/W Sensor Input Enable Controls whether the capacitive touch sensor inputs are sampled 3Fh Page 25 22h R/W Sensor Input Configuration Controls max duration and auto-repeat delay for sensor inputs operating in the full power state A4h Page 25 23h R/W Sensor Input Configuration 2 Controls the MPRESS controls for all sensor inputs 07h Page 26 24h R/W Averaging and Sampling Config Controls averaging and sampling window 39h Page 27 26h R/W Calibration Activate Forces re-calibration for capacitive touch sensor inputs 00h Page 28 27h R/W Interrupt Enable Enables Interrupts associated with capacitive touch sensor inputs 3Fh Page 29 28h R/W Repeat Rate Enable Enables repeat rate for all sensor inputs 3Fh Page 29 2Ah R/W Multiple Touch Configuration Determines the number of simultaneous touches to flag a multiple touch condition 80h Page 30 2Bh R/W Multiple Touch Pattern Configuration Determines the multiple touch pattern (MTP) configuration 00h Page 30 2Dh R/W Multiple Touch Pattern Determines the pattern or number of sensor inputs used by the MTP circuitry 3Fh Page 31  2015 Microchip Technology Inc. DS00001624B-page 19 CAP1106 2Fh R/W Recalibration Configuration Determines re-calibration timing and sampling window 8Ah Page 32 30h R/W Sensor Input 1 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 1 40h Page 33 31h R/W Sensor Input 2 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 2 40h Page 33 32h R/W Sensor Input 3 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 3 40h Page 33 33h R/W Sensor Input 4 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 4 40h Page 33 34h R/W Sensor Input 5 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 5 40h Page 33 35h R/W Sensor Input 6 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 6 40h Page 33 38h R/W Sensor Input Noise Threshold Stores controls for selecting the noise threshold for all sensor inputs 01h Page 33 Standby Configuration Registers 40h R/W Standby Channel Controls which sensor inputs are enabled while in standby 00h Page 34 41h R/W Standby Configuration Controls averaging and cycle time while in standby 39h Page 34 42h R/W Standby Sensitivity Controls sensitivity settings used while in standby 02h Page 35 43h R/W Standby Threshold Stores the touch detection threshold for active sensor inputs in standby 40h Page 36 44h R/W Configuration 2 Stores additional configuration controls for the device 40h Page 24 Base Count Registers 50h R Sensor Input 1 Base Count Stores the reference count value for sensor input 1 C8h Page 36 51h R Sensor Input 2 Base Count Stores the reference count value for sensor input 2 C8h Page 36 52h R Sensor Input 3 Base Count Stores the reference count value for sensor input 3 C8h Page 36 53h R Sensor Input 4 Base Count Stores the reference count value for sensor input 4 C8h Page 36 54h R Sensor Input 5 Base Count Stores the reference count value for sensor input 5 C8h Page 36 55h R Sensor Input 6 Base Count Stores the reference count value for sensor input 6 C8h Page 36 B1h R Sensor Input 1 Calibration Stores the upper 8-bit calibration value for sensor input 1 00h Page 37 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1106 DS00001624B-page 20  2015 Microchip Technology Inc. During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. When a bit is “set”, this means that the user writes a logic ‘1’ to it. When a bit is “cleared”, this means that the user writes a logic ‘0’ to it. 6.1 Main Control Register The Main Control register controls the primary power state of the device. Bits 7 - 6 - GAIN[1:0] - Controls the gain used by the capacitive touch sensing circuitry. As the gain is increased, the effective sensitivity is likewise increased as a smaller delta capacitance is required to generate the same delta count values. The sensitivity settings may need to be adjusted along with the gain settings such that data overflow does not occur. APPLICATION NOTE: The gain settings apply to both Standby and Active states. B2h R Sensor Input 2 Calibration Stores the upper 8-bit calibration value for sensor input 2 00h Page 37 B3h R Sensor Input 3 Calibration Stores the upper 8-bit calibration value for sensor input 3 00h Page 37 B4h R Sensor Input 4 Calibration Stores the upper 8-bit calibration value for sensor input 4 00h Page 37 B5h R Sensor Input 5 Calibration Stores the upper 8-bit calibration value for sensor input 5 00h Page 37 B6h R Sensor Input 6 Calibration Stores the upper 8-bit calibration value for sensor input 6 00h Page 37 B9h R Sensor Input Calibration LSB 1 Stores the 2 LSBs of the calibration value for sensor inputs 1 - 4 00h Page 37 BAh R Sensor Input Calibration LSB 2 Stores the 2 LSBs of the calibration value for sensor inputs 5- 6 00h Page 37 FDh R Product ID CAP1106 Stores a fixed value that identifies each product 55h Page 37 FEh R Manufacturer ID Stores a fixed value that identifies Microchip 5Dh Page 38 FFh R Revision Stores a fixed value that represents the revision number 83h Page 38 TABLE 6-2: MAIN CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 00h R/W Main Control GAIN[1:0] STBY DSLEEP - - - INT 00h TABLE 6-3: GAIN BIT DECODE GAIN[1:0] Capacitive Touch Sensor Gain 1 0 0 0 1 01 2 10 4 11 8 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page  2015 Microchip Technology Inc. DS00001624B-page 21 CAP1106 Bit 5 - STBY - Enables Standby. • ‘0’ (default) - Sensor input scanning is active. • ‘1’ - Capacitive touch sensor input scanning is limited to the sensor inputs set in the Standby Channel register (see Section 6.20). The status registers will not be cleared until read. Sensor inputs that are no longer sampled will flag a release and then remain in a non-touched state. • Bit 4 - DSLEEP - Enables Deep Sleep by deactivating all functions. ‘0’ (default) - Sensor input scanning is active. • ‘1’ - All sensor input scanning is disabled.. The status registers are automatically cleared and the INT bit is cleared. Bit 0 - INT - Indicates that there is an interrupt. When this bit is set, it asserts the ALERT# pin. If a channel detects a touch and its associated interrupt enable bit is not set to a logic ‘1’, no action is taken. This bit is cleared by writing a logic ‘0’ to it. When this bit is cleared, the ALERT# pin will be deasserted and all status registers will be cleared if the condition has been removed. • ‘0’ - No interrupt pending. • ‘1’ - A touch has been detected on one or more channels and the interrupt has been asserted. 6.2 Status Registers All status bits are cleared when the device enters the Deep Sleep (DSLEEP = ‘1’ - see Section 6.1). 6.2.1 GENERAL STATUS - 02H Bit 2 - MULT - Indicates that the device is blocking detected touches due to the Multiple Touch detection circuitry (see Section 6.14). This bit will not cause the INT bit to be set and hence will not cause an interrupt. Bit 1 - MTP - Indicates that the device has detected a number of sensor inputs that exceed the MTP threshold either via the pattern recognition or via the number of sensor inputs (see Section 6.15). This bit will cause the INT bit to be set if the MTP_ALERT bit is also set. This bit will not be cleared until the condition that caused it to be set has been removed. Bit 0 - TOUCH - Indicates that a touch was detected. This bit is set if any bit in the Sensor Input Status register is set. 6.2.2 SENSOR INPUT STATUS - 03H The Sensor Input Status Register stores status bits that indicate a touch has been detected. A value of ‘0’ in any bit indicates that no touch has been detected. A value of ‘1’ in any bit indicates that a touch has been detected. All bits are cleared when the INT bit is cleared and if a touch on the respective capacitive touch sensor input is no longer present. If a touch is still detected, the bits will not be cleared (but this will not cause the interrupt to be asserted - see Section 6.6). Bit 5 - CS6 - Indicates that a touch was detected on Sensor Input 6. Bit 4 - CS5 - Indicates that a touch was detected on Sensor Input 5. Bit 3 - CS4 - Indicates that a touch was detected on Sensor Input 4. Bit 2 - CS3 - Indicates that a touch was detected on Sensor Input 3. Bit 1 - CS2 - Indicates that a touch was detected on Sensor Input 2. Bit 0 - CS1 - Indicates that a touch was detected on Sensor Input 1. TABLE 6-4: STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 02h R General Status - - - - - MULT MTP TOUCH 00h 03h R Sensor Input Status - - CS6 CS5 CS4 CS3 CS2 CS1 00h CAP1106 DS00001624B-page 22  2015 Microchip Technology Inc. 6.3 Noise Flag Status Registers The Noise Flag Status registers store status bits that are generated from the analog block if the detected noise is above the operating region of the analog detector or the RF noise detector. These bits indicate that the most recently received data from the sensor input is invalid and should not be used for touch detection. So long as the bit is set for a particular channel, the delta count value is reset to 00h and thus no touch is detected. These bits are not sticky and will be cleared automatically if the analog block does not report a noise error. APPLICATION NOTE: If the MTP detection circuitry is enabled, these bits count as sensor inputs above the MTP threshold (see Section 5.2.4, "Multiple Touch Pattern Detection") even if the corresponding delta count is not. If the corresponding delta count also exceeds the MTP threshold, it is not counted twice. APPLICATION NOTE: Regardless of the state of the Noise Status bits, if low frequency noise is detected on a sensor input, that sample will be discarded unless the DIS_ANA_NOISE bit is set. As well, if RF noise is detected on a sensor input, that sample will be discarded unless the DIS_RF_NOISE bit is set. 6.4 Sensor Input Delta Count Registers The Sensor Input Delta Count registers store the delta count that is compared against the threshold used to determine if a touch has been detected. The count value represents a change in input due to the capacitance associated with a touch on one of the sensor inputs and is referenced to a calibrated base “Not Touched” count value. The delta is an instantaneous change and is updated once per sensor input per sensing cycle (see Section 5.2.1, "Sensing Cycle"). The value presented is a standard 2’s complement number. In addition, the value is capped at a value of 7Fh. A reading of 7Fh indicates that the sensitivity settings are too high and should be adjusted accordingly (see Section 6.5). The value is also capped at a negative value of 80h for negative delta counts which may result upon a release. 6.5 Sensitivity Control Register TABLE 6-5: NOISE FLAG STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 0Ah R Noise Flag Status - - CS6_ NOISE CS5_ NOISE CS4_ NOISE CS3_ NOISE CS2_ NOISE CS1_ NOISE 00h TABLE 6-6: SENSOR INPUT DELTA COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 10h R Sensor Input 1 Delta Count Sign 64 32 16 8 4 2 1 00h 11h R Sensor Input 2 Delta Count Sign 64 32 16 8 4 2 1 00h 12h R Sensor Input 3 Delta Count Sign 64 32 16 8 4 2 1 00h 13h R Sensor Input 4 Delta Count Sign 64 32 16 8 4 2 1 00h 14h R Sensor Input 5 Delta Count Sign 64 32 16 8 4 2 1 00h 15h R Sensor Input 6 Delta Count Sign 64 32 16 8 4 2 1 00h TABLE 6-7: SENSITIVITY CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 1Fh R/W Sensitivity Control - DELTA_SENSE[2:0] BASE_SHIFT[3:0] 2Fh  2015 Microchip Technology Inc. DS00001624B-page 23 CAP1106 The Sensitivity Control register controls the sensitivity of a touch detection. Bits 6-4 DELTA_SENSE[2:0] - Controls the sensitivity of a touch detection. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta capacitance corresponding to a “lighter” touch. These settings are more sensitive to noise, however, and a noisy environment may flag more false touches with higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely, a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). Bits 3 - 0 - BASE_SHIFT[3:0] - Controls the scaling and data presentation of the Base Count registers. The higher the value of these bits, the larger the range and the lower the resolution of the data presented. The scale factor represents the multiplier to the bit-weighting presented in these register descriptions. APPLICATION NOTE: The BASE_SHIFT[3:0] bits normally do not need to be updated. These settings will not affect touch detection or sensitivity. These bits are sometimes helpful in analyzing the Cap Sensing board performance and stability. TABLE 6-8: DELTA_SENSE BIT DECODE DELTA_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-9: BASE_SHIFT BIT DECODE BASE_SHIFT[3:0] Data Scaling Factor 32 1 0 0 0 0 0 1x 0 0 0 1 2x 0 0 1 0 4x 0 0 1 1 8x 0 1 0 0 16x 0 1 0 1 32x 0 1 1 0 64x 0 1 1 1 128x 1 0 0 0 256x All others 256x (default = 1111b) CAP1106 DS00001624B-page 24  2015 Microchip Technology Inc. 6.6 Configuration Registers The Configuration registers control general global functionality that affects the entire device. 6.6.1 CONFIGURATION - 20H Bit 7 - TIMEOUT - Enables the timeout and idle functionality of the SMBus protocol. • ‘0’ (default for Functional Revision C) - The SMBus timeout and idle functionality are disabled. The SMBus interface will not time out if the clock line is held low. Likewise, it will not reset if both the data and clock lines are held high for longer than 200us. This is used for I2C compliance. • ‘1’ (default for Functional Revision B) - The SMBus timeout and idle functionality are enabled. The SMBus interface will time out if the clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock lines are held high for longer than 200us. Bit 5 - DIS_DIG_NOISE - Determines whether the digital noise threshold (see Section 6.19, "Sensor Input Noise Threshold Register") is used by the device. Setting this bit disables the feature. • ‘0’ - The digital noise threshold is used. If a delta count value exceeds the noise threshold but does not exceed the touch threshold, the sample is discarded and not used for the automatic re-calibration routine. • ‘1’ (default) - The noise threshold is disabled. Any delta count that is less than the touch threshold is used for the automatic re-calibration routine. Bit 4 - DIS_ANA_NOISE - Determines whether the analog noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If low frequency noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if low frequency noise is detected. Bit 3 - MAX_DUR_EN - Determines whether the maximum duration recalibration is enabled. • ‘0’ (default) - The maximum duration recalibration functionality is disabled. A touch may be held indefinitely and no re-calibration will be performed on any sensor input. • ‘1’ - The maximum duration recalibration functionality is enabled. If a touch is held for longer than the MAX_DUR bit settings, then the re-calibration routine will be restarted (see Section 6.8). 6.6.2 CONFIGURATION 2 - 44H Bit 6 - ALT_POL - Determines the ALERT# pin polarity and behavior. • ‘0’ - The ALERT# pin is active high and push-pull. • ‘1’ (default) - The ALERT# pin is active low and open drain. Bit 5 - BLK_PWR_CTRL - Determines whether the device will reduce power consumption while waiting between conversion time completion and the end of the polling cycle. • ‘0’ (default) - The device will always power down as much as possible during the time between the end of the last conversion and the end of the polling cycle. • ‘1’ - The device will not power down the Cap Sensor during the time between the end of the last conversion and the end of the polling cycle. Bit 3 - SHOW_RF_NOISE - Determines whether the Noise Status bits will show RF Noise as the only input source. • ‘0’ (default) - The Noise Status registers will show both RF noise and low frequency EMI noise if either is detected on a capacitive touch sensor input. • ‘1’ - The Noise Status registers will only show RF noise if it is detected on a capacitive touch sensor input. EMI TABLE 6-10: CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 20h R/W Configuration TIMEOUT - DIS_ DIG_ NOISE DIS_ ANA_ NOISE MAX_ DUR_EN - -- A0h (Rev B) 20h (rev C) 44h R/W Configuration 2 - ALT_ POL BLK_PWR_ CTRL - SHOW_ RF_ NOISE DIS_ RF_ NOISE - INT_ REL_n 40h  2015 Microchip Technology Inc. DS00001624B-page 25 CAP1106 noise will still be detected and touches will be blocked normally; however, the status bits will not be updated. Bit 2 - DIS_RF_NOISE - Determines whether the RF noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If RF noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if RF noise is detected. Bit 0 - INT_REL_n - Controls the interrupt behavior when a release is detected on a button. • ‘0’ (default) - An interrupt is generated when a press is detected and again when a release is detected and at the repeat rate (if enabled - see Section 6.13). • ‘1’ - An interrupt is generated when a press is detected and at the repeat rate but not when a release is detected. 6.7 Sensor Input Enable Registers The Sensor Input Enable registers determine whether a capacitive touch sensor input is included in the sampling cycle. The length of the sampling cycle is not affected by the number of sensor inputs measured. Bit 5 - CS6_EN - Enables the CS6 input to be included during the sampling cycle. • ‘0’ - The CS6 input is not included in the sampling cycle. • ‘1’ (default) - The CS6 input is included in the sampling cycle. Bit 4 - CS5_EN - Enables the CS5 input to be included during the sampling cycle. Bit 3 - CS4_EN - Enables the CS4 input to be included during the sampling cycle. Bit 2 - CS3_EN - Enables the CS3 input to be included during the sampling cycle. Bit 1 - CS2_EN - Enables the CS2 input to be included during the sampling cycle. Bit 0 - CS1_EN - Enables the CS1 input to be included during the sampling cycle. 6.8 Sensor Input Configuration Register The Sensor Input Configuration Register controls timings associated with the Capacitive sensor inputs 1 - 6. Bits 7 - 4 - MAX_DUR[3:0] - (default 1010b) - Determines the maximum time that a sensor pad is allowed to be touched until the capacitive touch sensor input is recalibrated, as shown in Table 6-13. TABLE 6-11: SENSOR INPUT ENABLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 21h R/W Sensor Input Enable - - CS6_EN CS5_EN CS4_EN CS3_EN CS2_EN CS1_EN 3Fh TABLE 6-12: SENSOR INPUT CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 22h R/W Sensor Input Configuration MAX_DUR[3:0] RPT_RATE[3:0] A4h TABLE 6-13: MAX_DUR BIT DECODE MAX_DUR[3:0] Time Before Recalibration 32 1 0 0 0 0 0 560ms 0 0 0 1 840ms 0 0 1 0 1120ms 0 0 1 1 1400ms 0 1 0 0 1680ms 0 1 0 1 2240ms 0 1 1 0 2800ms CAP1106 DS00001624B-page 26  2015 Microchip Technology Inc. Bits 3 - 0 - RPT_RATE[3:0] - (default 0100b) Determines the time duration between interrupt assertions when auto repeat is enabled. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-14. 6.9 Sensor Input Configuration 2 Register Bits 3 - 0 - M_PRESS[3:0] - (default 0111b) - Determines the minimum amount of time that sensor inputs configured to use auto repeat must detect a sensor pad touch to detect a “press and hold” event. If the sensor input detects a touch for longer than the M_PRESS[3:0] settings, a “press and hold” event is detected. If a sensor input detects a touch for less than or equal to the M_PRESS[3:0] settings, a touch event is detected. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-16. 1 1 1 3360ms 1 0 0 0 3920ms 1 0 0 1 4480ms 1 0 1 0 5600ms (default) 1 0 1 1 6720ms 1 1 0 0 7840ms 1 1 0 1 8906ms 1 1 1 0 10080ms 1 1 1 1 11200ms TABLE 6-14: RPT_RATE BIT DECODE RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms (default) 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-15: SENSOR INPUT CONFIGURATION 2 REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 23h R/W Sensor Input Configuration 2 - - - - M_PRESS[3:0] 07h TABLE 6-13: MAX_DUR BIT DECODE (CONTINUED) MAX_DUR[3:0] Time Before Recalibration 32 1 0  2015 Microchip Technology Inc. DS00001624B-page 27 CAP1106 6.10 Averaging and Sampling Configuration Register The Averaging and Sampling Configuration register controls the number of samples taken and the total sensor input cycle time for all active sensor inputs while the device is functioning in Active state. Bits 6 - 4 - AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-18. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. For example, if CS1, CS2, and CS3 are sampled during the sensor cycle, and the AVG[2:0] bits are set to take 4 samples per channel, then the full sensor cycle will be: CS1, CS1, CS1, CS1, CS2, CS2, CS2, CS2, CS3, CS3, CS3, CS3. Bits 3 - 2 - SAMP_TIME[1:0] - Determines the time to take a single sample as shown in Table 6-19. TABLE 6-16: M_PRESS BIT DECODE M_PRESS[3:0] M_PRESS SETTINGS 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms (default) 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-17: AVERAGING AND SAMPLING CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 24h R/W Averaging and Sampling Config AVG[2:0] SAMP_TIME[1:0] CYCLE_TIME [1:0] 39h TABLE 6-18: AVG BIT DECODE AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 CAP1106 DS00001624B-page 28  2015 Microchip Technology Inc. Bits 1 - 0 - CYCLE_TIME[1:0] - Determines the overall cycle time for all measured channels during normal operation as shown in Table 6-20. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, then the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.11 Calibration Activate Register The Calibration Activate register forces the respective sensor inputs to be re-calibrated affecting both the analog and digital blocks. During the re-calibration routine, the sensor inputs will not detect a press for up to 600ms and the Sensor Input Base Count register values will be invalid. During this time, any press on the corresponding sensor pads will invalidate the re-calibration. When finished, the CALX[9:0] bits will be updated (see Section 6.25). When the corresponding bit is set, the device will perform the calibration and the bit will be automatically cleared once the re-calibration routine has finished. Bit 5 - CS6_CAL - When set, the CS6 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 4 - CS5_CAL - When set, the CS5 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 3 - CS4_CAL - When set, the CS4 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 2 - CS3_CAL - When set, the CS3 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 1 - CS2_CAL - When set, the CS2 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 0 - CS1_CAL - When set, the CS1 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. TABLE 6-19: SAMP_TIME BIT DECODE SAMP_TIME[1:0] Sample Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-20: CYCLE_TIME BIT DECODE CYCLE_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-21: CALIBRATION ACTIVATE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 26h R/W Calibration Activate - - CS6_ CAL CS5_ CAL CS4_ CAL CS3_ CAL CS2_ CAL CS1_ CAL 00h  2015 Microchip Technology Inc. DS00001624B-page 29 CAP1106 6.12 Interrupt Enable Register The Interrupt Enable register determines whether a sensor pad touch or release (if enabled) causes the interrupt pin to be asserted. Bit 5 - CS6_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS6 (associated with the CS6 status bit). • ‘0’ - The interrupt pin will not be asserted if a touch is detected on CS6 (associated with the CS6 status bit). • ‘1’ (default) - The interrupt pin will be asserted if a touch is detected on CS6 (associated with the CS6 status bit). Bit 4 - CS5_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS5 (associated with the CS5 status bit). Bit 3 - CS4_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS4 (associated with the CS4 status bit). Bit 2 - CS3_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS3 (associated with the CS3 status bit). Bit 1 - CS2_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS2 (associated with the CS2 status bit). Bit 0 - CS1_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS1 (associated with the CS1 status bit). 6.13 Repeat Rate Enable Register The Repeat Rate Enable register enables the repeat rate of the sensor inputs as described in Section 5.3.1. Bit 5 - CS6_RPT_EN - Enables the repeat rate for capacitive touch sensor input 6. • ‘0’ - The repeat rate for CS6 is disabled. It will only generate an interrupt when a touch is detected and when a release is detected no matter how long the touch is held for. • ‘1’ (default) - The repeat rate for CS6 is enabled. In the case of a “touch” event, it will generate an interrupt when a touch is detected and a release is detected (as determined by the INT_REL_n bit - see Section 6.6). In the case of a “press and hold” event, it will generate an interrupt when a touch is detected and at the repeat rate so long as the touch is held. Bit 4 - CS5_RPT_EN - Enables the repeat rate for capacitive touch sensor input 5. Bit 3 - CS4_RPT_EN - Enables the repeat rate for capacitive touch sensor input 4. Bit 2 - CS3_RPT_EN - Enables the repeat rate for capacitive touch sensor input 3. Bit 1 - CS2_RPT_EN - Enables the repeat rate for capacitive touch sensor input 2. Bit 0 - CS1_RPT_EN - Enables the repeat rate for capacitive touch sensor input 1. TABLE 6-22: INTERRUPT ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 27h R/W Interrupt Enable - - CS6_ INT_EN CS5_ INT_EN CS4_ INT_EN CS3_ INT_EN CS2_ INT_EN CS1_ INT_EN 3Fh TABLE 6-23: REPEAT RATE ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 28h R/W Repeat Rate Enable - - CS6_ RPT_EN CS5_ RPT_EN CS4_ RPT_EN CS3_ RPT_EN CS2_ RPT_EN CS1_ RPT_EN 3Fh CAP1106 DS00001624B-page 30  2015 Microchip Technology Inc. 6.14 Multiple Touch Configuration Register The Multiple Touch Configuration register controls the settings for the multiple touch detection circuitry. These settings determine the number of simultaneous buttons that may be pressed before additional buttons are blocked and the MULT status bit is set. Bit 7 - MULT_BLK_EN - Enables the multiple button blocking circuitry. • ‘0’ - The multiple touch circuitry is disabled. The device will not block multiple touches. • ‘1’ (default) - The multiple touch circuitry is enabled. The device will flag the number of touches equal to programmed multiple touch threshold and block all others. It will remember which sensor inputs are valid and block all others until that sensor pad has been released. Once a sensor pad has been released, the N detected touches (determined via the cycle order of CS1 - CS6) will be flagged and all others blocked. Bits 3 - 2 - B_MULT_T[1:0] - Determines the number of simultaneous touches on all sensor pads before a Multiple Touch Event is detected and sensor inputs are blocked. The bit decode is given by Table 6-25. 6.15 Multiple Touch Pattern Configuration Register The Multiple Touch Pattern Configuration register controls the settings for the multiple touch pattern detection circuitry. This circuitry works like the multiple touch detection circuitry with the following differences: 1. The detection threshold is a percentage of the touch detection threshold as defined by the MTP_TH[1:0] bits whereas the multiple touch circuitry uses the touch detection threshold. 2. The MTP detection circuitry either will detect a specific pattern of sensor inputs as determined by the Multiple Touch Pattern register settings or it will use the Multiple Touch Pattern register settings to determine a minimum number of sensor inputs that will cause the MTP circuitry to flag an event. When using pattern recognition mode, if all of the sensor inputs set by the Multiple Touch Pattern register have a delta count greater than the MTP threshold or have their corresponding Noise Flag Status bits set, the MTP bit will be set. When using the absolute number mode, if the number of sensor inputs with thresholds above the MTP threshold or with Noise Flag Status bits set is equal to or greater than this number, the MTP bit will be set. 3. When an MTP event occurs, all touches are blocked and an interrupt is generated. 4. All sensor inputs will remain blocked so long as the requisite number of sensor inputs are above the MTP threshold or have Noise Flag Status bits set. Once this condition is removed, touch detection will be restored. Note that the MTP status bit is only cleared by writing a ‘0’ to the INT bit once the condition has been removed. TABLE 6-24: MULTIPLE TOUCH CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Ah R/W Multiple Touch Config MULT_ BLK_ EN - - - B_MULT_T[1:0] - - 80h TABLE 6-25: B_MULT_T BIT DECODE B_MULT_T[1:0] Number of Simultaneous Touches 1 0 0 0 1 (default) 01 2 10 3 11 4 TABLE 6-26: MULTIPLE TOUCH PATTERN CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Bh R/W Multiple Touch Pattern Config MTP_ EN - - MTP_TH[1:0] COMP_ PTRN MTP_ ALERT 00h  2015 Microchip Technology Inc. DS00001624B-page 31 CAP1106 Bit 7 - MTP_EN - Enables the multiple touch pattern detection circuitry. • ‘0’ (default) - The MTP detection circuitry is disabled. • ‘1’ - The MTP detection circuitry is enabled. Bits 3-2 - MTP_TH[1:0] - Determine the MTP threshold, as shown in Table 6-27. This threshold is a percentage of sensor input threshold (see Section 6.18, "Sensor Input Threshold Registers") when the device is in the Fully Active state or of the standby threshold (see Section 6.23, "Standby Threshold Register") when the device is in the Standby state. Bit 1 - COMP_PTRN - Determines whether the MTP detection circuitry will use the Multiple Touch Pattern register as a specific pattern of sensor inputs or as an absolute number of sensor inputs. • ‘0’ (default) - The MTP detection circuitry will use the Multiple Touch Pattern register bit settings as an absolute minimum number of sensor inputs that must be above the threshold or have Noise Flag Status bits set. The number will be equal to the number of bits set in the register. • ‘1’ - The MTP detection circuitry will use pattern recognition. Each bit set in the Multiple Touch Pattern register indicates a specific sensor input that must have a delta count greater than the MTP threshold or have a Noise Flag Status bit set. If the criteria are met, the MTP status bit will be set. Bit 0 - MTP_ALERT - Enables an interrupt if an MTP event occurs. In either condition, the MTP status bit will be set. • ‘0’ (default) - If an MTP event occurs, the ALERT# pin is not asserted. • ‘1’ - If an MTP event occurs, the ALERT# pin will be asserted. 6.16 Multiple Touch Pattern Register The Multiple Touch Pattern register acts as a pattern to identify an expected sensor input profile for diagnostics or other significant events. There are two methods for how the Multiple Touch Pattern register is used: as specific sensor inputs or number of sensor input that must exceed the MTP threshold or have Noise Flag Status bits set. Which method is used is based on the COMP_PTRN bit (see Section 6.15). The methods are described below. 1. Specific Sensor Inputs: If, during a single polling cycle, the specific sensor inputs above the MTP threshold or with Noise Flag Status bits set match those bits set in the Multiple Touch Pattern register, an MTP event is flagged. 2. Number of Sensor Inputs: If, during a single polling cycle, the number of sensor inputs with a delta count above the MTP threshold or with Noise Flag Status bits set is equal to or greater than the number of pattern bits set, an MTP event is flagged. Bit 5 - CS6_PTRN - Determines whether CS6 is considered as part of the Multiple Touch Pattern. • ‘0’ - CS6 is not considered a part of the pattern. • ‘1’ - CS6 is considered a part of the pattern or the absolute number of sensor inputs that must have a delta count greater than the MTP threshold or have the Noise Flag Status bit set is increased by 1. Bit 4 - CS5_PTRN - Determines whether CS5 is considered as part of the Multiple Touch Pattern. Bit 3 - CS4_PTRN - Determines whether CS4 is considered as part of the Multiple Touch Pattern. Bit 2 - CS3_PTRN - Determines whether CS3 is considered as part of the Multiple Touch Pattern. TABLE 6-27: MTP_TH BIT DECODE MTP_TH[1:0] Threshold Divide Setting 1 0 0 0 12.5% (default) 0 1 25% 1 0 37.5% 1 1 100% TABLE 6-28: MULTIPLE TOUCH PATTERN REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Dh R/W Multiple Touch Pattern - - CS6_ PTRN CS5_ PTRN CS4_ PTRN CS3_ PTRN CS2_ PTRN CS1_ PTRN 3Fh CAP1106 DS00001624B-page 32  2015 Microchip Technology Inc. Bit 1 - CS2_PTRN - Determines whether CS2 is considered as part of the Multiple Touch Pattern. Bit 0 - CS1_PTRN - Determines whether CS1 is considered as part of the Multiple Touch Pattern. 6.17 Recalibration Configuration Register The Recalibration Configuration register controls the automatic re-calibration routine settings as well as advanced controls to program the Sensor Input Threshold register settings. Bit 7 - BUT_LD_TH - Enables setting all Sensor Input Threshold registers by writing to the Sensor Input 1 Threshold register. • ‘0’ - Each Sensor Input X Threshold register is updated individually. • ‘1’ (default) - Writing the Sensor Input 1 Threshold register will automatically overwrite the Sensor Input Threshold registers for all sensor inputs (Sensor Input Threshold 1 through Sensor Input Threshold 6). The individual Sensor Input X Threshold registers (Sensor Input 2 Threshold through Sensor Input 6 Threshold) can be individually updated at any time. Bit 6 - NO_CLR_INTD - Controls whether the accumulation of intermediate data is cleared if the noise status bit is set. • ‘0’ (default) - The accumulation of intermediate data is cleared if the noise status bit is set. • ‘1’ - The accumulation of intermediate data is not cleared if the noise status bit is set. APPLICATION NOTE: Bits 5 and 6 should both be set to the same value. Either both should be set to ‘0’ or both should be set to ‘1’. Bit 5 - NO_CLR_NEG - Controls whether the consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘0’ (default) - The consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘1’ - The consecutive negative delta counts counter is not cleared if the noise status bit is set. Bits 4 - 3 - NEG_DELTA_CNT[1:0] - Determines the number of negative delta counts necessary to trigger a digital recalibration as shown in Table 6-30. Bits 2 - 0 - CAL_CFG[2:0] - Determines the update time and number of samples of the automatic re-calibration routine. The settings apply to all sensor inputs universally (though individual sensor inputs can be configured to support re-calibration - see Section 6.11). TABLE 6-29: RECALIBRATION CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Fh R/W Recalibration Configuration BUT_ LD_TH NO_ CLR_ INTD NO_ CLR_ NEG NEG_DELTA_ CNT[1:0] CAL_CFG[2:0] 8Ah TABLE 6-30: NEG_DELTA_CNT BIT DECODE NEG_DELTA_CNT[1:0] Number of Consecutive Negative Delta Count Values 1 0 00 8 0 1 16 (default) 1 0 32 1 1 None (disabled) TABLE 6-31: CAL_CFG BIT DECODE CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210 0 0 0 16 16 0 0 1 32 32  2015 Microchip Technology Inc. DS00001624B-page 33 CAP1106 Note 6-1 Recalibration Samples refers to the number of samples that are measured and averaged before the Base Count is updated however does not control the base count update period. Note 6-2 Update Time refers to the amount of time (in polling cycle periods) that elapses before the Base Count is updated. The time will depend upon the number of channels active, the averaging setting, and the programmed cycle time. 6.18 Sensor Input Threshold Registers The Sensor Input Threshold registers store the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. When the BUT_LD_TH bit is set (see Section 6.17 - bit 7), writing data to the Sensor Input 1 Threshold register will update all of the sensor input threshold registers (31h - 35h inclusive). 6.19 Sensor Input Noise Threshold Register The Sensor Input Noise Threshold register controls the value of a secondary internal threshold to detect noise and improve the automatic recalibration routine. If a capacitive touch sensor input exceeds the Sensor Input Noise Threshold but does not exceed the sensor input threshold, it is determined to be caused by a noise spike. That sample is not used by the automatic re-calibration routine. This feature can be disabled by setting the DIS_DIG_NOISE bit. 0 1 0 64 64 (default) 0 1 1 128 128 1 0 0 256 256 1 0 1 256 1024 1 1 0 256 2048 1 1 1 256 4096 TABLE 6-32: SENSOR INPUT THRESHOLD REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 30h R/W Sensor Input 1 Threshold - 64 32 16 8 4 2 1 40h 31h R/W Sensor Input 2 Threshold - 64 32 16 8 4 2 1 40h 32h R/W Sensor Input 3 Threshold - 64 32 16 8 4 2 1 40h 33h R/W Sensor Input 4 Threshold - 64 32 16 8 4 2 1 40h 34h R/W Sensor Input 5 Threshold - 64 32 16 8 4 2 1 40h 35h R/W Sensor Input 6 Threshold - 64 32 16 8 4 2 1 40h TABLE 6-33: SENSOR INPUT NOISE THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 38h R/W Sensor Input Noise Threshold CS_BN_TH [1:0] 01h TABLE 6-31: CAL_CFG BIT DECODE (CONTINUED) CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210 CAP1106 DS00001624B-page 34  2015 Microchip Technology Inc. Bits 1-0 - CS1_BN_TH[1:0] - Controls the noise threshold for all capacitive touch sensor inputs, as shown in Table 6-34. The threshold is proportional to the threshold setting. 6.20 Standby Channel Register The Standby Channel register controls which (if any) capacitive touch sensor inputs are active during Standby. Bit 5 - CS6_STBY - Controls whether the CS6 channel is active in Standby. • ‘0’ (default) - The CS6 channel not be sampled during Standby mode. • ‘1’ - The CS6 channel will be sampled during Standby Mode. It will use the Standby threshold setting, and the standby averaging and sensitivity settings. Bit 4 - CS5_STBY - Controls whether the CS5 channel is active in Standby. Bit 3 - CS4_STBY - Controls whether the CS4 channel is active in Standby. Bit 2 - CS3_STBY - Controls whether the CS3 channel is active in Standby. Bit 1 - CS2_STBY - Controls whether the CS2 channel is active in Standby. Bit 0 - CS1_STBY - Controls whether the CS1 channel is active in Standby. 6.21 Standby Configuration Register The Standby Configuration register controls averaging and cycle time for those sensor inputs that are active in Standby. This register is useful for detecting proximity on a small number of sensor inputs as it allows the user to change averaging and sample times on a limited number of sensor inputs and still maintain normal functionality in the fully active state. Bit 7 - AVG_SUM - Determines whether the active sensor inputs will average the programmed number of samples or whether they will accumulate for the programmed number of samples. • ‘0’ - (default) - The active sensor input delta count values will be based on the average of the programmed number of samples when compared against the threshold. • ‘1’ - The active sensor input delta count values will be based on the summation of the programmed number of samples when compared against the threshold. This bit should only be set when performing proximity detection as a physical touch will overflow the delta count registers and may result in false readings. Bits 6 - 4 - STBY_AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-37. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. TABLE 6-34: CSX_BN_TH BIT DECODE CS_BN_TH[1:0] Percent Threshold Setting 1 0 0 0 25% 0 1 37.5% (default) 1 0 50% 1 1 62.5% TABLE 6-35: STANDBY CHANNEL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 40h R/W Standby Channel - - CS6_ STBY CS5_ STBY CS4_ STBY CS3_ STBY CS2_ STBY CS1_ STBY 00h TABLE 6-36: STANDBY CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 41h R/W Standby Configuration AVG_ SUM STBY_AVG[2:0] STBY_SAMP_ TIME[1:0] STBY_CY_TIME [1:0] 39h  2015 Microchip Technology Inc. DS00001624B-page 35 CAP1106 Bit 3-2 - STBY SAMP_TIME[1:0] - Determines the time to take a single sample when the device is in Standby as shown in Table 6-38. Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during standby operation as shown in Table 6-39. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.22 Standby Sensitivity Register The Standby Sensitivity register controls the sensitivity for sensor inputs that are active in Standby. TABLE 6-37: STBY_AVG BIT DECODE STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-38: STBY_SAMP_TIME BIT DECODE STBY_SAMP_TIME[1:0] Sampling Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-39: STBY_CY_TIME BIT DECODE STBY_CY_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-40: STANDBY SENSITIVITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 42h R/W Standby Sensitivity - - - - - STBY_SENSE[2:0] 02h CAP1106 DS00001624B-page 36  2015 Microchip Technology Inc. Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensor inputs that are active in Standby. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more sensitive to noise however and a noisy environment may flag more false touches than higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). 6.23 Standby Threshold Register The Standby Threshold register stores the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. 6.24 Sensor Input Base Count Registers TABLE 6-41: STBY_SENSE BIT DECODE STBY_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-42: STANDBY THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 43h R/W Standby Threshold - 64 32 16 8 4 2 1 40h TABLE 6-43: SENSOR INPUT BASE COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 50h R Sensor Input 1 Base Count 128 64 32 16 8 4 2 1 C8h 51h R Sensor Input 2 Base Count 128 64 32 16 8 4 2 1 C8h 52h R Sensor Input 3 Base Count 128 64 32 16 8 4 2 1 C8h 53h R Sensor Input 4 Base Count 128 64 32 16 8 4 2 1 C8h 54h R Sensor Input 5 Base Count 128 64 32 16 8 4 2 1 C8h 55h R Sensor Input 6 Base Count 128 64 32 16 8 4 2 1 C8h  2015 Microchip Technology Inc. DS00001624B-page 37 CAP1106 The Sensor Input Base Count registers store the calibrated “Not Touched” input value from the capacitive touch sensor inputs. These registers are periodically updated by the re-calibration routine. The routine uses an internal adder to add the current count value for each reading to the sum of the previous readings until sample size has been reached. At this point, the upper 16 bits are taken and used as the Sensor Input Base Count. The internal adder is then reset and the re-calibration routine continues. The data presented is determined by the BASE_SHIFT[3:0] bits (see Section 6.5). 6.25 Sensor Input Calibration Registers The Sensor Input Calibration registers hold the 10-bit value that represents the last calibration value. 6.26 Product ID Register The Product ID register stores a unique 8-bit value that identifies the device. 6.27 Manufacturer ID Register The Vendor ID register stores an 8-bit value that represents Microchip. TABLE 6-44: SENSOR INPUT CALIBRATION REGISTERS ADDR Register R/W B7 B6 B5 B4 B3 B2 B1 B0 Default B1h Sensor Input 1 Calibration R CAL1_9 CAL1_8 CAL1_7 CAL1_6 CAL1_5 CAL1_4 CAL1_3 CAL1_2 00h B2h Sensor Input 2 Calibration R CAL2_9 CAL2_8 CAL2_7 CAL2_6 CAL2_5 CAL2_4 CAL2_3 CAL2_2 00h B3h Sensor Input 3 Calibration R CAL3_9 CAL3_8 CAL3_7 CAL3_6 CAL3_5 CAL3_4 CAL3_3 CAL3_2 00h B4h Sensor Input 4 Calibration R CAL4_9 CAL4_8 CAL4_7 CAL4_6 CAL4_5 CAL4_4 CAL4_3 CAL4_2 00h B5h Sensor Input 5 Calibration R CAL5_9 CAL5_8 CAL5_7 CAL5_6 CAL5_5 CAL5_4 CAL5_3 CAL5_2 00h B6h Sensor Input 6 Calibration R CAL6_9 CAL6_8 CAL6_7 CAL6_6 CAL6_5 CAL6_4 CAL6_3 CAL6_2 00h B9h Sensor Input Calibration LSB 1 R CAL4_1 CAL4_0 CAL3_1 CAL3_0 CAL2_1 CAL2_0 CAL1_1 CAL1_0 00h BAh Sensor Input Calibration LSB 2 R - - - - CAL6_1 CAL6_0 CAL5_1 CAL5_0 00h TABLE 6-45: PRODUCT ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FDh R Product ID CAP1106 0 1 0 1 0 1 0 1 55h TABLE 6-46: VENDOR ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh CAP1106 DS00001624B-page 38  2015 Microchip Technology Inc. 6.28 Revision Register The Revision register stores an 8-bit value that represents the part revision. TABLE 6-47: REVISION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FFh R Revision 1 0 0 0 0 0 1 1 83h  2015 Microchip Technology Inc. DS00001624B-page 39 CAP1106 7.0 PACKAGE INFORMATION 7.1 CAP1106 Package Drawings FIGURE 7-1: 10-Pin DFN 3mm x 3mm Package Drawings (1 of 2) Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging CAP1106 DS00001624B-page 40  2015 Microchip Technology Inc. FIGURE 7-2: 10-Pin DFN 3mm x 3mm Package Drawings (2 of 2) Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging  2015 Microchip Technology Inc. DS00001624B-page 41 CAP1106 7.2 Package Marking FIGURE 7-3: CAP1106 Package Markings 1 8 W NNNA e4 TOP BOTTOM Bottom marking not allowed PB-FREE/GREEN SYMBOL PIN 1 (Ni/Pd PP-LF) Line 1 – Device Code, Week 2x 0.6 Line 2 – Alphanumeric Traceability Code W Lines 1-2: Line 3: Center Horizontal Alignment As Shown CAP1106 DS00001624B-page 42  2015 Microchip Technology Inc. APPENDIX A: DEVICE DELTA A.1 Delta from CAP1006 to CAP1106 1. Updated circuitry to improve power supply rejection. 2. Added Multiple Touch Pattern detection circuitry. See Section 6.15, "Multiple Touch Pattern Configuration Register". 3. Added General Status register to flag Multiple touches, Multiple Touch Pattern issues and general touch detections. See Section 6.2, "Status Registers". 4. Added bits 6 and 5 to the Recalibration Configuration register (2Fh - see Section 6.17, "Recalibration Configuration Register"). These bits control whether the accumulation of intermediate data and the consecutive negative delta counts counter are cleared when the noise status bit is set. 5. Added Configuration 2 register for noise detection controls and control to interrupt on press but not on release. Added control to change alert pin polarity. See Section 6.6, "Configuration Registers". 6. Updated Deep Sleep behavior so that device does not clear DSLEEP bit on received communications but will wake to communicate. 7. Register delta: Table A.1 Register Delta From CAP1006 to CAP1106 Address Register Delta Delta Default 00h Page 20 Changed - Main Status / Control added bits 7-6 to control gain 00h 02h Page 21 New - General Status new register to store MTP, MULT, and general TOUCH bits 00h 44h Page 24 New - Configuration 2 new register to control alert polarity, and noise detection, and interrupt on release 00h 24h Page 27 Changed - Averaging Control updated register bits - moved SAMP_AVG[2:0] bits and added SAMP_- TIME bit 1. Default changed 39h 2Bh Page 30 New - Multiple Touch Pattern Configuration new register for Multiple Touch Pattern configuration - enable and threshold settings 80h 2Dh Page 31 New - Multiple Touch Pattern Register new register for Multiple Touch Pattern detection circuitry - pattern or number of sensor inputs 3Fh 2Fh Page 32 Changed - Recalibration Configuration updated register - updated CAL_CFG bit decode to add a 128 averages setting and removed highest time setting. Default changed. Added bit 6 NO_CLR_INTD and bit 5 NO_CLR_NEG. 8Ah 38h Page 33 Changed - Sensor Input Noise Threshold updated register bits - removed bits 7 - 3 and consolidated all controls into bits 1 - 0. These bits will set the noise threshold for all channels. Default changed 01h 39h Removed - Noise Threshold Register 2 removed register n/a 41h Page 34 Changed - Standby Configuration updated register bits - moved STBY_AVG[2:0] bits and added STBY_- TIME bit 1. Default changed 39h FDh Page 37 Changed - Product ID Changed bit decode for CAP1106 55h  2015 Microchip Technology Inc. DS00001624B-page 43 CAP1106 APPENDIX B: DATA SHEET REVISION HISTORY Revision Section/Figure/Entry Correction DS00001624B (02-09-15) Features, Table 2-2, Table 2- 2, "Pin Types", Section 5.0, "General Description" References to BC-Link Interface, BC_DATA, BC_- CLK, BC-IRQ#, BC-Link bus have been removed Application Note under Table 2-6 [BC-Link] hidden in data sheet Table 3-2, "Electrical Specifications" BC-Link Timing Section hidden in data sheet Table 4-1 Protocol Used for 68K Pull Down Resistor changed from “BC-Link Communications” to “Reserved” Section 4.1.3 BC-Link Communications Removed this section and Application Note Section 4.2.2, "SMBus Address and RD / WR Bit" Replaced “client address” with “slave address” in this section. Section 4.2.4, SMBus ACK and NACK Bits, Section 4.2.5, SMBus Stop Bit,Section 4.2.7, SMBus and I2C Compatibility Replaced “client” with “slave” in these sections. Table 4-3, "Read Byte Protocol" Heading changed from “Client Address” to “Slave Address” Section 5.1, Power States Removed “BC-Link” Application Notes Table 6-1 Register Name for Register Address 77h changed from “LED Linked Transition Control” to “Linked LED Transition Control” Section 6.1 Main Control Register BC-Link paragraph removed from Bit 4 under Table 6-3 Section 7.7 Package Marking Updated package drawing Figure 7-25 CAP1106 with BC-Link Support Package Markings Removed figure. Appendix A: Device Delta changed 2Dh to 2Fh in item #12 Product Identification System Removed BC-Link references REV A REV A replaces previous SMSC version Rev. 1.32 (01-05-12) Rev. 1.32 (01-05-12) Table 3-2, "Electrical Specifications" Added conditions for tHD:DAT. Section 4.2.7, "SMBus and I2C Compatibility" Renamed from “SMBus and I2C Compliance.” First paragraph, added last sentence: “For information on using the CAP1106 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I 2C Systems.” Added: CAP1106 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. Section 6.4, "Sensor Input Delta Count Registers" Changed negative value cap from FFh to 80h. Rev. 1.31 (08-18-11) Section 4.3.3, "SMBus Send Byte" Added an application note: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Section 4.3.4, "SMBus Receive Byte" Added an application note: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). CAP1106 DS00001624B-page 44  2015 Microchip Technology Inc. Section 6.2, "Status Registers" Removed RESET as bit 3 in register 02h. Rev. 1.3 (05-18-11) Section 6.28, "Revision Register" Updated revision ID from 82h to 83h. Section 6.2, "Status Registers" Added RESET as bit 3 in register 02h. Rev. 1.2 (02-10-11) Section A.8, "Delta from Rev B (Mask B0) to Rev C (Mask B1)" Added. Table 3-2, "Electrical Specifications" PSR improvements made in functional revision B. Changed PSR spec from ±100 typ and ±200 max counts / V to ±3 and ±10 counts / V. Conditions updated. Section 5.2.2, "Recalibrating Sensor Inputs" Added more detail with subheadings for each type of recalibration. Section 6.6, "Configuration Registers" Added bit 5 BLK_PWR_CTRL to the Configuration 2 Register 44h. The TIMEOUT bit is set to ‘1’ by default for functional revision B and is set to ‘0’ by default for functional revision C. Section 6.28, "Revision Register" Updated revision ID in register FFh from 81h to 82h. Rev. 1.1 (11-17-10) Document Updated for functional revision B. See Section A.7, "Delta from Rev A (Mask A0) to Rev B (Mask B0)". Cover Added to General Description: “includes circuitry and support for enhanced sensor proximity detection.” Added the following Features: Calibrates for Parasitic Capacitance Analog Filtering for System Noise Sources Press and Hold feature for Volume-like Applications Table 3-2, "Electrical Specifications" Conditions for Power Supply Rejection modified adding the following: Sampling time = 2.56ms Averaging = 1 Negative Delta Counts = Disabled All other parameters default Section 6.11, "Calibration Activate Register" Updated register description to indicate which re-calibration routine is used. Section 6.14, "Multiple Touch Configuration Register" Updated register description to indicate what will happen. Table 6-34, "CSx_BN_TH Bit Decode" Table heading changed from “Threshold Divide Setting” to “Percent Threshold Setting”. Rev. 1.0 (06-14-10) Initial release Revision Section/Figure/Entry Correction  2015 Microchip Technology Inc. DS00001624B-page 45 CAP1106 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support CAP1106 DS00001624B-page 46  2015 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] - [X] - XXX - [X](1) l l l l l Device Temperature Addressing Package Tape and Reel Range Option Option Example: Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Device: CAP1106 Temperature Range: Blank = 0°C to +85°C (Extended Commercial) Package: AIA = DFN Tape and Reel Option: TR = Tape and Reel(1) CAP1106-1-AIA-TR 10-pin DFN 3mm x 3mm (RoHS compliant) Six capacitive touch sensor inputs, SMBus interface Reel size is 4,000 pieces  2015 Microchip Technology Inc. DS00001624B-page 47 CAP1106 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. 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Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632770349 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2015 Microchip Technology Inc. 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DS00001623B-page 1 General Description The CAP1126, which incorporates RightTouch® technology, is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains six (6) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1126 also contains two (2) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. The CAP1126 includes Multiple Pattern Touch recognition that allows the user to select a specific set of buttons to be touched simultaneously. If this pattern is detected, then a status bit is set and an interrupt generated. Additionally, the CAP1126 includes circuitry and support for enhanced sensor proximity detection. The CAP1126 offers multiple power states operating at low quiescent currents. In the Standby state of operation, one or more capacitive touch sensor inputs are active and all LEDs may be used. If a touch is detected, it will wake the system using the WAKE/SPI_MOSI pin. Deep Sleep is the lowest power state available, drawing 5uA (typical) of current. In this state, no sensor inputs are active. Driving the WAKE/SPI_MOSI pin or communications will wake the device. Applications • Desktop and Notebook PCs • LCD Monitors • Consumer Electronics • Appliances Features • Six (6) Capacitive Touch Sensor Inputs - Programmable sensitivity - Automatic recalibration - Individual thresholds for each button • Proximity Detection • Multiple Button Pattern Detection • Calibrates for Parasitic Capacitance • Analog Filtering for System Noise Sources • Press and Hold feature for Volume-like Applications • Multiple Communication Interfaces - SMBus / I2C compliant interface - SPI communications - Pin selectable communications protocol and multiple slave addresses (SMBus / I2C only) • Low Power Operation - 5uA quiescent current in Deep Sleep - 50uA quiescent current in Standby (1 sensor input monitored) - Samples one or more channels in Standby • Two (2) LED Driver Outputs - Open Drain or Push-Pull - Programmable blink, breathe, and dimness controls - Can be linked to Capacitive Touch Sensor inputs • Dedicated Wake output flags touches in low power state • System RESET pin • Available in 16-pin 4mm x 4mm RoHS compliant QFN package CAP1126 6 Channel Capacitive Touch Sensor with 2 LED Drivers CAP1126 DS00001623B-page 2  2015 Microchip Technology Inc. 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Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2015 Microchip Technology Inc. DS00001623B-page 3 CAP1126 Table of Contents 1.0 Block Diagram ................................................................................................................................................................................. 4 2.0 Pin Description ................................................................................................................................................................................ 5 3.0 Electrical Specifications .................................................................................................................................................................. 9 4.0 Communications ........................................................................................................................................................................... 12 5.0 General Description ...................................................................................................................................................................... 23 6.0 Register Description ...................................................................................................................................................................... 29 7.0 Package Information ..................................................................................................................................................................... 67 Appendix A: Device Delta ................................................................................................................................................................... 72 Appendix B: Data Sheet Revision History ........................................................................................................................................... 74 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77 CAP1126 DS00001623B-page 4  2015 Microchip Technology Inc. 1.0 BLOCK DIAGRAM SMBus / BC-Link / SPI Slave Protocol SMCLK BC_CLK / SPI_CLK SMDATA BC_DATA / SPI_MSIO / SPI_MISO VDD GND ALERT# / BC_IRQ# Capacitive Touch Sensing Algorithm LED1 CS1 CS2 CS3 CS4 CS5 CS6 LED Driver, Breathe, and Dimness control RESET WAKE / SPI_MOSI ADDR_COMM SPI_CS# LED2  2015 Microchip Technology Inc. DS00001623B-page 5 CAP1126 2.0 PIN DESCRIPTION FIGURE 2-1: CAP1126 Pin Diagram (16-Pin QFN) TABLE 2-1: PIN DESCRIPTION FOR CAP1126 Pin Number Pin Name Pin Function Pin Type Unused Connection 1 SPI_CS# Active low chip-select for SPI bus DI (5V) Connect to Ground 2 WAKE / SPI_- MOSI WAKE - Active high wake / interrupt output Standby power state - requires pull-down resistor DO Pull-down WAKE - Active high wake input - requires pull-down Resistor resistor Deep Sleep power state DI SPI_MOSI - SPI Master-Out-Slave-In port when used in normal mode DI (5V) Connect to Ground 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 SMCLK / BC_CLK / SPI_CLK SMDATA / BC_DATA / SPI_MSIO / SPI_MISO WAKE / SPI_MOSI ADDR_COMM VDD CS6 SPI_CS# CS5 CS1 CS2 CS3 RESET LED1 LED2 CS4 ALERT# / BC_IRQ# CAP1126 16 pin QFN GND CAP1126 DS00001623B-page 6  2015 Microchip Technology Inc. 3 SMDATA / SPI_MSIO / SPI_MISO SMDATA - Bi-directional, open-drain SMBus data - requires pull-up resistor DIOD (5V) n/a SPI_MSIO - SPI Master-Slave-In-Out bidirectional port when used in bi-directional mode DIO SPI_MISO - SPI Master-In-Slave-Out port when used in normal mode DO 4 SMCLK / SPI_- CLK SMCLK - SMBus clock input - requires pull-up resistor DI (5V) SPI_CLK - SPI clock input DI (5V) n/a 5 LED1 Open drain LED 1 driver (default) OD (5V) Connect to Ground Push-pull LED 1 driver DO leave open or connect to Ground 6 LED2 Open drain LED 2 driver (default) OD (5V) Connect to Ground Push-pull LED 2 driver DO leave open or connect to Ground 7 RESET Active high soft reset for system - resets all registers to default values. If not used, connect to ground. DI (5V) Connect to Ground 8 ALERT# ALERT# - Active low alert / interrupt output for SMBus alert or SPI interrupt OD (5V) Connect to Ground ALERT# - Active high push-pull alert / interrupt output for SMBus alert or SPI interrupt DO leave open 9 ADDR_COMM Address / communications select pin - pull-down resistor determines address / communications mechanism AI n/a 10 CS6 Capacitive Touch Sensor Input 6 AIO Connect to Ground 11 CS5 Capacitive Touch Sensor Input 5 AIO Connect to Ground 12 CS4 Capacitive Touch Sensor Input 4 AIO Connect to Ground 13 CS3 Capacitive Touch Sensor Input 3 AIO Connect to Ground 14 CS2 Capacitive Touch Sensor Input 2 AIO Connect to Ground 15 CS1 Capacitive Touch Sensor Input 1 AIO Connect to Ground 16 VDD Positive Power supply Power n/a TABLE 2-1: PIN DESCRIPTION FOR CAP1126 (CONTINUED) Pin Number Pin Name Pin Function Pin Type Unused Connection  2015 Microchip Technology Inc. DS00001623B-page 7 CAP1126 APPLICATION NOTE: When the ALERT# pinis configured as an active low output, it will be open drain. When it is configured as an active high output, it will be push-pull. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the CAP1126 is unpowered. APPLICATION NOTE: The SPI_CS# pin should be grounded when SMBus, or I2C,communications are used. The pin types are described in Table 2-2. All pins labeled with (5V) are 5V tolerant. Bottom Pad GND Ground Power n/a TABLE 2-2: PIN TYPES Pin Type Description Power This pin is used to supply power or ground to the device. DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant. AIO Analog Input / Output -This pin is used as an I/O for analog signals. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. DO Push-pull Digital Output - This pin is used as a digital output and can sink and source current. DIO Push-pull Digital Input / Output - This pin is used as an I/O for digital signals. TABLE 2-1: PIN DESCRIPTION FOR CAP1126 (CONTINUED) Pin Number Pin Name Pin Function Pin Type Unused Connection CAP1126 DS00001623B-page 8  2015 Microchip Technology Inc. 3.0 ELECTRICAL SPECIFICATIONS Note 3-1 Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3-2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V5VT_PIN and VDD must never exceed 3.6V. Note 3-3 The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 3x3 matrix of 0.3mm (12mil) vias at 1.0mm pitch connected to the ground plane with a 2.1mm x 2.1mm thermal landing. Note 3-4 Junction to Ambient (θJA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the θJA is approximately 60°C/W including localized PCB temperature increase. TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Voltage on 5V tolerant pins (V5VT_PIN) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_PIN - VDD|) Note 3-2 0 to 3.6 V Voltage on VDD pin -0.3 to 4 V Voltage on any other pin to GND -0.3 to VDD + 0.3 V Package Power Dissipation up to TA = 85°C for 16 pin QFN (see Note 3-3) 0.9 W Junction to Ambient (θJA) (see Note 3-4) 58 °C/W Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 8000 V  2015 Microchip Technology Inc. DS00001623B-page 9 CAP1126 TABLE 3-2: ELECTRICAL SPECIFICATIONS VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions DC Power Supply Voltage VDD 3.0 3.3 3.6 V Supply Current ISTBY 120 170 uA Standby state active 1 sensor input monitored No LEDs active Default conditions (8 avg, 70ms cycle time) ISTBY 50 uA Standby state active 1 sensor input monitored No LEDs active 1 avg, 140ms cycle time, IDSLEEP 5 15 uA Deep Sleep state active LEDs at 100% or 0% Duty Cycle No communications TA < 40°C 3.135 < VDD < 3.465V IDD 500 600 uA Capacitive Sensing Active No LEDs active Capacitive Touch Sensor Inputs Maximum Base Capacitance CBASE 50 pF Pad untouched Minimum Detectable Capacitive Shift ΔCTOUCH 20 fF Pad touched - default conditions (1 avg, 35ms cycle time, 1x sensitivity) Recommended Cap Shift ΔCTOUCH 0.1 2 pF Pad touched - Not tested Power Supply Rejection PSR ±3 ±10 counts / V Untouched Current Counts Base Capacitance 5pF - 50pF Maximum sensitivity Negative Delta Counts disabled All other parameters default Timing RESET Pin Delay tRST_DLY 10 ms Time to communications ready tCOMM_DLY 15 ms Time to first conversion ready tCONV_DLY 170 200 ms LED Drivers Duty Cycle DUTYLED 0 100 % Programmable Drive Frequency fLED 2 kHz Sinking Current ISINK 24 mA VOL = 0.4 Sourcing Current ISOURCE 24 mA VOH = VDD - 0.4 Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered I/O Pins Output Low Voltage VOL 0.4 V ISINK_IO = 8mA Output High Voltage VOH VDD - 0.4 V ISOURCE_IO = 8mA CAP1126 DS00001623B-page 10  2015 Microchip Technology Inc. Note 3-5 The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage. Note 3-6 The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage. Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered RESET Pin Release to conversion ready tRESET 170 200 ms SMBus Timing Input Capacitance CIN 5 pF Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 us Start Setup Time tSU:STA 0.6 us Start Hold Time tHD:STA 0.6 us Stop Setup Time tSU:STO 0.6 us Data Hold Time tHD:DAT 0 us When transmitting to the master Data Hold Time tHD:DAT 0.3 us When receiving from the master Data Setup Time tSU:DAT 0.6 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line SPI Timing Clock Period tP 250 ns Clock Low Period tLOW 0.4 x tP 0.6 x tP ns Clock High Period tHIGH 0.4 x tP 0.6 x tP ns Clock Rise / Fall time tRISE / tFALL 0.1 x tP ns Data Output Delay tD:CLK 10 ns Data Setup Time tSU:DAT 20 ns Data Hold Time tHD:DAT 20 ns SPI_CS# to SPI_CLK setup time tSU:CS 0 ns Wake Time tWAKE 10 20 us SPI_CS# asserted to CLK assert TABLE 3-2: ELECTRICAL SPECIFICATIONS (CONTINUED) VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions  2015 Microchip Technology Inc. DS00001623B-page 11 CAP1126 4.0 COMMUNICATIONS 4.1 Communications The CAP1126communicates using the 2-wire SMBus or I2C bus, the 2-wire proprietary BC-Link, or the SPI bus. If the proprietary BC-Link protocol is required for your application, please contact your Microchip representative for ordering instructions. Regardless of communication mechanism, the device functionality remains unchanged. The communications mechanism as well as the SMBus (or I2C) slave address is determined by the resistor connected between the ADDR_COMM pin and ground as shown in Table 4-1. 4.1.1 SMBUS (I2C) COMMUNICATIONS When configured to communicate via the SMBus, the CAP1126 supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block. In addition, the device supports I2C formatting for block read and block write protocols. APPLICATION NOTE: For SMBus/I2C communications, the SPI_CS# pin is not used and should be grounded; any data presented to this pin will be ignored. See Section 4.2 and Section 4.3 for more information on the SMBus bus and protocols respectively. 4.1.2 SPI COMMUNICATIONS When configured to communicate via the SPI bus, the CAP1126supports both bi-directional 3-wire and normal 4-wire protocols and uses the SPI_CS# pin to enable communications. APPLICATION NOTE: See Section 4.5 and Section 4.6 for more information on the SPI bus and protocols respectively.Upon power up, the CAP1126 will not respond to any communications for up to 15ms. After this time, full functionality is available. 4.2 System Management Bus The CAP1126 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1126 will not stretch the clock signal. TABLE 4-1: ADDR_COMM PIN DECODE Pull-Down Resistor (+/- 5%) Protocol Used SMBus Address GND SPI Communications using Normal 4-wire Protocol Used n/a 56k SPI Communications using BiDirectional 3-wire Protocol Used n/a 68k Reserved n/a 82k SMBus / I2C 0101_100(r/w) 100k SMBus / I2C 0101_011(r/w) 120k SMBus / I2C 0101_010(r/w) 150k SMBus / I2C 0101_001(r/w) VDD SMBus / I2C 0101_000(r/w) CAP1126 DS00001623B-page 12  2015 Microchip Technology Inc. 4.2.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.2.2 SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the slave device. See Table 4-1 for available SMBus addresses. 4.2.3 SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.2.4 SMBUS ACK AND NACK BITS The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives except the last data byte. 4.2.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1126 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. 4.2.6 SMBUS TIMEOUT The CAP1126 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the SMCLK pin is held low, the device will timeout and reset the SMBus interface. The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register (see Section 6.6, "Configuration Registers"). 4.2.7 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the CAP1126 in an I2C system, refer to AN 14.0 Dedicated Slave Devices in I2C Systems. FIGURE 4-1: SMBus Timing Diagram SMDATA SMCLK TLOW TRISE THIGH TFALL TBUF THD:STA P S S - Start Condition P - Stop Condition THD:DAT TSU:DAT TSU:STA THD:STA P TSU:STO S  2015 Microchip Technology Inc. DS00001623B-page 13 CAP1126 1. CAP1126 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2. Minimum frequency for SMBus communications is 10kHz. 3. The SMBus slave protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the CAP1126 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4. The SMBus slave protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200µs (idle condition). This function is disabled by default in the CAP1126 and can be enabled by writing to the TIMEOUT bit. I2C does not have an idle condition. 5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). 6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. The CAP1126 supports I2C formatting only. 4.3 SMBus Protocols The CAP1126 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid protocols as shown below. All of the below protocols use the convention in Table 4-2. 4.3.1 SMBUS WRITE BYTE The Write Byte is used to write one byte of data to a specific register as shown in Table 4-3. 4.3.2 SMBUS READ BYTE The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4-4. 4.3.3 SMBUS SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4-5. APPLICATION NOTE: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). TABLE 4-2: PROTOCOL FORMAT Data Sent to Device Data Sent to the HOst Data sent Data sent TABLE 4-3: WRITE BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK Stop 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1 TABLE 4-4: READ BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data NACK Stop 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh 1 0 -> 1 TABLE 4-5: SEND BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Stop 1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 CAP1126 DS00001623B-page 14  2015 Microchip Technology Inc. 4.3.4 SMBUS RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4-6. APPLICATION NOTE: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.4 I2C Protocols The CAP1126 supports I2C Block Write and Block Read. The protocols listed below use the convention in Table 4-2. 4.4.1 BLOCK WRITE The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 4-7. APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.4.2 BLOCK READ The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 4-8. APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.5 SPI Interface The SMBus has a predefined packet structure, the SPI does not. The SPI Bus can operate in two modes of operation, normal 4-wire mode and bi-directional 3-wire mode. All SPI commands consist of 8-bit packets sent to a specific slave device (identified by the CS pin). The SPI bus will latch data on the rising edge of the clock and the clock and data both idle high. All commands are supported via both operating modes. The supported commands are: Reset Serial interface, set address pointer, write command and read command. Note that all other codes received during the command phase are ignored and have no effect on the operation of the device. TABLE 4-6: RECEIVE BYTE PROTOCOL Start Slave Address RD ACK Register Data NACK Stop 1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1 TABLE 4-7: BLOCK WRITE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK . . . Register Data ACK Stop XXh 0 XXh 0 . . . XXh 0 0 -> 1 TABLE 4-8: BLOCK READ PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK . . . Register Data NACK Stop 0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1  2015 Microchip Technology Inc. DS00001623B-page 15 CAP1126 4.5.1 SPI NORMAL MODE The SPI Bus can operate in two modes of operation, normal and bi-directional mode. In the normal mode of operation, there are dedicated input and output data lines. The host communicates by sending a command along the CAP1126 SPI_MOSI data line and reading data on the SPI_MISO data line. Both communications occur simultaneously which allows for larger throughput of data transactions. All basic transfers consist of two 8 bit transactions from the Master device while the slave device is simultaneously sending data at the current address pointer value. Data writes consist of two or more 8-bit transactions. The host sends a specific write command followed by the data to write the address pointer. Data reads consist of one or more 8-bit transactions. The host sends the specific read data command and continues clocking for as many data bytes as it wishes to receive. 4.5.2 SPI BI-DIRECTIONAL MODE In the bi-directional mode of operation, the SPI data signals are combined into the SPI_MSIO line, which is shared for data received by the device and transmitted by the device. The protocol uses a simple handshake and turn around sequence for data communications based on the number of clocks transmitted during each phase. All basic transfers consist of two 8 bit transactions. The first is an 8 bit command phase driven by the Master device. The second is by an 8 bit data phase driven by the Master for writes, and by the CAP1126 for read operations. The auto increment feature of the address pointer allows for successive reads or writes. The address pointer will return to 00h after reaching FFh. 4.5.3 SPI_CS# PIN The SPI Bus is a single master, multiple slave serial bus. Each slave has a dedicated CS pin (chip select) that the master asserts low to identify that the slave is being addressed. There are no formal addressing options. 4.5.4 ADDRESS POINTER All data writes and reads are accessed from the current address pointer. In both Bi-directional mode and Full Duplex mode, the Address pointer is automatically incremented following every read command or every write command. The address pointer will return to 00h after reaching FFh. 4.5.5 SPI TIMEOUT The CAP1126 does not detect any timeout conditions on the SPI bus. FIGURE 4-2: SPI Timing SPI_MSIO or SPI_MOSI or SPI_MISO SPI_CLK tLOW tRISE tHIGH tFALL tD:CLK tHD:DAT tSU:DAT tP  2015 Microchip Technology Inc. DS00001623B-page 16 CAP1126 4.6 Normal SPI Protocols When operating in normal mode, the SPI bus internal address pointer is incremented depending upon which command has been transmitted. Multiple commands may be transmitted sequentually so long as the SPI_CS# pin is asserted low. Figure 4-3 shows an example of this operation. 4.6.1 RESET INTERFACE Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation. FIGURE 4-3: Example SPI Bus Communication - Normal Mode SPI_CS# SPI_MISO SPI_MOSI SPI Address Pointer SPI Data output buffer Register Address / Data 7Ah XXh (invalid) XXh (invalid) YYh (invalid) 7Ah 7Dh 41h YYh (invalid) 7Eh 66h XXh (invalid) 45h 7Dh 41h AAh (invalid) AAh (invalid) 7Fh 7Fh 55h (invalid) 66h 7Fh AAh 7Dh 43h 40h 78h 7Fh XXh (invalid) 7Fh 56h 40h / 56h 41h / 45h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 45h 40h / 56h 41h / 45h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 42h AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 55h 7Fh AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 66h 42h AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 44h 80h 40h 80h 40h 56h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 43h 55h 7Fh 7Fh 55h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 80h 45h 43h 46h 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 00h XXh Indicates SPI Address pointer incremented  2015 Microchip Technology Inc. DS00001623B-page 17 CAP1126 4.6.2 SET ADDRESS POINTER The Set Address Pointer command sets the Address pointer for subsequent reads and writes of data. The pointer is set on the rising edge of the final data bit. At the same time, the data that is to be read is fetched and loaded into the internal output buffer but is not transmitted. 4.6.3 WRITE DATA The Write Data protocol updates the contents of the register referenced by the address pointer. As the command is processed, the data to be read is fetched and loaded into the internal output buffer but not transmitted. Then, the register is updated with the data to be written. Finally, the address pointer is incremented. FIGURE 4-4: SPI Reset Interface Command - Normal Mode FIGURE 4-5: SPI Set Address Pointer Command - Normal Mode Master SPDOUT SPI_MOSI SPI_CS# SPI_CLK Reset - 7Ah Reset - 7Ah Invalid register data 00h – Internal Data buffer empty SPI_MISO Master Drives Slave Drives ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ Master SPDOUT SPI_MOSI Register Address SPI_CS# SPI_CLK Set Address Pointer – 7Dh SPI_MISO Unknown, Invalid Data Unknown, Invalid Data Master Drives Slave Drives Address pointer set ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ CAP1126 DS00001623B-page 18  2015 Microchip Technology Inc. 4.6.4 READ DATA The Read Data protocol is used to read data from the device. During the normal mode of operation, while the device is receiving data, the CAP1126 is simultaneously transmitting data to the host. For the Set Address commands and the Write Data commands, this data may be invalid and it is recommended that the Read Data command is used. FIGURE 4-6: SPI Write Command - Normal Mode FIGURE 4-7: SPI Read Command - Normal Mode Master SPDOUT SPI_MOSI Data to Write SPI_CS# SPI_CLK Write Command – 7Eh Unknown, Invalid Data Old Data at Current Address Pointer SPI_MISO Master Drives Slave Drives 1. Data written at current address pointer 2. Address pointer incremented Master SPDOUT SPI_MOSI Master Drives Slave Drives SPI_CLK First Read Command – 7Fh SPI_CS# SPI_MISO Invalid, Unknown Data * ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Subsequent Read Commands – 7F Data at Current Address Pointer Address Pointer Incremented ** ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ * The first read command after any other command will return invalid data for the first byte. Subsequent read commands will return the data at the Current Address Pointer ** The Address Pointer is incremented 8 clocks after the Read Command has been received. Therefore continually sending Read Commands will result in each command reporting new data. Once Read Commands have been finished, the last data byte will be read during the next 8 clocks for any command  2015 Microchip Technology Inc. DS00001623B-page 19 CAP1126 4.7 Bi-Directional SPI Protocols 4.7.1 RESET INTERFACE Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation. 4.7.2 SET ADDRESS POINTER Sets the address pointer to the register to be accessed by a read or write command. This command overrides the autoincrementing of the address pointer. FIGURE 4-8: SPI Read Command - Normal Mode - Full FIGURE 4-9: SPI Reset Interface Command - Bi-directional Mode Master SPDOUT SPI_MOSI Master Drives Slave Drives SPI_CLK Read Command – 7Fh SPI_CS# Data at previously set register address = current address pointer SPI_MISO ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Data at previously set register address = current address pointer (SPI) XXh 1. Register Read Address updated to Current SPI Read Address pointer 1. Register data loaded into output buffer = data at current address pointer 1. Output buffer transmitted = data at previous address pointer + 1 = current address pointer 1. Register Read Address incremented = current address pointer + 1 1. SPI Read Address Incremented = new current address pointer 2. Register Read Address Incremented = current address pointer +1 Register Data loaded into Output buffer = data at current address pointer + 1 1. Output buffer transmitted = data at current address pointer + 1 2. Flag set to increment SPI Read Address at end of next 8 clocks ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Data at previously set register address = current address pointer (SPI) 1. Register data loaded into output buffer = data at current address pointer 1. Output buffer transmitted = data at previous register address pointer + 1 = current address pointer 1. Output buffer transmitted = data at current address pointer + 1 2. Flag set to increment SPI Read Address at end of next 8 clocks Subsequent Read Commands – 7Fh 1. Register Read Address updated to Current SPI Read Address pointer. 2. Register Read Address incremented = current address pointer +1 – end result = register address pointer doesn’t change Master SPDOUT SPI_MSIO SPI_CS# SPI_CLK Reset - 7Ah Reset - 7Ah ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ CAP1126 DS00001623B-page 20  2015 Microchip Technology Inc. 4.7.3 WRITE DATA Writes data value to the register address stored in the address pointer. Performs auto increment of address pointer after the data is loaded into the register. 4.7.4 READ DATA Reads data referenced by the address pointer. Performs auto increment of address pointer after the data is transferred to the Master. FIGURE 4-10: SPI Set Address Pointer Command - Bi-directional Mode FIGURE 4-11: SPI Write Data Command - Bi-directional Mode FIGURE 4-12: SPI Read Data Command - Bi-directional Mode Master SPDOUT SPI_MSIO Register Address SPI_CS# SPI_CLK Set Address Pointer – 7Dh ‘0’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Master SPDOUT SPI_MSIO Register Write Data SPI_CS# SPI_CLK Write Command – 7Eh ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ Master SPDOUT SPI_MSIO Master Drives Slave Drives Indeterminate Register Read Data SPI_CLK Read Command – 7Fh SPI_CS# ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’  2015 Microchip Technology Inc. DS00001623B-page 21 CAP1126 4.8 BC-Link Interface The BC-Link is a proprietary bus developed to allow communication between a host controller device to a companion device. This device uses this serial bus to read and write registers and for interrupt processing. The interface uses a data port concept, where the base interface has an address register, data register and a control register, defined in the 8051’s SFR space. Refer to documentation for the BC-Link compatible host controller for details on how to access the CAP1126 via the BCLink Interface. CAP1126 DS00001623B-page 22  2015 Microchip Technology Inc. 5.0 GENERAL DESCRIPTION The CAP1126 is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains six (6) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1126 also contains two (2) low side (or push-pull) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. Finally, the device contains a dedicated RESET pin to act as a soft reset by the system. The CAP1126 offers multiple power states. It operates at the lowest quiescent current during its Deep Sleep state. In the low power Standby state, it can monitor one or more channels and respond to communications normally. The device contains a wake pin (WAKE/SPI_MOSI) output to wake the system when a touch is detected in Standby and to wake the device from Deep Sleep. The device communicates with a host controller using the SPI bus, or via SMBus / I2C. The host controller may poll the device for updated information at any time or it may configure the device to flag an interrupt whenever a touch is detected on any sensor pad. A typical system diagram is shown in Figure 5-1.  2015 Microchip Technology Inc. DS00001623B-page 23 CAP1126 5.1 Power States The CAP1126 has three operating states depending on the status of the STBY and DSLEEP bits. When the device transitions between power states, previously detected touches (for inactive channels) are cleared and the status bits reset. 1. Fully Active - The device is fully active. It is monitoring all active capacitive sensor inputs and driving all LED channels as defined. 2. Standby - The device is in a lower power state. It will measure a programmable number of channels using the Standby Configuration controls (see Section 6.20 through Section 6.22). Interrupts will still be generated based on the active channels. The device will still respond to communications normally and can be returned to the Fully Active state of operation by clearing the STBY bit. FIGURE 5-1: System Diagram for CAP1126 CAP1126 CS6 SMDATA / BC_DATA / SPI_MSIO / SPI_MISO SMCLK / BC_CLK / SPI_CLK VDD Embedded Controller ALERT# / BC_IRQ# CS4 CS2 3.3V – 5V CS5 CS3 CS1 WAKE / SPI_MOSI RESET SPI_CS# ADDR_COMM LED1 LED2 3.3V – 5V Touch Button Touch Button Touch Button Touch Button Touch Button Touch Button CAP1126 DS00001623B-page 24  2015 Microchip Technology Inc. 3. Deep Sleep - The device is in its lowest power state. It is not monitoring any capacitive sensor inputs and not driving any LEDs. All LEDs will be driven to their programmed non-actuated state and no PWM operations will be done. While in Deep Sleep, the device can be awakened by SMBus or SPI communications targeting the device. This will not cause the DSLEEP to be cleared so the device will return to Deep Sleep once all communications have stopped. If the device is not communicating via the 4-wire SPI bus, then during this state of operation, if the WAKE/SPI_MOSI pin is driven high by an external source, the device will clear the DSLEEP bit and return to Fully Active. APPLICATION NOTE: In the Deep Sleep state, the LED output will be either high or low and will not be PWM’d at the min or max duty cycle. 5.2 RESET Pin The RESET pin is an active high reset that is driven from an external source. While it is asserted high, all the internal blocks will be held in reset including the communications protocol used. No capacitive touch sensor inputs will be sampled and the LEDs will not be driven. All configuration settings will be reset to default states and all readings will be cleared. The device will be held in Deep Sleep that can only be removed by driving the RESET pin low. This will cause the RESET status bit to be set to a logic ‘1’ and generate an interrupt. 5.3 WAKE/SPI_MOSI Pin Operation The WAKE / SPI_MOSI pin is a multi-function pin depending on device operation. When the device is configured to communicate using the 4-wire SPI bus, this pin is an input. However, when the CAP1126 is placed in Standby and is not communicating using the 4-wire SPI protocol, the WAKE pin is an active high output. In this condition, the device will assert the WAKE/SPI_MOSI pin when a touch is detected on one of its sampled sensor inputs. The pin will remain asserted until the INT bit has been cleared and then it will be de-asserted. When the CAP1126 is placed in Deep Sleep and it is not communicating using the 4-wire SPI protocol, the WAKE/SPI_- MOSI pin is monitored by the device as an input. If the WAKE/SPI_MOSI pin is driven high by an external source, the CAP1126will clear the DSLEEP bit causing the device to return to Fully Active. When the device is placed in Deep Sleep, this pin is a High-Z input and must have a pull-down resistor to GND for proper operation. 5.4 LED Drivers The CAP1126 contains two (2) LED drivers. Each LED driver can be linked to its respective capacitive touch sensor input or it can be controlled by the host. Each LED driver can be configured to operate in one of the following modes with either push-pull or open drain drive. 1. Direct - The LED is configured to be on or off when the corresponding input stimulus is on or off (or inverted). The brightness of the LED can be programmed from full off to full on (default). Additionally, the LED contains controls to individually configure ramping on, off, and turn-off delay. 2. Pulse 1 - The LED is configured to “Pulse” (transition ON-OFF-ON) a programmable number of times with programmable rate and min / max brightness. This behavior may be actuated when a press is detected or when a release is detected. 3. Pulse 2 - The LED is configured to “Pulse” while actuated and then “Pulse” a programmable number of times with programmable rate and min / max brightness when the sensor pad is released. 4. Breathe - The LED is configured to transition continuously ON-OFF-ON (i.e. to “Breathe”) with a programmable rate and min / max brightness. When an LED is not linked to a sensor and is actuated by the host, there’s an option to assert the ALERT# pin when the initiated LED behavior has completed. 5.4.1 LINKING LEDS TO CAPACITIVE TOUCH SENSOR INPUTS All LEDs can be linked to the corresponding capacitive touch sensor input so that when the sensor input detects a touch, the corresponding LED will be actuated at one of the programmed responses.  2015 Microchip Technology Inc. DS00001623B-page 25 CAP1126 5.5 Capacitive Touch Sensing The CAP1126 contains six (6) independent capacitive touch sensor inputs. Each sensor input has dynamic range to detect a change of capacitance due to a touch. Additionally, each sensor input can be configured to be automatically and routinely re-calibrated. 5.5.1 SENSING CYCLE Each capacitive touch sensor input has controls to be activated and included in the sensing cycle. When the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it finishes. The cycle polls through each active sensor input starting with CS1 and extending through CS6. As each capacitive touch sensor input is polled, its measurement is compared against a baseline “Not Touched” measurement. If the delta measurement is large enough, a touch is detected and an interrupt is generated. The sensing cycle time is programmable (see Section 6.10, "Averaging and Sampling Configuration Register"). 5.5.2 RECALIBRATING SENSOR INPUTS There are various options for recalibrating the capacitive touch sensor inputs. Recalibration re-sets the Base Count Registers (Section 6.24, "Sensor Input Base Count Registers") which contain the “not touched” values used for touch detection comparisons. APPLICATION NOTE: The device will recalibrate all sensor inputs that were disabled when it transitions from Standby. Likewise, the device will recalibrate all sensor inputs when waking out of Deep Sleep. 5.5.2.1 Manual Recalibration The Calibration Activate Registers (Section 6.11, "Calibration Activate Register") force recalibration of selected sensor inputs. When a bit is set, the corresponding capacitive touch sensor input will be recalibrated (both analog and digital). The bit is automatically cleared once the recalibration routine has finished. 5.5.2.2 Automatic Recalibration Each sensor input is regularly recalibrated at a programmable rate (see Section 6.17, "Recalibration Configuration Register"). By default, the recalibration routine stores the average 64 previous measurements and periodically updates the base “not touched” setting for the capacitive touch sensor input. 5.5.2.3 Negative Delta Count Recalibration It is possible that the device loses sensitivity to a touch. This may happen as a result of a noisy environment, an accidental recalibration during a touch, or other environmental changes. When this occurs, the base untouched sensor input may generate negative delta count values. The NEG_DELTA_CNT bits (see Section 6.17, "Recalibration Configuration Register") can be set to force a recalibration after a specified number of consecutive negative delta readings. 5.5.2.4 Delayed Recalibration It is possible that a “stuck button” occurs when something is placed on a button which causes a touch to be detected for a long period. By setting the MAX_DUR_EN bit (see Section 6.6, "Configuration Registers"), a recalibration can be forced when a touch is held on a button for longer than the duration specified in the MAX_DUR bits (see Section 6.8, "Sensor Input Configuration Register"). Note: During this recalibration routine, the sensor inputs will not detect a press for up to 200ms and the Sensor Base Count Register values will be invalid. In addition, any press on the corresponding sensor pads will invalidate the recalibration. Note: Automatic recalibration only works when the delta count is below the active sensor input threshold. It is disabled when a touch is detected. Note: During this recalibration, the device will not respond to touches. CAP1126 DS00001623B-page 26  2015 Microchip Technology Inc. 5.5.3 PROXIMITY DETECTION Each sensor input can be configured to detect changes in capacitance due to proximity of a touch. This circuitry detects the change of capacitance that is generated as an object approaches, but does not physically touch, the enabled sensor pad(s). When a sensor input is selected to perform proximity detection, it will be sampled from 1x to 128x per sampling cycle. The larger the number of samples that are taken, the greater the range of proximity detection is available at the cost of an increased overall sampling time. 5.5.4 MULTIPLE TOUCH PATTERN DETECTION The multiple touch pattern (MTP) detection circuitry can be used to detect lid closure or other similar events. An event can be flagged based on either a minimum number of sensor inputs or on specific sensor inputs simultaneously exceeding an MTP threshold or having their Noise Flag Status Register bits set. An interrupt can also be generated. During an MTP event, all touches are blocked (see Section 6.15, "Multiple Touch Pattern Configuration Register"). 5.5.5 LOW FREQUENCY NOISE DETECTION Each sensor input has an EMI noise detector that will sense if low frequency noise is injected onto the input with sufficient power to corrupt the readings. If this occurs, the device will reject the corrupted sample and set the corresponding bit in the Noise Status register to a logic ‘1’. 5.5.6 RF NOISE DETECTION Each sensor input contains an integrated RF noise detector. This block will detect injected RF noise on the CS pin. The detector threshold is dependent upon the noise frequency. If RF noise is detected on a CS line, that sample is removed and not compared against the threshold. 5.6 ALERT# Pin The ALERT# pin is an active low (or active high when configured) output that is driven when an interrupt event is detected. Whenever an interrupt is generated, the INT bit (see Section 6.1, "Main Control Register") is set. The ALERT# pin is cleared when the INT bit is cleared by the user. Additionally, when the INT bit is cleared by the user, status bits are only cleared if no touch is detected. 5.6.1 SENSOR INTERRUPT BEHAVIOR The sensor interrupts are generated in one of two ways: 1. An interrupt is generated when a touch is detected and, as a user selectable option, when a release is detected (by default - see Section 6.6). See Figure 5-3. 2. If the repeat rate is enabled then, so long as the touch is held, another interrupt will be generated based on the programmed repeat rate (see Figure 5-2). When the repeat rate is enabled, the device uses an additional control called MPRESS that determines whether a touch is flagged as a simple “touch” or a “press and hold”. The MPRESS[3:0] bits set a minimum press timer. When the button is touched, the timer begins. If the sensor pad is released before the minimum press timer expires, it is flagged as a touch and an interrupt is generated upon release. If the sensor input detects a touch for longer than this timer value, it is flagged as a “press and hold” event. So long as the touch is held, interrupts will be generated at the programmed repeat rate and upon release (if enabled). APPLICATION NOTE: Figure 5-2 and Figure 5-3 show default operation which is to generate an interrupt upon sensor pad release and an active-low ALERT# pin. APPLICATION NOTE: The host may need to poll the device twice to determine that a release has been detected. Note: Delayed recalibration only works when the delta count is above the active sensor input threshold. If enabled, it is invoked when a sensor pad touch is held longer than the MAX_DUR bit setting.  2015 Microchip Technology Inc. DS00001623B-page 27 CAP1126 FIGURE 5-2: Sensor Interrupt Behavior - Repeat Rate Enabled FIGURE 5-3: Sensor Interrupt Behavior - No Repeat Rate Enabled Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Min Press Setting (280ms) Interrupt on Touch Button Repeat Rate (175ms) Button Repeat Rate (175ms) Interrupt on Release (optional) ALERT# pin (active low) Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Interrupt on Touch Interrupt on Release (optional) ALERT# pin (active low) CAP1126 DS00001623B-page 28  2015 Microchip Technology Inc. 6.0 REGISTER DESCRIPTION The registers shown in Table 6-1 are accessible through the communications protocol. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Address R/W Register Name Function Default Value Page 00h R/W Main Control Controls general power states and power dissipation 00h Page 31 02h R General Status Stores general status bits 00h Page 32 03h R Sensor Input Status Returns the state of the sampled capacitive touch sensor inputs 00h Page 32 04h R LED Status Stores status bits for LEDs 00h Page 32 0Ah R Noise Flag Status Stores the noise flags for sensor inputs 00h Page 33 10h R Sensor Input 1 Delta Count Stores the delta count for CS1 00h Page 33 11h R Sensor Input 2 Delta Count Stores the delta count for CS2 00h Page 33 12h R Sensor Input 3 Delta Count Stores the delta count for CS3 00h Page 33 13h R Sensor Input 4 Delta Count Stores the delta count for CS4 00h Page 33 14h R Sensor Input 5 Delta Count Stores the delta count for CS5 00h Page 33 15h R Sensor Input 6 Delta Count Stores the delta count for CS6 00h Page 33 1Fh R/W Sensitivity Control Controls the sensitivity of the threshold and delta counts and data scaling of the base counts 2Fh Page 33 20h R/W Configuration Controls general functionality 20h Page 35 21h R/W Sensor Input Enable Controls whether the capacitive touch sensor inputs are sampled 3Fh Page 36 22h R/W Sensor Input Configuration Controls max duration and auto-repeat delay for sensor inputs operating in the full power state A4h Page 36 23h R/W Sensor Input Configuration 2 Controls the MPRESS controls for all sensor inputs 07h Page 38 24h R/W Averaging and Sampling Config Controls averaging and sampling window 39h Page 38 26h R/W Calibration Activate Forces re-calibration for capacitive touch sensor inputs 00h Page 39 27h R/W Interrupt Enable Enables Interrupts associated with capacitive touch sensor inputs 3Fh Page 40 28h R/W Repeat Rate Enable Enables repeat rate for all sensor inputs 3Fh Page 40 2Ah R/W Multiple Touch Configuration Determines the number of simultaneous touches to flag a multiple touch condition 80h Page 41 2Bh R/W Multiple Touch Pattern Configuration Determines the multiple touch pattern (MTP) configuration 00h Page 41  2015 Microchip Technology Inc. DS00001623B-page 29 CAP1126 2Dh R/W Multiple Touch Pattern Determines the pattern or number of sensor inputs used by the MTP circuitry 3Fh Page 42 2Fh R/W Recalibration Configuration Determines re-calibration timing and sampling window 8Ah Page 43 30h R/W Sensor Input 1 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 1 40h Page 44 31h R/W Sensor Input 2 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 2 40h Page 44 32h R/W Sensor Input 3 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 3 40h Page 44 33h R/W Sensor Input 4 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 4 40h Page 44 34h R/W Sensor Input 5 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 5 40h Page 44 35h R/W Sensor Input 6 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 6 40h Page 44 38h R/W Sensor Input Noise Threshold Stores controls for selecting the noise threshold for all sensor inputs 01h Page 44 Standby Configuration Registers 40h R/W Standby Channel Controls which sensor inputs are enabled while in standby 00h Page 45 41h R/W Standby Configuration Controls averaging and cycle time while in standby 39h Page 45 42h R/W Standby Sensitivity Controls sensitivity settings used while in standby 02h Page 47 43h R/W Standby Threshold Stores the touch detection threshold for active sensor inputs in standby 40h Page 47 44h R/W Configuration 2 Stores additional configuration controls for the device 40h Page 35 Base Count Registers 50h R Sensor Input 1 Base Count Stores the reference count value for sensor input 1 C8h Page 47 51h R Sensor Input 2 Base Count Stores the reference count value for sensor input 2 C8h Page 47 52h R Sensor Input 3 Base Count Stores the reference count value for sensor input 3 C8h Page 47 53h R Sensor Input 4 Base Count Stores the reference count value for sensor input 4 C8h Page 47 54h R Sensor Input 5 Base Count Stores the reference count value for sensor input 5 C8h Page 47 55h R Sensor Input 6 Base Count Stores the reference count value for sensor input 6 C8h Page 47 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1126 DS00001623B-page 30  2015 Microchip Technology Inc. LED Controls 71h R/W LED Output Type Controls the output type for the LED outputs 00h Page 48 72h R/W Sensor Input LED Linking Controls linking of sensor inputs to LED channels 00h Page 48 73h R/W LED Polarity Controls the output polarity of LEDs 00h Page 49 74h R/W LED Output Control Controls the output state of the LEDs 00h Page 50 77h R/W Linked LED Transition Control Controls the transition when LEDs are linked to CS channels 00h Page 51 79h R/W LED Mirror Control Controls the mirroring of duty cycles for the LEDs 00h Page 51 81h R/W LED Behavior 1 Controls the behavior and response of LEDs 1 - 2 00h Page 51 84h R/W LED Pulse 1 Period Controls the period of each breathe during a pulse 20h Page 53 85h R/W LED Pulse 2 Period Controls the period of the breathing during breathe and pulse operation 14h Page 55 86h R/W LED Breathe Period Controls the period of an LED breathe operation 5Dh Page 56 88h R/W LED Config Controls LED configuration 04h Page 56 90h R/W LED Pulse 1 Duty Cycle Determines the min and max duty cycle for the pulse operation F0h Page 57 91h R/W LED Pulse 2 Duty Cycle Determines the min and max duty cycle for breathe and pulse operation F0h Page 57 92h R/W LED Breathe Duty Cycle Determines the min and max duty cycle for the breathe operation F0h Page 57 93h R/W LED Direct Duty Cycle Determines the min and max duty cycle for Direct mode LED operation F0h Page 57 94h R/W LED Direct Ramp Rates Determines the rising and falling edge ramp rates of the LEDs 00h Page 58 95h R/W LED Off Delay Determines the off delay for all LED behaviors 00h Page 58 B1h R Sensor Input 1 Calibration Stores the upper 8-bit calibration value for sensor input 1 00h Page 61 B2h R Sensor Input 2 Calibration Stores the upper 8-bit calibration value for sensor input 2 00h Page 61 B3h R Sensor Input 3 Calibration Stores the upper 8-bit calibration value for sensor input 3 00h Page 61 B4h R Sensor Input 4 Calibration Stores the upper 8-bit calibration value for sensor input 4 00h Page 61 B5h R Sensor Input 5 Calibration Stores the upper 8-bit calibration value for sensor input 5 00h Page 61 B6h R Sensor Input 6 Calibration Stores the upper 8-bit calibration value for sensor input 6 00h Page 61 B9h R Sensor Input Calibration LSB 1 Stores the 2 LSBs of the calibration value for sensor inputs 1 - 4 00h Page 61 BAh R Sensor Input Calibration LSB 2 Stores the 2 LSBs of the calibration value for sensor inputs 5 - 6 00h Page 61 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page  2015 Microchip Technology Inc. DS00001623B-page 31 CAP1126 During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. When a bit is “set”, this means that the user writes a logic ‘1’ to it. When a bit is “cleared”, this means that the user writes a logic ‘0’ to it. 6.1 Main Control Register The Main Control register controls the primary power state of the device. Bits 7 - 6 - GAIN[1:0] - Controls the gain used by the capacitive touch sensing circuitry. As the gain is increased, the effective sensitivity is likewise increased as a smaller delta capacitance is required to generate the same delta count values. The sensitivity settings may need to be adjusted along with the gain settings such that data overflow does not occur. APPLICATION NOTE: The gain settings apply to both Standby and Active states. Bit 5 - STBY - Enables Standby. • ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - Capacitive touch sensor input scanning is limited to the sensor inputs set in the Standby Channel register (see Section 6.20). The status registers will not be cleared until read. LEDs that are linked to capacitive touch sensor inputs will remain linked and active. Sensor inputs that are no longer sampled will flag a release and then remain in a non-touched state. LEDs that are manually controlled will be unaffected. • Bit 4 - DSLEEP - Enables Deep Sleep by deactivating all functions. This bit will be cleared when the WAKE pin is driven high. ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - All sensor input scanning is disabled. All LEDs are driven to their programmed non-actuated state and no PWM operations will be done. The status registers are automatically cleared and the INT bit is cleared. Bit 0 - INT - Indicates that there is an interrupt. When this bit is set, it asserts the ALERT# pin. If a channel detects a touch and its associated interrupt enable bit is not set to a logic ‘1’, no action is taken. FDh R Product ID Stores a fixed value that identifies each product 53h Page 62 FEh R Manufacturer ID Stores a fixed value that identifies Microchip 5Dh Page 62 FFh R Revision Stores a fixed value that represents the revision number 83h Page 62 TABLE 6-2: MAIN CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 00h R/W Main Control GAIN[1:0] STBY DSLEEP - - - INT 00h TABLE 6-3: GAIN BIT DECODE GAIN[1:0] Capacitive Touch Sensor Gain 1 0 0 0 1 01 2 10 4 11 8 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1126 DS00001623B-page 32  2015 Microchip Technology Inc. This bit is cleared by writing a logic ‘0’ to it. When this bit is cleared, the ALERT# pin will be deasserted and all status registers will be cleared if the condition has been removed. If the WAKE/SPI_MOSI pin is asserted as a result of a touch detected while in Standby, it will likewise be deasserted when this bit is cleared. Note that the WAKE / SPI_MOSI pin is not driven when communicating via the 4-wire SPI protocol. • ‘0’ - No interrupt pending. • ‘1’ - A touch has been detected on one or more channels and the interrupt has been asserted. 6.2 Status Registers All status bits are cleared when the device enters the Deep Sleep (DSLEEP = ‘1’ - see Section 6.1). 6.2.1 GENERAL STATUS - 02H Bit 4 - LED - Indicates that one or more LEDs have finished their programmed activity. This bit is set if any bit in the LED Status register is set. Bit 3 - RESET - Indicates that the device has come out of reset. This bit is set when the device exits a POR state or when the RESET pin has been deasserted and qualified via the RESET pin filter (see Section 5.2). This bit will cause the INT bit to be set and is cleared when the INT bit is cleared. Bit 2 - MULT - Indicates that the device is blocking detected touches due to the Multiple Touch detection circuitry (see Section 6.14). This bit will not cause the INT bit to be set and hence will not cause an interrupt. Bit 1 - MTP - Indicates that the device has detected a number of sensor inputs that exceed the MTP threshold either via the pattern recognition or via the number of sensor inputs (see Section 6.15). This bit will cause the INT bit to be set if the MTP_ALERT bit is also set. This bit will not be cleared until the condition that caused it to be set has been removed. Bit 0 - TOUCH - Indicates that a touch was detected. This bit is set if any bit in the Sensor Input Status register is set. 6.2.2 SENSOR INPUT STATUS - 03H The Sensor Input Status Register stores status bits that indicate a touch has been detected. A value of ‘0’ in any bit indicates that no touch has been detected. A value of ‘1’ in any bit indicates that a touch has been detected. All bits are cleared when the INT bit is cleared and if a touch on the respective capacitive touch sensor input is no longer present. If a touch is still detected, the bits will not be cleared (but this will not cause the interrupt to be asserted - see Section 6.6). Bit 5 - CS6 - Indicates that a touch was detected on Sensor Input 6. Bit 4 - CS5 - Indicates that a touch was detected on Sensor Input 5. Bit 3 - CS4 - Indicates that a touch was detected on Sensor Input 4. Bit 2 - CS3 - Indicates that a touch was detected on Sensor Input 3. Bit 1 - CS2 - Indicates that a touch was detected on Sensor Input 2. This sensor input can be linked to LED2. Bit 0 - CS1 - Indicates that a touch was detected on Sensor Input 1. This sensor input can be linked to LED1. 6.2.3 LED STATUS - 04H The LED Status Registers indicate when an LED has completed its configured behavior (see Section 6.31, "LED Behavior Register") after being actuated by the host (see Section 6.28, "LED Output Control Register"). These bits are ignored when the LED is linked to a capacitive sensor input. All LED Status bits are cleared when the INT bit is cleared. Bit 1 - LED2_DN - Indicates that LED2 has finished its behavior after being actuated by the host. Bit 0 - LED1_DN - Indicates that LED1 has finished its behavior after being actuated by the host. TABLE 6-4: STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 02h R General Status - - - LED RESET MULT MTP TOUCH 00h 03h R Sensor Input Status - - CS6 CS5 CS4 CS3 CS2 CS1 00h 04h R LED Status - - - - - - LED2_ DN LED1_ DN 00h  2015 Microchip Technology Inc. DS00001623B-page 33 CAP1126 6.3 Noise Flag Status Registers The Noise Flag Status registers store status bits that are generated from the analog block if the detected noise is above the operating region of the analog detector or the RF noise detector. These bits indicate that the most recently received data from the sensor input is invalid and should not be used for touch detection. So long as the bit is set for a particular channel, the delta count value is reset to 00h and thus no touch is detected. These bits are not sticky and will be cleared automatically if the analog block does not report a noise error. APPLICATION NOTE: If the MTP detection circuitry is enabled, these bits count as sensor inputs above the MTP threshold (see Section 5.5.4, "Multiple Touch Pattern Detection") even if the corresponding delta count is not. If the corresponding delta count also exceeds the MTP threshold, it is not counted twice. APPLICATION NOTE: Regardless of the state of the Noise Status bits, if low frequency noise is detected on a sensor input, that sample will be discarded unless the DIS_ANA_NOISE bit is set. As well, if RF noise is detected on a sensor input, that sample will be discarded unless the DIS_RF_NOISE bit is set. 6.4 Sensor Input Delta Count Registers The Sensor Input Delta Count registers store the delta count that is compared against the threshold used to determine if a touch has been detected. The count value represents a change in input due to the capacitance associated with a touch on one of the sensor inputs and is referenced to a calibrated base “Not Touched” count value. The delta is an instantaneous change and is updated once per sensor input per sensing cycle (see Section 5.5.1, "Sensing Cycle"). The value presented is a standard 2’s complement number. In addition, the value is capped at a value of 7Fh. A reading of 7Fh indicates that the sensitivity settings are too high and should be adjusted accordingly (see Section 6.5). The value is also capped at a negative value of 80h for negative delta counts which may result upon a release. 6.5 Sensitivity Control Register TABLE 6-5: NOISE FLAG STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 0Ah R Noise Flag Status - - CS6_ NOISE CS5_ NOISE CS4_ NOISE CS3_ NOISE CS2_ NOISE CS1_ NOISE 00h TABLE 6-6: SENSOR INPUT DELTA COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 10h R Sensor Input 1 Delta Count Sign 64 32 16 8 4 2 1 00h 11h R Sensor Input 2 Delta Count Sign 64 32 16 8 4 2 1 00h 12h R Sensor Input 3 Delta Count Sign 64 32 16 8 4 2 1 00h 13h R Sensor Input 4 Delta Count Sign 64 32 16 8 4 2 1 00h 14h R Sensor Input 5 Delta Count Sign 64 32 16 8 4 2 1 00h 15h R Sensor Input 6 Delta Count Sign 64 32 16 8 4 2 1 00h TABLE 6-7: SENSITIVITY CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 1Fh R/W Sensitivity Control - DELTA_SENSE[2:0] BASE_SHIFT[3:0] 2Fh CAP1126 DS00001623B-page 34  2015 Microchip Technology Inc. The Sensitivity Control register controls the sensitivity of a touch detection. Bits 6-4 DELTA_SENSE[2:0] - Controls the sensitivity of a touch detection. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta capacitance corresponding to a “lighter” touch. These settings are more sensitive to noise, however, and a noisy environment may flag more false touches with higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely, a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). Bits 3 - 0 - BASE_SHIFT[3:0] - Controls the scaling and data presentation of the Base Count registers. The higher the value of these bits, the larger the range and the lower the resolution of the data presented. The scale factor represents the multiplier to the bit-weighting presented in these register descriptions. APPLICATION NOTE: The BASE_SHIFT[3:0] bits normally do not need to be updated. These settings will not affect touch detection or sensitivity. These bits are sometimes helpful in analyzing the Cap Sensing board performance and stability. TABLE 6-8: DELTA_SENSE BIT DECODE DELTA_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-9: BASE_SHIFT BIT DECODE BASE_SHIFT[3:0] Data Scaling Factor 32 1 0 0 0 0 0 1x 0 0 0 1 2x 0 0 1 0 4x 0 0 1 1 8x 0 1 0 0 16x 0 1 0 1 32x 0 1 1 0 64x 0 1 1 1 128x 1 0 0 0 256x All others 256x (default = 1111b)  2015 Microchip Technology Inc. DS00001623B-page 35 CAP1126 6.6 Configuration Registers The Configuration registers control general global functionality that affects the entire device. 6.6.1 CONFIGURATION - 20H Bit 7 - TIMEOUT - Enables the timeout and idle functionality of the SMBus protocol. • ‘0’ (default for Functional Revision C) - The SMBus timeout and idle functionality are disabled. The SMBus interface will not time out if the clock line is held low. Likewise, it will not reset if both the data and clock lines are held high for longer than 200us. This is used for I2C compliance. • ‘1’ (default for Functional Revision B) - The SMBus timeout and idle functionality are enabled. The SMBus interface will time out if the clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock lines are held high for longer than 200us. Bit 6 - WAKE_CFG - Configures the operation of the WAKE pin. • ‘0’ (default) - The WAKE pin is not asserted when a touch is detected while the device is in Standby. It will still be used to wake the device from Deep Sleep when driven high. • ‘1’ - The WAKE pin will be asserted high when a touch is detected while the device is in Standby. It will also be used to wake the device from Deep Sleep when driven high. Bit 5 - DIS_DIG_NOISE - Determines whether the digital noise threshold (see Section 6.19, "Sensor Input Noise Threshold Register") is used by the device. Setting this bit disables the feature. • ‘0’ - The digital noise threshold is used. If a delta count value exceeds the noise threshold but does not exceed the touch threshold, the sample is discarded and not used for the automatic re-calibration routine. • ‘1’ (default) - The noise threshold is disabled. Any delta count that is less than the touch threshold is used for the automatic re-calibration routine. Bit 4 - DIS_ANA_NOISE - Determines whether the analog noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If low frequency noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if low frequency noise is detected. Bit 3 - MAX_DUR_EN - Determines whether the maximum duration recalibration is enabled. • ‘0’ (default) - The maximum duration recalibration functionality is disabled. A touch may be held indefinitely and no re-calibration will be performed on any sensor input. • ‘1’ - The maximum duration recalibration functionality is enabled. If a touch is held for longer than the MAX_DUR bit settings, then the re-calibration routine will be restarted (see Section 6.8). 6.6.2 CONFIGURATION 2 - 44H Bit 7 - INV_LINK_TRAN - Determines the behavior of the Linked LED Transition controls (see Section 6.29). • ‘0’ (default) - The Linked LED Transition controls set the min duty cycle equal to the max duty cycle. • ‘1’ - The Linked LED Transition controls will invert the touch signal. For example, a touch signal will be inverted to a non-touched signal. Bit 6 - ALT_POL - Determines the ALERT# pin polarity and behavior. • ‘0’ - The ALERT# pin is active high and push-pull. • ‘1’ (default) - The ALERT# pin is active low and open drain. TABLE 6-10: CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 20h R/W Configuration TIMEOUT WAKE_ CFG DIS_ DIG_ NOISE DIS_ ANA_ NOISE MAX_ DUR_EN - -- A0h (Rev B) 20h (rev C) 44h R/W Configuration 2 INV_LINK_ TRAN ALT_ POL BLK_PWR_ CTRL BLK_POL_ MIR SHOW_ RF_ NOISE DIS_ RF_ NOISE - INT_ REL_n 40h CAP1126 DS00001623B-page 36  2015 Microchip Technology Inc. Bit 5 - BLK_PWR_CTRL - Determines whether the device will reduce power consumption while waiting between conversion time completion and the end of the polling cycle. • ‘0’ (default) - The device will always power down as much as possible during the time between the end of the last conversion and the end of the polling cycle. • ‘1’ - The device will not power down the Cap Sensor during the time between the end of the last conversion and the end of the polling cycle. Bit 4 - BLK_POL_MIR - Determines whether the LED Mirror Control register bits are linked to the LED Polarity bits. Setting this bit blocks the normal behavior which is to automatically set and clear the LED Mirror Control bits when the LED Polarity bits are set or cleared. • ‘0’ (default) - When the LED Polarity controls are set, the corresponding LED Mirror control is automatically set. Likewise, when the LED Polarity controls are cleared, the corresponding LED Mirror control is also cleared. • ‘1’ - When the LED Polarity controls are set, the corresponding LED Mirror control is not automatically set. Bit 3 - SHOW_RF_NOISE - Determines whether the Noise Status bits will show RF Noise as the only input source. • ‘0’ (default) - The Noise Status registers will show both RF noise and low frequency EMI noise if either is detected on a capacitive touch sensor input. • ‘1’ - The Noise Status registers will only show RF noise if it is detected on a capacitive touch sensor input. EMI noise will still be detected and touches will be blocked normally; however, the status bits will not be updated. Bit 2 - DIS_RF_NOISE - Determines whether the RF noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If RF noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if RF noise is detected. Bit 0 - INT_REL_n - Controls the interrupt behavior when a release is detected on a button. • ‘0’ (default) - An interrupt is generated when a press is detected and again when a release is detected and at the repeat rate (if enabled - see Section 6.13). • ‘1’ - An interrupt is generated when a press is detected and at the repeat rate but not when a release is detected. 6.7 Sensor Input Enable Registers The Sensor Input Enable registers determine whether a capacitive touch sensor input is included in the sampling cycle. The length of the sampling cycle is not affected by the number of sensor inputs measured. Bit 5 - CS6_EN - Enables the CS6 input to be included during the sampling cycle. • ‘0’ - The CS6 input is not included in the sampling cycle. • ‘1’ (default) - The CS6 input is included in the sampling cycle. Bit 4 - CS5_EN - Enables the CS5 input to be included during the sampling cycle. Bit 3 - CS4_EN - Enables the CS4 input to be included during the sampling cycle. Bit 2 - CS3_EN - Enables the CS3 input to be included during the sampling cycle. Bit 1 - CS2_EN - Enables the CS2 input to be included during the sampling cycle. Bit 0 - CS1_EN - Enables the CS1 input to be included during the sampling cycle. 6.8 Sensor Input Configuration Register TABLE 6-11: SENSOR INPUT ENABLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 21h R/W Sensor Input Enable - - CS6_EN CS5_EN CS4_EN CS3_EN CS2_EN CS1_EN 3Fh TABLE 6-12: SENSOR INPUT CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 22h R/W Sensor Input Configuration MAX_DUR[3:0] RPT_RATE[3:0] A4h  2015 Microchip Technology Inc. DS00001623B-page 37 CAP1126 The Sensor Input Configuration Register controls timings associated with the Capacitive sensor inputs 1 - 6. Bits 7 - 4 - MAX_DUR[3:0] - (default 1010b) - Determines the maximum time that a sensor pad is allowed to be touched until the capacitive touch sensor input is recalibrated, as shown in Table 6-13. Bits 3 - 0 - RPT_RATE[3:0] - (default 0100b) Determines the time duration between interrupt assertions when auto repeat is enabled. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-14. TABLE 6-13: MAX_DUR BIT DECODE MAX_DUR[3:0] Time Before Recalibration 32 1 0 0 0 0 0 560ms 0 0 0 1 840ms 0 0 1 0 1120ms 0 0 1 1 1400ms 0 1 0 0 1680ms 0 1 0 1 2240ms 0 1 1 0 2800ms 1 1 1 3360ms 1 0 0 0 3920ms 1 0 0 1 4480ms 1 0 1 0 5600ms (default) 1 0 1 1 6720ms 1 1 0 0 7840ms 1 1 0 1 8906ms 1 1 1 0 10080ms 1 1 1 1 11200ms TABLE 6-14: RPT_RATE BIT DECODE RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms (default) 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms CAP1126 DS00001623B-page 38  2015 Microchip Technology Inc. 6.9 Sensor Input Configuration 2 Register Bits 3 - 0 - M_PRESS[3:0] - (default 0111b) - Determines the minimum amount of time that sensor inputs configured to use auto repeat must detect a sensor pad touch to detect a “press and hold” event. If the sensor input detects a touch for longer than the M_PRESS[3:0] settings, a “press and hold” event is detected. If a sensor input detects a touch for less than or equal to the M_PRESS[3:0] settings, a touch event is detected. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-16. 6.10 Averaging and Sampling Configuration Register The Averaging and Sampling Configuration register controls the number of samples taken and the total sensor input cycle time for all active sensor inputs while the device is functioning in Active state. Bits 6 - 4 - AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-18. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. For example, if CS1, CS2, and CS3 are sampled during the sensor cycle, and the AVG[2:0] bits are set to take 4 samples per channel, then the full sensor cycle will be: CS1, CS1, CS1, CS1, CS2, CS2, CS2, CS2, CS3, CS3, CS3, CS3. TABLE 6-15: SENSOR INPUT CONFIGURATION 2 REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 23h R/W Sensor Input Configuration 2 - - - - M_PRESS[3:0] 07h TABLE 6-16: M_PRESS BIT DECODE M_PRESS[3:0] M_PRESS SETTINGS 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms (default) 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-17: AVERAGING AND SAMPLING CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 24h R/W Averaging and Sampling Config AVG[2:0] SAMP_TIME[1:0] CYCLE_TIME [1:0] 39h  2015 Microchip Technology Inc. DS00001623B-page 39 CAP1126 Bits 3 - 2 - SAMP_TIME[1:0] - Determines the time to take a single sample as shown in Table 6-19. Bits 1 - 0 - CYCLE_TIME[1:0] - Determines the overall cycle time for all measured channels during normal operation as shown in Table 6-20. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, then the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.11 Calibration Activate Register The Calibration Activate register forces the respective sensor inputs to be re-calibrated affecting both the analog and digital blocks. During the re-calibration routine, the sensor inputs will not detect a press for up to 600ms and the Sensor Input Base Count register values will be invalid. During this time, any press on the corresponding sensor pads will invalidate the re-calibration. When finished, the CALX[9:0] bits will be updated (see Section 6.39). TABLE 6-18: AVG BIT DECODE AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-19: SAMP_TIME BIT DECODE SAMP_TIME[1:0] Sample Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-20: CYCLE_TIME BIT DECODE CYCLE_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-21: CALIBRATION ACTIVATE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 26h R/W Calibration Activate - - CS6_ CAL CS5_ CAL CS4_ CAL CS3_ CAL CS2_ CAL CS1_ CAL 00h CAP1126 DS00001623B-page 40  2015 Microchip Technology Inc. When the corresponding bit is set, the device will perform the calibration and the bit will be automatically cleared once the re-calibration routine has finished. Bit 5 - CS6_CAL - When set, the CS6 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 4 - CS5_CAL - When set, the CS5 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 3 - CS4_CAL - When set, the CS4 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 2 - CS3_CAL - When set, the CS3 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 1 - CS2_CAL - When set, the CS2 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 0 - CS1_CAL - When set, the CS1 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. 6.12 Interrupt Enable Register The Interrupt Enable register determines whether a sensor pad touch or release (if enabled) causes the interrupt pin to be asserted. Bit 5 - CS6_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS6 (associated with the CS6 status bit). • ‘0’ - The interrupt pin will not be asserted if a touch is detected on CS6 (associated with the CS6 status bit). • ‘1’ (default) - The interrupt pin will be asserted if a touch is detected on CS6 (associated with the CS6 status bit). Bit 4 - CS5_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS5 (associated with the CS5 status bit). Bit 3 - CS4_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS4 (associated with the CS4 status bit). Bit 2 - CS3_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS3 (associated with the CS3 status bit). Bit 1 - CS2_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS2 (associated with the CS2 status bit). Bit 0 - CS1_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS1 (associated with the CS1 status bit). 6.13 Repeat Rate Enable Register The Repeat Rate Enable register enables the repeat rate of the sensor inputs as described in Section 5.6.1. Bit 5 - CS6_RPT_EN - Enables the repeat rate for capacitive touch sensor input 6. • ‘0’ - The repeat rate for CS6 is disabled. It will only generate an interrupt when a touch is detected and when a release is detected no matter how long the touch is held for. • ‘1’ (default) - The repeat rate for CS6 is enabled. In the case of a “touch” event, it will generate an interrupt when a TABLE 6-22: INTERRUPT ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 27h R/W Interrupt Enable - - CS6_ INT_EN CS5_ INT_EN CS4_ INT_EN CS3_ INT_EN CS2_ INT_EN CS1_ INT_EN 3Fh TABLE 6-23: REPEAT RATE ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 28h R/W Repeat Rate Enable - - CS6_ RPT_EN CS5_ RPT_EN CS4_ RPT_EN CS3_ RPT_EN CS2_ RPT_EN CS1_ RPT_EN 3Fh  2015 Microchip Technology Inc. DS00001623B-page 41 CAP1126 touch is detected and a release is detected (as determined by the INT_REL_n bit - see Section 6.6). In the case of a “press and hold” event, it will generate an interrupt when a touch is detected and at the repeat rate so long as the touch is held. Bit 4 - CS5_RPT_EN - Enables the repeat rate for capacitive touch sensor input 5. Bit 3 - CS4_RPT_EN - Enables the repeat rate for capacitive touch sensor input 4. Bit 2 - CS3_RPT_EN - Enables the repeat rate for capacitive touch sensor input 3. Bit 1 - CS2_RPT_EN - Enables the repeat rate for capacitive touch sensor input 2. Bit 0 - CS1_RPT_EN - Enables the repeat rate for capacitive touch sensor input 1. 6.14 Multiple Touch Configuration Register The Multiple Touch Configuration register controls the settings for the multiple touch detection circuitry. These settings determine the number of simultaneous buttons that may be pressed before additional buttons are blocked and the MULT status bit is set. Bit 7 - MULT_BLK_EN - Enables the multiple button blocking circuitry. • ‘0’ - The multiple touch circuitry is disabled. The device will not block multiple touches. • ‘1’ (default) - The multiple touch circuitry is enabled. The device will flag the number of touches equal to programmed multiple touch threshold and block all others. It will remember which sensor inputs are valid and block all others until that sensor pad has been released. Once a sensor pad has been released, the N detected touches (determined via the cycle order of CS1 - CS6) will be flagged and all others blocked. Bits 3 - 2 - B_MULT_T[1:0] - Determines the number of simultaneous touches on all sensor pads before a Multiple Touch Event is detected and sensor inputs are blocked. The bit decode is given by Table 6-25. 6.15 Multiple Touch Pattern Configuration Register The Multiple Touch Pattern Configuration register controls the settings for the multiple touch pattern detection circuitry. This circuitry works like the multiple touch detection circuitry with the following differences: 1. The detection threshold is a percentage of the touch detection threshold as defined by the MTP_TH[1:0] bits whereas the multiple touch circuitry uses the touch detection threshold. 2. The MTP detection circuitry either will detect a specific pattern of sensor inputs as determined by the Multiple Touch Pattern register settings or it will use the Multiple Touch Pattern register settings to determine a minimum number of sensor inputs that will cause the MTP circuitry to flag an event. When using pattern recognition mode, TABLE 6-24: MULTIPLE TOUCH CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Ah R/W Multiple Touch Config MULT_ BLK_ EN - - - B_MULT_T[1:0] - - 80h TABLE 6-25: B_MULT_T BIT DECODE B_MULT_T[1:0] Number of Simultaneous Touches 1 0 0 0 1 (default) 01 2 10 3 11 4 TABLE 6-26: MULTIPLE TOUCH PATTERN CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Bh R/W Multiple Touch Pattern Config MTP_ EN - - MTP_TH[1:0] COMP_ PTRN MTP_ ALERT 00h CAP1126 DS00001623B-page 42  2015 Microchip Technology Inc. if all of the sensor inputs set by the Multiple Touch Pattern register have a delta count greater than the MTP threshold or have their corresponding Noise Flag Status bits set, the MTP bit will be set. When using the absolute number mode, if the number of sensor inputs with thresholds above the MTP threshold or with Noise Flag Status bits set is equal to or greater than this number, the MTP bit will be set. 3. When an MTP event occurs, all touches are blocked and an interrupt is generated. 4. All sensor inputs will remain blocked so long as the requisite number of sensor inputs are above the MTP threshold or have Noise Flag Status bits set. Once this condition is removed, touch detection will be restored. Note that the MTP status bit is only cleared by writing a ‘0’ to the INT bit once the condition has been removed. Bit 7 - MTP_EN - Enables the multiple touch pattern detection circuitry. • ‘0’ (default) - The MTP detection circuitry is disabled. • ‘1’ - The MTP detection circuitry is enabled. Bits 3-2 - MTP_TH[1:0] - Determine the MTP threshold, as shown in Table 6-27. This threshold is a percentage of sensor input threshold (see Section 6.18, "Sensor Input Threshold Registers") when the device is in the Fully Active state or of the standby threshold (see Section 6.23, "Standby Threshold Register") when the device is in the Standby state. Bit 1 - COMP_PTRN - Determines whether the MTP detection circuitry will use the Multiple Touch Pattern register as a specific pattern of sensor inputs or as an absolute number of sensor inputs. • ‘0’ (default) - The MTP detection circuitry will use the Multiple Touch Pattern register bit settings as an absolute minimum number of sensor inputs that must be above the threshold or have Noise Flag Status bits set. The number will be equal to the number of bits set in the register. • ‘1’ - The MTP detection circuitry will use pattern recognition. Each bit set in the Multiple Touch Pattern register indicates a specific sensor input that must have a delta count greater than the MTP threshold or have a Noise Flag Status bit set. If the criteria are met, the MTP status bit will be set. Bit 0 - MTP_ALERT - Enables an interrupt if an MTP event occurs. In either condition, the MTP status bit will be set. • ‘0’ (default) - If an MTP event occurs, the ALERT# pin is not asserted. • ‘1’ - If an MTP event occurs, the ALERT# pin will be asserted. 6.16 Multiple Touch Pattern Register The Multiple Touch Pattern register acts as a pattern to identify an expected sensor input profile for diagnostics or other significant events. There are two methods for how the Multiple Touch Pattern register is used: as specific sensor inputs or number of sensor input that must exceed the MTP threshold or have Noise Flag Status bits set. Which method is used is based on the COMP_PTRN bit (see Section 6.15). The methods are described below. 1. Specific Sensor Inputs: If, during a single polling cycle, the specific sensor inputs above the MTP threshold or with Noise Flag Status bits set match those bits set in the Multiple Touch Pattern register, an MTP event is flagged. 2. Number of Sensor Inputs: If, during a single polling cycle, the number of sensor inputs with a delta count above the MTP threshold or with Noise Flag Status bits set is equal to or greater than the number of pattern bits set, an MTP event is flagged. TABLE 6-27: MTP_TH BIT DECODE MTP_TH[1:0] Threshold Divide Setting 1 0 0 0 12.5% (default) 0 1 25% 1 0 37.5% 1 1 100% TABLE 6-28: MULTIPLE TOUCH PATTERN REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Dh R/W Multiple Touch Pattern - - CS6_ PTRN CS5_ PTRN CS4_ PTRN CS3_ PTRN CS2_ PTRN CS1_ PTRN 3Fh  2015 Microchip Technology Inc. DS00001623B-page 43 CAP1126 Bit 5 - CS6_PTRN - Determines whether CS6 is considered as part of the Multiple Touch Pattern. • ‘0’ - CS6 is not considered a part of the pattern. • ‘1’ - CS6 is considered a part of the pattern or the absolute number of sensor inputs that must have a delta count greater than the MTP threshold or have the Noise Flag Status bit set is increased by 1. Bit 4 - CS5_PTRN - Determines whether CS5 is considered as part of the Multiple Touch Pattern. Bit 3 - CS4_PTRN - Determines whether CS4 is considered as part of the Multiple Touch Pattern. Bit 2 - CS3_PTRN - Determines whether CS3 is considered as part of the Multiple Touch Pattern. Bit 1 - CS2_PTRN - Determines whether CS2 is considered as part of the Multiple Touch Pattern. Bit 0 - CS1_PTRN - Determines whether CS1 is considered as part of the Multiple Touch Pattern. 6.17 Recalibration Configuration Register The Recalibration Configuration register controls the automatic re-calibration routine settings as well as advanced controls to program the Sensor Input Threshold register settings. Bit 7 - BUT_LD_TH - Enables setting all Sensor Input Threshold registers by writing to the Sensor Input 1 Threshold register. • ‘0’ - Each Sensor Input X Threshold register is updated individually. • ‘1’ (default) - Writing the Sensor Input 1 Threshold register will automatically overwrite the Sensor Input Threshold registers for all sensor inputs (Sensor Input Threshold 1 through Sensor Input Threshold 6). The individual Sensor Input X Threshold registers (Sensor Input 2 Threshold through Sensor Input 6 Threshold) can be individually updated at any time. Bit 6 - NO_CLR_INTD - Controls whether the accumulation of intermediate data is cleared if the noise status bit is set. • ‘0’ (default) - The accumulation of intermediate data is cleared if the noise status bit is set. • ‘1’ - The accumulation of intermediate data is not cleared if the noise status bit is set. APPLICATION NOTE: Bits 5 and 6 should both be set to the same value. Either both should be set to ‘0’ or both should be set to ‘1’. Bit 5 - NO_CLR_NEG - Controls whether the consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘0’ (default) - The consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘1’ - The consecutive negative delta counts counter is not cleared if the noise status bit is set. Bits 4 - 3 - NEG_DELTA_CNT[1:0] - Determines the number of negative delta counts necessary to trigger a digital recalibration as shown in Table 6-30. TABLE 6-29: RECALIBRATION CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Fh R/W Recalibration Configuration BUT_ LD_TH NO_ CLR_ INTD NO_ CLR_ NEG NEG_DELTA_ CNT[1:0] CAL_CFG[2:0] 8Ah TABLE 6-30: NEG_DELTA_CNT BIT DECODE NEG_DELTA_CNT[1:0] Number of Consecutive Negative Delta Count Values 1 0 00 8 0 1 16 (default) 1 0 32 1 1 None (disabled) CAP1126 DS00001623B-page 44  2015 Microchip Technology Inc. Bits 2 - 0 - CAL_CFG[2:0] - Determines the update time and number of samples of the automatic re-calibration routine. The settings apply to all sensor inputs universally (though individual sensor inputs can be configured to support re-calibration - see Section 6.11). Note 6-1 Recalibration Samples refers to the number of samples that are measured and averaged before the Base Count is updated however does not control the base count update period. Note 6-2 Update Time refers to the amount of time (in polling cycle periods) that elapses before the Base Count is updated. The time will depend upon the number of channels active, the averaging setting, and the programmed cycle time. 6.18 Sensor Input Threshold Registers The Sensor Input Threshold registers store the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. When the BUT_LD_TH bit is set (see Section 6.17 - bit 7), writing data to the Sensor Input 1 Threshold register will update all of the sensor input threshold registers (31h - 35h inclusive). 6.19 Sensor Input Noise Threshold Register TABLE 6-31: CAL_CFG BIT DECODE CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210 0 0 0 16 16 0 0 1 32 32 0 1 0 64 64 (default) 0 1 1 128 128 1 0 0 256 256 1 0 1 256 1024 1 1 0 256 2048 1 1 1 256 4096 TABLE 6-32: SENSOR INPUT THRESHOLD REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 30h R/W Sensor Input 1 Threshold - 64 32 16 8 4 2 1 40h 31h R/W Sensor Input 2 Threshold - 64 32 16 8 4 2 1 40h 32h R/W Sensor Input 3 Threshold - 64 32 16 8 4 2 1 40h 33h R/W Sensor Input 4 Threshold - 64 32 16 8 4 2 1 40h 34h R/W Sensor Input 5 Threshold - 64 32 16 8 4 2 1 40h 35h R/W Sensor Input 6 Threshold - 64 32 16 8 4 2 1 40h TABLE 6-33: SENSOR INPUT NOISE THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 38h R/W Sensor Input Noise Threshold CS_BN_TH [1:0] 01h  2015 Microchip Technology Inc. DS00001623B-page 45 CAP1126 The Sensor Input Noise Threshold register controls the value of a secondary internal threshold to detect noise and improve the automatic recalibration routine. If a capacitive touch sensor input exceeds the Sensor Input Noise Threshold but does not exceed the sensor input threshold, it is determined to be caused by a noise spike. That sample is not used by the automatic re-calibration routine. This feature can be disabled by setting the DIS_DIG_NOISE bit. Bits 1-0 - CS1_BN_TH[1:0] - Controls the noise threshold for all capacitive touch sensor inputs, as shown in Table 6-34. The threshold is proportional to the threshold setting. 6.20 Standby Channel Register The Standby Channel register controls which (if any) capacitive touch sensor inputs are active during Standby. Bit 5 - CS6_STBY - Controls whether the CS6 channel is active in Standby. • ‘0’ (default) - The CS6 channel not be sampled during Standby mode. • ‘1’ - The CS6 channel will be sampled during Standby Mode. It will use the Standby threshold setting, and the standby averaging and sensitivity settings. Bit 4 - CS5_STBY - Controls whether the CS5 channel is active in Standby. Bit 3 - CS4_STBY - Controls whether the CS4 channel is active in Standby. Bit 2 - CS3_STBY - Controls whether the CS3 channel is active in Standby. Bit 1 - CS2_STBY - Controls whether the CS2 channel is active in Standby. Bit 0 - CS1_STBY - Controls whether the CS1 channel is active in Standby. 6.21 Standby Configuration Register The Standby Configuration register controls averaging and cycle time for those sensor inputs that are active in Standby. This register is useful for detecting proximity on a small number of sensor inputs as it allows the user to change averaging and sample times on a limited number of sensor inputs and still maintain normal functionality in the fully active state. Bit 7 - AVG_SUM - Determines whether the active sensor inputs will average the programmed number of samples or whether they will accumulate for the programmed number of samples. • ‘0’ - (default) - The active sensor input delta count values will be based on the average of the programmed number of samples when compared against the threshold. • ‘1’ - The active sensor input delta count values will be based on the summation of the programmed number of samples when compared against the threshold. This bit should only be set when performing proximity detection as TABLE 6-34: CSX_BN_TH BIT DECODE CS_BN_TH[1:0] Percent Threshold Setting 1 0 0 0 25% 0 1 37.5% (default) 1 0 50% 1 1 62.5% TABLE 6-35: STANDBY CHANNEL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 40h R/W Standby Channel - - CS6_ STBY CS5_ STBY CS4_ STBY CS3_ STBY CS2_ STBY CS1_ STBY 00h TABLE 6-36: STANDBY CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 41h R/W Standby Configuration AVG_ SUM STBY_AVG[2:0] STBY_SAMP_ TIME[1:0] STBY_CY_TIME [1:0] 39h CAP1126 DS00001623B-page 46  2015 Microchip Technology Inc. a physical touch will overflow the delta count registers and may result in false readings. Bits 6 - 4 - STBY_AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-37. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. Bit 3-2 - STBY SAMP_TIME[1:0] - Determines the time to take a single sample when the device is in Standby as shown in Table 6-38. Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during standby operation as shown in Table 6-39. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. TABLE 6-37: STBY_AVG BIT DECODE STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-38: STBY_SAMP_TIME BIT DECODE STBY_SAMP_TIME[1:0] Sampling Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-39: STBY_CY_TIME BIT DECODE STBY_CY_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms  2015 Microchip Technology Inc. DS00001623B-page 47 CAP1126 6.22 Standby Sensitivity Register The Standby Sensitivity register controls the sensitivity for sensor inputs that are active in Standby. Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensor inputs that are active in Standby. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more sensitive to noise however and a noisy environment may flag more false touches than higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). 6.23 Standby Threshold Register The Standby Threshold register stores the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. 6.24 Sensor Input Base Count Registers TABLE 6-40: STANDBY SENSITIVITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 42h R/W Standby Sensitivity - - - - - STBY_SENSE[2:0] 02h TABLE 6-41: STBY_SENSE BIT DECODE STBY_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-42: STANDBY THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 43h R/W Standby Threshold - 64 32 16 8 4 2 1 40h TABLE 6-43: SENSOR INPUT BASE COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 50h R Sensor Input 1 Base Count 128 64 32 16 8 4 2 1 C8h CAP1126 DS00001623B-page 48  2015 Microchip Technology Inc. The Sensor Input Base Count registers store the calibrated “Not Touched” input value from the capacitive touch sensor inputs. These registers are periodically updated by the re-calibration routine. The routine uses an internal adder to add the current count value for each reading to the sum of the previous readings until sample size has been reached. At this point, the upper 16 bits are taken and used as the Sensor Input Base Count. The internal adder is then reset and the re-calibration routine continues. The data presented is determined by the BASE_SHIFT[3:0] bits (see Section 6.5). 6.25 LED Output Type Register The LED Output Type register controls the type of output for the LED pins. Each pin is controlled by a single bit. Refer to application note 21.4 CAP1126Family LED Configuration Options for more information about implementing LEDs. Bit 1 - LED2_OT - Determines the output type of the LED2 pin. • ‘0’ (default) - The LED2 pin is an open-drain output with an external pull-up resistor. When the appropriate pin is set to the “active” state (logic ‘1’), the pin will be driven low. Conversely, when the pin is set to the “inactive” state (logic ‘0’), then the pin will be left in a High Z state and pulled high via an external pull-up resistor. • ‘1’ - The LED2 pin is a push-pull output. When driving a logic ‘1’, the pin is driven high. When driving a logic ‘0’, the pin is driven low. Bit 0 - LED1_OT - Determines the output type of the LED1 pin. 6.26 Sensor Input LED Linking Register The Sensor Input LED Linking register controls whether a capacitive touch sensor input is linked to an LED output. If the corresponding bit is set, then the appropriate LED output will change states defined by the LED Behavior controls (see Section 6.31) in response to the capacitive touch sensor input. Bit 1 - CS2_LED2 - Links the LED2 output to a detected touch on the CS2 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. • ‘0’ (default) - The LED 2 output is not associated with the CS2 input. If a touch is detected on the CS2 input, the LED will not automatically be actuated. The LED is enabled and controlled via the LED Output Control register (see Section 6.28) and the LED Behavior registers (see Section 6.31). 51h R Sensor Input 2 Base Count 128 64 32 16 8 4 2 1 C8h 52h R Sensor Input 3 Base Count 128 64 32 16 8 4 2 1 C8h 53h R Sensor Input 4 Base Count 128 64 32 16 8 4 2 1 C8h 54h R Sensor Input 5 Base Count 128 64 32 16 8 4 2 1 C8h 55h R Sensor Input 6 Base Count 128 64 32 16 8 4 2 1 C8h TABLE 6-44: LED OUTPUT TYPE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 71h R/W LED Output Type ----- - LED2_ OT LED1_ OT 00h TABLE 6-45: SENSOR INPUT LED LINKING REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 72h R/W Sensor Input LED Linking - - - - - - CS2_ LED2 CS1_ LED1 00h TABLE 6-43: SENSOR INPUT BASE COUNT REGISTERS (CONTINUED) ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default  2015 Microchip Technology Inc. DS00001623B-page 49 CAP1126 • ‘1’ - The LED 2 output is associated with the CS2 input. If a touch is detected on the CS2 input, the LED will be actuated and behave as defined in Table 6-52. Bit 0 - CS1_LED1 - Links the LED1 output to a detected touch on the CS1 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. 6.27 LED Polarity Register The LED Polarity register controls the logical polarity of the LED outputs. When these bits are set or cleared, the corresponding LED Mirror controls are also set or cleared (unless the BLK_POL_MIR bit is set - see Section 6.6, "Configuration Registers"). Table 6-48, "LED Polarity Behavior" shows the interaction between the polarity controls, output controls, and relative brightness. APPLICATION NOTE: The polarity controls determine the final LED pin drive. A touch on a linked capacitive touch sensor input is treated in the same way as the LED Output Control bit being set to a logic ‘1’. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’ then the LED will be on and that the CAP1126 LED pin is sinking the LED current. Conversely, if the LED pin is driven to a logic ‘1’, the LED will be off and there is no current flow. See Figure 5-1, "System Diagram for CAP1126". APPLICATION NOTE: This application note applies when the LED polarity is inverted (LEDx_POL = ‘0’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘0’ state in. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven low (i.e. maximum % of time that the LED is on) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven low (i.e. minimum % of time that the LED is on). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at the minimum duty cycle setting. Breathe operations will ramp the duty cycle from the minimum duty cycle to the maximum duty cycle. APPLICATION NOTE: This application note applies when the LED polarity is non-inverted (LEDx_POL = ‘1’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘1’ state. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven high (i.e. maximum % of time that the LED is off) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven high (i.e. minimum % of time that the LED is off). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at 100 minus the minimum duty cycle setting. Breathe operations will ramp the duty cycle from 100 minus the minimum duty cycle to 100 minus the maximum duty cycle. APPLICATION NOTE: The LED Mirror controls (see Section 6.30, "LED Mirror Control Register") work with the polarity controls with respect to LED brightness but will not have a direct effect on the output pin drive. Bit 1 - LED2_POL - Determines the polarity of the LED2 output. • ‘0’ (default) - The LED2 output is inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘0’. • ‘1’ - The LED2 output is non-inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘1’ or left in the high-z state as determined by its output type. Bit 0 - LED1_POL - Determines the polarity of the LED1 output. TABLE 6-46: LED POLARITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 73h R/W LED Polarity - - - - - - LED2_ POL LED1_ POL 00h CAP1126 DS00001623B-page 50  2015 Microchip Technology Inc. 6.28 LED Output Control Register The LED Output Control Register controls the output state of the LED pins that are not linked to sensor inputs. The LED Polarity Control Register will determine the non actuated state of the LED pins. The actuated LED behavior is determined by the LED behavior controls (see Section 6.31, "LED Behavior Register"). Table 6-48 shows the interaction between the polarity controls, output controls, and relative brightness. Bit 1 - LED2_DR - Determines whether LED2 output is driven high or low. • ‘0’ (default) - The LED2 output is driven at the minimum duty cycle or not actuated. • ‘1’ - The LED2 output is High Z or driven at the maximum duty cycle or actuated. Bit 0 - LED1_DR - Determines whether LED1 output is driven high or low. TABLE 6-47: LED OUTPUT CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 74h R/W LED Output Control --- - -- LED2_ DR LED1_ DR 00h Note: If an LED is linked to a sensor input in the Sensor Input LED Linking Register (Section 6.26, "Sensor Input LED Linking Register"), the corresponding bit in the LED Output Control Register is ignored (i.e. a linked LED cannot be host controlled). TABLE 6-48: LED POLARITY BEHAVIOR LED Output Control Register or Touch Polarity Max Duty Min Duty Brightness LED Appearance 0 inverted (‘0’) not used minimum % of time that the LED is on (logic 0) maximum brightness at min duty cycle on at min duty cycle 1 inverted (‘0’) maximum % of time that the LED is on (logic 0) minimum % of time that the LED is on (logic 0) maximum brightness at max duty cycle. Brightness ramps from min duty cycle to max duty cycle according to LED behavior 0 non-inverted (‘1’) not used minimum % of time that the LED is off (logic 1) maximum brightness at 100 minus min duty cycle. on at 100 - min duty cycle 1 non-inverted (‘1’) maximum % of time that the LED is off (logic 1) minimum % of time that the LED is off (logic 1) For Direct behavior, maximum brightness is 100 minus max duty cycle. When breathing, max brightness is 100 minus min duty cycle. Brightness ramps from 100 - min duty cycle to 100 - max duty cycle. according to LED behavior  2015 Microchip Technology Inc. DS00001623B-page 51 CAP1126 6.29 Linked LED Transition Control Register The Linked LED Transition Control register controls the LED drive when the LED is linked to a capacitive touch sensor input. These controls work in conjunction with the INV_LINK_TRAN bit (see Section 6.6.2, "Configuration 2 - 44h") to create smooth transitions from host control to linked LEDs. Bit 1 - LED2_LTRAN - Determines the transition effect when LED2 is linked to CS2. • ‘0’ (default) - When the LED output control bit for LED2 is ‘1’, and then LED2 is linked to CS2 and no touch is detected, the LED will change states. • ‘1’ - If the INV_LINK_TRAN bit is ‘1’, when the LED output control bit for CS2 is ‘1’, and then CS2 is linked to LED2 and no touch is detected, the LED will not change states. In addition, the LED state will change when the sensor pad is touched. If the INV_LINK_TRAN bit is ‘0’, when the LED output control bit for CS2 is ‘1’, and then CS2 is linked to LED2 and no touch is detected, the LED will not change states. However, the LED state will not change when the sensor pad is touched. APPLICATION NOTE: If the LED behavior is not “Direct” and the INV_LINK_TRAN bit it ‘0’, the LED will not perform as expected when the LED2_LTRAN bit is set to ‘1’. Therefore, if breathe and pulse behaviors are used, set the INV_LINK_TRAN bit to ‘1’. Bit 0 - LED1_LTRAN - Determines the transition effect when LED1 is linked to CS1. 6.30 LED Mirror Control Register The LED Mirror Control Registers determine the meaning of duty cycle settings when polarity is non-inverted for each LED channel. When the polarity bit is set to ‘1’ (non-inverted), to obtain correct steps for LED ramping, pulse, and breathe behaviors, the min and max duty cycles need to be relative to 100%, rather than the default, which is relative to 0%. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’, the LED will be on and the CAP1126 LED pin is sinking the LED current. When the polarity bit is set to ‘1’, it is considered non-inverted. For systems using the opposite LED configuration, mirror controls would apply when the polarity bit is ‘0’. These bits are changed automatically if the corresponding LED Polarity bit is changed (unless the BLK_POL_MIR bit is set - see Section 6.6). Bit 1 - LED2_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. • ‘0’ (default) - The duty cycle settings are determined relative to 0% and are determined directly with the settings. • ‘1’ - The duty cycle settings are determined relative to 100%. Bit 0 - LED1_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. 6.31 LED Behavior Register TABLE 6-49: LINKED LED TRANSITION CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 77h R/W Linked LED Transition Control - ----- LED2_ LTRAN LED1_ LTRAN 00h TABLE 6-50: LED MIRROR CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 79h R/W LED Mirror Control ------ LED2_ MIR _ EN LED1_ MIR _ EN 00h TABLE 6-51: LED BEHAVIOR REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 81h R/W LED Behavior 1 - - - - LED2_CTL[1:0] LED1_CTL[1:0] 00h CAP1126 DS00001623B-page 52  2015 Microchip Technology Inc. The LED Behavior register controls the operation of LEDs. Each LED pin is controlled by a 2-bit field and the behavior is determined by whether the LED is linked to a capacitive touch sensor input or not. If the corresponding LED output is linked to a capacitive touch sensor input, the appropriate behavior will be enabled / disabled based on touches and releases. If the LED output is not associated with a capacitive touch sensor input, the appropriate behavior will be enabled / disabled by the LED Output Control register. If the respective LEDx_DR bit is set to a logic ‘1’, this will be associated as a “touch”, and if the LEDx_DR bit is set to a logic ‘0’, this will be associated as a “release”. Table 6-52, "LEDx_CTL Bit Decode" shows the behavior triggers. The defined behavior will activate when the Start Trigger is met and will stop when the Stop Trigger is met. Note the behavior of the Breathe Hold and Pulse Release option. The LED Polarity Control register will determine the non actuated state of the LED outputs (see Section 6.27, "LED Polarity Register"). APPLICATION NOTE: If an LED is not linked to a capacitive touch sensor input and is breathing (via the Breathe or Pulse behaviors), it must be unactuated and then re-actuated before changes to behavior are processed. For example, if the LED output is breathing and the Maximum duty cycle is changed, this change will not take effect until the LED output control register is set to ‘0’ and then re-set to ‘1’. APPLICATION NOTE: If an LED is not linked to the capacitive touch sensor input and configured to operate using Pulse 1 Behavior, then the circuitry will only be actuated when the corresponding output control bit is set. It will not check the bit condition until the Pulse 1 behavior is finished. The device will not remember if the bit was cleared and reset while it was actuated. APPLICATION NOTE: If an LED is actuated and not linked and the desired LED behavior is changed, this new behavior will take effect immediately; however, the first instance of the changed behavior may act incorrectly (e.g. if changed from Direct to Pulse 1, the LED output may ‘breathe’ 4 times and then end at minimum duty cycle). LED Behaviors will operate normally once the LED has been un-actuated and then re-actuated. APPLICATION NOTE: If an LED is actuated and it is switched from linked to a capacitive touch sensor input to unlinked (or vice versa), the LED will respond to the new command source immediately if the behavior was Direct or Breathe. For Pulse behaviors, it will complete the behavior already in progress. For example, if a linked LED was actuated by a touch and the control is changed so that it is unlinked, it will check the status of the corresponding LED Output Control bit. If that bit is ‘0’, then the LED will behave as if a release was detected. Likewise, if an unlinked LED was actuated by the LED Output Control register and the control is changed so that it is linked and no touch is detected, then the LED will behave as if a release was detected. Bits 3 - 2 - LED2_CTL[1:0] - Determines the behavior of LED2 as shown in Table 6-52. Bits 1 - 0 - LED1_CTL[1:0] - Determines the behavior of LED1 as shown in Table 6-52.  2015 Microchip Technology Inc. DS00001623B-page 53 CAP1126 APPLICATION NOTE: The PWM frequency is determined based on the selected LED behavior, the programmed breathe period, and the programmed min and max duty cycles. For the Direct behavior mode, the PWM frequency is calculated based on the programmed Rise and Fall times. If these are set at 0, then the maximum PWM frequency will be used based on the programmed duty cycle settings. 6.32 LED Pulse 1 Period Register The LED Pulse Period 1 register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 01b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms (24 x 32ms = 768ms). The total range is from 32ms to 4.064 seconds as shown in Table 6-54 with the default being 1024ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. Bit 7 - ST_TRIG - Determines the start trigger for the LED Pulse behavior. • ‘0’ (default) - The LED will Pulse when a touch is detected or the drive bit is set. • ‘1’ - The LED will Pulse when a release is detected or the drive bit is cleared. TABLE 6-52: LEDX_CTL BIT DECODE LEDx_CTL [1:0] Operation Description Start TRigger Stop Trigger 1 0 0 0 Direct The LED is driven to the programmed state (active or inactive). See Figure 6-7 Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 0 1 Pulse 1 The LED will “Pulse” a programmed number of times. During each “Pulse” the LED will breathe up to the maximum brightness and back down to the minimum brightness so that the total “Pulse” period matches the programmed value. Touch or Release Detected or LED Output Control bit set or cleared (see Section 6.32) n/a 1 0 Pulse 2 The LED will “Pulse” when the start trigger is detected. When the stop trigger is detected, it will “Pulse” a programmable number of times then return to its minimum brightness. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 1 1 Breathe The LED will breathe. It will be driven with a duty cycle that ramps up from the programmed minimum duty cycle (default 0%) to the programmed maximum duty cycle duty cycle (default 100%) and then back down. Each ramp takes up 50% of the programmed period. The total period of each “breath” is determined by the LED Breathe Period controls - see Section 6.34. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared TABLE 6-53: LED PULSE 1 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 84h R/W LED Pulse 1 Period ST_ TRIG P1_ PER6 P1_ PER5 P1_ PER4 P1_ PER3 P1_ PER2 P1_ PER1 P1_ PER0 20h CAP1126 DS00001623B-page 54  2015 Microchip Technology Inc. The Pulse 1 operation is shown in Figure 6-1 when the LED output is configured for non-inverted polarity (LEDx_POL = 1) and in Figure 6-2 for inverted polarity (LEDx_POL = 0). . FIGURE 6-1: Pulse 1 Behavior with Non-Inverted Polarity FIGURE 6-2: Pulse 1 Behavior with Inverted Polarity TABLE 6-54: LED PULSE / BREATHE PERIOD EXAMPLE Setting (HEX) Setting (Decimal) Total Breathe / Pulse Period (MS) 00h 0 32 01h 1 32 02h 2 64 03h 3 96 . . . . . . . . . 7Dh 125 4000 Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected (100% - Pulse 1 Max Duty Cycle) * Brightness X pulses after touch or after release Pulse 1 Period (P1_PER) (100% - Pulse 1 Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected Pulse 1 Min Duty Cycle * Brightness X pulses after touch or after release Pulse Period (P1_PER) Pulse 1 Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001623B-page 55 CAP1126 6.33 LED Pulse 2 Period Register The LED Pulse 2 Period register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 10b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 640ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. The Pulse 2 Behavior is shown in Figure 6-3 for non-inverted polarity (LEDx_POL = 1) and in Figure 6-4 for inverted polarity (LEDx_POL = 0). 7Eh 126 4032 7Fh 127 4064 TABLE 6-55: LED PULSE 2 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 85h R/W LED Pulse 2 Period - P2_ PER6 P2_ PER5 P2_ PER4 P2_ PER3 P2_ PER2 P2_ PER1 P2_ PER0 14h FIGURE 6-3: Pulse 2 Behavior with Non-Inverted Polarity TABLE 6-54: LED PULSE / BREATHE PERIOD EXAMPLE (CONTINUED) Setting (HEX) Setting (Decimal) Total Breathe / Pulse Period (MS) . . . Normal – untouched operation Normal – untouched operation Touch Detected (100% - Pulse 2 Min Duty Cycle) * Brightness (100% - Pulse 2 Max Duty Cycle) * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness CAP1126 DS00001623B-page 56  2015 Microchip Technology Inc. 6.34 LED Breathe Period Register The LED Breathe Period register determines the overall period of a breathe operation as determined by the LED_CTL registers (see Table 6-52 - setting 11b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 2976ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. 6.35 LED Configuration Register The LED Configuration register controls general LED behavior as well as the number of pulses that are sent for the PULSE LED output behavior. Bit 6 - RAMP_ALERT - Determines whether the device will assert the ALERT# pin when LEDs actuated by the LED Output Control register bits have finished their respective behaviors. Interrupts will only be generated if the LED activity is generated by writing the LED Output Control registers. Any LED activity associated with touch detection will not cause an interrupt to be generated when the LED behavior has been finished. • ‘0’ (default) - The ALERT# pin will not be asserted when LEDs actuated by the LED Output Control register have finished their programmed behaviors. • ‘1’ - The ALERT# pin will be asserted whenever any LED that is actuated by the LED Output Control register has finished its programmed behavior. Bits 5 - 3 - PULSE2_CNT[2:0] - Determines the number of pulses used for the Pulse 2 behavior as shown in Table 6-58. Bits 2 - 0 - PULSE1_CNT[2:0] - Determines the number of pulses used for the Pulse 1 behavior as shown in Table 6-58. FIGURE 6-4: Pulse 2 Behavior with Inverted Polarity TABLE 6-56: LED BREATHE PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 86h R/W LED Breathe Period - BR_ PER6 BR_ PER5 BR_ PER4 BR_ PER3 BR_ PER2 BR_ PER1 BR_ PER0 5Dh TABLE 6-57: LED CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 88h R/W LED Config - RAMP_ ALERT PULSE2_CNT[2:0] PULSE1_CNT[2:0] 04h Normal – untouched operation Normal – untouched operation Touch Detected Pulse 2 Max Duty Cycle * Brightness Pulse 2 Min Duty Cycle * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness . . .  2015 Microchip Technology Inc. DS00001623B-page 57 CAP1126 6.36 LED Duty Cycle Registers The LED Duty Cycle registers determine the minimum and maximum duty cycle settings used for the LED for each LED behavior. These settings affect the brightness of the LED when it is fully off and fully on. The LED driver duty cycle will ramp up from the minimum duty cycle to the maximum duty cycle and back down again. APPLICATION NOTE: When operating in Direct behavior mode, changes to the Duty Cycle settings will be applied immediately. When operating in Breathe, Pulse 1, or Pulse 2 modes, the LED must be unactuated and then re-actuated before changes to behavior are processed. Bits 7 - 4 - X_MAX_DUTY[3:0] - Determines the maximum PWM duty cycle for the LED drivers as shown in Table 6-60. Bits 3 - 0 - X_MIN_DUTY[3:0] - Determines the minimum PWM duty cycle for the LED drivers as shown in Table 6-60. TABLE 6-58: PULSEX_CNT DECODE PULSEX_CNT[2:0] Number of Breaths 21 0 0 0 0 1 (default - Pulse 2) 00 1 2 01 0 3 01 1 4 1 0 0 5 (default - Pulse 1) 10 1 6 11 0 7 11 1 8 TABLE 6-59: LED DUTY CYCLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 90h R/W LED Pulse 1 Duty Cycle P1_MAX_DUTY[3:0] P1_MIN_DUTY[3:0] F0h 91h R/W LED Pulse 2 Duty Cycle P2_MAX_DUTY[3:0] P2_MIN_DUTY[3:0] F0h 92h R/W LED Breathe Duty Cycle BR_MAX_DUTY[3:0] BR_MIN_DUTY[3:0] F0h 93h R/W Direct Duty Cycle DR_MAX_DUTY[3:0] DR_MIN_DUTY[3:0] F0h TABLE 6-60: LED DUTY CYCLE DECODE x_MAX/MIN_Duty [3:0] Maximum Duty Cycle Minimum Duty Cycle 3 21 0 0 0 0 0 7% 0% 0 0 0 1 9% 7% 0 0 1 0 11% 9% 0 0 1 1 14% 11% 0 1 0 0 17% 14% 0 1 0 1 20% 17% 0 1 1 0 23% 20% 0 1 1 1 26% 23% 1 0 0 0 30% 26% 1 0 0 1 35% 30% 1 0 1 0 40% 35% CAP1126 DS00001623B-page 58  2015 Microchip Technology Inc. 6.37 LED Direct Ramp Rates Register The LED Direct Ramp Rates register control the rising and falling edge time of an LED that is configured to operate in Direct behavior mode. The rising edge time corresponds to the amount of time the LED takes to transition from its minimum duty cycle to its maximum duty cycle. Conversely, the falling edge time corresponds to the amount of time that the LED takes to transition from its maximum duty cycle to its minimum duty cycle. Bits 5 - 3 - RISE_RATE[2:0] - Determines the rising edge time of an LED when it transitions from its minimum drive state to its maximum drive state as shown in Table 6-62. Bits 2 - 0 - FALL_RATE[2:0] - Determines the falling edge time of an LED when it transitions from its maximum drive state to its minimum drive state as shown in Table 6-62. 6.38 LED Off Delay Register The LED Off Delay register determines the amount of time that an LED remains at its maximum duty cycle (or minimum as determined by the polarity controls) before it starts to ramp down. If the LED is operating in Breathe mode, this delay is applied at the top of each “breath”. If the LED is operating in the Direct mode, this delay is applied when the LED is unactuated. 1 0 1 1 46% 40% 1 1 0 0 53% 46% 1 1 0 1 63% 53% 1 1 1 0 77% 63% 1 1 1 1 100% 77% TABLE 6-61: LED DIRECT RAMP RATES REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 94h R/W LED Direct Ramp Rates - - RISE_RATE[2:0] FALL_RATE[2:0] 00h TABLE 6-62: RISE / FALL RATE DECODE RISE_RATE/ FALL_RATE/ Bit Decode Rise / Fall Time (TRISE / TFALL) 21 0 00 0 0 0 0 1 250ms 0 1 0 500ms 0 1 1 750ms 1 0 0 1s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2s TABLE 6-63: LED OFF DELAY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 95h R/W LED Off Delay Register - BR_OFF_DLY[2:0] DIR_OFF_DLY[3:0] 00h TABLE 6-60: LED DUTY CYCLE DECODE (CONTINUED) x_MAX/MIN_Duty [3:0] Maximum Duty Cycle Minimum Duty Cycle 3 21 0  2015 Microchip Technology Inc. DS00001623B-page 59 CAP1126 Bits 6 - 4 - BR_OFF_DLY[2:0] - Determines the Breathe behavior mode off delay, which is the amount of time an LED in Breathe behavior mode remains inactive after it finishes a breathe pulse (ramp on and ramp off), as shown in Figure 6- 5 (non-inverted polarity LEDx_POL = 1) and Figure 6-6 (inverted polarity LEDx_POL = 0). Available settings are shown in Table 6-64. FIGURE 6-5: Breathe Behavior with Non-Inverted Polarity FIGURE 6-6: Breathe Behavior with Inverted Polarity LED Actuated 100% - Breathe Max Min Cycle * Brightness 100% - Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) LED Actuated Breathe Max Duty Cycle * Brightness Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) CAP1126 DS00001623B-page 60  2015 Microchip Technology Inc. Bits 3 - 0 - DIR_OFF_DLY[3:0] - Determines the turn-off delay, as shown in Table 6-65, for all LEDs that are configured to operate in Direct behavior mode. The Direct behavior operation is determined by the combination of programmed Rise Time, Fall Time, Min and Max Duty cycles, Off Delay, and polarity. Figure 6-7 shows the behavior for non-inverted polarity (LEDx_POL = 1) while Figure 6- 8 shows the behavior for inverted polarity (LEDx_POL = 0). TABLE 6-64: BREATHE OFF DELAY SETTINGS BR_OFF_DLY [2:0] OFF Delay 2 10 0 0 0 0 (default) 0 0 1 0.25s 0 1 0 0.5s 0 1 1 0.75s 1 0 0 1.0s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2.0s FIGURE 6-7: Direct Behavior for Non-Inverted Polarity FIGURE 6-8: Direct Behavior for Inverted Polarity Normal – untouched operation RISE_RATE Setting (tRISE) (100% - Max Duty Cycle) * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation (100% - Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation RISE_RATE Setting (tRISE) Min Duty Cycle * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001623B-page 61 CAP1126 6.39 Sensor Input Calibration Registers The Sensor Input Calibration registers hold the 10-bit value that represents the last calibration value. TABLE 6-65: OFF DELAY DECODE OFF Delay[3:0] Bit Decode OFF Delay (tOFF_DLY) 32 1 0 00 0 0 0 0 0 0 1 250ms 0 0 1 0 500ms 0 0 1 1 750ms 0 1 0 0 1s 0 1 0 1 1.25s 0 1 1 0 1.5s 0 1 1 1 2s 1 0 0 0 2.5s 1 0 0 1 3.0s 1 0 1 0 3.5s 1 0 1 1 4.0s 1 1 0 0 4.5s All others 5.0s TABLE 6-66: SENSOR INPUT CALIBRATION REGISTERS ADDR Register R/W B7 B6 B5 B4 B3 B2 B1 B0 Default B1h Sensor Input 1 Calibration R CAL1_9 CAL1_8 CAL1_7 CAL1_6 CAL1_5 CAL1_4 CAL1_3 CAL1_2 00h B2h Sensor Input 2 Calibration R CAL2_9 CAL2_8 CAL2_7 CAL2_6 CAL2_5 CAL2_4 CAL2_3 CAL2_2 00h B3h Sensor Input 3 Calibration R CAL3_9 CAL3_8 CAL3_7 CAL3_6 CAL3_5 CAL3_4 CAL3_3 CAL3_2 00h B4h Sensor Input 4 Calibration R CAL4_9 CAL4_8 CAL4_7 CAL4_6 CAL4_5 CAL4_4 CAL4_3 CAL4_2 00h B5h Sensor Input 5 Calibration R CAL5_9 CAL5_8 CAL5_7 CAL5_6 CAL5_5 CAL5_4 CAL5_3 CAL5_2 00h B6h Sensor Input 6 Calibration R CAL6_9 CAL6_8 CAL6_7 CAL6_6 CAL6_5 CAL6_4 CAL6_3 CAL6_2 00h B9h Sensor Input Calibration LSB 1 R CAL4_1 CAL4_0 CAL3_1 CAL3_0 CAL2_1 CAL2_0 CAL1_1 CAL1_0 00h BAh Sensor Input Calibration LSB 2 R - - - - CAL6_1 CAL6_0 CAL5_1 CAL5_0 00h CAP1126 DS00001623B-page 62  2015 Microchip Technology Inc. 6.40 Product ID Register The Product ID register stores a unique 8-bit value that identifies the device. 6.41 Manufacturer ID Register The Vendor ID register stores an 8-bit value that represents Microchip. 6.42 Revision Register The Revision register stores an 8-bit value that represents the part revision. TABLE 6-67: PRODUCT ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FDh R Product ID 0 1 0 1 0 0 1 1 53h TABLE 6-68: VENDOR ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh TABLE 6-69: REVISION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FFh R Revision 1 0 0 0 0 0 1 1 83h  2015 Microchip Technology Inc. DS00001623B-page 63 CAP1126 7.0 PACKAGE INFORMATION 7.1 CAP1126 Package Drawings Note: For the most current package drawings, see the Microchip Packaging Specification at: http://www.microchip.com/packaging. FIGURE 7-1: 16-Pin QFN 4mm x 4mm Package Drawing CAP1126 DS00001623B-page 64  2015 Microchip Technology Inc. FIGURE 7-2: 16-Pin QFN 4mm x 4mm Package Dimensions FIGURE 7-3: 16-Pin QFN 4mm x 4mm PCB Footprint  2015 Microchip Technology Inc. DS00001623B-page 65 CAP1126 7.2 Package Marking FIGURE 7-4: CAP1126 Package Markings C 1 26 - 1 Y WWN N N A RCC e3 TOP BOTTOM Bottom marking not allowed PB-FREE/GREEN SYMBOL (Matte Sn) Lines 1-3: Line 4: Center Horizontal Alignment Left Horizontal Alignment PIN 1 0.41 3x 0.56 Line 1 – SMSC Logo without circled R symbol Line 2 – Device ID, Version Line 3 – Year, Week, Alphanumeric Traceability Code Line 4 – Revision, Country Code 1 CAP1126 DS00001623B-page 66  2015 Microchip Technology Inc. APPENDIX A: DEVICE DELTA A.1 Delta from CAP1026 to CAP1126 1. Updated circuitry to improve power supply rejection. 2. Updated LED driver duty cycle decode values to have more distribution at lower values - closer to a logarithmic curve. See Table 6-60, "LED Duty Cycle Decode". 3. Updated bug that breathe periods were not correct above 2.6s. This includes rise / fall time decodes above 1.5s. 4. Added filtering on RESET pin to prevent errant resets. 5. Updated controls so that the RESET pin assertion places the device into the lowest power state available and causes an interrupt when released. See Section 5.2, "RESET Pin". 6. Added 1 bit to the LED Off Delay register (see Section 6.38, "LED Off Delay Register") to extend times from 2s to 5s in 0.5s intervals. 7. Breathe behavior modified. A breathe off delay control was added to the LED Off Delay Register (see Section 6.38, "LED Off Delay Register") so the LEDs can be configured to remain inactive between breathes. 8. Added controls for the LED transition effects when linking LEDs to capacitive sensor inputs. See Section 6.29, "Linked LED Transition Control Register". 9. Added controls to “mirror” the LED duty cycle outputs so that when polarity changes, the LED brightness levels look right. These bits are automatically set when polarity is set. Added control to break this auto-set behavior. See Section 6.30, "LED Mirror Control Register". 10. Added Multiple Touch Pattern detection circuitry. See Section 6.15, "Multiple Touch Pattern Configuration Register". 11. Added General Status register to flag Multiple touches, Multiple Touch Pattern issues and general touch detections. See Section 6.2, "Status Registers". 12. Added bits 6 and 5 to the Recalibration Configuration register (2Fh - see Section 6.17, "Recalibration Configuration Register"). These bits control whether the accumulation of intermediate data and the consecutive negative delta counts counter are cleared when the noise status bit is set. 13. Added Configuration 2 register for LED linking controls, noise detection controls, and control to interrupt on press but not on release. Added control to change alert pin polarity. See Section 6.6, "Configuration Registers". 14. Updated Deep Sleep behavior so that device does not clear DSLEEP bit on received communications but will wake to communicate. 15. Changed PWM frequency for LED drivers. The PWM frequency was derived from the programmed breathe period and duty cycle settings and it ranged from ~4Hz to ~8000 Hz. The PWM frequency has been updated to be a fixed value of ~2000Hz. 16. Register delta: Table A.1 Register Delta From CAP1026 to CAP1126 Address Register Delta Delta Default 00h Page 31 Changed - Main Status / Control added bits 7-6 to control gain 00h 02h Page 32 New - General Status new register to store MTP, MULT, LED, RESET, and general TOUCH bits 00h 44h Page 35 New - Configuration 2 new register to control alert polarity, LED touch linking behavior, LED output behavior, and noise detection, and interrupt on release 40h 24h Page 38 Changed - Averaging Control updated register bits - moved SAMP_AVG[2:0] bits and added SAMP_- TIME bit 1. Default changed 39h 2Bh Page 41 New - Multiple Touch Pattern Configuration new register for Multiple Touch Pattern configuration - enable and threshold settings 80h  2015 Microchip Technology Inc. DS00001623B-page 67 CAP1126 2Dh Page 42 New - Multiple Touch Pattern Register new register for Multiple Touch Pattern detection circuitry - pattern or number of sensor inputs 3Fh 2Fh Page 43 Changed - Recalibration Configuration updated register - updated CAL_CFG bit decode to add a 128 averages setting and removed highest time setting. Default changed. Added bit 6 NO_CLR_INTD and bit 5 NO_CLR_NEG. 8Ah 38h Page 44 Changed - Sensor Input Noise Threshold updated register bits - removed bits 7 - 3 and consolidated all controls into bits 1 - 0. These bits will set the noise threshold for all channels. Default changed 01h 39h Removed - Noise Threshold Register 2 removed register n/a 41h Page 45 Changed - Standby Configuration updated register bits - moved STBY_AVG[2:0] bits and added STBY_- TIME bit 1. Default changed 39h 77h Page 51 New - Linked LED Transition Control new register to control transition effect when LED linked to sensor inputs 00h 79h Page 51 New - LED Mirror Control new register to control LED output mirroring for brightness control when polarity changed 00h 90h Page 57 Changed - LED Pulse 1 Duty Cycle changed bit decode to be more logarithmic F0h 91h Page 57 Changed - LED Pulse 2 Duty Cycle changed bit decode to be more logarithmic F0h 92h Page 57 Changed - LED Breathe Duty Cycle changed bit decode to be more logarithmic F0h 93h Page 57 Changed - LED Direct Duty Cycle changed bit decode to be more logarithmic F0h 95h Added controls - LED Off Delay Added bits 6-4 BR_OFF_DLY[2:0] Added bit 3 DIR_OFF_DLY[3] 00h FDh Page 62 Changed - Product ID Changed bit decode for CAP1126 53h Table A.1 Register Delta From CAP1026 to CAP1126 (continued) Address Register Delta Delta Default CAP1126 DS00001623B-page 68  2015 Microchip Technology Inc. APPENDIX B: DATA SHEET REVISION HISTORY Revision Section/Figure/Entry Correction DS00001623B (02-09-15) Features, Table 2-1, Table 2- 2, "Pin Types", Section 5.0, "General Description" References to BC-Link Interface, BC_DATA, BC_- CLK, BC-IRQ#, BC-Link bus have been removed Application Note under Table 2-6 [BC-Link] hidden in data sheet Table 3-2, "Electrical Specifications" BC-Link Timing Section hidden in data sheet Table 4-1 Protocol Used for 68K Pull Down Resistor changed from “BC-Link Communications” to “Reserved” Section 4.2.2, "SMBus Address and RD / WR Bit" Replaced “client address” with “slave address” in this section. Section 4.2.4, SMBus ACK and NACK Bits, Section 4.2.5, SMBus Stop Bit,Section 4.2.7, SMBus and I2C Compatibility Replaced “client” with “slave” in these sections. Table 4-4, "Read Byte Protocol" Heading changed from “Client Address” to “Slave Address” Table 6-1 Register Name for Register Address 77h changed from “LED Linked Transition Control” to “Linked LED Transition Control” Section 6.30 changed CS2 to LED2 Section 7.7 Package Marking Updated package drawing Appendix A: Device Delta changed 2Dh to 2Fh in item #12 Product Identification System Removed BC-Link references REV A REV A replaces previous SMSC version Rev. 1.32 (01-05-12) Rev. 1.32 (01-05-12) Table 3-2, "Electrical Specifications" Added conditions for tHD:DAT. Section 4.2.7, "SMBus and I2C Compatibility" Renamed from “SMBus and I2C Compliance.” First paragraph, added last sentence: “For information on using the CAP1188 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I 2C Systems.” Added: CAP1188 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. Section 6.4, "Sensor Input Delta Count Registers" Changed negative value cap from FFh to 80h. Rev. 1.31 (08-18-11) Section 4.3.3, "SMBus Send Byte" Added an application note: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Section 4.3.4, "SMBus Receive Byte" Added an application note: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Rev. 1.3 (05-18-11) Section 6.42, "Revision Register" Updated revision ID from 82h to 83h. Rev. 1.2 (02-10-11) Section A.8, "Delta from Rev B (Mask B0) to Rev C (Mask B1)" Added. Cover Corrected block diagram. ALERT#/BC_IRQ# is an output, not an input.  2015 Microchip Technology Inc. DS00001623B-page 69 CAP1126 Table 2-1, "Pin Description for CAP1126" Changed value in “Unused Connection” column for the ADDR_COMM pin from “Connect to Ground” to “n/a“. Table 3-2, "Electrical Specifications" PSR improvements made in functional revision B. Changed PSR spec from ±100 typ and ±200 max counts / V to ±3 and ±10 counts / V. Conditions updated. Section 5.5.2, "Recalibrating Sensor Inputs" Added more detail with subheadings for each type of recalibration. Section 6.6, "Configuration Registers" Added bit 5 BLK_PWR_CTRL to the Configuration 2 Register 44h. The TIMEOUT bit is set to ‘1’ by default for functional revision B and is set to ‘0’ by default for functional revision C. Section 6.42, "Revision Register" Updated revision ID in register FFh from 81h to 82h. Rev. 1.1 (11-17-10) Document Updated for functional revision B. See Section A.7, "Delta from Rev A (Mask A0) to Rev B (Mask B0)". Cover Added to General Description: “includes circuitry and support for enhanced sensor proximity detection.” Added the following Features: Calibrates for Parasitic Capacitance Analog Filtering for System Noise Sources Press and Hold feature for Volume-like Applications Table 3-2, "Electrical Specifications" Conditions for Power Supply Rejection modified adding the following: Sampling time = 2.56ms Averaging = 1 Negative Delta Counts = Disabled All other parameters default Section 6.11, "Calibration Activate Register" Updated register description to indicate which re-calibration routine is used. Section 6.14, "Multiple Touch Configuration Register" Updated register description to indicate what will happen. Table 6-34, "CSx_BN_TH Bit Decode" Table heading changed from “Threshold Divide Setting” to “Percent Threshold Setting”. Rev. 1.0 (06-14-10) Initial release Revision Section/Figure/Entry Correction CAP1126 DS00001623B-page 70  2015 Microchip Technology Inc. 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Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2015 Microchip Technology Inc. DS00001623B-page 71 CAP1126 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] - 1 - XXX - [X](1) l l l l Device Temperature Package Tape and Reel Range Option Example: Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Device: CAP1126 Temperature Range: Blank = 0°C to +85°C (Extended Commercial) Package: AP = QFN Tape and Reel Option: TR = Tape and Reel(1) CAP1126-1-AP-TR 16-pin QFN 4mm x 4mm (RoHS compliant) Six capacitive touch sensor inputs, Two LED drivers, Dedicated Wake, Reset, SMBus / BC-Link / SPI interfaces Reel size is 4,000 pieces CAP1126 DS00001623B-page 72  2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. 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Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632770332 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2015 Microchip Technology Inc. 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DS00001622B-page 1 General Description The CAP1128, which incorporates RightTouch® technology, is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains eight (8) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1128 also contains two (2) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. The CAP1128 includes Multiple Pattern Touch recognition that allows the user to select a specific set of buttons to be touched simultaneously. If this pattern is detected, then a status bit is set and an interrupt generated. Additionally, the CAP1128 includes circuitry and support for enhanced sensor proximity detection. The CAP1128 offers multiple power states operating at low quiescent currents. In the Standby state of operation, one or more capacitive touch sensor inputs are active and all LEDs may be used. If a touch is detected, it will wake the system using the WAKE/SPI_MOSI pin. Deep Sleep is the lowest power state available, drawing 5uA (typical) of current. In this state, no sensor inputs are active. Driving the WAKE/SPI_MOSI pin or communications will wake the device. Applications • Desktop and Notebook PCs • LCD Monitors • Consumer Electronics • Appliances Features • Eight (8) Capacitive Touch Sensor Inputs - Programmable sensitivity - Automatic recalibration - Individual thresholds for each button • Proximity Detection • Multiple Button Pattern Detection • Calibrates for Parasitic Capacitance • Analog Filtering for System Noise Sources • Press and Hold feature for Volume-like Applications • Multiple Communication Interfaces - SMBus / I2C compliant interface - SPI communications - Pin selectable communications protocol and multiple slave addresses (SMBus / I2C only) • Low Power Operation - 5uA quiescent current in Deep Sleep - 50uA quiescent current in Standby (1 sensor input monitored) - Samples one or more channels in Standby • Two (2) LED Driver Outputs - Open Drain or Push-Pull - Programmable blink, breathe, and dimness controls - Can be linked to Capacitive Touch Sensor inputs • Dedicated Wake output flags touches in low power state • System RESET pin • Available in 20-pin 4mm x 4mm QFN RoHS compliant package CAP1128 8 Channel Capacitive Touch Sensor with 2 LED Drivers CAP1128 DS00001622B-page 2  2015 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2015 Microchip Technology Inc. DS00001622B-page 3 CAP1128 Table of Contents 1.0 Block Diagram ................................................................................................................................................................................. 4 2.0 Pin Description ................................................................................................................................................................................ 5 3.0 Electrical Specifications .................................................................................................................................................................. 9 4.0 Communications ........................................................................................................................................................................... 12 5.0 General Description ...................................................................................................................................................................... 23 6.0 Register Description ...................................................................................................................................................................... 29 7.0 Package Information ..................................................................................................................................................................... 67 Appendix A: Device Delta ................................................................................................................................................................... 72 Appendix B: Data Sheet Revision History ........................................................................................................................................... 74 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77 CAP1128 DS00001622B-page 4  2015 Microchip Technology Inc. 1.0 BLOCK DIAGRAM SMBus / BC-Link / SPI Slave Protocol SMCLK/ BC_CLK / SPI_CLK SMDATA / BC_DATA/ SPI_MSIO / SPI_MISO VDD GND ALERT# / BC_IRQ# Capacitive Touch Sensing Algorithm LED1 CS1 CS2 CS3 CS4 CS5 CS6 LED Driver, Breathe, and Dimness control WAKE / SPI_MOSI CS7 CS8 RESET ADDR_COMM SPI_CS# LED2  2015 Microchip Technology Inc. DS00001622B-page 5 CAP1128 2.0 PIN DESCRIPTION FIGURE 2-1: CAP1128 Pin Diagram (20-Pin QFN) TABLE 2-1: PIN DESCRIPTION FOR CAP1128 Pin Number Pin Name Pin Function Pin Type Unused Connection 1 SPI_CS# Active low chip-select for SPI bus DI (5V) Connect to Ground 2 WAKE / SPI_- MOSI WAKE - Active high wake / interrupt output Standby power state - requires pull-down resistor DO Pull-down WAKE - Active high wake input - requires pull-down Resistor resistor Deep Sleep power state DI SPI_MOSI - SPI Master-Out-Slave-In port when used in normal mode DI (5V) Connect to Ground 1 2 3 4 15 14 13 12 20 19 18 17 6 7 8 9 GND ALERT# / BC_IRQ# WAKE / SPI_MOSI SPI_CS# SMCLK / BC_CLK / SPI_CLK SMDAT / BC_DATA / SPI_MSIO / SPI_MISO CS7 RESET CS5 CS6 5 10 11 16 VDD CS1 CS2 CS4 CS8 CS3 N/C* LED1 LED2 ADDR_COMM CAP1128 20 pin QFN N/C* *N/C pins must be connected to ground CAP1128 DS00001622B-page 6  2015 Microchip Technology Inc. 3 SMDATA / SPI_MSIO / SPI_MISO SMDATA - Bi-directional, open-drain SMBus data - requires pull-up resistor DIOD (5V) n/a SPI_MSIO - SPI Master-Slave-In-Out bidirectional port when used in bi-directional mode DIO SPI_MISO - SPI Master-In-Slave-Out port when used in normal mode DO 4 SMCLK / SPI_- CLK SMCLK - SMBus clock input - requires pull-up resistor DI (5V) SPI_CLK - SPI clock input DI (5V) n/a 5 N/C Not Internally Connected n/a Connect to Ground 6 LED1 Open drain LED 1 driver (default) OD (5V) Connect to Ground Push-pull LED 1 driver DO leave open or connect to Ground 7 LED2 Open drain LED 2 driver (default) OD (5V) Connect to Ground Push-pull LED 2 driver DO leave open or connect to Ground 8 N/C Not Internally Connected n/a Connect to Ground 9 RESET Active high soft reset for system - resets all registers to default values. If not used, connect to ground. DI (5V) Connect to Ground 10 ALERT# ALERT# - Active low alert / interrupt output for SMBus alert or SPI interrupt OD (5V) Connect to Ground ALERT# - Active high push-pull alert / interrupt output for SMBus alert or SPI interrupt DO leave open 11 ADDR_COMM Address / communications select pin - pull-down resistor determines address / communications mechanism AI n/a 12 CS8 Capacitive Touch Sensor Input 8 AIO Connect to Ground 13 CS7 Capacitive Touch Sensor Input 7 AIO Connect to Ground 14 CS6 Capacitive Touch Sensor Input 6 AIO Connect to Ground 15 CS5 Capacitive Touch Sensor Input 5 AIO Connect to Ground 16 CS4 Capacitive Touch Sensor Input 4 AIO Connect to Ground TABLE 2-1: PIN DESCRIPTION FOR CAP1128 (CONTINUED) Pin Number Pin Name Pin Function Pin Type Unused Connection  2015 Microchip Technology Inc. DS00001622B-page 7 CAP1128 APPLICATION NOTE: When the ALERT# pinis configured as an active low output, it will be open drain. When it is configured as an active high output, it will be push-pull. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the CAP1128 is unpowered. APPLICATION NOTE: The SPI_CS# pin should be grounded when SMBus, or I2C,communications are used. The pin types are described in Table 2-2. All pins labeled with (5V) are 5V tolerant. 17 CS3 Capacitive Touch Sensor Input 3 AIO Connect to Ground 18 CS2 Capacitive Touch Sensor Input 2 AIO Connect to Ground 19 CS1 Capacitive Touch Sensor Input 1 AIO Connect to Ground 20 VDD Positive Power supply Power n/a Bottom Pad GND Ground Power n/a TABLE 2-2: PIN TYPES Pin Type Description Power This pin is used to supply power or ground to the device. DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant. AIO Analog Input / Output -This pin is used as an I/O for analog signals. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. DO Push-pull Digital Output - This pin is used as a digital output and can sink and source current. DIO Push-pull Digital Input / Output - This pin is used as an I/O for digital signals. TABLE 2-1: PIN DESCRIPTION FOR CAP1128 (CONTINUED) Pin Number Pin Name Pin Function Pin Type Unused Connection CAP1128 DS00001622B-page 8  2015 Microchip Technology Inc. 3.0 ELECTRICAL SPECIFICATIONS Note 3-1 Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3-2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V5VT_PIN and VDD must never exceed 3.6V. Note 3-3 The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 3x3 matrix of 0.3mm (12mil) vias at 1.0mm pitch connected to the ground plane with a 2.5 x 2.5mm thermal landing. Note 3-4 Junction to Ambient (θJA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the θJA is approximately 60°C/W including localized PCB temperature increase. TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Voltage on 5V tolerant pins (V5VT_PIN) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_PIN - VDD|) Note 3-2 0 to 3.6 V Voltage on VDD pin -0.3 to 4 V Voltage on any other pin to GND -0.3 to VDD + 0.3 V Package Power Dissipation up to TA = 85°C for 20 pin QFN (see Note 3-3) 0.9 W Junction to Ambient (θJA) (see Note 3-4) 58 °C/W Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 8000 V  2015 Microchip Technology Inc. DS00001622B-page 9 CAP1128 TABLE 3-2: ELECTRICAL SPECIFICATIONS VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions DC Power Supply Voltage VDD 3.0 3.3 3.6 V Supply Current ISTBY 120 170 uA Standby state active 1 sensor input monitored No LEDs active Default conditions (8 avg, 70ms cycle time) ISTBY 50 uA Standby state active 1 sensor input monitored No LEDs active 1 avg, 140ms cycle time, IDSLEEP 5 15 uA Deep Sleep state active LEDs at 100% or 0% Duty Cycle No communications TA < 40°C 3.135 < VDD < 3.465V IDD 500 600 uA Capacitive Sensing Active No LEDs active Capacitive Touch Sensor Inputs Maximum Base Capacitance CBASE 50 pF Pad untouched Minimum Detectable Capacitive Shift ΔCTOUCH 20 fF Pad touched - default conditions (1 avg, 35ms cycle time, 1x sensitivity) Recommended Cap Shift ΔCTOUCH 0.1 2 pF Pad touched - Not tested Power Supply Rejection PSR ±3 ±10 counts / V Untouched Current Counts Base Capacitance 5pF - 50pF Maximum sensitivity Negative Delta Counts disabled All other parameters default Timing RESET Pin Delay tRST_DLY 10 ms Time to communications ready tCOMM_DLY 15 ms Time to first conversion ready tCONV_DLY 170 200 ms LED Drivers Duty Cycle DUTYLED 0 100 % Programmable Drive Frequency fLED 2 kHz Sinking Current ISINK 24 mA VOL = 0.4 Sourcing Current ISOURCE 24 mA VOH = VDD - 0.4 Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered I/O Pins Output Low Voltage VOL 0.4 V ISINK_IO = 8mA Output High Voltage VOH VDD - 0.4 V ISOURCE_IO = 8mA CAP1128 DS00001622B-page 10  2015 Microchip Technology Inc. Note 3-5 The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage. Note 3-6 The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage. Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered RESET Pin Release to conversion ready tRESET 170 200 ms SMBus Timing Input Capacitance CIN 5 pF Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 us Start Setup Time tSU:STA 0.6 us Start Hold Time tHD:STA 0.6 us Stop Setup Time tSU:STO 0.6 us Data Hold Time tHD:DAT 0 us When transmitting to the master Data Hold Time tHD:DAT 0.3 us When receiving from the master Data Setup Time tSU:DAT 0.6 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line SPI Timing Clock Period tP 250 ns Clock Low Period tLOW 0.4 x tP 0.6 x tP ns Clock High Period tHIGH 0.4 x tP 0.6 x tP ns Clock Rise / Fall time tRISE / tFALL 0.1 x tP ns Data Output Delay tD:CLK 10 ns Data Setup Time tSU:DAT 20 ns Data Hold Time tHD:DAT 20 ns SPI_CS# to SPI_CLK setup time tSU:CS 0 ns Wake Time tWAKE 10 20 us SPI_CS# asserted to CLK assert TABLE 3-2: ELECTRICAL SPECIFICATIONS (CONTINUED) VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions  2015 Microchip Technology Inc. DS00001622B-page 11 CAP1128 4.0 COMMUNICATIONS 4.1 Communications The CAP1128communicates using the 2-wire SMBus or I2C bus, the 2-wire proprietary BC-Link, or the SPI bus. If the proprietary BC-Link protocol is required for your application, please contact your Microchip representative for ordering instructions. Regardless of communication mechanism, the device functionality remains unchanged. The communications mechanism as well as the SMBus (or I2C) slave address is determined by the resistor connected between the ADDR_COMM pin and ground as shown in Table 4-1. 4.1.1 SMBUS (I2C) COMMUNICATIONS When configured to communicate via the SMBus, the CAP1128 supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block. In addition, the device supports I2C formatting for block read and block write protocols. APPLICATION NOTE: For SMBus/I2C communications, the SPI_CS# pin is not used and should be grounded; any data presented to this pin will be ignored. See Section 4.2 and Section 4.3 for more information on the SMBus bus and protocols respectively. 4.1.2 SPI COMMUNICATIONS When configured to communicate via the SPI bus, the CAP1128supports both bi-directional 3-wire and normal 4-wire protocols and uses the SPI_CS# pin to enable communications. APPLICATION NOTE: See Section 4.5 and Section 4.6 for more information on the SPI bus and protocols respectively.Upon power up, the CAP1128 will not respond to any communications for up to 15ms. After this time, full functionality is available. 4.2 System Management Bus The CAP1128 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1128 will not stretch the clock signal. TABLE 4-1: ADDR_COMM PIN DECODE Pull-Down Resistor (+/- 5%) Protocol Used SMBus Address GND SPI Communications using Normal 4-wire Protocol Used n/a 56k SPI Communications using BiDirectional 3-wire Protocol Used n/a 68k Reserved n/a 82k SMBus / I2C 0101_100(r/w) 100k SMBus / I2C 0101_011(r/w) 120k SMBus / I2C 0101_010(r/w) 150k SMBus / I2C 0101_001(r/w) VDD SMBus / I2C 0101_000(r/w) CAP1128 DS00001622B-page 12  2015 Microchip Technology Inc. 4.2.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.2.2 SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the slave device. See Table 4-1 for available SMBus addresses. 4.2.3 SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.2.4 SMBUS ACK AND NACK BITS The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives except the last data byte. 4.2.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1128 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. 4.2.6 SMBUS TIMEOUT The CAP1128 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the SMCLK pin is held low, the device will timeout and reset the SMBus interface. The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register (see Section 6.6, "Configuration Registers"). 4.2.7 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the CAP1128 in an I2C system, refer to AN 14.0 Dedicated Slave Devices in I2C Systems. FIGURE 4-1: SMBus Timing Diagram SMDATA SMCLK TLOW TRISE THIGH TFALL TBUF THD:STA P S S - Start Condition P - Stop Condition THD:DAT TSU:DAT TSU:STA THD:STA P TSU:STO S  2015 Microchip Technology Inc. DS00001622B-page 13 CAP1128 1. CAP1128 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2. Minimum frequency for SMBus communications is 10kHz. 3. The SMBus slave protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the CAP1128 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4. The SMBus slave protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200µs (idle condition). This function is disabled by default in the CAP1128 and can be enabled by writing to the TIMEOUT bit. I2C does not have an idle condition. 5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). 6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. The CAP1128 supports I2C formatting only. 4.3 SMBus Protocols The CAP1128 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid protocols as shown below. All of the below protocols use the convention in Table 4-2. 4.3.1 SMBUS WRITE BYTE The Write Byte is used to write one byte of data to a specific register as shown in Table 4-3. 4.3.2 SMBUS READ BYTE The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4-4. 4.3.3 SMBUS SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4-5. APPLICATION NOTE: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). TABLE 4-2: PROTOCOL FORMAT Data Sent to Device Data Sent to the HOst Data sent Data sent TABLE 4-3: WRITE BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK Stop 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1 TABLE 4-4: READ BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data NACK Stop 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh 1 0 -> 1 TABLE 4-5: SEND BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Stop 1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 CAP1128 DS00001622B-page 14  2015 Microchip Technology Inc. 4.3.4 SMBUS RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4-6. APPLICATION NOTE: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.4 I2C Protocols The CAP1128 supports I2C Block Write and Block Read. The protocols listed below use the convention in Table 4-2. 4.4.1 BLOCK WRITE The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 4-7. APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.4.2 BLOCK READ The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 4-8. APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.5 SPI Interface The SMBus has a predefined packet structure, the SPI does not. The SPI Bus can operate in two modes of operation, normal 4-wire mode and bi-directional 3-wire mode. All SPI commands consist of 8-bit packets sent to a specific slave device (identified by the CS pin). The SPI bus will latch data on the rising edge of the clock and the clock and data both idle high. All commands are supported via both operating modes. The supported commands are: Reset Serial interface, set address pointer, write command and read command. Note that all other codes received during the command phase are ignored and have no effect on the operation of the device. TABLE 4-6: RECEIVE BYTE PROTOCOL Start Slave Address RD ACK Register Data NACK Stop 1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1 TABLE 4-7: BLOCK WRITE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK . . . Register Data ACK Stop XXh 0 XXh 0 . . . XXh 0 0 -> 1 TABLE 4-8: BLOCK READ PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK . . . Register Data NACK Stop 0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1  2015 Microchip Technology Inc. DS00001622B-page 15 CAP1128 4.5.1 SPI NORMAL MODE The SPI Bus can operate in two modes of operation, normal and bi-directional mode. In the normal mode of operation, there are dedicated input and output data lines. The host communicates by sending a command along the CAP1128 SPI_MOSI data line and reading data on the SPI_MISO data line. Both communications occur simultaneously which allows for larger throughput of data transactions. All basic transfers consist of two 8 bit transactions from the Master device while the slave device is simultaneously sending data at the current address pointer value. Data writes consist of two or more 8-bit transactions. The host sends a specific write command followed by the data to write the address pointer. Data reads consist of one or more 8-bit transactions. The host sends the specific read data command and continues clocking for as many data bytes as it wishes to receive. 4.5.2 SPI BI-DIRECTIONAL MODE In the bi-directional mode of operation, the SPI data signals are combined into the SPI_MSIO line, which is shared for data received by the device and transmitted by the device. The protocol uses a simple handshake and turn around sequence for data communications based on the number of clocks transmitted during each phase. All basic transfers consist of two 8 bit transactions. The first is an 8 bit command phase driven by the Master device. The second is by an 8 bit data phase driven by the Master for writes, and by the CAP1128 for read operations. The auto increment feature of the address pointer allows for successive reads or writes. The address pointer will return to 00h after reaching FFh. 4.5.3 SPI_CS# PIN The SPI Bus is a single master, multiple slave serial bus. Each slave has a dedicated CS pin (chip select) that the master asserts low to identify that the slave is being addressed. There are no formal addressing options. 4.5.4 ADDRESS POINTER All data writes and reads are accessed from the current address pointer. In both Bi-directional mode and Full Duplex mode, the Address pointer is automatically incremented following every read command or every write command. The address pointer will return to 00h after reaching FFh. 4.5.5 SPI TIMEOUT The CAP1128 does not detect any timeout conditions on the SPI bus. FIGURE 4-2: SPI Timing SPI_MSIO or SPI_MOSI or SPI_MISO SPI_CLK tLOW tRISE tHIGH tFALL tD:CLK tHD:DAT tSU:DAT tP  2015 Microchip Technology Inc. DS00001622B-page 16 CAP1128 4.6 Normal SPI Protocols When operating in normal mode, the SPI bus internal address pointer is incremented depending upon which command has been transmitted. Multiple commands may be transmitted sequentually so long as the SPI_CS# pin is asserted low. Figure 4-3 shows an example of this operation. 4.6.1 RESET INTERFACE Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation. FIGURE 4-3: Example SPI Bus Communication - Normal Mode SPI_CS# SPI_MISO SPI_MOSI SPI Address Pointer SPI Data output buffer Register Address / Data 7Ah XXh (invalid) XXh (invalid) YYh (invalid) 7Ah 7Dh 41h YYh (invalid) 7Eh 66h XXh (invalid) 45h 7Dh 41h AAh (invalid) AAh (invalid) 7Fh 7Fh 55h (invalid) 66h 7Fh AAh 7Dh 43h 40h 78h 7Fh XXh (invalid) 7Fh 56h 40h / 56h 41h / 45h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 45h 40h / 56h 41h / 45h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 42h AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 55h 7Fh AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 66h 42h AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 44h 80h 40h 80h 40h 56h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 43h 55h 7Fh 7Fh 55h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 80h 45h 43h 46h 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 00h XXh Indicates SPI Address pointer incremented  2015 Microchip Technology Inc. DS00001622B-page 17 CAP1128 4.6.2 SET ADDRESS POINTER The Set Address Pointer command sets the Address pointer for subsequent reads and writes of data. The pointer is set on the rising edge of the final data bit. At the same time, the data that is to be read is fetched and loaded into the internal output buffer but is not transmitted. 4.6.3 WRITE DATA The Write Data protocol updates the contents of the register referenced by the address pointer. As the command is processed, the data to be read is fetched and loaded into the internal output buffer but not transmitted. Then, the register is updated with the data to be written. Finally, the address pointer is incremented. FIGURE 4-4: SPI Reset Interface Command - Normal Mode FIGURE 4-5: SPI Set Address Pointer Command - Normal Mode Master SPDOUT SPI_MOSI SPI_CS# SPI_CLK Reset - 7Ah Reset - 7Ah Invalid register data 00h – Internal Data buffer empty SPI_MISO Master Drives Slave Drives ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ Master SPDOUT SPI_MOSI Register Address SPI_CS# SPI_CLK Set Address Pointer – 7Dh SPI_MISO Unknown, Invalid Data Unknown, Invalid Data Master Drives Slave Drives Address pointer set ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ CAP1128 DS00001622B-page 18  2015 Microchip Technology Inc. 4.6.4 READ DATA The Read Data protocol is used to read data from the device. During the normal mode of operation, while the device is receiving data, the CAP1128 is simultaneously transmitting data to the host. For the Set Address commands and the Write Data commands, this data may be invalid and it is recommended that the Read Data command is used. FIGURE 4-6: SPI Write Command - Normal Mode FIGURE 4-7: SPI Read Command - Normal Mode Master SPDOUT SPI_MOSI Data to Write SPI_CS# SPI_CLK Write Command – 7Eh Unknown, Invalid Data Old Data at Current Address Pointer SPI_MISO Master Drives Slave Drives 1. Data written at current address pointer 2. Address pointer incremented Master SPDOUT SPI_MOSI Master Drives Slave Drives SPI_CLK First Read Command – 7Fh SPI_CS# SPI_MISO Invalid, Unknown Data * ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Subsequent Read Commands – 7F Data at Current Address Pointer Address Pointer Incremented ** ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ * The first read command after any other command will return invalid data for the first byte. Subsequent read commands will return the data at the Current Address Pointer ** The Address Pointer is incremented 8 clocks after the Read Command has been received. Therefore continually sending Read Commands will result in each command reporting new data. Once Read Commands have been finished, the last data byte will be read during the next 8 clocks for any command  2015 Microchip Technology Inc. DS00001622B-page 19 CAP1128 4.7 Bi-Directional SPI Protocols 4.7.1 RESET INTERFACE Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation. 4.7.2 SET ADDRESS POINTER Sets the address pointer to the register to be accessed by a read or write command. This command overrides the autoincrementing of the address pointer. FIGURE 4-8: SPI Read Command - Normal Mode - Full FIGURE 4-9: SPI Reset Interface Command - Bi-directional Mode Master SPDOUT SPI_MOSI Master Drives Slave Drives SPI_CLK Read Command – 7Fh SPI_CS# Data at previously set register address = current address pointer SPI_MISO ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Data at previously set register address = current address pointer (SPI) XXh 1. Register Read Address updated to Current SPI Read Address pointer 1. Register data loaded into output buffer = data at current address pointer 1. Output buffer transmitted = data at previous address pointer + 1 = current address pointer 1. Register Read Address incremented = current address pointer + 1 1. SPI Read Address Incremented = new current address pointer 2. Register Read Address Incremented = current address pointer +1 Register Data loaded into Output buffer = data at current address pointer + 1 1. Output buffer transmitted = data at current address pointer + 1 2. Flag set to increment SPI Read Address at end of next 8 clocks ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Data at previously set register address = current address pointer (SPI) 1. Register data loaded into output buffer = data at current address pointer 1. Output buffer transmitted = data at previous register address pointer + 1 = current address pointer 1. Output buffer transmitted = data at current address pointer + 1 2. Flag set to increment SPI Read Address at end of next 8 clocks Subsequent Read Commands – 7Fh 1. Register Read Address updated to Current SPI Read Address pointer. 2. Register Read Address incremented = current address pointer +1 – end result = register address pointer doesn’t change Master SPDOUT SPI_MSIO SPI_CS# SPI_CLK Reset - 7Ah Reset - 7Ah ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ CAP1128 DS00001622B-page 20  2015 Microchip Technology Inc. 4.7.3 WRITE DATA Writes data value to the register address stored in the address pointer. Performs auto increment of address pointer after the data is loaded into the register. 4.7.4 READ DATA Reads data referenced by the address pointer. Performs auto increment of address pointer after the data is transferred to the Master. FIGURE 4-10: SPI Set Address Pointer Command - Bi-directional Mode FIGURE 4-11: SPI Write Data Command - Bi-directional Mode FIGURE 4-12: SPI Read Data Command - Bi-directional Mode Master SPDOUT SPI_MSIO Register Address SPI_CS# SPI_CLK Set Address Pointer – 7Dh ‘0’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Master SPDOUT SPI_MSIO Register Write Data SPI_CS# SPI_CLK Write Command – 7Eh ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ Master SPDOUT SPI_MSIO Master Drives Slave Drives Indeterminate Register Read Data SPI_CLK Read Command – 7Fh SPI_CS# ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’  2015 Microchip Technology Inc. DS00001622B-page 21 CAP1128 4.8 BC-Link Interface The BC-Link is a proprietary bus developed to allow communication between a host controller device to a companion device. This device uses this serial bus to read and write registers and for interrupt processing. The interface uses a data port concept, where the base interface has an address register, data register and a control register, defined in the 8051’s SFR space. Refer to documentation for the BC-Link compatible host controller for details on how to access the CAP1128 via the BCLink Interface. CAP1128 DS00001622B-page 22  2015 Microchip Technology Inc. 5.0 GENERAL DESCRIPTION The CAP1128 is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains eight (8) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1128 also contains two (2) low side (or push-pull) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. Finally, the device contains a dedicated RESET pin to act as a soft reset by the system. The CAP1128 offers multiple power states. It operates at the lowest quiescent current during its Deep Sleep state. In the low power Standby state, it can monitor one or more channels and respond to communications normally. The device contains a wake pin (WAKE/SPI_MOSI) output to wake the system when a touch is detected in Standby and to wake the device from Deep Sleep. The device communicates with a host controller using the SPI bus, or via SMBus / I2C. The host controller may poll the device for updated information at any time or it may configure the device to flag an interrupt whenever a touch is detected on any sensor pad. A typical system diagram is shown in Figure 5-1.  2015 Microchip Technology Inc. DS00001622B-page 23 CAP1128 FIGURE 5-1: System Diagram for CAP1128 CAP1128 CS6 SMDATA / BC_DATA / SPI_MSIO / SPI_MISO SMCLK / BC_CLK / SPI_CLK VDD Embedded Controller ALERT# / BC_IRQ# CS4 CS2 3.3V – 5V CS5 CS3 CS1 WAKE / SPI_MOSI CS7 CS8 RESET SPI_CS# ADDR_COMM LED1 LED2 3.3V – 5V Touch Button Touch Button Touch Button Touch Button Touch Button Touch Button Touch Button Touch Button CAP1128 DS00001622B-page 24  2015 Microchip Technology Inc. 5.1 Power States The CAP1128 has three operating states depending on the status of the STBY and DSLEEP bits. When the device transitions between power states, previously detected touches (for inactive channels) are cleared and the status bits reset. 1. Fully Active - The device is fully active. It is monitoring all active capacitive sensor inputs and driving all LED channels as defined. 2. Standby - The device is in a lower power state. It will measure a programmable number of channels using the Standby Configuration controls (see Section 6.20 through Section 6.22). Interrupts will still be generated based on the active channels. The device will still respond to communications normally and can be returned to the Fully Active state of operation by clearing the STBY bit. 3. Deep Sleep - The device is in its lowest power state. It is not monitoring any capacitive sensor inputs and not driving any LEDs. All LEDs will be driven to their programmed non-actuated state and no PWM operations will be done. While in Deep Sleep, the device can be awakened by SMBus or SPI communications targeting the device. This will not cause the DSLEEP to be cleared so the device will return to Deep Sleep once all communications have stopped. If the device is not communicating via the 4-wire SPI bus, then during this state of operation, if the WAKE/SPI_MOSI pin is driven high by an external source, the device will clear the DSLEEP bit and return to Fully Active. APPLICATION NOTE: In the Deep Sleep state, the LED output will be either high or low and will not be PWM’d at the min or max duty cycle. 5.2 RESET Pin The RESET pin is an active high reset that is driven from an external source. While it is asserted high, all the internal blocks will be held in reset including the communications protocol used. No capacitive touch sensor inputs will be sampled and the LEDs will not be driven. All configuration settings will be reset to default states and all readings will be cleared. The device will be held in Deep Sleep that can only be removed by driving the RESET pin low. This will cause the RESET status bit to be set to a logic ‘1’ and generate an interrupt. 5.3 WAKE/SPI_MOSI Pin Operation The WAKE / SPI_MOSI pin is a multi-function pin depending on device operation. When the device is configured to communicate using the 4-wire SPI bus, this pin is an input. However, when the CAP1128 is placed in Standby and is not communicating using the 4-wire SPI protocol, the WAKE pin is an active high output. In this condition, the device will assert the WAKE/SPI_MOSI pin when a touch is detected on one of its sampled sensor inputs. The pin will remain asserted until the INT bit has been cleared and then it will be de-asserted. When the CAP1128 is placed in Deep Sleep and it is not communicating using the 4-wire SPI protocol, the WAKE/SPI_- MOSI pin is monitored by the device as an input. If the WAKE/SPI_MOSI pin is driven high by an external source, the CAP1128will clear the DSLEEP bit causing the device to return to Fully Active. When the device is placed in Deep Sleep, this pin is a High-Z input and must have a pull-down resistor to GND for proper operation. 5.4 LED Drivers The CAP1128 contains two (2) LED drivers. Each LED driver can be linked to its respective capacitive touch sensor input or it can be controlled by the host. Each LED driver can be configured to operate in one of the following modes with either push-pull or open drain drive. 1. Direct - The LED is configured to be on or off when the corresponding input stimulus is on or off (or inverted). The brightness of the LED can be programmed from full off to full on (default). Additionally, the LED contains controls to individually configure ramping on, off, and turn-off delay. 2. Pulse 1 - The LED is configured to “Pulse” (transition ON-OFF-ON) a programmable number of times with programmable rate and min / max brightness. This behavior may be actuated when a press is detected or when a release is detected. 3. Pulse 2 - The LED is configured to “Pulse” while actuated and then “Pulse” a programmable number of times with programmable rate and min / max brightness when the sensor pad is released.  2015 Microchip Technology Inc. DS00001622B-page 25 CAP1128 4. Breathe - The LED is configured to transition continuously ON-OFF-ON (i.e. to “Breathe”) with a programmable rate and min / max brightness. When an LED is not linked to a sensor and is actuated by the host, there’s an option to assert the ALERT# pin when the initiated LED behavior has completed. 5.4.1 LINKING LEDS TO CAPACITIVE TOUCH SENSOR INPUTS All LEDs can be linked to the corresponding capacitive touch sensor input so that when the sensor input detects a touch, the corresponding LED will be actuated at one of the programmed responses. 5.5 Capacitive Touch Sensing The CAP1128 contains eight (8) independent capacitive touch sensor inputs. Each sensor input has dynamic range to detect a change of capacitance due to a touch. Additionally, each sensor input can be configured to be automatically and routinely re-calibrated. 5.5.1 SENSING CYCLE Each capacitive touch sensor input has controls to be activated and included in the sensing cycle. When the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it finishes. The cycle polls through each active sensor input starting with CS1 and extending through CS8. As each capacitive touch sensor input is polled, its measurement is compared against a baseline “Not Touched” measurement. If the delta measurement is large enough, a touch is detected and an interrupt is generated. The sensing cycle time is programmable (see Section 6.10, "Averaging and Sampling Configuration Register"). 5.5.2 RECALIBRATING SENSOR INPUTS There are various options for recalibrating the capacitive touch sensor inputs. Recalibration re-sets the Base Count Registers (Section 6.24, "Sensor Input Base Count Registers") which contain the “not touched” values used for touch detection comparisons. APPLICATION NOTE: The device will recalibrate all sensor inputs that were disabled when it transitions from Standby. Likewise, the device will recalibrate all sensor inputs when waking out of Deep Sleep. 5.5.2.1 Manual Recalibration The Calibration Activate Registers (Section 6.11, "Calibration Activate Register") force recalibration of selected sensor inputs. When a bit is set, the corresponding capacitive touch sensor input will be recalibrated (both analog and digital). The bit is automatically cleared once the recalibration routine has finished. 5.5.2.2 Automatic Recalibration Each sensor input is regularly recalibrated at a programmable rate (see Section 6.17, "Recalibration Configuration Register"). By default, the recalibration routine stores the average 64 previous measurements and periodically updates the base “not touched” setting for the capacitive touch sensor input. Note: During this recalibration routine, the sensor inputs will not detect a press for up to 200ms and the Sensor Base Count Register values will be invalid. In addition, any press on the corresponding sensor pads will invalidate the recalibration. Note: Automatic recalibration only works when the delta count is below the active sensor input threshold. It is disabled when a touch is detected. CAP1128 DS00001622B-page 26  2015 Microchip Technology Inc. 5.5.2.3 Negative Delta Count Recalibration It is possible that the device loses sensitivity to a touch. This may happen as a result of a noisy environment, an accidental recalibration during a touch, or other environmental changes. When this occurs, the base untouched sensor input may generate negative delta count values. The NEG_DELTA_CNT bits (see Section 6.17, "Recalibration Configuration Register") can be set to force a recalibration after a specified number of consecutive negative delta readings. 5.5.2.4 Delayed Recalibration It is possible that a “stuck button” occurs when something is placed on a button which causes a touch to be detected for a long period. By setting the MAX_DUR_EN bit (see Section 6.6, "Configuration Registers"), a recalibration can be forced when a touch is held on a button for longer than the duration specified in the MAX_DUR bits (see Section 6.8, "Sensor Input Configuration Register"). 5.5.3 PROXIMITY DETECTION Each sensor input can be configured to detect changes in capacitance due to proximity of a touch. This circuitry detects the change of capacitance that is generated as an object approaches, but does not physically touch, the enabled sensor pad(s). When a sensor input is selected to perform proximity detection, it will be sampled from 1x to 128x per sampling cycle. The larger the number of samples that are taken, the greater the range of proximity detection is available at the cost of an increased overall sampling time. 5.5.4 MULTIPLE TOUCH PATTERN DETECTION The multiple touch pattern (MTP) detection circuitry can be used to detect lid closure or other similar events. An event can be flagged based on either a minimum number of sensor inputs or on specific sensor inputs simultaneously exceeding an MTP threshold or having their Noise Flag Status Register bits set. An interrupt can also be generated. During an MTP event, all touches are blocked (see Section 6.15, "Multiple Touch Pattern Configuration Register"). 5.5.5 LOW FREQUENCY NOISE DETECTION Each sensor input has an EMI noise detector that will sense if low frequency noise is injected onto the input with sufficient power to corrupt the readings. If this occurs, the device will reject the corrupted sample and set the corresponding bit in the Noise Status register to a logic ‘1’. 5.5.6 RF NOISE DETECTION Each sensor input contains an integrated RF noise detector. This block will detect injected RF noise on the CS pin. The detector threshold is dependent upon the noise frequency. If RF noise is detected on a CS line, that sample is removed and not compared against the threshold. 5.6 ALERT# Pin The ALERT# pin is an active low (or active high when configured) output that is driven when an interrupt event is detected. Whenever an interrupt is generated, the INT bit (see Section 6.1, "Main Control Register") is set. The ALERT# pin is cleared when the INT bit is cleared by the user. Additionally, when the INT bit is cleared by the user, status bits are only cleared if no touch is detected. 5.6.1 SENSOR INTERRUPT BEHAVIOR The sensor interrupts are generated in one of two ways: 1. An interrupt is generated when a touch is detected and, as a user selectable option, when a release is detected (by default - see Section 6.6). See Figure 5-3. 2. If the repeat rate is enabled then, so long as the touch is held, another interrupt will be generated based on the programmed repeat rate (see Figure 5-2). Note: During this recalibration, the device will not respond to touches. Note: Delayed recalibration only works when the delta count is above the active sensor input threshold. If enabled, it is invoked when a sensor pad touch is held longer than the MAX_DUR bit setting.  2015 Microchip Technology Inc. DS00001622B-page 27 CAP1128 When the repeat rate is enabled, the device uses an additional control called MPRESS that determines whether a touch is flagged as a simple “touch” or a “press and hold”. The MPRESS[3:0] bits set a minimum press timer. When the button is touched, the timer begins. If the sensor pad is released before the minimum press timer expires, it is flagged as a touch and an interrupt is generated upon release. If the sensor input detects a touch for longer than this timer value, it is flagged as a “press and hold” event. So long as the touch is held, interrupts will be generated at the programmed repeat rate and upon release (if enabled). APPLICATION NOTE: Figure 5-2 and Figure 5-3 show default operation which is to generate an interrupt upon sensor pad release and an active-low ALERT# pin. APPLICATION NOTE: The host may need to poll the device twice to determine that a release has been detected. FIGURE 5-2: Sensor Interrupt Behavior - Repeat Rate Enabled FIGURE 5-3: Sensor Interrupt Behavior - No Repeat Rate Enabled Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Min Press Setting (280ms) Interrupt on Touch Button Repeat Rate (175ms) Button Repeat Rate (175ms) Interrupt on Release (optional) ALERT# pin (active low) Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Interrupt on Touch Interrupt on Release (optional) ALERT# pin (active low) CAP1128 DS00001622B-page 28  2015 Microchip Technology Inc. 6.0 REGISTER DESCRIPTION The registers shown in Table 6-1 are accessible through the communications protocol. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Address R/W Register Name Function Default Value Page 00h R/W Main Control Controls general power states and power dissipation 00h Page 31 02h R General Status Stores general status bits 00h Page 32 03h R Sensor Input Status Returns the state of the sampled capacitive touch sensor inputs 00h Page 32 04h R LED Status Stores status bits for LEDs 00h Page 32 0Ah R Noise Flag Status Stores the noise flags for sensor inputs 00h Page 33 10h R Sensor Input 1 Delta Count Stores the delta count for CS1 00h Page 34 11h R Sensor Input 2 Delta Count Stores the delta count for CS2 00h Page 34 12h R Sensor Input 3 Delta Count Stores the delta count for CS3 00h Page 34 13h R Sensor Input 4 Delta Count Stores the delta count for CS4 00h Page 34 14h R Sensor Input 5 Delta Count Stores the delta count for CS5 00h Page 34 15h R Sensor Input 6 Delta Count Stores the delta count for CS6 00h Page 34 16h R Sensor Input 7 Delta Count Stores the delta count for CS7 00h Page 34 17h R Sensor Input 8 Delta Count Stores the delta count for CS8 00h Page 34 1Fh R/W Sensitivity Control Controls the sensitivity of the threshold and delta counts and data scaling of the base counts 2Fh Page 34 20h R/W Configuration Controls general functionality 20h Page 36 21h R/W Sensor Input Enable Controls whether the capacitive touch sensor inputs are sampled FFh Page 37 22h R/W Sensor Input Configuration Controls max duration and auto-repeat delay for sensor inputs operating in the full power state A4h Page 38 23h R/W Sensor Input Configuration 2 Controls the MPRESS controls for all sensor inputs 07h Page 39 24h R/W Averaging and Sampling Config Controls averaging and sampling window 39h Page 39 26h R/W Calibration Activate Forces re-calibration for capacitive touch sensor inputs 00h Page 41 27h R/W Interrupt Enable Enables Interrupts associated with capacitive touch sensor inputs FFh Page 41 28h R/W Repeat Rate Enable Enables repeat rate for all sensor inputs FFh Page 42 2Ah R/W Multiple Touch Configuration Determines the number of simultaneous touches to flag a multiple touch condition 80h Page 42  2015 Microchip Technology Inc. DS00001622B-page 29 CAP1128 2Bh R/W Multiple Touch Pattern Configuration Determines the multiple touch pattern (MTP) configuration 00h Page 43 2Dh R/W Multiple Touch Pattern Determines the pattern or number of sensor inputs used by the MTP circuitry FFh Page 44 2Fh R/W Recalibration Configuration Determines re-calibration timing and sampling window 8Ah Page 44 30h R/W Sensor Input 1 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 1 40h Page 46 31h R/W Sensor Input 2 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 2 40h Page 46 32h R/W Sensor Input 3 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 3 40h Page 46 33h R/W Sensor Input 4 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 4 40h Page 46 34h R/W Sensor Input 5 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 5 40h Page 46 35h R/W Sensor Input 6 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 6 40h Page 46 36h R/W Sensor Input 7 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 7 40h Page 46 37h R/W Sensor Input 8 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 8 40h 38h R/W Sensor Input Noise Threshold Stores controls for selecting the noise threshold for all sensor inputs 01h Page 46 Standby Configuration Registers 40h R/W Standby Channel Controls which sensor inputs are enabled while in standby 00h Page 47 41h R/W Standby Configuration Controls averaging and cycle time while in standby 39h Page 47 42h R/W Standby Sensitivity Controls sensitivity settings used while in standby 02h Page 48 43h R/W Standby Threshold Stores the touch detection threshold for active sensor inputs in standby 40h Page 49 44h R/W Configuration 2 Stores additional configuration controls for the device 40h Page 36 Base Count Registers 50h R Sensor Input 1 Base Count Stores the reference count value for sensor input 1 C8h Page 49 51h R Sensor Input 2 Base Count Stores the reference count value for sensor input 2 C8h Page 49 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1128 DS00001622B-page 30  2015 Microchip Technology Inc. 52h R Sensor Input 3 Base Count Stores the reference count value for sensor input 3 C8h Page 49 53h R Sensor Input 4 Base Count Stores the reference count value for sensor input 4 C8h Page 49 54h R Sensor Input 5 Base Count Stores the reference count value for sensor input 5 C8h Page 49 55h R Sensor Input 6 Base Count Stores the reference count value for sensor input 6 C8h Page 49 56h R Sensor Input 7 Base Count Stores the reference count value for sensor input 7 C8h Page 49 57h R Sensor Input 8 Base Count Stores the reference count value for sensor input 8 C8h Page 49 LED Controls 71h R/W LED Output Type Controls the output type for the LED outputs 00h Page 50 72h R/W Sensor Input LED Linking Controls linking of sensor inputs to LED channels 00h Page 50 73h R/W LED Polarity Controls the output polarity of LEDs 00h Page 50 74h R/W LED Output Control Controls the output state of the LEDs 00h Page 51 77h R/W Linked LED Transition Control Controls the transition when LEDs are linked to CS channels 00h Page 52 79h R/W LED Mirror Control Controls the mirroring of duty cycles for the LEDs 00h Page 53 81h R/W LED Behavior 1 Controls the behavior and response of LEDs 1 - 2 00h Page 53 84h R/W LED Pulse 1 Period Controls the period of each breathe during a pulse 20h Page 55 85h R/W LED Pulse 2 Period Controls the period of the breathing during breathe and pulse operation 14h Page 56 86h R/W LED Breathe Period Controls the period of an LED breathe operation 5Dh Page 57 88h R/W LED Config Controls LED configuration 04h Page 58 90h R/W LED Pulse 1 Duty Cycle Determines the min and max duty cycle for the pulse operation F0h Page 58 91h R/W LED Pulse 2 Duty Cycle Determines the min and max duty cycle for breathe and pulse operation F0h Page 58 92h R/W LED Breathe Duty Cycle Determines the min and max duty cycle for the breathe operation F0h Page 58 93h R/W LED Direct Duty Cycle Determines the min and max duty cycle for Direct mode LED operation F0h Page 58 94h R/W LED Direct Ramp Rates Determines the rising and falling edge ramp rates of the LEDs 00h Page 59 95h R/W LED Off Delay Determines the off delay for all LED behaviors 00h Page 60 B1h R Sensor Input 1 Calibration Stores the upper 8-bit calibration value for sensor input 1 00h Page 63 B2h R Sensor Input 2 Calibration Stores the upper 8-bit calibration value for sensor input 2 00h Page 63 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page  2015 Microchip Technology Inc. DS00001622B-page 31 CAP1128 During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. When a bit is “set”, this means that the user writes a logic ‘1’ to it. When a bit is “cleared”, this means that the user writes a logic ‘0’ to it. 6.1 Main Control Register The Main Control register controls the primary power state of the device. Bits 7 - 6 - GAIN[1:0] - Controls the gain used by the capacitive touch sensing circuitry. As the gain is increased, the effective sensitivity is likewise increased as a smaller delta capacitance is required to generate the same delta count values. The sensitivity settings may need to be adjusted along with the gain settings such that data overflow does not occur. APPLICATION NOTE: The gain settings apply to both Standby and Active states. B3h R Sensor Input 3 Calibration Stores the upper 8-bit calibration value for sensor input 3 00h Page 63 B4h R Sensor Input 4 Calibration Stores the upper 8-bit calibration value for sensor input 4 00h Page 63 B5h R Sensor Input 5 Calibration Stores the upper 8-bit calibration value for sensor input 5 00h Page 63 B6h R Sensor Input 6 Calibration Stores the upper 8-bit calibration value for sensor input 6 00h Page 63 B7h R Sensor Input 7 Calibration Stores the upper 8-bit calibration value for sensor input 7 00h Page 63 B8h R Sensor Input 8 Calibration Stores the upper 8-bit calibration value for sensor input 8 00h Page 63 B9h R Sensor Input Calibration LSB 1 Stores the 2 LSBs of the calibration value for sensor inputs 1 - 4 00h Page 63 BAh R Sensor Input Calibration LSB 2 Stores the 2 LSBs of the calibration value for sensor inputs 5 - 8 00h Page 63 FDh R Product ID Stores a fixed value that identifies each product 52h Page 63 FEh R Manufacturer ID Stores a fixed value that identifies Microchip 5Dh Page 64 FFh R Revision Stores a fixed value that represents the revision number 83h Page 64 TABLE 6-2: MAIN CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 00h R/W Main Control GAIN[1:0] STBY DSLEEP - - - INT 00h TABLE 6-3: GAIN BIT DECODE GAIN[1:0] Capacitive Touch Sensor Gain 1 0 0 0 1 01 2 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1128 DS00001622B-page 32  2015 Microchip Technology Inc. Bit 5 - STBY - Enables Standby. • ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - Capacitive touch sensor input scanning is limited to the sensor inputs set in the Standby Channel register (see Section 6.20). The status registers will not be cleared until read. LEDs that are linked to capacitive touch sensor inputs will remain linked and active. Sensor inputs that are no longer sampled will flag a release and then remain in a non-touched state. LEDs that are manually controlled will be unaffected. • Bit 4 - DSLEEP - Enables Deep Sleep by deactivating all functions. This bit will be cleared when the WAKE pin is driven high. ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - All sensor input scanning is disabled. All LEDs are driven to their programmed non-actuated state and no PWM operations will be done. The status registers are automatically cleared and the INT bit is cleared. Bit 0 - INT - Indicates that there is an interrupt. When this bit is set, it asserts the ALERT# pin. If a channel detects a touch and its associated interrupt enable bit is not set to a logic ‘1’, no action is taken. This bit is cleared by writing a logic ‘0’ to it. When this bit is cleared, the ALERT# pin will be deasserted and all status registers will be cleared if the condition has been removed. If the WAKE/SPI_MOSI pin is asserted as a result of a touch detected while in Standby, it will likewise be deasserted when this bit is cleared. Note that the WAKE / SPI_MOSI pin is not driven when communicating via the 4-wire SPI protocol. • ‘0’ - No interrupt pending. • ‘1’ - A touch has been detected on one or more channels and the interrupt has been asserted. 6.2 Status Registers All status bits are cleared when the device enters the Deep Sleep (DSLEEP = ‘1’ - see Section 6.1). 6.2.1 GENERAL STATUS - 02H Bit 4 - LED - Indicates that one or more LEDs have finished their programmed activity. This bit is set if any bit in the LED Status register is set. Bit 3 - RESET - Indicates that the device has come out of reset. This bit is set when the device exits a POR state or when the RESET pin has been deasserted and qualified via the RESET pin filter (see Section 5.2). This bit will cause the INT bit to be set and is cleared when the INT bit is cleared. Bit 2 - MULT - Indicates that the device is blocking detected touches due to the Multiple Touch detection circuitry (see Section 6.14). This bit will not cause the INT bit to be set and hence will not cause an interrupt. Bit 1 - MTP - Indicates that the device has detected a number of sensor inputs that exceed the MTP threshold either via the pattern recognition or via the number of sensor inputs (see Section 6.15). This bit will cause the INT bit to be set if the MTP_ALERT bit is also set. This bit will not be cleared until the condition that caused it to be set has been removed. Bit 0 - TOUCH - Indicates that a touch was detected. This bit is set if any bit in the Sensor Input Status register is set. 10 4 11 8 TABLE 6-4: STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 02h R General Status - - - LED RESET MULT MTP TOUCH 00h 03h R Sensor Input Status CS8 CS7 CS6 CS5 CS4 CS3 CS2 CS1 00h 04h R LED Status - - - - - - LED2_ DN LED1_ DN 00h TABLE 6-3: GAIN BIT DECODE (CONTINUED) GAIN[1:0] Capacitive Touch Sensor Gain 1 0  2015 Microchip Technology Inc. DS00001622B-page 33 CAP1128 6.2.2 SENSOR INPUT STATUS - 03H The Sensor Input Status Register stores status bits that indicate a touch has been detected. A value of ‘0’ in any bit indicates that no touch has been detected. A value of ‘1’ in any bit indicates that a touch has been detected. All bits are cleared when the INT bit is cleared and if a touch on the respective capacitive touch sensor input is no longer present. If a touch is still detected, the bits will not be cleared (but this will not cause the interrupt to be asserted - see Section 6.6). Bit 7 - CS8 - Indicates that a touch was detected on Sensor Input 8. Bit 6 - CS7 - Indicates that a touch was detected on Sensor Input 7. Bit 5 - CS6 - Indicates that a touch was detected on Sensor Input 6. Bit 4 - CS5 - Indicates that a touch was detected on Sensor Input 5. Bit 3 - CS4 - Indicates that a touch was detected on Sensor Input 4. Bit 2 - CS3 - Indicates that a touch was detected on Sensor Input 3. Bit 1 - CS2 - Indicates that a touch was detected on Sensor Input 2. This sensor input can be linked to LED2. Bit 0 - CS1 - Indicates that a touch was detected on Sensor Input 1. This sensor input can be linked to LED1. 6.2.3 LED STATUS - 04H The LED Status Registers indicate when an LED has completed its configured behavior (see Section 6.31, "LED Behavior Register") after being actuated by the host (see Section 6.28, "LED Output Control Register"). These bits are ignored when the LED is linked to a capacitive sensor input. All LED Status bits are cleared when the INT bit is cleared. Bit 1 - LED2_DN - Indicates that LED2 has finished its behavior after being actuated by the host. Bit 0 - LED1_DN - Indicates that LED1 has finished its behavior after being actuated by the host. 6.3 Noise Flag Status Registers The Noise Flag Status registers store status bits that are generated from the analog block if the detected noise is above the operating region of the analog detector or the RF noise detector. These bits indicate that the most recently received data from the sensor input is invalid and should not be used for touch detection. So long as the bit is set for a particular channel, the delta count value is reset to 00h and thus no touch is detected. These bits are not sticky and will be cleared automatically if the analog block does not report a noise error. APPLICATION NOTE: If the MTP detection circuitry is enabled, these bits count as sensor inputs above the MTP threshold (see Section 5.5.4, "Multiple Touch Pattern Detection") even if the corresponding delta count is not. If the corresponding delta count also exceeds the MTP threshold, it is not counted twice. APPLICATION NOTE: Regardless of the state of the Noise Status bits, if low frequency noise is detected on a sensor input, that sample will be discarded unless the DIS_ANA_NOISE bit is set. As well, if RF noise is detected on a sensor input, that sample will be discarded unless the DIS_RF_NOISE bit is set. TABLE 6-5: NOISE FLAG STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 0Ah R Noise Flag Status CS8_ NOISE CS7_ NOISE CS6_ NOISE CS5_ NOISE CS4_ NOISE CS3_ NOISE CS2_ NOISE CS1_ NOISE 00h CAP1128 DS00001622B-page 34  2015 Microchip Technology Inc. 6.4 Sensor Input Delta Count Registers The Sensor Input Delta Count registers store the delta count that is compared against the threshold used to determine if a touch has been detected. The count value represents a change in input due to the capacitance associated with a touch on one of the sensor inputs and is referenced to a calibrated base “Not Touched” count value. The delta is an instantaneous change and is updated once per sensor input per sensing cycle (see Section 5.5.1, "Sensing Cycle"). The value presented is a standard 2’s complement number. In addition, the value is capped at a value of 7Fh. A reading of 7Fh indicates that the sensitivity settings are too high and should be adjusted accordingly (see Section 6.5). The value is also capped at a negative value of 80h for negative delta counts which may result upon a release. 6.5 Sensitivity Control Register The Sensitivity Control register controls the sensitivity of a touch detection. Bits 6-4 DELTA_SENSE[2:0] - Controls the sensitivity of a touch detection. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta capacitance corresponding to a “lighter” touch. These settings are more sensitive to noise, however, and a noisy environment may flag more false touches with higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely, a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). TABLE 6-6: SENSOR INPUT DELTA COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 10h R Sensor Input 1 Delta Count Sign 64 32 16 8 4 2 1 00h 11h R Sensor Input 2 Delta Count Sign 64 32 16 8 4 2 1 00h 12h R Sensor Input 3 Delta Count Sign 64 32 16 8 4 2 1 00h 13h R Sensor Input 4 Delta Count Sign 64 32 16 8 4 2 1 00h 14h R Sensor Input 5 Delta Count Sign 64 32 16 8 4 2 1 00h 15h R Sensor Input 6 Delta Count Sign 64 32 16 8 4 2 1 00h 16h R Sensor Input 7 Delta Count Sign 64 32 16 8 4 2 1 00h 17h R Sensor Input 8 Delta Count Sign 64 32 16 8 4 2 1 00h TABLE 6-7: SENSITIVITY CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 1Fh R/W Sensitivity Control - DELTA_SENSE[2:0] BASE_SHIFT[3:0] 2Fh  2015 Microchip Technology Inc. DS00001622B-page 35 CAP1128 Bits 3 - 0 - BASE_SHIFT[3:0] - Controls the scaling and data presentation of the Base Count registers. The higher the value of these bits, the larger the range and the lower the resolution of the data presented. The scale factor represents the multiplier to the bit-weighting presented in these register descriptions. APPLICATION NOTE: The BASE_SHIFT[3:0] bits normally do not need to be updated. These settings will not affect touch detection or sensitivity. These bits are sometimes helpful in analyzing the Cap Sensing board performance and stability. TABLE 6-8: DELTA_SENSE BIT DECODE DELTA_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-9: BASE_SHIFT BIT DECODE BASE_SHIFT[3:0] Data Scaling Factor 32 1 0 0 0 0 0 1x 0 0 0 1 2x 0 0 1 0 4x 0 0 1 1 8x 0 1 0 0 16x 0 1 0 1 32x 0 1 1 0 64x 0 1 1 1 128x 1 0 0 0 256x All others 256x (default = 1111b) CAP1128 DS00001622B-page 36  2015 Microchip Technology Inc. 6.6 Configuration Registers The Configuration registers control general global functionality that affects the entire device. 6.6.1 CONFIGURATION - 20H Bit 7 - TIMEOUT - Enables the timeout and idle functionality of the SMBus protocol. • ‘0’ (default for Functional Revision C) - The SMBus timeout and idle functionality are disabled. The SMBus interface will not time out if the clock line is held low. Likewise, it will not reset if both the data and clock lines are held high for longer than 200us. This is used for I2C compliance. • ‘1’ (default for Functional Revision B) - The SMBus timeout and idle functionality are enabled. The SMBus interface will time out if the clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock lines are held high for longer than 200us. Bit 6 - WAKE_CFG - Configures the operation of the WAKE pin. • ‘0’ (default) - The WAKE pin is not asserted when a touch is detected while the device is in Standby. It will still be used to wake the device from Deep Sleep when driven high. • ‘1’ - The WAKE pin will be asserted high when a touch is detected while the device is in Standby. It will also be used to wake the device from Deep Sleep when driven high. Bit 5 - DIS_DIG_NOISE - Determines whether the digital noise threshold (see Section 6.19, "Sensor Input Noise Threshold Register") is used by the device. Setting this bit disables the feature. • ‘0’ - The digital noise threshold is used. If a delta count value exceeds the noise threshold but does not exceed the touch threshold, the sample is discarded and not used for the automatic re-calibration routine. • ‘1’ (default) - The noise threshold is disabled. Any delta count that is less than the touch threshold is used for the automatic re-calibration routine. Bit 4 - DIS_ANA_NOISE - Determines whether the analog noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If low frequency noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if low frequency noise is detected. Bit 3 - MAX_DUR_EN - Determines whether the maximum duration recalibration is enabled. • ‘0’ (default) - The maximum duration recalibration functionality is disabled. A touch may be held indefinitely and no re-calibration will be performed on any sensor input. • ‘1’ - The maximum duration recalibration functionality is enabled. If a touch is held for longer than the MAX_DUR bit settings, then the re-calibration routine will be restarted (see Section 6.8). 6.6.2 CONFIGURATION 2 - 44H Bit 7 - INV_LINK_TRAN - Determines the behavior of the Linked LED Transition controls (see Section 6.29). • ‘0’ (default) - The Linked LED Transition controls set the min duty cycle equal to the max duty cycle. • ‘1’ - The Linked LED Transition controls will invert the touch signal. For example, a touch signal will be inverted to a non-touched signal. Bit 6 - ALT_POL - Determines the ALERT# pin polarity and behavior. • ‘0’ - The ALERT# pin is active high and push-pull. • ‘1’ (default) - The ALERT# pin is active low and open drain. TABLE 6-10: CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 20h R/W Configuration TIMEOUT WAKE_ CFG DIS_ DIG_ NOISE DIS_ ANA_ NOISE MAX_ DUR_EN - -- A0h (Rev B) 20h (rev C) 44h R/W Configuration 2 INV_LINK_ TRAN ALT_ POL BLK_PWR_ CTRL BLK_POL_ MIR SHOW_ RF_ NOISE DIS_ RF_ NOISE - INT_ REL_n 40h  2015 Microchip Technology Inc. DS00001622B-page 37 CAP1128 Bit 5 - BLK_PWR_CTRL - Determines whether the device will reduce power consumption while waiting between conversion time completion and the end of the polling cycle. • ‘0’ (default) - The device will always power down as much as possible during the time between the end of the last conversion and the end of the polling cycle. • ‘1’ - The device will not power down the Cap Sensor during the time between the end of the last conversion and the end of the polling cycle. Bit 4 - BLK_POL_MIR - Determines whether the LED Mirror Control register bits are linked to the LED Polarity bits. Setting this bit blocks the normal behavior which is to automatically set and clear the LED Mirror Control bits when the LED Polarity bits are set or cleared. • ‘0’ (default) - When the LED Polarity controls are set, the corresponding LED Mirror control is automatically set. Likewise, when the LED Polarity controls are cleared, the corresponding LED Mirror control is also cleared. • ‘1’ - When the LED Polarity controls are set, the corresponding LED Mirror control is not automatically set. Bit 3 - SHOW_RF_NOISE - Determines whether the Noise Status bits will show RF Noise as the only input source. • ‘0’ (default) - The Noise Status registers will show both RF noise and low frequency EMI noise if either is detected on a capacitive touch sensor input. • ‘1’ - The Noise Status registers will only show RF noise if it is detected on a capacitive touch sensor input. EMI noise will still be detected and touches will be blocked normally; however, the status bits will not be updated. Bit 2 - DIS_RF_NOISE - Determines whether the RF noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If RF noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if RF noise is detected. Bit 0 - INT_REL_n - Controls the interrupt behavior when a release is detected on a button. • ‘0’ (default) - An interrupt is generated when a press is detected and again when a release is detected and at the repeat rate (if enabled - see Section 6.13). • ‘1’ - An interrupt is generated when a press is detected and at the repeat rate but not when a release is detected. 6.7 Sensor Input Enable Registers The Sensor Input Enable registers determine whether a capacitive touch sensor input is included in the sampling cycle. The length of the sampling cycle is not affected by the number of sensor inputs measured. Bit 7 - CS8_EN - Enables the CS8 input to be included during the sampling cycle. • ‘0’ - The CS8 input is not included in the sampling cycle. • ‘1’ (default) - The CS8 input is included in the sampling cycle. Bit 6 - CS7_EN - Enables the CS7 input to be included during the sampling cycle. Bit 5 - CS6_EN - Enables the CS6 input to be included during the sampling cycle. Bit 4 - CS5_EN - Enables the CS5 input to be included during the sampling cycle. Bit 3 - CS4_EN - Enables the CS4 input to be included during the sampling cycle. Bit 2 - CS3_EN - Enables the CS3 input to be included during the sampling cycle. Bit 1 - CS2_EN - Enables the CS2 input to be included during the sampling cycle. Bit 0 - CS1_EN - Enables the CS1 input to be included during the sampling cycle. TABLE 6-11: SENSOR INPUT ENABLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 21h R/W Sensor Input Enable CS8_EN CS7_EN CS6_EN CS5_EN CS4_EN CS3_EN CS2_EN CS1_EN FFh CAP1128 DS00001622B-page 38  2015 Microchip Technology Inc. 6.8 Sensor Input Configuration Register The Sensor Input Configuration Register controls timings associated with the Capacitive sensor inputs 1 - 8. Bits 7 - 4 - MAX_DUR[3:0] - (default 1010b) - Determines the maximum time that a sensor pad is allowed to be touched until the capacitive touch sensor input is recalibrated, as shown in Table 6-13. Bits 3 - 0 - RPT_RATE[3:0] - (default 0100b) Determines the time duration between interrupt assertions when auto repeat is enabled. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-14. TABLE 6-12: SENSOR INPUT CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 22h R/W Sensor Input Configuration MAX_DUR[3:0] RPT_RATE[3:0] A4h TABLE 6-13: MAX_DUR BIT DECODE MAX_DUR[3:0] Time Before Recalibration 32 1 0 0 0 0 0 560ms 0 0 0 1 840ms 0 0 1 0 1120ms 0 0 1 1 1400ms 0 1 0 0 1680ms 0 1 0 1 2240ms 0 1 1 0 2800ms 1 1 1 3360ms 1 0 0 0 3920ms 1 0 0 1 4480ms 1 0 1 0 5600ms (default) 1 0 1 1 6720ms 1 1 0 0 7840ms 1 1 0 1 8906ms 1 1 1 0 10080ms 1 1 1 1 11200ms TABLE 6-14: RPT_RATE BIT DECODE RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms (default) 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms  2015 Microchip Technology Inc. DS00001622B-page 39 CAP1128 6.9 Sensor Input Configuration 2 Register Bits 3 - 0 - M_PRESS[3:0] - (default 0111b) - Determines the minimum amount of time that sensor inputs configured to use auto repeat must detect a sensor pad touch to detect a “press and hold” event. If the sensor input detects a touch for longer than the M_PRESS[3:0] settings, a “press and hold” event is detected. If a sensor input detects a touch for less than or equal to the M_PRESS[3:0] settings, a touch event is detected. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-16. 6.10 Averaging and Sampling Configuration Register 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-15: SENSOR INPUT CONFIGURATION 2 REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 23h R/W Sensor Input Configuration 2 - - - - M_PRESS[3:0] 07h TABLE 6-16: M_PRESS BIT DECODE M_PRESS[3:0] M_PRESS SETTINGS 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms (default) 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-17: AVERAGING AND SAMPLING CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 24h R/W Averaging and Sampling Config AVG[2:0] SAMP_TIME[1:0] CYCLE_TIME [1:0] 39h TABLE 6-14: RPT_RATE BIT DECODE (CONTINUED) RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 CAP1128 DS00001622B-page 40  2015 Microchip Technology Inc. The Averaging and Sampling Configuration register controls the number of samples taken and the total sensor input cycle time for all active sensor inputs while the device is functioning in Active state. Bits 6 - 4 - AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-18. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. For example, if CS1, CS2, and CS3 are sampled during the sensor cycle, and the AVG[2:0] bits are set to take 4 samples per channel, then the full sensor cycle will be: CS1, CS1, CS1, CS1, CS2, CS2, CS2, CS2, CS3, CS3, CS3, CS3. Bits 3 - 2 - SAMP_TIME[1:0] - Determines the time to take a single sample as shown in Table 6-19. Bits 1 - 0 - CYCLE_TIME[1:0] - Determines the overall cycle time for all measured channels during normal operation as shown in Table 6-20. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, then the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. TABLE 6-18: AVG BIT DECODE AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-19: SAMP_TIME BIT DECODE SAMP_TIME[1:0] Sample Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-20: CYCLE_TIME BIT DECODE CYCLE_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms  2015 Microchip Technology Inc. DS00001622B-page 41 CAP1128 6.11 Calibration Activate Register The Calibration Activate register forces the respective sensor inputs to be re-calibrated affecting both the analog and digital blocks. During the re-calibration routine, the sensor inputs will not detect a press for up to 600ms and the Sensor Input Base Count register values will be invalid. During this time, any press on the corresponding sensor pads will invalidate the re-calibration. When finished, the CALX[9:0] bits will be updated (see Section 6.39). When the corresponding bit is set, the device will perform the calibration and the bit will be automatically cleared once the re-calibration routine has finished. Bit 7 - CS8_CAL - When set, the CS8 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 6 - CS7_CAL - When set, the CS7 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 5 - CS6_CAL - When set, the CS6 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 4 - CS5_CAL - When set, the CS5 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 3 - CS4_CAL - When set, the CS4 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 2 - CS3_CAL - When set, the CS3 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 1 - CS2_CAL - When set, the CS2 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 0 - CS1_CAL - When set, the CS1 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. 6.12 Interrupt Enable Register The Interrupt Enable register determines whether a sensor pad touch or release (if enabled) causes the interrupt pin to be asserted. Bit 7 - CS8_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS8 (associated with the CS8 status bit). • ‘0’ - The interrupt pin will not be asserted if a touch is detected on CS8 (associated with the CS8 status bit). • ‘1’ (default) - The interrupt pin will be asserted if a touch is detected on CS8 (associated with the CS8 status bit). Bit 6 - CS7_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS7 (associated with the CS7 status bit). Bit 5 - CS6_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS6 (associated with the CS6 status bit). Bit 4 - CS5_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS5 (associated with the CS5 status bit). Bit 3 - CS4_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS4 (associated with the CS4 status bit). TABLE 6-21: CALIBRATION ACTIVATE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 26h R/W Calibration Activate CS8_ CAL CS7_ CAL CS6_ CAL CS5_ CAL CS4_ CAL CS3_ CAL CS2_ CAL CS1_ CAL 00h TABLE 6-22: INTERRUPT ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 27h R/W Interrupt Enable CS8_ INT_EN CS7_ INT_EN CS6_ INT_EN CS5_ INT_EN CS4_ INT_EN CS3_ INT_EN CS2_ INT_EN CS1_ INT_EN FFh CAP1128 DS00001622B-page 42  2015 Microchip Technology Inc. Bit 2 - CS3_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS3 (associated with the CS3 status bit). Bit 1 - CS2_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS2 (associated with the CS2 status bit). Bit 0 - CS1_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS1 (associated with the CS1 status bit). 6.13 Repeat Rate Enable Register The Repeat Rate Enable register enables the repeat rate of the sensor inputs as described in Section 5.6.1. Bit 7 - CS8_RPT_EN - Enables the repeat rate for capacitive touch sensor input 8. • ‘0’ - The repeat rate for CS8 is disabled. It will only generate an interrupt when a touch is detected and when a release is detected (if enabled) no matter how long the touch is held for. • ‘1’ (default) - The repeat rate for CS8 is enabled. In the case of a “touch” event, it will generate an interrupt when a touch is detected and a release is detected (as determined by the INT_REL_n bit - see Section 6.6). In the case of a “press and hold” event, it will generate an interrupt when a touch is detected and at the repeat rate so long as the touch is held. Bit 6 - CS7_RPT_EN - Enables the repeat rate for capacitive touch sensor input 7. Bit 5 - CS6_RPT_EN - Enables the repeat rate for capacitive touch sensor input 6. Bit 4 - CS5_RPT_EN - Enables the repeat rate for capacitive touch sensor input 5. Bit 3 - CS4_RPT_EN - Enables the repeat rate for capacitive touch sensor input 4. Bit 2 - CS3_RPT_EN - Enables the repeat rate for capacitive touch sensor input 3. Bit 1 - CS2_RPT_EN - Enables the repeat rate for capacitive touch sensor input 2. Bit 0 - CS1_RPT_EN - Enables the repeat rate for capacitive touch sensor input 1. 6.14 Multiple Touch Configuration Register The Multiple Touch Configuration register controls the settings for the multiple touch detection circuitry. These settings determine the number of simultaneous buttons that may be pressed before additional buttons are blocked and the MULT status bit is set. Bit 7 - MULT_BLK_EN - Enables the multiple button blocking circuitry. • ‘0’ - The multiple touch circuitry is disabled. The device will not block multiple touches. • ‘1’ (default) - The multiple touch circuitry is enabled. The device will flag the number of touches equal to programmed multiple touch threshold and block all others. It will remember which sensor inputs are valid and block all others until that sensor pad has been released. Once a sensor pad has been released, the N detected touches (determined via the cycle order of CS1 - CS8) will be flagged and all others blocked. Bits 3 - 2 - B_MULT_T[1:0] - Determines the number of simultaneous touches on all sensor pads before a Multiple Touch Event is detected and sensor inputs are blocked. The bit decode is given by Table 6-25. TABLE 6-23: REPEAT RATE ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 28h R/W Repeat Rate Enable CS8_ RPT_EN CS7_ RPT_EN CS6_ RPT_EN CS5_ RPT_EN CS4_ RPT_EN CS3_ RPT_EN CS2_ RPT_EN CS1_ RPT_EN FFh TABLE 6-24: MULTIPLE TOUCH CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Ah R/W Multiple Touch Config MULT_ BLK_ EN - - - B_MULT_T[1:0] - - 80h  2015 Microchip Technology Inc. DS00001622B-page 43 CAP1128 6.15 Multiple Touch Pattern Configuration Register The Multiple Touch Pattern Configuration register controls the settings for the multiple touch pattern detection circuitry. This circuitry works like the multiple touch detection circuitry with the following differences: 1. The detection threshold is a percentage of the touch detection threshold as defined by the MTP_TH[1:0] bits whereas the multiple touch circuitry uses the touch detection threshold. 2. The MTP detection circuitry either will detect a specific pattern of sensor inputs as determined by the Multiple Touch Pattern register settings or it will use the Multiple Touch Pattern register settings to determine a minimum number of sensor inputs that will cause the MTP circuitry to flag an event. When using pattern recognition mode, if all of the sensor inputs set by the Multiple Touch Pattern register have a delta count greater than the MTP threshold or have their corresponding Noise Flag Status bits set, the MTP bit will be set. When using the absolute number mode, if the number of sensor inputs with thresholds above the MTP threshold or with Noise Flag Status bits set is equal to or greater than this number, the MTP bit will be set. 3. When an MTP event occurs, all touches are blocked and an interrupt is generated. 4. All sensor inputs will remain blocked so long as the requisite number of sensor inputs are above the MTP threshold or have Noise Flag Status bits set. Once this condition is removed, touch detection will be restored. Note that the MTP status bit is only cleared by writing a ‘0’ to the INT bit once the condition has been removed. Bit 7 - MTP_EN - Enables the multiple touch pattern detection circuitry. • ‘0’ (default) - The MTP detection circuitry is disabled. • ‘1’ - The MTP detection circuitry is enabled. Bits 3-2 - MTP_TH[1:0] - Determine the MTP threshold, as shown in Table 6-27. This threshold is a percentage of sensor input threshold (see Section 6.18, "Sensor Input Threshold Registers") when the device is in the Fully Active state or of the standby threshold (see Section 6.23, "Standby Threshold Register") when the device is in the Standby state. Bit 1 - COMP_PTRN - Determines whether the MTP detection circuitry will use the Multiple Touch Pattern register as a specific pattern of sensor inputs or as an absolute number of sensor inputs. • ‘0’ (default) - The MTP detection circuitry will use the Multiple Touch Pattern register bit settings as an absolute minimum number of sensor inputs that must be above the threshold or have Noise Flag Status bits set. The number will be equal to the number of bits set in the register. TABLE 6-25: B_MULT_T BIT DECODE B_MULT_T[1:0] Number of Simultaneous Touches 1 0 0 0 1 (default) 01 2 10 3 11 4 TABLE 6-26: MULTIPLE TOUCH PATTERN CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Bh R/W Multiple Touch Pattern Config MTP_ EN - - MTP_TH[1:0] COMP_ PTRN MTP_ ALERT 00h TABLE 6-27: MTP_TH BIT DECODE MTP_TH[1:0] Threshold Divide Setting 1 0 0 0 12.5% (default) 0 1 25% 1 0 37.5% 1 1 100% CAP1128 DS00001622B-page 44  2015 Microchip Technology Inc. • ‘1’ - The MTP detection circuitry will use pattern recognition. Each bit set in the Multiple Touch Pattern register indicates a specific sensor input that must have a delta count greater than the MTP threshold or have a Noise Flag Status bit set. If the criteria are met, the MTP status bit will be set. Bit 0 - MTP_ALERT - Enables an interrupt if an MTP event occurs. In either condition, the MTP status bit will be set. • ‘0’ (default) - If an MTP event occurs, the ALERT# pin is not asserted. • ‘1’ - If an MTP event occurs, the ALERT# pin will be asserted. 6.16 Multiple Touch Pattern Register The Multiple Touch Pattern register acts as a pattern to identify an expected sensor input profile for diagnostics or other significant events. There are two methods for how the Multiple Touch Pattern register is used: as specific sensor inputs or number of sensor input that must exceed the MTP threshold or have Noise Flag Status bits set. Which method is used is based on the COMP_PTRN bit (see Section 6.15). The methods are described below. 1. Specific Sensor Inputs: If, during a single polling cycle, the specific sensor inputs above the MTP threshold or with Noise Flag Status bits set match those bits set in the Multiple Touch Pattern register, an MTP event is flagged. 2. Number of Sensor Inputs: If, during a single polling cycle, the number of sensor inputs with a delta count above the MTP threshold or with Noise Flag Status bits set is equal to or greater than the number of pattern bits set, an MTP event is flagged. Bit 7 - CS8_PTRN - Determines whether CS8 is considered as part of the Multiple Touch Pattern. • ‘0’ - CS8 is not considered a part of the pattern. • ‘1’ - CS8 is considered a part of the pattern, or the absolute number of sensor inputs that must have a delta count greater than the MTP threshold or have the Noise Flag Status bit set is increased by 1. Bit 6 - CS7_PTRN - Determines whether CS7 is considered as part of the Multiple Touch Pattern. Bit 5 - CS6_PTRN - Determines whether CS6 is considered as part of the Multiple Touch Pattern. Bit 4 - CS5_PTRN - Determines whether CS5 is considered as part of the Multiple Touch Pattern. Bit 3 - CS4_PTRN - Determines whether CS4 is considered as part of the Multiple Touch Pattern. Bit 2 - CS3_PTRN - Determines whether CS3 is considered as part of the Multiple Touch Pattern. Bit 1 - CS2_PTRN - Determines whether CS2 is considered as part of the Multiple Touch Pattern. Bit 0 - CS1_PTRN - Determines whether CS1 is considered as part of the Multiple Touch Pattern. 6.17 Recalibration Configuration Register The Recalibration Configuration register controls the automatic re-calibration routine settings as well as advanced controls to program the Sensor Input Threshold register settings. Bit 7 - BUT_LD_TH - Enables setting all Sensor Input Threshold registers by writing to the Sensor Input 1 Threshold register. • ‘0’ - Each Sensor Input X Threshold register is updated individually. • ‘1’ (default) - Writing the Sensor Input 1 Threshold register will automatically overwrite the Sensor Input Threshold registers for all sensor inputs (Sensor Input Threshold 1 through Sensor Input Threshold 8). The individual Sensor TABLE 6-28: MULTIPLE TOUCH PATTERN REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Dh R/W Multiple Touch Pattern CS8_ PTRN CS7_ PTRN CS6_ PTRN CS5_ PTRN CS4_ PTRN CS3_ PTRN CS2_ PTRN CS1_ PTRN FFh TABLE 6-29: RECALIBRATION CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Fh R/W Recalibration Configuration BUT_ LD_TH NO_ CLR_ INTD NO_ CLR_ NEG NEG_DELTA_ CNT[1:0] CAL_CFG[2:0] 8Ah  2015 Microchip Technology Inc. DS00001622B-page 45 CAP1128 Input X Threshold registers (Sensor Input 2 Threshold through Sensor Input 8 Threshold) can be individually updated at any time. Bit 6 - NO_CLR_INTD - Controls whether the accumulation of intermediate data is cleared if the noise status bit is set. • ‘0’ (default) - The accumulation of intermediate data is cleared if the noise status bit is set. • ‘1’ - The accumulation of intermediate data is not cleared if the noise status bit is set. APPLICATION NOTE: Bits 5 and 6 should both be set to the same value. Either both should be set to ‘0’ or both should be set to ‘1’. Bit 5 - NO_CLR_NEG - Controls whether the consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘0’ (default) - The consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘1’ - The consecutive negative delta counts counter is not cleared if the noise status bit is set. Bits 4 - 3 - NEG_DELTA_CNT[1:0] - Determines the number of negative delta counts necessary to trigger a digital recalibration as shown in Table 6-30. Bits 2 - 0 - CAL_CFG[2:0] - Determines the update time and number of samples of the automatic re-calibration routine. The settings apply to all sensor inputs universally (though individual sensor inputs can be configured to support re-calibration - see Section 6.11). Note 6-1 Recalibration Samples refers to the number of samples that are measured and averaged before the Base Count is updated however does not control the base count update period. Note 6-2 Update Time refers to the amount of time (in polling cycle periods) that elapses before the Base Count is updated. The time will depend upon the number of channels active, the averaging setting, and the programmed cycle time. TABLE 6-30: NEG_DELTA_CNT BIT DECODE NEG_DELTA_CNT[1:0] Number of Consecutive Negative Delta Count Values 1 0 00 8 0 1 16 (default) 1 0 32 1 1 None (disabled) TABLE 6-31: CAL_CFG BIT DECODE CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210 0 0 0 16 16 0 0 1 32 32 0 1 0 64 64 (default) 0 1 1 128 128 1 0 0 256 256 1 0 1 256 1024 1 1 0 256 2048 1 1 1 256 4096 CAP1128 DS00001622B-page 46  2015 Microchip Technology Inc. 6.18 Sensor Input Threshold Registers The Sensor Input Threshold registers store the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. When the BUT_LD_TH bit is set (see Section 6.17 - bit 7), writing data to the Sensor Input 1 Threshold register will update all of the sensor input threshold registers (31h - 37h inclusive). 6.19 Sensor Input Noise Threshold Register The Sensor Input Noise Threshold register controls the value of a secondary internal threshold to detect noise and improve the automatic recalibration routine. If a capacitive touch sensor input exceeds the Sensor Input Noise Threshold but does not exceed the sensor input threshold, it is determined to be caused by a noise spike. That sample is not used by the automatic re-calibration routine. This feature can be disabled by setting the DIS_DIG_NOISE bit. Bits 1-0 - CS1_BN_TH[1:0] - Controls the noise threshold for all capacitive touch sensor inputs, as shown in Table 6-34. The threshold is proportional to the threshold setting. TABLE 6-32: SENSOR INPUT THRESHOLD REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 30h R/W Sensor Input 1 Threshold - 64 32 16 8 4 2 1 40h 31h R/W Sensor Input 2 Threshold - 64 32 16 8 4 2 1 40h 32h R/W Sensor Input 3 Threshold - 64 32 16 8 4 2 1 40h 33h R/W Sensor Input 4 Threshold - 64 32 16 8 4 2 1 40h 34h R/W Sensor Input 5 Threshold - 64 32 16 8 4 2 1 40h 35h R/W Sensor Input 6 Threshold - 64 32 16 8 4 2 1 40h 36h R/W Sensor Input 7 Threshold - 64 32 16 8 4 2 1 40h 37h R/W Sensor Input 8 Threshold - 64 32 16 8 4 2 1 40h TABLE 6-33: SENSOR INPUT NOISE THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 38h R/W Sensor Input Noise Threshold CS_BN_TH [1:0] 01h TABLE 6-34: CSX_BN_TH BIT DECODE CS_BN_TH[1:0] Percent Threshold Setting 1 0 0 0 25% 0 1 37.5% (default) 1 0 50% 1 1 62.5%  2015 Microchip Technology Inc. DS00001622B-page 47 CAP1128 6.20 Standby Channel Register The Standby Channel register controls which (if any) capacitive touch sensor inputs are active during Standby. Bit 7 - CS8_STBY - Controls whether the CS8 channel is active in Standby. • ‘0’ (default) - The CS8 channel not be sampled during Standby. • ‘1’ - The CS8 channel will be sampled during Standby. It will use the Standby threshold setting, and the standby averaging and sensitivity settings. Bit 6 - CS7_STBY - Controls whether the CS7 channel is active in Standby. Bit 5 - CS6_STBY - Controls whether the CS6 channel is active in Standby. Bit 4 - CS5_STBY - Controls whether the CS5 channel is active in Standby. Bit 3 - CS4_STBY - Controls whether the CS4 channel is active in Standby. Bit 2 - CS3_STBY - Controls whether the CS3 channel is active in Standby. Bit 1 - CS2_STBY - Controls whether the CS2 channel is active in Standby. Bit 0 - CS1_STBY - Controls whether the CS1 channel is active in Standby. 6.21 Standby Configuration Register The Standby Configuration register controls averaging and cycle time for those sensor inputs that are active in Standby. This register is useful for detecting proximity on a small number of sensor inputs as it allows the user to change averaging and sample times on a limited number of sensor inputs and still maintain normal functionality in the fully active state. Bit 7 - AVG_SUM - Determines whether the active sensor inputs will average the programmed number of samples or whether they will accumulate for the programmed number of samples. • ‘0’ - (default) - The active sensor input delta count values will be based on the average of the programmed number of samples when compared against the threshold. • ‘1’ - The active sensor input delta count values will be based on the summation of the programmed number of samples when compared against the threshold. This bit should only be set when performing proximity detection as a physical touch will overflow the delta count registers and may result in false readings. Bits 6 - 4 - STBY_AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-37. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. TABLE 6-35: STANDBY CHANNEL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 40h R/W Standby Channel CS8_ STBY CS7_ STBY CS6_ STBY CS5_ STBY CS4_ STBY CS3_ STBY CS2_ STBY CS1_ STBY 00h TABLE 6-36: STANDBY CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 41h R/W Standby Configuration AVG_ SUM STBY_AVG[2:0] STBY_SAMP_ TIME[1:0] STBY_CY_TIME [1:0] 39h TABLE 6-37: STBY_AVG BIT DECODE STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 CAP1128 DS00001622B-page 48  2015 Microchip Technology Inc. Bit 3-2 - STBY SAMP_TIME[1:0] - Determines the time to take a single sample when the device is in Standby as shown in Table 6-38. Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during standby operation as shown in Table 6-39. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.22 Standby Sensitivity Register The Standby Sensitivity register controls the sensitivity for sensor inputs that are active in Standby. Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensor inputs that are active in Standby. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more sensitive to noise however and a noisy environment may flag more false touches than higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-38: STBY_SAMP_TIME BIT DECODE STBY_SAMP_TIME[1:0] Sampling Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-39: STBY_CY_TIME BIT DECODE STBY_CY_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-40: STANDBY SENSITIVITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 42h R/W Standby Sensitivity - - - - - STBY_SENSE[2:0] 02h TABLE 6-37: STBY_AVG BIT DECODE (CONTINUED) STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10  2015 Microchip Technology Inc. DS00001622B-page 49 CAP1128 of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). 6.23 Standby Threshold Register The Standby Threshold register stores the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. 6.24 Sensor Input Base Count Registers The Sensor Input Base Count registers store the calibrated “Not Touched” input value from the capacitive touch sensor inputs. These registers are periodically updated by the re-calibration routine. TABLE 6-41: STBY_SENSE BIT DECODE STBY_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-42: STANDBY THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 43h R/W Standby Threshold - 64 32 16 8 4 2 1 40h TABLE 6-43: SENSOR INPUT BASE COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 50h R Sensor Input 1 Base Count 128 64 32 16 8 4 2 1 C8h 51h R Sensor Input 2 Base Count 128 64 32 16 8 4 2 1 C8h 52h R Sensor Input 3 Base Count 128 64 32 16 8 4 2 1 C8h 53h R Sensor Input 4 Base Count 128 64 32 16 8 4 2 1 C8h 54h R Sensor Input 5 Base Count 128 64 32 16 8 4 2 1 C8h 55h R Sensor Input 6 Base Count 128 64 32 16 8 4 2 1 C8h 56h R Sensor Input 7 Base Count 128 64 32 16 8 4 2 1 C8h 57h R Sensor Input 8 Base Count 128 64 32 16 8 4 2 1 C8h CAP1128 DS00001622B-page 50  2015 Microchip Technology Inc. The routine uses an internal adder to add the current count value for each reading to the sum of the previous readings until sample size has been reached. At this point, the upper 16 bits are taken and used as the Sensor Input Base Count. The internal adder is then reset and the re-calibration routine continues. The data presented is determined by the BASE_SHIFT[3:0] bits (see Section 6.5). 6.25 LED Output Type Register The LED Output Type register controls the type of output for the LED pins. Each pin is controlled by a single bit. Refer to application note 21.4 CAP1128Family LED Configuration Options for more information about implementing LEDs. Bit 1 - LED2_OT - Determines the output type of the LED2 pin. • ‘0’ (default) - The LED2 pin is an open-drain output with an external pull-up resistor. When the appropriate pin is set to the “active” state (logic ‘1’), the pin will be driven low. Conversely, when the pin is set to the “inactive” state (logic ‘0’), then the pin will be left in a High Z state and pulled high via an external pull-up resistor. • ‘1’ - The LED2 pin is a push-pull output. When driving a logic ‘1’, the pin is driven high. When driving a logic ‘0’, the pin is driven low. Bit 0 - LED1_OT - Determines the output type of the LED1 pin. 6.26 Sensor Input LED Linking Register The Sensor Input LED Linking register controls whether a capacitive touch sensor input is linked to an LED output. If the corresponding bit is set, then the appropriate LED output will change states defined by the LED Behavior controls (see Section 6.31) in response to the capacitive touch sensor input. Bit 1 - CS2_LED2 - Links the LED2 output to a detected touch on the CS2 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. • ‘0’ (default) - The LED 2 output is not associated with the CS2 input. If a touch is detected on the CS2 input, the LED will not automatically be actuated. The LED is enabled and controlled via the LED Output Control register (see Section 6.28) and the LED Behavior registers (see Section 6.31). • ‘1’ - The LED 2 output is associated with the CS2 input. If a touch is detected on the CS2 input, the LED will be actuated and behave as defined in Table 6-52. Bit 0 - CS1_LED1 - Links the LED1 output to a detected touch on the CS1 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. 6.27 LED Polarity Register The LED Polarity register controls the logical polarity of the LED outputs. When these bits are set or cleared, the corresponding LED Mirror controls are also set or cleared (unless the BLK_POL_MIR bit is set - see Section 6.6, "Configuration Registers"). Table 6-48, "LED Polarity Behavior" shows the interaction between the polarity controls, output controls, and relative brightness. TABLE 6-44: LED OUTPUT TYPE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 71h R/W LED Output Type ----- - LED2_ OT LED1_ OT 00h TABLE 6-45: SENSOR INPUT LED LINKING REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 72h R/W Sensor Input LED Linking - - - - - - CS2_ LED2 CS1_ LED1 00h TABLE 6-46: LED POLARITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 73h R/W LED Polarity - - - - - - LED2_ POL LED1_ POL 00h  2015 Microchip Technology Inc. DS00001622B-page 51 CAP1128 APPLICATION NOTE: The polarity controls determine the final LED pin drive. A touch on a linked capacitive touch sensor input is treated in the same way as the LED Output Control bit being set to a logic ‘1’. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’ then the LED will be on and that the CAP1128 LED pin is sinking the LED current. Conversely, if the LED pin is driven to a logic ‘1’, the LED will be off and there is no current flow. See Figure 5-1, "System Diagram for CAP1128". APPLICATION NOTE: This application note applies when the LED polarity is inverted (LEDx_POL = ‘0’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘0’ state in. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven low (i.e. maximum % of time that the LED is on) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven low (i.e. minimum % of time that the LED is on). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at the minimum duty cycle setting. Breathe operations will ramp the duty cycle from the minimum duty cycle to the maximum duty cycle. APPLICATION NOTE: This application note applies when the LED polarity is non-inverted (LEDx_POL = ‘1’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘1’ state. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven high (i.e. maximum % of time that the LED is off) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven high (i.e. minimum % of time that the LED is off). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at 100 minus the minimum duty cycle setting. Breathe operations will ramp the duty cycle from 100 minus the minimum duty cycle to 100 minus the maximum duty cycle. APPLICATION NOTE: The LED Mirror controls (see Section 6.30, "LED Mirror Control Register") work with the polarity controls with respect to LED brightness but will not have a direct effect on the output pin drive. Bit 1 - LED2_POL - Determines the polarity of the LED2 output. • ‘0’ (default) - The LED2 output is inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘0’. • ‘1’ - The LED2 output is non-inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘1’ or left in the high-z state as determined by its output type. Bit 0 - LED1_POL - Determines the polarity of the LED1 output. 6.28 LED Output Control Register The LED Output Control Register controls the output state of the LED pins that are not linked to sensor inputs. The LED Polarity Control Register will determine the non actuated state of the LED pins. The actuated LED behavior is determined by the LED behavior controls (see Section 6.31, "LED Behavior Register"). TABLE 6-47: LED OUTPUT CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 74h R/W LED Output Control --- - -- LED2_ DR LED1_ DR 00h Note: If an LED is linked to a sensor input in the Sensor Input LED Linking Register (Section 6.26, "Sensor Input LED Linking Register"), the corresponding bit in the LED Output Control Register is ignored (i.e. a linked LED cannot be host controlled). CAP1128 DS00001622B-page 52  2015 Microchip Technology Inc. Table 6-48 shows the interaction between the polarity controls, output controls, and relative brightness. Bit 1 - LED2_DR - Determines whether LED2 output is driven high or low. • ‘0’ (default) - The LED2 output is driven at the minimum duty cycle or not actuated. • ‘1’ - The LED2 output is High Z or driven at the maximum duty cycle or actuated. Bit 0 - LED1_DR - Determines whether LED1 output is driven high or low. 6.29 Linked LED Transition Control Register The Linked LED Transition Control register controls the LED drive when the LED is linked to a capacitive touch sensor input. These controls work in conjunction with the INV_LINK_TRAN bit (see Section 6.6.2, "Configuration 2 - 44h") to create smooth transitions from host control to linked LEDs. Bit 1 - LED2_LTRAN - Determines the transition effect when LED2 is linked to CS2. • ‘0’ (default) - When the LED output control bit for LED2 is ‘1’, and then LED2 is linked to CS2 and no touch is detected, the LED will change states. • ‘1’ - If the INV_LINK_TRAN bit is ‘1’, when the LED output control bit for CS2 is ‘1’, and then CS2 is linked to LED2 and no touch is detected, the LED will not change states. In addition, the LED state will change when the sensor pad is touched. If the INV_LINK_TRAN bit is ‘0’, when the LED output control bit for CS2 is ‘1’, and then CS2 is linked to LED2 and no touch is detected, the LED will not change states. However, the LED state will not change when the sensor pad is touched. APPLICATION NOTE: If the LED behavior is not “Direct” and the INV_LINK_TRAN bit it ‘0’, the LED will not perform as expected when the LED2_LTRAN bit is set to ‘1’. Therefore, if breathe and pulse behaviors are used, set the INV_LINK_TRAN bit to ‘1’. TABLE 6-48: LED POLARITY BEHAVIOR LED Output Control Register or Touch Polarity Max Duty Min Duty Brightness LED Appearance 0 inverted (‘0’) not used minimum % of time that the LED is on (logic 0) maximum brightness at min duty cycle on at min duty cycle 1 inverted (‘0’) maximum % of time that the LED is on (logic 0) minimum % of time that the LED is on (logic 0) maximum brightness at max duty cycle. Brightness ramps from min duty cycle to max duty cycle according to LED behavior 0 non-inverted (‘1’) not used minimum % of time that the LED is off (logic 1) maximum brightness at 100 minus min duty cycle. on at 100 - min duty cycle 1 non-inverted (‘1’) maximum % of time that the LED is off (logic 1) minimum % of time that the LED is off (logic 1) For Direct behavior, maximum brightness is 100 minus max duty cycle. When breathing, max brightness is 100 minus min duty cycle. Brightness ramps from 100 - min duty cycle to 100 - max duty cycle. according to LED behavior TABLE 6-49: LINKED LED TRANSITION CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 77h R/W Linked LED Transition Control - ----- LED2_ LTRAN LED1_ LTRAN 00h  2015 Microchip Technology Inc. DS00001622B-page 53 CAP1128 Bit 0 - LED1_LTRAN - Determines the transition effect when LED1 is linked to CS1. 6.30 LED Mirror Control Register The LED Mirror Control Registers determine the meaning of duty cycle settings when polarity is non-inverted for each LED channel. When the polarity bit is set to ‘1’ (non-inverted), to obtain correct steps for LED ramping, pulse, and breathe behaviors, the min and max duty cycles need to be relative to 100%, rather than the default, which is relative to 0%. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’, the LED will be on and the CAP1128 LED pin is sinking the LED current. When the polarity bit is set to ‘1’, it is considered non-inverted. For systems using the opposite LED configuration, mirror controls would apply when the polarity bit is ‘0’. These bits are changed automatically if the corresponding LED Polarity bit is changed (unless the BLK_POL_MIR bit is set - see Section 6.6). Bit 1 - LED2_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. • ‘0’ (default) - The duty cycle settings are determined relative to 0% and are determined directly with the settings. • ‘1’ - The duty cycle settings are determined relative to 100%. Bit 0 - LED1_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. 6.31 LED Behavior Register The LED Behavior register controls the operation of LEDs. Each LED pin is controlled by a 2-bit field and the behavior is determined by whether the LED is linked to a capacitive touch sensor input or not. If the corresponding LED output is linked to a capacitive touch sensor input, the appropriate behavior will be enabled / disabled based on touches and releases. If the LED output is not associated with a capacitive touch sensor input, the appropriate behavior will be enabled / disabled by the LED Output Control register. If the respective LEDx_DR bit is set to a logic ‘1’, this will be associated as a “touch”, and if the LEDx_DR bit is set to a logic ‘0’, this will be associated as a “release”. Table 6-52, "LEDx_CTL Bit Decode" shows the behavior triggers. The defined behavior will activate when the Start Trigger is met and will stop when the Stop Trigger is met. Note the behavior of the Breathe Hold and Pulse Release option. The LED Polarity Control register will determine the non actuated state of the LED outputs (see Section 6.27, "LED Polarity Register"). APPLICATION NOTE: If an LED is not linked to a capacitive touch sensor input and is breathing (via the Breathe or Pulse behaviors), it must be unactuated and then re-actuated before changes to behavior are processed. For example, if the LED output is breathing and the Maximum duty cycle is changed, this change will not take effect until the LED output control register is set to ‘0’ and then re-set to ‘1’. APPLICATION NOTE: If an LED is not linked to the capacitive touch sensor input and configured to operate using Pulse 1 Behavior, then the circuitry will only be actuated when the corresponding output control bit is set. It will not check the bit condition until the Pulse 1 behavior is finished. The device will not remember if the bit was cleared and reset while it was actuated. TABLE 6-50: LED MIRROR CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 79h R/W LED Mirror Control ------ LED2_ MIR _ EN LED1_ MIR _ EN 00h TABLE 6-51: LED BEHAVIOR REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 81h R/W LED Behavior 1 - - - - LED2_CTL[1:0] LED1_CTL[1:0] 00h CAP1128 DS00001622B-page 54  2015 Microchip Technology Inc. APPLICATION NOTE: If an LED is actuated and not linked and the desired LED behavior is changed, this new behavior will take effect immediately; however, the first instance of the changed behavior may act incorrectly (e.g. if changed from Direct to Pulse 1, the LED output may ‘breathe’ 4 times and then end at minimum duty cycle). LED Behaviors will operate normally once the LED has been un-actuated and then re-actuated. APPLICATION NOTE: If an LED is actuated and it is switched from linked to a capacitive touch sensor input to unlinked (or vice versa), the LED will respond to the new command source immediately if the behavior was Direct or Breathe. For Pulse behaviors, it will complete the behavior already in progress. For example, if a linked LED was actuated by a touch and the control is changed so that it is unlinked, it will check the status of the corresponding LED Output Control bit. If that bit is ‘0’, then the LED will behave as if a release was detected. Likewise, if an unlinked LED was actuated by the LED Output Control register and the control is changed so that it is linked and no touch is detected, then the LED will behave as if a release was detected. Bits 3 - 2 - LED2_CTL[1:0] - Determines the behavior of LED2 as shown in Table 6-52. Bits 1 - 0 - LED1_CTL[1:0] - Determines the behavior of LED1 as shown in Table 6-52. APPLICATION NOTE: The PWM frequency is determined based on the selected LED behavior, the programmed breathe period, and the programmed min and max duty cycles. For the Direct behavior mode, the PWM frequency is calculated based on the programmed Rise and Fall times. If these are set at 0, then the maximum PWM frequency will be used based on the programmed duty cycle settings. TABLE 6-52: LEDX_CTL BIT DECODE LEDx_CTL [1:0] Operation Description Start TRigger Stop Trigger 1 0 0 0 Direct The LED is driven to the programmed state (active or inactive). See Figure 6-7 Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 0 1 Pulse 1 The LED will “Pulse” a programmed number of times. During each “Pulse” the LED will breathe up to the maximum brightness and back down to the minimum brightness so that the total “Pulse” period matches the programmed value. Touch or Release Detected or LED Output Control bit set or cleared (see Section 6.32) n/a 1 0 Pulse 2 The LED will “Pulse” when the start trigger is detected. When the stop trigger is detected, it will “Pulse” a programmable number of times then return to its minimum brightness. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 1 1 Breathe The LED will breathe. It will be driven with a duty cycle that ramps up from the programmed minimum duty cycle (default 0%) to the programmed maximum duty cycle duty cycle (default 100%) and then back down. Each ramp takes up 50% of the programmed period. The total period of each “breath” is determined by the LED Breathe Period controls - see Section 6.34. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared  2015 Microchip Technology Inc. DS00001622B-page 55 CAP1128 6.32 LED Pulse 1 Period Register The LED Pulse Period 1 register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 01b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms (24 x 32ms = 768ms). The total range is from 32ms to 4.064 seconds as shown in Table 6-54 with the default being 1024ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. Bit 7 - ST_TRIG - Determines the start trigger for the LED Pulse behavior. • ‘0’ (default) - The LED will Pulse when a touch is detected or the drive bit is set. • ‘1’ - The LED will Pulse when a release is detected or the drive bit is cleared. The Pulse 1 operation is shown in Figure 6-1 when the LED output is configured for non-inverted polarity (LEDx_POL = 1) and in Figure 6-2 for inverted polarity (LEDx_POL = 0). . TABLE 6-53: LED PULSE 1 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 84h R/W LED Pulse 1 Period ST_ TRIG P1_ PER6 P1_ PER5 P1_ PER4 P1_ PER3 P1_ PER2 P1_ PER1 P1_ PER0 20h FIGURE 6-1: Pulse 1 Behavior with Non-Inverted Polarity Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected (100% - Pulse 1 Max Duty Cycle) * Brightness X pulses after touch or after release Pulse 1 Period (P1_PER) (100% - Pulse 1 Min Duty Cycle) * Brightness LED Brightness CAP1128 DS00001622B-page 56  2015 Microchip Technology Inc. 6.33 LED Pulse 2 Period Register The LED Pulse 2 Period register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 10b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 640ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. The Pulse 2 Behavior is shown in Figure 6-3 for non-inverted polarity (LEDx_POL = 1) and in Figure 6-4 for inverted polarity (LEDx_POL = 0). FIGURE 6-2: Pulse 1 Behavior with Inverted Polarity TABLE 6-54: LED PULSE / BREATHE PERIOD EXAMPLE Setting (HEX) Setting (Decimal) Total Breathe / Pulse Period (MS) 00h 0 32 01h 1 32 02h 2 64 03h 3 96 . . . . . . . . . 7Dh 125 4000 7Eh 126 4032 7Fh 127 4064 TABLE 6-55: LED PULSE 2 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 85h R/W LED Pulse 2 Period - P2_ PER6 P2_ PER5 P2_ PER4 P2_ PER3 P2_ PER2 P2_ PER1 P2_ PER0 14h Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected Pulse 1 Min Duty Cycle * Brightness X pulses after touch or after release Pulse Period (P1_PER) Pulse 1 Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001622B-page 57 CAP1128 6.34 LED Breathe Period Register The LED Breathe Period register determines the overall period of a breathe operation as determined by the LED_CTL registers (see Table 6-52 - setting 11b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 2976ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. FIGURE 6-3: Pulse 2 Behavior with Non-Inverted Polarity FIGURE 6-4: Pulse 2 Behavior with Inverted Polarity TABLE 6-56: LED BREATHE PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 86h R/W LED Breathe Period - BR_ PER6 BR_ PER5 BR_ PER4 BR_ PER3 BR_ PER2 BR_ PER1 BR_ PER0 5Dh . . . Normal – untouched operation Normal – untouched operation Touch Detected (100% - Pulse 2 Min Duty Cycle) * Brightness (100% - Pulse 2 Max Duty Cycle) * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness Normal – untouched operation Normal – untouched operation Touch Detected Pulse 2 Max Duty Cycle * Brightness Pulse 2 Min Duty Cycle * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness . . . CAP1128 DS00001622B-page 58  2015 Microchip Technology Inc. 6.35 LED Configuration Register The LED Configuration register controls general LED behavior as well as the number of pulses that are sent for the PULSE LED output behavior. Bit 6 - RAMP_ALERT - Determines whether the device will assert the ALERT# pin when LEDs actuated by the LED Output Control register bits have finished their respective behaviors. Interrupts will only be generated if the LED activity is generated by writing the LED Output Control registers. Any LED activity associated with touch detection will not cause an interrupt to be generated when the LED behavior has been finished. • ‘0’ (default) - The ALERT# pin will not be asserted when LEDs actuated by the LED Output Control register have finished their programmed behaviors. • ‘1’ - The ALERT# pin will be asserted whenever any LED that is actuated by the LED Output Control register has finished its programmed behavior. Bits 5 - 3 - PULSE2_CNT[2:0] - Determines the number of pulses used for the Pulse 2 behavior as shown in Table 6-58. Bits 2 - 0 - PULSE1_CNT[2:0] - Determines the number of pulses used for the Pulse 1 behavior as shown in Table 6-58. 6.36 LED Duty Cycle Registers The LED Duty Cycle registers determine the minimum and maximum duty cycle settings used for the LED for each LED behavior. These settings affect the brightness of the LED when it is fully off and fully on. The LED driver duty cycle will ramp up from the minimum duty cycle to the maximum duty cycle and back down again. APPLICATION NOTE: When operating in Direct behavior mode, changes to the Duty Cycle settings will be applied immediately. When operating in Breathe, Pulse 1, or Pulse 2 modes, the LED must be unactuated and then re-actuated before changes to behavior are processed. TABLE 6-57: LED CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 88h R/W LED Config - RAMP_ ALERT PULSE2_CNT[2:0] PULSE1_CNT[2:0] 04h TABLE 6-58: PULSEX_CNT DECODE PULSEX_CNT[2:0] Number of Breaths 21 0 0 0 0 1 (default - Pulse 2) 00 1 2 01 0 3 01 1 4 1 0 0 5 (default - Pulse 1) 10 1 6 11 0 7 11 1 8 TABLE 6-59: LED DUTY CYCLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 90h R/W LED Pulse 1 Duty Cycle P1_MAX_DUTY[3:0] P1_MIN_DUTY[3:0] F0h 91h R/W LED Pulse 2 Duty Cycle P2_MAX_DUTY[3:0] P2_MIN_DUTY[3:0] F0h 92h R/W LED Breathe Duty Cycle BR_MAX_DUTY[3:0] BR_MIN_DUTY[3:0] F0h 93h R/W Direct Duty Cycle DR_MAX_DUTY[3:0] DR_MIN_DUTY[3:0] F0h  2015 Microchip Technology Inc. DS00001622B-page 59 CAP1128 Bits 7 - 4 - X_MAX_DUTY[3:0] - Determines the maximum PWM duty cycle for the LED drivers as shown in Table 6-60. Bits 3 - 0 - X_MIN_DUTY[3:0] - Determines the minimum PWM duty cycle for the LED drivers as shown in Table 6-60. 6.37 LED Direct Ramp Rates Register The LED Direct Ramp Rates register control the rising and falling edge time of an LED that is configured to operate in Direct behavior mode. The rising edge time corresponds to the amount of time the LED takes to transition from its minimum duty cycle to its maximum duty cycle. Conversely, the falling edge time corresponds to the amount of time that the LED takes to transition from its maximum duty cycle to its minimum duty cycle. Bits 5 - 3 - RISE_RATE[2:0] - Determines the rising edge time of an LED when it transitions from its minimum drive state to its maximum drive state as shown in Table 6-62. Bits 2 - 0 - FALL_RATE[2:0] - Determines the falling edge time of an LED when it transitions from its maximum drive state to its minimum drive state as shown in Table 6-62. TABLE 6-60: LED DUTY CYCLE DECODE x_MAX/MIN_Duty [3:0] Maximum Duty Cycle Minimum Duty Cycle 3 21 0 0 0 0 0 7% 0% 0 0 0 1 9% 7% 0 0 1 0 11% 9% 0 0 1 1 14% 11% 0 1 0 0 17% 14% 0 1 0 1 20% 17% 0 1 1 0 23% 20% 0 1 1 1 26% 23% 1 0 0 0 30% 26% 1 0 0 1 35% 30% 1 0 1 0 40% 35% 1 0 1 1 46% 40% 1 1 0 0 53% 46% 1 1 0 1 63% 53% 1 1 1 0 77% 63% 1 1 1 1 100% 77% TABLE 6-61: LED DIRECT RAMP RATES REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 94h R/W LED Direct Ramp Rates - - RISE_RATE[2:0] FALL_RATE[2:0] 00h TABLE 6-62: RISE / FALL RATE DECODE RISE_RATE/ FALL_RATE/ Bit Decode Rise / Fall Time (TRISE / TFALL) 21 0 00 0 0 0 0 1 250ms 0 1 0 500ms 0 1 1 750ms 1 0 0 1s 1 0 1 1.25s CAP1128 DS00001622B-page 60  2015 Microchip Technology Inc. 6.38 LED Off Delay Register The LED Off Delay register determines the amount of time that an LED remains at its maximum duty cycle (or minimum as determined by the polarity controls) before it starts to ramp down. If the LED is operating in Breathe mode, this delay is applied at the top of each “breath”. If the LED is operating in the Direct mode, this delay is applied when the LED is unactuated. Bits 6 - 4 - BR_OFF_DLY[2:0] - Determines the Breathe behavior mode off delay, which is the amount of time an LED in Breathe behavior mode remains inactive after it finishes a breathe pulse (ramp on and ramp off), as shown in Figure 6- 5 (non-inverted polarity LEDx_POL = 1) and Figure 6-6 (inverted polarity LEDx_POL = 0). Available settings are shown in Table 6-64. 1 1 0 1.5s 1 1 1 2s TABLE 6-63: LED OFF DELAY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 95h R/W LED Off Delay Register - BR_OFF_DLY[2:0] DIR_OFF_DLY[3:0] 00h FIGURE 6-5: Breathe Behavior with Non-Inverted Polarity TABLE 6-62: RISE / FALL RATE DECODE (CONTINUED) RISE_RATE/ FALL_RATE/ Bit Decode Rise / Fall Time (TRISE / TFALL) 21 0 LED Actuated 100% - Breathe Max Min Cycle * Brightness 100% - Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER)  2015 Microchip Technology Inc. DS00001622B-page 61 CAP1128 Bits 3 - 0 - DIR_OFF_DLY[3:0] - Determines the turn-off delay, as shown in Table 6-65, for all LEDs that are configured to operate in Direct behavior mode. The Direct behavior operation is determined by the combination of programmed Rise Time, Fall Time, Min and Max Duty cycles, Off Delay, and polarity. Figure 6-7 shows the behavior for non-inverted polarity (LEDx_POL = 1) while Figure 6- 8 shows the behavior for inverted polarity (LEDx_POL = 0). FIGURE 6-6: Breathe Behavior with Inverted Polarity TABLE 6-64: BREATHE OFF DELAY SETTINGS BR_OFF_DLY [2:0] OFF Delay 2 10 0 0 0 0 (default) 0 0 1 0.25s 0 1 0 0.5s 0 1 1 0.75s 1 0 0 1.0s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2.0s LED Actuated Breathe Max Duty Cycle * Brightness Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) CAP1128 DS00001622B-page 62  2015 Microchip Technology Inc. FIGURE 6-7: Direct Behavior for Non-Inverted Polarity FIGURE 6-8: Direct Behavior for Inverted Polarity TABLE 6-65: OFF DELAY DECODE OFF Delay[3:0] Bit Decode OFF Delay (tOFF_DLY) 32 1 0 00 0 0 0 0 0 0 1 250ms 0 0 1 0 500ms 0 0 1 1 750ms 0 1 0 0 1s 0 1 0 1 1.25s 0 1 1 0 1.5s 0 1 1 1 2s 1 0 0 0 2.5s 1 0 0 1 3.0s 1 0 1 0 3.5s 1 0 1 1 4.0s 1 1 0 0 4.5s All others 5.0s Normal – untouched operation RISE_RATE Setting (tRISE) (100% - Max Duty Cycle) * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation (100% - Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation RISE_RATE Setting (tRISE) Min Duty Cycle * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001622B-page 63 CAP1128 6.39 Sensor Input Calibration Registers The Sensor Input Calibration registers hold the 10-bit value that represents the last calibration value. 6.40 Product ID Register The Product ID register stores a unique 8-bit value that identifies the device. 6.41 Manufacturer ID Register The Vendor ID register stores an 8-bit value that represents Microchip. TABLE 6-66: SENSOR INPUT CALIBRATION REGISTERS ADDR Register R/W B7 B6 B5 B4 B3 B2 B1 B0 Default B1h Sensor Input 1 Calibration R CAL1_9 CAL1_8 CAL1_7 CAL1_6 CAL1_5 CAL1_4 CAL1_3 CAL1_2 00h B2h Sensor Input 2 Calibration R CAL2_9 CAL2_8 CAL2_7 CAL2_6 CAL2_5 CAL2_4 CAL2_3 CAL2_2 00h B3h Sensor Input 3 Calibration R CAL3_9 CAL3_8 CAL3_7 CAL3_6 CAL3_5 CAL3_4 CAL3_3 CAL3_2 00h B4h Sensor Input 4 Calibration R CAL4_9 CAL4_8 CAL4_7 CAL4_6 CAL4_5 CAL4_4 CAL4_3 CAL4_2 00h B5h Sensor Input 5 Calibration R CAL5_9 CAL5_8 CAL5_7 CAL5_6 CAL5_5 CAL5_4 CAL5_3 CAL5_2 00h B6h Sensor Input 6 Calibration R CAL6_9 CAL6_8 CAL6_7 CAL6_6 CAL6_5 CAL6_4 CAL6_3 CAL6_2 00h B7h Sensor Input 7 Calibration R CAL7_9 CAL7_8 CAL7_7 CAL7_6 CAL7_5 CAL7_4 CAL7_3 CAL7_2 00h B8h Sensor Input 8 Calibration R CAL8_9 CAL8_8 CAL8_7 CAL8_6 CAL8_5 CAL8_4 CAL8_3 CAL8_2 00h B9h Sensor Input Calibration LSB 1 R CAL4_1 CAL4_0 CAL3_1 CAL3_0 CAL2_1 CAL2_0 CAL1_1 CAL1_0 00h BAh Sensor Input Calibration LSB 2 R CAL8_1 CAL8_0 CAL7_1 CAL7_0 CAL6_1 CAL6_0 CAL5_1 CAL5_0 00h TABLE 6-67: PRODUCT ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FDh R Product ID 0 1 0 1 0 0 1 0 52h TABLE 6-68: VENDOR ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh CAP1128 DS00001622B-page 64  2015 Microchip Technology Inc. 6.42 Revision Register The Revision register stores an 8-bit value that represents the part revision. TABLE 6-69: REVISION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FFh R Revision 1 0 0 0 0 0 1 1 83h  2015 Microchip Technology Inc. DS00001622B-page 65 CAP1128 7.0 PACKAGE INFORMATION 7.1 CAP1128 Package Drawings Note: For the most current package drawings, see the Microchip Packaging Specification at: http://www.microchip.com/packaging. FIGURE 7-1: 20-Pin QFN 4mm x 4mm Package Drawing CAP1128 DS00001622B-page 66  2015 Microchip Technology Inc. FIGURE 7-2: 20-Pin QFN 4mm x 4mm Package Dimensions FIGURE 7-3: 20-Pin QFN 4mm x 4mm PCB Drawing  2015 Microchip Technology Inc. DS00001622B-page 67 CAP1128 7.2 Package Marking FIGURE 7-4: CAP1128 Package Markings C 1 28 - 1 Y WWN N N A RCC e3 TOP BOTTOM Bottom marking not allowed PB-FREE/GREEN SYMBOL (Matte Sn) Lines 1-3: Line 4: Center Horizontal Alignment Left Horizontal Alignment PIN 1 0.41 3x 0.56 Line 1 – SMSC Logo without circled R symbol Line 2 – Device ID, Version Line 3 – Year, Week, Alphanumeric Traceability Code Line 4 – Revision, Country Code 1 CAP1128 DS00001622B-page 68  2015 Microchip Technology Inc. APPENDIX A: DEVICE DELTA A.1 Delta from CAP1028 to CAP1128 1. Updated circuitry to improve power supply rejection. 2. Updated LED driver duty cycle decode values to have more distribution at lower values - closer to a logarithmic curve. See Table 6-60, "LED Duty Cycle Decode". 3. Updated bug that breathe periods were not correct above 2.6s. This includes rise / fall time decodes above 1.5s. 4. Added filtering on RESET pin to prevent errant resets. 5. Updated controls so that the RESET pin assertion places the device into the lowest power state available and causes an interrupt when released. See Section 5.2, "RESET Pin". 6. Added 1 bit to the LED Off Delay register (see Section 6.38, "LED Off Delay Register") to extend times from 2s to 5s in 0.5s intervals. 7. Breathe behavior modified. A breathe off delay control was added to the LED Off Delay Register (see Section 6.38, "LED Off Delay Register") so the LEDs can be configured to remain inactive between breathes. 8. Added controls for the LED transition effects when linking LEDs to capacitive sensor inputs. See Section 6.29, "Linked LED Transition Control Register". 9. Added controls to “mirror” the LED duty cycle outputs so that when polarity changes, the LED brightness levels look right. These bits are automatically set when polarity is set. Added control to break this auto-set behavior. See Section 6.30, "LED Mirror Control Register". 10. Added Multiple Touch Pattern detection circuitry. See Section 6.15, "Multiple Touch Pattern Configuration Register". 11. Added General Status register to flag Multiple touches, Multiple Touch Pattern issues and general touch detections. See Section 6.2, "Status Registers". 12. Added bits 6 and 5 to the Recalibration Configuration register (2Fh - see Section 6.17, "Recalibration Configuration Register"). These bits control whether the accumulation of intermediate data and the consecutive negative delta counts counter are cleared when the noise status bit is set. 13. Added Configuration 2 register for LED linking controls, noise detection controls, and control to interrupt on press but not on release. Added control to change alert pin polarity. See Section 6.6, "Configuration Registers". 14. Updated Deep Sleep behavior so that device does not clear DSLEEP bit on received communications but will wake to communicate. 15. Changed PWM frequency for LED drivers. The PWM frequency was derived from the programmed breathe period and duty cycle settings and it ranged from ~4Hz to ~8000 Hz. The PWM frequency has been updated to be a fixed value of ~2000Hz. 16. Register delta: Table A.1 Register Delta From CAP1028 to CAP1128 Address Register Delta Delta Default 00h Page 31 Changed - Main Status / Control added bits 7-6 to control gain 00h 02h Page 32 New - General Status new register to store MTP, MULT, LED, RESET, and general TOUCH bits 00h 44h Page 36 New - Configuration 2 new register to control alert polarity, LED touch linking behavior, LED output behavior, and noise detection, and interrupt on release 40h 24h Page 39 Changed - Averaging Control updated register bits - moved SAMP_AVG[2:0] bits and added SAMP_- TIME bit 1. Default changed 39h 2Bh Page 43 New - Multiple Touch Pattern Configuration new register for Multiple Touch Pattern configuration - enable and threshold settings 80h  2015 Microchip Technology Inc. DS00001622B-page 69 CAP1128 2Dh Page 44 New - Multiple Touch Pattern Register new register for Multiple Touch Pattern detection circuitry - pattern or number of sensor inputs FFh 2Fh Page 44 Changed - Recalibration Configuration updated register - updated CAL_CFG bit decode to add a 128 averages setting and removed highest time setting. Default changed. Added bit 6 NO_CLR_INTD and bit 5 NO_CLR_NEG. 8Ah 38h Page 46 Changed - Sensor Input Noise Threshold updated register bits - removed bits 7 - 3 and consolidated all controls into bits 1 - 0. These bits will set the noise threshold for all channels. Default changed 01h 39h Removed - Noise Threshold Register 2 removed register n/a 41h Page 47 Changed - Standby Configuration updated register bits - moved STBY_AVG[2:0] bits and added STBY_- TIME bit 1. Default changed 39h 77h Page 52 New - Linked LED Transition Control new register to control transition effect when LED linked to sensor inputs 00h 79h Page 53 New - LED Mirror Control new register to control LED output mirroring for brightness control when polarity changed 00h 90h Page 58 Changed - LED Pulse 1 Duty Cycle changed bit decode to be more logarithmic F0h 91h Page 58 Changed - LED Pulse 2 Duty Cycle changed bit decode to be more logarithmic F0h 92h Page 58 Changed - LED Breathe Duty Cycle changed bit decode to be more logarithmic F0h 93h Page 58 Changed - LED Direct Duty Cycle changed bit decode to be more logarithmic F0h 95h Added controls - LED Off Delay Added bits 6-4 BR_OFF_DLY[2:0] Added bit 3 DIR_OFF_DLY[3] 00h FDh Page 63 Changed - Product ID Changed bit decode for CAP1128 52h Table A.1 Register Delta From CAP1028 to CAP1128 (continued) Address Register Delta Delta Default CAP1128 DS00001622B-page 70  2015 Microchip Technology Inc. APPENDIX B: DATA SHEET REVISION HISTORY Revision Section/Figure/Entry Correction DS00001622B (02-09-15) Features, Table 2-1, Table 2- 2, "Pin Types", Section 5.0, "General Description" References to BC-Link Interface, BC_DATA, BC_- CLK, BC-IRQ#, BC-Link bus have been removed Application Note under Table 2-6 [BC-Link] hidden in data sheet Table 3-2, "Electrical Specifications" BC-Link Timing Section hidden in data sheet Table 4-1 Protocol Used for 68K Pull Down Resistor changed from “BC-Link Communications” to “Reserved” Section 4.2.2, "SMBus Address and RD / WR Bit" Replaced “client address” with “slave address” in this section. Section 4.2.4, SMBus ACK and NACK Bits, Section 4.2.5, SMBus Stop Bit,Section 4.2.7, SMBus and I2C Compatibility Replaced “client” with “slave” in these sections. Table 4-4, "Read Byte Protocol" Heading changed from “Client Address” to “Slave Address” Table 6-1 Register Name for Register Address 77h changed from “LED Linked Transition Control” to “Linked LED Transition Control” Section 6.30 changed CS2 to LED2 Section 7.7 Package Marking Updated package drawing Appendix A: Device Delta changed 2Dh to 2Fh in item #12 Product Identification System Removed BC-Link references REV A REV A replaces previous SMSC version Rev. 1.32 (01-05-12) Rev. 1.32 (01-05-12) Table 3-2, "Electrical Specifications" Added conditions for tHD:DAT. Section 4.2.7, "SMBus and I2C Compatibility" Renamed from “SMBus and I2C Compliance.” First paragraph, added last sentence: “For information on using the CAP1188 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I 2C Systems.” Added: CAP1188 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. Section 6.4, "Sensor Input Delta Count Registers" Changed negative value cap from FFh to 80h. Rev. 1.31 (08-18-11) Section 4.3.3, "SMBus Send Byte" Added an application note: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Section 4.3.4, "SMBus Receive Byte" Added an application note: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Rev. 1.3 (05-18-11) Section 6.42, "Revision Register" Updated revision ID from 82h to 83h. Rev. 1.2 (02-10-11) Section A.8, "Delta from Rev B (Mask B0) to Rev C (Mask B1)" Added. Table 2-1, "Pin Description for CAP1128" Changed value in “Unused Connection” column for the ADDR_COMM pin from “Connect to Ground” to “n/a“.  2015 Microchip Technology Inc. DS00001622B-page 71 CAP1128 Table 3-2, "Electrical Specifications" PSR improvements made in functional revision B. Changed PSR spec from ±100 typ and ±200 max counts / V to ±3 and ±10 counts / V. Conditions updated. Section 5.5.2, "Recalibrating Sensor Inputs" Added more detail with subheadings for each type of recalibration. Section 6.6, "Configuration Registers" Added bit 5 BLK_PWR_CTRL to the Configuration 2 Register 44h. The TIMEOUT bit is set to ‘1’ by default for functional revision B and is set to ‘0’ by default for functional revision C. Section 6.42, "Revision Register" Updated revision ID in register FFh from 81h to 82h. Rev. 1.1 (11-17-10) Document Updated for functional revision B. See Section A.7, "Delta from Rev A (Mask A0) to Rev B (Mask B0)". Cover Added to General Description: “includes circuitry and support for enhanced sensor proximity detection.” Added the following Features: Calibrates for Parasitic Capacitance Analog Filtering for System Noise Sources Press and Hold feature for Volume-like Applications Table 3-2, "Electrical Specifications" Conditions for Power Supply Rejection modified adding the following: Sampling time = 2.56ms Averaging = 1 Negative Delta Counts = Disabled All other parameters default Section 6.11, "Calibration Activate Register" Updated register description to indicate which re-calibration routine is used. Section 6.14, "Multiple Touch Configuration Register" Updated register description to indicate what will happen. Table 6-34, "CSx_BN_TH Bit Decode" Table heading changed from “Threshold Divide Setting” to “Percent Threshold Setting”. Rev. 1.0 (06-14-10) Initial release Revision Section/Figure/Entry Correction CAP1128 DS00001622B-page 72  2015 Microchip Technology Inc. THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2015 Microchip Technology Inc. DS00001622B-page 73 CAP1128 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] - 1 - XXX - [X](1) l l l l Device Temperature Package Tape and Reel Range Option Example: Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Device: CAP1128 Temperature Range: Blank = 0°C to +85°C (Extended Commercial) Package: BP = QFN Tape and Reel Option: TR = Tape and Reel(1) CAP1128-1-BP-TR 20-pin QFN 4mm x 4mm (RoHS compliant) Eight capacitive touch sensor inputs, Two LED drivers, Dedicated Wake, Reset, SMBus / BC-Link / SPI interfaces Reel size is 4,000 pieces CAP1128 DS00001622B-page 74  2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632770325 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2015 Microchip Technology Inc. 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 2015 Microchip Technology Inc. DS00001621B-page 1 General Description The CAP1166, which incorporates RightTouch® technology, is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains six (6) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1166 also contains six (6) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. The CAP1166 includes Multiple Pattern Touch recognition that allows the user to select a specific set of buttons to be touched simultaneously. If this pattern is detected, then a status bit is set and an interrupt generated. Additionally, the CAP1166 includes circuitry and support for enhanced sensor proximity detection. The CAP1166 offers multiple power states operating at low quiescent currents. In the Standby state of operation, one or more capacitive touch sensor inputs are active and all LEDs may be used. If a touch is detected, it will wake the system using the WAKE/SPI_MOSI pin. Deep Sleep is the lowest power state available, drawing 5uA (typical) of current. In this state, no sensor inputs are active. Driving the WAKE/SPI_MOSI pin or communications will wake the device. Applications • Desktop and Notebook PCs • LCD Monitors • Consumer Electronics • Appliances Features • Six (6) Capacitive Touch Sensor Inputs - Programmable sensitivity - Automatic recalibration - Individual thresholds for each button • Proximity Detection • Multiple Button Pattern Detection • Calibrates for Parasitic Capacitance • Analog Filtering for System Noise Sources • Press and Hold feature for Volume-like Applications • Multiple Communication Interfaces - SMBus / I2C compliant interface - SPI communications - Pin selectable communications protocol and multiple slave addresses (SMBus / I2C only) • Low Power Operation - 5uA quiescent current in Deep Sleep - 50uA quiescent current in Standby (1 sensor input monitored) - Samples one or more channels in Standby • Six (6) LED Driver Outputs - Open Drain or Push-Pull - Programmable blink, breathe, and dimness controls - Can be linked to Capacitive Touch Sensor inputs • Dedicated Wake output flags touches in low power state • System RESET pin • Available in 20-pin 4mm x 4mm QFN or 24-pin SSOP RoHS compliant package CAP1166 6 Channel Capacitive Touch Sensor with 6 LED Drivers CAP1166 DS00001621B-page 2  2015 Microchip Technology Inc. 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Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2015 Microchip Technology Inc. DS00001621B-page 3 CAP1166 Table of Contents 1.0 Block Diagram ................................................................................................................................................................................. 4 2.0 Pin Description ................................................................................................................................................................................ 5 3.0 Electrical Specifications .................................................................................................................................................................. 9 4.0 Communications ........................................................................................................................................................................... 12 5.0 General Description ...................................................................................................................................................................... 23 6.0 Register Description ...................................................................................................................................................................... 29 7.0 Package Information ..................................................................................................................................................................... 67 Appendix A: Device Delta ................................................................................................................................................................... 72 Appendix B: Data Sheet Revision History ........................................................................................................................................... 74 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77  2015 Microchip Technology Inc. DS00001621B-page 4 CAP1166 1.0 BLOCK DIAGRAM SMBus / BC-Link or SPI Slave Protocol SMCLK / BC_CLK / SPI_CLK SMDATA BC_DATA / SPI_MSIO/ SPI_MISO VDD GND ALERT# / BC_IRQ# Capacitive Touch Sensing Algorithm LED1 CS1 CS2 CS3 CS4 CS5 CS6 LED Driver, Breathe, and Dimness control RESET WAKE / SPI_MOSI ADDR_COMM SPI_CS# LED2 LED3 LED4 LED5 LED6 CAP1166 DS00001621B-page 5  2015 Microchip Technology Inc. 2.0 PIN DESCRIPTION FIGURE 2-1: CAP1166 Pin Diagram (20-Pin QFN) 1 2 3 4 15 14 13 12 20 19 18 17 6 7 8 9 5 10 11 16 CAP1166 20 pin QFN GND LED2 LED3 LED4 LED5 LED6 SMCLK / BC_CLK / SPI_CLK WAKE / SPI_MOSI SPI_CS# LED1 SMDATA / BC_DATA / SPI_MSIO / SPI_MISO RESET CS1 CS2 CS3 CS6 CS5 ADDR_COMM CS4 ALERT# / BC_IRQ# VDD  2015 Microchip Technology Inc. DS00001621B-page 6 CAP1166 FIGURE 2-2: CAP1166 Pin Diagram (24-pin SSOP) TABLE 2-1: PIN DESCRIPTION FOR CAP1166 Pin Number (QFN 20) Pin Number (SSOP 24) Pin Name Pin Function Pin Type Unused Connection 1 4 SPI_CS# Active low chip-select for SPI bus DI (5V) Connect to Ground 2 5 WAKE / SPI_- MOSI WAKE - Active high wake / interrupt output Standby power state - requires pull-down resistor WAKE - Active high wake input - requires pull-down resistor Deep Sleep power state DO Pull-down Resistor DI SPI_MOSI - SPI Master-Out-Slave-In port when used in normal mode DI (5V) Connect to GND CAP1166 24 SSOP 24 23 22 21 20 17 19 18 16 13 15 14 1 2 3 4 5 8 6 7 9 12 10 11 CS1 RESET SPI_CS# WAKE / SPI_MOSI SMDATA /SPI_MSIO / SPI_MISO SMCLK / SPI_CLK LED1 LED2 LED3 GND LED4 GND LED5 LED6 ALERT# / BC_IRQ# ADDR_COMM CS6 CS5 CS4 CS3 CS2 VDD N/C N/C CAP1166 DS00001621B-page 7  2015 Microchip Technology Inc. 3 6 SMDATA / SPI_MSIO / SPI_MISO SMDATA - Bi-directional, open-drain SMBus data - requires pull-up resistor DIOD (5V) n/a SPI_MSIO - SPI Master-Slave-In-Out bidirectional port when used in bi-directional mode DIO SPI_MISO - SPI Master-In-Slave-Out port when used in normal mode DO 4 8 SMCLK / SPI_CLK SMCLK - SMBus clock input - requires pull-up resistor DI (5V) SPI_CLK - SPI clock input DI (5V) n/a 5 9 LED1 Open drain LED 1 driver (default) OD (5V) Connect to Ground Push-pull LED 1 driver DO leave open or connect to Ground 6 10 LED2 Open drain LED 2 driver (default) OD (5V) Connect to Ground Push-pull LED 2 driver DO leave open or connect to Ground 7 11 LED3 Open drain LED 3 driver (default) OD (5V) Connect to Ground Push-pull LED 3 driver DO leave open or connect to Ground 8 13 LED4 Open drain LED 4 driver (default) OD (5V) Connect to Ground Push-pull LED 4 driver DO leave open or connect to Ground 9 15 LED5 Open drain LED 5 driver (default) OD (5V) Connect to Ground Push-pull LED 5 driver DO leave open or connect to Ground 10 16 LED6 Open drain LED 6 driver (default) OD (5V) Connect to Ground Push-pull LED 6 driver DO leave open or connect to Ground TABLE 2-1: PIN DESCRIPTION FOR CAP1166 (CONTINUED) Pin Number (QFN 20) Pin Number (SSOP 24) Pin Name Pin Function Pin Type Unused Connection  2015 Microchip Technology Inc. DS00001621B-page 8 CAP1166 APPLICATION NOTE: When the ALERT# pinis configured as an active low output, it will be open drain. When it is configured as an active high output, it will be push-pull. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the CAP1166 is unpowered. APPLICATION NOTE: The SPI_CS# pin should be grounded when SMBus, or I2C,communications are used. The pin types are described in Table 2-2. All pins labeled with (5V) are 5V tolerant. 11 17 ALERT# ALERT# - Active low alert / interrupt output for SMBus alert or SPI interrupt - requires pull-up resistor (default) OD (5V) Connect to GND ALERT# - Active high push-pull alert / interrupt output for SMBus alert or SPI interrupt DO High-Z 12 18 ADDR_ COMM Address / communications select pin - pull-down resistor determines address / communications mechanism AI n/a 13 19 CS6 Capacitive Touch Sensor Input 6 AIO Connect to Ground 14 20 CS5 Capacitive Touch Sensor Input 5 AIO Connect to Ground 15 21 CS4 Capacitive Touch Sensor Input 4 AIO Connect to Ground 16 22 CS3 Capacitive Touch Sensor Input 3 AIO Connect to Ground 17 23 CS2 Capacitive Touch Sensor Input 2 AIO Connect to Ground 18 24 CS1 Capacitive Touch Sensor Input 1 AIO Connect to Ground 19 1 VDD Positive Power supply Power n/a 20 1 RESET Active high soft reset for system - resets all registers to default values. If not used, connect to ground. DI (5V) Connect to Ground Bottom Pad 12 GND Ground Power n/a 14 GND Ground Power n/a TABLE 2-1: PIN DESCRIPTION FOR CAP1166 (CONTINUED) Pin Number (QFN 20) Pin Number (SSOP 24) Pin Name Pin Function Pin Type Unused Connection CAP1166 DS00001621B-page 9  2015 Microchip Technology Inc. TABLE 2-2: PIN TYPES Pin Type Description Power This pin is used to supply power or ground to the device. DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant. AIO Analog Input / Output -This pin is used as an I/O for analog signals. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. DO Push-pull Digital Output - This pin is used as a digital output and can sink and source current. DIO Push-pull Digital Input / Output - This pin is used as an I/O for digital signals.  2015 Microchip Technology Inc. DS00001621B-page 10 CAP1166 3.0 ELECTRICAL SPECIFICATIONS Note 3-1 Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3-2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between V5VT_PIN and VDD must never exceed 3.6V. Note 3-3 The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 3x3 matrix of 0.3mm (12mil) vias at 1.0mm pitch connected to the ground plane with a 2.5 x 2.5mm thermal landing. Note 3-4 Junction to Ambient (θJA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the θJA is approximately 60°C/W including localized PCB temperature increase. TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Voltage on 5V tolerant pins (V5VT_PIN) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_PIN - VDD|) Note 3-2 0 to 3.6 V Voltage on VDD pin -0.3 to 4 V Voltage on any other pin to GND -0.3 to VDD + 0.3 V Package Power Dissipation up to TA = 85°C for 20 pin QFN (see Note 3-3) 0.9 W Junction to Ambient (θJA) (see Note 3-4) 58 °C/W Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 8000 V CAP1166 DS00001621B-page 11  2015 Microchip Technology Inc. TABLE 3-2: ELECTRICAL SPECIFICATIONS VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions DC Power Supply Voltage VDD 3.0 3.3 3.6 V Supply Current ISTBY 120 170 uA Standby state active 1 sensor input monitored No LEDs active Default conditions (8 avg, 70ms cycle time) ISTBY 50 uA Standby state active 1 sensor input monitored No LEDs active 1 avg, 140ms cycle time, IDSLEEP 5 15 uA Deep Sleep state active LEDs at 100% or 0% Duty Cycle No communications TA < 40°C 3.135 < VDD < 3.465V IDD 500 600 uA Capacitive Sensing Active No LEDs active Capacitive Touch Sensor Inputs Maximum Base Capacitance CBASE 50 pF Pad untouched Minimum Detectable Capacitive Shift ΔCTOUCH 20 fF Pad touched - default conditions (1 avg, 35ms cycle time, 1x sensitivity) Recommended Cap Shift ΔCTOUCH 0.1 2 pF Pad touched - Not tested Power Supply Rejection PSR ±3 ±10 counts / V Untouched Current Counts Base Capacitance 5pF - 50pF Maximum sensitivity Negative Delta Counts disabled All other parameters default Timing RESET Pin Delay tRST_DLY 10 ms Time to communications ready tCOMM_DLY 15 ms Time to first conversion ready tCONV_DLY 170 200 ms LED Drivers Duty Cycle DUTYLED 0 100 % Programmable Drive Frequency fLED 2 kHz Sinking Current ISINK 24 mA VOL = 0.4 Sourcing Current ISOURCE 24 mA VOH = VDD - 0.4 Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered I/O Pins Output Low Voltage VOL 0.4 V ISINK_IO = 8mA Output High Voltage VOH VDD - 0.4 V ISOURCE_IO = 8mA  2015 Microchip Technology Inc. DS00001621B-page 12 CAP1166 Note 3-5 The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage. Note 3-6 The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage. Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered RESET Pin Release to conversion ready tRESET 170 200 ms SMBus Timing Input Capacitance CIN 5 pF Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 us Start Setup Time tSU:STA 0.6 us Start Hold Time tHD:STA 0.6 us Stop Setup Time tSU:STO 0.6 us Data Hold Time tHD:DAT 0 us When transmitting to the master Data Hold Time tHD:DAT 0.3 us When receiving from the master Data Setup Time tSU:DAT 0.6 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line SPI Timing Clock Period tP 250 ns Clock Low Period tLOW 0.4 x tP 0.6 x tP ns Clock High Period tHIGH 0.4 x tP 0.6 x tP ns Clock Rise / Fall time tRISE / tFALL 0.1 x tP ns Data Output Delay tD:CLK 10 ns Data Setup Time tSU:DAT 20 ns Data Hold Time tHD:DAT 20 ns SPI_CS# to SPI_CLK setup time tSU:CS 0 ns Wake Time tWAKE 10 20 us SPI_CS# asserted to CLK assert TABLE 3-2: ELECTRICAL SPECIFICATIONS (CONTINUED) VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions  2015 Microchip Technology Inc. DS00001621B-page 13 CAP1166 4.0 COMMUNICATIONS 4.1 Communications The CAP1166communicates using the 2-wire SMBus or I2C bus, the 2-wire proprietary BC-Link, or the SPI bus. If the proprietary BC-Link protocol is required for your application, please contact your Microchip representative for ordering instructions. Regardless of communication mechanism, the device functionality remains unchanged. The communications mechanism as well as the SMBus (or I2C) slave address is determined by the resistor connected between the ADDR_COMM pin and ground as shown in Table 4-1. 4.1.1 SMBUS (I2C) COMMUNICATIONS When configured to communicate via the SMBus, the CAP1166 supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block. In addition, the device supports I2C formatting for block read and block write protocols. APPLICATION NOTE: For SMBus/I2C communications, the SPI_CS# pin is not used and should be grounded; any data presented to this pin will be ignored. See Section 4.2 and Section 4.3 for more information on the SMBus bus and protocols respectively. 4.1.2 SPI COMMUNICATIONS When configured to communicate via the SPI bus, the CAP1166supports both bi-directional 3-wire and normal 4-wire protocols and uses the SPI_CS# pin to enable communications. APPLICATION NOTE: See Section 4.5 and Section 4.6 for more information on the SPI bus and protocols respectively.Upon power up, the CAP1166 will not respond to any communications for up to 15ms. After this time, full functionality is available. 4.2 System Management Bus The CAP1166 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1166 will not stretch the clock signal. TABLE 4-1: ADDR_COMM PIN DECODE Pull-Down Resistor (+/- 5%) Protocol Used SMBus Address GND SPI Communications using Normal 4-wire Protocol Used n/a 56k SPI Communications using BiDirectional 3-wire Protocol Used n/a 68k Reserved n/a 82k SMBus / I2C 0101_100(r/w) 100k SMBus / I2C 0101_011(r/w) 120k SMBus / I2C 0101_010(r/w) 150k SMBus / I2C 0101_001(r/w) VDD SMBus / I2C 0101_000(r/w) CAP1166 DS00001621B-page 14  2015 Microchip Technology Inc. 4.2.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.2.2 SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the slave device. See Table 4-1 for available SMBus addresses. 4.2.3 SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.2.4 SMBUS ACK AND NACK BITS The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives except the last data byte. 4.2.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1166 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications. 4.2.6 SMBUS TIMEOUT The CAP1166 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the SMCLK pin is held low, the device will timeout and reset the SMBus interface. The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register (see Section 6.6, "Configuration Registers"). 4.2.7 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the CAP1166 in an I2C system, refer to AN 14.0 Dedicated Slave Devices in I2C Systems. FIGURE 4-1: SMBus Timing Diagram SMDATA SMCLK TLOW TRISE THIGH TFALL TBUF THD:STA P S S - Start Condition P - Stop Condition THD:DAT TSU:DAT TSU:STA THD:STA P TSU:STO S  2015 Microchip Technology Inc. DS00001621B-page 15 CAP1166 1. CAP1166 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2. Minimum frequency for SMBus communications is 10kHz. 3. The SMBus slave protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the CAP1166 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4. The SMBus slave protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200µs (idle condition). This function is disabled by default in the CAP1166 and can be enabled by writing to the TIMEOUT bit. I2C does not have an idle condition. 5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). 6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read / write is transmitted. The CAP1166 supports I2C formatting only. 4.3 SMBus Protocols The CAP1166 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid protocols as shown below. All of the below protocols use the convention in Table 4-2. 4.3.1 SMBUS WRITE BYTE The Write Byte is used to write one byte of data to a specific register as shown in Table 4-3. 4.3.2 SMBUS READ BYTE The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4-4. 4.3.3 SMBUS SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4-5. APPLICATION NOTE: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). TABLE 4-2: PROTOCOL FORMAT Data Sent to Device Data Sent to the HOst Data sent Data sent TABLE 4-3: WRITE BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK Stop 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1 TABLE 4-4: READ BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data NACK Stop 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh 1 0 -> 1 TABLE 4-5: SEND BYTE PROTOCOL Start Slave Address WR ACK Register Address ACK Stop 1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 CAP1166 DS00001621B-page 16  2015 Microchip Technology Inc. 4.3.4 SMBUS RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4-6. APPLICATION NOTE: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). 4.4 I2C Protocols The CAP1166 supports I2C Block Write and Block Read. The protocols listed below use the convention in Table 4-2. 4.4.1 BLOCK WRITE The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 4-7. APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.4.2 BLOCK READ The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 4-8. APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically incremented after every data byte is received. It will wrap from FFh to 00h. 4.5 SPI Interface The SMBus has a predefined packet structure, the SPI does not. The SPI Bus can operate in two modes of operation, normal 4-wire mode and bi-directional 3-wire mode. All SPI commands consist of 8-bit packets sent to a specific slave device (identified by the CS pin). The SPI bus will latch data on the rising edge of the clock and the clock and data both idle high. All commands are supported via both operating modes. The supported commands are: Reset Serial interface, set address pointer, write command and read command. Note that all other codes received during the command phase are ignored and have no effect on the operation of the device. TABLE 4-6: RECEIVE BYTE PROTOCOL Start Slave Address RD ACK Register Data NACK Stop 1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1 TABLE 4-7: BLOCK WRITE PROTOCOL Start Slave Address WR ACK Register Address ACK Register Data ACK 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK . . . Register Data ACK Stop XXh 0 XXh 0 . . . XXh 0 0 -> 1 TABLE 4-8: BLOCK READ PROTOCOL Start Slave Address WR ACK Register Address ACK Start Slave Address RD ACK Register Data 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK . . . Register Data NACK Stop 0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1  2015 Microchip Technology Inc. DS00001621B-page 17 CAP1166 4.5.1 SPI NORMAL MODE The SPI Bus can operate in two modes of operation, normal and bi-directional mode. In the normal mode of operation, there are dedicated input and output data lines. The host communicates by sending a command along the CAP1166 SPI_MOSI data line and reading data on the SPI_MISO data line. Both communications occur simultaneously which allows for larger throughput of data transactions. All basic transfers consist of two 8 bit transactions from the Master device while the slave device is simultaneously sending data at the current address pointer value. Data writes consist of two or more 8-bit transactions. The host sends a specific write command followed by the data to write the address pointer. Data reads consist of one or more 8-bit transactions. The host sends the specific read data command and continues clocking for as many data bytes as it wishes to receive. 4.5.2 SPI BI-DIRECTIONAL MODE In the bi-directional mode of operation, the SPI data signals are combined into the SPI_MSIO line, which is shared for data received by the device and transmitted by the device. The protocol uses a simple handshake and turn around sequence for data communications based on the number of clocks transmitted during each phase. All basic transfers consist of two 8 bit transactions. The first is an 8 bit command phase driven by the Master device. The second is by an 8 bit data phase driven by the Master for writes, and by the CAP1166 for read operations. The auto increment feature of the address pointer allows for successive reads or writes. The address pointer will return to 00h after reaching FFh. 4.5.3 SPI_CS# PIN The SPI Bus is a single master, multiple slave serial bus. Each slave has a dedicated CS pin (chip select) that the master asserts low to identify that the slave is being addressed. There are no formal addressing options. 4.5.4 ADDRESS POINTER All data writes and reads are accessed from the current address pointer. In both Bi-directional mode and Full Duplex mode, the Address pointer is automatically incremented following every read command or every write command. The address pointer will return to 00h after reaching FFh. 4.5.5 SPI TIMEOUT The CAP1166 does not detect any timeout conditions on the SPI bus. FIGURE 4-2: SPI Timing SPI_MSIO or SPI_MOSI or SPI_MISO SPI_CLK tLOW tRISE tHIGH tFALL tD:CLK tHD:DAT tSU:DAT tP  2015 Microchip Technology Inc. DS00001621B-page 18 CAP1166 4.6 Normal SPI Protocols When operating in normal mode, the SPI bus internal address pointer is incremented depending upon which command has been transmitted. Multiple commands may be transmitted sequentually so long as the SPI_CS# pin is asserted low. Figure 4-3 shows an example of this operation. 4.6.1 RESET INTERFACE Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation. FIGURE 4-3: Example SPI Bus Communication - Normal Mode SPI_CS# SPI_MISO SPI_MOSI SPI Address Pointer SPI Data output buffer Register Address / Data 7Ah XXh (invalid) XXh (invalid) YYh (invalid) 7Ah 7Dh 41h YYh (invalid) 7Eh 66h XXh (invalid) 45h 7Dh 41h AAh (invalid) AAh (invalid) 7Fh 7Fh 55h (invalid) 66h 7Fh AAh 7Dh 43h 40h 78h 7Fh XXh (invalid) 7Fh 56h 40h / 56h 41h / 45h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 45h 40h / 56h 41h / 45h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 42h AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 55h 7Fh AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 41h 66h 42h AAh 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 44h 80h 40h 80h 40h 56h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 43h 55h 7Fh 7Fh 55h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h /78h 80h 45h 43h 46h 78h 40h / 56h 41h / 66h 42h / AAh 43h / 55h 44h / 80h 45h / 43h 46h / 78h 00h XXh Indicates SPI Address pointer incremented  2015 Microchip Technology Inc. DS00001621B-page 19 CAP1166 4.6.2 SET ADDRESS POINTER The Set Address Pointer command sets the Address pointer for subsequent reads and writes of data. The pointer is set on the rising edge of the final data bit. At the same time, the data that is to be read is fetched and loaded into the internal output buffer but is not transmitted. 4.6.3 WRITE DATA The Write Data protocol updates the contents of the register referenced by the address pointer. As the command is processed, the data to be read is fetched and loaded into the internal output buffer but not transmitted. Then, the register is updated with the data to be written. Finally, the address pointer is incremented. FIGURE 4-4: SPI Reset Interface Command - Normal Mode FIGURE 4-5: SPI Set Address Pointer Command - Normal Mode Master SPDOUT SPI_MOSI SPI_CS# SPI_CLK Reset - 7Ah Reset - 7Ah Invalid register data 00h – Internal Data buffer empty SPI_MISO Master Drives Slave Drives ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ Master SPDOUT SPI_MOSI Register Address SPI_CS# SPI_CLK Set Address Pointer – 7Dh SPI_MISO Unknown, Invalid Data Unknown, Invalid Data Master Drives Slave Drives Address pointer set ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ CAP1166 DS00001621B-page 20  2015 Microchip Technology Inc. 4.6.4 READ DATA The Read Data protocol is used to read data from the device. During the normal mode of operation, while the device is receiving data, the CAP1166 is simultaneously transmitting data to the host. For the Set Address commands and the Write Data commands, this data may be invalid and it is recommended that the Read Data command is used. FIGURE 4-6: SPI Write Command - Normal Mode FIGURE 4-7: SPI Read Command - Normal Mode Master SPDOUT SPI_MOSI Data to Write SPI_CS# SPI_CLK Write Command – 7Eh Unknown, Invalid Data Old Data at Current Address Pointer SPI_MISO Master Drives Slave Drives 1. Data written at current address pointer 2. Address pointer incremented Master SPDOUT SPI_MOSI Master Drives Slave Drives SPI_CLK First Read Command – 7Fh SPI_CS# SPI_MISO Invalid, Unknown Data * ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Subsequent Read Commands – 7F Data at Current Address Pointer Address Pointer Incremented ** ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ * The first read command after any other command will return invalid data for the first byte. Subsequent read commands will return the data at the Current Address Pointer ** The Address Pointer is incremented 8 clocks after the Read Command has been received. Therefore continually sending Read Commands will result in each command reporting new data. Once Read Commands have been finished, the last data byte will be read during the next 8 clocks for any command  2015 Microchip Technology Inc. DS00001621B-page 21 CAP1166 4.7 Bi-Directional SPI Protocols 4.7.1 RESET INTERFACE Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data, the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation. 4.7.2 SET ADDRESS POINTER Sets the address pointer to the register to be accessed by a read or write command. This command overrides the autoincrementing of the address pointer. FIGURE 4-8: SPI Read Command - Normal Mode - Full FIGURE 4-9: SPI Reset Interface Command - Bi-directional Mode Master SPDOUT SPI_MOSI Master Drives Slave Drives SPI_CLK Read Command – 7Fh SPI_CS# Data at previously set register address = current address pointer SPI_MISO ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Data at previously set register address = current address pointer (SPI) XXh 1. Register Read Address updated to Current SPI Read Address pointer 1. Register data loaded into output buffer = data at current address pointer 1. Output buffer transmitted = data at previous address pointer + 1 = current address pointer 1. Register Read Address incremented = current address pointer + 1 1. SPI Read Address Incremented = new current address pointer 2. Register Read Address Incremented = current address pointer +1 Register Data loaded into Output buffer = data at current address pointer + 1 1. Output buffer transmitted = data at current address pointer + 1 2. Flag set to increment SPI Read Address at end of next 8 clocks ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Data at previously set register address = current address pointer (SPI) 1. Register data loaded into output buffer = data at current address pointer 1. Output buffer transmitted = data at previous register address pointer + 1 = current address pointer 1. Output buffer transmitted = data at current address pointer + 1 2. Flag set to increment SPI Read Address at end of next 8 clocks Subsequent Read Commands – 7Fh 1. Register Read Address updated to Current SPI Read Address pointer. 2. Register Read Address incremented = current address pointer +1 – end result = register address pointer doesn’t change Master SPDOUT SPI_MSIO SPI_CS# SPI_CLK Reset - 7Ah Reset - 7Ah ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ CAP1166 DS00001621B-page 22  2015 Microchip Technology Inc. 4.7.3 WRITE DATA Writes data value to the register address stored in the address pointer. Performs auto increment of address pointer after the data is loaded into the register. 4.7.4 READ DATA Reads data referenced by the address pointer. Performs auto increment of address pointer after the data is transferred to the Master. FIGURE 4-10: SPI Set Address Pointer Command - Bi-directional Mode FIGURE 4-11: SPI Write Data Command - Bi-directional Mode FIGURE 4-12: SPI Read Data Command - Bi-directional Mode Master SPDOUT SPI_MSIO Register Address SPI_CS# SPI_CLK Set Address Pointer – 7Dh ‘0’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Master SPDOUT SPI_MSIO Register Write Data SPI_CS# SPI_CLK Write Command – 7Eh ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ Master SPDOUT SPI_MSIO Master Drives Slave Drives Indeterminate Register Read Data SPI_CLK Read Command – 7Fh SPI_CS# ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’  2015 Microchip Technology Inc. DS00001621B-page 23 CAP1166 4.8 BC-Link Interface The BC-Link is a proprietary bus developed to allow communication between a host controller device to a companion device. This device uses this serial bus to read and write registers and for interrupt processing. The interface uses a data port concept, where the base interface has an address register, data register and a control register, defined in the 8051’s SFR space. Refer to documentation for the BC-Link compatible host controller for details on how to access the CAP1166 via the BCLink Interface.  2015 Microchip Technology Inc. DS00001621B-page 24 CAP1166 5.0 GENERAL DESCRIPTION The CAP1166 is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It contains six (6) individual capacitive touch sensor inputs with programmable sensitivity for use in touch sensor applications. Each sensor input automatically recalibrates to compensate for gradual environmental changes. The CAP1166 also contains six (6) low side (or push-pull) LED drivers that offer full-on / off, variable rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the sensor inputs to be actuated when a touch is detected. As well, each LED driver may be individually controlled via a host controller. Finally, the device contains a dedicated RESET pin to act as a soft reset by the system. The CAP1166 offers multiple power states. It operates at the lowest quiescent current during its Deep Sleep state. In the low power Standby state, it can monitor one or more channels and respond to communications normally. The device contains a wake pin (WAKE/SPI_MOSI) output to wake the system when a touch is detected in Standby and to wake the device from Deep Sleep. The device communicates with a host controller using the SPI bus, or via SMBus / I2C. The host controller may poll the device for updated information at any time or it may configure the device to flag an interrupt whenever a touch is detected on any sensor pad. A typical system diagram is shown in Figure 5-1. CAP1166 DS00001621B-page 25  2015 Microchip Technology Inc. 5.1 Power States The CAP1166 has three operating states depending on the status of the STBY and DSLEEP bits. When the device transitions between power states, previously detected touches (for inactive channels) are cleared and the status bits reset. 1. Fully Active - The device is fully active. It is monitoring all active capacitive sensor inputs and driving all LED channels as defined. 2. Standby - The device is in a lower power state. It will measure a programmable number of channels using the Standby Configuration controls (see Section 6.20 through Section 6.22). Interrupts will still be generated based on the active channels. The device will still respond to communications normally and can be returned to the Fully FIGURE 5-1: System Diagram for CAP1166 CAP1166 CS4 SMDATA / BC_DATA / SPI_MSIO / SPI_MISO SMCLK / BC_CLK / SPI_CLK VDD Embedded Controller ALERT# / BC_IRQ# CS5 CS6 3.3V – 5V CS3 CS2 CS1 WAKE / SPI_MOSI RESET SPI_CS# ADDR_COMM LED6 LED5 LED4 LED1 LED2 LED3 3.3V – 5V Touch Button Touch Button Touch Button Touch Button Touch Button Touch Button  2015 Microchip Technology Inc. DS00001621B-page 26 CAP1166 Active state of operation by clearing the STBY bit. 3. Deep Sleep - The device is in its lowest power state. It is not monitoring any capacitive sensor inputs and not driving any LEDs. All LEDs will be driven to their programmed non-actuated state and no PWM operations will be done. While in Deep Sleep, the device can be awakened by SMBus or SPI communications targeting the device. This will not cause the DSLEEP to be cleared so the device will return to Deep Sleep once all communications have stopped. If the device is not communicating via the 4-wire SPI bus, then during this state of operation, if the WAKE/SPI_MOSI pin is driven high by an external source, the device will clear the DSLEEP bit and return to Fully Active. APPLICATION NOTE: In the Deep Sleep state, the LED output will be either high or low and will not be PWM’d at the min or max duty cycle. 5.2 RESET Pin The RESET pin is an active high reset that is driven from an external source. While it is asserted high, all the internal blocks will be held in reset including the communications protocol used. No capacitive touch sensor inputs will be sampled and the LEDs will not be driven. All configuration settings will be reset to default states and all readings will be cleared. The device will be held in Deep Sleep that can only be removed by driving the RESET pin low. This will cause the RESET status bit to be set to a logic ‘1’ and generate an interrupt. 5.3 WAKE/SPI_MOSI Pin Operation The WAKE / SPI_MOSI pin is a multi-function pin depending on device operation. When the device is configured to communicate using the 4-wire SPI bus, this pin is an input. However, when the CAP1166 is placed in Standby and is not communicating using the 4-wire SPI protocol, the WAKE pin is an active high output. In this condition, the device will assert the WAKE/SPI_MOSI pin when a touch is detected on one of its sampled sensor inputs. The pin will remain asserted until the INT bit has been cleared and then it will be de-asserted. When the CAP1166 is placed in Deep Sleep and it is not communicating using the 4-wire SPI protocol, the WAKE/SPI_- MOSI pin is monitored by the device as an input. If the WAKE/SPI_MOSI pin is driven high by an external source, the CAP1166will clear the DSLEEP bit causing the device to return to Fully Active. When the device is placed in Deep Sleep, this pin is a High-Z input and must have a pull-down resistor to GND for proper operation. 5.4 LED Drivers The CAP1166 contains six (6) LED drivers. Each LED driver can be linked to its respective capacitive touch sensor input or it can be controlled by the host. Each LED driver can be configured to operate in one of the following modes with either push-pull or open drain drive. 1. Direct - The LED is configured to be on or off when the corresponding input stimulus is on or off (or inverted). The brightness of the LED can be programmed from full off to full on (default). Additionally, the LED contains controls to individually configure ramping on, off, and turn-off delay. 2. Pulse 1 - The LED is configured to “Pulse” (transition ON-OFF-ON) a programmable number of times with programmable rate and min / max brightness. This behavior may be actuated when a press is detected or when a release is detected. 3. Pulse 2 - The LED is configured to “Pulse” while actuated and then “Pulse” a programmable number of times with programmable rate and min / max brightness when the sensor pad is released. 4. Breathe - The LED is configured to transition continuously ON-OFF-ON (i.e. to “Breathe”) with a programmable rate and min / max brightness. When an LED is not linked to a sensor and is actuated by the host, there’s an option to assert the ALERT# pin when the initiated LED behavior has completed. 5.4.1 LINKING LEDS TO CAPACITIVE TOUCH SENSOR INPUTS All LEDs can be linked to the corresponding capacitive touch sensor input so that when the sensor input detects a touch, the corresponding LED will be actuated at one of the programmed responses. CAP1166 DS00001621B-page 27  2015 Microchip Technology Inc. 5.5 Capacitive Touch Sensing The CAP1166 contains six (6) independent capacitive touch sensor inputs. Each sensor input has dynamic range to detect a change of capacitance due to a touch. Additionally, each sensor input can be configured to be automatically and routinely re-calibrated. 5.5.1 SENSING CYCLE Each capacitive touch sensor input has controls to be activated and included in the sensing cycle. When the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it finishes. The cycle polls through each active sensor input starting with CS1 and extending through CS6. As each capacitive touch sensor input is polled, its measurement is compared against a baseline “Not Touched” measurement. If the delta measurement is large enough, a touch is detected and an interrupt is generated. The sensing cycle time is programmable (see Section 6.10, "Averaging and Sampling Configuration Register"). 5.5.2 RECALIBRATING SENSOR INPUTS There are various options for recalibrating the capacitive touch sensor inputs. Recalibration re-sets the Base Count Registers (Section 6.24, "Sensor Input Base Count Registers") which contain the “not touched” values used for touch detection comparisons. APPLICATION NOTE: The device will recalibrate all sensor inputs that were disabled when it transitions from Standby. Likewise, the device will recalibrate all sensor inputs when waking out of Deep Sleep. 5.5.2.1 Manual Recalibration The Calibration Activate Registers (Section 6.11, "Calibration Activate Register") force recalibration of selected sensor inputs. When a bit is set, the corresponding capacitive touch sensor input will be recalibrated (both analog and digital). The bit is automatically cleared once the recalibration routine has finished. 5.5.2.2 Automatic Recalibration Each sensor input is regularly recalibrated at a programmable rate (see Section 6.17, "Recalibration Configuration Register"). By default, the recalibration routine stores the average 64 previous measurements and periodically updates the base “not touched” setting for the capacitive touch sensor input. 5.5.2.3 Negative Delta Count Recalibration It is possible that the device loses sensitivity to a touch. This may happen as a result of a noisy environment, an accidental recalibration during a touch, or other environmental changes. When this occurs, the base untouched sensor input may generate negative delta count values. The NEG_DELTA_CNT bits (see Section 6.17, "Recalibration Configuration Register") can be set to force a recalibration after a specified number of consecutive negative delta readings. 5.5.2.4 Delayed Recalibration It is possible that a “stuck button” occurs when something is placed on a button which causes a touch to be detected for a long period. By setting the MAX_DUR_EN bit (see Section 6.6, "Configuration Registers"), a recalibration can be forced when a touch is held on a button for longer than the duration specified in the MAX_DUR bits (see Section 6.8, "Sensor Input Configuration Register"). Note: During this recalibration routine, the sensor inputs will not detect a press for up to 200ms and the Sensor Base Count Register values will be invalid. In addition, any press on the corresponding sensor pads will invalidate the recalibration. Note: Automatic recalibration only works when the delta count is below the active sensor input threshold. It is disabled when a touch is detected. Note: During this recalibration, the device will not respond to touches.  2015 Microchip Technology Inc. DS00001621B-page 28 CAP1166 5.5.3 PROXIMITY DETECTION Each sensor input can be configured to detect changes in capacitance due to proximity of a touch. This circuitry detects the change of capacitance that is generated as an object approaches, but does not physically touch, the enabled sensor pad(s). When a sensor input is selected to perform proximity detection, it will be sampled from 1x to 128x per sampling cycle. The larger the number of samples that are taken, the greater the range of proximity detection is available at the cost of an increased overall sampling time. 5.5.4 MULTIPLE TOUCH PATTERN DETECTION The multiple touch pattern (MTP) detection circuitry can be used to detect lid closure or other similar events. An event can be flagged based on either a minimum number of sensor inputs or on specific sensor inputs simultaneously exceeding an MTP threshold or having their Noise Flag Status Register bits set. An interrupt can also be generated. During an MTP event, all touches are blocked (see Section 6.15, "Multiple Touch Pattern Configuration Register"). 5.5.5 LOW FREQUENCY NOISE DETECTION Each sensor input has an EMI noise detector that will sense if low frequency noise is injected onto the input with sufficient power to corrupt the readings. If this occurs, the device will reject the corrupted sample and set the corresponding bit in the Noise Status register to a logic ‘1’. 5.5.6 RF NOISE DETECTION Each sensor input contains an integrated RF noise detector. This block will detect injected RF noise on the CS pin. The detector threshold is dependent upon the noise frequency. If RF noise is detected on a CS line, that sample is removed and not compared against the threshold. 5.6 ALERT# Pin The ALERT# pin is an active low (or active high when configured) output that is driven when an interrupt event is detected. Whenever an interrupt is generated, the INT bit (see Section 6.1, "Main Control Register") is set. The ALERT# pin is cleared when the INT bit is cleared by the user. Additionally, when the INT bit is cleared by the user, status bits are only cleared if no touch is detected. 5.6.1 SENSOR INTERRUPT BEHAVIOR The sensor interrupts are generated in one of two ways: 1. An interrupt is generated when a touch is detected and, as a user selectable option, when a release is detected (by default - see Section 6.6). See Figure 5-3. 2. If the repeat rate is enabled then, so long as the touch is held, another interrupt will be generated based on the programmed repeat rate (see Figure 5-2). When the repeat rate is enabled, the device uses an additional control called MPRESS that determines whether a touch is flagged as a simple “touch” or a “press and hold”. The MPRESS[3:0] bits set a minimum press timer. When the button is touched, the timer begins. If the sensor pad is released before the minimum press timer expires, it is flagged as a touch and an interrupt is generated upon release. If the sensor input detects a touch for longer than this timer value, it is flagged as a “press and hold” event. So long as the touch is held, interrupts will be generated at the programmed repeat rate and upon release (if enabled). APPLICATION NOTE: Figure 5-2 and Figure 5-3 show default operation which is to generate an interrupt upon sensor pad release and an active-low ALERT# pin. APPLICATION NOTE: The host may need to poll the device twice to determine that a release has been detected. Note: Delayed recalibration only works when the delta count is above the active sensor input threshold. If enabled, it is invoked when a sensor pad touch is held longer than the MAX_DUR bit setting. CAP1166 DS00001621B-page 29  2015 Microchip Technology Inc. FIGURE 5-2: Sensor Interrupt Behavior - Repeat Rate Enabled FIGURE 5-3: Sensor Interrupt Behavior - No Repeat Rate Enabled Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Min Press Setting (280ms) Interrupt on Touch Button Repeat Rate (175ms) Button Repeat Rate (175ms) Interrupt on Release (optional) ALERT# pin (active low) Touch Detected INT bit Button Status Write to INT bit Polling Cycle (35ms) Interrupt on Touch Interrupt on Release (optional) ALERT# pin (active low)  2015 Microchip Technology Inc. DS00001621B-page 30 CAP1166 6.0 REGISTER DESCRIPTION The registers shown in Table 6-1 are accessible through the communications protocol. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Address R/W Register Name Function Default Value Page 00h R/W Main Control Controls general power states and power dissipation 00h Page 33 02h R General Status Stores general status bits 00h Page 34 03h R Sensor Input Status Returns the state of the sampled capacitive touch sensor inputs 00h Page 34 04h R LED Status Stores status bits for LEDs 00h Page 34 0Ah R Noise Flag Status Stores the noise flags for sensor inputs 00h Page 35 10h R Sensor Input 1 Delta Count Stores the delta count for CS1 00h Page 35 11h R Sensor Input 2 Delta Count Stores the delta count for CS2 00h Page 35 12h R Sensor Input 3 Delta Count Stores the delta count for CS3 00h Page 35 13h R Sensor Input 4 Delta Count Stores the delta count for CS4 00h Page 35 14h R Sensor Input 5 Delta Count Stores the delta count for CS5 00h Page 35 15h R Sensor Input 6 Delta Count Stores the delta count for CS6 00h Page 35 1Fh R/W Sensitivity Control Controls the sensitivity of the threshold and delta counts and data scaling of the base counts 2Fh Page 36 20h R/W Configuration Controls general functionality 20h Page 37 21h R/W Sensor Input Enable Controls whether the capacitive touch sensor inputs are sampled 3Fh Page 38 22h R/W Sensor Input Configuration Controls max duration and auto-repeat delay for sensor inputs operating in the full power state A4h Page 39 23h R/W Sensor Input Configuration 2 Controls the MPRESS controls for all sensor inputs 07h Page 40 24h R/W Averaging and Sampling Config Controls averaging and sampling window 39h Page 41 26h R/W Calibration Activate Forces re-calibration for capacitive touch sensor inputs 00h Page 42 27h R/W Interrupt Enable Enables Interrupts associated with capacitive touch sensor inputs 3Fh Page 42 28h R/W Repeat Rate Enable Enables repeat rate for all sensor inputs 3Fh Page 43 2Ah R/W Multiple Touch Configuration Determines the number of simultaneous touches to flag a multiple touch condition 80h Page 43 2Bh R/W Multiple Touch Pattern Configuration Determines the multiple touch pattern (MTP) configuration 00h Page 44 CAP1166 DS00001621B-page 31  2015 Microchip Technology Inc. 2Dh R/W Multiple Touch Pattern Determines the pattern or number of sensor inputs used by the MTP circuitry 3Fh Page 45 2Fh R/W Recalibration Configuration Determines re-calibration timing and sampling window 8Ah Page 45 30h R/W Sensor Input 1 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 1 40h Page 47 31h R/W Sensor Input 2 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 2 40h Page 47 32h R/W Sensor Input 3 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 3 40h Page 47 33h R/W Sensor Input 4 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 4 40h Page 47 34h R/W Sensor Input 5 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 5 40h Page 47 35h R/W Sensor Input 6 Threshold Stores the delta count threshold to determine a touch for Capacitive Touch Sensor Input 6 40h Page 47 38h R/W Sensor Input Noise Threshold Stores controls for selecting the noise threshold for all sensor inputs 01h Page 47 Standby Configuration Registers 40h R/W Standby Channel Controls which sensor inputs are enabled while in standby 00h Page 47 41h R/W Standby Configuration Controls averaging and cycle time while in standby 39h Page 48 42h R/W Standby Sensitivity Controls sensitivity settings used while in standby 02h Page 49 43h R/W Standby Threshold Stores the touch detection threshold for active sensor inputs in standby 40h Page 50 44h R/W Configuration 2 Stores additional configuration controls for the device 40h Page 37 Base Count Registers 50h R Sensor Input 1 Base Count Stores the reference count value for sensor input 1 C8h Page 50 51h R Sensor Input 2 Base Count Stores the reference count value for sensor input 2 C8h Page 50 52h R Sensor Input 3 Base Count Stores the reference count value for sensor input 3 C8h Page 50 53h R Sensor Input 4 Base Count Stores the reference count value for sensor input 4 C8h Page 50 54h R Sensor Input 5 Base Count Stores the reference count value for sensor input 5 C8h Page 50 55h R Sensor Input 6 Base Count Stores the reference count value for sensor input 6 C8h Page 50 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page  2015 Microchip Technology Inc. DS00001621B-page 32 CAP1166 LED Controls 71h R/W LED Output Type Controls the output type for the LED outputs 00h Page 50 72h R/W Sensor Input LED Linking Controls linking of sensor inputs to LED channels 00h Page 51 73h R/W LED Polarity Controls the output polarity of LEDs 00h Page 51 74h R/W LED Output Control Controls the output state of the LEDs 00h Page 52 77h R/W Linked LED Transition Control Controls the transition when LEDs are linked to CS channels 00h Page 53 79h R/W LED Mirror Control Controls the mirroring of duty cycles for the LEDs 00h Page 54 81h R/W LED Behavior 1 Controls the behavior and response of LEDs 1 - 4 00h Page 55 82h R/W LED Behavior 2 Controls the behavior and response of LEDs 5 - 6 00h Page 55 84h R/W LED Pulse 1 Period Controls the period of each breathe during a pulse 20h Page 56 85h R/W LED Pulse 2 Period Controls the period of the breathing during breathe and pulse operation 14h Page 58 86h R/W LED Breathe Period Controls the period of an LED breathe operation 5Dh Page 59 88h R/W LED Config Controls LED configuration 04h Page 59 90h R/W LED Pulse 1 Duty Cycle Determines the min and max duty cycle for the pulse operation F0h Page 60 91h R/W LED Pulse 2 Duty Cycle Determines the min and max duty cycle for breathe and pulse operation F0h Page 60 92h R/W LED Breathe Duty Cycle Determines the min and max duty cycle for the breathe operation F0h Page 60 93h R/W LED Direct Duty Cycle Determines the min and max duty cycle for Direct mode LED operation F0h Page 60 94h R/W LED Direct Ramp Rates Determines the rising and falling edge ramp rates of the LEDs 00h Page 61 95h R/W LED Off Delay Determines the off delay for all LED behaviors 00h Page 61 B1h R Sensor Input 1 Calibration Stores the upper 8-bit calibration value for sensor input 1 00h Page 64 B2h R Sensor Input 2 Calibration Stores the upper 8-bit calibration value for sensor input 2 00h Page 64 B3h R Sensor Input 3 Calibration Stores the upper 8-bit calibration value for sensor input 3 00h Page 64 B4h R Sensor Input 4 Calibration Stores the upper 8-bit calibration value for sensor input 4 00h Page 64 B5h R Sensor Input 5 Calibration Stores the upper 8-bit calibration value for sensor input 5 00h Page 64 B6h R Sensor Input 6 Calibration Stores the upper 8-bit calibration value for sensor input 6 00h Page 64 B9h R Sensor Input Calibration LSB 1 Stores the 2 LSBs of the calibration value for sensor inputs 1 - 4 00h Page 64 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page CAP1166 DS00001621B-page 33  2015 Microchip Technology Inc. During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. When a bit is “set”, this means that the user writes a logic ‘1’ to it. When a bit is “cleared”, this means that the user writes a logic ‘0’ to it. 6.1 Main Control Register The Main Control register controls the primary power state of the device. Bits 7 - 6 - GAIN[1:0] - Controls the gain used by the capacitive touch sensing circuitry. As the gain is increased, the effective sensitivity is likewise increased as a smaller delta capacitance is required to generate the same delta count values. The sensitivity settings may need to be adjusted along with the gain settings such that data overflow does not occur. APPLICATION NOTE: The gain settings apply to both Standby and Active states. Bit 5 - STBY - Enables Standby. • ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - Capacitive touch sensor input scanning is limited to the sensor inputs set in the Standby Channel register (see Section 6.20). The status registers will not be cleared until read. LEDs that are linked to capacitive touch sensor inputs will remain linked and active. Sensor inputs that are no longer sampled will flag a release and then remain in a non-touched state. LEDs that are manually controlled will be unaffected. • Bit 4 - DSLEEP - Enables Deep Sleep by deactivating all functions. This bit will be cleared when the WAKE pin is driven high. ‘0’ (default) - Sensor input scanning is active and LEDs are functional. • ‘1’ - All sensor input scanning is disabled. All LEDs are driven to their programmed non-actuated state and no PWM operations will be done. The status registers are automatically cleared and the INT bit is cleared. Bit 0 - INT - Indicates that there is an interrupt. When this bit is set, it asserts the ALERT# pin. If a channel detects a touch and its associated interrupt enable bit is not set to a logic ‘1’, no action is taken. BAh R Sensor Input Calibration LSB 2 Stores the 2 LSBs of the calibration value for sensor inputs 5 - 6 00h Page 64 FDh R Product ID Stores a fixed value that identifies each product 51h Page 65 FEh R Manufacturer ID Stores a fixed value that identifies Microchip 5Dh Page 65 FFh R Revision Stores a fixed value that represents the revision number 83h Page 65 TABLE 6-2: MAIN CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 00h R/W Main Control GAIN[1:0] STBY DSLEEP - - - INT 00h TABLE 6-3: GAIN BIT DECODE GAIN[1:0] Capacitive Touch Sensor Gain 1 0 0 0 1 01 2 10 4 11 8 TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Address R/W Register Name Function Default Value Page  2015 Microchip Technology Inc. DS00001621B-page 34 CAP1166 This bit is cleared by writing a logic ‘0’ to it. When this bit is cleared, the ALERT# pin will be deasserted and all status registers will be cleared if the condition has been removed. If the WAKE/SPI_MOSI pin is asserted as a result of a touch detected while in Standby, it will likewise be deasserted when this bit is cleared. Note that the WAKE / SPI_MOSI pin is not driven when communicating via the 4-wire SPI protocol. • ‘0’ - No interrupt pending. • ‘1’ - A touch has been detected on one or more channels and the interrupt has been asserted. 6.2 Status Registers All status bits are cleared when the device enters the Deep Sleep (DSLEEP = ‘1’ - see Section 6.1). 6.2.1 GENERAL STATUS - 02H Bit 4 - LED - Indicates that one or more LEDs have finished their programmed activity. This bit is set if any bit in the LED Status register is set. Bit 3 - RESET - Indicates that the device has come out of reset. This bit is set when the device exits a POR state or when the RESET pin has been deasserted and qualified via the RESET pin filter (see Section 5.2). This bit will cause the INT bit to be set and is cleared when the INT bit is cleared. Bit 2 - MULT - Indicates that the device is blocking detected touches due to the Multiple Touch detection circuitry (see Section 6.14). This bit will not cause the INT bit to be set and hence will not cause an interrupt. Bit 1 - MTP - Indicates that the device has detected a number of sensor inputs that exceed the MTP threshold either via the pattern recognition or via the number of sensor inputs (see Section 6.15). This bit will cause the INT bit to be set if the MTP_ALERT bit is also set. This bit will not be cleared until the condition that caused it to be set has been removed. Bit 0 - TOUCH - Indicates that a touch was detected. This bit is set if any bit in the Sensor Input Status register is set. 6.2.2 SENSOR INPUT STATUS - 03H The Sensor Input Status Register stores status bits that indicate a touch has been detected. A value of ‘0’ in any bit indicates that no touch has been detected. A value of ‘1’ in any bit indicates that a touch has been detected. All bits are cleared when the INT bit is cleared and if a touch on the respective capacitive touch sensor input is no longer present. If a touch is still detected, the bits will not be cleared (but this will not cause the interrupt to be asserted - see Section 6.6). Bit 5 - CS6 - Indicates that a touch was detected on Sensor Input 6. This sensor input can be linked to LED6. Bit 4 - CS5 - Indicates that a touch was detected on Sensor Input 5. This sensor input can be linked to LED5. Bit 3 - CS4 - Indicates that a touch was detected on Sensor Input 4. This sensor input can be linked to LED4. Bit 2 - CS3 - Indicates that a touch was detected on Sensor Input 3. This sensor input can be linked to LED3. Bit 1 - CS2 - Indicates that a touch was detected on Sensor Input 2. This sensor input can be linked to LED2. Bit 0 - CS1 - Indicates that a touch was detected on Sensor Input 1. This sensor input can be linked to LED1. 6.2.3 LED STATUS - 04H The LED Status Registers indicate when an LED has completed its configured behavior (see Section 6.31, "LED Behavior Registers") after being actuated by the host (see Section 6.28, "LED Output Control Register"). These bits are ignored when the LED is linked to a capacitive sensor input. All LED Status bits are cleared when the INT bit is cleared. Bit 5 - LED6_DN - Indicates that LED6 has finished its behavior after being actuated by the host. Bit 4 - LED5_DN - Indicates that LED5 has finished its behavior after being actuated by the host. TABLE 6-4: STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 02h R General Status - - - LED RESET MULT MTP TOUCH 00h 03h R Sensor Input Status - - CS6 CS5 CS4 CS3 CS2 CS1 00h 04h R LED Status - - LED6_ DN LED5_ DN LED4_ DN LED3_ DN LED2_ DN LED1_ DN 00h CAP1166 DS00001621B-page 35  2015 Microchip Technology Inc. Bit 3 - LED4_DN - Indicates that LED4 has finished its behavior after being actuated by the host. Bit 2 - LED3_DN - Indicates that LED3 has finished its behavior after being actuated by the host. Bit 1 - LED2_DN - Indicates that LED2 has finished its behavior after being actuated by the host. Bit 0 - LED1_DN - Indicates that LED1 has finished its behavior after being actuated by the host. 6.3 Noise Flag Status Registers The Noise Flag Status registers store status bits that are generated from the analog block if the detected noise is above the operating region of the analog detector or the RF noise detector. These bits indicate that the most recently received data from the sensor input is invalid and should not be used for touch detection. So long as the bit is set for a particular channel, the delta count value is reset to 00h and thus no touch is detected. These bits are not sticky and will be cleared automatically if the analog block does not report a noise error. APPLICATION NOTE: If the MTP detection circuitry is enabled, these bits count as sensor inputs above the MTP threshold (see Section 5.5.4, "Multiple Touch Pattern Detection") even if the corresponding delta count is not. If the corresponding delta count also exceeds the MTP threshold, it is not counted twice. APPLICATION NOTE: Regardless of the state of the Noise Status bits, if low frequency noise is detected on a sensor input, that sample will be discarded unless the DIS_ANA_NOISE bit is set. As well, if RF noise is detected on a sensor input, that sample will be discarded unless the DIS_RF_NOISE bit is set. 6.4 Sensor Input Delta Count Registers The Sensor Input Delta Count registers store the delta count that is compared against the threshold used to determine if a touch has been detected. The count value represents a change in input due to the capacitance associated with a touch on one of the sensor inputs and is referenced to a calibrated base “Not Touched” count value. The delta is an instantaneous change and is updated once per sensor input per sensing cycle (see Section 5.5.1, "Sensing Cycle"). The value presented is a standard 2’s complement number. In addition, the value is capped at a value of 7Fh. A reading of 7Fh indicates that the sensitivity settings are too high and should be adjusted accordingly (see Section 6.5). The value is also capped at a negative value of 80h for negative delta counts which may result upon a release. TABLE 6-5: NOISE FLAG STATUS REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 0Ah R Noise Flag Status - - CS6_ NOISE CS5_ NOISE CS4_ NOISE CS3_ NOISE CS2_ NOISE CS1_ NOISE 00h TABLE 6-6: SENSOR INPUT DELTA COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 10h R Sensor Input 1 Delta Count Sign 64 32 16 8 4 2 1 00h 11h R Sensor Input 2 Delta Count Sign 64 32 16 8 4 2 1 00h 12h R Sensor Input 3 Delta Count Sign 64 32 16 8 4 2 1 00h 13h R Sensor Input 4 Delta Count Sign 64 32 16 8 4 2 1 00h 14h R Sensor Input 5 Delta Count Sign 64 32 16 8 4 2 1 00h 15h R Sensor Input 6 Delta Count Sign 64 32 16 8 4 2 1 00h  2015 Microchip Technology Inc. DS00001621B-page 36 CAP1166 6.5 Sensitivity Control Register The Sensitivity Control register controls the sensitivity of a touch detection. Bits 6-4 DELTA_SENSE[2:0] - Controls the sensitivity of a touch detection. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta capacitance corresponding to a “lighter” touch. These settings are more sensitive to noise, however, and a noisy environment may flag more false touches with higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely, a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). Bits 3 - 0 - BASE_SHIFT[3:0] - Controls the scaling and data presentation of the Base Count registers. The higher the value of these bits, the larger the range and the lower the resolution of the data presented. The scale factor represents the multiplier to the bit-weighting presented in these register descriptions. APPLICATION NOTE: The BASE_SHIFT[3:0] bits normally do not need to be updated. These settings will not affect touch detection or sensitivity. These bits are sometimes helpful in analyzing the Cap Sensing board performance and stability. TABLE 6-7: SENSITIVITY CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 1Fh R/W Sensitivity Control - DELTA_SENSE[2:0] BASE_SHIFT[3:0] 2Fh TABLE 6-8: DELTA_SENSE BIT DECODE DELTA_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-9: BASE_SHIFT BIT DECODE BASE_SHIFT[3:0] Data Scaling Factor 32 1 0 0 0 0 0 1x 0 0 0 1 2x 0 0 1 0 4x 0 0 1 1 8x 0 1 0 0 16x 0 1 0 1 32x 0 1 1 0 64x CAP1166 DS00001621B-page 37  2015 Microchip Technology Inc. 6.6 Configuration Registers The Configuration registers control general global functionality that affects the entire device. 6.6.1 CONFIGURATION - 20H Bit 7 - TIMEOUT - Enables the timeout and idle functionality of the SMBus protocol. • ‘0’ (default for Functional Revision C) - The SMBus timeout and idle functionality are disabled. The SMBus interface will not time out if the clock line is held low. Likewise, it will not reset if both the data and clock lines are held high for longer than 200us. This is used for I2C compliance. • ‘1’ (default for Functional Revision B) - The SMBus timeout and idle functionality are enabled. The SMBus interface will time out if the clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock lines are held high for longer than 200us. Bit 6 - WAKE_CFG - Configures the operation of the WAKE pin. • ‘0’ (default) - The WAKE pin is not asserted when a touch is detected while the device is in Standby. It will still be used to wake the device from Deep Sleep when driven high. • ‘1’ - The WAKE pin will be asserted high when a touch is detected while the device is in Standby. It will also be used to wake the device from Deep Sleep when driven high. Bit 5 - DIS_DIG_NOISE - Determines whether the digital noise threshold (see Section 6.19, "Sensor Input Noise Threshold Register") is used by the device. Setting this bit disables the feature. • ‘0’ - The digital noise threshold is used. If a delta count value exceeds the noise threshold but does not exceed the touch threshold, the sample is discarded and not used for the automatic re-calibration routine. • ‘1’ (default) - The noise threshold is disabled. Any delta count that is less than the touch threshold is used for the automatic re-calibration routine. Bit 4 - DIS_ANA_NOISE - Determines whether the analog noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If low frequency noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if low frequency noise is detected. Bit 3 - MAX_DUR_EN - Determines whether the maximum duration recalibration is enabled. • ‘0’ (default) - The maximum duration recalibration functionality is disabled. A touch may be held indefinitely and no re-calibration will be performed on any sensor input. • ‘1’ - The maximum duration recalibration functionality is enabled. If a touch is held for longer than the MAX_DUR bit settings, then the re-calibration routine will be restarted (see Section 6.8). 0 1 1 1 128x 1 0 0 0 256x All others 256x (default = 1111b) TABLE 6-10: CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 20h R/W Configuration TIMEOUT WAKE_ CFG DIS_ DIG_ NOISE DIS_ ANA_ NOISE MAX_ DUR_EN - -- A0h (Rev B) 20h (rev C) 44h R/W Configuration 2 INV_LINK_ TRAN ALT_ POL BLK_PWR_ CTRL BLK_POL_ MIR SHOW_ RF_ NOISE DIS_ RF_ NOISE - INT_ REL_n 40h TABLE 6-9: BASE_SHIFT BIT DECODE (CONTINUED) BASE_SHIFT[3:0] Data Scaling Factor 32 1 0  2015 Microchip Technology Inc. DS00001621B-page 38 CAP1166 6.6.2 CONFIGURATION 2 - 44H Bit 7 - INV_LINK_TRAN - Determines the behavior of the Linked LED Transition controls (see Section 6.29). • ‘0’ (default) - The Linked LED Transition controls set the min duty cycle equal to the max duty cycle. • ‘1’ - The Linked LED Transition controls will invert the touch signal. For example, a touch signal will be inverted to a non-touched signal. Bit 6 - ALT_POL - Determines the ALERT# pin polarity and behavior. • ‘0’ - The ALERT# pin is active high and push-pull. • ‘1’ (default) - The ALERT# pin is active low and open drain. Bit 5 - BLK_PWR_CTRL - Determines whether the device will reduce power consumption while waiting between conversion time completion and the end of the polling cycle. • ‘0’ (default) - The device will always power down as much as possible during the time between the end of the last conversion and the end of the polling cycle. • ‘1’ - The device will not power down the Cap Sensor during the time between the end of the last conversion and the end of the polling cycle. Bit 4 - BLK_POL_MIR - Determines whether the LED Mirror Control register bits are linked to the LED Polarity bits. Setting this bit blocks the normal behavior which is to automatically set and clear the LED Mirror Control bits when the LED Polarity bits are set or cleared. • ‘0’ (default) - When the LED Polarity controls are set, the corresponding LED Mirror control is automatically set. Likewise, when the LED Polarity controls are cleared, the corresponding LED Mirror control is also cleared. • ‘1’ - When the LED Polarity controls are set, the corresponding LED Mirror control is not automatically set. Bit 3 - SHOW_RF_NOISE - Determines whether the Noise Status bits will show RF Noise as the only input source. • ‘0’ (default) - The Noise Status registers will show both RF noise and low frequency EMI noise if either is detected on a capacitive touch sensor input. • ‘1’ - The Noise Status registers will only show RF noise if it is detected on a capacitive touch sensor input. EMI noise will still be detected and touches will be blocked normally; however, the status bits will not be updated. Bit 2 - DIS_RF_NOISE - Determines whether the RF noise filter is enabled. Setting this bit disables the feature. • ‘0’ (default) - If RF noise is detected by the analog block, the delta count on the corresponding channel is set to 0. Note that this does not require that Noise Status bits be set. • ‘1’ - A touch is not blocked even if RF noise is detected. Bit 0 - INT_REL_n - Controls the interrupt behavior when a release is detected on a button. • ‘0’ (default) - An interrupt is generated when a press is detected and again when a release is detected and at the repeat rate (if enabled - see Section 6.13). • ‘1’ - An interrupt is generated when a press is detected and at the repeat rate but not when a release is detected. 6.7 Sensor Input Enable Registers The Sensor Input Enable registers determine whether a capacitive touch sensor input is included in the sampling cycle. The length of the sampling cycle is not affected by the number of sensor inputs measured. Bit 5 - CS6_EN - Enables the CS6 input to be included during the sampling cycle. • ‘0’ - The CS6 input is not included in the sampling cycle. • ‘1’ (default) - The CS6 input is included in the sampling cycle. Bit 4 - CS5_EN - Enables the CS5 input to be included during the sampling cycle. Bit 3 - CS4_EN - Enables the CS4 input to be included during the sampling cycle. Bit 2 - CS3_EN - Enables the CS3 input to be included during the sampling cycle. TABLE 6-11: SENSOR INPUT ENABLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 21h R/W Sensor Input Enable - - CS6_EN CS5_EN CS4_EN CS3_EN CS2_EN CS1_EN 3Fh CAP1166 DS00001621B-page 39  2015 Microchip Technology Inc. Bit 1 - CS2_EN - Enables the CS2 input to be included during the sampling cycle. Bit 0 - CS1_EN - Enables the CS1 input to be included during the sampling cycle. 6.8 Sensor Input Configuration Register The Sensor Input Configuration Register controls timings associated with the Capacitive sensor inputs 1 - 6. Bits 7 - 4 - MAX_DUR[3:0] - (default 1010b) - Determines the maximum time that a sensor pad is allowed to be touched until the capacitive touch sensor input is recalibrated, as shown in Table 6-13. Bits 3 - 0 - RPT_RATE[3:0] - (default 0100b) Determines the time duration between interrupt assertions when auto repeat is enabled. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-14. TABLE 6-12: SENSOR INPUT CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 22h R/W Sensor Input Configuration MAX_DUR[3:0] RPT_RATE[3:0] A4h TABLE 6-13: MAX_DUR BIT DECODE MAX_DUR[3:0] Time Before Recalibration 32 1 0 0 0 0 0 560ms 0 0 0 1 840ms 0 0 1 0 1120ms 0 0 1 1 1400ms 0 1 0 0 1680ms 0 1 0 1 2240ms 0 1 1 0 2800ms 1 1 1 3360ms 1 0 0 0 3920ms 1 0 0 1 4480ms 1 0 1 0 5600ms (default) 1 0 1 1 6720ms 1 1 0 0 7840ms 1 1 0 1 8906ms 1 1 1 0 10080ms 1 1 1 1 11200ms TABLE 6-14: RPT_RATE BIT DECODE RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms (default) 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms  2015 Microchip Technology Inc. DS00001621B-page 40 CAP1166 6.9 Sensor Input Configuration 2 Register Bits 3 - 0 - M_PRESS[3:0] - (default 0111b) - Determines the minimum amount of time that sensor inputs configured to use auto repeat must detect a sensor pad touch to detect a “press and hold” event. If the sensor input detects a touch for longer than the M_PRESS[3:0] settings, a “press and hold” event is detected. If a sensor input detects a touch for less than or equal to the M_PRESS[3:0] settings, a touch event is detected. The resolution is 35ms the range is from 35ms to 560ms as shown in Table 6-16. 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-15: SENSOR INPUT CONFIGURATION 2 REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 23h R/W Sensor Input Configuration 2 - - - - M_PRESS[3:0] 07h TABLE 6-16: M_PRESS BIT DECODE M_PRESS[3:0] M_PRESS SETTINGS 3 21 0 0 0 0 0 35ms 0 0 0 1 70ms 0 0 1 0 105ms 0 0 1 1 140ms 0 1 0 0 175ms 0 1 0 1 210ms 0 1 1 0 245ms 0 1 1 1 280ms (default) 1 0 0 0 315ms 1 0 0 1 350ms 1 0 1 0 385ms 1 0 1 1 420ms 1 1 0 0 455ms 1 1 0 1 490ms 1 1 1 0 525ms 1 1 1 1 560ms TABLE 6-14: RPT_RATE BIT DECODE (CONTINUED) RPT_RATE[3:0] Interrupt Repeat RATE 3 21 0 CAP1166 DS00001621B-page 41  2015 Microchip Technology Inc. 6.10 Averaging and Sampling Configuration Register The Averaging and Sampling Configuration register controls the number of samples taken and the total sensor input cycle time for all active sensor inputs while the device is functioning in Active state. Bits 6 - 4 - AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-18. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. For example, if CS1, CS2, and CS3 are sampled during the sensor cycle, and the AVG[2:0] bits are set to take 4 samples per channel, then the full sensor cycle will be: CS1, CS1, CS1, CS1, CS2, CS2, CS2, CS2, CS3, CS3, CS3, CS3. Bits 3 - 2 - SAMP_TIME[1:0] - Determines the time to take a single sample as shown in Table 6-19. Bits 1 - 0 - CYCLE_TIME[1:0] - Determines the overall cycle time for all measured channels during normal operation as shown in Table 6-20. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, then the device is placed into a lower power state for the remaining duration of the cycle. TABLE 6-17: AVERAGING AND SAMPLING CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 24h R/W Averaging and Sampling Config AVG[2:0] SAMP_TIME[1:0] CYCLE_TIME [1:0] 39h TABLE 6-18: AVG BIT DECODE AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 TABLE 6-19: SAMP_TIME BIT DECODE SAMP_TIME[1:0] Sample Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-20: CYCLE_TIME BIT DECODE CYCLE_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms  2015 Microchip Technology Inc. DS00001621B-page 42 CAP1166 APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.11 Calibration Activate Register The Calibration Activate register forces the respective sensor inputs to be re-calibrated affecting both the analog and digital blocks. During the re-calibration routine, the sensor inputs will not detect a press for up to 600ms and the Sensor Input Base Count register values will be invalid. During this time, any press on the corresponding sensor pads will invalidate the re-calibration. When finished, the CALX[9:0] bits will be updated (see Section 6.39). When the corresponding bit is set, the device will perform the calibration and the bit will be automatically cleared once the re-calibration routine has finished. Bit 5 - CS6_CAL - When set, the CS6 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 4 - CS5_CAL - When set, the CS5 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 3 - CS4_CAL - When set, the CS4 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 2 - CS3_CAL - When set, the CS3 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 1 - CS2_CAL - When set, the CS2 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. Bit 0 - CS1_CAL - When set, the CS1 input is re-calibrated. This bit is automatically cleared once the sensor input has been re-calibrated successfully. 6.12 Interrupt Enable Register The Interrupt Enable register determines whether a sensor pad touch or release (if enabled) causes the interrupt pin to be asserted. Bit 5 - CS6_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS6 (associated with the CS6 status bit). • ‘0’ - The interrupt pin will not be asserted if a touch is detected on CS6 (associated with the CS6 status bit). • ‘1’ (default) - The interrupt pin will be asserted if a touch is detected on CS6 (associated with the CS6 status bit). Bit 4 - CS5_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS5 (associated with the CS5 status bit). Bit 3 - CS4_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS4 (associated with the CS4 status bit). Bit 2 - CS3_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS3 (associated with the CS3 status bit). Bit 1 - CS2_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS2 (associated with the CS2 status bit). TABLE 6-21: CALIBRATION ACTIVATE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 26h R/W Calibration Activate - - CS6_ CAL CS5_ CAL CS4_ CAL CS3_ CAL CS2_ CAL CS1_ CAL 00h TABLE 6-22: INTERRUPT ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 27h R/W Interrupt Enable - - CS6_ INT_EN CS5_ INT_EN CS4_ INT_EN CS3_ INT_EN CS2_ INT_EN CS1_ INT_EN 3Fh CAP1166 DS00001621B-page 43  2015 Microchip Technology Inc. Bit 0 - CS1_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS1 (associated with the CS1 status bit). 6.13 Repeat Rate Enable Register The Repeat Rate Enable register enables the repeat rate of the sensor inputs as described in Section 5.6.1. Bit 5 - CS6_RPT_EN - Enables the repeat rate for capacitive touch sensor input 6. • ‘0’ - The repeat rate for CS6 is disabled. It will only generate an interrupt when a touch is detected and when a release is detected no matter how long the touch is held for. • ‘1’ (default) - The repeat rate for CS6 is enabled. In the case of a “touch” event, it will generate an interrupt when a touch is detected and a release is detected (as determined by the INT_REL_n bit - see Section 6.6). In the case of a “press and hold” event, it will generate an interrupt when a touch is detected and at the repeat rate so long as the touch is held. Bit 4 - CS5_RPT_EN - Enables the repeat rate for capacitive touch sensor input 5. Bit 3 - CS4_RPT_EN - Enables the repeat rate for capacitive touch sensor input 4. Bit 2 - CS3_RPT_EN - Enables the repeat rate for capacitive touch sensor input 3. Bit 1 - CS2_RPT_EN - Enables the repeat rate for capacitive touch sensor input 2. Bit 0 - CS1_RPT_EN - Enables the repeat rate for capacitive touch sensor input 1. 6.14 Multiple Touch Configuration Register The Multiple Touch Configuration register controls the settings for the multiple touch detection circuitry. These settings determine the number of simultaneous buttons that may be pressed before additional buttons are blocked and the MULT status bit is set. Bit 7 - MULT_BLK_EN - Enables the multiple button blocking circuitry. • ‘0’ - The multiple touch circuitry is disabled. The device will not block multiple touches. • ‘1’ (default) - The multiple touch circuitry is enabled. The device will flag the number of touches equal to programmed multiple touch threshold and block all others. It will remember which sensor inputs are valid and block all others until that sensor pad has been released. Once a sensor pad has been released, the N detected touches (determined via the cycle order of CS1 - CS6) will be flagged and all others blocked. Bits 3 - 2 - B_MULT_T[1:0] - Determines the number of simultaneous touches on all sensor pads before a Multiple Touch Event is detected and sensor inputs are blocked. The bit decode is given by Table 6-25. TABLE 6-23: REPEAT RATE ENABLE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 28h R/W Repeat Rate Enable - - CS6_ RPT_EN CS5_ RPT_EN CS4_ RPT_EN CS3_ RPT_EN CS2_ RPT_EN CS1_ RPT_EN 3Fh TABLE 6-24: MULTIPLE TOUCH CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Ah R/W Multiple Touch Config MULT_ BLK_ EN - - - B_MULT_T[1:0] - - 80h TABLE 6-25: B_MULT_T BIT DECODE B_MULT_T[1:0] Number of Simultaneous Touches 1 0 0 0 1 (default) 01 2 10 3 11 4  2015 Microchip Technology Inc. DS00001621B-page 44 CAP1166 6.15 Multiple Touch Pattern Configuration Register The Multiple Touch Pattern Configuration register controls the settings for the multiple touch pattern detection circuitry. This circuitry works like the multiple touch detection circuitry with the following differences: 1. The detection threshold is a percentage of the touch detection threshold as defined by the MTP_TH[1:0] bits whereas the multiple touch circuitry uses the touch detection threshold. 2. The MTP detection circuitry either will detect a specific pattern of sensor inputs as determined by the Multiple Touch Pattern register settings or it will use the Multiple Touch Pattern register settings to determine a minimum number of sensor inputs that will cause the MTP circuitry to flag an event. When using pattern recognition mode, if all of the sensor inputs set by the Multiple Touch Pattern register have a delta count greater than the MTP threshold or have their corresponding Noise Flag Status bits set, the MTP bit will be set. When using the absolute number mode, if the number of sensor inputs with thresholds above the MTP threshold or with Noise Flag Status bits set is equal to or greater than this number, the MTP bit will be set. 3. When an MTP event occurs, all touches are blocked and an interrupt is generated. 4. All sensor inputs will remain blocked so long as the requisite number of sensor inputs are above the MTP threshold or have Noise Flag Status bits set. Once this condition is removed, touch detection will be restored. Note that the MTP status bit is only cleared by writing a ‘0’ to the INT bit once the condition has been removed. Bit 7 - MTP_EN - Enables the multiple touch pattern detection circuitry. • ‘0’ (default) - The MTP detection circuitry is disabled. • ‘1’ - The MTP detection circuitry is enabled. Bits 3-2 - MTP_TH[1:0] - Determine the MTP threshold, as shown in Table 6-27. This threshold is a percentage of sensor input threshold (see Section 6.18, "Sensor Input Threshold Registers") when the device is in the Fully Active state or of the standby threshold (see Section 6.23, "Standby Threshold Register") when the device is in the Standby state. Bit 1 - COMP_PTRN - Determines whether the MTP detection circuitry will use the Multiple Touch Pattern register as a specific pattern of sensor inputs or as an absolute number of sensor inputs. • ‘0’ (default) - The MTP detection circuitry will use the Multiple Touch Pattern register bit settings as an absolute minimum number of sensor inputs that must be above the threshold or have Noise Flag Status bits set. The number will be equal to the number of bits set in the register. • ‘1’ - The MTP detection circuitry will use pattern recognition. Each bit set in the Multiple Touch Pattern register indicates a specific sensor input that must have a delta count greater than the MTP threshold or have a Noise Flag Status bit set. If the criteria are met, the MTP status bit will be set. Bit 0 - MTP_ALERT - Enables an interrupt if an MTP event occurs. In either condition, the MTP status bit will be set. • ‘0’ (default) - If an MTP event occurs, the ALERT# pin is not asserted. • ‘1’ - If an MTP event occurs, the ALERT# pin will be asserted. TABLE 6-26: MULTIPLE TOUCH PATTERN CONFIGURATION ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Bh R/W Multiple Touch Pattern Config MTP_ EN - - MTP_TH[1:0] COMP_ PTRN MTP_ ALERT 00h TABLE 6-27: MTP_TH BIT DECODE MTP_TH[1:0] Threshold Divide Setting 1 0 0 0 12.5% (default) 0 1 25% 1 0 37.5% 1 1 100% CAP1166 DS00001621B-page 45  2015 Microchip Technology Inc. 6.16 Multiple Touch Pattern Register The Multiple Touch Pattern register acts as a pattern to identify an expected sensor input profile for diagnostics or other significant events. There are two methods for how the Multiple Touch Pattern register is used: as specific sensor inputs or number of sensor input that must exceed the MTP threshold or have Noise Flag Status bits set. Which method is used is based on the COMP_PTRN bit (see Section 6.15). The methods are described below. 1. Specific Sensor Inputs: If, during a single polling cycle, the specific sensor inputs above the MTP threshold or with Noise Flag Status bits set match those bits set in the Multiple Touch Pattern register, an MTP event is flagged. 2. Number of Sensor Inputs: If, during a single polling cycle, the number of sensor inputs with a delta count above the MTP threshold or with Noise Flag Status bits set is equal to or greater than the number of pattern bits set, an MTP event is flagged. Bit 5 - CS6_PTRN - Determines whether CS6 is considered as part of the Multiple Touch Pattern. • ‘0’ - CS6 is not considered a part of the pattern. • ‘1’ - CS6 is considered a part of the pattern or the absolute number of sensor inputs that must have a delta count greater than the MTP threshold or have the Noise Flag Status bit set is increased by 1. Bit 4 - CS5_PTRN - Determines whether CS5 is considered as part of the Multiple Touch Pattern. Bit 3 - CS4_PTRN - Determines whether CS4 is considered as part of the Multiple Touch Pattern. Bit 2 - CS3_PTRN - Determines whether CS3 is considered as part of the Multiple Touch Pattern. Bit 1 - CS2_PTRN - Determines whether CS2 is considered as part of the Multiple Touch Pattern. Bit 0 - CS1_PTRN - Determines whether CS1 is considered as part of the Multiple Touch Pattern. 6.17 Recalibration Configuration Register The Recalibration Configuration register controls the automatic re-calibration routine settings as well as advanced controls to program the Sensor Input Threshold register settings. Bit 7 - BUT_LD_TH - Enables setting all Sensor Input Threshold registers by writing to the Sensor Input 1 Threshold register. • ‘0’ - Each Sensor Input X Threshold register is updated individually. • ‘1’ (default) - Writing the Sensor Input 1 Threshold register will automatically overwrite the Sensor Input Threshold registers for all sensor inputs (Sensor Input Threshold 1 through Sensor Input Threshold 6). The individual Sensor Input X Threshold registers (Sensor Input 2 Threshold through Sensor Input 6 Threshold) can be individually updated at any time. Bit 6 - NO_CLR_INTD - Controls whether the accumulation of intermediate data is cleared if the noise status bit is set. • ‘0’ (default) - The accumulation of intermediate data is cleared if the noise status bit is set. • ‘1’ - The accumulation of intermediate data is not cleared if the noise status bit is set. APPLICATION NOTE: Bits 5 and 6 should both be set to the same value. Either both should be set to ‘0’ or both should be set to ‘1’. Bit 5 - NO_CLR_NEG - Controls whether the consecutive negative delta counts counter is cleared if the noise status bit is set. TABLE 6-28: MULTIPLE TOUCH PATTERN REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Dh R/W Multiple Touch Pattern - - CS6_ PTRN CS5_ PTRN CS4_ PTRN CS3_ PTRN CS2_ PTRN CS1_ PTRN 3Fh TABLE 6-29: RECALIBRATION CONFIGURATION REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 2Fh R/W Recalibration Configuration BUT_ LD_TH NO_ CLR_ INTD NO_ CLR_ NEG NEG_DELTA_ CNT[1:0] CAL_CFG[2:0] 8Ah  2015 Microchip Technology Inc. DS00001621B-page 46 CAP1166 • ‘0’ (default) - The consecutive negative delta counts counter is cleared if the noise status bit is set. • ‘1’ - The consecutive negative delta counts counter is not cleared if the noise status bit is set. Bits 4 - 3 - NEG_DELTA_CNT[1:0] - Determines the number of negative delta counts necessary to trigger a digital recalibration as shown in Table 6-30. Bits 2 - 0 - CAL_CFG[2:0] - Determines the update time and number of samples of the automatic re-calibration routine. The settings apply to all sensor inputs universally (though individual sensor inputs can be configured to support re-calibration - see Section 6.11). Note 6-1 Recalibration Samples refers to the number of samples that are measured and averaged before the Base Count is updated however does not control the base count update period. Note 6-2 Update Time refers to the amount of time (in polling cycle periods) that elapses before the Base Count is updated. The time will depend upon the number of channels active, the averaging setting, and the programmed cycle time. TABLE 6-30: NEG_DELTA_CNT BIT DECODE NEG_DELTA_CNT[1:0] Number of Consecutive Negative Delta Count Values 1 0 00 8 0 1 16 (default) 1 0 32 1 1 None (disabled) TABLE 6-31: CAL_CFG BIT DECODE CAL_CFG[2:0] Recalibration Samples (see Note 6-1) Update Time (see Note 6-2) 210 0 0 0 16 16 0 0 1 32 32 0 1 0 64 64 (default) 0 1 1 128 128 1 0 0 256 256 1 0 1 256 1024 1 1 0 256 2048 1 1 1 256 4096 CAP1166 DS00001621B-page 47  2015 Microchip Technology Inc. 6.18 Sensor Input Threshold Registers The Sensor Input Threshold registers store the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. When the BUT_LD_TH bit is set (see Section 6.17 - bit 7), writing data to the Sensor Input 1 Threshold register will update all of the sensor input threshold registers (31h - 35h inclusive). 6.19 Sensor Input Noise Threshold Register The Sensor Input Noise Threshold register controls the value of a secondary internal threshold to detect noise and improve the automatic recalibration routine. If a capacitive touch sensor input exceeds the Sensor Input Noise Threshold but does not exceed the sensor input threshold, it is determined to be caused by a noise spike. That sample is not used by the automatic re-calibration routine. This feature can be disabled by setting the DIS_DIG_NOISE bit. Bits 1-0 - CS1_BN_TH[1:0] - Controls the noise threshold for all capacitive touch sensor inputs, as shown in Table 6-34. The threshold is proportional to the threshold setting. 6.20 Standby Channel Register TABLE 6-32: SENSOR INPUT THRESHOLD REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 30h R/W Sensor Input 1 Threshold - 64 32 16 8 4 2 1 40h 31h R/W Sensor Input 2 Threshold - 64 32 16 8 4 2 1 40h 32h R/W Sensor Input 3 Threshold - 64 32 16 8 4 2 1 40h 33h R/W Sensor Input 4 Threshold - 64 32 16 8 4 2 1 40h 34h R/W Sensor Input 5 Threshold - 64 32 16 8 4 2 1 40h 35h R/W Sensor Input 6 Threshold - 64 32 16 8 4 2 1 40h TABLE 6-33: SENSOR INPUT NOISE THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 38h R/W Sensor Input Noise Threshold CS_BN_TH [1:0] 01h TABLE 6-34: CSX_BN_TH BIT DECODE CS_BN_TH[1:0] Percent Threshold Setting 1 0 0 0 25% 0 1 37.5% (default) 1 0 50% 1 1 62.5% TABLE 6-35: STANDBY CHANNEL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 40h R/W Standby Channel - - CS6_ STBY CS5_ STBY CS4_ STBY CS3_ STBY CS2_ STBY CS1_ STBY 00h  2015 Microchip Technology Inc. DS00001621B-page 48 CAP1166 The Standby Channel register controls which (if any) capacitive touch sensor inputs are active during Standby. Bit 5 - CS6_STBY - Controls whether the CS6 channel is active in Standby. • ‘0’ (default) - The CS6 channel not be sampled during Standby mode. • ‘1’ - The CS6 channel will be sampled during Standby Mode. It will use the Standby threshold setting, and the standby averaging and sensitivity settings. Bit 4 - CS5_STBY - Controls whether the CS5 channel is active in Standby. Bit 3 - CS4_STBY - Controls whether the CS4 channel is active in Standby. Bit 2 - CS3_STBY - Controls whether the CS3 channel is active in Standby. Bit 1 - CS2_STBY - Controls whether the CS2 channel is active in Standby. Bit 0 - CS1_STBY - Controls whether the CS1 channel is active in Standby. 6.21 Standby Configuration Register The Standby Configuration register controls averaging and cycle time for those sensor inputs that are active in Standby. This register is useful for detecting proximity on a small number of sensor inputs as it allows the user to change averaging and sample times on a limited number of sensor inputs and still maintain normal functionality in the fully active state. Bit 7 - AVG_SUM - Determines whether the active sensor inputs will average the programmed number of samples or whether they will accumulate for the programmed number of samples. • ‘0’ - (default) - The active sensor input delta count values will be based on the average of the programmed number of samples when compared against the threshold. • ‘1’ - The active sensor input delta count values will be based on the summation of the programmed number of samples when compared against the threshold. This bit should only be set when performing proximity detection as a physical touch will overflow the delta count registers and may result in false readings. Bits 6 - 4 - STBY_AVG[2:0] - Determines the number of samples that are taken for all active channels during the sensor cycle as shown in Table 6-37. All samples are taken consecutively on the same channel before the next channel is sampled and the result is averaged over the number of samples measured before updating the measured results. Bit 3-2 - STBY SAMP_TIME[1:0] - Determines the time to take a single sample when the device is in Standby as shown in Table 6-38. TABLE 6-36: STANDBY CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 41h R/W Standby Configuration AVG_ SUM STBY_AVG[2:0] STBY_SAMP_ TIME[1:0] STBY_CY_TIME [1:0] 39h TABLE 6-37: STBY_AVG BIT DECODE STBY_AVG[2:0] Number of Samples Taken per Measurement 2 10 0 0 0 1 0 01 2 0 10 4 0 1 1 8 (default) 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 CAP1166 DS00001621B-page 49  2015 Microchip Technology Inc. Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during standby operation as shown in Table 6-39. All measured channels are sampled at the beginning of the cycle time. If additional time is remaining, the device is placed into a lower power state for the remaining duration of the cycle. APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more samples are required than would normally be allowed during the cycle time, the cycle time will be extended as necessary to accommodate the number of samples to be measured. 6.22 Standby Sensitivity Register The Standby Sensitivity register controls the sensitivity for sensor inputs that are active in Standby. Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensor inputs that are active in Standby. The sensitivity settings act to scale the relative delta count value higher or lower based on the system parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more sensitive to noise however and a noisy environment may flag more false touches than higher sensitivity levels. APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base capacitance). Conversely a value of 1x is the least sensitive setting available. At these settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance (or a ΔC of 3.33pF from a 10pF base capacitance). TABLE 6-38: STBY_SAMP_TIME BIT DECODE STBY_SAMP_TIME[1:0] Sampling Time 1 0 0 0 320us 0 1 640us 1 0 1.28ms (default) 1 1 2.56ms TABLE 6-39: STBY_CY_TIME BIT DECODE STBY_CY_TIME[1:0] Overall Cycle Time 1 0 0 0 35ms 0 1 70ms (default) 1 0 105ms 1 1 140ms TABLE 6-40: STANDBY SENSITIVITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 42h R/W Standby Sensitivity - - - - - STBY_SENSE[2:0] 02h TABLE 6-41: STBY_SENSE BIT DECODE STBY_SENSE[2:0] Sensitivity Multiplier 210 0 0 0 128x (most sensitive) 0 0 1 64x  2015 Microchip Technology Inc. DS00001621B-page 50 CAP1166 6.23 Standby Threshold Register The Standby Threshold register stores the delta threshold that is used to determine if a touch has been detected. When a touch occurs, the input signal of the corresponding sensor pad changes due to the capacitance associated with a touch. If the sensor input change exceeds the threshold settings, a touch is detected. 6.24 Sensor Input Base Count Registers The Sensor Input Base Count registers store the calibrated “Not Touched” input value from the capacitive touch sensor inputs. These registers are periodically updated by the re-calibration routine. The routine uses an internal adder to add the current count value for each reading to the sum of the previous readings until sample size has been reached. At this point, the upper 16 bits are taken and used as the Sensor Input Base Count. The internal adder is then reset and the re-calibration routine continues. The data presented is determined by the BASE_SHIFT[3:0] bits (see Section 6.5). 6.25 LED Output Type Register 0 1 0 32x (default) 0 1 1 16x 1 0 0 8x 1 0 1 4x 1 1 0 2x 1 1 1 1x - (least sensitive) TABLE 6-42: STANDBY THRESHOLD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 43h R/W Standby Threshold - 64 32 16 8 4 2 1 40h TABLE 6-43: SENSOR INPUT BASE COUNT REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 50h R Sensor Input 1 Base Count 128 64 32 16 8 4 2 1 C8h 51h R Sensor Input 2 Base Count 128 64 32 16 8 4 2 1 C8h 52h R Sensor Input 3 Base Count 128 64 32 16 8 4 2 1 C8h 53h R Sensor Input 4 Base Count 128 64 32 16 8 4 2 1 C8h 54h R Sensor Input 5 Base Count 128 64 32 16 8 4 2 1 C8h 55h R Sensor Input 6 Base Count 128 64 32 16 8 4 2 1 C8h TABLE 6-44: LED OUTPUT TYPE REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 71h R/W LED Output Type - - LED6_ OT LED5_ OT LED4_ OT LED3_ OT LED2_ OT LED1_ OT 00h TABLE 6-41: STBY_SENSE BIT DECODE (CONTINUED) STBY_SENSE[2:0] Sensitivity Multiplier 210 CAP1166 DS00001621B-page 51  2015 Microchip Technology Inc. The LED Output Type register controls the type of output for the LED pins. Each pin is controlled by a single bit. Refer to application note 21.4 CAP1166Family LED Configuration Options for more information about implementing LEDs. Bit 5 - LED6_OT - Determines the output type of the LED6 pin. • ‘0’ (default) - The LED6 pin is an open-drain output with an external pull-up resistor. When the appropriate pin is set to the “active” state (logic ‘1’), the pin will be driven low. Conversely, when the pin is set to the “inactive” state (logic ‘0’), then the pin will be left in a High Z state and pulled high via an external pull-up resistor. • ‘1’ - The LED6 pin is a push-pull output. When driving a logic ‘1’, the pin is driven high. When driving a logic ‘0’, the pin is driven low. Bit 4 - LED5_OT - Determines the output type of the LED5 pin. Bit 3 - LED4_OT - Determines the output type of the LED4 pin. Bit 2 - LED3_OT - Determines the output type of the LED3 pin. Bit 1 - LED2_OT - Determines the output type of the LED2 pin. Bit 0 - LED1_OT - Determines the output type of the LED1 pin. 6.26 Sensor Input LED Linking Register The Sensor Input LED Linking register controls whether a capacitive touch sensor input is linked to an LED output. If the corresponding bit is set, then the appropriate LED output will change states defined by the LED Behavior controls (see Section 6.31) in response to the capacitive touch sensor input. Bit 5 - CS6_LED6 - Links the LED6 output to a detected touch on the CS6 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. • ‘0’ (default) - The LED6 output is not associated with the CS6 input. If a touch is detected on the CS6 input, the LED will not automatically be actuated. The LED is enabled and controlled via the LED Output Control register (see Section 6.28) and the LED Behavior registers (see Section 6.31). • ‘1’ - The LED6 output is associated with the CS6 input. If a touch is detected on the CS6 input, the LED will be actuated and behave as defined in Table 6-52. Bit 4 - CS5_LED5 - Links the LED5 output to a detected touch on the CS5 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. Bit 3 - CS4_LED4 - Links the LED4 output to a detected touch on the CS4 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. Bit 2 - CS3_LED3 - Links the LED3 output to a detected touch on the CS3 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. Bit 1 - CS2_LED2 - Links the LED2 output to a detected touch on the CS2 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. Bit 0 - CS1_LED1 - Links the LED1 output to a detected touch on the CS1 sensor input. When a touch is detected, the LED is actuated and will behave as determined by the LED Behavior controls. 6.27 LED Polarity Register TABLE 6-45: SENSOR INPUT LED LINKING REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 72h R/W Sensor Input LED Linking - - CS6_ LED6 CS5_ LED5 CS4_ LED4 CS3_ LED3 CS2_ LED2 CS1_ LED1 00h TABLE 6-46: LED POLARITY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 73h R/W LED Polarity - - LED6_ POL LED5_ POL LED4_ POL LED3_ POL LED2_ POL LED1_ POL 00h  2015 Microchip Technology Inc. DS00001621B-page 52 CAP1166 The LED Polarity register controls the logical polarity of the LED outputs. When these bits are set or cleared, the corresponding LED Mirror controls are also set or cleared (unless the BLK_POL_MIR bit is set - see Section 6.6, "Configuration Registers"). Table 6-48, "LED Polarity Behavior" shows the interaction between the polarity controls, output controls, and relative brightness. APPLICATION NOTE: The polarity controls determine the final LED pin drive. A touch on a linked capacitive touch sensor input is treated in the same way as the LED Output Control bit being set to a logic ‘1’. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’ then the LED will be on and that the CAP1166 LED pin is sinking the LED current. Conversely, if the LED pin is driven to a logic ‘1’, the LED will be off and there is no current flow. See Figure 5-1, "System Diagram for CAP1166". APPLICATION NOTE: This application note applies when the LED polarity is inverted (LEDx_POL = ‘0’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘0’ state in. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven low (i.e. maximum % of time that the LED is on) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven low (i.e. minimum % of time that the LED is on). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at the minimum duty cycle setting. Breathe operations will ramp the duty cycle from the minimum duty cycle to the maximum duty cycle. APPLICATION NOTE: This application note applies when the LED polarity is non-inverted (LEDx_POL = ‘1’). For LED operation, the duty cycle settings determine the % of time that the LED pin will be driven to a logic ‘1’ state. The Max Duty Cycle settings define the maximum % of time that the LED pin will be driven high (i.e. maximum % of time that the LED is off) while the Min Duty Cycle settings determine the minimum % of time that the LED pin will be driven high (i.e. minimum % of time that the LED is off). When there is no touch detected or the LED Output Control register bit is at a logic ‘0’, the LED output will be driven at 100 minus the minimum duty cycle setting. Breathe operations will ramp the duty cycle from 100 minus the minimum duty cycle to 100 minus the maximum duty cycle. APPLICATION NOTE: The LED Mirror controls (see Section 6.30, "LED Mirror Control Register") work with the polarity controls with respect to LED brightness but will not have a direct effect on the output pin drive. Bit 5 - LED6_POL - Determines the polarity of the LED6 output. • ‘0’ (default) - The LED6 output is inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘0’. • ‘1’ - The LED6 output is non-inverted. For example, a setting of ‘1’ in the LED Output Control register will cause the LED pin output to be driven to a logic ‘1’ or left in the high-z state as determined by its output type. Bit 4 - LED5_POL - Determines the polarity of the LED5 output. Bit 3 - LED4_POL - Determines the polarity of the LED4 output. Bit 2 - LED3_POL - Determines the polarity of the LED3 output. Bit 1 - LED2_POL - Determines the polarity of the LED2 output. Bit 0 - LED1_POL - Determines the polarity of the LED1 output. 6.28 LED Output Control Register The LED Output Control Register controls the output state of the LED pins that are not linked to sensor inputs. TABLE 6-47: LED OUTPUT CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 74h R/W LED Output Control - - LED6_ DR LED5_ DR LED4_ DR LED3_ DR LED2_ DR LED1_ DR 00h CAP1166 DS00001621B-page 53  2015 Microchip Technology Inc. The LED Polarity Control Register will determine the non actuated state of the LED pins. The actuated LED behavior is determined by the LED behavior controls (see Section 6.31, "LED Behavior Registers"). Table 6-48 shows the interaction between the polarity controls, output controls, and relative brightness. Bit 5 - LED6_DR - Determines whether LED6 output is driven high or low. • ‘0’ (default) - The LED6 output is driven at the minimum duty cycle or not actuated. • ‘1’ - The LED6 output is driven at the maximum duty cycle or is actuated. Bit 4 - LED5_DR - Determines whether LED5 output is driven high or low. Bit 3 - LED4_DR - Determines whether LED4 output is driven high or low. Bit 2 - LED3_DR - Determines whether LED3 output is driven high or low. Bit 1 - LED2_DR - Determines whether LED2 output is driven high or low. Bit 0 - LED1_DR - Determines whether LED1 output is driven high or low. 6.29 Linked LED Transition Control Register The Linked LED Transition Control register controls the LED drive when the LED is linked to a capacitive touch sensor input. These controls work in conjunction with the INV_LINK_TRAN bit (see Section 6.6.2, "Configuration 2 - 44h") to create smooth transitions from host control to linked LEDs. Note: If an LED is linked to a sensor input in the Sensor Input LED Linking Register (Section 6.26, "Sensor Input LED Linking Register"), the corresponding bit in the LED Output Control Register is ignored (i.e. a linked LED cannot be host controlled). TABLE 6-48: LED POLARITY BEHAVIOR LED Output Control Register or Touch Polarity Max Duty Min Duty Brightness LED Appearance 0 inverted (‘0’) not used minimum % of time that the LED is on (logic 0) maximum brightness at min duty cycle on at min duty cycle 1 inverted (‘0’) maximum % of time that the LED is on (logic 0) minimum % of time that the LED is on (logic 0) maximum brightness at max duty cycle. Brightness ramps from min duty cycle to max duty cycle according to LED behavior 0 non-inverted (‘1’) not used minimum % of time that the LED is off (logic 1) maximum brightness at 100 minus min duty cycle. on at 100 - min duty cycle 1 non-inverted (‘1’) maximum % of time that the LED is off (logic 1) minimum % of time that the LED is off (logic 1) For Direct behavior, maximum brightness is 100 minus max duty cycle. When breathing, max brightness is 100 minus min duty cycle. Brightness ramps from 100 - min duty cycle to 100 - max duty cycle. according to LED behavior TABLE 6-49: LINKED LED TRANSITION CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 77h R/W Linked LED Transition Control - - LED6_ LTRAN LED5_ LTRAN LED4_ LTRAN LED3_ LTRAN LED2_ LTRAN LED1_ LTRAN 00h  2015 Microchip Technology Inc. DS00001621B-page 54 CAP1166 Bit 5 - LED6_LTRAN - Determines the transition effect when LED6 is linked to CS6. • ‘0’ (default) - When the LED output control bit for LED6 is ‘1’, and then LED6 is linked to CS6 and no touch is detected, the LED will change states. • ‘1’ - If the INV_LINK_TRAN bit is ‘1’, when the LED output control bit for CS6 is ‘1’, and then CS6 is linked to LED6 and no touch is detected, the LED will not change states. In addition, the LED state will change when the sensor pad is touched. If the INV_LINK_TRAN bit is ‘0’, when the LED output control bit for CS6 is ‘1’, and then CS6 is linked to LED6 and no touch is detected, the LED will not change states. However, the LED state will not change when the sensor pad is touched. APPLICATION NOTE: If the LED behavior is not “Direct” and the INV_LINK_TRAN bit it ‘0’, the LED will not perform as expected when the LED6_LTRAN bit is set to ‘1’. Therefore, if breathe and pulse behaviors are used, set the INV_LINK_TRAN bit to ‘1’. Bit 4 - LED5_LTRAN - Determines the transition effect when LED5 is linked to CS5. Bit 3 - LED4_LTRAN - Determines the transition effect when LED4 is linked to CS4. Bit 2 - LED3_LTRAN - Determines the transition effect when LED3 is linked to CS3. Bit 1 - LED2_LTRAN - Determines the transition effect when LED2 is linked to CS2. Bit 0 - LED1_LTRAN - Determines the transition effect when LED1 is linked to CS1. 6.30 LED Mirror Control Register The LED Mirror Control Registers determine the meaning of duty cycle settings when polarity is non-inverted for each LED channel. When the polarity bit is set to ‘1’ (non-inverted), to obtain correct steps for LED ramping, pulse, and breathe behaviors, the min and max duty cycles need to be relative to 100%, rather than the default, which is relative to 0%. APPLICATION NOTE: The LED drive assumes that the LEDs are configured such that if the LED pin is driven to a logic ‘0’, the LED will be on and the CAP1166 LED pin is sinking the LED current. When the polarity bit is set to ‘1’, it is considered non-inverted. For systems using the opposite LED configuration, mirror controls would apply when the polarity bit is ‘0’. These bits are changed automatically if the corresponding LED Polarity bit is changed (unless the BLK_POL_MIR bit is set - see Section 6.6). Bit 5 - LED6_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. • ‘0’ (default) - The duty cycle settings are determined relative to 0% and are determined directly with the settings. • ‘1’ - The duty cycle settings are determined relative to 100%. Bit 4 - LED5_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. Bit 3 - LED4_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. Bit 2 - LED3_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. Bit 1 - LED2_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. Bit 0 - LED1_MIR_EN - Determines whether the duty cycle settings are “biased” relative to 0% or 100% duty cycle. TABLE 6-50: LED MIRROR CONTROL REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 79h R/W LED Mirror Control - - LED6_ MIR _ EN LED5_ MIR _ EN LED4_M IR_ EN LED3_ MIR_ EN LED2_ MIR _ EN LED1_ MIR _ EN 00h CAP1166 DS00001621B-page 55  2015 Microchip Technology Inc. 6.31 LED Behavior Registers The LED Behavior registers control the operation of LEDs. Each LED pin is controlled by a 2-bit field and the behavior is determined by whether the LED is linked to a capacitive touch sensor input or not. If the corresponding LED output is linked to a capacitive touch sensor input, the appropriate behavior will be enabled / disabled based on touches and releases. If the LED output is not associated with a capacitive touch sensor input, the appropriate behavior will be enabled / disabled by the LED Output Control register. If the respective LEDx_DR bit is set to a logic ‘1’, this will be associated as a “touch”, and if the LEDx_DR bit is set to a logic ‘0’, this will be associated as a “release”. Table 6-52, "LEDx_CTL Bit Decode" shows the behavior triggers. The defined behavior will activate when the Start Trigger is met and will stop when the Stop Trigger is met. Note the behavior of the Breathe Hold and Pulse Release option. The LED Polarity Control register will determine the non actuated state of the LED outputs (see Section 6.27, "LED Polarity Register"). APPLICATION NOTE: If an LED is not linked to a capacitive touch sensor input and is breathing (via the Breathe or Pulse behaviors), it must be unactuated and then re-actuated before changes to behavior are processed. For example, if the LED output is breathing and the Maximum duty cycle is changed, this change will not take effect until the LED output control register is set to ‘0’ and then re-set to ‘1’. APPLICATION NOTE: If an LED is not linked to the capacitive touch sensor input and configured to operate using Pulse 1 Behavior, then the circuitry will only be actuated when the corresponding output control bit is set. It will not check the bit condition until the Pulse 1 behavior is finished. The device will not remember if the bit was cleared and reset while it was actuated. APPLICATION NOTE: If an LED is actuated and not linked and the desired LED behavior is changed, this new behavior will take effect immediately; however, the first instance of the changed behavior may act incorrectly (e.g. if changed from Direct to Pulse 1, the LED output may ‘breathe’ 4 times and then end at minimum duty cycle). LED Behaviors will operate normally once the LED has been un-actuated and then re-actuated. APPLICATION NOTE: If an LED is actuated and it is switched from linked to a capacitive touch sensor input to unlinked (or vice versa), the LED will respond to the new command source immediately if the behavior was Direct or Breathe. For Pulse behaviors, it will complete the behavior already in progress. For example, if a linked LED was actuated by a touch and the control is changed so that it is unlinked, it will check the status of the corresponding LED Output Control bit. If that bit is ‘0’, then the LED will behave as if a release was detected. Likewise, if an unlinked LED was actuated by the LED Output Control register and the control is changed so that it is linked and no touch is detected, then the LED will behave as if a release was detected. 6.31.1 LED BEHAVIOR 1 - 81H Bits 7 - 6 - LED4_CTL[1:0] - Determines the behavior of LED4 as shown in Table 6-52. Bits 5 - 4 - LED3_CTL[1:0] - Determines the behavior of LED3 as shown in Table 6-52. Bits 3 - 2 - LED2_CTL[1:0] - Determines the behavior of LED2 as shown in Table 6-52. Bits 1 - 0 - LED1_CTL[1:0] - Determines the behavior of LED1 as shown in Table 6-52. 6.31.2 LED BEHAVIOR 2 - 82H Bits 3 - 2 - LED6_CTL[1:0] - Determines the behavior of LED6 as shown in Table 6-52. Bits 1 - 0 - LED5_CTL[1:0] - Determines the behavior of LED5 as shown in Table 6-52. TABLE 6-51: LED BEHAVIOR REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 81h R/W LED Behavior 1 LED4_CTL[1:0] LED3_CTL[1:0] LED2_CTL[1:0] LED1_CTL[1:0] 00h 82h R/W LED Behavior 2 - - - - LED6_CTL[1:0] LED5_CTL[1:0] 00h  2015 Microchip Technology Inc. DS00001621B-page 56 CAP1166 APPLICATION NOTE: The PWM frequency is determined based on the selected LED behavior, the programmed breathe period, and the programmed min and max duty cycles. For the Direct behavior mode, the PWM frequency is calculated based on the programmed Rise and Fall times. If these are set at 0, then the maximum PWM frequency will be used based on the programmed duty cycle settings. 6.32 LED Pulse 1 Period Register The LED Pulse Period 1 register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 01b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms (24 x 32ms = 768ms). The total range is from 32ms to 4.064 seconds as shown in Table 6-54 with the default being 1024ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. Bit 7 - ST_TRIG - Determines the start trigger for the LED Pulse behavior. • ‘0’ (default) - The LED will Pulse when a touch is detected or the drive bit is set. • ‘1’ - The LED will Pulse when a release is detected or the drive bit is cleared. TABLE 6-52: LEDX_CTL BIT DECODE LEDx_CTL [1:0] Operation Description Start TRigger Stop Trigger 1 0 0 0 Direct The LED is driven to the programmed state (active or inactive). See Figure 6-7 Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 0 1 Pulse 1 The LED will “Pulse” a programmed number of times. During each “Pulse” the LED will breathe up to the maximum brightness and back down to the minimum brightness so that the total “Pulse” period matches the programmed value. Touch or Release Detected or LED Output Control bit set or cleared (see Section 6.32) n/a 1 0 Pulse 2 The LED will “Pulse” when the start trigger is detected. When the stop trigger is detected, it will “Pulse” a programmable number of times then return to its minimum brightness. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared 1 1 Breathe The LED will breathe. It will be driven with a duty cycle that ramps up from the programmed minimum duty cycle (default 0%) to the programmed maximum duty cycle duty cycle (default 100%) and then back down. Each ramp takes up 50% of the programmed period. The total period of each “breath” is determined by the LED Breathe Period controls - see Section 6.34. Touch Detected or LED Output Control bit set Release Detected or LED Output Control bit cleared TABLE 6-53: LED PULSE 1 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 84h R/W LED Pulse 1 Period ST_ TRIG P1_ PER6 P1_ PER5 P1_ PER4 P1_ PER3 P1_ PER2 P1_ PER1 P1_ PER0 20h CAP1166 DS00001621B-page 57  2015 Microchip Technology Inc. The Pulse 1 operation is shown in Figure 6-1 when the LED output is configured for non-inverted polarity (LEDx_POL = 1) and in Figure 6-2 for inverted polarity (LEDx_POL = 0). . FIGURE 6-1: Pulse 1 Behavior with Non-Inverted Polarity FIGURE 6-2: Pulse 1 Behavior with Inverted Polarity TABLE 6-54: LED PULSE / BREATHE PERIOD EXAMPLE Setting (HEX) Setting (Decimal) Total Breathe / Pulse Period (MS) 00h 0 32 01h 1 32 02h 2 64 03h 3 96 . . . . . . . . . 7Dh 125 4000 Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected (100% - Pulse 1 Max Duty Cycle) * Brightness X pulses after touch or after release Pulse 1 Period (P1_PER) (100% - Pulse 1 Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation Normal – untouched operation Touch Detected or Release Detected Pulse 1 Min Duty Cycle * Brightness X pulses after touch or after release Pulse Period (P1_PER) Pulse 1 Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001621B-page 58 CAP1166 6.33 LED Pulse 2 Period Register The LED Pulse 2 Period register determines the overall period of a pulse operation as determined by the LED_CTL registers (see Table 6-52 - setting 10b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 640ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. The Pulse 2 Behavior is shown in Figure 6-3 for non-inverted polarity (LEDx_POL = 1) and in Figure 6-4 for inverted polarity (LEDx_POL = 0). 7Eh 126 4032 7Fh 127 4064 TABLE 6-55: LED PULSE 2 PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 85h R/W LED Pulse 2 Period - P2_ PER6 P2_ PER5 P2_ PER4 P2_ PER3 P2_ PER2 P2_ PER1 P2_ PER0 14h FIGURE 6-3: Pulse 2 Behavior with Non-Inverted Polarity TABLE 6-54: LED PULSE / BREATHE PERIOD EXAMPLE (CONTINUED) Setting (HEX) Setting (Decimal) Total Breathe / Pulse Period (MS) . . . Normal – untouched operation Normal – untouched operation Touch Detected (100% - Pulse 2 Min Duty Cycle) * Brightness (100% - Pulse 2 Max Duty Cycle) * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness CAP1166 DS00001621B-page 59  2015 Microchip Technology Inc. 6.34 LED Breathe Period Register The LED Breathe Period register determines the overall period of a breathe operation as determined by the LED_CTL registers (see Table 6-52 - setting 11b). The LSB represents 32ms so that a setting of 18h (24d) would represent a period of 768ms. The total range is from 32ms to 4.064 seconds (see Table 6-54) with a default of 2976ms. APPLICATION NOTE: Due to constraints on the LED Drive PWM operation, any Breathe Period less than 160ms (05h) may not be achievable. The device will breathe at the minimum period possible as determined by the period and min / max duty cycle settings. 6.35 LED Configuration Register The LED Configuration register controls general LED behavior as well as the number of pulses that are sent for the PULSE LED output behavior. Bit 6 - RAMP_ALERT - Determines whether the device will assert the ALERT# pin when LEDs actuated by the LED Output Control register bits have finished their respective behaviors. Interrupts will only be generated if the LED activity is generated by writing the LED Output Control registers. Any LED activity associated with touch detection will not cause an interrupt to be generated when the LED behavior has been finished. • ‘0’ (default) - The ALERT# pin will not be asserted when LEDs actuated by the LED Output Control register have finished their programmed behaviors. • ‘1’ - The ALERT# pin will be asserted whenever any LED that is actuated by the LED Output Control register has finished its programmed behavior. Bits 5 - 3 - PULSE2_CNT[2:0] - Determines the number of pulses used for the Pulse 2 behavior as shown in Table 6-58. Bits 2 - 0 - PULSE1_CNT[2:0] - Determines the number of pulses used for the Pulse 1 behavior as shown in Table 6-58. FIGURE 6-4: Pulse 2 Behavior with Inverted Polarity TABLE 6-56: LED BREATHE PERIOD REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 86h R/W LED Breathe Period - BR_ PER6 BR_ PER5 BR_ PER4 BR_ PER3 BR_ PER2 BR_ PER1 BR_ PER0 5Dh TABLE 6-57: LED CONFIGURATION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 88h R/W LED Config - RAMP_ ALERT PULSE2_CNT[2:0] PULSE1_CNT[2:0] 04h Normal – untouched operation Normal – untouched operation Touch Detected Pulse 2 Max Duty Cycle * Brightness Pulse 2 Min Duty Cycle * Brightness X additional pulses after release Release Detected Pulse Period (P2_PER) LED Brightness . . .  2015 Microchip Technology Inc. DS00001621B-page 60 CAP1166 6.36 LED Duty Cycle Registers The LED Duty Cycle registers determine the minimum and maximum duty cycle settings used for the LED for each LED behavior. These settings affect the brightness of the LED when it is fully off and fully on. The LED driver duty cycle will ramp up from the minimum duty cycle to the maximum duty cycle and back down again. APPLICATION NOTE: When operating in Direct behavior mode, changes to the Duty Cycle settings will be applied immediately. When operating in Breathe, Pulse 1, or Pulse 2 modes, the LED must be unactuated and then re-actuated before changes to behavior are processed. Bits 7 - 4 - X_MAX_DUTY[3:0] - Determines the maximum PWM duty cycle for the LED drivers as shown in Table 6-60. Bits 3 - 0 - X_MIN_DUTY[3:0] - Determines the minimum PWM duty cycle for the LED drivers as shown in Table 6-60. TABLE 6-58: PULSEX_CNT DECODE PULSEX_CNT[2:0] Number of Breaths 21 0 0 0 0 1 (default - Pulse 2) 00 1 2 01 0 3 01 1 4 1 0 0 5 (default - Pulse 1) 10 1 6 11 0 7 11 1 8 TABLE 6-59: LED DUTY CYCLE REGISTERS ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 90h R/W LED Pulse 1 Duty Cycle P1_MAX_DUTY[3:0] P1_MIN_DUTY[3:0] F0h 91h R/W LED Pulse 2 Duty Cycle P2_MAX_DUTY[3:0] P2_MIN_DUTY[3:0] F0h 92h R/W LED Breathe Duty Cycle BR_MAX_DUTY[3:0] BR_MIN_DUTY[3:0] F0h 93h R/W Direct Duty Cycle DR_MAX_DUTY[3:0] DR_MIN_DUTY[3:0] F0h TABLE 6-60: LED DUTY CYCLE DECODE x_MAX/MIN_Duty [3:0] Maximum Duty Cycle Minimum Duty Cycle 3 21 0 0 0 0 0 7% 0% 0 0 0 1 9% 7% 0 0 1 0 11% 9% 0 0 1 1 14% 11% 0 1 0 0 17% 14% 0 1 0 1 20% 17% 0 1 1 0 23% 20% 0 1 1 1 26% 23% 1 0 0 0 30% 26% 1 0 0 1 35% 30% 1 0 1 0 40% 35% CAP1166 DS00001621B-page 61  2015 Microchip Technology Inc. 6.37 LED Direct Ramp Rates Register The LED Direct Ramp Rates register control the rising and falling edge time of an LED that is configured to operate in Direct behavior mode. The rising edge time corresponds to the amount of time the LED takes to transition from its minimum duty cycle to its maximum duty cycle. Conversely, the falling edge time corresponds to the amount of time that the LED takes to transition from its maximum duty cycle to its minimum duty cycle. Bits 5 - 3 - RISE_RATE[2:0] - Determines the rising edge time of an LED when it transitions from its minimum drive state to its maximum drive state as shown in Table 6-62. Bits 2 - 0 - FALL_RATE[2:0] - Determines the falling edge time of an LED when it transitions from its maximum drive state to its minimum drive state as shown in Table 6-62. 6.38 LED Off Delay Register The LED Off Delay register determines the amount of time that an LED remains at its maximum duty cycle (or minimum as determined by the polarity controls) before it starts to ramp down. If the LED is operating in Breathe mode, this delay is applied at the top of each “breath”. If the LED is operating in the Direct mode, this delay is applied when the LED is unactuated. 1 0 1 1 46% 40% 1 1 0 0 53% 46% 1 1 0 1 63% 53% 1 1 1 0 77% 63% 1 1 1 1 100% 77% TABLE 6-61: LED DIRECT RAMP RATES REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 94h R/W LED Direct Ramp Rates - - RISE_RATE[2:0] FALL_RATE[2:0] 00h TABLE 6-62: RISE / FALL RATE DECODE RISE_RATE/ FALL_RATE/ Bit Decode Rise / Fall Time (TRISE / TFALL) 21 0 00 0 0 0 0 1 250ms 0 1 0 500ms 0 1 1 750ms 1 0 0 1s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2s TABLE 6-63: LED OFF DELAY REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default 95h R/W LED Off Delay Register - BR_OFF_DLY[2:0] DIR_OFF_DLY[3:0] 00h TABLE 6-60: LED DUTY CYCLE DECODE (CONTINUED) x_MAX/MIN_Duty [3:0] Maximum Duty Cycle Minimum Duty Cycle 3 21 0  2015 Microchip Technology Inc. DS00001621B-page 62 CAP1166 Bits 6 - 4 - BR_OFF_DLY[2:0] - Determines the Breathe behavior mode off delay, which is the amount of time an LED in Breathe behavior mode remains inactive after it finishes a breathe pulse (ramp on and ramp off), as shown in Figure 6- 5 (non-inverted polarity LEDx_POL = 1) and Figure 6-6 (inverted polarity LEDx_POL = 0). Available settings are shown in Table 6-64. FIGURE 6-5: Breathe Behavior with Non-Inverted Polarity FIGURE 6-6: Breathe Behavior with Inverted Polarity LED Actuated 100% - Breathe Max Min Cycle * Brightness 100% - Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) LED Actuated Breathe Max Duty Cycle * Brightness Breathe Min Duty Cycle * Brightness LED Unactuated Breathe Off Delay (BR_OFF_DLY) LED Brightness Breathe Period (BR_PER) CAP1166 DS00001621B-page 63  2015 Microchip Technology Inc. Bits 3 - 0 - DIR_OFF_DLY[3:0] - Determines the turn-off delay, as shown in Table 6-65, for all LEDs that are configured to operate in Direct behavior mode. The Direct behavior operation is determined by the combination of programmed Rise Time, Fall Time, Min and Max Duty cycles, Off Delay, and polarity. Figure 6-7 shows the behavior for non-inverted polarity (LEDx_POL = 1) while Figure 6- 8 shows the behavior for inverted polarity (LEDx_POL = 0). TABLE 6-64: BREATHE OFF DELAY SETTINGS BR_OFF_DLY [2:0] OFF Delay 2 10 0 0 0 0 (default) 0 0 1 0.25s 0 1 0 0.5s 0 1 1 0.75s 1 0 0 1.0s 1 0 1 1.25s 1 1 0 1.5s 1 1 1 2.0s FIGURE 6-7: Direct Behavior for Non-Inverted Polarity FIGURE 6-8: Direct Behavior for Inverted Polarity Normal – untouched operation RISE_RATE Setting (tRISE) (100% - Max Duty Cycle) * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation (100% - Min Duty Cycle) * Brightness LED Brightness Normal – untouched operation RISE_RATE Setting (tRISE) Min Duty Cycle * Brightness Touch Detected Release Detected Off Delay (tOFF_DLY) FALL_RATE Setting (tFALL) Normal – untouched operation Max Duty Cycle * Brightness LED Brightness  2015 Microchip Technology Inc. DS00001621B-page 64 CAP1166 6.39 Sensor Input Calibration Registers The Sensor Input Calibration registers hold the 10-bit value that represents the last calibration value. TABLE 6-65: OFF DELAY DECODE OFF Delay[3:0] Bit Decode OFF Delay (tOFF_DLY) 32 1 0 00 0 0 0 0 0 0 1 250ms 0 0 1 0 500ms 0 0 1 1 750ms 0 1 0 0 1s 0 1 0 1 1.25s 0 1 1 0 1.5s 0 1 1 1 2s 1 0 0 0 2.5s 1 0 0 1 3.0s 1 0 1 0 3.5s 1 0 1 1 4.0s 1 1 0 0 4.5s All others 5.0s TABLE 6-66: SENSOR INPUT CALIBRATION REGISTERS ADDR Register R/W B7 B6 B5 B4 B3 B2 B1 B0 Default B1h Sensor Input 1 Calibration R CAL1_9 CAL1_8 CAL1_7 CAL1_6 CAL1_5 CAL1_4 CAL1_3 CAL1_2 00h B2h Sensor Input 2 Calibration R CAL2_9 CAL2_8 CAL2_7 CAL2_6 CAL2_5 CAL2_4 CAL2_3 CAL2_2 00h B3h Sensor Input 3 Calibration R CAL3_9 CAL3_8 CAL3_7 CAL3_6 CAL3_5 CAL3_4 CAL3_3 CAL3_2 00h B4h Sensor Input 4 Calibration R CAL4_9 CAL4_8 CAL4_7 CAL4_6 CAL4_5 CAL4_4 CAL4_3 CAL4_2 00h B5h Sensor Input 5 Calibration R CAL5_9 CAL5_8 CAL5_7 CAL5_6 CAL5_5 CAL5_4 CAL5_3 CAL5_2 00h B6h Sensor Input 6 Calibration R CAL6_9 CAL6_8 CAL6_7 CAL6_6 CAL6_5 CAL6_4 CAL6_3 CAL6_2 00h B9h Sensor Input Calibration LSB 1 R CAL4_1 CAL4_0 CAL3_1 CAL3_0 CAL2_1 CAL2_0 CAL1_1 CAL1_0 00h BAh Sensor Input Calibration LSB 2 R - - - - CAL6_1 CAL6_0 CAL5_1 CAL5_0 00h CAP1166 DS00001621B-page 65  2015 Microchip Technology Inc. 6.40 Product ID Register The Product ID register stores a unique 8-bit value that identifies the device. 6.41 Manufacturer ID Register The Vendor ID register stores an 8-bit value that represents Microchip. 6.42 Revision Register The Revision register stores an 8-bit value that represents the part revision. TABLE 6-67: PRODUCT ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FDh R Product ID 0 1 0 1 0 0 0 1 51h TABLE 6-68: VENDOR ID REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh TABLE 6-69: REVISION REGISTER ADDR R/W Register B7 B6 B5 B4 B3 B2 B1 B0 Default FFh R Revision 1 0 0 0 0 0 1 1 83h  2015 Microchip Technology Inc. DS00001621B-page 66 CAP1166 7.0 PACKAGE INFORMATION 7.1 CAP1166 Package Drawings Note: For the most current package drawings, see the Microchip Packaging Specification at: http://www.microchip.com/packaging. FIGURE 7-1: 24-Pin SSOP Package Drawing CAP1166 DS00001621B-page 67  2015 Microchip Technology Inc. FIGURE 7-2: 24-Pin SSOP Package Dimensions  2015 Microchip Technology Inc. DS00001621B-page 68 CAP1166 FIGURE 7-3: CAP1166 PCB Land Pattern - 24-Pin SSOP CAP1166 DS00001621B-page 69  2015 Microchip Technology Inc. FIGURE 7-4: 20-Pin QFN 4mm x 4mm Package Drawing  2015 Microchip Technology Inc. DS00001621B-page 70 CAP1166 FIGURE 7-5: 20-Pin QFN 4mm x 4mm Package Dimensions FIGURE 7-6: 20-Pin QFN 4mm x 4mm PCB Drawing CAP1166 DS00001621B-page 71  2015 Microchip Technology Inc. 7.2 Package Marking FIGURE 7-7: CAP1166 Package Markings - 20-Pin QFN FIGURE 7-8: CAP1166 Package Markings - 24-Pin SSOP C 1 66 - 1 Y WWN N N A RCC e3 TOP BOTTOM Bottom marking not allowed PB-FREE/GREEN SYMBOL (Matte Sn) Lines 1-3: Line 4: Center Horizontal Alignment Left Horizontal Alignment PIN 1 0.41 3x 0.56 Line 1 – SMSC Logo without circled R symbol Line 2 – Device ID, Version Line 3 – Year, Week, Alphanumeric Traceability Code Line 4 – Revision, Country Code 1 e3 TOP BOTTOM PB-FREE/GREEN SYMBOL (Matte Sn) PIN 1 0.6 2x 1.5pt Line 1 – SMSC Logo with circled R symbol Line 2 – Device ID, Version Line 3 – Revision, Year, Week, Traceability Code Line 2 – Vendor Code, Country Code PIN 1 C A 11 P 6 6 - 1 Y W NNNA W ® R B B 9 3 V V V CC - Line 1 – Engineering Code 2x 1.5pt  2015 Microchip Technology Inc. DS00001621B-page 72 CAP1166 APPENDIX A: DEVICE DELTA A.1 Delta from CAP1066 to CAP1166 1. Updated circuitry to improve power supply rejection. 2. Updated LED driver duty cycle decode values to have more distribution at lower values - closer to a logarithmic curve. See Table 6-60, "LED Duty Cycle Decode". 3. Updated bug that breathe periods were not correct above 2.6s. This includes rise / fall time decodes above 1.5s. 4. Added filtering on RESET pin to prevent errant resets. 5. Updated controls so that the RESET pin assertion places the device into the lowest power state available and causes an interrupt when released. See Section 5.2, "RESET Pin". 6. Added 1 bit to the LED Off Delay register (see Section 6.38, "LED Off Delay Register") to extend times from 2s to 5s in 0.5s intervals. 7. Breathe behavior modified. A breathe off delay control was added to the LED Off Delay Register (see Section 6.38, "LED Off Delay Register") so the LEDs can be configured to remain inactive between breathes. 8. Added controls for the LED transition effects when linking LEDs to capacitive sensor inputs. See Section 6.29, "Linked LED Transition Control Register". 9. Added controls to “mirror” the LED duty cycle outputs so that when polarity changes, the LED brightness levels look right. These bits are automatically set when polarity is set. Added control to break this auto-set behavior. See Section 6.30, "LED Mirror Control Register". 10. Added Multiple Touch Pattern detection circuitry. See Section 6.15, "Multiple Touch Pattern Configuration Register". 11. Added General Status register to flag Multiple touches, Multiple Touch Pattern issues and general touch detections. See Section 6.2, "Status Registers". 12. Added bits 6 and 5 to the Recalibration Configuration register (2Fh - see Section 6.17, "Recalibration Configuration Register"). These bits control whether the accumulation of intermediate data and the consecutive negative delta counts counter are cleared when the noise status bit is set. 13. Added Configuration 2 register for LED linking controls, noise detection controls, and control to interrupt on press but not on release. Added control to change alert pin polarity. See Section 6.6, "Configuration Registers". 14. Updated Deep Sleep behavior so that device does not clear DSLEEP bit on received communications but will wake to communicate. 15. Changed PWM frequency for LED drivers. The PWM frequency was derived from the programmed breathe period and duty cycle settings and it ranged from ~4Hz to ~8000 Hz. The PWM frequency has been updated to be a fixed value of ~2000Hz. 16. Register delta: Table A.1 Register Delta From CAP1066 to CAP1166 Address Register Delta Delta Default 00h Page 33 Changed - Main Status / Control added bits 7-6 to control gain 00h 02h Page 34 New - General Status new register to store MTP, MULT, LED, RESET, and general TOUCH bits 00h 44h Page 37 New - Configuration 2 new register to control alert polarity, LED touch linking behavior, LED output behavior, and noise detection, and interrupt on release 40h 24h Page 41 Changed - Averaging Control updated register bits - moved SAMP_AVG[2:0] bits and added SAMP_- TIME bit 1. Default changed 39h 2Bh Page 44 New - Multiple Touch Pattern Configuration new register for Multiple Touch Pattern configuration - enable and threshold settings 80h CAP1166 DS00001621B-page 73  2015 Microchip Technology Inc. 2Dh Page 45 New - Multiple Touch Pattern Register new register for Multiple Touch Pattern detection circuitry - pattern or number of sensor inputs 3Fh 2Fh Page 45 Changed - Recalibration Configuration updated register - updated CAL_CFG bit decode to add a 128 averages setting and removed highest time setting. Default changed. Added bit 6 NO_CLR_INTD and bit 5 NO_CLR_NEG. 8Ah 38h Page 47 Changed - Sensor Input Noise Threshold updated register bits - removed bits 7 - 3 and consolidated all controls into bits 1 - 0. These bits will set the noise threshold for all channels. Default changed 01h 39h Removed - Noise Threshold Register 2 removed register n/a 41h Page 48 Changed - Standby Configuration updated register bits - moved STBY_AVG[2:0] bits and added STBY_- TIME bit 1. Default changed 39h 77h Page 53 New - Linked LED Transition Control new register to control transition effect when LED linked to sensor inputs 00h 79h Page 54 New - LED Mirror Control new register to control LED output mirroring for brightness control when polarity changed 00h 90h Page 60 Changed - LED Pulse 1 Duty Cycle changed bit decode to be more logarithmic F0h 91h Page 60 Changed - LED Pulse 2 Duty Cycle changed bit decode to be more logarithmic F0h 92h Page 60 Changed - LED Breathe Duty Cycle changed bit decode to be more logarithmic F0h 93h Page 60 Changed - LED Direct Duty Cycle changed bit decode to be more logarithmic F0h 95h Added controls - LED Off Delay Added bits 6-4 BR_OFF_DLY[2:0] Added bit 3 DIR_OFF_DLY[3] 00h FDh Page 65 Changed - Product ID Changed bit decode for CAP1166 51h Table A.1 Register Delta From CAP1066 to CAP1166 (continued) Address Register Delta Delta Default  2015 Microchip Technology Inc. DS00001621B-page 74 CAP1166 APPENDIX B: DATA SHEET REVISION HISTORY Revision Section/Figure/Entry Correction DS00001621B (02-09-15) Features, Table 2-1, Table 2- 2, "Pin Types", Section 5.0, "General Description" References to BC-Link Interface, BC_DATA, BC_- CLK, BC-IRQ#, BC-Link bus have been removed Application Note under Table 2-6 [BC-Link] hidden in data sheet Table 3-2, "Electrical Specifications" BC-Link Timing Section hidden in data sheet Table 4-1 Protocol Used for 68K Pull Down Resistor changed from “BC-Link Communications” to “Reserved” Section 4.2.2, "SMBus Address and RD / WR Bit" Replaced “client address” with “slave address” in this section. Section 4.2.4, SMBus ACK and NACK Bits, Section 4.2.5, SMBus Stop Bit,Section 4.2.7, SMBus and I2C Compatibility Replaced “client” with “slave” in these sections. Table 4-4, "Read Byte Protocol" Heading changed from “Client Address” to “Slave Address” Table 6-1 Register Name for Register Address 77h changed from “LED Linked Transition Control” to “Linked LED Transition Control” Section 6.30 changed CS6 to LED6 Table 6-53 Modified B3 bit name Section 7.7 Package Marking Updated package drawing Appendix A: Device Delta changed 2Dh to 2Fh in item #12 Product Identification System Removed BC-Link references REV A REV A replaces previous SMSC version Rev. 1.32 (01-05-12) Rev. 1.32 (01-05-12) Table 3-2, "Electrical Specifications" Added conditions for tHD:DAT. Section 4.2.7, "SMBus and I2C Compatibility" Renamed from “SMBus and I2C Compliance.” First paragraph, added last sentence: “For information on using the CAP1188 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I 2C Systems.” Added: CAP1188 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. Section 6.4, "Sensor Input Delta Count Registers" Changed negative value cap from FFh to 80h. Rev. 1.31 (08-18-11) Section 4.3.3, "SMBus Send Byte" Added an application note: The Send Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Section 4.3.4, "SMBus Receive Byte" Added an application note: The Receive Byte protocol is not functional in Deep Sleep (i.e., DSLEEP bit is set). Rev. 1.3 (05-18-11) Section 6.42, "Revision Register" Updated revision ID from 82h to 83h. Rev. 1.2 (02-10-11) Section A.8, "Delta from Rev B (Mask B0) to Rev C (Mask B1)" Added. CAP1166 DS00001621B-page 75  2015 Microchip Technology Inc. Table 2-1, "Pin Description for CAP1166" Changed value in “Unused Connection” column for the ADDR_COMM pin from “Connect to Ground” to “n/a“. Table 3-2, "Electrical Specifications" PSR improvements made in functional revision B. Changed PSR spec from ±100 typ and ±200 max counts / V to ±3 and ±10 counts / V. Conditions updated. Section 5.5.2, "Recalibrating Sensor Inputs" Added more detail with subheadings for each type of recalibration. Section 6.6, "Configuration Registers" Added bit 5 BLK_PWR_CTRL to the Configuration 2 Register 44h. The TIMEOUT bit is set to ‘1’ by default for functional revision B and is set to ‘0’ by default for functional revision C. Section 6.42, "Revision Register" Updated revision ID in register FFh from 81h to 82h. Rev. 1.1 (11-17-10) Document Updated for functional revision B. See Section A.7, "Delta from Rev A (Mask A0) to Rev B (Mask B0)". Cover Added to General Description: “includes circuitry and support for enhanced sensor proximity detection.” Added the following Features: Calibrates for Parasitic Capacitance Analog Filtering for System Noise Sources Press and Hold feature for Volume-like Applications Table 3-2, "Electrical Specifications" Conditions for Power Supply Rejection modified adding the following: Sampling time = 2.56ms Averaging = 1 Negative Delta Counts = Disabled All other parameters default Section 6.11, "Calibration Activate Register" Updated register description to indicate which re-calibration routine is used. Section 6.14, "Multiple Touch Configuration Register" Updated register description to indicate what will happen. Table 6-34, "CSx_BN_TH Bit Decode" Table heading changed from “Threshold Divide Setting” to “Percent Threshold Setting”. Section 7.0, "Package Information" Added PCB land pattern. CAP1166-1 added in an SSOP package. Rev. 1.0 (06-14-10) Initial release Revision Section/Figure/Entry Correction  2015 Microchip Technology Inc. DS00001621B-page 76 CAP1166 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2015 Microchip Technology Inc. DS00001621B-page 77 CAP1166 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] - 1 - XXX - [X](1) l l l l Device Temperature Package Tape and Reel Range Option Examples: Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Device: CAP1166 Temperature Range: Blank = 0°C to +85°C (Extended Commercial) Package: BP = QFN CZC = SSOP Tape and Reel Option: TR = Tape and Reel(1) CAP1166-1-BP-TR 20-pin QFN 4mm x 4mm (RoHS compliant) Six capacitive touch sensor inputs, Six LED drivers, Dedicated Wake, Reset, SMBus / BC-Link / SPI interfaces Reel size is 4,000 pieces CAP1166-1-CZC-TR 24-pin SSOP (RoHS compliant) Six capacitive touch sensor inputs, Six LED drivers, Dedicated Wake, Reset, SMBus / BC-Link / SPI interfaces Reel size is 2,500 pieces  2015 Microchip Technology Inc. DS00001621B-page 78 CAP1166 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632770318 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2015 Microchip Technology Inc. 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