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Transistor-Farnell.htm 18-Apr-2013 08:06 4.7M
Tension-2-Farnell.htm 18-Apr-2013 08:05 5.2M
Piece-Farnell.htm 18-Apr-2013 08:05 5.2M
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Contact-Farnell.htm 18-Apr-2013 07:59 5.4M
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Ecrou-Farnell.htm 18-Apr-2013 07:57 3.5M
Nylon-Farnell.htm 18-Apr-2013 07:57 3.6M
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LED-Farnell.htm 17-Apr-2013 18:25 3.4M
Joint-Farnell.htm 17-Apr-2013 18:25 3.4M
Commutateurs-Farnell..> 17-Apr-2013 18:25 2.3M
Analogique-Farnell.htm 17-Apr-2013 18:24 1.2M
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AOP-Farnell.htm 16-Apr-2013 16:17 4.4M
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Kemet-Farnell.htm 16-Apr-2013 11:43 2.7M
Oscillateurs-Farnell..> 16-Apr-2013 11:43 2.9M
Valeurs-Fixes-Divers..> 12-Apr-2013 19:37 3.2M
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Lames-Farnell.htm 12-Apr-2013 19:23 2.8M
INTERSIL-Farnell.htm 12-Apr-2013 19:22 2.7M
RFID-Farnell.htm 12-Apr-2013 19:21 2.7M
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pressure_ic-Farnell.htm 12-Apr-2013 18:58 2.9M
Galettes-Farnell.htm 12-Apr-2013 18:58 1.3M
CINCH-SD-LB-CONNECTOR-BACKSHELL
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DRIVER-DE-MOSFET-HI-..> 14-Dec-2012 08:43 3.2K
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DRIVER-DEMI-PONT-CMS..> 13-Dec-2012 19:02 3.2K
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RESIST.-0.1%-2K67-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-2K87-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K01-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K4-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K16-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K32-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K57-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K65-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K74-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K83-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-3K92-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-4K02-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-4K22-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-4K42-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-4K53-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-4K75-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-4K99-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-5K9-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-5K11-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-5K23-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-5K62-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-6K04-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-6K49-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-6K81-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-7K15-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-7K32-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-7K68-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-7K87-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-8K06-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-8K25-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-8K45-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-9K31-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-9K53-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-10K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-10K2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-10K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-10R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-10R2-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-10R5-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-11K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-11K3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-11K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-11R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-12K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-12K7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-12R1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-13K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-13K3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-13K7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-13R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-13R3-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-14K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-14K3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-14R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-15K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-15K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-15R-108..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-16K2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-16K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-16K9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-16R2-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-17K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-19K1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-19K6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-19R1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-20K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-20K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-21K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-21K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-22R1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-23K7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-23R7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-24K9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-26K1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-27K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-27R4-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-28K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-28R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-28R7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-29R4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-30K1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-30K9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-30R1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-30R9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-31K6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-31R6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-32K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-33R2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-34K8-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-34R-108..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-35K7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-36K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-37K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-38K3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-38R3-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-39K2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-39R2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-40R2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-42K2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-42R2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-44K2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-45K3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-45R3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-46K4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-47K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-49K9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-49R9-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-51K1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-51R1-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-52K3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-52R3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-53K6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-53R6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-57K6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-59R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-60R4-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-61K9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-61R9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-63R4-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-64R9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-66K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-66R5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-71K5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-71R5-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-73K2-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-75K-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-75R-108..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-76R8-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-78K7-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-78R7-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-80K6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-80R6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-82R5-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-86K6-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-88R7-10..> 14-Dec-2012 08:52 3.1K
RESIST.-0.1%-90K9-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-93R1-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-95R3-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-100K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-102K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-102R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-105K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-107K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-110K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-110R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-113R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-115K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-115R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-118R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-121K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-121R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-127K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-130K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-130R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-137K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-137R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-143R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-147K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-150K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-154R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-162K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-162R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-165K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-169K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-174K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-182K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-182R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-191R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-196K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-196R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-200K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-200R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-210R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-215R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-221K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-221R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-226K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-226R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-232R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-237K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-243K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-243R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-249K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-261K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-267R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-274K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-280K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-280R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-301K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-309K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-309R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-332R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-340K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-340R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-348K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-357R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-374K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-383R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-402K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-422R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-432K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-464K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-499R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-511K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-562K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-562R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-576K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-576R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-590K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-604R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-619K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-619R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-634R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-649K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-649R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-665K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-665R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-681R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-698R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-715R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-787R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-806R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-825K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-825R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-887K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-909K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-953K-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1%-976R-10..> 14-Dec-2012 08:51 3.1K
RESIST.-0.1--1K02-10..> 14-Dec-2012 08:41 3.1K
RESIST.-0.1--1K07-10..> 14-Dec-2012 08:41 3.1K
RESIST.-0.1--1K1-108..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--1K3-108..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--1K4-108..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--1K13-10..> 14-Dec-2012 08:41 3.1K
RESIST.-0.1--1K18-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--1K21-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1K27-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--1K37-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--1K43-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1K47-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1K54-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1K62-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1K65-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--1K69-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1K74-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--1K82-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--1K96-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--1M0-108..> 14-Dec-2012 08:37 3.1K
RESIST.-0.1--2K0-108..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--2K05-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--2K1-108..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--2K21-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--2K37-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--2K43-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--2K49-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--2K67-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--2K87-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--3K01-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--3K4-108..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--3K16-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--3K32-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--3K57-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--3K65-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--3K74-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--3K83-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--3K92-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--4K02-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--4K22-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--4K42-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--4K53-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--4K75-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--4K99-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--5K9-108..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--5K11-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--5K23-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--5K62-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--6K04-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--6K49-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--6K81-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--7K15-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--7K32-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--7K68-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--7K87-10..> 14-Dec-2012 08:38 3.1K
RESIST.-0.1--8K06-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--8K25-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--8K45-10..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--9K31-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--9K53-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--10K-108..> 14-Dec-2012 08:40 3.1K
RESIST.-0.1--10K2-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--10K5-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--10R-108..> 14-Dec-2012 08:41 3.1K
RESIST.-0.1--10R2-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--10R5-10..> 14-Dec-2012 08:42 3.1K
RESIST.-0.1--11K-108..> 14-Dec-2012 08:40 3.1K
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Page 1 Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. PCN# Issue Date Description 05A-12 February 27, 2012 Initial release 05B-12 February 25, 2013 Removing the Shipping Box/Label Change (2b) The return address on all boxes will now be Lattice Singapore Pte. Ltd. February 25, 2013 Subject: PCN# 05B-12 Notification of Change in Lattice Logo affecting Device Topside Mark and Shipping Box/Label Design Dear Lattice Customer, Lattice is providing this notification of our intent to change the Lattice logo. The logo change is part of a rebranding effort at Lattice and will result in changes to topside marking on most devices as well as changes to all shipping boxes/labels. The conversion to the new device topside mark, shipping boxes/labels will be a gradual transition until existing inventories have been exhausted. Shown below are images of current and new Lattice logos. A description of each of the changes follows: 1. Device Topside Marking: The device topside marking on most Lattice products will now carry the new Lattice logo in one of the formats listed below depending on package size constraints. A list of all current logo formats and corresponding new logo formats can be found in Exhibit “A”. Custom device topside marks which utilize the current Lattice logo will also transition to the new logo. A comparison of device topside marks using the current and new logos in the full and short formats are shown below. Full Form Logo Device Topside Mark Example LCMXO2-7000ZE 1FG484I DATECODE LCMXO2-7000ZE 1FG484I DATECODE Current Logo on Device Topside Mark New Logo on Device Topside Mark PCN#05B-12 issued on February 25, 2013 will supersede PCN#05A-12 issued on February 27, 2012. Page 2 Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. Short Form Logo Device Topside Mark Eaxmple 2. Shipping Box/Label Changes: a. The color of the shipping boxes will change from white to brown and carry the new logo b. A patent statement will be added c. Elimination of phrases such as “Silicon Forest”, “ISP Products” and “LSC Products” d. All standard Lattice labels will incorporate the new logo Physical dimensions and properties of the boxes are unchanged. Shown below are the current and new logos in the full and short forms as they would appear on shipping boxes/labels. Logo Format Current Logo New Logo Full Form Short Form TIMING This change is effective immediately. As mentioned earlier, specific conversions will be a function of existing inventories. RESPONSE No response is required. Lattice PCNs are available on the Lattice website. Please sign up to receive e-mail PCN alerts by registering here. If you already have a Lattice web account and wish to receive PCN alerts, you can do so by logging into your account and making edits to your subscription options. New Logo on Device Topside Mark Current Logo on Device Topside Mark LC4032ZE 5MN-7I DATECODE LC4032ZE 5MN-7I DATECODEPage 3 Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies. CONTACT If you have any questions or require additional information, please contact pcn@latticesemi.com. Sincerely, Lattice Semiconductor PCN Administration Page 4 EXHIBIT “A” – CURRENT AND NEW LOGO FORMATS Current Logo Format New Logo FormatPage 5 Current Logo Format New Logo Format No change No change 5555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347 Internet: http:///www.latticesemi.com Rev. Q March 7, 2013 Registration, Evaluation, Authorisation and Restriction of Chemicals (REACH) REACH is a European Community Regulation on chemicals and their safe use (EC 1907/2006). It deals with the Registration, Evaluation, Authorisation and Restriction of CHemical substances. The law entered into force on 1 June 2007. The aim of REACH is to improve the protection of human health and the environment through the better and earlier identification of the intrinsic properties of chemical substances. More information may be found at http://ec.europa.eu/environment/chemicals/reach/reach_intro.htm. Lattice is a supplier of “articles” as defined in REACH. The “substances” contained in these articles are not intentionally released, nor do the articles contain any of the substances on the updated SVHC Candidate List of 138 substances published on December 19, 2012: # Substance Name CAS # SVHC Published Date 1 4,4'- Diaminodiphenylmethane (MDA) 101-77-9 10/28/2008 2 5-tert-butyl-2,4,6-trinitro-m-xylene (musk xylene) 81-15-2 10/28/2008 3 Alkanes, C10-13, chloro (Short Chain Chlorinated Paraffins) 85535-84-8 10/28/2008 4 Anthracene 120-12-7 10/28/2008 5 Benzyl butyl phthalate (BBP) 85-68-7 10/28/2008 6 Bis (2-ethylhexyl)phthalate (DEHP) 117-81-7 10/28/2008 7 Bis(tributyltin)oxide (TBTO) 56-35-9 10/28/2008 8 Cobalt dichloride 7646-79-9 10/28/2008 6/20/2011 9 Diarsenic pentaoxide 1303-28-2 10/28/2008 10 Diarsenic trioxide 1327-53-3 10/28/2008 11 Dibutyl phthalate (DBP) 84-74-2 10/28/2008 12 Hexabromocyclododecane (HBCDD) and all major diastereoisomers identified: 25637-99-4 10/28/2008 Alpha-hexabromocyclododecane 3194-55-6 Beta-hexabromocyclododecane (134237-50-6) Gamma-hexabromocyclododecane (134237-51-7) (134237-52-8) 13 Lead hydrogen arsenate 7784-40-9 10/28/2008 14 Sodium dichromate 7789-12-0 10/28/2008 10588-01-9 15 Triethyl arsenate 15606-95-8 10/28/2008 16 2,4-Dinitrotoluene 121-14-2 1/13/20105555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347 Internet: http:///www.latticesemi.com Rev. Q 17 Anthracene oil 90640-80-5 1/13/2010 18 Anthracene oil, anthracene paste 90640-81-6 1/13/2010 19 Anthracene oil, anthracene paste, anthracene fraction 91995-15-2 1/13/2010 20 Anthracene oil, anthracene paste,distn. lights 91995-17-4 1/13/2010 21 Anthracene oil, anthracene-low 90640-82-7 1/13/2010 22 Diisobutyl phthalate 84-69-5 1/13/2010 23 Lead chromate 7758-97-6 1/13/2010 24 Lead chromate molybdate sulphate red (C.I. Pigment Red 104) 12656-85-8 1/13/2010 25 Lead sulfochromate yellow (C.I. Pigment Yellow 34) 1344-37-2 1/13/2010 26 Pitch, coal tar, high temp. 65996-93-2 1/13/2010 27 Tris(2-chloroethyl)phosphate 115-96-8 1/13/2010 28 Acrylamide 79-06-1 3/30/2010 29 Ammonium dichromate 7789-09-5 6/18/2010 30 Boric acid 10043-35-3 6/18/2010 11113-50-1 31 Disodium tetraborate, anhydrous 1303-96-4 1330-43-4 6/18/2010 12179-04-3 32 Potassium chromate 7789-00-6 6/18/2010 33 Potassium dichromate 7778-50-9 6/18/2010 34 Sodium chromate 7775-11-3 6/18/2010 35 Tetraboron disodium heptaoxide, hydrate 12267-73-1 6/18/2010 36 Trichloroethylene 79-01-6 6/18/2010 37 2-Ethoxyethanol 110-80-5 12/15/2010 38 2-Methoxyethanol 109-86-4 12/15/2010 39 Chromic acid, 7738-94-5 Oligomers of chromic acid and dichromic acid, - 12/15/2010 Dichromic acid 13530-68-2 40 Chromium trioxide 1333-82-0 12/15/2010 41 Cobalt(II) carbonate 513-79-1 12/15/2010 42 Cobalt(II) diacetate 71-48-7 12/15/2010 43 Cobalt(II) dinitrate 10141-05-6 12/15/2010 44 Cobalt(II) sulphate 10124-43-3 12/15/2010 45 1,2,3-Trichloropropane 96-18-4 6/20/2011 46 1,2-Benzenedicarboxylic acid, di-C6-8-branched alkyl esters, C7-rich 71888-89-6 6/20/2011 47 1,2-Benzenedicarboxylic acid, di-C7-11- branched and linear alkyl esters 68515-42-4 6/20/20115555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347 Internet: http:///www.latticesemi.com Rev. Q 48 1-Methyl-2-pyrrolidone 872-50-4 6/20/2011 49 2-Ethoxyethyl acetate 111-15-9 6/20/2011 50 Hydrazine 302-01-2 6/20/2011 7803-57-8 51 Strontium chromate 7789-06-2 6/20/2011 52 Dichromium tris(chromate) 24613-89-6 12/19/2011 53 Potassium hydroxyoctaoxodizincatedi-chromate 11103-86-9 12/19/2011 54 Pentazinc chromate octahydroxide 49663-84-5 12/19/2011 55 Aluminosilicate Refractory Ceramic Fibres (RCF) - 12/19/2011 56 Zirconia Aluminosilicate Refractory Ceramic Fibres (Zr-RCF) - 12/19/2011 57 Formaldehyde, oligomeric reaction products with aniline (technical MDA) 25214-70-4 12/19/2011 58 Bis(2-methoxyethyl) phthalate 117-82-8 12/19/2011 59 2-Methoxyaniline; o-Anisidine 90-04-0 12/19/2011 60 4-(1,1,3,3-tetramethyl butyl)phenol, (4-tertOctylphenol) 140-66-9 12/19/2011 61 1,2-Dichloroethane 107-06-2 12/19/2011 62 Bis(2-methoxyethyl) ether 111-96-6 12/19/2011 63 Arsenic acid 7778-39-4 12/19/2011 64 Calcium arsenate 7778-44-1 12/19/2011 65 Trilead diarsenate 3687-31-8 12/19/2011 66 N,N-dimethylacetamide (DMAC) 127-19-5 12/19/2011 67 2,2'-dichloro-4,4'-methylenedianiline (MOCA) 101-14-4 12/19/2011 68 Phenolphthalein 77-09-8 12/19/2011 69 Lead azide, Lead diazide 13424-46-9 12/19/2011 70 Lead styphnate 15245-44-0 12/19/2011 71 Lead dipicrate 6477-64-1 12/19/2011 72 α,α-Bis[4-(dimethylamino)phenyl]-4 (phenylamino)naphthalene-1-methanol 6786-83-0 6/18/2012 (C.I. Solvent Blue 4) 73 N,N,N',N'-tetramethyl-4,4'-methylenedianiline (Michler's base) 101-61-1 6/18/2012 74 β-TGIC (1,3,5-tris[(2S and 2R)-2,3- epoxypropyl]-1,3,5-triazine-2,4,6-(1H,3H,5H)- trione) 59653-74-6 6/18/2012 75 Diboron trioxide 1303-86-2 6/18/2012 76 1,2-bis(2-methoxyethoxy)ethane (TEGDME; triglyme) 112-49-2 6/18/2012 77 4,4'-bis(dimethylamino)-4''-(methylamino)trityl alcohol 561-41-1 6/18/20125555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347 Internet: http:///www.latticesemi.com Rev. Q 78 Lead(II) bis(methanesulfonate) 17570-76-2 6/18/2012 79 Formamide 75-12-7 6/18/2012 80 [4-[4,4'-bis(dimethylamino) benzhydrylidene]cyclohexa-2,5-dien-1- ylidene]dimethylammonium chloride 548-62-9 6/18/2012 81 1,2-dimethoxyethane; ethylene glycol dimethyl ether (EGDME) 110-71-4 6/18/2012 82 [4-[[4-anilino-1-naphthyl][4- (dimethylamino)phenyl]methylene]cyclohexa- 2,5-dien-1-ylidene] dimethylammonium chloride 2580-56-5 6/18/2012 83 TGIC (1,3,5-tris(oxiranylmethyl)-1,3,5-triazine- 2,4,6(1H,3H,5H)-trione) 2451-62-9 6/18/2012 84 4,4'-bis(dimethylamino)benzophenone 90-94-8 6/18/2012 (Michler's ketone) 85 Bis(pentabromophenyl) ether (decabromodiphenyl ether; DecaBDE) 1163-19-5 12/19/2012 86 Pentacosafluorotridecanoic acid 72629-94-8 12/19/2012 87 Tricosafluorododecanoic acid 307-55-1 12/19/2012 88 Henicosafluoroundecanoic acid 2058-94-8 12/19/2012 89 Heptacosafluorotetradecanoic acid 376-06-7 12/19/2012 90 Diazene-1,2-dicarboxamide (C,C'- azodi(formamide)) 123-77-3 12/19/2012 91 Cyclohexane-1,2-dicarboxylic anhydride [1] 85-42-7, 13149-00-3, 14166-21-3 12/19/2012 cis-cyclohexane-1,2-dicarboxylic anhydride [2] trans-cyclohexane-1,2-dicarboxylic anhydride [3] [The individual cis- [2] and trans- [3] isomer substances and all possible combinations of the cis- and trans-isomers [1] are covered by this entry]. 92 Hexahydromethylphthalic anhydride [1], 25550-51-0, 19438-60-9, 48122-14-1, 57110-29-9 12/19/2012 Hexahydro-4-methylphthalic anhydride [2], Hexahydro-1-methylphthalic anhydride [3], Hexahydro-3-methylphthalic anhydride [4] [The individual isomers [2], [3] and [4] (including their cis- and trans- stereo isomeric forms) and all possible combinations of the isomers [1] are covered by this entry] 93 4-Nonylphenol, branched and linear - 12/19/2012 [substances with a linear and/or branched alkyl chain with a carbon number of 9 covalently bound in position 4 to phenol, covering also UVCB- and well-defined substances which include any of the individual isomers or a combination thereof] 5555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347 Internet: http:///www.latticesemi.com Rev. Q 94 4-(1,1,3,3-tetramethylbutyl)phenol, ethoxylated [covering well-defined substances and UVCB - 12/19/2012 substances, polymers and homologues] 95 Methoxyacetic acid 625-45-6 12/19/2012 96 N,N-dimethylformamide 68-12-2 12/19/2012 97 Dibutyltin dichloride (DBTC) 683-18-1 12/19/2012 98 Lead monoxide (Lead oxide) 1317-36-8 12/19/2012 99 Orange lead (Lead tetroxide) 1314-41-6 12/19/2012 100 Lead bis(tetrafluoroborate) 13814-96-5 12/19/2012 101 Trilead bis(carbonate)dihydroxide 1319-46-6 12/19/2012 102 Lead titanium trioxide 12060-00-3 12/19/2012 103 Lead titanium zirconium oxide 12626-81-2 12/19/2012 104 Silicic acid, lead salt 11120-22-2 12/19/2012 105 Silicic acid (H2Si2O5), barium salt (1:1), leaddoped 68784-75-8 12/19/2012 [with lead (Pb) content above the applicable generic concentration limit for 'toxicity for reproduction' Repr. 1A (CLP) or category 1 (DSD); the substance is a member of the group entry of lead compounds, with index number 082-001-00-6 in Regulation (EC) No 1272/2008] 106 1-bromopropane (n-propyl bromide) 106-94-5 12/19/2012 107 Methyloxirane (Propylene oxide) 75-56-9 12/19/2012 108 1,2-Benzenedicarboxylic acid, dipentylester, branched and linear 84777-06-0 12/19/2012 109 Diisopentylphthalate (DIPP) 605-50-5 12/19/2012 110 N-pentyl-isopentylphthalate 776297-69-9 12/19/2012 111 1,2-diethoxyethane 629-14-1 12/19/2012 112 Acetic acid, lead salt, basic 51404-69-4 12/19/2012 113 Lead oxide sulfate 12036-76-9 12/19/2012 114 [Phthalato(2-)]dioxotrilead 69011-06-9 12/19/2012 115 Dioxobis(stearato)trilead 12578-12-0 12/19/2012 116 Fatty acids, C16-18, lead salts 91031-62-8 12/19/2012 117 Lead cynamidate 20837-86-9 12/19/2012 118 Lead dinitrate 10099-74-8 12/19/2012 119 Pentalead tetraoxide sulphate 12065-90-6 12/19/2012 120 Pyrochlore, antimony lead yellow 8012-00-8 12/19/2012 121 Sulfurous acid, lead salt, dibasic 62229-08-7 12/19/2012 122 Tetraethyllead 78-00-2 12/19/2012 123 Tetralead trioxide sulphate 12202-17-4 12/19/2012 124 Trilead dioxide phosphonate 12141-20-7 12/19/2012 125 Furan 110-00-9 12/19/20125555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347 Internet: http:///www.latticesemi.com Rev. Q 126 Diethyl sulphate 64-67-5 12/19/2012 127 Dimethyl sulphate 77-78-1 12/19/2012 128 3-ethyl-2-methyl-2-(3-methylbutyl)-1,3- oxazolidine 143860-04-2 12/19/2012 129 Dinoseb (6-sec-butyl-2,4-dinitrophenol) 88-85-7 12/19/2012 130 4,4'-methylenedi-o-toluidine 838-88-0 12/19/2012 131 4,4'-oxydianiline and its salts 101-80-4 12/19/2012 132 4-aminoazobenzene 60-09-3 12/19/2012 133 4-methyl-m-phenylenediamine (toluene-2,4- diamine) 95-80-7 12/19/2012 134 6-methoxy-m-toluidine (p-cresidine) 120-71-8 12/19/2012 135 Biphenyl-4-ylamine 92-67-1 12/19/2012 136 o-aminoazotoluene [(4-o-tolylazo-o-toluidine)] 97-56-3 12/19/2012 137 o-toluidine 95-53-4 12/19/2012 138 N-methylacetamide 79-16-3 12/19/2012 While our products do not currently fall within the scope of REACH’s registration requirement, we continue to monitor the EU regulation for changes that may require our attention. Lattice is fully supportive of the various industry efforts throughout the world to phase out the use of undesirable elements from electronic equipment materials and manufacturing processes. Lattice remains committed to continually reducing its impact on the world's natural environment, and we work closely with our customers and suppliers to identify and rapidly eliminate hazardous substances from our products. Be assured that your business is greatly valued by Lattice Semiconductor and that we will do everything within our power to provide you with the highest level of service and support and with the broadest portfolio of high performance Field Programmable Gate Arrays (FPGAs), Field Programmable System Chips (FPSCs), ispPAC Mixed Signal devices and high-performance ISPTM programmable logic devices (PLDs). Regards, Chris Leonhard Sr. Customer Requirements Administrator Lattice Semiconductor Corp. custreq@latticesemi.com LatticeSC Family Data Sheet Version 01.0, February 2006February 2006 Preliminary Data Sheet © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 Introduction_01.0 Features ■ High Performance FPGA Fabric • 15K to 115K four input Look-up Tables (LUT4s) • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks ■ 8 to 32 High Speed SERDES and flexiPCS™ (per Device) • Performance ranging from 622Mbps to 3.4Gbps • Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) • Low Tx jitter (0.29UI at 3.125Gbps) • Built-in Pre-emphasis and equalization • Low power (typically 100mW per channel) • Embedded Physical Coding Sublayer (PCS) provides pre-engineered implementation for the following standards: – GbE, XAUI, PCI Express, SONET, Serial RapidIO, 1G Fibre Channel, 2G Fibre Channel ■ 2Gbps High Performance PURESPEED™ I/O • Supports the following performance bandwidths – Differential I/O up to 2Gbps DDR (1GHz Clock) – Single-ended memory interfaces up to 800Mbps • 144 Tap programable Input Delay (INDEL) block on every I/O dynamically aligns data to clock for robust performance – Dynamic bit Adaptive Input Logic (AIL) monitoring and control circuitry per pin that automatically ensures proper set-up and hold – Dynamic bus: uses control bus from DLL – Static per bit • Electrical standards supported: – LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL – SSTL 3/2/18 I, II; HSTL 18/15 I, II – PCI, PCI-X – LVDS, Mini-LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS, Hypertransport • Programmable On Die Termination (ODT) – Includes Thevenin Equivalent and low power VTT termination options ■ Memory Intensive FPGA • sysMEM™ embedded Block RAM – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM – 500MHz performance • Additional 240K to 1.8Mbits distributed RAM ■ sysCLOCK™ Network • Eight analog PLLs per device – Frequency range from 15MHz to 1GHz – Spread spectrum support • 12 DLLs per device with direct control of I/O delay – Frequency range from 100MHz to 700MHz • Extensive clocking network – 700MHz primary and 325 MHz secondary clocks – 1GHz I/O-connected edge clocks • Precision Clock Divider – Phase matched x2 and x4 division of incoming clocks • Dynamic Clock Select (DCS) – Glitch free clock MUX ■ Masked Array for Cost Optimization (MACO™) Blocks • On-chip structured ASIC Blocks provide preengineered IP for low power, low cost system level integration ■ High Performance System Bus • Ties FPGA elements together with a standard bus framework – Connects to peripheral user interfaces for run-time dynamic configuration ■ System Level Support • IEEE standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer • IEEE Standard 1532 in-system configuration • 1.2V and 1.0V operation • Onboard oscillator for initialization and general use • Embedded PowerPC microprocessor interface • Low cost wire-bond and high pin count flip-chip packaging • Low cost SPI Flash RAM configuration LatticeSC Family Data Sheet IntroductionIntroduction Lattice Semiconductor LatticeSC Family Data Sheet 1-2 Table 1-1. LatticeSC Family Selection Guide The LatticeSCM devices add MACO-enabled IP functionality to the base LatticeSC devices. Table 1-2 shows the type and number of each pre-engineered IP core. Table 1-2. LatticeSCM Family – Current Introduction The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a state of the art technology to provide one of the highest performing FPGAs in the industry. This family of devices includes features to meet the needs of today’s communication network systems. These features include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, HyperTransport, SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift PLLs, numerous DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs. High speed, high bandwidth I/O make this family ideal for high throughput systems. The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and backannotates it into the design for timing verification. Device SC15 SC25 SC40 SC80 SC115 LUT4s (K) 15.2 25.4 40.4 80.1 115.2 sysMEM Blocks (18Kb) 56 104 216 308 424 Embedded Memory (Mbits) 1.03 1.92 3.98 5.68 7.8 Max. Distributed Memory (Mbits) 0.24 0.41 0.65 1.28 1.84 Number of 3.4G SERDES (Max.) 8 16 16 32 32 DLLs 12 12 12 12 12 Analog PLLs 88888 MACO Blocks 4 6 10 10 12 Package I/O/SERDES Combinations (1mm ball pitch) 256-ball fpBGA (17 x 17mm) 139/4 900-ball fpBGA (31 x 31mm) 300/8 378/8 1020-ball ffBGA (33 x 33mm) 484/16 562/16 1152-ball fcBGA (35 x 35mm) 660/16 660/16 1704-ball fcBGA (42.5 x 42.5mm) 904/32 942/32 Device SCM15 SCM25 SCM40 SCM80 SCM115 flexiMAC Blocks • 1GbE Mode • 10GbE Mode • PCI Express Mode 12224 SPI4.2 Blocks 12222 Memory Controller Blocks • DDR1 DRAM Mode • DDR2 DRAM Mode • QDR2 SRAM Mode 12222Introduction Lattice Semiconductor LatticeSC Family Data Sheet 1-3 Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s leading edge systems designs. Table 1-3 details the performance of several common functions implemented within the LatticeSC. Table1-3. Speed Performance for Typical Functions1 Functions Performance (MHz)2 32-bit Address Decoder 455 64-bit Address Decoder 405 32:1 Multiplexer 507 64-bit Adder (ripple) 325 32x8 Distributed Single Port (SP) RAM 748 64-bit Counter (up or down counter, non-loadable) 355 True Dual-Port 1024x18 bits 359 FIFO Port A: x36 bits, B: x9 bits 361 1. For additional information, see Typical Building BLock Function Performance table in this data sheet. 2. Advance information (-7 speed grade).February 2006 Preliminary Data Sheet © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 Architecture_01.0 Architecture Overview The LatticeSC architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR). The upper left and upper right corners of the devices contain SERDES blocks and their associated PCS blocks, as show in Figure 2-1. Top left and top right corner of the device contain blocks of SERDES. Each block of SERDES contains four channels (quad). Each channel contains a single serializer and de-serializer, synchronization and word alignment logic. The SERDES quad connects with Physical Coding Sub-layer (PCS) block that contain logic to simultaneously perform alignment, coding, de-coding and other functions. The SERDES quad block has separate supply, ground and reference voltage pins. The PICs contain logic to facilitate the conditioning of signals to and from the I/O before they leave or enter the FPGA fabric. The block provides DDR and shift register capabilities that act as a gearbox between high speed I/O and the FPGA fabric. The blocks also contain programmable Adaptive Input Logic that adjusts the delay applied to signals as they enter the device to optimize setup and hold times and ensure robust performance. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM, ROM or FIFO. These blocks have dedicated logic to simplify the implementation of FIFOs. The PFU, PIC and EBR blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. These blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. The corners contain the sysCLOCK Analog Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Blocks. The PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeSC architecture provides eight analog PLLs per device and 12 DLLs. The DLLs provide a simple delay capability and can also be used to calibrate other delays within the device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™ port which allows for serial or parallel device configuration. The system bus simplifies the connections of the external microprocessor to the device for tasks such as SERDES and PCS configuration or interface to the general FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible. LatticeSC Family Data Sheet Architecture2-2 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-1. Simplified Block Diagram (Top Level) Programmable Function Unit (PFU) sysMEM Embedded Block RAM (EBR) Structured ASIC Block (MACO) Quad SERDES Physical Coding Sublayer (PCS) Quad SERDES Programmable I/O Cell (PIC) includes PURESPEED I/O Interface sysCLOCK Analog PLLs sysCLOCK DLLs sysCLOCK Analog PLLs sysCLOCK DLLs Each PIC contains four Programmable I/Os (PIO) Three PICs per four PFUs2-3 Architecture Lattice Semiconductor LatticeSC Family Data Sheet PFU Blocks The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-2. PFU Diagram Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6, LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. Slice 0 LUT4 & CARRY LUT4 & CARRY FF/ Latch D FF/ Latch D Slice 1 LUT4 & CARRY LUT4 & CARRY Slice 2 LUT4 & CARRY LUT4 & CARRY From Routing To Routing Slice 3 LUT4 & CARRY LUT4 & CARRY FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D2-4 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-3. Slice Diagram Table 2-1. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice Output Inter-PFU signal FCO For the right most PFU the fast carry chain output2 1. See Figure 2-2 for connection details. 2. Requires two PFUs. LUT4 & CARRY LUT4 & CARRY Slice A0 B0 C0 D0 FF/ Latch OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO F CE CLK LSR FF/ Latch OFX1 F1 Q1 F D D M1 To / From Different slice / PFU To / From Different slice / PFU LUT Expansion Mux M0 OFX0 From Routing To Routing Control Signals selected and inverted per slice in routing Note: some interslice signals not shown.2-5 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic Mode In this mode, the LUTs in each Slice are configured as combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices in the PFU. Ripple Mode Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: • Addition 2-bit • Subtraction 2-bit • Up counter 2-bit • Down counter 2-bit • Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the Slice. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the readonly port. For more information on RAM mode, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM ROM Mode The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. Logic Ripple RAM ROM PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SPR 16x2 DPR 16x2 ROM 16x1 SPR16x2 DPR16x2 Number of Slices 1 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM2-6 Architecture Lattice Semiconductor LatticeSC Family Data Sheet PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Routing There are many resources provided in the LatticeSC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU) resources. The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. All connections are buffered to ensure high-speed operation even with long high-fanout connections. The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysCLOCK Network The LatticeSC devices have three distinct clock networks for use in distributing high-performance clocks within the device, primary clocks, secondary clocks and edge clocks. In addition to these dedicated clock networks, users are free to route clocks within the device using the general purpose routing. Figure 2-4 shows the clock resources available to each slice. Figure 2-4. Slice Clock Selection Primary Clock Sources LatticeSC devices have a wide variety of primary clock sources available. Primary clocks sources consists of the following: • Primary clock input pins • Edge clock input pins • Two outputs per DLL Logic Ripple RAM ROM LUT 4x8 or MUX 2x1 x 8 2-bit Add x 4 SPR 16x2 x 4 DPR 16x2 x 2 ROM 16x1 x 8 LUT 5x4 or MUX 4x1 x 4 2-bit Sub x 4 SPR 16x4 x 2 DPR 16x4 x 1 ROM 16x2 x 4 LUT 6x2 or MUX 8x1 x 2 2-bit Counter x 4 SPR 16x8 x 1 ROM 16x4 x 2 LUT 7x1 or MUX 16x1 x 1 2-bit Comp x 4 ROM 16x8 x1 Primary Clock Secondary Clock Routing Clock to Slice GND 12 6 Note: GND is available to switch off the network.2-7 Architecture Lattice Semiconductor LatticeSC Family Data Sheet • Two outputs per PLL • Clock divider outputs • Digital Clock Select (DCS) block outputs • Three outputs per SERDES quad Figure 2-5 shows the arrangement of the primary clock sources. Figure 2-5. Clock Sources Primary Clock Routing The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6 shows this clock routing. SERDES PLL DCS DCS DCS DCS DCS DCS DLL DLL DLL DLL DLL DLL DCS Primary/ Edge Clock PIOs DCS PLL PLL (3 per SERDES Channel) (3 per SERDES Channel) 4 8 24 24 Primary Clock Sources PLL PLL DLL DLL DLL DLL PLL DLL DLL PLL PLL SERDES Primary/ Edge Clock PIOs Edge Clock PIOs Clock Dividers Clock Dividers Clock Dividers Clock Dividers Clock Dividers Primary/ Edge Clock PIOs Primary/ Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs2-8 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-6. Per Quadrant Clock Selection Secondary Clocks In addition to the primary clock network and edge clocks the LatticeSC devices also contain a secondary clock network. Built of X6 style routing elements this secondary clock network is ideal for routing slower speed clock and control signals throughout the device preserving high-speed clock networks for the most timing critical signals. Edge Clocks LatticeSC devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per bank for the top and bottom of the device. The left and right sides have eight edge clocks per side for both banks located on that side. Figure 2-7 shows the arrangement of edge clocks. Edge clock resources can be driven from a variety of sources. Edge clock resources can be driven from: • Edge clock PIOs in the same bank • Primary clock PIOs in the same bank • Routing • Adjacent PLLs and DLLs • ELSR output from the clock divider 12 Primary Clock per Quadrants 12 feedlines per quadrants times 4 + 12 feedlines from upper and lower half 12 Primary Clocks 60 Primary Clock Sources GND 60 3 3 GND GND From Local Routing From Local Routing From Local Routing 60 60 3 Note: GND is available to switch off the network.2-9 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-7. Edge Clock Resources Precision Clock Divider Each set of edge clocks has four high-speed dividers associated with it. These are intended for generating a slower speed system clock from the high-speed edge clock. The block operates in a X2 or X4 mode and maintains a known phase relationship between the divided down clock and high-speed clock based on the release of its reset signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as primary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via the edge clock network and is used for the rest of the I/O gearing logic. Figure 2-8. Clock Divider Circuit Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is SERDES SERDES Bank 1 Bank 5 Bank 4 Bank 7 Bank 6 Bank 2 Bank 3 Edge clock S/R S/R S/R S/R Divided clock Clock derived from selected PIOs, PLLs and routing LSR Register chain to synchronize LSR to clock input ELSR2-10 Architecture Lattice Semiconductor LatticeSC Family Data Sheet toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-9 illustrates the DCS Block diagram. Figure 2-9. DCS Block Diagram Figure 2-10 shows timing waveforms for one of the DCS operating modes. The DCS block can be programmed to other modes. For more information on the DCS, please see details of additional technical documentation at the end of this data sheet. Figure 2-10. DCS Waveforms Clock Boosting There are programmable delays available in the clock signal paths in the PFU, PIC and EBR blocks. These allow setup and clock-to-output times to be traded to meet critical timing without slowing the system clock. If this feature is enabled then the design tool automatically uses these delays to improve timing performance. sysCLOCK Phase Locked Loops (PLLs) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider and two clock output dividers. The input divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. The Phase Select block can modify the phase of the clock signal if desired. The Spread Spectrum block supports the modulation of the PLL output frequency. This reduces the peak energy in the fundamental and its harmonics providing for lower EMI (Electro Magnetic Interference). The sysCLOCK PLL can be configured at power-up and then, if desired, reconfigured dynamically through the serial memory interface bus which connects with the on-chip system bus. For example, the user can select inputs, loop filters, divider setting, delay settings and phase shift settings. The user can also directly access the SMI bus through the routing. The PLL clock input, from pin or routing, feeds into an input divider. There are four sources of feedback signal to the feedback divider: from the clock net, directly from the voltage controlled oscillator (VCO) output, from the routing or DCS CLK0 CLK1 DCSOUT SEL CLK0 SEL DCSOUT CLK12-11 Architecture Lattice Semiconductor LatticeSC Family Data Sheet from an external pin. The signal from the input clock divider and the feedback divider are passed through the programmable delay before entering the phase frequency detector (PFD) unit. The output of this PFD is used to control the voltage controlled oscillator. There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram. Figure 2-11. PLL Diagram For more information on the PLL, please see details of additional technical documentation at the end of this data sheet. Digital Locked Loop (DLLs) In addition to PLLs, the LatticeSC devices have up to 12 DLLs per device. DLLs assist in the management of clocks and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input to output is important, for example forward clocked interfaces. PLLs are good for applications requiring the lowest output jitter or jitter filtering. All DLL outputs are routed as primary/edge clock sources. The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. LOCK output signal is asserted when the DLL is locked. The ALU HOLD signal setting allows users to freeze the DLL at its current delay setting. There is a Digital Control (DCNTL) bus available from the DLL block. This Digital Control bus is available to the delay lines in the PIC blocks in the adjacent banks. The UDDCNTL signal allows the user to latch the current value on the digital control bus. Figure 2-12 shows the DLL block diagram of the DLL inputs and outputs. The output of the phase frequency detector controls an arithmetic logic unit (ALU) to add or subract one delay tap. The digital output of this ALU is used to control the delay value of the delay chain and this digital code is transmitted via the DCNTL bus. The sysCLOCK DLL can be configured at power-up, then, if desired, reconfigured dynamically through the Serial Memory Interface bus which interfaces with the on-chip Microprocessor Interface (MPI) bus. In addition, users can drive the SMI interface from routing if desired. The user can configure the DLL for many common functions such as clock injection match and single delay cell. Lattice provides primitives in its design for time reference delay (DDR memory) and clock injection delay removal. CLKI CLKFB CLKOP CLKOS VCO/ Loop Filter Phase Adjust PFD LOCK Div Div Prog Delay Prog Delay Prog Delay Div Div Optional Internal Feedback RSTN From PFD2-12 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-12. DLL Diagram PLL/DLL Cascading The LatticeSC devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable combinations are as follows: • PLL to PLL Supported • PLL to DLL Supported • DLL to DLL Supported • DLL to PLL Not supported DLLs are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applications to utilize the unique benefits of both DLL and PLLs. For further information on the DLL, please see details of additional technical documentation at the end of this data sheet. sysMEM Memory Block The sysMEM block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing resources for flag generation. Each block can be used in a variety of depths and widths as shown in Table 2-5. Memory with ranges from x1 to x18 in all modes: single port, pseudo-dual port and FIFO also providing x36. CLKI CLKFB CLKOP CLKOS UDDCNTL ALUHOLD DCNTL Delay Chain ALU Duty50 Phase Adj Duty50 PFD DCNTL Gen LOCK Phase Adj RSTN2-13 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Table 2-5. sysMEM Block Configurations Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. A clock is required even in asynchronous read mode. The EBR memory supports three forms of write behavior for dual port operation: 1. Normal — data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. 2. Write Through — a copy of the input data appears at the output of the same port. 3. Read-Before-Write — when new data is being written, the old content of the address appears at the output. FIFO Configuration The FIFO has a write port with Data-in, WCE, WE and WCLK signals. There is a separate read port with Data-out, RCE, RE and RCLK signals. The FIFO internally generates Almost Full, Full, Almost Empty, and Empty Flags. The Full and Almost Full flags are registered with WCLK. The Empty and Almost Empty flags are registered with RCLK. The range of program values for these flags are in Table 2-6. Memory Mode Configurations Single Port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 True Dual Port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 Pseudo Dual Port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 FIFO 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 362-14 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Table 2-6. Programmable FIFO Flag Ranges The FIFO state machine supports two types of reset signals. The first reset signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in initial reset state. The second reset signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. Programmable I/O Cells (PIC) Each PIC contains four PIOs connected to their respective PURESPEED I/O Buffer which are then connected to the PADs as shown in Figure 2-13. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to PURESPEED I/O buffer, and receives input (DI) from the buffer. The PIO contains advanced capabilities to allow the support of speeds up to 2Gbps. These include dedicated shift and DDR logic and adaptive input logic. The dedicated resources simplify the design of robust interfaces. Flag Name Programming Range Full (FF) 1 to (up to 2N -1) Almost Full (AF) 1 to Full-1 Almost Empty (AE) 1 to Full-1 Empty (EF) 0 Note: N = Address bit width.2-15 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-13. PIC Diagram The A/B PIOs on the left and the right of the device can be paired to form a differentiated driver. The A/B and C/D PIOs on all sides of the device can be paired to form differential receivers. Either A or C PIOs on all sides except the one on top also contain an adaptive input logic capability that facilitates the implementation of high-speed interPIO B PADA TO DO DI "T" PADB “C” OPOS2 ONEG2 OPOS3 ONEG3 TD INCK INDD INFF IPOS0 INEG0 IPOS1 INEG1 IPOS2 INEG2 IPOS3 INEG3 RUNAIL LOCK UPDATE *AIL only on A or C pads located on the left, right and bottom of the device. CLK CE LSR GSRN HCLKOUT GSR LCLKOUT LSRO HCLKIN LCLKIN PIO A PURESPEED I/O Buffer Control Muxes CEO LSRO ELSR ECLK IOLT0 POS Update NEG Update DI DO Tristate Register Block Input Register Block (including delay and AIL elements*) Update Block Output Register Block PIO C PADC “T” PIO D PADD “C” OPOS0 ONEG0 OPOS1 ONEG12-16 Architecture Lattice Semiconductor LatticeSC Family Data Sheet faces in the LatticeSC devices. Figure 2-14 shows how differential receivers and drivers are arranged between PIOs. Figure 2-14. Differential Drivers and Receivers PIO The PIO contains five blocks: an input register block, output register block, tristate register block, update block, and a control logic block. These blocks contain registers for both single data rate (SDR), double data rate (DDR), and shift register operation along with the necessary clock and selection logic. Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-16 show the diagram of the input register block. The signal from the PURESPEED I/O buffer (DI) enters the input register block and can be used for three purposes, as a source for the combinatorial (INDD) and clock outputs (INCK), the input into the SDR register/latch block and the input to the delay block. The output of the delay block can be used as combinatorial (INDD) and clock (INCK) outputs, an input to the DDR/Shift Register Block or an input into the SDR register block. Input SDR Register/Latch Block The SDR register/latch block has a latch and a register/latch that can be used in a variety of combinations to provide a registered or latched output (INFF). The latch operates off high-speed input clocks and latches data on the positive going edge. The register/latch operates off the low-speed input clock and registers/latches data on the positive going edge. Both the latch and the register/latch have a clock enable input that is driven by the input clock enable. In addition both have a variety of programmable options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable. The register and latch LSR inputs are driven from LSRI, which is generated from the PIO control MUX. The GSR inputs are driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on a PIO basis. Input Delay Block The delay block uses 144 tapped delay lines to obtain coarse and fine delay resolution. These delays can be adjusted during configuration or automatically via DLL or AIL blocks. The Adaptive Input Logic (AIL) uses this delay block to adjust automatically the delay in the data path to ensure that it has sufficient setup and hold time. The delay line in this block matches the delay line that is used in the 12 on-chip DLLs. The delay line can be set via configuration bits or driven from a calibration bus that allows the setting to be controlled either from one of the onchip DLLs or user logic. Controlling the delay from one of the on-chip DLLs allow the delay to be calibrated to the DLL clock and hence compensated for the variations in process, voltage and temperature. PIO D PIO C PADC "T" PADD "C" PIO A PADA "T" PIO B PADB "C" *Differential Driver only available on right and left of the device.2-17 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Adaptive Input Logic (AIL) Block The AIL block is available in the A or C pads of each PIO on the left, right and bottom of the chip. This logic automatically adjusts the delay in the data path on a signal-by-signal basis to ensure that it has sufficient set-up and hold. This capability simplifies the system level design of high-speed interfaces and ultimately allows higher overall speeds to be achieved. The AIL block receives data from nine taps in the delay line present in the input delay block. These signals are fed to 18 registers. The registers operate off the high-speed input clock (9 on the positive edge and 9 on the negative edge.) The output of these registers, along with the high speed input clock and RUNAIL signal are inputs to the AIL control logic. If RUNAIL is enabled then the AIL control logic will determine if the delay needs to be adjusted in order to avoid data transitions within a user specified margin. The margin can be a specified as 2, 4, 6 or 8 delay increments. The LOCK output indicates that transitions are not occurring within the specified margin of the clock edge. The AIL logic is automatically configured by the Lattice design tools dependent on the primitives that are specified. Figure 2-15 shows the arrangement of the adaptive input logic. Figure 2-15. Adaptive Input Logic and Delay Block Input DDR/Shift Block The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the high-speed clock and the associated transfer to the low-speed clock domain. It functions as a gearbox allowing high-speed incoming data to be passed into the FPGA fabric. Each PIO supports DDR and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. The PIOs A and C on the left, right and bottom of the device also contain an optional Adaptive Input Logic (AIL) element. This logic automatically aligns incoming data with the clock allowing for easy design of high-speed interfaces. Figure 2-16 shows a simpliDelay tap n+16 Delay tap n+14 Delay tap n+12 Delay tap n+10 Delay tap n+8 Delay tap n+6 Delay tap n+4 Delay tap n+2 Delay tap n Delay Line (96 Steps) Coarse Select (47 Steps) Fine Select Mux From DLL or configuration bits Fine Select Muxes Delay Block To IOL DI from input buffer AIL Control Logic Delay tap n+16 Delay tap n+14 Delay tap n+12 Delay tap n+10 Delay tap n+8 Delay tap n+6 Delay tap n+4 Delay tap n+2 Delay tap n To DDR/Shift Register Block AIL Block HCLKIN RUNAIL LOCK 7-bit Control Bus2-18 Architecture Lattice Semiconductor LatticeSC Family Data Sheet fied block diagram of the shift register block. The shift block in conjunction with the update and clock divider blocks automatically handles the hand off between the low-speed and high-speed clock domains. Figure 2-16. Input Register Block1 DDR/Shift Register Block Optional Adaptive Input Logic2 • DDR • DDR + half clock • DDR + shift x1 • DDR + shift x2 • DDR + shift x43 • Shift x1 • Shift x2 • Shift x43 To Routing INFF INDD INCK IPOS0 CLKDISABLE CLKENABLE IPOS1 INEG0 INEG1 LCLKIN (ECLK/SCLK) HCLKIN (ECLK/SCLK) Latch D-Type/ Latch Delay Block LOCK RUNAIL DI (from PURESPEED I/O Buffer) DCNTL[0:8] (From DLL) 1. UPDATE, Set and Reset not shown for clarity 2. Adaptive input logic is only available in selected PIO 3. By four shift modes utilize DDR/shift register block from paired PIO. 4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used to disable any/all input signals to save power. SDR Register/Latch Block2-19 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-17. Input DDR/Shift Register Block Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of registers for DDR and shift register operation. The output signal (DO) can be derived directly from one of the inputs (bypass mode), the SDR register or the DDR/shift register block. Figure 2-18 shows the diagram of the Output Register Block. Output SDR Register/Latch Block The SDR register operates on the positive edge of the high-speed clock. It has clock enable that is driven by the clock enable output signal generated by the control MUX. In addition it has a variety of programmable options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control MUX. The GSR inputs is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on a PIO basis. Output DDR/Shift Block The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing low-speed parallel data from the FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. Figure 2-18 shows a simplified block diagram of the shift register block. Data Input (From Delay Block) HCLKIN LCLKIN POS Update IPOS0 (Can act as IPOS2 when paired) IPOS1 (Can act as IPOS3 when paired) INEG0 (Can act as INEG2 when paired) INEG1 (Can act as INEG3 when paired) NEG Update Used for DDR with Half Clock Transfer To paired PIO for wide muxing To paired PIO for wide muxing Bypass used for DDR Bypass used for DDR From paired PIO for wide muxing From paired PIO for wide muxing2-20 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-18. Output Register Block1 Figure 2-19. Output/Tristate DDR/Shift Register Block DDR/Shift Register Block • DDR • DDR + half clock • DDR + shift x2 • DDR + shift x42 • Shift x2 • Shift x42 Notes: 1. CE, Update, Set and Reset not shown for clarity. 2. By four shift modes utilizes DDR/Shift register block from paired PIO. 3. DDR/Shift register block shared with tristate block. HCLKOUT LCLKOUT OPOS0 From Routing To Tri-state Block DO (to PURESPEED I/O Buffer) From Control MUX ONEG0 OPOS1 ONEG1 SDR Register Bypass Used for DDR/DDRX Modes Shift x2 / x4 Output LCLKOUT HCLKOUT From paired PIO ( x4 shift modes) To paired PIO (x4 shift modes) POS Update OPOS0 (Can act as OPOS2 when paired) NEG Update OPOS1 (Can act as OPOS3 when paired) Bypass Used for DDR/DDRX Modes From paired PIO ( x4 shift modes) To paired PIO (x4 shift modes) ONEG0 (Can act as ONEG2 when paired) ONEG1 (Can act as ONEG3 when paired) TSDDR/DDRX ODDR/DDR/ X2/X42-21 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of three registers for DDR and shift register operation. The output signal tri-state control signal (TO) can be derived directly from one of the inputs (bypass mode), the SDR shift register, the DDR registers or the data associated with the buffer (for open drain emulation). Figure 2-20 shows the diagram of the Tristate Register Block. Tristate SDR Register/Latch Block The SDR register operates on the positive edge of the high-speed clock. In it has a variety of programmable options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control MUX. The GSR input is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on a PIO basis. Tristate DDR/Shift Register Block The DDR/Shift block is shared with the output block allowing DDR support using the high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing low–speed parallel data from the FPGA fabric to provide a high-speed tri-state control stream. There is a special mode for DDR-II memory interfaces where the termination is controlled by the output tristate signal. During WRITE cycle when the FPGA is driving the lines, the parallel terminations are turned off. During READ cycle when the FPGA is receiving data, the parallel terminations are turned on. Figure 2-20. Tristate Register Block1 Control Logic Block The control logic block allows the modification of control signals selected by the routing before they are used in the PIO. It can optionally invert all signals passing through it except the Global Set/Reset. Global Set/Reset can be enabled or disabled. It can route either the edge clock or the clock to the high-speed clock nets. The clock provided to the PIO by routing is used as the slow-speed clocks. In addition this block contains delays that can be inserted in the clock nets to enable Lattice’s unique cycle boosting capability. Update Block The update block is used to generate the POS update and NEG update signals used by the DDR/Shift register blocks within the PIO. Note the update block is only required in shift modes. This is required in order to do the high speed to low speed handoff. One of these update signals is also selected and output from the PIC as the signal UPDATE. It consists of a shift chain that operates off either the high-speed input or output clock. The values of each DDR/Shift Register Block2 • DDR • DDR + half clock HCLKOUT LCLKOUT From Routing TO (To PURESPEED I/O Buffer) From Control MUX From Output OPOS1 VCC GND TD ONEG1 Notes: 1. CE, Update, Set and Reset not shown for clarity. 2. DDR/Shift Register Block shared with output register block. 2-22 Architecture Lattice Semiconductor LatticeSC Family Data Sheet register in the chain are set or reset depending on the desired mode of operation. The set/reset signal is generated from either the edge reset ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically configure and connect the update block when one of the DDR or shift register primitives is used. Figure 2-21. Update Block PURESPEED I/O Buffer Each I/O is associated with a flexible buffer referred to as PURESPEED I/O buffer. These buffers are arranged around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. The availability of programmable on-chip termination for both input and output use, further enhances the utility of these buffers. PURESPEED I/O Buffer Banks LatticeSC devices have seven PURESPEED I/O buffer banks; each is capable of supporting multiple I/O standards. Each PURESPEED I/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and V REF2 resources allowing each bank to be completely independent from each other. Figure 2-22 shows the seven banks and their associated supplies. Table 2-7 lists the maximum number of I/Os per bank for the whole LatticeSC family. In the LatticeSC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI33 and PCIX33) are powered using VCCIO. In addition to the bank VCCIO supplies, the LatticeSC devices have a VCC core logic power supply, and a VCCAUX supply that power all differential and referenced buffers. VCCAUX also powers a predriver of single-ended output buffers to enhance buffer performance. Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the referenced input buffers. In the LatticeSC devices any I/O pin in a bank can be configured to be a dedicated reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages. Differential drivers have user selectable internal or external bias. External bias is brought in by the VREF1 pin in the bank. External bias for differential buffers is needed for applications that requires tighter than standard output common mode range. Since a bank can have only one external bias circuit for differential drivers, LVDS and RSDS differential outputs can be mixed in a bank but not with HYPT (HyperTransport). If a differential driver is configured in a bank, one pin in that bank becomes a DIFFR pin. This DIFFR pin must be connected to ground via an external 1K +/-1% ohm resistor. POS Update NEG Update HCLKUP ESLRUP LSRUP LCLKUP UPDATE ÷1/2/42-23 Architecture Lattice Semiconductor LatticeSC Family Data Sheet In addition, there are dedicated Terminating Supply (VTT) pins to be used as terminating voltage for one of the two ways to perform parallel terminations. These VTT pins are available in banks 2-7, these pins are not available in some packages. When these pins are not used they should be left unconnected. There are further restrictions on the use of VTT pins, for additional details refer to technical information at the end of this data sheet. Figure 2-22. LatticeSC Banks Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family The LatticeSC devices contain three types of PURESPEED I/O buffers: 1. Left and Right Sides (Banks 2, 3, 6 and 7) These buffers can support LVCMOS standards up to 2.5V. A differential driver is provided on all primary PIO pairs (A and B) and differential receivers are available on all pairs. Adaptive input logic is available on PIOs A or C. Device LFSC15 LFSC25 LFSC40 LFSC80 LFSC115 Bank1 104 80 136 80 136 Bank2 28 36 60 96 136 Bank3 60 84 96 132 156 Bank4 72 100 124 184 208 Bank5 72 100 124 184 208 Bank6 60 84 96 132 156 Bank7 28 36 60 96 136 Note: Not all the I/Os of the Banks are available in all the packages Bank 2 Bank 3 V REF1[7] GND Bank 7 V CCIO7 VTT7 V REF2[7] V REF1[6] GND V CCIO6 VTT6 V REF2[6] V REF1[2] GND V CCIO2 VTT2 V REF2[2] V REF1[5] V GND CCIO5 VTT5 V REF2[5] V REF1[4] V GND CCIO4 VTT4 V REF2[4] V REF2[1] GND V CCIO1 V REF1[1] V REF1[3] GND V CCIO3 VTT[3] Bank 6 V REF2[3] Bank 4 SERDES SERDES Bank 5 Bank 12-24 Architecture Lattice Semiconductor LatticeSC Family Data Sheet 2. Top Side (Bank 1) These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential receivers are provided on all PIO pairs but differential drivers are not available. Adaptive input logic is not available on this side. 3. Bottom Side (Banks 4 and 5) These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential receivers are provided on all PIO pairs but differential drivers are not available. Adaptive input logic is available on PIOs A or C. Table 2-8 lists the standards supported by each side. Table 2-8. I/O Standards Supported by Different Banks Supported Standards The LatticeSC PURESPEED I/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP-2X33. Differential standards supported include LVDS, RSDS, Description Top Side Banks 1 Right Side Banks 2-3 Bottom Side Banks 4-5 Left Side Banks 6-7 I/O Buffer Type Single-ended, Differential Receiver Single-ended, Differential Receiver and Driver Single-ended, Differential Receiver Single-ended, Differential Receiver and Driver Output Standards Supported LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I SSTL25_ I, II SSTL33_ I, II HSTL15_I, II, III1 , IV1 HSTL18_I, II,III1 , IV1 SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II PCI33 PCIX15 PCIX33 AGP1X33 AGP2X33 MLVDS/BLVDS GTL2 , GTL+2 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I SSTL25_ I, II HSTL15_I,III HSTL18_I,II,III PCIX15 SSTL18D_I, II SSTL25D_I, II HSTL15D_I, II HSTL18D_I, II LVDS/RSDS/HYPT Mini-LVDS MLVDS/BLVDS GTL2 , GTL+2 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I SSTL25_ I, II SSTL33_ I, II HSTL15_I, II, III1 , IV1 HSTL18_I, II,III1 , IV1 SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II PCI33 PCIX15 PCIX33 AGP1X33 AGP2X33 MLVDS/BLVDS GTL2 , GTL+2 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I SSTL25_ I, II HSTL15_I,III HSTL18_I,II,III PCIX15 SSTL18D_I, II SSTL25D_I, II HSTL15D_I, II HSTL18D_I, II LVDS/RSDS/HYPT Mini-LVDS MLVDS/BLVDS GTL2 , GTL+2 Input Standards Supported Single-ended, Differential Single-ended, Differential Single-ended, Differential Single-ended, Differential Clock Inputs Single-ended, Differential Single-ended, Differential Single-ended, Differential Single-ended, Differential Differential Output Support via Emulation LVDS/MLVDS/BLVDS/ LVPECL MLVDS/BLVDS/ LVPECL LVDS/MLVDS/BLVDS/ LVPECL MLVDS/BLVDS/ LVPECL AIL Support No Yes Yes Yes 1. Input only. 2. Input only. Outputs supported by bussing multiple outputs together.2-25 Architecture Lattice Semiconductor LatticeSC Family Data Sheet BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O standards (together with their supply and reference voltages) supported by the LatticeSC devices. The tables also provide the available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer to support a variety of standards please see details of additional technical documentation at the end of this data sheet. Table 2-9. Supported Input Standards Input Standard VREF (Nom.) VCCIO 1 (Nom.) On-chip Termination Single Ended Interfaces LVTTL333 — 3.3 None LVCMOS 33, 25, 18, 15, 123 — 3.3/2.5/1.8/1.5/1.2 None PCI33, PCIX33, AGP1X333 — 3.3 None PCIX15 0.75 1.52 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 AGP2X33 1.32 — None HSTL18_I, II 0.9 1.82 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 HSTL18_III, IV 1.08 1.82 None / VCCIO: 50 HSTL15_I, II 0.75 1.52 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 HSTL15_III, IV 0.9 1.52 None / VCCIO: 50 SSTL33_I, II 1.5 3.3 None SSTL25_I, II 1.25 2.52 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 SSTL18_I, II 0.9 1.82 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 GTL+, GTL 1.0 / 0.8 1.5 / 1.22 None / VCCIO: 50 Differential Interfaces SSTL18D_I, II — 1.82 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 SSTL25D_I, II — 2.52 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 SSTL33D_I, II — 3.3 None HSTL15D_I, II — 1.52 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 HSTL18D_I, II — 1.82 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 LVDS — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 Mini-LVDS — — None / Diff: 120, 150 / Diff to VCMT: 120, 150 BLVDS25 — — None MLVDS25 — — None HYPT (Hyper Transport) — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 RSDS — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 LVPECL33 — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 1. When not specified VCCIO can be set anywhere in the valid operating range. 2. VCCIO needed for on-chip termination to VCCIO/2 or VCCIO only. VCCIO is not specified for off-chip termination. 3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV.2-26 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Table 2-10. Supported Output Standards4 Output Standard Drive VCCIO (Nom) On-chip Output Termination Single-ended Interfaces LVTTL/D1 8mA, 16mA, 24mA 3.3 None. LVCMOS33/D1 8mA, 16mA, 24mA 3.3 None LVCMOS25/D1, 2 4mA, 8mA, 12mA, 16mA, 2.5 None, series: 25, 33, 50, 100 LVCMOS18/D1, 2 4mA, 8mA, 12mA, 16mA, 1.8 None, series: 25, 33, 50, 100 LVCMOS15/D1, 2 4mA, 8mA, 12mA, 16mA, 1.5 None, series: 25, 33, 50, 100 LVCMOS12/D1, 2 2mA, 4mA, 8mA, 12mA 1.2 None, series: 25, 33, 50, 100 PCIX15 N/A 1.5 None PCI33, PCIX33, AGP1X33, AGP2X33 N/A 3.3 None HSTL18_I N/A 1.8 None, series: 50 HSTL18_II N/A 1.8 None, series: 25, series + parallel to VCCIO/2: 25 + 60 HSTL15_I N/A 1.5 None, series: 50 HSTL15_II N/A 1.5 None, series: 25, series + parallel to VCCIO/2: 25 + 60 SSTL33_I N/A 3.3 None SSTL33_II N/A 3.3 None SSTL25_I N/A 2.5 None, series: 50 SSTL25_II N/A 2.5 None, series: 33, series + parallel to VCCIO/2: 33+ 60 SSTL18_ I N/A 1.8 None, series: 33 SSTL18_II N/A 1.8 None, series: 33, series + parallel to VCCIO/2: 33+ 60 Differential Interfaces SSTL18D_I N/A 1.8 None, series: 33 SSTL25D_I N/A 2.5 None, series: 50 SSTL18D_II, SSTL25D_II N/A 1.2/2.5/3.3 None, series: 33, series + parallel to VCCIO/2: 33+ 60 SSTL33D_I, II N/A 3.3 None HSTL15D_I, HSTL18D_I N/A 1.5/1.8 None, series: 50 HST15D_II, HSTL18D_II N/A 1.5/1.8 None, series: 25, series + parallel to VCCIO/2: 25 + 60 LVDS 2mA, 3.5mA, 4mA, 6mA 2.5 None Mini-LVDS 3.5mA, 4mA, 6mA 2.5 None BLVDS25 N/A 2.5 None MLVDS25 N/A 2.5 None LVPECL333 N/A 3.3 None HYPT (Hyper Transport) 3.5mA, 4mA, 6mA 2.5 None RSDS 2mA, 3.5mA, 4mA, 6mA 2.5 None 1. D refers to open drain capability. 2. User can select either drive current or driver impedances but not both. 3. Emulated with external resistors. 4. No GTL or GTL+ support.2-27 Architecture Lattice Semiconductor LatticeSC Family Data Sheet PCI Clamp A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned “ON” or “OFF” on each pin independently. The PCI clamp is used when implementing a 3.3V PCI interface. The PCI Specification, Revision 2.2 requires the use of clamping diodes for 3.3V operation. For more information on the PCI interface, please refer to the PCI Specification, Revision 2.2. Programmable Slew Rate Control All output and bidirectional buffers have an optional programmable output slew rate control that can be configured for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling edges. Programmable Termination Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both. The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete components required on the circuit board. The termination schemes can be split into two categories single-ended and differential. Single Ended Termination Single Ended Outputs: The SC devices support a number of different terminations for single ended outputs: • Series • Parallel to VCCIO or GND • Parallel to VCCIO/2 • Parallel to VCCIO/2 combined with series Figure 2-23 shows the single ended output schemes that are supported. The nominal values of the termination resistors are shown in Table 2-10.2-28 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-23. Output Termination Schemes Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution Series termination (controlled output impedance) Parallel termination to V CCIO, or parallel driving end Combined series + parallel termination to V CCIO/2 at driving end (only series termination moved on-chip) Combined series + parallel to VCCIO/2 driving end Parallel termination to V CCIO/2 driving end ON-chip Zo Zo Zo OFF-chip OFF-chip ON-chip ON-chip Zo OFF-chip ON-chip VCCIO or GND VCCIO or GND Zo Zo Zo OFF-chip Zo Rs Rs Rs ON-chip OFF-chip Zo ON-chip OFF-chip Zo ON-chip VCCIO/2 Zo Zo OFF-chip VCCIO/2 Zo ON-chip Zo OFF-chip Rs VCCIO/2 Zo VCCIO/2 Zo VCCIO GND 2Zo 2Zo ON-chip OFF-chip Zo VCCIO GND 2Zo 2Zo ON-chip OFF-chip Zo2-29 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs: • Parallel to VCCIO or GND • Parallel to VCCIO/2 • Parallel to VTT Figure 2-24 shows the single ended input schemes that are supported. The nominal values of the termination resistors are shown in Table 2-9. Figure 2-24. Input Termination Schemes In many situations designers can chose whether to use Thevenin or parallel to VTT termination. The Thevenin approach has the benefit of not requiring a termination voltage to be applied to the device. The parallel to VTT approach consumes less power. VTT Termination Resources Each I/O bank, except bank 1, has a number of VTT pins that must be connected if VTT is used. Note VTT pins can sink or source current and the power supply they are connected to must be able to handle the relatively high currents associated with the termination circuits. Note: VTT is not available in all package styles. On-chip parallel termination to VTT is supported at the receiving end only. On-chip parallel output termination to VTT is not supported. The VTT internal bus is also connected to the internal VCMT node. Thus in one bank designers can implement either VTT termination or VCMT termination for differential inputs. DDRII/RLDRAMII Termination Support The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to VTT be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required circuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet. Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution Parallel termination to V CCIO/2 receiving end Parallel termination to to VCCIO, or parallel to GND receiving end VCCIO or GND OFF-chip ON-chip Zo Zo VCCIO2 OFF-chip ON-chip Zo Zo VTT OFF-chip ON-chip Zo Zo OFF-chip ON-chip Zo VTT Zo VCCIO or GND OFF-chip ON-chip Zo Zo VCCIO GND OFF-chip ON-chip 2Zo 2Zo Zo Parallel termination to VTT at receiving end2-30 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Differential Input Termination The LatticeSC device allows two types of differential termination. The first is a single resistor across the differential inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus VCMT. The VCMT bus is DC-coupled through an internal capacitor to ground. Figure 2-25 shows the differential termination schemes and Table 2-9 shows the nominal values of the termination resistors. Figure 2-25. Differential Termination Scheme Calibration There are two calibration sources that are associated with the termination scheme used in the LatticeSC devices: • DIFFR – This pin occurs in each bank and must be connected through a 1K+/-1% resistor to ground if differential outputs are used. • XRES – There is one of these pins per device. It is used for several functions including calibrating on-chip termination. This pin should always be connected through a 1K+/-1% resistor to ground. The LatticeSC devices support two modes of calibration: • Continuous – In this mode the SC devices continually calibrate the termination resistances. Calibration happens several times a second. Using this mode ensures that termination resistances remain calibrated as the silicon junction temperature changes. • User Request – In this mode the calibration circuit operates continuously. However, the termination resistor values are only updated on the assertion of the calibration_update signal available to the core logic. For more information on calibration, refer to the details of additional technical documentation at the end of this data sheet. Hot Socketing The LatticeSC devices have been carefully designed to ensure predictable behavior during power-up and powerdown. To ensure proper power sequencing, care must be taken during power-up and power-down as described below. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits, Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution Differential termination Differential and common mode termination OFF-chip ON-chip + - 2Zo Zo Zo OFF-chip ON-chip GND + - Zo Zo Zo Zo OFF-chip ON-chip + - 2Zo Zo Zo OFF-chip ON-chip GND VCMT + - Zo Zo Zo Zo2-31 Architecture Lattice Semiconductor LatticeSC Family Data Sheet this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many multiple power supply and hot-swap applications. Power-Up Requirements To prevent high power supply and input pin currents, each VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies must have a monotonic ramp up time of 75 ms or less to reach its minimum operating voltage. Apart from VCC and VCC12, which have an additional requirement, and VCCIO and VCCAUX, which also have an additional requirement, the VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies can ramp up in any order, with no restriction on the time between them. However, the ramp time for each must be 75 ms or less. Configuration of the device will not proceed until the last power supply has reached its minimum operating voltage. Additional Requirement for VCC and VCC12 VCC12 must always be higher than VCC. This condition must be maintained at ALL times, including during powerup and power-down. Note that for 1.2V only operation, it is advisable to source both of these supplies from the same power supply. Additional Requirement for VCCIO and VCCAUX If any VCCIOs are 1.2/1.5/1.8V, then VCCAUX MUST be applied before them. If any VCCIO is 1.2/1.5/1.8V and is powered up before VCCAUX, then when VCCAUX is powered up, it may drag VCCIO up with it as it crosses through the VCCIO value. (Note: If the VCCIO supply is capable of sinking current, as well as the more usual sourcing capability, this behavior is eliminated. However, the amount of current that the supply needs to sink is unknown and is likely to be in the hundreds of milliamps range). Power-Down Requirements To prevent high power supply and input pin currents, power must be removed monotonically from either VCC or VCCAUX (and must reach the power-down trip point of 0.5V for VCC, 0.95V for VCCAUX) before power is removed monotonically from VCC12, any of the VCCIOs, or VCCJ. Note that VCC12 can be removed at the same time as VCC, but it cannot be removed earlier. In many applications, VCC and VCC12 will be sourced from the same power supply and so will be removed together. For systems where disturbance of the user pins is a don't care condition, the power supplies can be removed in any order as long as they power down monotonically within 200ms of each other. Additionally, if any banks have VCCIO=3.3V nominal (potentially banks 1, 4, 5) then VCCIO for those banks must not be lower than VCCAUX during power-down. The normal variation in ramp-up times of power supplies and voltage regulators is not a concern here. Note: The SERDES power supplies are NOT included in these requirements and have no specific sequencing requirements. However, when using the SERDES with VDDIB or VDDOB that is greater than 1.2V (1.5V nominal for example), the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V power not applied. Both the 1.2V and 1.5V power should be applied to the SERDES at nominally the same time. The normal variation in the ramp-up times of power supplies and voltage regulators is not a concern here. Supported Source Synchronous Interfaces The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR standards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet.2-32 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Table 2-11. Source Synchronous Standards Table1 flexiPCS™ (Physical Coding Sublayer Block) flexiPCS Functionality The LatticeSC family combines a high-performance FPGA fabric, high-performance I/Os and large embedded RAM in a single industry leading architecture. LatticeSC devices also feature up to 32 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The flexiPCS logic can be configured to support numerous industry standard high-speed data transfer protocols. Each channel of flexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial data transfers at data rates up to 3.4 Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 1.02 or 2.04 Gbps Fibre Channel, PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface. Protocols requiring data rates above 3.4 Gbps can be accommodated by dedicating either one pair or all four channels in one flexiPCS quad block to one data link. One quad can support full-duplex serial data transfers at data rates up to 13.6 Gbps. A single flexiPCS quad can be configured to support 10Gb Ethernet (with a fully compliant XAUI interface), 10Gb Fibre Channel, and x4 PCI-Express and 4x RapidIO. The flexiPCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic which can also be geared to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Each SERDES pin can be DC coupled independently and can allow for both high-speed and low-speed operation down to DC rates on the same SERDES pin, as required by some Serial Digital Video applications. The ispLEVER design tools from Lattice support all modes of the flexiPCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow a user to define their own operation. With ispLEVER, the user can define the mode for each quad in a design. Nine modes are currently supported by the ispLEVER design flow: • 8-bit SERDES Only • 10-bit SERDES Only • SONET (STS-12/STS-48) • Gigabit Ethernet • Fibre Channel • XAUI • Serial RapidIO Source Synchronous Standard Clocking Speeds (MHz) Data Rate (Mbps) RapidIO DDR 500 1000 HyperTransport DDR 400 800 SPI4.2 (POS-PHY4)/NPSI DDR 650 1300 SFI4/XSBI DDR SDR 334 667 667 XGMII DDR 156.25 312 CSIX SDR 250 250 QDRII memory interface DDR 300 600 DDR memory interface DDR 240 480 DDRII memory interface DDR 400 800 RLDRAM memory interface DDR 400 800 1. Memory width is dependent on the system design and limited by the number of I/Os in the device.2-33 Architecture Lattice Semiconductor LatticeSC Family Data Sheet • PCI-Express • Generic 8b10b flexiPCS Quad The flexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each device in the LatticeSC family has up to eight quads of flexiPCS logic. The LatticeSC Family Selection Guide table on the first page of this data sheet contains the number of flexiPCS channels present on the chip. Note that in some packages (particularly lower pin count packages), not all channels from all quads on a given device may be bonded to package pins. Each quad supports up to four channels of full-duplex data and can be programmed into any one of several protocol based modes. Each quad requires its own reference clock which can be sourced externally or from the FPGA logic. The user can utilize between one and four channels in a quad, depending on the application. Figure 2-26 shows an example of four flexiPCS quads in a LatticeSC device. Quads are labeled according to the address of their software controlled registers. Figure 2-26. LatticeSC flexiPCS Since each quad has its own reference clock, different quads can support different standards on the same chip. This feature makes the LatticeSC family of devices ideal for bridging between different standards. flexiPCS quads are not dedicated solely to industry standard protocols. Each quad (and each channel within a quad) can be programmed for many user defined data manipulation modes. For example, modes governing userdefined word alignment and multi-channel alignment can be programmed for non-standard protocol applications. For more information on the functions and use of the flexiPCS, refer to the LatticeSC flexiPCS Data Sheet. SERDES Interface FPGA Logic Channel 0 PCS Logic Channel 1 PCS Logic Channel 2 PCS Logic Channel 3 PCS Logic FPGA Logic I/Os FPGA Logic I/Os FPGA Logic I/Os flexiPCS Quad 360 PCS/FPGA Interface flexiPCS Quad 360 High Speed Serial Data FPGA Logic I/Os SERDES Interface Channel 0 PCS Logic Channel 1 PCS Logic Channel 2 PCS Logic Channel 3 PCS Logic flexiPCS Quad 361 PCS/FPGA Interface flexiPCS Quad 361 High Speed Serial Data SERDES Interface Channel 3 PCS Logic Channel 2 PCS Logic Channel 1 PCS Logic Channel 0 PCS Logic flexiPCS Quad 3E1 PCS/FPGA Interface flexiPCS Quad 3E1 High Speed Serial Data SERDES Interface Channel 3 PCS Logic Channel 2 PCS Logic Channel 1 PCS Logic Channel 0 PCS Logic flexiPCS Quad 3E0 PCS/FPGA Interface flexiPCS Quad 3E0 High Speed Serial Data2-34 Architecture Lattice Semiconductor LatticeSC Family Data Sheet System Bus Each LatticeSC device connects the FPGA elements with a standardized bus framework referred to as a System Bus. Multiple bus masters optimize system performance by sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus configuration of 32 bits with 4-bit parity supports high-bandwidth, data intensive applications. There are two types of interfaces on the System Bus, master and slave. A master interface has the ability to perform actions on the bus, such as writes and reads to and from a specific address. A slave interface responds to the actions of a master by accepting data and address on a write and providing data on a read. The System Bus has a memory map which describes each of the slave peripherals that is connected on the bus. Using the addresses listed in the memory map, a master interface can access each of the slave peripherals on the System Bus. Any and all peripherals on the System Bus can be used at the same time. Table 2-12 list all of the available user peripherals on the System Bus after device power-up. Table 2-12. System Bus User Peripherals The peripherals listed in Table 2-12 can be added when the System Bus module is created using Module IP/Manager (ispLEVER Module/IP Manager). Figure 2-27 also lists the existing peripherals on the System Bus. The gray boxes are available only during configuration. Refer to Lattice technical note TN1080, LatticeSC sysCONFIG Usage Guide, for configuration options. The Status and Config box refers to internal System Bus registers. This document presents all the interfaces listed in Table 2-12 in detail to help the user utilize the desired functions of the System Bus. Figure 2-27. LatticeSC System Bus Interfaces Several interfaces exist between the System Bus and other FPGA elements. The MPI interface acts as a bridge between the external microprocessor bus and System Bus. The MPI may work in an independent clock domain from the System Bus if the System Bus clock is not sourced from the external microprocessor clock. Pipelined Peripheral Name Interface Type Micro Processor Interface MPI Master User Master Interface UMI Master User Slave Interface USI Slave Serial Management Interface (PLL, DLL, User Logic) SMI Slave Physical Coding Sublayer PCS Slave Direct FPGA Access DFA Slave DFA (Direct Access from MPI) SMI (PLL, DLL, USER LOGIC) STATUS and CONFIG (SYS REG) CONFIG (MASTER) System Bus USI (SLAVE) UMI (MASTER) EBR INIT (WRITE) MPI (MASTER) PCS (LEFT, RIGHT and INTER-QUAD) (SLAVE)2-35 Architecture Lattice Semiconductor LatticeSC Family Data Sheet operation allows high-speed memory interface to the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of the nature of the transfers. Details for the majority of the peripherals can be found in the associated technical documentation, see details at the end of this data sheet. Additional details of the MPI are provided below. Microprocessor Interface (MPI) The LatticeSC family devices have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration and read-back of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. The control portion of the MPI is available following power-up of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4-bit. In configuration mode the data and parity bus width are related to the state of the M[0:3] mode pins. For post-configuration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ispLEVER primitive library, or by setting the bit of the MPI configuration control register prior to the start of configuration. The user can also enable and disable the parity bus through the con- figuration bit stream. These pads can be used as general I/O when they are not needed for MPI use. The MPI block also provides the capability to interface directly to the FPGA fabric with a databus after configuration.The bus protocol is still handled by the MPI block but the direct FPGA access allows high-speed block data transfers such as DMA transactions. Figure 2-28 shows one of the ways a PowerPC is connected to MPI. Figure 2-28. PowerPCI and MPI Schematic Bus Controller LatticeSC FPGA To DaisyChained Devices PowerPC DOUT DONE HDC INIT LDC CCLK RETRY MPI_RTRY MPI_ACK BDIP MPI_BDIP IRQx MPI_IRQ TS MPI_STRB CS0 TSZ[0:1] MPI_TSZ[0:1] A[14:31] PPC_A[14:31] CLKOUT MPI_CLK RD/WR MPI_RW TA DP[0:m] 1, 2, 4 8, 16, 32 DP[0:m] D[0:n] D[0:n] CS1 TEA MPI_TEA BURST MPI_BURST2-36 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Configuration and Testing The following section describes the configuration and testing features of the LatticeSC family of devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS33, 25 and 18 standards. For additional detail refer to technical information at the end of the data sheet. Device Configuration All LatticeSC devices contain three possible ports that can be used for device configuration. The serial port, which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration. The MPI port supports 8-bit, 16-bit or 32-bit configuration. The serial port supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Configuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for general purpose I/O. All I/Os for the sysCONFIG and MPI ports are in I/O bank #1. On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a configuration port is selected, that port is locked and another configuration port cannot be activated until the next re-initialization sequence. For additional detail refer to technical information at the end of the data sheet. Internal Logic Analyzer Capability (ispTRACY) All LatticeSC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile time. For additional detail refer to technical information at the end of the data sheet. Temperature Sensing Lattice provides a way to monitor the die temperature by using a temperature-sensing diode that is designed into every LatticeSC device. The difference in VBE of the diode at two different forward currents varies with temperature. This relationship is shown in Figure 2-29. This temperature-sensing diode is designed to work with an external temperature sensor such as the Maxim 1617A. The Maxim 1617A is configured to measure difference in VBE (of the temperature-sensing diode) at 10µA and at 100µA. This difference in VBE voltage varies with temperature at approximately 1.64 mV/°C. A typical device with a 85°C junction temperature will measure approximately 593mV. For additional detail refer to technical information at the end of the data sheet.2-37 Architecture Lattice Semiconductor LatticeSC Family Data Sheet Figure 2-29. Sensing Diode Typical Characteristics Oscillator Every LatticeSC device has an internal CMOS oscillator, which is used as a master serial clock for configuration and is also available as a potential general purpose clock (MCK) for the FPGA core. There is a K divider (divide by 2/4/8/16/32/64/128) available with this oscillator to get lower MCK frequencies. This clock is available as a general purpose clock signal to the software routing tool. For additional detail refer to technical information at the end of the data sheet. Density Shifting The LatticeSC family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 0.50 -50 50 75 100 125 -25 25 100μA 10μA Junction Temperature (°C) Voltage 0 0.55 0.65 0.65 0.70 0.75 0.80 0.88 VBE difference increases with temperatureFebruary 2006 Preliminary Data Sheet © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DC and Switching_01.0 Absolute Maximum Ratings Supply Voltage VCC, VCC12, VDDIB, V DDOB, V DDRX, V DDTX, V DDP . . . . . . . . . . -0.5 to 1.6V Supply Voltage VCCAUX, VDDAX25, VTT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Supply Voltage VCCIO (Banks 1, 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Supply Voltage VCCIO (Banks 2, 3, 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V Input or I/O Tristate Voltage Applied (Banks 1, 4, 5) . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Input or I/O Tristate Voltage Applied (Banks 2, 3, 6, 7) . . . . . . . . . . . . . . . . -0.5 to 2.75V Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Notes: 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and Undershoot of -2V to (VIHMAX +2) volts is permitted for a duration of <20ns. Recommended Operating Conditions Symbol Parameter Min. Max. Units V CC Core Supply Voltage (Nominal 1.2V Operation) 0.95 1.26 V V CCAUX Programmable I/O Auxiliary Supply Voltage 2.375 2.625 V V CCIO 1, 2 Programmable I/O Driver Supply Voltage (Banks 1, 4, 5) 1.14 3.45 V V CCIO 1, 2 Programmable I/O Driver Supply Voltage (Banks 2, 3, 6, 7) 1.14 2.625 V V CC12 4 Internal 1.2V Configuration Logic and FPGA PLL Power Supply Voltage for Configuration Logic and FPGA PLL 1.14 1.26 V V DDP SERDES PLL Power Supply Voltage 1.14 1.26 V V DDTX, VDDRX SERDES Analog Supply Voltage 1.14 1.26 V V DDIB SERDES Input Buffer Supply Voltage 1.14 1.575 V V DDOB SERDES Output Buffer Supply Voltage 1.14 1.575 V V DDAX25 SERDES Termination Auxiliary Supply Voltage 2.375 2.625 V V CCJ 1 Supply Voltage for IEEE 1149.1 Test Access Port 1.71 3.45 V VTT 2, 3 Programmable I/O Termination Power Supply 0.5 VCCAUX - 0.5 V t JCOM Junction Commercial Operation 0 +85 C t JIND Junction Industrial Operation -40 105 C 1. If VCCIO or VCCJ is set to 2.5V, they must be connected to the same power supply as VCCAUX. 2. See recommended voltages by I/O standard in subsequent table. 3. If VTT termination and CTAP function is not used in a bank, VTT can be tied to ground. 4. VCC12 cannot be lower than VCC at any time. For 1.2V operation, it is recommended that the VCC and VCC12 supplies be tied together with proper noise decoupling between the digital VCC and analog VCC12 supplies. LatticeSC Family Data Sheet DC and Switching Characteristics3-2 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Hot Socketing Specifications DC Electrical Characteristics5 Over Recommended Operating Conditions Symbol Parameter Condition Min. Typ. Max Units I DK Programmable and dedicated Input or I/O leakage current1, 2, 3, 4, 5 0 <= VIN <= VIH (MAX) — — +/-1500 µA SERDES average input current when device powered down and inputs driven6 — — 4 mA 1. Assumes monotonic rise/fall rates for all power supplies. 2. Sensitive to power supply sequencing as described in hot socketing section. 3. Assumes power supplies are between 0 and maximum recommended operations conditions. 4. IDK is additive to IPU, IPD or IBH. 5. Represents DC conditions. For the first 20ns after hot insertion, current specification is 8 mA. 6. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed VDDOB of 1.575V, 8b/10b data and internal AC coupling. Symbol Parameter Condition Min.3 Typ. Max. Units I IL, IIH 1 Input or I/O Low leakage 0 ≤ VIN ≤ VIH (MAX) — — 10 µA I PU I/O Active Pull-up Current 0 ≤ VIN ≤ 0.7 VCCIO -30 — -210 µA I PD I/O Active Pull-down Current VIL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 210 µA I BHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA I BHHS Bus Hold High Sustaining Current VIN = 0.7VCCIO -30 — — µA I BHLO Bus Hold Low Overdrive Current 0 ≤ VIN ≤ VIH (MAX) — — 210 µA I BHLH Bus Hold High Overdrive Current 0 ≤ VIN ≤ VIH (MAX) — — -210 µA I CL PCI Low Clamp Current -3 < VIN ≤ -1 -25 + (VIN + 1)/0.015 — — mA I CH PCI High Clamp Current VCC + 4 > VIN ≥ VCC + 1 25 + (VIN - VCC -1)/ 0.015 — — mA VBHT Bus Hold trip Points 0 ≤ VIN ≤ VIH (MAX) VIL (MAX) — VIH (MIN) V C1 I/O Capacitance2 V CCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, V CC = 1.2V, VCCIP2 = 1.2V, V CCAUX = 2.5, VIO = 0 to VIH (MAX) — 8 — pf C32 Dedicated Input Capacitance2 V CCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, V CC = 1.2V, VCCIP2 = 1.2V, V CCAUX = 2.5, VIO = 0 to VIH (MAX) — 6 — pf 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25°C, f = 1.0MHz 3. IPU, IPD, IBHLS and I BHHS have minimum values of 15 or -15µA if VCCIO is set to 1.2V nominal. 4. This table does not apply to SERDES pins. 5. For programmable I/Os.3-3 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Initialization and Standby Supply Current1, 2, 3 Over Recommended Operating Conditions Symbol Parameter Device 25 o C 105 o C Units I CC Core Operating Power Supply Current (for VCC + VCC12) LFSC15 mA LFSC25 210 1500 mA LFSC40 mA LFSC80 mA LFSC115 mA I CCAUX Auxiliary Operating Power Supply Current LFSC15 mA LFSC25 5 35 mA LFSC40 mA LFSC60 mA LFSC80 mA LFSC115 mA I CCIO Bank Power Supply Current4 LFSC15 mA LFSC25 0.2 1 mA LFSC40 mA LFSC80 mA LFSC115 mA Notes: 1. For further information on supply current, please see the details of additional technical documentation at the end of this data sheet. 2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. 3. SERDES supply current is detailed in the SERDES section. 4. Includes ICCJ.3-4 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet PURESPEED I/O Recommended Operating Conditions V CCIO V REF (V) Standard Min. Typ. Max. Min. Typ. Max. LVCMOS 33 3.135 3.3 3.465 — — — LVCMOS 25 2.375 2.5 2.625 — — — LVCMOS 18 1.71 1.8 1.89 — — — LVCMOS 15 1.425 1.5 1.575 — — — LVCMOS 12 1.14 1.2 1.26 — — — LVTTL 3.135 3.3 3.465 — — — PCI33 3.135 3.3 3.465 — — — PCIX33 3.135 3.3 3.465 — — — PCIX15 1.425 1.5 1.575 0.49VCCIO 0.5VCCIO 0.51VCCIO AGP1X33 3.135 3.3 3.465 — — — AGP2X33 3.135 3.3 3.465 0.39VCCIO 0.4VCCIO 0.41VCCIO SSTL18_I, II3 1.71 1.8 1.89 0.833 0.9 0.969 SSTL25_I, II3 2.375 2.5 2.625 1.15 1.25 1.35 SSTL33_I, II3 3.135 3.3 3.465 1.3 1.5 1.7 HSTL15_I, II3 1.425 1.5 1.575 0.68 0.75 0.9 HSTL15_III1, 3 and IV1, 3 1.425 1.5 1.575 0.68 0.9 0.9 HSTL 18_I3 , II3 1.71 1.8 1.89 0.816 0.9 1.08 HSTL 18_ III1, 3, IV1, 3 1.71 1.8 1.89 0.816 1.08 1.08 GTL121, 3, GTLPLUS151, 3 — — — 0.882 1.0 1.122 LVDS — — — — — — Mini-LVDS —————— RSDS —————— HYPT (Hyper Transport) —————— LVPECL332, 3 3.135 3.3 3.465 — — — BLVDS252, 3 2.375 2.5 2.625 — — — MLVDS252, 3 2.375 2.5 2.625 — — — SSTL18D_I3 , II3 1.71 1.8 1.89 — — — SSTL25D_I3 , II3 2.375 2.5 2.625 — — — SSTL33D_I3 , II3 3.135 3.3 3.465 — — — HSTL15D_I3 , II3 1.425 1.5 1.575 — — — HSTL18D_I3 , II3 1.71 1.8 1.89 — — — 1. Input only. 2. Inputs on chip. Outputs are implemented with the addition of external resisters. 3. Input for this standard does not depend on the value of VCCIO.3-5 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet PURESPEED I/O Single-Ended DC Electrical Characteristics Over Recommended Operating Conditions Input/Output Standard VIL VIH V OL Max. (V) V OH Min. (V) I OL (mA) I OH Min. (V) Max. (V) Min. (V) Max. (V) (mA) LVCMOS 33 -0.3 0.8 2 3.6 0.4 2.4 24, 16, 8 -24, -16, -8 0.2 VCCIO - 0.2 0.1 -0.1 LVTTL -0.3 0.8 2 3.6 0.4 2.4 24, 16, 8 -24, -16, -8 0.2 VCCIO - 0.2 0.1 -0.1 LVCMOS 25 -0.3 0.7 1.7 2.65 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 LVCMOS 18 -0.3 0.35VCCIO 0.65VCCIO 2.65 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 LVCMOS 15 -0.3 0.35VCCIO 0.65VCCIO 2.65 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 LVCMOS 12 -0.3 0.35VCCIO 0.65VCCIO 2.65 0.3 VCCIO - 0.3 12, 8, 4, 2 -12, -8, -4, -2 0.2 VCCIO - 0.2 0.1 -0.1 PCIX15 -0.3 0.3VCCIO 0.5VCCIO 1.5 0.1VCCIO 0.9VCCIO 1.5 -0.5 PCI33 -0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5 PCIX33 -0.3 0.35VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5 AGP-1X, AGP-2X -0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5 SSTL3_I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8 SSTS3_I OST2 -0.3 VREF - 0.2 VREF + 0.2 3.6 0.9 VCCIO - 1.3 8 -8 SSTL3_II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16 SSTL3_II OST2 -0.3 VREF - 0.2 VREF + 0.2 3.6 0.9 VCCIO - 0.13 16 -16 SSTL2_I -0.3 VREF - 0.18 VREF + 0.18 2.65 0.54 VCCIO - 0.62 7.6 -7.6 SSTL2_I OST2 -0.3 VREF - 0.18 VREF + 0.18 2.65 0.73 VCCIO - 0.81 7.6 -7.6 SSTL2_II -0.3 VREF - 0.18 VREF + 0.18 2.65 0.35 VCCIO - 0.43 15.2 -15.2 SSTL2_II OST2 -0.3 VREF - 0.18 VREF + 0.18 2.65 0.73 VCCIO - 0.81 15.2 -15.2 SSTL18_I -0.3 VREF - 0.125 VREF + 0.125 2.65 0.28 VCCIO - 0.28 13.4 -13.4 SSTL18_II -0.3 VREF - 0.125 VREF + 0.125 2.65 0.28 VCCIO - 0.28 13.4 -13.4 HSTL15_I -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 8 -8 HSTL15_II -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 16 -16 HSTL15_III1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A HSTL15_IV1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A HSTL18_I -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 9.6 -9.6 HSTL18_II -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 19.2 -19.2 HSTL18_III1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A HSTL18_IV1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A GTL121 , GTLPLUS151 -0.3 VREF - 0.2 VREF + 0.2 N/A N/A N/A N/A N/A 1. Input only. 2. Input with on-chip series termination.3-6 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet PURESPEED I/O Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Hyper Transport Over Recommended Operating Conditions Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Units VINP, VINM Input voltage 0 — 2.4 V VTHD Differential input threshold +/-100 — — mV V CM Input common mode voltage 0.05 1.2 2.35 V I IN Input current Power on or power off — — +/-10 µA V OH Output high voltage for VOP or VOM RT = 100 Ohm — 1.38 1.60 V V OL Output low voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03 — V V OD Output voltage differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV ΔV OD Change in VOD between high and low — — 50 mV V OS Output voltage offset (VOP - VOM)/2, RT = 100 Ohm 1.125 1.20 1.375 V ΔV OS Change in VOS between H and L — — 50 mV I SAB Output short circuit current V OD = 0V Driver outputs shorted — — 12 mA Note: Data is for 3.5mA differential current drive. Other differential driver current options are available. Parameter Symbol Description Min. Typ. Max. Units V OD Differential output voltage 500 600 700 mV ΔV OD Change in VOD magnitude -15 — 15 mV V OCM Output common mode voltage 560 600 640 mV ΔV OCM Change in VOCM magnitude -15 — 15 mV VID Input differential voltage 500 600 700 mV ΔVID Input differential voltage -15 — 15 mV VICM Input common mode voltage 500 600 700 mV ΔVICM Change in VICM magnitude -15 — 15 mV Note: Data is for 6mA differential current drive. Other differential driver current options are available.3-7 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Mini-LVDS Over Recommended Operating Conditions RSDS Over Recommended Operating Conditions Parameter Symbol Description Min. Typ. Max. Units Z O Single-ended PCB trace impedance 30 50 75 ohms RT Differential termination resistance 60 100 150 ohms V OD Output voltage, differential, |VOP - VOM| 300 — 600 mV V OS Output voltage, common mode, |VOP + VOM|/2 1 1.2 1.4 V ΔV OD Change in VOD, between H and L — — 50 mV ΔVID Change in VOS, between H and L — — 50 mV VTHD Input voltage, differential, |VINP - VINM| 200 — 600 mV V CM Input voltage, common mode, |VINP + VINM|/2 0.3+(VTHD/2) — 2.1-(VTHD/2) T R, TF Output rise and fall times, 20% to 80% — — 500 ps T ODUTY Output clock duty cycle 45 — 55 % TIDUTY Input clock duty cycle 40 — 60 % Note: Data is for 6mA differential current drive. Other differential driver current options are available. Parameter Symbol Description Min. Typ. Max. Units V OD Output voltage, differential, RT = 100 ohms 100 200 600 mV V OS Output voltage, common mode 0.5 1.2 1.5 V I RSDS Differential driver output current 1 2 6 mA VTHD Input voltage differential 100 — — mV V CM Input common mode voltage 0.3 — 1.5 V T R, TF Output rise and fall times, 20% to 80% — 500 — ps T ODUTY Output clock duty cycle 45 50 55 % Note: Data is for 2mA drive. Other differential driver current options are available.3-8 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. MLVDS The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled impedance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals. Figure 3-1. MLVDS Multi-Point Output Example Table 3-1. MLVDS DC Conditions1 Over Recommended Operating Conditions Nominal Symbol Description Zo = 50 Zo = 70 Units Z OUT Output impedance 50 50 ohm RTLEFT Left end termination 50 70 ohm RTRIGHT Right end termination 50 70 ohm V OH Output high voltage 1.50 1.575 V V OL Output low voltage 1.00 0.925 V V OD Output differential voltage 0.50 0.65 V V CM Output common mode voltage 1.25 1.25 V I DC DC output current 20.0 18.5 mA 1. For input buffer, see LVDS table. Heavily loaded backplane, effective Zo ~ 50 to 70 ohms differential 50 50 2.5V 2.5V 50 50 2.5V 2.5V 50 50 2.5V 2.5V + - 50 50 2.5V 2.5V + - . . . 50-70 ohms, +/- 1% 50-70 ohms, +/- 1% + + - - + - . . .3-9 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet BLVDS The LatticeSC devices support BLVDS standard. This standard is emulated using controlled impedance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example Table 3-2. BLVDS DC Conditions1 Over Recommended Operating Conditions Nominal Symbol Description Zo = 45 Zo = 90 Units Z OUT Output impedance 100 100 ohm RTLEFT Left end termination 45 90 ohm RTRIGHT Right end termination 45 90 ohm V OH Output high voltage 1.375 1.48 V V OL Output low voltage 1.125 1.02 V V OD Output differential voltage 0.25 0.46 V V CM Output common mode voltage 1.25 1.25 V I DC DC output current 11.2 10.2 mA 1. For input buffer, see LVDS table. Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 100 100 2.5V 2.5V 100 100 2.5V 2.5V 100 100 2.5V 2.5V + - 100 100 2.5V 2.5V + - . . . 45-90 ohms, +/- 1% 45-90 ohms, +/- 1% + - + - . . . % - + -3-10 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet LVPECL The LatticeSC devices support differential LVPECL standard. This standard is emulated using controlled impedance complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals. Figure 3-3. Differential LVPECL Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions For further information on LVPECL, BLVDS, MLVDS and other differential interfaces please see details of additional technical documentation at the end of this data sheet. On-die Differential Common Mode Termination Symbol Description Nominal Units Z OUT Output impedance 16 ohm RS Driver series resistor 85 ohm RP Driver parallel resistor 150 ohm RT Receiver termination 100 ohm V OH Output high voltage 2.03 V V OL Output low voltage 1.27 V V OD Output differential voltage 0.76 V V CM Output common mode voltage 1.65 V Z BACK Back impedance 86 ohm I DC DC output current 12.6 mA 1. For input buffer, see LVDS table. Symbol Description Min. Typ. Max. Units CCMT Capacitance VCMT to GND — 40 — pF Transmission line, Zo = 100 ohm differential 100 ohms 150 ohms ON-chip OFF-chip 3.3V 3.3V 24mA ~16 ohms 24mA ~16 ohms + 85 ohms +/-1% 85 ohms +/-1% Zback -3-11 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Typical Building Block Function Performance Pin to Pin Performance (LVCMOS25 12 mA Drive) Register-to-Register Performance Switching Characteristics All devices are 100% functionally tested. Listed below are representative values of internal and external timing parameters. For more specific, more precise, and worst-case guaranteed data at a particular temperature and voltage use the values reported by the static timing analyzer in the ispLEVER design tool from Lattice and back-annotate to the simulation net list. Function -7 -6 -5 Units Basic Functions 32-bit Decoder 6.02 6.49 7.00 ns Combinatorial (Pin to LUT to Pin) 4.91 5.24 5.56 ns Embedded Memory Functions (Single Port RAM) Pin to EBR Input Register Setup (Global Clock) 1.42 1.50 1.58 ns EBR Output Clock to Pin (Global Clock) 7.72 8.53 9.67 ns Distributed (PFU) RAM (Single Port RAM) Pin to PFU RAM Register Setup (Global Clock) 1.70 1.84 2.05 ns PFU RAM Clock to Pin (Global Clock) 5.66 6.19 6.73 ns Function -7 -6 -5 Units Basic Functions 32-Bit Decoder 455 432 398 MHz 64-Bit Decoder 405 381 368 MHz 16:1 MUX 524 487 447 MHz 32:1 MUX 507 458 424 MHz 16-Bit Adder 567 477 481 MHz 64-Bit Adder 325 296 270 MHz 16-Bit Counter 690 622 565 MHz 64-Bit Counter 355 320 291 MHz 32x8 SP RAM (PFU, Output Registered) 748 686 602 MHz 128x8 SP RAM (PFU, Output Registered) 544 472 471 MHz Embedded Memory Functions Single Port RAM (512x36 Bits) 359 341 325 MHz True Dual Port RAM 1024x18 Bits (No EBR Out Reg) 314 279 265 MHz True dual port RAM 1024x18 Bits (EBR Reg) 359 341 325 MHz FIFO port (A: x36 bits, B: x9 Bits, No EBR Out Reg) 315 290 243 MHz FIFO port (A: x36 bits, B: x9 Bits, EBR Reg) 361 342 325 MHz True DP RAM Width Cascading (1024x72) 346 285 280 MHz DSP Functions 9x9 1-stage Multiplier 196 176 158 MHz 18x18 1-Stage Mutiplier 140 126 109 MHz 9x9 3-Stage Pipelined Multiplier 347 332 281 MHz 18x18 4-Stage Pipelined Mutiplier 298 280 250 MHz 9x9 Constant Multiplier 359 341 325 MHz3-12 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet LatticeSC External Switching Characteristics4 Over Recommended Operating Conditions Parameter Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units General I/O Pin Parameters (Using Primary Clock without PLL)2 t CO Global Clock Input to Output - PIO Output Register — 5.00 — 5.54 — 6.08 ns t SU Global Clock Input Setup - PIO Input Register without fixed input delay 0.00 — 0.00 — 0.00 — ns t H Global Clock Input Hold - PIO Input Register without fixed input delay 1.14 — 1.14 — 1.14 — ns t SU_IDLY Global Clock Input Setup - PIO Input Register with input delay 0.68 — 0.83 — 0.73 — ns t H_IDLY Global Clock Input Hold - PIO Input Register with input delay 0.00 — 0.00 — 0.00 — ns f MAX_PFU Global Clock frequency of PFU register — 700 — 700 — 700 MHz f MAX_IO Global Clock frequency of I/O register — 1000 — 1000 — 1000 MHz t GC_SKEW Global Clock skew 89 — 103 — 116 — ps General I/O Pin Parameters (Using Primary Clock with PLL)1, 2 t CO Global Clock Input to Output - PIO Output Register — 4.02 — 4.42 — 4.83 ns t SU Global Clock Input Setup - PIO Input Register without fixed input delay 0.00 — 0.00 — 0.00 — ns t H Global Clock Input Hold - PIO Input Register without fixed input delay 0.60 — 0.60 — 0.60 — ns * Note: No PLL delay tuning (clock injection removal mode), system clock feedback. General I/O Pin Parameters (Using Edge Clock without PLL)2 t CO Edge Clock Input to Output - PIO Output Register — 4.14 — 4.60 — 5.08 ns t SU Edge Clock Input Setup - PIO Input Register without fixed input delay 0.00 — 0.00 — 0.00 — ns t H Edge Clock Input Hold - PIO Input Register without fixed input delay 0.48 — 0.48 — 0.48 — ns t SU_IDLY Edgel Clock Input Setup - PIO Input Register with input delay 0.53 — 0.66 — 0.78 — ns t H_IDLY Edge Clock Input Hold - PIO Input Register with input delay 0.00 — 0.00 — 0.00 — ns t EC_SKEW Edge Clock skew 28 — 32 — 36 — ps General I/O Pin Parameters (Using Latch FF without PLL)2 t SU Latch FF, Input Setup - PIO Input Register without fixed input delay 0.00 — 0.00 — 0.00 — ns t H Latch FF, Input Hold - PIO Input Register without fixed input delay 0.51 — 0.51 — 0.51 — ns t SU_IDLY Latch FF, Input Setup - PIO Input Register with input delay 0.71 — 0.83 — 0.96 — ns t H_IDLY Latch FF, Input Hold - PIO Input Register with input delay 0.00 — 0.00 — 0.00 — ns 1. No PLL delay tuning (clock injection removal mode, system clock feedback). 2. Using LVCMOS25 12mA I/O. 3. A complete listing of Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters. 4. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is listed, there is no positive hold time.3-13 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet LatticeSC Internal Timing Parameters1, 2 Over Recommended Operating Conditions Parameter Symbol Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units PFU Logic Mode Timing t LUT4_PFU CTOF_DEL LUT4 delay (A to D inputs to F output) — 0.046 — 0.050 — 0.054 ns t LUT5_PFU MTOOFX_DEL LUT5 delay (inputs to output) — 0.157 — 0.174 — 0.192 ns t LUT6_PFU CTOOFX_DEL LUT6 delay (A to D inputs to OFX output) — 0.130 — 0.144 — 0.157 ns t LSR_PFU LSR_DEL Set/Reset to output (asynchronous) — 0.393 — 0.433 — 0.474 ns t SUM_PFU M_SET Clock to Mux (M0,M1) input setup time 0.118 — 0.133 — 0.148 — ns t HM_PFU M_HLD Clock to Mux (M0,M1) input hold time 0.000 — 0.000 — 0.000 — ns t SUD_PFU DIN_SET Clock to D input setup time -0.025 — -0.026 — -0.027 — ns t HD_PFU DIN_HLD Clock to D input hold time 0.000 — 0.000 — 0.000 — ns t CK2Q_PFU REG_DEL Clock to Q delay, D-type register configuration — 0.232 — 0.256 — 0.279 ns t LE2Q_PFU LTCH_DEL Clock to Q delay latch configuration — 0.305 — 0.336 — 0.367 ns t LD2Q_PFU TLTCH_DEL D to Q throughput delay when latch is enabled — 0.311 — 0.344 — 0.376 ns PFU Memory Mode Timing t CORAM_PFU CLKTOF_DEL Clock to Output — 0.596 — 0.660 — 0.724 ns t SUDATA_PFU DIN_SET Data Setup Time -0.025 — -0.026 — -0.027 — ns t HDATA_PFU DIN_HLD Data Hold Time 0.000 — 0.000 — 0.000 — ns t SUADDR_PFU WAD_SET Address Setup Time -0.183 — -0.199 — -0.215 — ns t HADDR_PFU WAD_HLD Address Hold Time 0.114 — 0.126 — 0.138 — ns t SUWREN_PFU WE_SET Write/Read Enable Setup Time 0.014 — 0.019 — 0.024 — ns t HWREN_PFU WE_HLD Write/Read Enable Hold Time 0.081 — 0.087 — 0.094 — ns PIC Timing PIO Input/Output Buffer Timing t IN_PIO IN_DEL Input Buffer Delay (LVCMOS25) 0.559 0.839 0.635 1.036 0.686 1.309 ns t OUT_PIO DOPADI_DEL Output Buffer Delay (LVCMOS25) 1.946 4.254 2.154 5.436 2.362 6.619 ns IOLOGIC Input/Output Timing t SUI_PIO DIN_SET Input Register Setup Time (Data Before Clock) -0.073 — -0.077 — -0.082 — ns t HI_PIO DIN_HLD Input Register Hold Time (Data after Clock) 0.000 — 0.000 — 0.000 — ns t COO_PIO CK_DEL Output Register Clock to Output Delay — 0.532 — 0.580 — 0.639 ns t SUCE_PIO CE_SET Input Register Clock Enable Setup Time — 0.000 — 0.000 — 0.000 ns3-14 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet t HCE_PIO CE_HLD Input Register Clock Enable Hold Time — 0.134 — 0.148 — 0.161 ns t SULSR_PIO LSR_SET Set/Reset Setup Time 0.059 — 0.061 — 0.063 — ns t HLSR_PIO LSR_HLD Set/Reset Hold Time 0.000 — 0.000 — 0.000 — ns t LE2Q_PIO CK_DEL Input Register Clock to Q delay latch configuration — 0.348 — 0.379 — 0.410 ns t LD2Q_PIO DIN_DEL Input Registe D to Q throughput delay when latch is enabled — 0.600 — 0.658 — 0.717 ns EBR Timing t CO_EBR CK_Q_DEL Clock (Read) to output from Address or Data — 2.004 — 2.191 — 2.377 ns t COO_EBR CK_Q_DEL Clock (Write) to output from EBR output Register — 2.004 — 2.191 — 2.377 ns t SUDATA_EBR D_CK_SET Setup Data to EBR Memory (Write clk) 0.095 — 0.088 — 0.082 — ns t HDATA_EBR D_CK_HLD Hold Data to EBR Memory (Write clk) 0.219 — 0.254 — 0.289 — ns t SUADDR_EBR A_CK_SET Setup Address to EBR Memroy (Write clk) 0.074 — 0.060 — 0.047 — ns t HADDR_EBR A_CK_HLD Hold Address to EBR Memory (Write clk) 0.218 — 0.255 — 0.291 — ns t SUWREN_EBR CE_CK_SET Setup Write/Read Enable to EBR Memory (Write/ Read clk) 0.233 — 0.230 — 0.226 — ns t HWREN_EBR CE_CK_HLD Hold Write/Read Enable to EBR Memory (write/read clk) 0.076 — 0.096 — 0.116 — ns t SUCE_EBR CS_CK_SET Clock Enable Setup Time to EBR Output Register (Read clk) 0.271 — 0.274 — 0.276 — ns t HCE_EBR CS_CK_HLD Clock Enable Hold Time to EBR Output Register (Read clk) 0.024 — 0.040 — 0.055 — ns t RSTO_EBR RESET_Q_DEL Reset To Output Delay Time from EBR Output Register (asynchronous) — 0.663 — 0.736 — 0.809 ns Cycle Boosting Timing t DEL1 DEL1 Cycle boosting delay 1 applies to PIO, PFU, EBR — 0.498 — 0.534 — 0.570 ns t DEL2 DEL2 Cycle boosting delay 2 applies to PIO, PFU, EBR — 0.956 — 1.022 — 1.090 ns t DEL3 DEL3 Cycle boosting delay 3 applies to PIO, PFU, EBR — 1.418 — 1.514 — 1.612 ns 1. A complete listing of Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters. 2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is listed, there is no positive hold time. LatticeSC Internal Timing Parameters1, 2 (Continued) Over Recommended Operating Conditions Parameter Symbol Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units3-15 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Timing Diagrams PFU Timing Diagrams Figure 3-4. Slice Single/Dual Port Write Cycle Timing Notes: • Rising Edge for latching WREN, WAD and DATAIN. • WREN must continue past falling edge clock. • Data output occurs on negative edge. Figure 3-5. Slice Single/Dual Port Read Cycle Timing D D AD Old Data CK WRE DI DO AD D AD Old Data CK WRE DO AD3-16 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet EBR Memory Timing Diagrams Figure 3-6. Read Mode Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. Figure 3-7. Read Mode with Input Registers Only A0 A1 A0 A1 D0 D1 A0 t ACCESS t ACCESS t ACCESS t ACCESS t SU t H D0 D1 D0 CLKA CSA WEA ADA DIA DOA A0 A1 A0 A1 D0 D1 Mem(n) data from previous read D0 D1 output is only updated during a read cycle t SU t H t ACCESS t ACCESS CLKA CSA WEA ADA DIA DOA3-17 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Figure 3-8. Read Mode with Input and Output Registers Figure 3-9. Read Before Write (SP Read/Write on Port A, Input Registers Only) Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. A0 A1 A0 A0 D0 D1 D0 D0 output is only updated during a read cycle A1 D1 Mem(n) data from previous read D0 D1 Mem(n) data from previous read DOA t SU t H t ACCESS t ACCESS CLKA CSA WEA ADA DIA DOA DOA (Registered) A0 A1 A0 A1 D0 D1 D2 A0 D2 D3 D1 old A0 Data old A1 Data D0 D1 t SU t H t ACCESS t ACCESS t ACCESS t ACCESS t ACCESS CLKA CSA WEA ADA DIA DOA3-18 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Figure 3-10. Write Through (SP Read/Write On Port A, Input Registers Only) Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. Figure 3-11. FIFO Reset Waveform Note: RE and WE must be deactivated tRSU before the Positive FIFO reset edge and enabled tRSH after the FIFO reset negative edge. A0 A1 A0 D0 D1 D4 t SU t ACCESS t ACCESS t ACCESS t H D2 D3 D4 D0 D1 D2 Data from Prev Read or Write Three consecutive writes to A0 D3 t ACCESS CLKA CSA WEA ADA DIA DOA t RW t RSU t RSU t RSF t RSF t RSH Asynchronous RESET, RESET pulse width (tRW), RESET to Flag valid (tRSF), RESET hold time (tRSH) t RSH RE RST EF, AE flags WE FF, AF flags DO3-19 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Figure 3-12. Read Pointer Reset Waveform Note: RE and WE must be deactivated tRSU before the Positive FIFO reset edge and enabled tRSH after the FIFO reset negative edge. Figure 3-13. Waveforms First Read after Full Flag t RW t RSU t RSF t RSU t RSH t ACCESS_F t ACCESS_E t RSH RESET pulse width (tRW), RESET to Flag valid (tRSF), RST_B RESET hold time (tRSH) RE RCLK EF, AE flags WE WCLK FF, AF flags First Read Last Write (FIFO FULL) t SU1 t CO t CO t SU1 t H1 t SKEW t H1 WCLK RE RCLK FF (flag) WE CS3-20 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Figure 3-14. Waveform First Write after Empty Flag First Write Last Read (FIFO Empty) RCLK WE WCLK EF (flag) RE CS t SU1 t SU1 t CO t SKEW t CO t H1 t H13-21 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet LatticeSC Family Timing Adders Over Recommended Operating Conditions Buffer Type Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units LVDS LVDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns RSDS RSDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns BLVDS25 BLVDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns MLVDS25 MLVDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns HYPT Hypertransport -0.021 -0.03 -0.002 -0.005 0.02 0.017 ns LVPECL33 LVPECL -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns HSTL18_I HSTL_18 class I -0.013 -0.015 0.015 0.007 0.042 0.029 ns HSTL18_II HSTL_18 class II -0.013 -0.015 0.015 0.007 0.042 0.029 ns HSTL18_III HSTL_18 class III -0.017 -0.019 0.008 0.002 0.032 0.023 ns HSTL18_IV HSTL_18 class IV -0.017 -0.019 0.008 0.002 0.032 0.023 ns HSTL18D_I Differential HSTL 18 class I 0.005 0.001 0.029 0.024 0.052 0.046 ns HSTL18D_II Differential HSTL 18 class II 0.005 0.001 0.029 0.024 0.052 0.046 ns HSTL15_I HSTL_15 class I -0.006 -0.017 0.026 -0.001 0.057 0.014 ns HSTL15_II HSTL_15 class II -0.006 -0.017 0.026 -0.001 0.057 0.014 ns HSTL15_III HSTL_15 class III -0.013 -0.015 0.015 0.007 0.042 0.029 ns HSTL15_IV HSTL_15 class IV -0.013 -0.015 0.015 0.007 0.042 0.029 ns HSTL15D_I Differential HSTL 15 class I -0.022 -0.023 0 -0.01 0.022 0.003 ns HSTL15D_II Differential HSTL 15 class II -0.022 -0.023 0 -0.01 0.022 0.003 ns SSTL33_I SSTL_3 class I -0.037 -0.063 -0.182 -0.314 -0.326 -0.565 ns SSTL33_II SSTL_3 class II -0.037 -0.063 -0.182 -0.314 -0.326 -0.565 ns SSTL33D_I Differential SSTL_3 class I 0.012 0.012 0.034 0.028 0.055 0.043 ns SSTL33D_II Differential SSTL_3 class II 0.012 0.012 0.034 0.028 0.055 0.043 ns SSTL25_I SSTL_2 class I 0.003 -0.009 0.03 0.011 0.058 0.03 ns SSTL25_II SSTL_2 class II 0.003 -0.009 0.03 0.011 0.058 0.03 ns SSTL25D_I Differential SSTL_2 class I 0.005 0 0.031 0.023 0.056 0.046 ns SSTL25D_II Differential SSTL_2 class II 0.005 0 0.031 0.023 0.056 0.046 ns SSTL18_I SSTL_18 class I -0.013 -0.015 0.015 0.007 0.042 0.029 ns SSTL18_II SSTL_18 class II -0.013 -0.015 0.015 0.007 0.042 0.029 ns SSTL18D_I Differential SSTL_18 class I 0.005 0.001 0.029 0.024 0.052 0.046 ns SSTL18D_II Differential SSTL_18 class II 0.005 0.001 0.029 0.024 0.052 0.046 ns LVTTL33 LVTTL 0.035 0.035 -0.05 -0.05 -0.134 -0.134 ns LVCMOS33 LVCMOS 3.3 0.035 0.035 -0.05 -0.05 -0.134 -0.134 ns LVCMOS25 LVCMOS 2.5 0 0 0 0 0 0 ns LVCMOS18 LVCMOS 1.8 -0.07 -0.07 -0.087 -0.087 -0.105 -0.105 ns LVCMOS15 LVCMOS 1.5 -0.135 -0.135 -0.188 -0.188 -0.241 -0.241 ns LVCMOS12 LVCMOS 1.2 -0.245 -0.245 -0.367 -0.367 -0.49 -0.49 ns PCI33 PCI 0.035 -0.063 -0.05 -0.314 -0.134 -0.565 ns PCIX33 PCI-X 3.3 0.035 -0.063 -0.05 -0.314 -0.134 -0.565 ns PCIX15 PCI-X 1.5 -0.006 -0.017 0.026 -0.001 0.057 0.014 ns AGP1X33 AGP-1X 3.3 0.035 -0.063 -0.05 -0.314 -0.134 -0.565 ns AGP2X33 AGP-2X -0.037 -0.063 -0.182 -0.314 -0.326 -0.565 ns3-22 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet GTLPLUS15 GTLPLUS15 -0.013 -0.018 0.012 0.003 0.037 0.024 ns GTL12 GTL12 -0.065 -0.074 -0.009 -0.049 0.056 -0.032 ns LVDS LVDS 0.022 -1.3932 0.0255 -1.602 0.029 -1.81 ns RSDS RSDS 0.022 -1.3932 0.0255 -1.602 0.029 -1.81 ns BLVDS25 BLVDS 0.362 0.362 0.394 0.394 0.427 0.427 ns MLVDS25 MLVDS 0.134 0.134 0.136 0.136 0.138 0.138 ns LVPECL33 LVPECL -0.125 -6.5322 -0.1435 -7.512 -0.163 -8.491 ns HYPT Hypertransport -0.007 -1.5752 -0.0085 -1.812 -0.009 -2.048 ns HSTL18_I HSTL_18 class I 0.057 0.021 0.068 0.014 0.078 0.007 ns HSTL18_II HSTL_18 class II 0.144 0.062 0.142 0.094 0.14 0.127 ns HSTL18D_I Differential HSTL 18 class I 0.057 0.021 0.068 0.014 0.078 0.007 ns HSTL18D_II Differential HSTL 18 class II 0.144 0.062 0.142 0.094 0.14 0.127 ns HSTL15_I HSTL_15 class I 0.095 0.064 0.075 0.062 0.061 0.055 ns HSTL15_II HSTL_15 class II 0.126 0.107 0.118 0.107 0.11 0.097 ns HSTL15D_I Differential HSTL 15 class I 0.095 0.064 0.075 0.062 0.061 0.055 ns HSTL15D_II Differential HSTL 15 class II 0.126 0.107 0.118 0.107 0.11 0.097 ns SSTL33_I SSTL_3 class I 0.179 0.179 0.169 0.169 0.159 0.159 ns SSTL33_II SSTL_3 class II 0.199 0.199 0.193 0.193 0.187 0.187 ns SSTL33D_I Differential SSTL_3 class I 0.179 0.179 0.169 0.169 0.159 0.159 ns SSTL33D_II Differential SSTL_3 class II 0.199 0.199 0.193 0.193 0.187 0.187 ns SSTL25_I SSTL_2 class I 0.061 0.026 0.067 0.033 0.073 0.04 ns SSTL25_II SSTL_2 class II 0.07 0.063 0.075 0.066 0.081 0.069 ns SSTL25D_I Differential SSTL_2 class I 0.061 0.026 0.067 0.033 0.073 0.04 ns SSTL25D_II Differential SSTL_2 class II 0.07 0.063 0.075 0.066 0.081 0.069 ns SSTL18_I SSTL_2 class I 0.111 0.078 0.1 0.086 0.094 0.089 ns SSTL18_II SSTL_2 class II 0.142 0.087 0.132 0.098 0.122 0.099 ns SSTL18D_I Differential SSTL_2 class I 0.111 0.078 0.1 0.086 0.094 0.089 ns SSTL18D_II Differential SSTL_2 class II 0.142 0.087 0.132 0.098 0.122 0.099 ns LVTTL33_8mA LVTTL 8mA drive -0.112 -0.112 -0.203 -0.203 -0.293 -0.293 ns LVTTL33_16mA LVTTL 16mA drive 0.094 0.094 0.034 0.034 -0.026 -0.026 ns LVTTL33_24mA LVTTL 24mA drive 0.168 0.168 0.119 0.119 0.07 0.07 ns LVCMOS33_8mA LVCMOS 3.3 8mA drive -0.112 -0.112 -0.203 -0.203 -0.293 -0.293 ns LVCMOS33_16mA LVCMOS 3.3 16mA drive 0.094 0.094 0.034 0.034 -0.026 -0.026 ns LVCMOS33_24mA LVCMOS 3.3 24mA drive 0.168 0.168 0.119 0.119 0.07 0.07 ns LVCMOS25_4mA LVCMOS 2.5 4mA drive -0.144 -0.144 -0.154 -0.154 -0.163 -0.163 ns LVCMOS25_8mA LVCMOS 2.5 8mA drive 0 0 0 0 0 0 ns LVCMOS25_12mA LVCMOS 2.5 12mA drive 0.041 0.041 0.044 0.044 0.048 0.048 ns LVCMOS25_16mA LVCMOS 2.5 16mA drive 0.065 0.065 0.07 0.07 0.075 0.075 ns LVCMOS25_OD LVCMOS 2.5 open drain -0.022 -0.283 -0.014 -0.263 -0.006 -0.244 ns LVCMOS18_4mA LVCMOS 1.8 4mA drive -0.135 -0.135 -0.173 -0.173 -0.211 -0.211 ns LVCMOS18_8mA LVCMOS 1.8 8mA drive 0.006 0.006 0.001 0.001 -0.004 -0.004 ns LatticeSC Family Timing Adders (Continued) Over Recommended Operating Conditions Buffer Type Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units3-23 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet LVCMOS18_12mA LVCMOS 1.8 12mA drive 0.053 0.053 0.058 0.058 0.063 0.063 ns LVCMOS18_16mA LVCMOS 1.8 16mA drive 0.082 0.082 0.086 0.086 0.091 0.091 ns LVCMOS18_OD LVCMOS 1.8 open drain 0.032 -0.22 0.002 -0.26 0.001 -0.301 ns LVCMOS15_4mA LVCMOS 1.5 4mA drive -0.081 -0.081 -0.167 -0.167 -0.252 -0.252 ns LVCMOS15_8mA LVCMOS 1.5 8mA drive 0.062 0.062 0.014 0.014 -0.033 -0.033 ns LVCMOS15_12mA LVCMOS 1.5 12mA drive 0.056 0.056 0.041 0.041 0.026 0.026 ns LVCMOS15_16mA LVCMOS 1.5 16mA drive 0.085 0.085 0.073 0.073 0.061 0.061 ns LVCMOS15_OD LVCMOS 1.5 open drain 0.04 -0.27 0.002 -0.305 -0.035 -0.34 ns LVCMOS12_2mA LVCMOS 1.2 2mA drive -0.136 -0.136 -0.229 -0.229 -0.321 -0.321 ns LVCMOS12_4mA LVCMOS 1.2 4mA drive 0.018 0.018 -0.042 -0.042 -0.101 -0.101 ns LVCMOS12_8mA LVCMOS 1.2 8mA drive 0.08 0.08 0.02 0.02 -0.041 -0.041 ns LVCMOS12_12mA LVCMOS 1.2 12mA drive 0.112 0.112 0.051 0.051 -0.011 -0.011 ns LVCMOS12_OD LVCMOS 1.2 open drain -0.013 -0.366 -0.054 -0.39 -0.094 -0.413 ns PCI33 PCI 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns PCIX33 PCI-X 3.3 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns PCIX15 PCI-X 1.5 0.107 0.107 0.107 0.107 0.108 0.108 ns AGP1X33 AGP-1X 3.3 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns AGP2X33 AGP-2X 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns LatticeSC Family Timing Adders (Continued) Over Recommended Operating Conditions Buffer Type Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units3-24 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter Description Conditions Min. Typ Max. Units f IN Input Clock Frequency (CLKI, CLKFB) 15 — 1000 MHz f OUT Output Clock Frequency (CLKOP, CLKOS) 1.5625 — 1000 MHz f VCO PLL VCO Frequency 100 — 1000 MHz f PFD Phase Detector Input Frequency 15 — 700 MHz AC Characteristics t DT Output Clock Duty Cycle Default duty cycle selected (at 50% levels) 45 — 55 % t OPJIT Output Clock Period Jitter f REF ≥ 50MHz — — 0.02 UI f REF < 50MHz — — 0.01m UI/VCO (MHz) UI t CPJIT Output Clock Cycle-to-Cycle Jitter Without feedback dividers — — 0.03 UI With feedback dividers — — 150 ps t SKEW Output Clock-to-Clock Skew (Between Two Outputs with the Same Phase Setting) — — 20 ps t LOCK PLL Lock-in Time — — 1 ms t IPJIT Input Clock Period Jitter — — +/- 250 ps t HI Input Clock High Time At 80% level 350 — — ps t LO Input Clock Low Time At 20% level 350 — — ps t RSWA Analog Reset Signal Pulse Width 100 — — ns t RSWD Digital Reset Signal Pulse Width 3 — — ns t DEL Timeshift Delay Step Size — 80 — ps t RANGE Timeshift Delay Range — +/- 560 — ps f SS Spread Spectrum Modulation Frequency 30 — 500 KHz % Spread Percentage Downspread for SS Mode 1 — 3 %3-25 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet sysCLOCK DLL Timing Over Recommended Operating Conditions Parameter Description Conditions Min. Typ. Max. Units f IN Input Clock Frequency (CLKI, CLKFB) 100 — 700 MHz f OUTOP Output Clock Frequency (CLKOP) 100 — 700 MHz f OUTOS Output Clock Frequency (CLKOS) 25 — 700 MHz AC Characteristics t DUTY Output Clock Duty Cycle Output Clock Duty Cycle (at 50% levels, 50% duty cycle input clock, duty cycle correction turned off, time reference delay mode) 38 — 62 % t DUTYRD Output Clock Duty Cycle Output Clock Duty Cycle (at 50% levels, arbitrary duty cycle input clock, duty cycle correction turned on, time reference delay mode) 45 — 55 % t DUTYCIR Output Clock Duty Cycle Output Clock Duty Cycle (at 50% levels, arbitrary duty cycle input clock, duty cycle correction turned on, clock injection removal mode) 40 — 60 % t OPJIT Output Clock Period Jitter — — 200 ps t CPJIT Output Clock Cycle-to-Cycle Jitter — — 200 ps t SKEW Output Clock to Clock Skew (Between Two Outputs with the Same Phase Setting) — — 100 ps t LOCK DLL Lock-in Time 8 — 18500 cycles t IPJIT Input Clock Period Jitter — — +/- 250 ps t HI Input Clock High Time At 80% level 500 — — ps t LO Input Clock Low Time At 20% level 500 — — ps t RSWD Reset Signal Pulse Width 3 — — ns t DEL Timeshift Delay Step Size 25 42 90 ps3-26 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet LatticeSC sysCONFIG Port Timing Over Recommended Operating Conditions Parameter Description Min. Max. Units General Configuration Timing t SMODE M[3:0] Setup Time to INITN High 0 — ns t HMODE M[3:0] Hold Time from INITN High 600 — ns t RW RESETN Pulse Width Low to Start Reconfiguration (1.2 V) 50 (or 100 at 0.95V) — ns t PGW PROGRAMN Pulse Width Low to Start Reconfiguration (1.2 V) 50 (or 100 at 0.95V) — ns f ESB_CLK_FRQ System Bus ESB_CLK Frequency (No Wait States) — 133 MHz sysCONFIG Master Serial Configuration Mode t SMS DIN Setup Time 4.4 — ns t HMS DIN Hold Time 0 — ns f CMS CCLK Frequency (No Divider) 90 190 MHz f C_DIV CCLK Frequency (Div 128) 0.70 1.48 MHz t D CCLK to DOUT Delay — 7.5 ns sysCONFIG Master Parallel Configuration Mode t AVMP RCLK to Address Valid — 10 ns t SMP D[7:0] Setup Time to RCLK High 6 — ns t HMP D[7:0] Hold Time to RCLK High 0 — ns t CLMP RCLK Low Time 8 190 MHz t CHMP RCLK High Time 0.63 1.48 MHz t DMP CCLK to DOUT — 7.5 ns sysCONFIG Asynchronous Peripheral Configuration Mode t WRAP WRN, CS0N and CS1 Pulse Width 5 - ns t SAP D[7:0] Setup Time 1.5 - ns t RDYAP RDY Delay — 8 ns t BAP RDY Low 1 8 CCLK periods t WR2AP Earliest WRN After RDY Goes High 0 — ns t DENAP RDN to D[7:0] Enable/Disable — 7.5 ns t DAP CCLK to DOUT — 7.5 ns sysCONFIG Slave Serial Configuration Mode t SSS DIN Setup Time 5.2 — ns t HSS DIN Hold Time 0 — ns t CHSS CCLK High Time 3.75 — ns t CLSS CCLK Low Time 3.75 — ns f CSS CCLK Frequency — 150 MHz t DSS CCLK to DOUT — 7.5 ns sysCONFIG Slave Parallel Configuration Mode t S1SP CS0N, CS1, WRN Setup Time 5.2 — ns t H1SP CS0N, CS1, WRN Hold Time 0 — ns t S2SP D[7:0] Setup Time 5.2 — ns t H2SP D[7:0] Hold Time 0 — ns t CHSP CCLK High Time 3.75 — ns3-27 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet sysCONFIG MPI Port t CL CCLK Low Time 3.75 — ns f CSP CCLK Frequency — 150 MHz sysCONFIG Readback Timing t SRB RDCFGN to CCLK Setup Time 5.2 — ns t RBA RDCFGN High Width to Abort Readback 2 — CCLK Cycles t CLRB CCLK Low Time 3.33 — ns t CHRB CCLK High Time 3.33 — ns f CRB CCLK Frequency — 150 MHz t DRB CCLK to RDDATA Delay — 7.5 ns Parameter Description -7 -6 -5 Min. Max. Min. Max. Min. Max. Units t MPICTRL_SET MPI Control (MPCSTRBN, MPCWRN, MPCCLK, etc.) to MPCCLK Setup Time 4.9 — 5.2 — 5.5 — ns t MPIADR_SET MPI Address to MPCCLK Setup Time 3.9 — 4.2 — 4.5 — ns t MPIDAT_SET MPI Write Data to MPCCLK Setup Time 4.9 — 5.2 — 5.5 — ns t MPIDPAR_SET MPI Write Parity Data to MPCCLK Setup Time 3.9 — 4.2 — 4.5 — ns t MPI_HLD All Hold Times 0 — 0 — 0 — ns t MPICTRL_DEL MPCCLK to MPI Control (MPCTA, MPCTEA, MPCRETRY) — 5.6 — 6.7 — 8.7 ns t MPIDAT_DEL MPCCLK to MPI Data — 5.6 — 6.7 — 8.7 ns t MPIDPAR_DEL MPCCLK to MPI Parity Data — 4.9 — 5.7 — 7.7 ns f MPI_CLK_FRQ MPCCLK Frequency — 100 — 83 — 66 MHz LatticeSC sysCONFIG Port Timing (Continued) Over Recommended Operating Conditions Parameter Description Min. Max. Units3-28 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Boundary Scan Timing Specifications Over Recommended Operating Conditions Symbol Parameter Min. Max. Units f MAX — 25 MHz t BTCP TCK [BSCAN] Clock Pulse Width 40 — ns t BTCPH TCK [BSCAN] Clock Pulse Width High 50 — mV/ns t BTCPL TCK [BSCAN] Clock Pulse Width Low — 10 ns t BTS TCK [BSCAN] Setup Time — 10 ns t BTH TCK [BSCAN] Hold Time 8 — ns t BTRF TCK [BSCAN] Rise/Fall Time 10 — ns t BTCO TAP Controller Falling Edge of Clock to Valid Output 20 — ns t BTCODIS TAP Controller Falling Edge of Clock to Valid Disable 20 — ns t BTCOEN TAP Controller Falling Edge of Clock to Valid Enable — 10 ns t BTCRS BSCAN Test Capture Register Setup Time 8 — ns t BTCRH BSCAN Test Capture Register Hold Time 10 — ns t BUTCO BSCAN Test Update Register, Falling Edge of Clock to Valid Output — 25 ns t BTUODIS BSCAN Test Update Register, Falling Edge of Clock to Valid Disable — 25 ns t BTUPOEN BSCAN Test Update Register, Falling Edge of Clock to Valid Enable — 25 ns3-29 DC and Switching Characteristics Lattice Semiconductor LatticeSC Family Data Sheet Switching Test Conditions Figure 3-15 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-4. Figure 3-15. Output Test Load, LVTTL and LVCMOS Standards Table 3-4. Test Fixture Required Components, Non-Terminated Interfaces Test Condition CL Timing Ref. VT LVTTL and other LVCMOS settings (L -> H, H -> L) 30pF LVCMOS 3.3 = 1.5V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — LVCMOS 2.5 I/O (Z -> H) 30pF V CCIO/2 VOL LVCMOS 2.5 I/O (Z -> L) VCCIO/2 VOH LVCMOS 2.5 I/O (H -> Z) VOH - 0.15 VOL LVCMOS 2.5 I/O (L -> Z) VOL + 0.15 VOH Note: Output test conditions for all other interfaces are determined by the respective standards. DUT CL Test PointFebruary 2006 Preliminary Data Sheet © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 Pinouts_01.0 Signal Descriptions Signal Name I/O Description General Purpose P[Edge] [Row/Column Number*]_[A/B/C/D] I/O [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PIC row or the column of the device on which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. [A/B/C/D] indicates the PIO within the PIC to which the pad is connected. Some of these user programmable pins are shared with special function pins. These pin when not used as special purpose pins can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. VREF1_x, VREF2_x — The reference supply pins for I/O bank x. Any I/O pin in a bank can be assigned as a reference supply pin, but software defaults use designated pin. NC — No connect. Non-SERDES Power Supplies VCCIOx — VCCIO - The power supply pins for I/O bank x. Dedicated pins. VCC12 — 1.2V supply for configuration logic and PLLs. VTT_x — Termination voltage for bank x. GND — GND - Ground. Dedicated pins. VCC — VCC - The power supply pins for core logic. Dedicated pins (1.2V/ 1.0V). VCCAUX — VCCAUX - Auxiliary power supply pin - powers all differential and referenced input buffers. Dedicated pins (2.5V). VCCJ — VCCJ - The power supply pin for JTAG Test Access Port. PROBE_VCC — VCC signal - Used for feedback to control the power converter. PROBE_GND — GND signal - Used for feedback to control the power converter. PLL and Clock Functions (Used as user-programmable I/O pins when not in use for PLL, DLL or clock pins.) [LOC]_PLL[T, C]_FB_[A/B] I PLL feedback input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the PLL is located in: ULC (upper left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C] indicates whether input is true or complement. [A, B] indicates PLL reference within the corner. [LOC]_DLL[T, C]_FB_[C, D, E, F] I DLL feedback input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the DLL is located in: ULC (upper left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C] indicates whether input is true or complement. [C, D, E, F] indicates DLL reference within a corner. Note: E and F are only available on the lower corners. LatticeSC Family Data Sheet Pinout Information4-2 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet [LOC]_PLL[T, C]_IN[A/B] I PLL reference clock input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the PLL is located in: ULC (upper left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C] indicates whether input is true or complement.[A, B] indicates PLL reference within the corner. [LOC]_DLL[T, C]_IN[C, D, E, F] DLL reference clock inputs. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the DLL is located in: ULC (upper left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C] indicates whether input is true or complement. [C, D, E, F] indicates DLL reference within a corner. Note: E and F are only available on the lower corners. PCLKxy_z General clock inputs. x indicates whether T (true) or C (complement). y indicates the I/O bank the clock is associated with. z indicates the clock number within a bank. Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.) TMS I Test Mode Select input, used to control the 1149.1 state machine. TCK I Test Clock input pin, used to clock the 1149.1 state machine. TDI I Test Data in pin, used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). TDO/RDDATA O Output pin -Test Data out pin used to shift data out of device using 1149.1. If used for serial read-back, RDDATA provides serial configuration data out which is clocked out using CCLK. Configuration Pads (Dedicated pins. Used during sysCONFIG.) M[3:0] I Mode pins used to specify configuration modes values latched on rising edge of INITN. INITN I/O Open Drain pin - Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. PROGRAMN I Initiates configuration sequence when asserted low. This pin always has an active pull-up. DONE I/O Open Drain pin - Indicates that the configuration sequence is complete, and the startup sequence is in progress. CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode. RESETN Reset. (Also sent to general routing). During configuration it resets the configuration state machine. After configuration this pin can perform the global set/reset (GSR) functions or can be used as a general input pin. CFGIRQN O MPI Interrupt request active low signal is controlled by system bus interrupt controller and may be sourced from any bus error or MPI con- figuration error. It can be connected to one of MPC860 IRQ pins. RDCFGN I Enables readback. Configuration Pads (User I/O if not used. Used during sysCONFIG.) HDC O High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. LDCN O Low During Configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. Signal Descriptions (Continued) Signal Name I/O Description4-3 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet DOUT O Serial data output that can drive the D0/DIN of daisy-chained slave devices. The data-stream from this output will propagate preamble bits of the bitstream to daisy-chained devices. Data out on DOUT changes on the rising edge of CCLK. QOUT/CEON O During daisy-chaining configuration, QOUT is the serial data output that can drive the D0/DIN of daisy-chained slave devices that do not propagate preamble bits. Data out on QOUT changes on the rising edge of CCLK. During parallel-chaining configuration, active low CEON enables the cascaded slave device to receive bitstream data. RDN I Used in the asynchronous peripheral configuration mode. A low on RDN changes D[7:3] into status outputs. WRN and RDN should not be used simultaneously. If they are, the write strobe overrides. WRN I When the FPGA is selected, a low on the write strobe, WRN, loads the data on D[7:0] inputs into an internal data buffer. CS0N CS1 I Used in the asynchronous peripheral, slave parallel and MPI modes. The FPGA is selected when CS0N is low and CS1 is high. During con- figuration, a pull-up is enabled on both except with MPI DMA access control. A[21:0] I/O In master parallel mode, A[21:0] is an output and will address the con- figuration EPROMs up to 4 MB space. For MPI configuration mode, A[17:0] will be the MPI address MPI_ADDR[31:14], A[19:18] will be the transfer size and A[21:20] will be the burst mode and burst in process. D[n:0] I/O In parallel configuration modes, D[7:0] receives configuration data, and each pin is pull-up enabled. For slave serial mode, D0 is the data input. D[7:3] is the output internal status for peripheral mode when RDN is low. D[7:0] is also the first byte of MPI data pins. In MPI configuration mode, MPI selectable data bus width from 8 and 16-bit. Driven by a bus master in a write transaction. Driven by MPI in a read transaction. DP[m:0] I/O MPI selectable parity data bus width from 1, 2, and 3-bit DP[0] for D[7:0], DP[1] for D[15:8], and DP[2] for D[23:16]. BUSYN/RCLK O During configuration in peripheral mode, high on BUSYN/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D[7] in asynchronous peripheral mode. During configuration in slave parallel mode, low on BUSYN/RCLK inhibits the external host from sending new data. During configuration in master parallel and master byte modes, BUSYN/RCLK is a read clock output signal to an external memory. The BUSYN/RCLK frequency is the same as CCLK when used with uncompressed bitstreams. BUSYN/RCLK will be 1/8 the frequency of CCLK when the bitstream is compressed. During configuration in SPI mode, BUSYN/RCLK is generated by the device and connected to the CLK input of the FLASH memory. MPI Interface (Dedicated pin) Signal Descriptions (Continued) Signal Name I/O Description4-4 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet MPI_IRQ_N O MPI Interrupt request active low signal is controlled by system bus interrupt controller and may be sourced from any bus error or MPI con- figuration error. It can be connected to one of MPC860 IRQ pins. MPI Interface (User I/O if MPI is not used.) MPI_CS0N MPI_CS1 I MPI chip select pins, active low on MPI_CS0N while active high on MPI_CS1. Both have to be active during the whole transfer data phase. During transfer address phase, both can be inactive so that the decoding for them from address can be slow. If they are active during address phase, one cycle can be saved for sync read. MPI_CLK I This is the PowerPC bus clock. It can be a source of the clock for embedded system bus. If MPI_CLK is used as system bus clock, MPI will be set into sync mode by default. All of the operation on PowerPC side of MPI are synchronized to the rising edge of this clock. MPI_TSIZ[1:0] I Driven by a bus master to indicate the data transfer size for the transaction. 01 for byte, 10 for half-word, and 00 for word. MPI_WR_N I Driven high indicates that a read access is in progress. Driven low indicates that a write access is in process. MPI_BURST I Driven active low indicates that a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. MPI_BDIP I Active low “Burst Data in Process” is driven by a PowerPC processor. Asserted indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_STRBN I Driven active low indicates the start of a transaction on the PowerPC bus. MPI will strobe the address bus at next rising edge of clock. MPI_ADDR[31:14] I Address bus driven by a PowerPC bus master. Only 18-bit width is needed. It has to be the least significant bit of the PowerPC 32-bit address A[31:14]. MPI_DAT[n:0] I/O Selectable data bus width from 8, and 16-bit. Driven by a bus master in a write transaction. Driven by MPI in a read transaction. MPI_PAR[m:0] I/O Selectable parity bus width from 1, 2, and 3-bit. MPI_DP[0] for MPI_D[7:0], MPI_DP[1] for MPI_D[15:8] and MPI_DP[2] for MPI_D[23:16]. MPI_TA O Transfer acknowledge. Driven active low indicates that MPI received the data on the write cycle or returned data on the read cycle. MPI_TEA O Transfer Error Acknowledge. Driven active low indicates that MPI detects a bus error on the internal system bus for current transaction. MPI_RETRY O Active low MPI Retry requests the MPC860 to relinquish the bus and retry the cycle. Multi-chip Alignment (User I/O if not used.) MCA_DONE_OUT O Multi-chip alignment done output (to second MCA chip) MCA_DONE_IN I Multi-chip alignment done input (from second MCA chip) MCA_CLK_P[1:2]_OUT O Multi-chip alignment clock [1:2] output (sourced by MCA master chip) MCA_CLK_P[1:2]_IN I Multi-chip alignment clock [1:2] input (from MCA master chip TEMP — Temperature sensing diode pin. Dedicated pin. Miscellaneous Dedicated Pins XRES — External reference resistor between this pin and ground. The reference resistor is used to calibrate the programmable terminating resistors used in the I/Os. Dedicated pin. Value: 1K ± 1% ohm. DIFFRx — Only used if a differential driver is used in a bank. This DIFFRx must be connected to ground via an external 1K ±1% ohm resistor for all banks that have a differential driver. Signal Descriptions (Continued) Signal Name I/O Description4-5 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet SERDES Block (Dedicated Pins) A_HDINPx_[L/R] I High-speed input (positive) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. A_HDINNx_[L/R] I High-speed input (negative) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. A_HDOUTPx_[L/R] O High-speed output (positive) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. A_HDOUTNx_[L/R] O High-speed output (negative) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. A_REFCLKP_[L/R] I Ref clock input (positive), aux channel on left [L] or right [R] side of device. A_REFCLKN_[L/R] I Ref clock input (negative), aux channel on left [L] or right [R] side of device. A_RXREFCLKP_[L/R] I Ref clock input (positive), RX only on left [L] or right [R] side of device. A_RXREFCLKN_[L/R] I Ref clock input (negative), RX only on left [L] or right [R] side of device. A_VDDIBx_[L/R] — Input buffer power supply for channel x (1.2V/1.5V) on left [L] or right [R] side of device. A_VDDOBx_[L/R] — Output buffer power supply for channel x (1.2V/1.5V) on left [L] or right [R] side of device. A_VDDAX25_[L/R] — Auxiliary power for input and output termination (2.5V) on left [L] or right [R] side of device. A_VDDRXx_[L/R] — Receiver power supply for channel x (1.2V) on left [L] or right [R] side of device. A_VDDTXx_[L/R] — Transmitter power supply for channel x (1.2V) on left [L] or right [R] side of device. A_VDDP_[L/R] — Power supply for SERDES PLL (1.2V) on left [L] or right [R] side of device. Signal Descriptions (Continued) Signal Name I/O Description4-6 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet Pin Information Summary Pin Type 900 ffBGA Single Ended User I/O 378 Differential Pair User I/O 182 LVDS Output Pairs 60 Configuration Dedicated 11 User I/O / MPI sysBUS 55 JTAG (excluding VCCJ) 4 Dedicated pins 4 V CC 46 V CC12 17 V CCAUX 36 V CCIO Bank1 18 Bank2 14 Bank3 15 Bank4 15 Bank5 15 Bank6 15 Bank7 16 VTT Bank2 2 Bank3 3 Bank4 3 Bank5 3 Bank6 3 Bank7 2 GND 177 NC 26 Single Ended User/Differential I/O per Bank Bank1 63/30 Bank2 30/15 Bank3 62/29 Bank4 66/32 Bank5 65/32 Bank6 62/29 Bank7 30/15 LVDS Output Pairs per Bank Bank2 9 Bank3 21 Bank6 21 Bank7 9 V CCJ 1 SERDES (signal + power supply) 76 Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.4-7 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet Power Supply and NC Connections1, 3 Ball Function 900 ffBGA Ball Numbers VCC AA10, AA11, AA12, AA13, AA14, AA17, AA18,AA19, AA20, AA21, AA22, AA9, AB10, AB21, J10, J21, J22, J9, K10, K11, K12, K13, K14, K17, K18, K19, K20, K21, K22, K9, L10, L21, M10, M21, N10, N21, P10, P21, U10, U21, V10, V21, W10, W21, Y10, Y21 VCC12 AB9, AB22, AC8, AC23, H8, H23, H15, R23, T8, E5, D4, AG4, AF5, AF26, AG27, D27, E26 VCCIO1 H10, H21, H22, H9, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20, F20, C19, C12, F11 VCCIO2 J23, J24, K23, K24, L22, L23, M22, N22, P22, R22, G30, J29, K27, N25 VCCIO3 AA23, AA24, AB23, AB24, T22, U22, V22, W22, Y22, Y23, Y24, AC29, AA26, Y28, AA29 VCCIO4 AB16, AB17, AB18, AB19, AB20, AC20, AC21, AC22, AD20, AD21, AD22, AJ23, AG20, AJ26, AG23 VCCIO5 AB11, AB12, AB13, AB14, AB15, AC10, AC11, AC9, AD10, AD11, AD9, AE7, AH6, AG11, AJ9 VCCIO6 AA7, AA8, AB7, AB8, T9, U9, V9, W9, Y7, Y8, Y9, AB2, AD1, W4, AA4 VCCIO7 J7, J8, K7, K8, L8, L9, M9, N9, P9, R9, H2, N4, N6, J2, L2, H4 VCCJ J25 VCCAUX H11, H12, H19, H20, M23, M24, N23, N24, U23, U24, V23, V24, W23, W24, AC17, AC18, AC19, AD17, AD18, AD19, AC12, AC13, AC14, AD12, AD13, AD14, U7, U8, V7, V8, W7, W8, M7, M8, N7, N8 GND A1, A30, AA15, AA16, AK1, AK30, K15, K16, L11, L12, L13, L14, L15, L16, L17, L18, L19, L20, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, U11, U12, U13, U14, U15, U16, U17, U18, U19, U20, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, W11, W12, W13, W14, W15, W16, W17, W18, W19, W20, Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y19, Y20, H1, L4, M3, N5, K2, M2, P6, G4, H3, AC2, AA3, AE1, Y4, AB4, AA5, AE6, AE8, AH5, AG9, AG6, AF11, AG12, AJ10, AK26, AJ22, AF20, AJ25, AJ27, AF23, AF22, AE27, AA27, AB29, Y26, AC30, Y29, F30, E27, F27, P25, H29, K29, R24, M28, J27, N26, E20, E21, F21, F23, G23, D21, D20, E18, C20, C11, A12, E11, F8, G8, D11, D10, H7, F10, E10 NC2 M4, P5, J3, AB3, AH9, AG10, AF12, AG7, AK27, AJ24, AB30, AA28, P24, K28, P23, L28, E19, G21, G20, G19, F9, A11, G7, AC16, A2, A29 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. SERDES power supply pins not shown, see Logic Signal Connections table for details.4-8 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet VTT Ball Function VCCIO Bank 900 ffBGA Ball Numbers VTT_2 2 L24, T23 VTT_3 3 AC24, T25, W25 VTT_4 4 AD24, AE17, AE18 VTT_5 5 AC15, AD16, AE9 VTT_6 6 AA6, T7, W6 VTT_7 7 L7, P74-9 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet LFSC25 Logic Signal Connections: 900-Ball ffBGA1 Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA A_VDDAX25_L I - - F7 A_REFCLKP_L I - - B1 A_REFCLKN_L I - - C1 A_VDDP_L I - - D5 A_RXREFCLKP_L I - - B2 A_RXREFCLKN_L I - - C2 NC - - - A2 VCC12 VCC12 - - E5 VCC12 VCC12 - - D4 RESETN I 1 0 H5 RDCFGN I 1 0 H6 DONE IO 1 0 G6 INITN IO 1 0 G5 M0 I 1 0 F5 M1 I 1 0 F6 M2 I 1 0 F4 M3 I 1 0 E4 PL16A IO 7 2 ULC_PLLT_IN_A/ULC_PLLT_FB_B D3 PL16B IO 7 2 ULC_PLLC_IN_A/ULC_PLLC_FB_B D2 PL16C IO 7 2 J6 PL16D IO 7 2 J5 PL17A IO 7 2 ULC_DLLT_IN_C/ULC_DLLT_FB_D E3 PL17B IO 7 2 ULC_DLLC_IN_C/ULC_DLLC_FB_D E2 PL17C IO 7 2 ULC_PLLT_IN_B/ULC_PLLT_FB_A K4 PL17D IO 7 2 ULC_PLLC_IN_B/ULC_PLLC_FB_A J4 PL18A IO 7 2 ULC_DLLT_IN_D/ULC_DLLT_FB_C F3 PL18B IO 7 2 ULC_DLLC_IN_D/ULC_DLLC_FB_C G3 PL18C IO 7 2 K5 PL18D IO 7 2 VREF2_7 K6 PL20A IO 7 2 G2 PL20B IO 7 2 G1 PL21A IO 7 2 L5 PL21B IO 7 2 M5 PL22A IO 7 2 F2 PL22B IO 7 2 F1 PL22C IO 7 2 E1 PL22D IO 7 2 D1 PL25A IO 7 2 _ K3 PL25B IO 7 2 L3 PL25C IO 7 2 VREF1_7 L6 PL25D IO 7 2 DIFFR_7 M6 PL26A IO 7 2 PCLKT7_1 J1 PL26B IO 7 2 PCLKC7_1 K14-10 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PL27A IO 7 2 PCLKT7_0 L1 PL27B IO 7 2 PCLKC7_0 M1 PL27C IO 7 2 PCLKT7_2 P8 PL27D IO 7 2 PCLKC7_2 R8 PL29A IO 6 2 PCLKT6_0 N2 PL29B IO 6 2 PCLKC6_0 N1 PL29C IO 6 2 PCLKT6_1 R7 PL29D IO 6 2 PCLKC6_1 R6 PL30A IO 6 2 N3 PL30B IO 6 2 P3 PL30C IO 6 2 PCLKT6_3 P4 PL31A IO 6 2 P2 PL31B IO 6 2 R2 PL31C IO 6 2 PCLKT6_2 T3 PL31D IO 6 2 PCLKC6_2 R3 PL34A IO 6 2 P1 PL34B IO 6 2 R1 PL34C IO 6 2 VREF1_6 R5 PL34D IO 6 2 R4 PL35A IO 6 2 T2 PL35B IO 6 2 U2 PL35C IO 6 2 T6 PL36A IO 6 2 U3 PL36B IO 6 2 V3 PL38A IO 6 2 T1 PL38B IO 6 2 U1 PL39A IO 6 2 T5 PL39B IO 6 2 T4 PL40A IO 6 2 U4 PL40B IO 6 2 U5 PL42A IO 6 2 V1 PL42B IO 6 2 W1 PL42C IO 6 2 U6 PL42D IO 6 2 DIFFR_6 V6 PL43A IO 6 2 V2 PL43B IO 6 2 W2 PL43C IO 6 2 V5 PL43D IO 6 2 V4 PL44A IO 6 2 Y1 PL44B IO 6 2 AA1 PL47A IO 6 2 Y2 PL47B IO 6 2 AA2 PL47C IO 6 2 Y3 PL47D IO 6 2 W3 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-11 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PL48A IO 6 2 AB1 PL48B IO 6 2 AC1 PL48C IO 6 2 W5 PL49A IO 6 2 Y5 PL49B IO 6 2 Y6 PL51A IO 6 2 AD2 PL51B IO 6 2 AE2 PL51D IO 6 2 VREF2_6 AB5 PL52A IO 6 2 AC3 PL52B IO 6 2 AD3 PL53A IO 6 2 AC4 PL53B IO 6 2 AD4 PL55A IO 6 2 AF1 PL55B IO 6 2 AG1 PL55C IO 6 2 LLC_DLLT_IN_E/LLC_DLLT_FB_F AB6 PL55D IO 6 2 LLC_DLLC_IN_E/LLC_DLLC_FB_F AC5 PL56A IO 6 2 AE3 PL56B IO 6 2 AF3 PL57A IO 6 2 LLC_DLLT_IN_F/LLC_DLLT_FB_E AF2 PL57B IO 6 2 LLC_DLLC_IN_F/LLC_DLLC_FB_E AG2 PL57C IO 6 2 LLC_PLLT_IN_B/LLC_PLLT_FB_A AC6 PL57D IO 6 2 LLC_PLLC_IN_B/LLC_PLLC_FB_A AC7 XRES IO - - AE4 VCC12 VCC12 - - AG4 TEMP I 6 0 AD5 VCC12 VCC12 - - AF5 PB3A IO 5 4 LLC_PLLT_IN_A/LLC_PLLT_FB_B AH1 PB3B IO 5 4 LLC_PLLC_IN_A/LLC_PLLC_FB_B AJ1 PB3C IO 5 4 LLC_DLLT_IN_C/LLC_DLLT_FB_D AF4 PB3D IO 5 4 LLC_DLLC_IN_C/LLC_DLLC_FB_D AE5 PB4A IO 5 4 LLC_DLLT_IN_D/LLC_DLLT_FB_C AG3 PB4B IO 5 4 LLC_DLLC_IN_D/LLC_DLLC_FB_C AH2 PB4C IO 5 4 AD6 PB5A IO 5 4 AJ2 PB5B IO 5 4 AK2 PB5C IO 5 4 AD7 PB5D IO 5 4 VREF1_5 AD8 PB7A IO 5 4 AF7 PB7B IO 5 4 AF6 PB8A IO 5 4 AH4 PB8B IO 5 4 AG5 PB9A IO 5 4 AF8 PB9B IO 5 4 AG8 PB11A IO 5 4 AH3 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-12 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PB11B IO 5 4 AJ3 PB11C IO 5 4 AF9 PB11D IO 5 4 AE10 PB12A IO 5 4 AK3 PB12B IO 5 4 AJ4 PB13A IO 5 4 AE11 PB13B IO 5 4 AF10 PB15A IO 5 4 AH7 PB15B IO 5 4 AH8 PB15C IO 5 4 AE12 PB15D IO 5 4 AE13 PB16A IO 5 4 AK4 PB16B IO 5 4 AK5 PB17A IO 5 4 AJ5 PB17B IO 5 4 AJ6 PB19A IO 5 4 AJ7 PB19B IO 5 4 AJ8 PB20A IO 5 4 PCLKT5_3 AH10 PB20B IO 5 4 PCLKC5_3 AH11 PB20C IO 5 4 PCLKT5_4 AF13 PB20D IO 5 4 PCLKC5_4 AE14 PB21A IO 5 4 PCLKT5_5 AK6 PB21B IO 5 4 PCLKC5_5 AK7 PB21C IO 5 4 AF14 PB21D IO 5 4 AF15 PB23A IO 5 4 PCLKT5_0 AJ11 PB23B IO 5 4 PCLKC5_0 AJ12 PB23C IO 5 4 AG13 PB23D IO 5 4 VREF2_5 AH13 PB24A IO 5 4 PCLKT5_1 AK8 PB24B IO 5 4 PCLKC5_1 AK9 PB25A IO 5 4 PCLKT5_2 AH14 PB25B IO 5 4 PCLKC5_2 AG14 PB28A IO 5 4 AK10 PB28B IO 5 4 AK11 PB29A IO 5 4 AH15 PB29B IO 5 4 AG15 PB31A IO 5 4 AH12 PB31B IO 5 4 AJ13 PB31C IO 5 4 AD15 PB31D IO 5 4 AE15 PB32A IO 5 4 AK12 PB32B IO 5 4 AK13 PB33A IO 5 4 AJ14 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-13 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PB33B IO 5 4 AJ15 PB35A IO 5 4 AK14 PB35B IO 5 4 AK15 PB37A IO 4 4 AK16 PB37B IO 4 4 AK17 PB38A IO 4 4 AJ16 PB38B IO 4 4 AJ17 PB38C IO 4 4 AE16 PB38D IO 4 4 AF16 PB39A IO 4 4 AH16 PB39B IO 4 4 AG16 PB41A IO 4 4 AK18 PB41B IO 4 4 AK19 PB42A IO 4 4 AH17 PB42B IO 4 4 AH18 PB42C IO 4 4 AF17 PB42D IO 4 4 AG17 PB43A IO 4 4 AJ18 PB43B IO 4 4 AJ19 PB46A IO 4 4 PCLKT4_2 AK20 PB46B IO 4 4 PCLKC4_2 AK21 PB47A IO 4 4 PCLKT4_1 AF18 PB47B IO 4 4 PCLKC4_1 AG18 PB49A IO 4 4 PCLKT4_0 AJ20 PB49B IO 4 4 PCLKC4_0 AJ21 PB49C IO 4 4 VREF2_4 AG19 PB49D IO 4 4 AF19 PB51A IO 4 4 PCLKT4_5 AK22 PB51B IO 4 4 PCLKC4_5 AK23 PB51C IO 4 4 AH19 PB51D IO 4 4 AH20 PB52A IO 4 4 PCLKT4_3 AK24 PB52B IO 4 4 PCLKC4_3 AK25 PB52C IO 4 4 PCLKT4_4 AE19 PB52D IO 4 4 PCLKC4_4 AE20 PB53A IO 4 4 AE21 PB53B IO 4 4 AF21 PB55A IO 4 4 AG21 PB55B IO 4 4 AG22 PB56A IO 4 4 AH22 PB56B IO 4 4 AH23 PB56C IO 4 4 AH21 PB57A IO 4 4 AD23 PB57B IO 4 4 AE23 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-14 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PB59A IO 4 4 AH24 PB59B IO 4 4 AH25 PB60A IO 4 4 AK28 PB60B IO 4 4 AK29 PB60C IO 4 4 AE22 PB61A IO 4 4 AH26 PB61B IO 4 4 AH27 PB63A IO 4 4 AF24 PB63B IO 4 4 AG24 PB64A IO 4 4 AG25 PB64B IO 4 4 AF25 PB65A IO 4 4 AG26 PB65B IO 4 4 AF27 PB67A IO 4 4 AJ28 PB67B IO 4 4 AH28 PB67C IO 4 4 VREF1_4 AE24 PB67D IO 4 4 AE25 PB68A IO 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D AJ29 PB68B IO 4 4 LRC_DLLC_IN_C/LRC_DLLC_FB_D AH29 PB68C IO 4 4 AE26 PB68D IO 4 4 AD25 PB69A IO 4 4 LRC_PLLT_IN_A/LRC_PLLT_FB_B AJ30 PB69B IO 4 4 LRC_PLLC_IN_A/LRC_PLLC_FB_B AH30 PB69C IO 4 4 LRC_DLLT_IN_D/LRC_DLLT_FB_C AG28 PB69D IO 4 4 LRC_DLLC_IN_D/LRC_DLLC_FB_C AG29 VCC12 VCC12 - - AF26 PROBE_VCC O - - AD27 VCC12 VCC12 - - AG27 PROBE_GND O - - AE28 PR57D IO 3 2 LRC_PLLC_IN_B/LRC_PLLC_FB_A AC25 PR57C IO 3 2 LRC_PLLT_IN_B/LRC_PLLT_FB_A AD26 PR57B IO 3 2 LRC_DLLC_IN_F/LRC_DLLC_FB_E AF28 PR57A IO 3 2 LRC_DLLT_IN_F/LRC_DLLT_FB_E AF29 PR56B IO 3 2 AD28 PR56A IO 3 2 AC27 PR55D IO 3 2 LRC_DLLC_IN_E/LRC_DLLC_FB_F AC26 PR55C IO 3 2 LRC_DLLT_IN_E/LRC_DLLT_FB_F AB26 PR55B IO 3 2 AG30 PR55A IO 3 2 AF30 PR53B IO 3 2 AE29 PR53A IO 3 2 AD29 PR52B IO 3 2 AC28 PR52A IO 3 2 AB28 PR51D IO 3 2 VREF2_3 AB27 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-15 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PR51B IO 3 2 AE30 PR51A IO 3 2 AD30 PR49B IO 3 2 AB25 PR49A IO 3 2 AA25 PR48C IO 3 2 Y25 PR48B IO 3 2 AA30 PR48A IO 3 2 Y30 PR47D IO 3 2 W27 PR47C IO 3 2 Y27 PR47B IO 3 2 W30 PR47A IO 3 2 V30 PR44B IO 3 2 W29 PR44A IO 3 2 V29 PR43D IO 3 2 W26 PR43C IO 3 2 V26 PR43B IO 3 2 U30 PR43A IO 3 2 T30 PR42D IO 3 2 DIFFR_3 V25 PR42C IO 3 2 U25 PR42B IO 3 2 W28 PR42A IO 3 2 V28 PR40B IO 3 2 T27 PR40A IO 3 2 R27 PR39B IO 3 2 V27 PR39A IO 3 2 U27 PR38B IO 3 2 R30 PR38A IO 3 2 P30 PR36B IO 3 2 U29 PR36A IO 3 2 T29 PR35C IO 3 2 T24 PR35B IO 3 2 N30 PR35A IO 3 2 M29 PR34D IO 3 2 U26 PR34C IO 3 2 VREF1_3 T26 PR34B IO 3 2 U28 PR34A IO 3 2 T28 PR31D IO 3 2 PCLKC3_2 M30 PR31C IO 3 2 PCLKT3_2 L29 PR31B IO 3 2 R29 PR31A IO 3 2 P29 PR30C IO 3 2 PCLKT3_3 P27 PR30B IO 3 2 N29 PR30A IO 3 2 N28 PR29D IO 3 2 PCLKC3_1 R25 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-16 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PR29C IO 3 2 PCLKT3_1 R26 PR29B IO 3 2 PCLKC3_0 R28 PR29A IO 3 2 PCLKT3_0 P28 PR27D IO 2 2 PCLKC2_2 N27 PR27C IO 2 2 PCLKT2_2 P26 PR27B IO 2 2 PCLKC2_0 L30 PR27A IO 2 2 PCLKT2_0 K30 PR26B IO 2 2 PCLKC2_1 J30 PR26A IO 2 2 PCLKT2_1 H30 PR25D IO 2 2 DIFFR_2 M26 PR25C IO 2 2 VREF1_2 M25 PR25B IO 2 2 G29 PR25A IO 2 2 F29 PR22D IO 2 2 H28 PR22C IO 2 2 J28 PR22B IO 2 2 E30 PR22A IO 2 2 E29 PR21B IO 2 2 M27 PR21A IO 2 2 L27 PR20B IO 2 2 H27 PR20A IO 2 2 G27 PR18D IO 2 2 VREF2_2 L26 PR18C IO 2 2 L25 PR18B IO 2 2 URC_DLLC_IN_D/URC_DLLC_FB_C F28 PR18A IO 2 2 URC_DLLT_IN_D/URC_DLLT_FB_C G28 PR17D IO 2 2 URC_PLLC_IN_B/URC_PLLC_FB_A K26 PR17C IO 2 2 URC_PLLT_IN_B/URC_PLLT_FB_A K25 PR17B IO 2 2 URC_DLLC_IN_C/URC_DLLC_FB_D D30 PR17A IO 2 2 URC_DLLT_IN_C/URC_DLLT_FB_D D29 PR16D IO 2 2 G26 PR16C IO 2 2 H26 PR16B IO 2 2 URC_PLLC_IN_A/URC_PLLC_FB_B E28 PR16A IO 2 2 URC_PLLT_IN_A/URC_PLLT_FB_B D28 VCCJ I - - J25 TDO O - - TDO/RDDATA H25 TMS I - - J26 TCK I - - G25 TDI I - - G24 PROGRAMN I 1 0 F26 MPIIRQN O 1 0 CFGIRQN/MPI_IRQ_N H24 CCLK IO 1 0 F25 VCC12 VCC12 - - D27 VCC12 VCC12 - - E26 NC - - - A29 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-17 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet A_RXREFCLKN_R I - - C29 A_RXREFCLKP_R I - - B29 A_VDDP_R I - - D26 A_REFCLKN_R I - - C30 A_REFCLKP_R I - - B30 A_VDDAX25_R I - - F24 A_VDDRX0_R I - - D25 A_VDDIB0_R I - - C28 A_HDINP0_R I - - PCS 3E0 CH 0 IN P B28 A_HDINN0_R I - - PCS 3E0 CH 0 IN N B27 A_VDDTX0_R I - - E25 A_HDOUTP0_R O - - PCS 3E0 CH 0 OUT P A28 A_VDDOB0_R I - - C27 A_HDOUTN0_R O - - PCS 3E0 CH 0 OUT N A27 A_VDDOB1_R I - - C26 A_HDOUTN1_R O - - PCS 3E0 CH 1 OUT N A26 A_VDDTX1_R I - - D24 A_HDOUTP1_R O - - PCS 3E0 CH 1 OUT P A25 A_HDINN1_R I - - PCS 3E0 CH 1 IN N B26 A_HDINP1_R I - - PCS 3E0 CH 1 IN P B25 A_VDDRX1_R I - - E24 A_VDDIB1_R I - - C25 A_VDDRX2_R I - - D23 A_VDDIB2_R I - - C24 A_HDINP2_R I - - PCS 3E0 CH 2 IN P B24 A_HDINN2_R I - - PCS 3E0 CH 2 IN N B23 A_VDDTX2_R I - - E23 A_HDOUTP2_R O - - PCS 3E0 CH 2 OUT P A24 A_VDDOB2_R I - - C23 A_HDOUTN2_R O - - PCS 3E0 CH 2 OUT N A23 A_VDDOB3_R I - - C22 A_HDOUTN3_R O - - PCS 3E0 CH 3 OUT N A22 A_VDDTX3_R I - - D22 A_HDOUTP3_R O - - PCS 3E0 CH 3 OUT P A21 A_HDINN3_R I - - PCS 3E0 CH 3 IN N B22 A_HDINP3_R I - - PCS 3E0 CH 3 IN P B21 A_VDDRX3_R I - - E22 A_VDDIB3_R I - - C21 PT49D IO 1 4 HDC G22 PT49C IO 1 4 LDCN F22 PT49B IO 1 4 D8/MPI_DATA8 B20 PT49A IO 1 4 CS1/MPI_CS1 B19 PT47D IO 1 4 D9/MPI_DATA9 A20 PT47C IO 1 4 D10/MPI_DATA10 A19 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-18 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PT47B IO 1 4 CS0N/MPI_CS0N D19 PT47A IO 1 4 RDN/MPI_STRB_N D18 PT46D IO 1 4 WRN/MPI_WR_N F19 PT46C IO 1 4 D7/MPI_DATA7 F18 PT46B IO 1 4 D6/MPI_DATA6 C18 PT46A IO 1 4 D5/MPI_DATA5 C17 PT45D IO 1 4 D4/MPI_DATA4 E17 PT45C IO 1 4 D3/MPI_DATA3 E16 PT45B IO 1 4 D2/MPI_DATA2 G18 PT45A IO 1 4 D1/MPI_DATA1 G17 PT43B IO 1 4 D0/MPI_DATA0 B18 PT43A IO 1 4 QOUT/CEON B17 PT42D IO 1 4 VREF2_1 G16 PT42B IO 1 4 DOUT A18 PT42A IO 1 4 MCA_DONE_IN A17 PT41B IO 1 4 MCA_CLK_P1_OUT H18 PT41A IO 1 4 MCA_CLK_P1_IN H17 PT39B IO 1 4 MCA_CLK_P2_OUT D17 PT39A IO 1 4 MCA_CLK_P2_IN D16 PT38D IO 1 4 MCA_DONE_OUT F17 PT38C IO 1 4 BUSYN/RCLK F16 PT38B IO 1 4 DP0/MPI_PAR0 C16 PT38A IO 1 4 MPI_TA C15 PT37B IO 1 4 PCLKC1_0 B16 PT37A IO 1 4 PCLKT1_0/MPI_CLK B15 PT35D IO 1 4 PCLKC1_4 H16 PT35B IO 1 4 MPI_RETRY A16 PT35A IO 1 4 A0/MPI_ADDR14 A15 PT33D IO 1 4 A1/MPI_ADDR15 G15 PT33C IO 1 4 A2/MPI_ADDR16 F15 PT33B IO 1 4 A3/MPI_ADDR17 E15 PT33A IO 1 4 A4/MPI_ADDR18 D15 PT32B IO 1 4 A5/MPI_ADDR19 C14 PT32A IO 1 4 A6/MPI_ADDR20 C13 PT31C IO 1 4 VREF1_1 H14 PT31B IO 1 4 A7/MPI_ADDR21 B14 PT31A IO 1 4 A8/MPI_ADDR22 B13 PT29B IO 1 4 A9/MPI_ADDR23 G14 PT29A IO 1 4 A10/MPI_ADDR24 F14 PT28B IO 1 4 A11/MPI_ADDR25 A14 PT28A IO 1 4 A12/MPI_ADDR26 A13 PT27D IO 1 4 D11/MPI_DATA11 G13 PT27C IO 1 4 D12/MPI_DATA12 H13 PT27B IO 1 4 A13/MPI_ADDR27 E14 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-19 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet PT27A IO 1 4 A14/MPI_ADDR28 E13 PT25D IO 1 4 A16/MPI_ADDR30 G12 PT25C IO 1 4 D13/MPI_DATA13 G11 PT25B IO 1 4 A15/MPI_ADDR29 D14 PT25A IO 1 4 A17/MPI_ADDR31 D13 PT24D IO 1 4 A19/MPI_TSIZ1 F12 PT24C IO 1 4 A20/MPI_BDIP F13 PT24B IO 1 4 A18/MPI_TSIZ0 B12 PT24A IO 1 4 MPI_TEA B11 PT23D IO 1 4 D14/MPI_DATA14 E12 PT23C IO 1 4 DP1/MPI_PAR1 D12 PT23B IO 1 4 A21/MPI_BURST G10 PT23A IO 1 4 D15/MPI_DATA15 G9 A_VDDIB3_L I - - C10 A_VDDRX3_L I - - E9 A_HDINP3_L I - - PCS 360 CH 3 IN P B10 A_HDINN3_L I - - PCS 360 CH 3 IN N B9 A_HDOUTP3_L O - - PCS 360 CH 3 OUT P A10 A_VDDTX3_L I - - D9 A_HDOUTN3_L O - - PCS 360 CH 3 OUT N A9 A_VDDOB3_L I - - C9 A_HDOUTN2_L O - - PCS 360 CH 2 OUT N A8 A_VDDOB2_L I - - C8 A_HDOUTP2_L O - - PCS 360 CH 2 OUT P A7 A_VDDTX2_L I - - E8 A_HDINN2_L I - - PCS 360 CH 2 IN N B8 A_HDINP2_L I - - PCS 360 CH 2 IN P B7 A_VDDIB2_L I - - C7 A_VDDRX2_L I - - D8 A_VDDIB1_L I - - C6 A_VDDRX1_L I - - E7 A_HDINP1_L I - - PCS 360 CH 1 IN P B6 A_HDINN1_L I - - PCS 360 CH 1 IN N B5 A_HDOUTP1_L O - - PCS 360 CH 1 OUT P A6 A_VDDTX1_L I - - D7 A_HDOUTN1_L O - - PCS 360 CH 1 OUT N A5 A_VDDOB1_L I - - C5 A_HDOUTN0_L O - - PCS 360 CH 0 OUT N A4 A_VDDOB0_L I - - C4 A_HDOUTP0_L O - - PCS 360 CH 0 OUT P A3 A_VDDTX0_L I - - E6 A_HDINN0_L I - - PCS 360 CH 0 IN N B4 A_HDINP0_L I - - PCS 360 CH 0 IN P B3 A_VDDIB0_L I - - C3 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-20 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet A_VDDRX0_L I - - D6 NC - - - M4 NC - - - J3 NC - - - P5 NC - - - AB3 NC - - - AH9 NC - - - AG10 NC - - - AF12 NC - - - AG7 NC - - - AK27 NC - - - AJ24 NC - - - AB30 NC - - - AA28 NC - - - P24 NC - - - K28 NC - - - P23 NC - - - L28 NC - - - E19 NC - - - G21 NC - - - G20 NC - - - G19 NC - - - F9 NC - - - A11 NC - - - G7 VCC12 VCC12 - - H8 VCC12 VCC12 - - T8 VCC12 VCC12 - - AB9 VCC12 VCC12 - - AC8 VCC12 VCC12 - - AB22 VCC12 VCC12 - - AC23 VCC12 VCC12 - - R23 VCC12 VCC12 - - H23 VCC12 VCC12 - - H15 VTT_2 VTT_2 - - L24 VTT_2 VTT_2 - - T23 VTT_3 VTT_3 - - AC24 VTT_3 VTT_3 - - T25 VTT_3 VTT_3 - - W25 VTT_4 VTT_4 - - AD24 VTT_4 VTT_4 - - AE17 VTT_4 VTT_4 - - AE18 VTT_5 VTT_5 - - AC15 VTT_5 VTT_5 - - AD16 VTT_5 VTT_5 - - AE9 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-21 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet VTT_6 VTT_6 - - AA6 VTT_6 VTT_6 - - T7 VTT_6 VTT_6 - - W6 VTT_7 VTT_7 - - L7 VTT_7 VTT_7 - - P7 VCC VCC - - AA10 VCC VCC - - AA11 VCC VCC - - AA12 VCC VCC - - AA13 VCC VCC - - AA14 VCC VCC - - AA17 VCC VCC - - AA18 VCC VCC - - AA19 VCC VCC - - AA20 VCC VCC - - AA21 VCC VCC - - AA22 VCC VCC - - AA9 VCC VCC - - AB10 VCC VCC - - AB21 VCC VCC - - J10 VCC VCC - - J21 VCC VCC - - K10 VCC VCC - - K11 VCC VCC - - K12 VCC VCC - - K13 VCC VCC - - K14 VCC VCC - - K17 VCC VCC - - K18 VCC VCC - - K19 VCC VCC - - K20 VCC VCC - - K21 VCC VCC - - K22 VCC VCC - - K9 VCC VCC - - L10 VCC VCC - - L21 VCC VCC - - M10 VCC VCC - - M21 VCC VCC - - N10 VCC VCC - - N21 VCC VCC - - P10 VCC VCC - - P21 VCC VCC - - U10 VCC VCC - - U21 VCC VCC - - V10 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-22 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet VCC VCC - - V21 VCC VCC - - W10 VCC VCC - - W21 VCC VCC - - Y10 VCC VCC - - Y21 VCCAUX VCCAUX - - H11 VCCAUX VCCAUX - - H12 VCCAUX VCCAUX - - H19 VCCAUX VCCAUX - - H20 VCCAUX VCCAUX - - M23 VCCAUX VCCAUX - - M24 VCCAUX VCCAUX - - N23 VCCAUX VCCAUX - - N24 VCCAUX VCCAUX - - U23 VCCAUX VCCAUX - - U24 VCCAUX VCCAUX - - V23 VCCAUX VCCAUX - - V24 VCCAUX VCCAUX - - W23 VCCAUX VCCAUX - - W24 VCCAUX VCCAUX - - AC17 VCCAUX VCCAUX - - AC18 VCCAUX VCCAUX - - AC19 VCCAUX VCCAUX - - AD17 VCCAUX VCCAUX - - AD18 VCCAUX VCCAUX - - AD19 VCCAUX VCCAUX - - AC12 VCCAUX VCCAUX - - AC13 VCCAUX VCCAUX - - AC14 VCCAUX VCCAUX - - AD12 VCCAUX VCCAUX - - AD13 VCCAUX VCCAUX - - AD14 VCCAUX VCCAUX - - U7 VCCAUX VCCAUX - - U8 VCCAUX VCCAUX - - V7 VCCAUX VCCAUX - - V8 VCCAUX VCCAUX - - W7 VCCAUX VCCAUX - - W8 VCCAUX VCCAUX - - M7 VCCAUX VCCAUX - - M8 VCCAUX VCCAUX - - N7 VCCAUX VCCAUX - - N8 VCCIO1 VCCIO1 - - H10 VCCIO1 VCCIO1 - - H21 VCCIO1 VCCIO1 - - H22 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-23 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet VCCIO1 VCCIO1 - - H9 VCCIO1 VCCIO1 - - J11 VCCIO1 VCCIO1 - - J12 VCCIO1 VCCIO1 - - J13 VCCIO1 VCCIO1 - - J14 VCCIO1 VCCIO1 - - J15 VCCIO1 VCCIO1 - - J16 VCCIO1 VCCIO1 - - J17 VCCIO1 VCCIO1 - - J18 VCCIO1 VCCIO1 - - J19 VCCIO1 VCCIO1 - - J20 VCCIO2 VCCIO2 - - J23 VCCIO2 VCCIO2 - - J24 VCCIO2 VCCIO2 - - K23 VCCIO2 VCCIO2 - - K24 VCCIO2 VCCIO2 - - L22 VCCIO2 VCCIO2 - - L23 VCCIO2 VCCIO2 - - M22 VCCIO2 VCCIO2 - - N22 VCCIO2 VCCIO2 - - P22 VCCIO2 VCCIO2 - - R22 VCCIO3 VCCIO3 - - AA23 VCCIO3 VCCIO3 - - AA24 VCCIO3 VCCIO3 - - AB23 VCCIO3 VCCIO3 - - AB24 VCCIO3 VCCIO3 - - T22 VCCIO3 VCCIO3 - - U22 VCCIO3 VCCIO3 - - V22 VCCIO3 VCCIO3 - - W22 VCCIO3 VCCIO3 - - Y22 VCCIO3 VCCIO3 - - Y23 VCCIO3 VCCIO3 - - Y24 VCCIO4 VCCIO4 - - AB16 VCCIO4 VCCIO4 - - AB17 VCCIO4 VCCIO4 - - AB18 VCCIO4 VCCIO4 - - AB19 VCCIO4 VCCIO4 - - AB20 VCCIO4 VCCIO4 - - AC20 VCCIO4 VCCIO4 - - AC21 VCCIO4 VCCIO4 - - AC22 VCCIO4 VCCIO4 - - AD20 VCCIO4 VCCIO4 - - AD21 VCCIO4 VCCIO4 - - AD22 VCCIO5 VCCIO5 - - AB11 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-24 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet VCCIO5 VCCIO5 - - AB12 VCCIO5 VCCIO5 - - AB13 VCCIO5 VCCIO5 - - AB14 VCCIO5 VCCIO5 - - AB15 VCCIO5 VCCIO5 - - AC10 VCCIO5 VCCIO5 - - AC11 VCCIO5 VCCIO5 - - AC9 VCCIO5 VCCIO5 - - AD10 VCCIO5 VCCIO5 - - AD11 VCCIO5 VCCIO5 - - AD9 VCCIO6 VCCIO6 - - AA7 VCCIO6 VCCIO6 - - AA8 VCCIO6 VCCIO6 - - AB7 VCCIO6 VCCIO6 - - AB8 VCCIO6 VCCIO6 - - T9 VCCIO6 VCCIO6 - - U9 VCCIO6 VCCIO6 - - V9 VCCIO6 VCCIO6 - - W9 VCCIO6 VCCIO6 - - Y7 VCCIO6 VCCIO6 - - Y8 VCCIO6 VCCIO6 - - Y9 VCCIO7 VCCIO7 - - J7 VCCIO7 VCCIO7 - - J8 VCCIO7 VCCIO7 - - K7 VCCIO7 VCCIO7 - - K8 VCCIO7 VCCIO7 - - L8 VCCIO7 VCCIO7 - - L9 VCCIO7 VCCIO7 - - M9 VCCIO7 VCCIO7 - - N9 VCCIO7 VCCIO7 - - P9 VCCIO7 VCCIO7 - - R9 GND GND - - A1 GND GND - - A30 GND GND - - AA15 GND GND - - AA16 GND GND - - AK1 GND GND - - AK30 GND GND - - K15 GND GND - - K16 GND GND - - L11 GND GND - - L12 GND GND - - L13 GND GND - - L14 GND GND - - L15 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-25 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet GND GND - - L16 GND GND - - L17 GND GND - - L18 GND GND - - L19 GND GND - - L20 GND GND - - M11 GND GND - - M12 GND GND - - M13 GND GND - - M14 GND GND - - M15 GND GND - - M16 GND GND - - M17 GND GND - - M18 GND GND - - M19 GND GND - - M20 GND GND - - N11 GND GND - - N12 GND GND - - N13 GND GND - - N14 GND GND - - N15 GND GND - - N16 GND GND - - N17 GND GND - - N18 GND GND - - N19 GND GND - - N20 GND GND - - P11 GND GND - - P12 GND GND - - P13 GND GND - - P14 GND GND - - P15 GND GND - - P16 GND GND - - P17 GND GND - - P18 GND GND - - P19 GND GND - - P20 GND GND - - R10 GND GND - - R11 GND GND - - R12 GND GND - - R13 GND GND - - R14 GND GND - - R15 GND GND - - R16 GND GND - - R17 GND GND - - R18 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-26 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet GND GND - - R19 GND GND - - R20 GND GND - - R21 GND GND - - T10 GND GND - - T11 GND GND - - T12 GND GND - - T13 GND GND - - T14 GND GND - - T15 GND GND - - T16 GND GND - - T17 GND GND - - T18 GND GND - - T19 GND GND - - T20 GND GND - - T21 GND GND - - U11 GND GND - - U12 GND GND - - U13 GND GND - - U14 GND GND - - U15 GND GND - - U16 GND GND - - U17 GND GND - - U18 GND GND - - U19 GND GND - - U20 GND GND - - V11 GND GND - - V12 GND GND - - V13 GND GND - - V14 GND GND - - V15 GND GND - - V16 GND GND - - V17 GND GND - - V18 GND GND - - V19 GND GND - - V20 GND GND - - W11 GND GND - - W12 GND GND - - W13 GND GND - - W14 GND GND - - W15 GND GND - - W16 GND GND - - W17 GND GND - - W18 GND GND - - W19 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-27 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet GND GND - - W20 GND GND - - Y11 GND GND - - Y12 GND GND - - Y13 GND GND - - Y14 GND GND - - Y15 GND GND - - Y16 GND GND - - Y17 GND GND - - Y18 GND GND - - Y19 GND GND - - Y20 VCCIO7 VCCIO7 - - H2 VCCIO7 VCCIO7 - - N4 VCCIO7 VCCIO7 - - N6 VCCIO7 VCCIO7 - - J2 VCCIO7 VCCIO7 - - L2 VCCIO7 VCCIO7 - - H4 VCCIO6 VCCIO6 - - AB2 VCCIO6 VCCIO6 - - AD1 VCCIO6 VCCIO6 - - W4 VCCIO6 VCCIO6 - - AA4 VCCIO5 VCCIO5 - - AE7 VCCIO5 VCCIO5 - - AH6 VCCIO5 VCCIO5 - - AG11 VCCIO5 VCCIO5 - - AJ9 VCCIO4 VCCIO4 - - AJ23 VCCIO4 VCCIO4 - - AG20 VCCIO4 VCCIO4 - - AJ26 VCCIO4 VCCIO4 - - AG23 VCCIO3 VCCIO3 - - AC29 VCCIO3 VCCIO3 - - AA26 VCCIO3 VCCIO3 - - Y28 VCCIO3 VCCIO3 - - AA29 VCCIO2 VCCIO2 - - G30 VCCIO2 VCCIO2 - - J29 VCCIO2 VCCIO2 - - K27 VCCIO2 VCCIO2 - - N25 VCCIO1 VCCIO1 - - F20 VCCIO1 VCCIO1 - - C19 VCCIO1 VCCIO1 - - C12 VCCIO1 VCCIO1 - - F11 GND GND - - H1 GND GND - - L4 GND GND - - M3 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-28 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet GND GND - - N5 GND GND - - K2 GND GND - - M2 GND GND - - P6 GND GND - - G4 GND GND - - H3 GND GND - - AC2 GND GND - - AA3 GND GND - - AE1 GND GND - - Y4 GND GND - - AB4 GND GND - - AA5 GND GND - - AE6 GND GND - - AE8 GND GND - - AH5 GND GND - - AG9 GND GND - - AG6 GND GND - - AF11 GND GND - - AG12 GND GND - - AJ10 GND GND - - AK26 GND GND - - AJ22 GND GND - - AF20 GND GND - - AJ25 GND GND - - AJ27 GND GND - - AF23 GND GND - - AF22 GND GND - - AE27 GND GND - - AA27 GND GND - - AB29 GND GND - - Y26 GND GND - - AC30 GND GND - - Y29 GND GND - - F30 GND GND - - E27 GND GND - - F27 GND GND - - P25 GND GND - - H29 GND GND - - K29 GND GND - - R24 GND GND - - M28 GND GND - - J27 GND GND - - N26 GND GND - - E20 LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-29 Pinout Information Lattice Semiconductor LatticeSC Family Data Sheet GND GND - - E21 GND GND - - F21 GND GND - - F23 GND GND - - G23 GND GND - - D21 GND GND - - D20 GND GND - - E18 GND GND - - C20 GND GND - - C11 GND GND - - A12 GND GND - - E11 GND GND - - F8 GND GND - - G8 GND GND - - D11 GND GND - - D10 GND GND - - H7 GND GND - - F10 GND GND - - E10 NC _ - - AC16 VCC VCC - - J22 VCC VCC - - J9 1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). LFSC25 Logic Signal Connections: 900-Ball ffBGA1 (Continued) Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGAFebruary 2006 Preliminary Data Sheet © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 Ordering Information_01.0 Part Number Description Ordering Information Commercial Industrial Part Number I/Os Grade Package Balls Temp. LUTs (K) LFSC3GA25E-7F900C 378 -7 fpBGA 900 COM 25.4 LFSC3GA25E-6F900C 378 -6 fpBGA 900 COM 25.4 LFSC3GA25E-5F900C 378 -5 fpBGA 900 COM 25.4 Part Number I/Os Grade Package Balls Temp. LUTs (K) LFSCM3GA25EP1-7F900C 378 -7 fpBGA 900 COM 25.4 LFSCM3GA25EP1-6F900C 378 -6 fpBGA 900 COM 25.4 LFSCM3GA25EP1-5F900C 378 -5 fpBGA 900 COM 25.4 Part Number I/Os Grade Package Balls Temp. LUTs (K) LFSC3GA25E-6F900I 378 -6 fpBGA 900 IND 25.4 LFSC3GA25E-5F900I 378 -5 fpBGA 900 IND 25.4 Part Number I/Os Grade Package Balls Temp. LUTs (K) LFSCM3GA25EP1-6F900I 378 -6 fpBGA 900 IND 25.4 LFSCM3GA25EP1-5F900I 378 -5 fpBGA 900 IND 25.4 LF XXX XXX XX E PX – X XXXXXX X Grade C = Commercial I = Industrial SERDES Speed 3GA = 3.8G Supply Voltage E = 1.2V Logic Capacity 15K LUTs 25K LUTs 40K LUTs 80K LUTs 115K LUTs Device Family LatticeSC FPGA LatticeSCM FPGA LF = Lattice FPGA Package* F256 = 256 fpBGA F900 = 900 fpBGA FF1020 = 1020 ffBGA FC1152 = 1152 fcBGA FC1704 = 1704 fcBGA Speed Grade -5 (Slowest) -6 -7 (Fastest) Predefined Function (LatticeSCM Only) P1 = Initial MACO Option *Note: fpBGA = 1.0mm pitch BGA, ffBGA = 1.0mm flip-chip BGA, fcBGA = 1.0mm ceramic flip-chip BGA LatticeSC Family Data Sheet Ordering InformationFebruary 2006 Preliminary Data Sheet © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 Further Information_01.0 For Further Information A variety of technical notes for the LatticeSC family are available on the Lattice web site at www.latticesemi.com. • PURESPEED I/O Usage Guide (TN1088) • LatticeSC sysCLOCK and PLL/DLL User’s Guide (TN1098) • On-Chip Memory Usage Guide for LatticeSC Devices (TN1094) • LatticeSC DDR/DDR2 SDRAM Memory Interface User’s Guide (TN1099) • LatticeSC QDR-II SRAM Memory Interface User’s Guide (TN1096) • LatticeSC sysCONFIG Usage Guide (TN1080) • LatticeSC MPI/System Bus (TN1085) • Power Calculations and Considerations for LatticeSC Devices (TN1101) For further information on Interface standards refer to the following web sites: • JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org • Hyper Transport: www.hypertransport.org • Optical Interface (SPI-4.2, XSBI, CSIX and XGMII): www.oiforum.com • RAPIDIO: www.rapidio.org • PCI/PCIX: ww.pcisig.com LatticeSC Family Data Sheet Supplemental Information Power 2You A Guide to Power Supply Management and Control Shyam Chandra LEARN HOW TO: » Reduce Power Management Costs » Increase System Reliability » Reduce the Risk of Circuit Board Respins Board Power Management Functionsi Power 2 You A Guide to Power Supply Management and Control Shyam Chandraii Copyright © 2010 Lattice Semiconductor Corporation, 5555 NE Moore Court, Hillsboro, Oregon 97124, USA. All rights reserved. Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, ispPAC, PAC, PAC-Designer are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Revision History: April 2010: First Edition September 2010: Second Edition While every precaution has been taken in the preparation of this book, the author assumes no responsibility for errors or omissions, or for damages resulting from the use of the information contained herein. ACKNOWLEDGEMENTS It takes a team of hardworking professionals to take a collection of documents, ideas, and diagrams and turn them into a finished book. Many thanks to Brian Kiernan, Buck Bartel, Chris Dix, Ed Coughlin, Ed Ramsden, Gordon Hands, Jeff Davis, Jim Krebs, John Alberts, Mark van Wyk, Nancy Knowlton, Shoji Sugawara, Ted Marena, Troy Scott, and Vesa Lauri. The contributions and efforts of these individuals helped to make the dream of this book a reality. ISBN: 978-0-578-06604-2iii Chapter 1. Introduction .......................................................1-1 1.1 Power 2 You............................................................................................................................................ 1-1 What is Power Management?.............................................................................................................. 1-1 Typical Board Power Supply Architectures ........................................................................................ 1-2 Typical Power Management Implementations and Their Drawbacks................................................. 1-4 1.2 Lattice Power Manager II IC Family ...................................................................................................... 1-5 1.3 PAC-Designer Software.......................................................................................................................... 1-8 1.4 Summary of Chapters.............................................................................................................................. 1-8 Chapter 2. Solutions Summary ..........................................2-1 2.1 N-Supply Supervisor, Reset Generator and Watchdog Timer................................................................ 2-1 2.2 Power Supply Sequencing ...................................................................................................................... 2-3 Flexible N-Supply Sequencing............................................................................................................ 2-3 Sequencing with MOSFETs and DC-DC Enables .............................................................................. 2-4 2.3 Hot-Swap Controllers ............................................................................................................................. 2-6 Hot-Swap Controller Using Soft-Start Mechanism............................................................................. 2-6 Hot-Swap Controller with Hysteretic Current Limit Mechanism ....................................................... 2-7 12V/24V Hot-Swap Controller............................................................................................................ 2-8 Negative Supply Hot-Swap Controller................................................................................................ 2-9 CompactPCI Board Management...................................................................................................... 2-11 CompactPCI Express Board Management ........................................................................................ 2-12 2.4 Redundant Supply Management ........................................................................................................... 2-14 Two Rail 5V Power Supply OR’ing (Using MOSFETs) .................................................................. 2-14 Table of ContentsTable of Contents iv Power Supply OR’ing of N-Rails Using MOSFETS ........................................................................ 2-15 N-rail (12V/24V) OR’ing .................................................................................................................. 2-16 -48V Supply OR’ing Through MOSFETS........................................................................................ 2-17 2.5 Power Feed Controllers......................................................................................................................... 2-19 Dual Rail -48V Power Feed Controller ............................................................................................. 2-19 Three-Channels of a 6V-24V Power Feed System............................................................................ 2-20 Two-Channel +12V & 3.3V Power Feed With Diode OR’ing ......................................................... 2-21 2.6 Trimming and Margining...................................................................................................................... 2-23 Chapter 3. Reset Generators & Supervisors.....................3-1 3.1 Introduction............................................................................................................................................. 3-1 Reliable Reset Generation by Monitoring All Supply Rails ............................................................... 3-2 Parts of a Supervisor IC....................................................................................................................... 3-3 Effect of Monitoring Accuracy on System Functionality ................................................................... 3-4 Reduced Accuracy Results in Reducing the Power Supply Tolerance Headroom ............................................................................................................................................ 3-6 Using a Supervisor IC With an Accuracy Of 1%................................................................................ 3-6 Effects of Fault Detection Delay ......................................................................................................... 3-6 If the Fault Detection Delay is 1ms:.................................................................................................... 3-7 If the Fault Detection Delay is 50µs:................................................................................................... 3-7 Supervisors Built Using ADC and a Microcontroller are Slow .......................................................... 3-8 Other Factors Contributing to Increased Reliability............................................................................ 3-8 3.2 N-Supply Supervisor, Reset Generator and Watchdog Timer.............................................................. 3-10 Circuit Operation ............................................................................................................................... 3-10 Reset Generator, Supervisor and Watchdog Timer Algorithm......................................................... 3-11 Parallel Equations of the Algorithm .................................................................................................. 3-11 Programmable Features ..................................................................................................................... 3-11 Additional Features That Can be Added to ProcessorPM-POWR605 ............................................. 3-11 Relevant Power Manager II ICs ........................................................................................................ 3-11 Chapter 4. Power Supply Sequencing...............................4-1 4.1 Introduction............................................................................................................................................. 4-1 Sequencing Power Supplies with Conflicting Sequencing Requirements....................................................................................................................................... 4-1 Other Factors Adding Complexity to Sequencing Algorithm............................................................. 4-2 4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices ..................................................... 4-3 Voltages are Monitored During/After Sequencing.............................................................................. 4-3 N-Supply Closed Loop Sequencing Algorithm................................................................................... 4-5 N-supply Closed Loop Sequencing with Failure Monitor Algorithm................................................. 4-6 Applying LogiBuilder Instructions to Sequencing Methods............................................................... 4-6 Advantages of Power Manager II-based Supply Sequencing ............................................................. 4-8 Table of Contents v Additional Power Management Functions that can be Integrated into Power Manager II ................. 4-8 Applicable Power Manager II Devices................................................................................................ 4-8 4.3 Sequencing With MOSFETs and DC-DC Converter Enables................................................................ 4-9 Circuit Operation ................................................................................................................................. 4-9 Power Sequencing Algorithm............................................................................................................ 4-10 Applicable Power Manager II Devices.............................................................................................. 4-10 Chapter 5. Hot-Swap Controllers .......................................5-1 5.1 What is a Hot-Swap Controller? ............................................................................................................. 5-1 Hot-Swap Circuit Design Considerations............................................................................................ 5-2 5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices .................... 5-2 Hot-Swap Controller Using Soft-start ................................................................................................. 5-3 Hot-Swap Controller with Hysteretic Current Limit Mechanism ....................................................... 5-4 12V/24V Hot-Swap Controller............................................................................................................ 5-8 5.3 Implementing a Negative Supply Hot-Swap Controller ....................................................................... 5-13 Controlling Current Inrush While Operating the MOSFET in its Safe Operating Area ................... 5-14 Customizing the -48V Hot-Swap Controller..................................................................................... 5-15 5.4 CompactPCI Board Management ......................................................................................................... 5-16 CompactPCI Express Board Management ........................................................................................ 5-19 Chapter 6. Power Supply OR’ing Controllers ...................6-1 6.1 What is Power Rail OR'ing? ................................................................................................................... 6-1 6.2 Challenges of Designing a MOSFET OR’ing Circuit .......................................................................... 6-2 6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit ......................................................................... 6-3 6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS ....................................... 6-5 6.5 N-rail (12V/24V) OR’ing......................................................................................................................... 6-7 6.6 -48V Supply OR’ing Through MOSFETS ............................................................................................ 6-10 Chapter 7. Power Feed Controllers....................................7-1 7.1 What are Power Feed Controllers? ......................................................................................................... 7-1 7.2 Dual Rail -48V Supply Feed................................................................................................................... 7-1 Circuit Operation ................................................................................................................................. 7-2 Algorithm............................................................................................................................................. 7-3 Programmable Features of this Circuit................................................................................................ 7-4 Applicable devices:.............................................................................................................................. 7-4 7.3 Three Channels of a +12V Power Feed System ..................................................................................... 7-4 Circuit Operation ................................................................................................................................. 7-5 Dual Current Level Hysteretic Control ............................................................................................... 7-6 Algorithm for Each Power Feed Channel............................................................................................ 7-7 Programmable Features of Power Feed............................................................................................... 7-7Table of Contents vi Integrating Other Payload Power Management Functions into the ispPAC-POWR1014A Device ... 7-7 Applicable Power Manager II Devices................................................................................................ 7-8 7.4 2-Channel +12V & 3.3V Power Feed With MOSFET OR’ing .............................................................. 7-8 Circuit Operation ................................................................................................................................. 7-9 During Operation......................................................................................................................................... 7- ispPAC-POWR1014A (MicroTCA) Power Feed Algorithm............................................................ 7-10 Programmable Features ............................................................................................................................. 7- Other Functional Enhancements........................................................................................................ 7-11 Applicable Power Manager II Devices.............................................................................................. 7-11 Chapter 8. Margining and Trimming ..................................8-1 8.1 What is Voltage Margining? ................................................................................................................... 8-1 8.2 Voltage Margining Implementation........................................................................................................ 8-1 8.3 What is Trimming? ................................................................................................................................. 8-2 Typical Applications That Require Power Supply Trimming............................................................. 8-3 8.4 Trimming and Margining – Principle of Operation ................................................................................ 8-3 Power Manager II TrimCell Architecture ........................................................................................... 8-4 Power Manager II Integrates Multiple TrimCells ............................................................................... 8-6 Closed Loop Trim - Mode Operation of TrimCell.............................................................................. 8-7 Closed Loop Trim and Closed Loop Margining Using a Microcontroller.......................................... 8-8 Interfacing Power Manager II with a DC-DC converter ..................................................................... 8-9 Designing Trimming and Margining Networks using PAC-Designer Software............................... 8-11 Creating a DC-DC Converter Library Entry ..................................................................................... 8-11 Chapter 9. Design Tools for Power Manager II .................9-1 9.1 PAC-Designer: Power Management Design Tool .................................................................................. 9-1 Benefits of Software-Driven Programmable Hardware Design.......................................................... 9-2 9.2 PAC-Designer Overview ........................................................................................................................ 9-3 Selecting the Power Manager II Device from a Design Specification................................................ 9-3 Power Manager II Design Example..................................................................................................... 9-5 Design Flow......................................................................................................................................... 9-6 9.3 Example Design Resources..................................................................................................................... 9-6 9.4 Designing PCI-Express Add-on Card Power Management Using an ispPAC-POWR1014A Device ... 9-7CHAPTER 1 1-1 Introduction 1.1 Power 2 You This book provides technical details and design considerations for implementing the common circuit board power management functions shown as 3-D blocks in Figure 1-1 and Figure 1-2. This book also provides generalized cost effective solutions for each of these functions that can be customized to meet a circuit board’s specific voltage, current and control environment. For readers viewing this document in .pdf format, the 3-D blocks in Figure 1-1 and Figure 1-2 are hyperlinked to the appropriate section of Chapter 2, where multiple circuit options are provided for that particular power management function. Each of the circuit options hyperlink to a detailed description in the relevant chapters. If you are already familiar with Lattice Semiconductor Power Manager II devices and need to find a solution for a power management function: 1. Click on the required power management block in Figure 1-1. 2. You will automatically navigate to the section of Chapter 2 that provides multiple circuit options for the selected power management function. 3. Click on the relevant circuit option. 4. You will automatically navigate to the detailed description of that circuit diagram. If you wish to read about the general board power management blocks, the design criteria and circuit options, read this chapter. After reading this chapter, you can skip Chapter 2 - “Solutions Summary” on page 2-1 and continue with Chapter 3 - “Reset Generators & Supervisors” on page 3-1. What is Power Management? Every circuit board is powered from one or more sources called the input, or primary, power supplies. And, every circuit board performs one or more functions using a number of ICs, such as ASICs, CPUs, FPGAs, and so on. These ICs are called the payload ICs. The circuit board generates multiple power rails from the input supplies to power these payload ICs, using board Power 2 You: A Guide to Power Supply Management and Control 1-2 Introduction mounted supplies called primary and secondary supplies. The term ‘Power Management’ in this book includes all power rail control functions implemented in a circuit board. Typically, input power rails are controlled by power management functions such as hot-swap control and redundant power rail control. On the payload side, power management functions include sequencing, monitoring, supervisory signal generation, trimming and margining. Typical Board Power Supply Architectures Circuit boards can be broadly classified into two types: 1. Boards that derive input power supply from a backplane with its power always on and the boards plugged into or extracted from the backplane without turning the power off – these are called hotswappable boards, shown in Figure 1-1. 2. Boards that derive power from an external power supply that is turned on after the board is connected and is turned off before the board is disconnected – these are called non hot-swappable boards. There are solutions to implement all of the critical power supply control functions. Advanced power supply designers can click on any of the hyperlinked functions to see the solution. To learn the background of all these functions, continue reading this chapter. Figure 1-1. Power Management in a Hot-Swappable Circuit Board. (If viewing this document in .pdf format, click on any of the 3-D blocks to jump to implementation details.) Figure 1-1 illustrates the power supply architecture of a circuit board with the common power management blocks shown in 3-D. A hot-swappable board derives its power from one or more supplies from the backplane. There can be more than one set of supplies sourced from the backplane, so these boards are operational even when one of the supplies fails. The backplane supplies in Figure 1-1 are also called the primary supplies. In systems that require high availability, such as telecom / datacom systems, backplanes provide redundant supplies called on-line and standby power. The Power Supply OR’ing Controller, also called the redundant power supply controller, selects between the online and standby supplies to derive the power to the board. (Refer to “2.4 Redundant Supply Management” on page 2-14.) In order to extract and reinsert the boards from the backplane without disturbing the other boards plugged into the same backplane, a hot-swap controller function is implemented on each of these circuit boards. Hot-Swap Controller DC-DC Primary Sequence Control Monitor Voltage & Current Reset Generation DC-DC Secondary DC-DC Secondary DC-DC Secondary Power Supply OR’ing Controller DC-DC Primary DC-DC Primary Trimming & Margining Backplane Power Payload ICs Sequencing Thru MOSFETs Chapter 6 Chapter 5 Chapter 4 Power Feed to External Chapter 7 Systems Chapter 3 Chapter 8Power 2 You: A Guide to Power Supply Management and Control Introduction 1-3 Introduction (Refer to “2.3 Hot-Swap Controllers” on page 2-6.) In some cases, the supply rail output from the hotswap controller feeds one or more DC-DC converters, shown in Figure 1-1 as ‘DC-DC Primary’ supplies. Primary supplies are used to derive one or more main payload supply rails, which are also called secondary supply rails and are shown in Figure 1-1 as the ‘DC-DC Secondary’ supplies. These secondary supplies may have to be sequenced either through the DC-DC converter enable signals or through MOSFETs. Sequencing of these supplies is controlled by the sequence controller. (Refer to “2.2 Power Supply Sequencing” on page 2-3.) After all supplies are sequenced, the reset generator starts the board’s normal operation by releasing the reset signal to the CPU. (Refer to “2.1 N-Supply Supervisor, Reset Generator and Watchdog Timer” on page 2-1.) The voltage and current are monitored for faults and board shut down or reset generation functions are initiated as a result. (Refer to “2.1 N-Supply Supervisor, Reset Generator and Watchdog Timer” on page 2-1.) In addition, monitoring these lower voltages for faults should take into consideration, and compensate for, other error sources such as the ground voltage difference between the supply and the monitoring device. For example, the fault level of 1.2V is 1.2V * 5% = ±60mV. The ground voltage difference between different points in the circuit board can be be as much as 20mV to 30mV. To compensate for the error, differential sensing, as shown in Figure 3-9 on page 9, is used. Modern ICs require lower core voltages (1.2V or lower) with high current capacity (10A or higher) with reduced voltage tolerance. To meet these stringent supply requirements, a power supply trimming controller is often required. (Refer to “2.6 Trimming and Margining” on page 2-23.) For quality assurance purposes, four-corner testing of boards (voltage and temperature) frequently requires margining of supplies. These boards use margining controllers. (Refer to “2.6 Trimming and Margining” on page 2-23.) In some applications, such as GSM basestation boards, microwave boards and boards supporting hotpluggable mezzanine cards, it may be necessary to power an external unit, such as a remote radio head or an outdoor antenna, or supply power to an AMC. To support these functions, the power feed controller is required. (Refer to “2.5 Power Feed Controllers” on page 2-19.) Figure 1-2 shows the power management requirements in a non hot-swappable circuit board. These boards require primary and secondary power management controllers, as shown in Figure 1-2. The only primary power management function that is not relevant in these non-hot-swappable boards is the hotswap controller. Systems that typically require non-hot-swappable boards include routers in “pizza-box” form factor, personal computers and medical ultrasound systems.Power 2 You: A Guide to Power Supply Management and Control 1-4 Introduction Figure 1-2. Power Management in a Non-Hot-Swappable Circuit Board. (If viewing this document in .pdf format, click on any of the 3-D blocks to jump to implementation details.) Typical Power Management Implementations and Their Drawbacks The power rails in a board currently are managed by simple, single function integrated circuits (ICs) on both the primary and secondary sides. On the input side, each function shown in Figure 1-1 requires different ICs, depending on the rail voltage, board power and other control specifications. Modern circuit boards with complex payload ICs typically require five or more secondary power rails. Monitoring, sequencing and the generation of resets in these boards require multiple single function ICs. Together, the power management section requires multiple types of single function power management ICs in a given system. This results in a larger bill of materials (BOM), higher cost of inventory and assembly, as well as reduced reliability. The cost of the power management portion in a circuit board increases with the number of rails, and the number of power management functions. Lower cost single function power management ICs are usually less accurate in monitoring for faults, resulting in reduced board reliability. In order to reduce the number of secondary power management ICs, some designs use microcontrollers with an Analog-to-Digital (ADC) converter to monitor power supplies and use software to adapt to board-specific requirements. These microcontrollers are too slow to respond to power supply faults (5 to 10ms) and are unreliable, as they use hundreds of lines of code to perform power management functions and require a watchdog timer to monitor software flow. Microcontrollers are also used because the changes to power management can be met simply by changing software, as opposed to modifying the circuit board layout. However, modifications to software are almost always avoided, as most companies have strict control over software releases. The ideal power management solution is the one that has the following characteristics: 1. Lower cost and reduced bill of material, and flexibility to meet individual board power management needs. 2. Increased board reliability through increased supply fault monitoring accuracy. DC-DC Primary Sequence Control Monitor Voltage & Current Reset Generation DC-DC Secondary DC-DC Secondary DC-DC Secondary Power Supply OR’ing Controller DC-DC Primary DC-DC Primary Trimming & Margining Input Supply Payload ICs Sequencing Thru MOSFETs Chapter 6 Chapter 4 Power Feed to External Systems Chapter 7 Chapter 3 Chapter 8Power 2 You: A Guide to Power Supply Management and Control Introduction 1-5 Introduction 3. Reduced risk of circuit board re-layout to board power management through programmability. This book details how a Lattice Power Manager II device can integrate all of these functions. Because these devices are in-system programmable, each device can be programmed to meet a wide variety of circuit board functions. 1.2 Lattice Power Manager II IC Family There are five members in the Power Manager II family of devices: ispPAC® -POWR1220AT8, ispPACPOWR1014A, ispPAC-POWR1014, ispPAC-POWR607 and ProcessorPM™-POWR605. Figure 1-3 shows the part numbering convention of the Lattice Power Manager II product family. Figure 1-3. Lattice Power Manager II Family Part Numbers Indicate I/O Resources While the largest device, the ispPAC-POWR1220AT8, can be used to implement complex power management functions, the smallest device, the ProcessorPM-POWR605, can be used to implement power management functions for a wide variety of microprocessors and DSPs. All Power Manager II devices can be programmed in-system through the JTAG interface. The power management algorithm can be designed using the PAC-Designer® software tool that can be downloaded from the Lattice website free of charge. Figure 1-4 shows the architecture of the largest member of the family, the ispPAC-POWR1220AT8. Figure 1-4. ispPAC-POWR1220AT8 Device Block Diagram Digital Outputs ispPAC-POWR XX YY A T 8 Trim Outputs Trimming if Present ADC if Present Analog Inputs 4 X High Voltage MOSFET Driver 16 Open Drain Outputs 6 Digital Inputs I 2 C Interface Timers & Oscillator ADC (10-bit ) Non-Volatile Configuration JTAG 8X Margin/ Trim Control 8 Margin/Trim • Closed Loop Trim • Precision Output Voltage Control (<1%) 12 Voltage Monitors • 2 Comparators Per Rail • UV & OV • Differential Voltage Sense • Programmable Thresholds • Range - 0.67V to 5.7V • 368 Steps • Accuracy 0.2% (Typ.) 20 Outputs • 4 Programmable MOSFET Drivers • 16 Digital Open-Drain Controls 100-pin TQFP Package 48 Macrocell PLDPower 2 You: A Guide to Power Supply Management and Control 1-6 Introduction This device can manage up to 12 supply rails and generate 20 outputs (including four programmable MOSFET drive outputs) using its on-chip 48-macrocell ruggedized CPLD. All supply voltages can be measured using the on-chip 10-bit ADC device via the I2 C interface. This device also supports trimming and margining of up to eight DC-DC converters. Various time delays used in the power management algorithm can be realized by four on-chip programmable hardware timers. The ispPAC-POWR1220AT8 device can integrate the following power management functions: • Power supply OR’ing • Positive rail power feed to external system • Hot-swap controller for positive voltage rail • Sequencing • Voltage and current monitoring • Reset generation • Trimming and margining • Watchdog timer Figure 1-5 is a block diagram of the next members of the Lattice Power Manager II family, the ispPACPOWR1014 and ispPAC-POWR1014A. Figure 1-5. Block Diagram of ispPAC-POWR1014 & ispPAC-POWR1014A Devices These devices can monitor up to 10 supply rails and generate 14 power management control outputs (including two programmable MOSFET drivers) using an on-chip 24-macrocell PLD block. The ispPACPOWR1014A device provides a 10-bit ADC and an I2 C interface to measure all supply voltages. Various time delays used in the power management algorithm can be realized by four on-chip programmable hardware timers. The ispPAC-POWR1014/A devices can integrate the following power management functions: 2 X High Voltage MOSFET Driver 12 Open Drain Outputs 4 Digital Inputs I 2 C* Interface Timers & Oscillator ADC* (10-bit ) Non-Volatile Configuration JTAG * ADC and I2 C Interface in ispPAC-POWR1014A only. 10 Voltage Monitors • 20 Precision Comparators • Programmable Thresholds • Range - 0.67V to 5.7V • 368 Steps • Accuracy 0.3% (Typ.) 14 Outputs • 2 Programmable MOSFET Drivers • 12 Digital Open-Drain Controls 48-pin TQFP Package 24 Macrocell PLDPower 2 You: A Guide to Power Supply Management and Control Introduction 1-7 Introduction • Power Supply OR’ing • Hot-swap controller for positive voltage rail • Positive or negative power feed controller • Sequencing • Voltage and current monitoring • Reset generation, sequencing • Watchdog timer The ispPAC-POWR607 device shown in Figure 1-6 can monitor up to six supplies and supports seven outputs (including two MOSFET drivers) that are controlled by the on-chip 16-macrocell PLD. Various time delays used in the power management algorithm can be realized by four on-chip programmable hardware timers. Figure 1-6. Block Diagram of an ispPAC-POWR607 Device This device can be powered down using a digital signal. The ispPAC-POWR607 device can be used for the following functions: • Power Supply OR’ing • Hot-swap controller for positive voltage rail • Hot-swap controller for negative voltage rail • Positive or negative power feed controller sequencing • Reset generation • Watchdog timer Figure 1-7 shows the ProcessorPM-POWR605 device, which is ideal for implementing power management functions for any processor or DSP. This device can monitor up to six supplies and generate five outputs that are controlled by the on-chip 16-macrocell PLD. Various time delays used in the power management algorithm can be realized by four on-chip programmable hardware timers. 2 X High Voltage MOSFET Driver 5 Open Drain I/O 2 Digital Inputs Timers & Oscillator Non-Volatile Configuration JTAG Power Down Control Powered-Down Mode < 10µA 6 Voltage Monitors • Programmable Thresholds • Range - 0.67V to 5.7V • 192 Steps • Accuracy 0.5% (Typ.) 7 Outputs • 2 Programmable MOSFET Drivers • 5 Digital Open-Drain I/O 32-pin QFN Package 16 Macrocell PLDPower 2 You: A Guide to Power Supply Management and Control 1-8 Introduction Figure 1-7. Architecture of the ProcessorPM-POWR605 Device The ProcessorPM-POWR605 device can be used to integrate the following functions: • Voltage supervision • Reset generation • Watchdog timer 1.3 PAC-Designer Software Board-specific power management is implemented using the PAC-Designer software: an intuitive, userfriendly software tool set. The PAC-Designer software enables the following: 1. Configure voltage monitoring thresholds for a given voltage rail. 2. Configure MOSFET driver characteristics to meet turn on and off ramp rates. 3. Implement power management functions such as hot-swap controller, sequencer, reset generator through LogiBuilder (simple configurable sequencer steps and logic equations). 4. Simulate the power management algorithm using either high-end tools such as Aldec® Active-HDL™ or Mentor Graphics® ModelSim™, or use the waveform simulator built into the software. 5. Calculate the resistor values to be connected between the Power Manager II devices and the DC-DC converters for implementing Trimming and Margining functions. 6. Generate JEDEC files and SVF files for programming the device using standard programming methods. 1.4 Summary of Chapters This book has nine chapters. Chapter 3 to Chapter 8 each cover a power management function in detail. Chapter 1 - “Introduction” on page 1-1 – summarizes the power management functions, explains drawbacks of traditional power management solutions, and provides a brief introduction to Lattice Power Manager II products. 5 Open Drain I/O 2 Digital Inputs Timers & Oscillator Non-Volatile Configuration JTAG Power Down Control 5 Outputs • 5 Digital Open-Drain I/O 6 Voltage Monitors • Programmable Thresholds • Range - 0.67V to 5.7V • 192 Steps • Accuracy 0.5% (Typ.) Powered-Down Mode < 10µA 24-pin QFN Package 16 Macrocell PLDPower 2 You: A Guide to Power Supply Management and Control Introduction 1-9 Introduction Chapter 2 - “Solutions Summary” on page 2-1 – is a summary of all of the solutions provided for each of the power management functions shown in Figure 1-1. Chapter 3 - “Reset Generators & Supervisors” on page 3-1 – describes reset generator supervisor and watchdog timer and identifies some of the common pitfalls to avoid in voltage supervision and reset generation in circuit boards with multiple power supplies. Chapter 4 - “Power Supply Sequencing” on page 4-1 – shows how a flexible power supply sequencing arrangement provides a solution. This section also describes software-based sequencing methodology. Chapter 5 - “Hot-Swap Controllers” on page 5-1 – describes design considerations for implementing hotswap controllers and selecting MOSFETs. This chapter also provides hot-swap controller solutions for positive rail, negative rail, and multiple backplane rails. Chapter 6 - “Power Supply OR’ing Controllers” on page 6-1 – describes the design considerations and provides N-rail positive and negative rail OR’ing solutions. Chapter 7 - “Power Feed Controllers” on page 7-1 – provides design considerations for implementing power feed controllers and selecting MOSFETs. N-supply positive and negative rail power feed, and MicroTCA power module design, are also discussed. Chapter 8 - “Margining and Trimming” on page 8-1 – describes the need for trimming and margining of supplies, provides trimming and margining solutions, and describes how to implement these designs using software. Chapter 9 - “Design Tools for Power Manager II” on page 9-1 – describes the software flow, provides a description of each of the steps, and describes software implementation of complex power management designs.Power 2 You: A Guide to Power Supply Management and Control 1-10 Introduction This page intentionally left blank.CHAPTER 2 2-1 Solutions Summary 2.1 N-Supply Supervisor, Reset Generator and Watchdog Timer Features of Supervisor, Reset Generator and Watchdog Timer in a Power Manager II Device • Monitors up to 12 rails for over-voltage / under-voltage faults • Precision (0.2% typ.) programmable monitoring threshold from 0.67V to 5.8V • Differential voltage sensing for monitoring low voltage, high current supplies • Fast fault detection with glitch filtering – up to 64s • Reset generation with programmable pulse stretch of up to hundreds of milliseconds • Low voltage interrupt generation • Manual reset input with programmable de-bounce period • Watchdog timer with programmable time delay from hundreds of milliseconds to minutes • Flexible watchdog timer interrupt / reset signal combinations • All features can be changed after assembly through in-system programming • Over-voltage protection and under-voltage lock-out • Integrates additional functions such as sequencing, hot-swap, trimming and margining • Measures voltage and current through I2 C. (A detailed circuit description of a design using ProcessorPM-POWR605 device is provided in “3.2 N-Supply Supervisor, Reset Generator and Watchdog Timer” on page 3-10.)Power 2 You: A Guide to Power Supply Management and Control 2-2 Solutions Summary Figure 2-1. ProcessorPM-POWR605 Integrating 6-Supply Supervisor, Reset Generator and Watchdog Timer Advantages of Supervisor, Reset Generator and Watchdog Timer in a Power Manager II Device • Lowers cost compared to multiple supervisor and reset ICs • Reduces number of components – No resistors to set threshold, no capacitors to set time delay • Increases functional reliability – Very fast fault detection, higher monitoring precision, fewer components • Reduces spurious supply fault interrupts due to supervisor monitoring threshold accuracy and filtering supply glitches • Reduces risk – Accommodates changes to specs through programmability • Reduces part types – Single chip can be used across a wide range of applications • Protects board against over-voltage faults by initiating shut-down. (A detailed circuit description of a design using ProcessorPM-POWR605 device is provided in “3.2 N-Supply Supervisor, Reset Generator and Watchdog Timer” on page 3-10.) ProcessorPM-POWR605 V#1 V#2 V#6 CPU_Reset WDT_Int Reset_in WDT_Trig VMON1 to VMON6 IN1 IN2 IN_OUT1 IN_OUT2Power 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-3 2.2 Power Supply Sequencing Solutions Summary Flexible N-Supply Sequencing Features of Sequencer Implementation in a Power Manager II Device • Programmable power up and power down sequencing • Shutdown can be initiated through supply fault or an external input • Allows user to change supply turn-on sequence or fine-tune sequence timing in software • Supports multiple types of supply turn-on/off sequencing algorithms • Closed loop sequencing / time-based open loop sequencing / complete sequencing within a given period • Integrates additional functions such as supervision reset generation, watchdog timer, hot-swap, trimming and margining • Measures voltage and current through through I2 C • Sequencing of supplies can be changed after assembly through in-system programming through JTAG. (A detailed circuit description is provided in “4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices” on page 4-3.) Figure 2-2. Flexible N-Supply Sequencing Using the ispPAC-POWR1014A Device Advantages of Integrating Sequencer into a Power Manager II Device • Reduces cost by integrating the sequencing function along with other board power management functions • Minimizes the risk of board re-spin due to change of sequencing algorithm – Can adjust sequencing ADC ispPAC-POWR1014A En V OUT POWER_GOOD Shut_Down N OUT 3 OUT 4 OUT 10 OUT 11 OUT 12 SCL SDA IN1 IN 2 VMON 1 to VMON N Recycle Power En V OUT DC-DC / LDO #1 DC-DC / LDO #2 En V OUT DC-DC / LDO #N Sequence_FailPower 2 You: A Guide to Power Supply Management and Control 2-4 Solutions Summary algorithm after board assembly • Reduces first prototype board bring-up time – By providing additional debug flags such as sequence incomplete, supply turn-on timeout, etc. • Increases board reliability by reducing the number of components – Does not require resistors or capacitors for timing or sequencing threshold adjustment • Reduces the number of ICs required for power management, including sequencing, by meeting the sequencing requirements of a wide variety of boards. (A detailed circuit description is provided in “4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices” on page 4-3.) Sequencing with MOSFETs and DC-DC Enables Features of Sequencer Implementation in a Power Manager II Device • Integrates multiple charge pumps to control high-side N-Channel MOSFETs • Has unified sequencing algorithm using MOSFETs and DC-DC converter enables • Programmable power-up and power-down sequencing • Shutdown can be initiated through supply fault or an external input • Allows user to change supply turn-on sequence or fine-tune sequence timing in software • Supports multiple types of supply turn-on/off sequencing algorithms: • Closed loop sequencing / time-based open-loop sequencing / complete sequencing within a given period • Integrates additional functions such as supervision reset generation, watchdog timer, hot-swap, trimming and margining • Sequencing of supplies can be changed after assembly through in-system programming via JTAG • Measures voltage and current through I2 C. (A detailed circuit description is provided in “4.3 Sequencing With MOSFETs and DC-DC Converter Enables” on page 4-9.)Power 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-5 Solutions Summary Figure 2-3. The ispPAC-POWR1014A Implementing Sequencing with MOSFET and DC-DC Enables Advantages of Integrating Sequencer into a Power Manager II Device • Lowers cost by reducing the number of DC-DC converters as well as integrating sequencing function along with other board power management functions • Minimizes the risk of board re-spin due to change of sequencing algorithm – Adjust sequencing algorithm after board assembly • Reduces board bring-up time by providing additional debug flags such as sequence incomplete and supply turn-on timeout • Increases board reliability by reducing the number of components – Does not require resistors or capacitors for timing or sequencing threshold adjustment • Reduces the number of ICs required for power management, including sequencing by meeting the sequencing requirements of a wide variety of boards. (A detailed circuit description is provided in “4.3 Sequencing With MOSFETs and DC-DC Converter Enables” on page 4-9.) VMON 5 VMON1 to HVOUT 1 OUT 3 OUT 4 OUT 5 Device #1 Device #2 Device #1 Sequence 1. 1.2V 2. 1.8V 3. 3.3V Device #2 Sequence 1. 3.3V 2. 2.5V 3. 1.2V 1.8V En 2.5V En 1.2V En Shut_Dn ispPAC-POWR1014A OUT 6 OUT 7 SCL SDA 3.3V ADC Power Good Failed Q1Power 2 You: A Guide to Power Supply Management and Control 2-6 Solutions Summary 2.3 Hot-Swap Controllers Hot-Swap Controller Using Soft-Start Mechanism Features of Hot-Swap Controller Implementation in a Power Manager II Device • Allows safe insertion into backplane – Programmable contact de-bounce delay • Over-voltage protection and under-voltage lockout • Controls inrush current through programmable soft-start rate feature • Retry on fault with programmable retry period • Backplane voltage status flag to secondary side • Isolates board from backplane due to faults on board. Ramp time can be customized to meet board turnon power requirements. • Backplane voltage range 3V to 5V • Integrate other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining • Measure backplane voltage in addition to other board voltages and currents through I2 C • Management of supplies can be changed after assembly through in-system programming via JTAG • Hot-swap controller can be programmed independently of other ICs on the board. (A detailed circuit description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on page 5-2.) Figure 2-4. Hot-Swap Control Implemented Through MOSFET Ramp Rate Control Advantages of Integrating Hot-Swap Controller into a Power Manager II Device • Lowers cost by integrating other board management functions and reducing the number of power management ICs • Minimizes fault propagation to other boards in the system due to a fault on a circuit board • Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary side Inp_5V Soft_start Backplane Q1 5V Load Start_5V_Load Out_5V VMON1 VMON2 HVOUT1 OUT3 ADC ispPAC-POWR1014A I 2 CPower 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-7 Solutions Summary • Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II devices. (A detailed circuit description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on page 5-2.) Hot-Swap Controller with Hysteretic Current Limit Mechanism Features of Hot-Swap Controller Implementation in a Power Manager II Device • Limits the backplane current to a value during a current inrush event, minimizing power supply dip on the backplane • Two programmable over-current limits: hot-swap event and board operation • Programmable contact de-bounce delay • Over-voltage, over-current protection and under-voltage lockout • Short circuit protection response < 1s • Programmable retry period • Retry on hot-swap fault / secondary supply fault • Early warning about the backplane voltage status to secondary side • Isolates board from backplane due to faults on board • Integrates other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining • Measures backplane voltage in addition to other board voltages and currents through I2 C • Management of supplies can be changed after assembly through in-system programming via JTAG • Hot-swap controller can be programmed independently of other ICs on the board. (A detailed circuit description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on page 5-2.) Figure 2-5. Hot-Swap Controller with Hysteretic Current Limit Inp_5V Hyst_Ctrl Q1 Out_5V I_In Rs +3.3V R1 R2 Short_Ckt IN1 Backplane 5V Load Start_5V_Load ADC ispPAC-POWR1014A SCL SDA VMON1 VMON2 VMON3 OUT3 HVOUT1 IN1 CSA Q2Power 2 You: A Guide to Power Supply Management and Control 2-8 Solutions Summary Advantages of Hot-Swap Controller Integrated into a Power Manager II Device • Reduces board cost by integrating other secondary board power management functions into Power Manager II • Reduces board space taken up by the hot-swap controller by using a smaller hold-off capacitor • Increases system reliability by reducing the peak current during the hot-swap event and during board fault • Minimizes fault propagation to other boards in the system due to a fault on a circuit board • Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary side • Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on page 5-2.) 12V/24V Hot-Swap Controller Features of Hot-Swap Controller Integrated into a Power Manager II Device • Wide operating voltage range – 6V to 24V • Can be used across a wide range of board power – 10W to 200W • Limit the backplane current to a value during current inrush event to meet the safe operating area (SOA) specifications of a MOSFET • Programmable inrush and operating over-current limits independently • Programmable contact de-bounce delay • Over-voltage, over-current protection and under-voltage lockout • Short circuit protection response < 1s • Programmable retry period • Retry on hot-swap fault/ secondary supply fault • Backplane fault early warning • Isolates board from backplane due to faults on board • Integrates other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining. • Measures backplane voltage in addition to other board voltages and currents through I2 C • Management of supplies can be changed after assembly through in-system programming via JTAG • Hot-swap controller can be programmed independently of other ICs on the board. (A detailed circuit description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on page 5-2.)Power 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-9 Solutions Summary Figure 2-6. 12V/24V Hot-Swap Controller Using an ispPAC-POWR1014A Device Advantages of Hot-Swap Controller Integrated Into a Power Manager II Device • Reduces board cost by integrating other secondary board power management functions into Power Manager II, lower cost MOSFET and smaller hold-off capacitor • Reduces board space due to smaller hold-off capacitor • Increases system reliability by reducing the peak current during the hot-swap event as during board fault • Minimizes fault propagation to other boards in the system due to a fault on a circuit board • Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary side • Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on page 5-2.) Negative Supply Hot-Swap Controller Features of the Negative Supply Hot-Swap Controller Implementation • Wide operating voltage range: -35V to -80V • Supports wide range of board power: 10W to 200W • Deterministic current level during hot-swap to meet the SOA specifications of a MOSFET • Programmable inrush current limit • Programmable over-current limit • Short circuit protection response time < 1s Inp_12V Backplane Q1 Out_12V I_In Rs +3.3V R1 R2 Short_Ckt +3.3V D1 Q2 D2 C2 C1 12V Load Start_12V_Load C_Pmp S_Dn Q3 Ch VMON1 VMON2 VMON3 OUT3 HVOUT1 OUT4 ADC ispPAC-POWR1014A SCL IN1 SDA CSAPower 2 You: A Guide to Power Supply Management and Control 2-10 Solutions Summary • Programmable contact de-bounce delay • Over-voltage protection and under-voltage lockout • Enables load after the hot-swap event, further minimizing inrush current • Programmable retry period • Control of hot-swap from the secondary side. • Early fault warning to secondary side • Immune to 100V glitches. (A detailed circuit description is provided in “5.3 Implementing a Negative Supply Hot-Swap Controller” on page 5-13.) Figure 2-7. Hot-Swap Controller Circuit Using an ispPAC-POWR607 Device Advantages of Hot-Swap Controller Integrated into a Power Manager II Device Increases system reliability by: • Limiting inrush current to the programmed value • Limiting current due to secondary side faults to the programmed value • Reducing current glitches on the backplane • Reducing power stress on the MOSFET • Minimizes fault propagation through the system from a faulty card • Reducing overall system cost -48V 43k 3.3k 6V 3.3k 6V .01µF .05(RS) Voltage Regulator ispPAC-POWR607 100k 100 HVOUT2 HVOUT1 VMON6 VMON5 VMON4 VMON3 VMON2 VMON1 GND VCC Vin_High Vin_OK VDS_2 VDS_1 Isense_2 Isense_1 Gate_Drive_2 Gate_Drive_1 Ch IN/OUT3 Enable_Load 43k IN2 Q2 Q3 VCC_607 GND_607 VCC_607 VCC_607 GND_607 IN/OUT4 Shut_Dn R2 R1 -48V Return Load STB120NFPower 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-11 Solutions Summary • Reducing board space due to smaller hold-off capacitor • Reducing the number of hot-swap controller types across multiple projects. (A detailed circuit description is provided in “5.3 Implementing a Negative Supply Hot-Swap Controller” on page 5-13.) CompactPCI Board Management Features of CompactPCI Board Management Controller Integrated into a Power Manager II Device • Hot-swap for 3.3V, 5V, ±12V (CompactPCI hot-swap and board controller) • Can be used across a wide range of board power – 10W to 200W • Programmable inrush current per individual rail • Programmable contact de-bounce delay on all supply inputs • Over-voltage, over-current protection and under-voltage lockout • Short circuit protection response < 1s • Programmable retry period – Retry on hot-swap fault / secondary supply fault • Backplane fault early warning • Isolates board from backplane due to faults on board • Integrate other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining. • Measures backplane voltages in addition to other board voltages and currents through I2 C • Management of supplies can be changed after assembly through in-system programming via JTAG. (A detailed circuit description is provided in “5.4 CompactPCI Board Management” on page 5-16.)Power 2 You: A Guide to Power Supply Management and Control 2-12 Solutions Summary Figure 2-8. An ispPAC-POWR1220AT8 Device – Complete CompactPCI Board Management Advantages of CompactPCI Board Management Integrated into a Power Manager II Device • Reduces board cost by integrating other secondary board power management functions into Power Manager II, lower cost MOSFET and smaller hold-off capacitor • Increases system reliability by reducing the peak current during the hot-swap event as well as during board fault • Minimizes fault propagation to other boards in the system due to a fault on a circuit board • Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary side • Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in “5.4 CompactPCI Board Management” on page 5-16.) CompactPCI Express Board Management Advantages of CompactPCI Express Board Management • Hot-swap for 3.3V, 5V, +12V (CompactPCI Express, VME system board controller) • Can be used across a wide range of board power – 10W to 200W • Programmable inrush current per individual rail • Programmable contact de-bounce delay on all supply inputs +12V +5V Q1 Q2 Ch 1.8V POL 2.5V POL BRD_SEL# PCI_RST_b Brown_Out CPU_RSTb 12V 1.8V 2.5V 5V 3.3V I_Sens3V3 FETDRV3V3 V_Sens3V3 I_Sens5V FETDRV5V V_Sens5V V_In_12V FETDRV12V V_Sens12V En_1V8 En_2V5 SCL SDA ispPAC-POWR1220AT8 -12V +3.3V En_Neg12 Healthy# -12V +3.3V CSA CSA Q3Power 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-13 Solutions Summary • Over-voltage, over-current protection and under-voltage lockout • Short circuit protection response < 1s • Programmable retry period – Retry on hot-swap fault / secondary supply fault • Backplane fault early warning • Isolates board from backplane due to faults on board • Integrates other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining. • Measures backplane voltages in addition to other board voltages and currents through I2 C • Management of supplies can be changed after assembly through in-system programming via JTAG. (A detailed circuit description is provided in “5.4 CompactPCI Board Management” on page 5-16.) Figure 2-9. Complete CompactPCI Express Board Power Management Advantages of CompactPCI Express Board Management Implementation • Reduces board cost by integrating other secondary board power management functions into Power Manager II, lower cost MOSFET and smaller hold-off capacitor • Increases system reliability by reducing the peak current during the hot-swap event as well as during board fault • Minimizes fault propagation to other boards in the system due to a fault on a circuit board • Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary side • Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in “5.4 CompactPCI Board Management” on page 5-16.) +12V +5V +3.3V Q5 Q1 Q2 D2 C2 C_Pmp S_Dn Q3 Ch 3.3V ATNSW# PRSNT# PWREN# PERST# MPWRGD 12V 1.8V 2.5V 5V 3.3V I_Sens3V3 FETDRV3V3 V_Sens3V3 I_Sens5V FETDRV5V V_Sens5V V_In_12V I_Sens12V FETDRV12V Sh V_Sens12V ut_Dn En_1V8 En_2V5 SCL SDA CSA CSA 1.8V POL 2.5V POL Q4 CSA ispPAC-POWR1220AT8Power 2 You: A Guide to Power Supply Management and Control 2-14 Solutions Summary 2.4 Redundant Supply Management Two Rail 5V Power Supply OR’ing (Using MOSFETs) Features of Power Manager II-Based Implementation • Low power loss replacement for diode • Uses N-Channel MOSFET • Proactive reverse current protection • Under-voltage and over-voltage protection • Individual branch current and voltage measurement through I2 C • Integrates other board management functions such as hot-swap, supply sequencing, voltage supervision, reset generation, watchdog timer, trimming and margining. (A detailed circuit description is provided in “6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit ” on page 6-3.) Figure 2-10. An ispPAC-POWR1014A Device Implementing Two-Rail 5V OR’ing Control Advantages of Integrating Power OR’ing Control into a Power Manager II Device • Increases board reliability through proactive reverse current protection Inp_5Vb Hyst_Ctrl Q2 5V_Hot-swap Inp_5Va I_Inb Rs R2 Q1 Rs R1 5V_a Start 5V_Hot-swap CSA A VMON1 VMON2 VMON3 VMON4 HVOUT1 OUT3 SCL SDA ispPAC-POWR1014A 5V_b I_Ina ADC CSA B HVOUT2Power 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-15 Solutions Summary • Lowers power management cost through integrating multiple power management functions into a single device • Reduces the number of ICs required to implement the Power OR’ing feature. (A detailed circuit description is provided in “6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit ” on page 6-3.) Power Supply OR’ing of N-Rails Using MOSFETS Features of Power Manager II-Based Implementation • Single Power Manager II chip implements OR’ing up to six channels • Low power loss replacement for diode • Uses N-Channel MOSFET • Proactive reverse current protection • Under-voltage and over-voltage protection • Individual branch current and voltage measurement through I2 C • Integrate other board management functions such as hot-swap, supply sequencing, voltage supervision, reset generation, watchdog timer, trimming and margining. (A detailed circuit description is provided in “6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS” on page 6-5.)Power 2 You: A Guide to Power Supply Management and Control 2-16 Solutions Summary Figure 2-11. N-Channel OR’ing through MOSFETS Advantages of Integrating Power OR’ing Control into a Power Manager II Device • Increases board reliability through proactive reverse current protection • Lowers power management cost through integrating multiple power management functions into a single device • Reduces number of ICs required to implement Power OR’ing feature. (A detailed circuit description is provided in “6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS” on page 6-5.) N-rail (12V/24V) OR’ing Features of Power Manager II-Based Implementation • Wide operating voltage range: 6V to 24V • Single Power Manager II chip implements OR’ing up to six channels • Low power loss replacement for diode • Uses N-Channel MOSFET Inp_5Vb Qn 5V_Hot-Swap Inp_5Va I_Inn Rs Rn Q1 Rs R1 5V_a Start 5V_Hot-Swap CSA a VMON1 VMON2 VMON3 VMON4 HVOUT1 OUT3 SCL SDA ispPAC-POWR1014A 5V_n I_Ina ADC CSA nPower 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-17 Solutions Summary • Proactive reverse current protection • Under-voltage and over-voltage protection • Individual branch current and voltage measurement through I2 C • Integrates other board management functions such as hot-swap, supply sequencing, voltage supervision, reset generation, watchdog timer, trimming and margining. (A detailed circuit description is provided in “6.5 N-rail (12V/24V) OR’ing” on page 6-7.) Figure 2-12. N- 12V Rail OR’ing Through MOSFET Using an ispPAC-POWR1014A Device Advantages of Integrating Power OR’ing Control into a Power Manager II Device • Increases board reliability through proactive reverse current protection • Lowers power management cost through integrating multiple power management functions into a single device • Reduces number of ICs required to implement the Power OR’ing feature. (A detailed circuit description is provided in “6.5 N-rail (12V/24V) OR’ing” on page 6-7.) -48V Supply OR’ing Through MOSFETS Features of Power Manager II-Based Implementation Inp_12Vb Qn 12V_Hot-Swap Inp_12Va I_Inn Rs Rn Q1 Rs R1 12V_a Start 12V_Hot-Swap CSA a VMON1 VMON2 VMON3 VMON4 HVOUT1 OUT4 SCL SDA ispPAC-POWR1014A 12V_n I_Ina ADC CSA n OUT3 OUT5Power 2 You: A Guide to Power Supply Management and Control 2-18 Solutions Summary • Wide operating voltage range: -30V to -80V • Low power loss replacement for diode • Uses N-Channel MOSFET • Hot-swappable • Proactive reverse current protection • Under-voltage and over-voltage protection • Fuse fault detection • Controls hot-swap controller. (A detailed circuit description is provided in “6.6 -48V Supply OR’ing Through MOSFETS” on page 6-10.) Figure 2-13. Dual -48V MOSFET OR’ing Circuit Using an ispPAC-POWR607 Device Advantages of Integrating Power OR’ing Control into a Power Manager II Device • Increases board reliability through proactive reverse current protection • Lowers power management cost through integrating power OR’ing along with voltage monitoring and contact de-bouncing • Reduces number of ICs required to implement the Power OR’ing feature. (A detailed circuit description is provided in “6.6 -48V Supply OR’ing Through MOSFETS” on page 6-10.) -48VA -48VB 10K 10K A_Hi B_Hi A_On B_On Start_HS Q1 Q2 R1 R2 R3 R4 To Hot-swap Controller BRD -48V HVOUT2 GND HVOUT1 VMON6 VMON5 OUT5 ispPACPOWR607 3K 3KPower 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-19 2.5 Power Feed Controllers Solutions Summary Dual Rail -48V Power Feed Controller Features of Power Manager II-Based Implementation • Wide operating voltage range: -30V to -80V • Safe MOSFETs operation (SOA) • Individual channel current limiting • Individual channel short circuit protection - < 1s response time • No-current and over-current flags per output branch • Individual channel enables • Retry upon fault detection • Filters out short period over-current glitches. (A detailed circuit description is provided in “7.2 Dual Rail -48V Supply Feed” on page 7-1.) Figure 2-14. An ispPAC-POWR607 Implements a Two-Channel -48V Power Feed Circuit Advantages of Integrating 2-Channel -48V Power Feed into a Power Manager II • Lowers cost by integrating two-channel power feed into a single chip • Increases board reliability through current limiting and short circuit protection on a per-channel basis • Reduces the number of ICs by being able to be customized across a wide range of power feed and protection requirements. (A detailed circuit description is provided in “7.2 Dual Rail -48V Supply Feed” on page 7-1.) SC_2 Fault_1 R1 R2 R3 R4 Rs1 Rs2 Q2 N1 N2 100K 100K VMON 1 VMON 2 HVOUT1 VMON 3 VMON 4 HVOUT2 OUT3 OUT4 -48V_1 -48V_2 Fault_2 OUT6 OUT5 OC_SCb OUT7 ispPAC-POWR607 -48V_IN SC_1 GND -48V_Rtn 3V3 Reg Vcc SC_2 SC_1 En_2 En_1 VMON 6 VMON 5 IN1 IN2 N3 N4 Q1Power 2 You: A Guide to Power Supply Management and Control 2-20 Solutions Summary Three-Channels of a 6V-24V Power Feed System Features of Power Manager II-Based implementation • Wide operating voltage range: 6V to 24V • Expandable up to four channels of power feed control • Safe MOSFET operation (SOA) • Individual channel current limiting • Individual channel short circuit protection - < 1s response time • No-current and over-current flags per output branch • Individual channel enables • Retry upon fault detection • Filters out short period over-current glitches • Individual channel current and voltage measurement through I2 C • Integrates other board power management functions. (A detailed circuit description is provided in “7.3 Three Channels of a +12V Power Feed System” on page 7-4.) Figure 2-15. Three-Channel 12V Power Feed Circuit Advantages of Integrating Multiple Channel Power Feed into a Power Manager II Device • Reduces cost of implementation by reducing the number of ICs required for the entire power feed circuit • Reduced number of power feed ICs – Customizable to meet power feed characteristics across a wide variety of applications Inp_12VIn Rs3 Q3 Rs2 Q2 12V_In Rs1 Q1 2 12V#1 12V#2 12V#3 CPOUT I_12V_1, Out_12V_1 SC_1 SC_2 SC_3 EN_1 EN_2 EN_3 SC_1,2,3 Fault_1, Fault_2, Fault_3 ADC ispPAC-POWR1014A VMON1 VMON2,3 VMON4,5 SCL OUT3,4 HVOUT1 SDA VMON6,8 OUT5,6 OUT7,8 VMON9 VMON10 IN1 IN2,3,4 OUT9,10,11 2 2 2 2 2Power 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-21 Solutions Summary • Increased reliability of the board by integrating other board management functions such as sequencing, reset generation, etc. (A detailed circuit description is provided in “7.3 Three Channels of a +12V Power Feed System” on page 7-4.) Two-Channel +12V & 3.3V Power Feed With Diode OR’ing Features of the Power Feed Solution Integrated into Power Manager II • Designed for use in MicroTCA Power Module – Two channels • Feeds 3.3V and 12V with OR’ing support using MOSFET • Turns off 12V power feed within 50s of AMC card extraction • Programmable over-current protection • MOSFET operates in safe operating area • Supports OR’ing of payload power supply rails (+12V) • Proactive reverse current protection • Measures voltage and current through I2 C • Monitors input 12V supply for over- and under-voltage conditions • Expand up to four channels of power feed as well as trimming of 12V supply for power supply OR’ing function. (A detailed circuit description is provided in “7.4 2-Channel +12V & 3.3V Power Feed With MOSFET OR’ing” on page 7-8.)Power 2 You: A Guide to Power Supply Management and Control 2-22 Solutions Summary Figure 2-16. One-Channel uTCA Power Feed Using Half of an ispPAC-POWR104A Device Advantages of Two-Channel MicroTCA Power Feed Circuit Using a Power Manager Device: • Lowers cost of implementation • Increased reliability through high precision voltage monitoring • Integrates more channels of power feed circuitry along with trimming features. (A detailed circuit description is provided in “7.4 2-Channel +12V & 3.3V Power Feed With MOSFET OR’ing” on page 7-8.) EMMC Alert VMON Open Drain Digital Out HVOUT1 OUT VMON OUT EMMC Primary/ Redundant Enable# Payload On Mgmt Power Control Current Sensing Pass Device OR’ing Device Q1 Q2 12V Payload Power to Load 100 100 4.7M P1 4.7M 0.001µF C2 MMBT 2222A N1 47 D2 P2 0.01µF C1 2.2K Quick Shutoff Output Monitor Half of ispPACPOWR1014A OR-FET Control MMBT 2222A N2 Q3 3.3V Power to Load D1 Open Drain Digital Out Vcc 12V 3.3V + _ 47M 3K N3 6V 1K MMBT2907 Primary Power SourcePower 2 You: A Guide to Power Supply Management and Control Solutions Summary 2-23 2.6 Trimming and Margining Solutions Summary (A detailed circuit description is provided in “8.4 Trimming and Margining – Principle of Operation” on page 8-3.) Features of Closed Loop Trimming and Margining Implemented in a Power Manager II Device • Ideally suited for trimming any low voltage (<1.2V) and high current analog DC-DC converter • Output voltage accuracy = Set pin voltage ±10mV • Single chip supports up to eight channels of trimming and margining • Voltage margining support • Differential voltage sensing • Voltage scaling • VID support through simple PLD • Integrates trimming and margining along with voltage supervision, sequencing, reset generation and hot-swap controller functions. Figure 2-17. Low Cost Trimming and Margining Solution Using Power Manager II Advantages of Implementing Trimming and Margining Using a Power Manager II Device • Lowers cost of a DC-DC converter - No need for Digital DC-DC converter to support margining and trimming • Increases functional reliability through DC-DC converter precision output voltage control • Reduces operating power through voltage scaling • Reduces debug time by automated margining tests PWM Controller Inductor & Filters Switcher Feedback Any DC-DC Converter ispPAC-POWR1220AT8/ ispPAC-POWR6AT6 Load Differential Voltage Sense I 2 C 2 Result: Voltage Error <1% At Load! (-40° to +85° C) Set Point +/-1 VIN DAC ADCPower 2 You: A Guide to Power Supply Management and Control 2-24 Solutions Summary This page intentionally left blank.CHAPTER 3 3-1 Reset Generators & Supervisors 3.1 Introduction One of the most important peripheral ICs required for a microprocessor is a reset generator and a watchdog timer. The functions of a reset generator are: 1. Hold the processor in a reset condition for an extended period of time during a power turn-on event. 2. If any supply is faulty, activate the reset to prevent it from mis-executing instructions and/or risk Flash memory corruption. The functions of a watchdog timer are: 1. A monitor for software execution using the trigger generated by the software. 2. If the processor skips a trigger, activate an interrupt or reset the CPU to initiate a recovery process. Traditional reset generators monitor just one input supply to generate the reset signal. However, most modern processors operate using many supplies, as shown in Figure 3-1. Because a fault on any of the supplies could result in the processor mis-executing instructions, reset generators that monitor only one supply are not adequate. Instead, reset generators are required that monitor all the relevant supplies for faults in order to generate the CPU reset. Figure 3-1 illustrates this. In the example shown it is not clear which of the five supplies should be chosen for reset.Power 2 You: A Guide to Power Supply Management and Control 3-2 Reset Generators & Supervisors Figure 3-1. Single Rail Reset Generator Cannot Guarantee Reliable Reset Generation In Figure 3-1, the processor requires 1.2V for its core, 1.8V and 0.9V for communicating with DDRII memory and 3.3V for communicating with Flash memory and other peripherals. The processor operates reliably only if all of its supply rails are within the datasheet-specified voltage limits; for example, the acceptable tolerance for: 3.3V (±5%), 1.8V (±5%), 1.2V (±3%), and 0.9V (±5%). One common behavior of a microprocessor when operating at a core voltage less than its specified low voltage level is the misinterpretation of instructions. When the instructions are misinterpreted (also called mis-executed), the program execution becomes unpredictable and the program can hang (not perform the intended task). If the I/O voltage drops below the specified signaling threshold level, the instruction/data transferred between the memory and the processor can be corrupted. The misinterpretation of instructions, or proper execution of corrupted instructions, by a microprocessor results in unpredictable behavior; in some cases, the microprocessor could overwrite the on-board Flash memory, resulting in a failed circuit board. Imagine the circuit board failing just because it was extracted from its sub-rack slot! Unpredictable behavior under low voltage conditions is limited not only to microprocessors, but is also true for any ASIC / FPGA on the board. For example, if the power supply voltage drops below the limit for a networking ASIC, it might send a garbled packet. In some cases it might lose an internally buffered acknowledged packet, resulting in a corrupt message. Reliable Reset Generation by Monitoring All Supply Rails To prevent the processor from operating when any of its supplies is faulty, one has to monitor all supplies. Monitoring all the supplies for faults is known as supply supervision. Supervisor ICs are used to monitor multiple supplies simultaneously. The following functions are typically performed by one or multiple supervisor ICs: 1. Accurately monitor multiple supply rails for faults and quickly generate an interrupt 2. If the processor core or memory supplies fail, reset the processor V = ? 3.3V 1.8V 1.2V 0.9V Reset CPU TMS320C6XXX DDR 1.8V 0.9V Flash Memory Reset ICReset Generators & Supervisors 3-3 Power 2 You: A Guide to Power Supply Management and Control Reset Generators & Supervisors Voltage Supervision Reliability Is Determined By the Supervisor IC’s Fault Detection Accuracy As Well As Its Fault Detection Speed Figure 3-2 shows the ProcessorPM-POWR605 supervisor and reset IC (replacing the reset IC in Figure 3-1) to monitor all supplies on the circuit board and prevent Flash corruption due to supply faults. Figure 3-2. The Most Reliable Reset Generator ICs Monitor All Supplies (Supervisor IC) Parts of a Supervisor IC Figure 3-3 shows a simple, single supply, voltage monitoring circuit. Figure 3-3. Single Power Supply Voltage Monitoring Circuit This circuit uses a voltage comparator to monitor the supply voltage. One limb of the comparator is held at a constant reference voltage through the bandgap voltage reference. The monitored power supply voltage is attenuated using a resistor network such that the attenuated voltage is greater than the bandgap reference voltage as long as the supply voltage is above the fault level. For example, the bandgap voltage is 2V, and the power supply should be monitored for 3.3V - 5% (= 3.135V). The attenuator is selected such that the output of the attenuator is greater than 2V as long as the monitored supply voltage is greater than 3.135V. The comparator output toggles when the monitored voltage drops below 3.135V. reset generators, supervisors and voltage detectors use circuits similar to the one shown in Figure 3-3. Figure 3-4 shows the architecture of a device to monitor multiple power supply voltages. These devices contain multiple comparators with individual attenuators to facilitate the simultaneous monitoring of dif- 3.3V 1.8V 1.2V 0.9V Reset CPU TMS320C6XXX DDR II / DDRIII 1.8V 0.9V ProcessorPMPOWR605 (Supervisor + Reset Generator) Voltage Comparator Band-gap Reference Voltage Monitored Supply Voltage Logic Output Interrupt/ Reset Signal AttenuatorPower 2 You: A Guide to Power Supply Management and Control 3-4 Reset Generators & Supervisors ferent power supply voltages. The outputs of these comparators are logically combined to provide a single logic output to interrupt or reset the processor. Figure 3-4. Block Diagram of a Three Power Supply Supervisor IC Effect of Monitoring Accuracy on System Functionality In the circuit shown in Figure 3-3, suppose we use an ideal bandgap reference source (output voltage is always 2V), ideal attenuator (its output voltage is exactly 2V when the input voltage is 3.135V), and an ideal comparator: then, the output of the comparator always toggles exactly when the monitored voltage is 3.135V. But in reality, the bandgap reference voltage changes with temperature, the output voltage of the attenuator varies from device to device and there are inaccuracies with the comparator. All these result in a slight variation of the threshold voltages for each device and across temperature and voltage. The accuracy of a supervisor is a measure of the variation of threshold with respect to the intended threshold. Many off-the-shelf supervisory ICs detect power faults with an accuracy of ±2%. This means that the actual threshold can vary by as much as 2% of the threshold value across voltage and temperature, and from device to device. Let’s examine the effect of this accuracy on system functionality and fault detection threshold selection. Refer to Figure 3-5. If the device is specified at a threshold of 3.3V - 5% (3.135V) with a 2% accuracy, that device can declare the power supply as faulty anywhere between 3.135 + 2% and 3.135 - 2% (3.2V to 3.072V), shown by points A and B. Voltage Comparator Band-gap Reference Voltage Logic Output Interrupt/ Reset Signal Attenuator Voltage Comparator Attenuator Voltage Comparator Monitored Supply Voltage #1 Attenuator Monitored Logic Supply Voltage #2 Monitored Supply Voltage #3Reset Generators & Supervisors 3-5 Power 2 You: A Guide to Power Supply Management and Control Reset Generators & Supervisors Figure 3-5. Fault Detection with Supervisor Accuracy Of 2% As can be seen, the supervisor can sometimes declare the power supply faulty when it is healthy, or declare it healthy when it is faulty. The latter is a more serious error, because at lower than the desired threshold voltage the processor can be mis-executing instructions, which defeats the purpose of using a supervisor IC. To avoid such problems, the supervisor threshold should be set such that the entire power supply fault detect range lies within the operating voltage range of the processor. In this case, if the supervisor threshold is set at 3.2V, then the voltage range in which the supervisor can declare the power supply faulty is between 3.14V to 3.26V, thus avoiding the condition under which the processor is operating at a voltage less than its threshold (3.3V - 5%). Figure 3-6. Fault Detection with Supervisor with Correct Threshold In the example shown in Figure 3-6, the threshold value of the supervisor was set at 3.2V. The 3.2V threshold value was actually calculated using the following equation: Where VTSup - Supervisor Threshold Vin - Power Supply Nominal Voltage VinTol - Input Power Supply Tolerance VTSup = Vin * (1-VinTol/100)/ (1-Asup/100) 3.3v - 5% Processor Lower Voltage Threshold & Supervisor Threshold { A B Supervisor Fault Defect Range 3.3V – 5% = 3.14V A = 3.2V, B = 3.07V Typical Power Supply Voltage 3.3V Typical Power Supply Voltage 3.3V A B { Supervisor Fault Defect Range Supervisor Threshold = 3.2V Processor Lower Voltage Threshold Power Supply Tolerance Headroom - 1.1% 3.3V – 5% = 3.14V A = 3.26V, B = 3.14V { 3.3V – 5%Power 2 You: A Guide to Power Supply Management and Control 3-6 Reset Generators & Supervisors Asup - Accuracy of the Supervisor In this example, Vin at 3.3V, VinTol - 5%, Asup - 2%. Substituting these values into the equation above, VTSup = 3.3 * (1 - (5/100)) / (1 - (2/100)) = 3.2V. By selecting the Supervisor IC with the threshold at 3.2V or above, the processor is guaranteed to be held in reset when the power supply voltage is less than or equal to 3.3V - 5%. Reduced Accuracy Results in Reducing the Power Supply Tolerance Headroom Power supply tolerance headroom is the maximum voltage swing allowed for the power supply, across load and operating temperatures, before being declared faulty as shown in Figure 3-6. Consider the power supply headroom while using a supervisor IC with an accuracy of 2%. According to Figure 3-6, the power supply voltage variation should be higher than 3.26V (the highest voltage at which the supervisor would declare the supply faulty) all the time, or a power supply head room of 1.1%! Typically, power supplies have an output tolerance of about 3% across load and temperature, or the power supply voltage can swing from 3.2V to 3.4V. Clearly the choice for the user is either to use a more expensive supply with a power supply voltage variation of 1%, or use a supervisor with better accuracy. Using a Supervisor IC With an Accuracy Of 1% From the equation for the same system described above, but using an error of 1%, the supervisor selected should have a threshold of 3.17V. The upper limit of the fault detect range is 3.19V and is still less than the lowest output voltage of the power supply, -3.2V, and a power supply with a voltage variation of 3% can be used. The board can be operated reliably with a lower cost power supply with larger output voltage tolerance by using a more accurate supervisor. The ispPAC-POWR1220AT8 device offers an accuracy of 0.2% (typical) and 0.7% (maximum). Effects of Fault Detection Delay Fault detection delay is the duration from the time the power supply voltage drops below the threshold of the supervisor (with very high accuracy), to the time the output of the supervisor toggles, indicating the fault.Reset Generators & Supervisors 3-7 Power 2 You: A Guide to Power Supply Management and Control Reset Generators & Supervisors Figure 3-7. Effect of Fault Detection Delay On Board Operation In Figure 3-7, the 3.3V supply starts to fail. The power supply supervisor detects the power supply failure and signals the processor. As can be seen from Figure 3-7, the longer the supervisor takes to report the fault, the lower will be the power supply voltage. For example, the power supply voltage is decaying at a rate of 1V per millisecond. The supervisor precision is very high, which allows the effects of the accuracy described above to be ignored and is set at the threshold of 3.3V - 5%. Let us examine two cases: Fault detection delay is 1ms and 50s. If the Fault Detection Delay is 1ms: Because the power supply output voltage continues to drop, by the time the processor is reset its power supply voltage would be much less than the low voltage threshold (about 2V), which means that the processor was executing code until the supply reached 2V! Most likely the processor was mis-executing instructions or locked up. The purpose of the supervisor IC is defeated. If the Fault Detection Delay is 50µs: By the time the supervisor output is active, the processor voltage would have been reduced by about 50mV from its threshold of 3.3V-5%. Again, the processor operation is not guaranteed at this voltage. Now, if the threshold was set 50mV above the 3.3V-5% level, the processor would be reset by the time the power supply crossed the operational threshold. As can be seen, in this application the fault detection delay of 1ms is unacceptable. But a fault detection delay of about 50s requires the threshold to be set 50mV above the minimum operating power supply voltage threshold. The supervisor threshold for reliable operation should consider both the accuracy as well as the fault detection delay. Many applications use over-voltage monitoring; that is, if the power supply voltage reaches above the operating voltage range, either the faulty power supply itself is turned off, or a “crowbar” mechanism is turned on by shorting that power supply output voltage to ground, protecting the devices on the circuit board. Speed of over-voltage detection, in this case, is even more important than the under-voltage fault detection. Supervisor Output 3.3V – 5% ? 3.3V Fault Detection DelayPower 2 You: A Guide to Power Supply Management and Control 3-8 Reset Generators & Supervisors The previous example considered only one power supply voltage and used a very accurate supervisor IC. In reality, the number of power supplies that the supervisor should monitor is more than one. The supervisor should be able to monitor all supplies simultaneously for fault and should be able to detect power supply faults with minimum fault detection delay. Fault detection delay of 1ms or higher is typically seen in circuits that use a microcontroller to monitor voltages using their on-chip ADC. Supervisors Built Using ADC and a Microcontroller are Slow Some applications use a microcontroller to monitor all the power supplies using an on-chip Analog to Digital Converter and an analog multiplexer. The monitoring algorithm, which typically is initiated by an interrupt once every 5 or 10ms, digitizes each power supply voltage, one supply at a time in a round robin format. The ADC sample is compared with the internally stored threshold. If the ADC read value is lower than the threshold, an output port pin (reset or interrupt pin) is toggled to indicate the power supply fault. Because the voltage monitoring algorithm is activated by the real time interrupt, the speed of fault detection is also determined by the delay between interrupts (5ms to 10ms). This is too slow for power supply fault detection. The only perceived advantage of a microcontroller is that it offers a flexible interface that lets designers change the power management algorithm after the board is assembled. However, designers typically avoid changing the microcontroller code. Because there are no software simulators available, any change in the code requires extensive circuit board testing. Consequently, the perceived advantage of flexibility is not real. In order to meet the reliability needs, which include supply fault detection accuracy as well as speed of fault detection, it is advisable to use hardware supervisors instead of microcontrollers. To meet the flexibility needs, the Lattice Power Manager II devices offer programmable analog and programmable digital functions, while providing superior accuracy and fault detection speed. For example, the ispPACPOWR1220AT8 device monitors 12 power supplies simultaneously and has a fault detection delay of 16s. Other Factors Contributing to Increased Reliability The other factors to be considered for reliable power supply fault detection are: Glitch filter – Power supplies are usually fairly noisy during the circuit board operation. The noise can be due to power supply output ripple or to transient currents in the system due to device operation, etc. This noise can result in a randomly toggling supervisor output. To prevent this, supervisors have a glitch filter that generates a clean input to the threshold comparators. Power Manager II devices support a 64s glitch filter for each input. Hysteresis – A small amount of hysteresis is added to the threshold comparators to prevent the outputs from toggling multiple times, due to power supply noise, when the power supply voltage is at its threshold. In Power Manager II devices, the hysteresis is set to 1% of the threshold voltage. The hysteresis does not affect the accuracy of the threshold because the hysteresis transition requirement is applied after the voltage crosses the threshold. Differential Voltage Sensing on a Circuit Board – When monitoring voltage levels of 1.2V and below, one has to use differential voltage sensing to meet the fault detection accuracy needs of the circuit board.Reset Generators & Supervisors 3-9 Power 2 You: A Guide to Power Supply Management and Control Reset Generators & Supervisors Figure 3-8. Ground Voltage Difference Adds Error at Supervisor Input Figure 3-9. Ground Voltage Difference Error Nullified by Differential Sensing Newer fabrication processes with smaller transistor geometries stipulate reduced core supply voltage and range such as 1V with a ±50 mV range. If these voltage rails are monitored from a central location, one should consider the ground voltage difference between the monitored node and the supervisor IC. For example, in Figure 3-8, if the ground voltage difference between the CPU and the voltage monitoring device using a single ended sensing method is about 20mV, and if the actual voltage as seen by the CPU is 30mV, the supervisor IC sees a 30mV + 20mV = 50mV rise from the target value, which is a fault, and interrupts the processor or holds the processor in reset even when it could operate. If the ground voltage difference between the supervisor IC and the CPU is -20mV, the monitor IC does not see a fault even when the supply voltage is lower than its minimum operating threshold level. This results in an unreliable fault detection circuitry. Circuit Board Difference Between Ground Potentials = V GG 1.2V CPU Core Supply CPU 1.2V CPU Core Supply Single Ended Sensing Supervisor IC Sensed Voltage = VCPU – VGG V CPU Circuit Board Difference Between Ground Potentials = V GG 1.2V CPU Core Supply CPU 1.2V CPU Core Supply Differential Sensing Supervisor IC Sensed Voltage = VCPU V CPU + - Differential Sensing Cancels Error Due to V GGPower 2 You: A Guide to Power Supply Management and Control 3-10 Reset Generators & Supervisors The safest solution is to use differential voltage sensing (Figure 3-9). Here the ground voltage difference between the CPU and supervisor IC becomes a common mode voltage at the supervisor and its input difference amplifier cancels the common mode voltage before feeding it to the comparator. Ensuring Deterministic Behavior Under Fault Conditions Through Simulation – The response of a circuit board depends on the power supply failure. As a result, the supervisor is expected to perform different functions depending on the supply that failed. For example, if the core voltage of a CPU failed, the supervisor has to activate the reset signal and start the board power shutdown. However, if one of the redundant supplies failed, the supervisor has to interrupt the processor. To guarantee functional reliability, one should ensure that the design implemented in the Supervisor IC responds to the supply faults correctly. The easiest method is to simulate the design with different types of faults using software, rather than conduct the hardware regression tests. 3.2 N-Supply Supervisor, Reset Generator and Watchdog Timer The ProcessorPM-POWR605 device provides six precision programmable threshold comparators, five I/Os, two digital inputs, four programmable timers and a 16-macrocell CPLD. This device is used to integrate the supervisor, the reset generator and a watchdog timer function. The ProcessorPM-POWR605 devices monitor supply rails with an accuracy of 0.7% and can identify faults within 12s. Figure 3-10. ProcessorPM-POWR605 Integrating Six-Supply Supervisor, Reset Genenerator & Watchdog TimerT Circuit Operation The ProcessorPM-POWR605 in the circuit diagram in Figure 3-10 monitors six supplies directly by configuring each of the monitoring comparator inputs to the fault threshold. Two digital outputs of the ProcessorPM-POWR605 device are configured as CPU_reset and WDT_Int. The CPU_Reset signal supports programmable pulse stretching up to 2 seconds. For example, if the programmable delay is set to 200ms, the CPU_Reset signal will remain active for a period of 200ms after all supplies are above their respective threshold levels. The CPU_Reset signal also gets activated if any of the supplies drops below their respective threshold levels. The WDT_Int signal is activated if the WDT_Trig input is not toggled before the watchdog timer expires. The watchdog timer delay can be programmed from 32s to 2.5 minutes. The reset_in input is used to activate the CPU_Reset signal from an external input such as a manual reset input signal. ProcessorPM-POWR605 V#1 V#2 V#6 CPU_Reset WDT_Int Reset_in WDT_Trig VMON1 to VMON6 IN1 IN2 IN_OUT1 IN_OUT2Reset Generators & Supervisors 3-11 Power 2 You: A Guide to Power Supply Management and Control Reset Generator, Supervisor and Watchdog Timer Algorithm Reset Generators & Supervisors 1. Activate Reset signal, deactivate WDT_Int signals and wait for all supply levels to reach a value above their respective thresholds. 2. Wait for 200ms (time delay programmable). 3. Release Reset. 4. Wait for any supply to fail. If any supply fails, activate the reset signal and jump to step 1. Parallel Equations of the Algorithm 1. Timer equation waits for WDT trig. If the negative edge of the WDT_Trig signal is not received before the timer expires, activate WDT_Int signal. 2. If Reset_In signal is activated and remains active beyond the 50ms (programmable) de-bounce period, activate the CPU_Reset signal. Programmable Features • The monitoring threshold for each of the 6 supplies can be individually set to monitor any supply voltage rail from 0.67V to 5.8V. • Reset pulse stretch duration can be programmed from 32s to 2 seconds. • Watchdog timer delay – Watchdog timer delay can be set from 32s to hours. • The input reset switch de-bounce delay can be programmed from 32s to 2 seconds. Additional Features That Can be Added to ProcessorPM-POWR605 • Three of the remaining I/O pins can be used to implement other input monitor features such as warm reset input, software reset input, FPGA Done, etc., or output control features such as DC-DC enables for sequencing, reset distribution to three other devices at different time intervals, etc. • Over-voltage protection – any of the comparator thresholds can be set to monitor for over-voltage. This configuration can be used to provide over-voltage protection. Relevant Power Manager II ICs Devices such as the ispPAC-POWR1014/A can be used to monitor up to 10 rails. These devices support dual programmable threshold comparators for each of the inputs that enables them to monitor for both over and under-voltages at the same time. The ispPAC-POWR1220AT8 device can be used to monitor up to 12 rails. These devices also support differential sense inputs that can be used to monitor lower voltage supply rails on a larger board more accurately.Power 2 You: A Guide to Power Supply Management and Control 3-12 Reset Generators & Supervisors This page intentionally left blank.CHAPTER 4 4-1 Power Supply Sequencing 4.1 Introduction The number of power supplies (DC-DC Converters, LDOs, Voltage References) in a circuit board is determined by the number of multi-voltage devices used in its payload section. These devices also determine power supply sequencing. Power supply sequencing indicates that all supplies on the board should not be turned on arbitrarily at any time, but instead should be turned on or off in a prescribed sequence. For example, on a circuit board a device with 3 supplies of 3.3V, 1.8V and 1.2V, usually the lowest voltage rail should be turned on first, followed by the larger voltages. The turn on sequence is 1.2V, 1.8V and finally 3.3V. Turning these supplies on in this sequence can be implemented easily by connecting the power good signal from the 1.2V supply to the enable signal of the 1.8V supply, and finally connecting the 1.8V power good signal to the enable signal of the 3.3V supply. However, when there are multiple devices, each with its own sequencing requirements, the logic required for sequencing can become complex. Sequencing Power Supplies with Conflicting Sequencing Requirements What if there is a second device on that same board with supplies of 3.3V, 2.5V and 1.2V, but the supplies must be turned on starting with the highest voltage? This is further complicated by the fact that 3.3V is the main input supply. Now the designer is required to implement sequencing using the fewest possible supplies. In such cases, MOSFETs are used to gate the supplies that conflict with conventional sequencing. The circuit in Figure 4-1 shows one such arrangement.Power 2 You: A Guide to Power Supply Management and Control 4-2 Power Supply Sequencing Figure 4-1. Sequencing Supplies to Meet Conflicting Sequencing Requirements This circuit uses the 3.3V supply to generate the remaining supply rails on the board. Because Device 1 requires 3.3V last and Device 2 requires 3.3V first, the 3.3V is applied to Device 2 with the remaining supplies. Then, the power sequencer enables 2.5V, followed by 1.2V, completing the powering up of Device 2. Next, because the 1.2V for Device 1 is already on, the power sequencer turns on the 1.8V, followed by the 3.3V that is enabled through the MOSFET. One could have implemented this sequencing by using one more 3.3V supply and turning it on only when Device 1 needed it. However, that would increase the board cost. Adding a second multi-voltage device with its own sequencing requirements can make the sequencing more complex. There are other factors that contribute to increased supply sequencing complexity. Other Factors Adding Complexity to Sequencing Algorithm Number of Board-Mounted Supplies is Increasing Modern circuit boards use several multi-voltage ICs such as ASICs, CPUs, memories, and FPGAs. Due to the high level of integration, fabrication processes and support for multiple interface standards, each of these devices can require three to five power supplies. Furthermore, some of these devices require a nonstandard, low voltage core supply. So, it is not uncommon for boards to require five to ten supplies! Sequencing the power supplies to meet the needs of each of the devices can be quite complex. Abort Sequencing if Any Supply Fails During Power-Up Supplies usually fail when they are turning on, leaving some of the devices partially powered. Often some of these devices can only withstand the partially powered condition for a limited time. To mitigate such conditions, the sequencer is required to abort supply sequencing when any supply fails to turn on within a given period. In this case, the sequencer is required to monitor supplies and monitor time during the supply sequencing. 1.8V 2.5V 1.2V 3.3V Device #1 Device #2 En En En Power Sequencer Device #1 Sequence 1. 1.2V 2. 1.8V 3. 3.3V Device #2 Sequence 1. 3.3V 2. 2.5V 3. 1.2VPower 2 You: A Guide to Power Supply Management and Control Power Supply Sequencing Power Supply Sequencing 4-3 Power-Down Sequencing Some devices require the power supplies to be turned off in the reverse order of the turn on sequence to prevent undesirable side effects, such as excessive current consumption on one of the rails that can damage the circuitry. Removing power to all DC-DC converters at the same time may not guarantee safe shut down in these cases, because the capacitors connected to the DC-DC converter outputs may not all discharge at the same time. Minimum Duration Between Two Supplies During Turn On This condition is usually discovered during the board debug phase, when a board does not turn on reliably. The best solution is to be able to easily increase and/or decrease the delay between sequencing steps. Accommodating Changes to Sequencing Observed During the Board Debug Phase Board design engineers are required to meet the sequencing requirements of all devices on the board during the final phases of the board design. To prevent a board re-spin, power sequencing sections are designed with ample provisions for additional components and 0Ω jumpers. This increases the number of components but still may not avoid a jumper wire or two. Power Supply Ramp-Rate Control Some devices require that the supply be turned on with a slow ramp to minimize current in-rush. To meet this requirement, designers feed the power through a MOSFET and the ramp-rate is controlled through the gate of the MOSFET. Turning Unused Power Domains Off to Save Power During Inactive Periods In order to reduce overall board power dissipation, designers turn off sections of the board when they are not in use. This means that when a power domain is turned on, the supplies in that domain need to be turned on in a sequence. Sometimes, to avoid disruption to the operation of the rest of the board, a shut down sequence may be required to minimize current glitches in the system. 4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices Power Manager II devices offer an ideal set of features, such as a PLD, multiple programmable threshold comparators, multiple programmable duration timers and multiple charge pumps, that can be used to turn MOSFETs on/off with programmable ramp-rate control. The resulting power management algorithm is very flexible because all features of the device, as well as the sequencing algorithm, can be controlled by the LogiBuilder utility in the PAC-Designer software tool. The sequencing algorithm also can be simulated to ensure that the algorithm is able to handle all of the faulty conditions. Figure 4-2 shows a typical power supply sequencing implementation using the ispPAC-POWR1014A device. In this circuit, the DC-DC converters are controlled by the ispPAC-POWR1014A device. While it is possible to interface with the active-low enable signals directly with the ispPAC-POWR1014A device outputs, an external transistor may be necessary to interface with active high enable signals. Voltages are Monitored During/After Sequencing All DC-DC converter voltages are monitored by the programmable threshold comparators of the ispPACPOWR1014A device. In this circuit, the ispPAC-POWR1014A device uses a programmable algorithm designed using the PAC-Designer software tool to turn the DC-DC converters on/off through the DC-DC Power 2 You: A Guide to Power Supply Management and Control 4-4 Power Supply Sequencing converter’s enable pins. During supply sequencing, the ispPAC-POWR1014A device will monitor the output voltage of each of the DC-DC converters using the on-chip programmable threshold precision comparators. The power supply sequencing is controlled by the open drain output pins of the ispPAC-POWR1014A. These output pins are controlled by the on-chip PLD. The sequencing algorithm is implemented using the LogiBuilder utility in the PAC-Designer software. Using the LogiBuilder utility, one can implement the following sequencing methods: 1. No sequencing – Here all the supplies are turned on at the same time and no sequencing is necessary. 2. The ispPAC-POWR1014A device waits for all the supplies to reach their operating levels and then generates a power good signal for the board to begin the initialization process. Operating voltage levels are higher than the lower voltage limit and less than the over-voltage limit. 3. Closed loop sequencing – This is a sequence where one supply is turned on only after the previous supply has reached its operating levels. 4. Time-based sequencing – The power sequencer inserts a time delay between each of the supplies without first checking if the first supply reached its normal operating level. 5. Closed loop sequencing with time delay – The second supply is turned on a fixed time after the first supply is on and is within its normal operating voltage level. 6. The supply reaches its normal operating condition within a period of time. Often, supplies fail during turn on. To prevent the locking up of sequencing while waiting for this failed supply, the algorithm turns the supply on and, if the supply does not reach its normal operating voltage levels within a specified time, then the supply is considered faulty and action for incomplete sequencing is initiated. 7. Turn on multiple supplies with a watchdog timer – In this case, supplies are turned on using any of the previous methods. After all the supplies are turned on, the power sequencing algorithm ensures that all supplies are on within the total watchdog timer period. If the watchdog timer expires, the faulty sequence action is initiated. Any or all of these sequencing methods can be implemented easily using the LogiBuilder utility within the PAC-Designer software. LogiBuilder enables implementation of a power management program using six types of intuitive, user friendly and powerful instructions. The user has the flexibility to apply these turn-on rules to each supply, or for groups of supplies, simply by using the appropriate LogiBuilder instructions to manage that supply.Power 2 You: A Guide to Power Supply Management and Control Power Supply Sequencing Power Supply Sequencing 4-5 N-Supply Closed Loop Sequencing Algorithm This section describes a closed loop N-supply sequencing algorithm implemented in the ispPACPOWR1014A device, as shown in Figure 4-2. Table 4-1 provides a detailed explanation of LogiBuilder instructions, along with the associated sequencing method. Figure 4-2. Flexible N- Supply Sequencing using the ispPAC-POWR1014A Device The power management algorithm is implemented in LogiBuilder in a sequence of steps using the LogiBuilder instructions. The Power Manager II device then executes these steps to sequence the supplies on the board. In this example there are N supplies. During each of the first N steps, the LogiBuilder instruction turns on a power supply and waits for the voltage to reach its operating limit. 1. Turn on DC-DC/LDO #1, enable the converter and wait for its output voltage to reach the operating range. The ispPAC-POWR1014A device uses two precision programmable threshold comparators to monitor a given voltage rail. One comparator threshold is set to the lower voltage limit of that voltage rail and the second comparator threshold is set to the over-voltage limit. A DC-DC converter is in its operating limit when its voltage is between the over and the under-voltage limits. 2. Turn on the DC-DC/LDO #2 enable signal and wait for its voltage to reach operating range. 3. Turn on the DC-DC/LDO #3 enable signal and wait for its voltage to reach its operating range (Same function as step 2). 4. Continue turning on supply #4 (Same function as step 2). 5. Continue turning on supply #5 (Same function as step 2). ADC ispPAC-POWR1014A En V OUT POWER_GOOD Shut_Down N OUT 3 OUT 4 OUT 10 OUT 11 OUT 12 SCL SDA IN1 IN 2 VMON 1 to VMON N Recycle Power En V OUT DC-DC / LDO #1 DC-DC / LDO #2 En V OUT DC-DC / LDO #N Sequence_FailPower 2 You: A Guide to Power Supply Management and Control 4-6 Power Supply Sequencing N. Continue turning on supply #N (Same function as step 2). O. If all the supplies are within the operating range, activate the power good signal. If any of the supplies are faulty, turn all the supplies off and activate the Sequence_Fail signal. P. Wait for the Recycle_Power to become active and then jump to step 1. Q. Shut-Down Signal Interrupt Routine – When the shut down signal becomes active, jump to step O. N-supply Closed Loop Sequencing with Failure Monitor Algorithm In the N-supply closed loop sequencing algorithm shown above, a supply failure would hold up the sequence forever. While this phenomenon may be acceptable for most applications, some ICs may be sensitive to being in a partially powered state for extended periods. In that case, the algorithm can be modified to include turn on with monitor mode. For example, if a device is sensitive to the duration of a partial power condition at step 2 of the algorithm above, it can be changed to the following: 1. Turn on DC-DC #1, enable converter and wait for its output voltage to reach operating range. 2. Turn on DC-DC#2 enable signal and wait for its voltage to reach operating range within 5ms. If the supply does not reach operating range within 5ms jump to step O or else proceed to turn off the rest of the supplies. 3. Turn on DC-DC #3 enable converter and wait for its output voltage to reach operating range. 4. Continue turning on supply #4, similar to step 3. 5. Continue turning on supply #5 with fault monitor, similar to step 2. N. Continue turning on supply #N, similar to step 3. O. If all the supplies are within the operating range, activate the power good signal. If any of the supplies are faulty, turn all the supplies off and activate the Sequence_Fail signal. P. Wait for Recycle_Power to become active and then jump to step 1. Applying LogiBuilder Instructions to Sequencing Methods As stated earlier, the LogiBuilder utility in the PAC-Designer software tool provides instructions to directly support different types of sequencing. Figure 4-3 shows the block diagram of a power sequencing circuit. Table 4-1 lists different LogiBuilder instruction sequences to implement the different sequencing methods used to enable the power to Device #1.Power 2 You: A Guide to Power Supply Management and Control Power Supply Sequencing Power Supply Sequencing 4-7 Figure 4-3. Three Supplies of a Device Managed by an ispPAC-POWR1014A Device Device #1 specifies that the 1.2V should be the first supply to turn on, the second is 2.5V for I/O and finally 3.3V for another set of I/Os. Table 4-1 describes the LogiBuilder instructions to implement different sequencing methods while meeting the sequencing requirements of Device #1. Table 4-1. LogiBuilder Instructions Description for a Given Sequence Method Sequence Method LogiBuilder Instruction (s) Output Description Closed Loop Sequencing with 1.2V followed by 2.5V & 3.3V Wait for Core_1V2_OK En_1V2=1 The 1.2V DC-DC is enabled (Active high) and the instruction waits at this step until 1.2V is in regulation Wait for IO_2V5_OK AND IO_3V3_OK En_2V5=0, En_3V3=1, The 2.5V DC-DC is enabled (Active low) and The 3.3V DC-DC is also enabled (Active high). This instruction waits at this step until 2.5 & 3.3V supplies are in regulation Open Loop Sequencing with 1.2V followed by 2.5V Separated by 5ms En_1V2 = 1 The 1.2V DC-DC is enabled (Active high) and the instruction does not wait at this step until 1.2V is in regulation Wait for 5ms using Timer 1 Waits for 5ms at this step before activating the next supply En_2V5 = 0 The 2.5V DC-DC is enabled (Active low) and the instruction does not wait at this step until 2.5V is in regulation but proceeds with the next instruction Closed Loop Sequencing with 1.2V followed by 2.5V Separated by 5ms Wait for Core_1V2_OK En_1V2=1 The 1.2V DC-DC is enabled (Active high) and the instruction waits at this step until 1.2V is in regulation Wait for 5ms using Timer 1 Waits for 5ms at this step before activating the next supply Wait for IO_2V5_OK En_2V5=0 The 2.5V DC-DC is enabled (Active low) and the instruction waits at this step until 2.5V is in regulation but proceeds with the next instruction Turn-on and ensure that the supply turns on within a short period of time Wait for Core_1V2_OK with Timeout of 5ms using Timer1. If Timer1 Go to Fault En_1V2=1 The 1.2V DC-DC is enabled (Active high) and the instruction waits at this step until 1.2V is in regulation within 5ms (determined by Timer 1), if Timer 1 expires, jump to Fault routine OUT 3 OUT 4 OUT 5 VMON1 VMON2 VMON3 En_3V3 En_2V5 En_1V2 ispPAC-POWR1014A 2.5V Device #1 3.3V 1.2V VIN 2.5V 3.3V 1.2VPower 2 You: A Guide to Power Supply Management and Control 4-8 Power Supply Sequencing Any of these sequencing methods can be used for any supply or group of supplies. The timer values can be set to any value between 32s and 2 seconds. Advantages of Power Manager II-based Supply Sequencing The sequencing of supplies is completely programmable. Designers can adjust the turn on or turn off sequence and the associated timing to provide reliable board start up after the board is assembled. No board re-spin is needed. Once the supplies are sequenced the ispPAC-POWR1014A device monitors all of the supplies for faults. Additional Power Management Functions that can be Integrated into Power Manager II In this circuit, the ispPAC-POWR1014A device provides flexible sequencing. The other functions that can be integrated into an ispPAC-POWR1014A device are: 1. Voltage supervision – Monitor all supplies after sequencing for fault and generate an interrupt signal such as a low voltage detect. 2. Reset generation – After the sequence is complete, the ispPAC-POWR1014A device can be used to release Reset for the CPU. 3. Hot-swap controller – If power supply sequencing is required in a positive voltage hot-swappable board, the hot-swap function can also be integrated. 4. Voltage measurement – In addition to all of the supplies being monitored for faults, an external microcontroller can measure individual voltages through the I2 C interface. 5. Fault logging – In case of a fault, the ispPAC-POWR1014A device can output the status of all comparators to an external PLD for logging into a non-volatile memory to aid debug. Applicable Power Manager II Devices Power Manager II devices that can be used for implementing sequencing are the ispPACPOWR1220AT8, ispPAC-POWR1014/A, ispPAC-POWR607 and ProcessorPM-POWR605. Turn-on multiple supplies with a watchdog timer Start Timer2 Timer 2 is the watchdog timer (eg., 20ms) this is started before beginning the supply sequence En_1V2 = 1, En_2V5=0 The 1.2V DC-DC & 2.5V DC-DC are enabled and the instruction does not wait for both supplied to reach regulation If Core_1V2_OK and IO_2V5_OK Then next step Else if Timer 2 Then jump to Fault Else Stay at this step This step waits for both 1.2V and 2.5V supplies to turn on within the 20ms timer. If the turn on, the control jumps to next step. If they fail to turn on within 20ms, the control jumps to fault routine Table 4-1. LogiBuilder Instructions Description for a Given Sequence Method (Continued) Sequence Method LogiBuilder Instruction (s) Output DescriptionPower 2 You: A Guide to Power Supply Management and Control Power Supply Sequencing Power Supply Sequencing 4-9 4.3 Sequencing With MOSFETs and DC-DC Converter Enables In some cases, to meet the device’s sequencing needs without using additional DC-DC converters, MOSFETs are required. Figure 4-4 shows one such circuit, where a ispPAC-POWR1014A device controls the DC-DC converter’s enable signals as well as an N-Channel MOSFET. In this circuit the MOSFET is used to enable 3.3V to Device 1 after all of its other supplies are turned on. To turn-on an N-Channel MOSFET on a 3.3V rail, its gate potential should be at least 8V. Designers either use the 12V supply (if available on the board) or a charge pump IC to generate 8V or higher. The ispPAC-POWR1014A device integrates two MOSFET gate drivers based on integrated charge pumps that can generate up to 12V. The charge pump voltage can be programmed to 6V, 8V, 10V or 12V. In addition, the MOSFET turn on ramp-rate also can be controlled using the programmable current source feature of the MOSFET driver. The gate drive source current can be set to 12.5A, 25A, 50A and 100A. The higher the current setting, the faster the MOSFET turn-on time. Circuit Operation In the circuit shown in Table 4-4, the ispPAC-POWR1014A device is controlling the enable signals of 1.8V, 2.5V and 1.2V DC-DC converters. The MOSFET driver of the ispPAC-POWR1014 device is used to turn the MOSFET Q1 on/off. The sequencing logic is implemented in the PLD using the LogiBuilder utility in the PAC-Designer software tool. After sequencing is complete, the ispPAC-POWR1014A activates the Power_Good signal. If the sequencing fails to complete, the algorithm activates the failed (to complete the sequence) signal. The Shut_Dn signal is used to turn the supplies off in reverse sequence. Figure 4-4. An ispPAC-POWR1014A Device Implementing Sequencing with MOSFET and DC-DC Enables VMON 5 VMON1 to HVOUT 1 OUT 3 OUT 4 OUT 5 Device #1 Device #2 Device #1 Sequence 1. 1.2V 2. 1.8V 3. 3.3V Device #2 Sequence 1. 3.3V 2. 2.5V 3. 1.2V 1.8V En 2.5V En 1.2V En Shut_Dn ispPAC-POWR1014A OUT 6 OUT 7 SCL SDA 3.3V ADC Power Good Failed Q1Power 2 You: A Guide to Power Supply Management and Control 4-10 Power Supply Sequencing Power Sequencing Algorithm The algorithm implemented in the Power Manager II is shown in Table 4-2 and Table 4-3). This section uses the actual LogiBuilder code extracted from the PAC-Designer software. Applicable Power Manager II Devices Power sequencing using MOSFETs can be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014/A and ispPAC-POWR607 devices. Table 4-2. State Machine 0 Step Instruction Outputs Interruptible Comment 0 Begin Startup Sequence 0 ispPAC-POWR1014-02 reset 1 Wait for AGOOD 0 2 Wait for INP_3V3_OK 0 Do not proceed with the sequencing until input supply is within operating range 3 Wait for IO_2V5_OK En_2V5 = 1, 0 3.3V is stable for Device 2. Now enable 2.5V and wait for it to reach operating range 4 Wait for Core_1V2_OK or 2.56ms using Timer 1 If Timeout Then Go to 13 with {Failed = 1,} En_1V2 = 1, 0 1.2V supply should turn on within 2.5ms. If 1.2V fails to turn on, activate Failed signal 5 Wait for IO_1V8_OK En_1V8 = 0, 0 Turn on 1.8V with active low enable signal and wait for it to reach the operating level 6 Wait for FET_3V3_OK En_3V3_MOSF ET = 1, 0 Turn the MOSFET on to begin feed 3.3V to Device 1 and wait for it to be stable 7 Wait for NOT INP_3V3_OK OR NOT IO_2V5_OK OR NOT IO_1V8_OK OR NOT Core_1V2_OK OR NOT FET_3V3_OK Power_Good = 1, 1 Wait for any supply to fail. If any supply fails, turn all supplies off in reverse order. The power good signal is activated as soon as the state machine enters this step 8 Begin Shutdown Sequence 0 9 En_3V3_MOSFET = 0, Power_Good = 0, 0 Fault condition, turn the MOSFET off first and deactivate Power_Good Signal 10 Wait for 2.56ms using timer 1 0 11 En_1V8 = 1, 0 Turn-off 1.8V supply 12 Wait for 2.56ms using timer 1 0 13 En_1V2 = 0, 0 1.2V supply off 14 Wait for 2.56ms using timer 1 0 15 En_2V5 = 0, 0 16 Halt (end-of-program) 0 Table 4-3. Exception Table EID Expression Outputs Exception Handler Comment 0 If Shut_Dn {no outputs specified} Go to step 8 Begin Shutting down supplies in reverse order when Shut_dn signal is active CHAPTER 5 5-1 Hot-Swap Controllers 5.1 What is a Hot-Swap Controller? Hot-swap controllers limit the inrush current when a circuit board is plugged into a live backplane. In addition, these devices offer over-current, over-voltage and under-voltage protection to the circuit board. Figure 5-1 shows the block diagram of a typical hot-swap controller implementation for a positive backplane power supply rail. RS is the current sense resistor. The MOSFET Q1 is used to control the current through the circuit. The resistors R1 , R2 and R3 are used to monitor the backplane voltage. The hold-off capacitor, Ch , is used to provide power to the board when the backplane voltage briefly drops below the low operating voltage (undervoltage) threshold (say, for less than 10ms). Figure 5-1. Positive Rail Hot-Swap Controller When the card is plugged into the live backplane, the hold-off capacitor, Ch , begins to draw a large amount of current from the backplane. The hot-swap controller limits the current in-rush by controlling the voltage applied to the MOSFET gate using the voltage across RS as feedback. The MOSFET will operate in this current limit mode until the capacitor Ch is fully charged. During the brief capacitor charging period, the inrush current drawn from the backplane often can be significantly higher than the normal board operating current. As a result, the backplane voltage can dip below the under-voltage threshold momentarily for the other cards attached to Hot-swap Controller OV UV Backplane Supply (Positive) Hold-Off Capacitor Load Rs R1 R2 R3 Ch Q1Power 2 You: A Guide to Power Supply Management and Control 5-2 Hot-Swap Controllers the backplane. The charge stored in the capacitor, Ch , keeps the card operating during this brief voltage dip period. Hot-swap controllers are also required to isolate the board from the backplane in case it develops a fault during operation. For this purpose, the hot-swap controller will monitor the current through the sense resistor RS . When the voltage across the resistor RS increases beyond its threshold value, the hot-swap controller turns the MOSFET off. If the backplane voltage drops below the under-voltage threshold or goes above the over-voltage threshold, the power supply to the load is shut off by turning the MOSFET off. Figure 5-2. Negative Supply Hot-Swap Controller One of the popular backplane voltages in the telecom industry is -48V. Hot-swap controllers for negative supplies use the current limiting MOSFET on the negative supply limb, as shown in Figure 5-2. Functions of negative rail hot-swap controllers are similar to the positive voltage hot-swap controllers described above. Hot-Swap Circuit Design Considerations In a hot-swap controller circuit the MOSFET will be required to withstand high levels of power dissipation while the hold-off capacitor is being charged. The suitability of the MOSFET for this purpose is determined by its Safe Operating Area (SOA) curves. When a circuit board fault occurs, the current through the MOSFET can increase significantly. If the MOSFET is not quickly turned off, the peak power dissipated on the MOSFET can damage it. hot-swap controllers are also required to monitor over-current conditions and initiate either a fold-back current limiting mechanism or turn the MOSFETs off. Usually under high current conditions, the MOSFET should be turned off within approximately 1s. Some hot-swap controllers implement “retry” to turn the board on if the fault subsequently clears on its own accord. hot-swap controllers are also required to monitor for low voltage conditions and shut the board off when such a condition occurs. 5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices There are many types of hot-swap controllers with different current control and other monitoring mechanisms. Usually, the complexity of a hot-swap controller depends on the power dissipation requirement of a circuit board. This section shows how Lattice Power Manager II devices can be used to implement hotswap controllers that range from the simple to the sophisticated. Hot-swap Controller OV UV Backplane Supply (Negative) Hold-off Capacitor Load R1 R2 R3 Rs Ch Q1Power 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-3 Hot-Swap Controller Using Soft-start Figure 5-3 shows the ispPAC-POWR1014A device implementing a simple hot-swap controller. The principle of operation of this circuit is also called a ‘soft-start’ mechanism. Figure 5-3. Hot-Swap Control Implemented Through MOSFET Ramp Rate Control Circuit Operation In this design, the backplane supply is 5V. The card with the ispPAC-POWR1014A device is plugged into the live 5V backplane. The ispPAC-POWR1014A device first waits for the 5V backplane voltage to stabilize from the initial contact bounce. After the contact bounce period is complete, the ispPACPOWR1014A turns the MOSFET Q1 on through the Soft_start pin (HVOUT pin). The HVOUT pin source current is set to a minimum (12.5A). This current charges the MOSFET gate capacitance slowly. As a result, the MOSFET on-resistance also drops slowly to its final RDS-on value (usually in a few tens to hundreds of mΩ range). This gradual reduction in MOSFET on-resistance reduces the current in-rush. This circuit can only be used in low power and low voltage boards. It also requires that the instantaneous power dissipated by the MOSFET does not violate its safe operating area specification. Soft-start algorithm: 1. Wait for 5V to be continuously on for 100ms and ensure it is within tolerance by monitoring Inp_5V signal. 2. Turn on Q1 by setting soft-start signal to logic 1. 3. Wait until supply at 5V load is within tolerance by monitoring the Out_5V signal. 4. Enable the 5V load through the Start_5V_Load signal. Programmable Features The following parameters can be changed to make this circuit meet a wide range of application needs: • Comparator thresholds can be changed to suit difference backplane voltages, e.g., 5V or 3.3V. The softstart function for 12V can be implemented using a P-Channel MOSFET and driven by one of the logic outputs. Negative rail soft-start can be implemented using N-channel MOSFETs. • Contact de-bounce period can be changed from 50ms to 2 seconds. Inp_5V Soft_start Backplane Q1 5V Load Start_5V_Load Out_5V VMON1 VMON2 HVOUT1 OUT3 ADC ispPAC-POWR1014A I 2 CPower 2 You: A Guide to Power Supply Management and Control 5-4 Hot-Swap Controllers • MOSFET turn on ramp rate can be set using the four current settings available for each HVOUT pin. • Design can be used to implement a dual hot-swap controller for dual supply backplanes using two MOSFET drivers in the ispPAC-POWR1014 device. Integrate Other Board Power Management Functions into a ispPAC-POWR1014A Device This design consumes a very small portion of the ispPAC-POWR1014A device. The remaining resources can be used to implement board power management functions such as power sequencing, voltage supervision, reset generation and watchdog timer. In addition, one may also include faulty board identification and protection. If the board is healthy, the voltage at the hold-off capacitor should stabilize within a short period of time (say, 5ms). If the board is faulty (drawing more current than expected), the voltage at the capacitor will drop to a value less than the lower voltage threshold. When such a condition arises, the MOSFET is turned off immediately. This prevents continuous overloading of the backplane. One can also monitor the backplane voltage to generate early warning to the load circuit for safe turn off. Backplane voltage and other on board rail voltages can be measured using the ispPAC-POWR1014A device’s ADC via the integrated I2 C interface. Applicable Power Manager II Devices In this example, a ispPAC-POWR1014A device was used to implement the soft-start function. However, the soft-start control application can also be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014 and ispPAC-POWR607 devices. The ispPAC-POWR607 devices, however, do not support the programmable ramp-rate control feature. Hot-Swap Controller with Hysteretic Current Limit Mechanism When designing hot-swap controllers for boards with higher power dissipation, or when one is not able to guarantee the MOSFET safe operating area limits are not violated during the hot-swap operation, or when the backplane inrush current is to be limited to prevent disruption to other boards plugged into the same backplane, the following circuit (Figure 5-4) should be used. This circuit begins to operate with the MOSFET Q1 turned on. The current starts to increase to charge the capacitor Ch . When the current exceeds the preset value, the logic in the hot-swap controller turns the MOSFET off. At that time, the current starts to decrease. When the current drops below the preset value, the logic turns the MOSFET on and the current starts to increase again. This method of limiting the current to a preset value by turning the MOSFET on/off is called hysteretic mode of operation. Power 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-5 Figure 5-4. Hot-Swap Controller with Hysteretic Current Limit There are two additional blocks in comparison to the soft-start control circuit shown in Figure 5-3: current monitoring and quick shut-off control. The name of ispPAC-POWR1014A device’s high voltage MOSFET gate drive pin has been changed from Soft_start to Hyst_Ctrl. Principle of Operation of the Hysteretic Control Mechanism Figure 5-5 shows plots of the gate drive of the MOSFET Q1 , current through the MOSFET and the voltage across the capacitor Ch . When Hyst_Ctrl signal is turned on, Q1 ’s gate capacitance starts to charge. At the same time, the current through the MOSFET also begins to increase. The current through the MOSFET passes through the sense resistor RS . The current sense amplifier (CSA) outputs a current proportional to the voltage dropped across RS into series resistors R1 and R2 . The voltage drop across R1 and R2 is monitored by the ispPAC-POWR1014A device through the signal I_In (one of the VMON pins). The comparator output of this VMON pin toggles when the current through RS exceeds the maximum allowable limit (IH). As a result, the logic equation in the PLD turns the Hyst_Ctrl pin off. When the Hyst_Ctrl pin is at logic 0, the MOSFET gate starts to discharge, throttling the current through the MOSFET channel, and the current through the MOSFET begins to drop. The voltage at the I_In pin reduces. When the voltage drops below the I_In pin threshold (IL), the logic equation in the ispPAC-POWR1014A device turns the MOSFET back on. This cyclic throttling action maintains the average current to a value determined by the current threshold settings. This technique provides many of the advantages of linear current control while sidestepping many of the potential stability issues. Inp_5V Hyst_Ctrl Q1 Out_5V I_In Rs +3.3V R1 R2 Short_Ckt IN1 Backplane 5V Load Start_5V_Load ADC ispPAC-POWR1014A SCL SDA VMON1 VMON2 VMON3 OUT3 HVOUT1 IN1 CSA Q2Power 2 You: A Guide to Power Supply Management and Control 5-6 Hot-Swap Controllers Figure 5-5. Hysteretic Current Control Through the Capacitor Turning MOSFET Off Under Short Circuit Conditions To prevent excessive current drain from the backplane and to protect the MOSFET against damage due to excessive power dissipation during a short circuit event, the MOSFET should be turned off within 1s from the time the current reaches a dangerous level. In Figure 5-4, the ispPAC-POWR1014A device’s digital input pin IN1 is driven to Logic 0 by the transistor Q2 when the current through the 5V supply rail exceeds short circuit current limit. The voltage across R2 is 0.7V when the current through RS reaches the short circuit current level. The logic equation in the ispPAC-POWR1014A device turns the MOSFET off immediately within 200ns. Hysteretic Hot-Swap Control Algorithm The algorithm is divided into two sections: • Logic equations for hysteretic control and fast-acting MOSFET shut down during a short circuit event • Sequence control for overall hot-swap event control Equation 1 implements the hysteretic control. The signal En_Hot_Swap turns the hot-swap controller on or off. This signal is turned on by the sequence control algorithm after the contact-de-bounce period. The Hyst_Ctrl (D-type flip-flop) is turned off when the I_In signal voltage exceeds the over-current limit level and turns back on when the I_In signal drops below the threshold. The comparator hysteresis provides the delay between turn-on and turn-off. Equation 2 is a combinatorial equation that turns the MOSFET off as soon as the Short_Ckt signal is equal to logic 0. Equation 1: Hyst_Ctrl.D = En_Hot_swap AND NOT I_IN Equation 2: Hyst_Ctrl.Reset = NOT Short_Ckt VGH VGL IL IH Capacitor Voltage Time Gate Drive CurrentPower 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-7 Sequence control: 1. Wait for 5V to be continuously on for 100ms and within the tolerance limits (monitoring Inp_5V signal). 2. Turn on the hysteric hot-swap action by turning on En_Hot_swap signal. 3. Wait for supply at 5V load is within tolerance limits by monitoring the Out_5V signal. 4. Enable the 5V load through the Start_5V_Load signal. 5. During normal operation, if an over current or under-/over-voltage supply fault occurs for a period greater than the hold-off period (5ms to 10ms), then shut the MOSFET off and retry. Programmable Features This circuit offers many programmable features that make it suitable for a wide range of applications. • Comparator thresholds can be changed to suit different backplane voltages, e.g., 5V or 3.3V. • Contact de-bounce period can be changed from 50ms to 2 seconds. • Over-current and short circuit current levels can be set independently. • The design can be used to implement dual hot-swap controllers for dual supply rail backplanes. • Hold-off time is programmable from 2 to 100ms (time during which the MOSFET should be left on under supply fault). After this period expires, the MOSFET is turned off. The ispPAC-POWR1014A Device Can Integrate Other Board Power Management Functions The difference between the soft-start method and hysteretic control in the algorithm is the addition of two logic equations. As a result, the remaining resources can be used to implement power sequencing, voltage supervision, reset generation and watchdog timer functions for the board. For faulty board identification and protection, add a watchdog timer when monitoring the load voltage immediately after the hysteretic control loop is turned on (after step 4). If this timer expires before the 5V reaches the operating threshold level (implying a fault that is preventing the charge build up in the capacitor Ch ), turn the MOSFET off and turn an LED on, indicating the supply fault. Add backplane voltage monitoring logic to provide early warning to the load circuit for safe turn off. Applicable Power Manager II Devices This example used the ispPAC-POWR1014A device to implement the hysteretic control hot-swap function. However, the hysteretic control can also be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014 and ispPAC-POWR607 devices. Advantages of Using Power Manager II Devices for Hot-Swap Controller There are many hot-swap controllers in the market. Designers have to use these hot-swap controller devices in addition to the board management function. The Power Manager II device reduces the cost of implementation by integrating the hot-swap controller function along with overall board management into a single chip. In addition, the design can be used across a wide range of applications.Power 2 You: A Guide to Power Supply Management and Control 5-8 Hot-Swap Controllers 12V/24V Hot-Swap Controller The operating principle of this circuit is the same as that of the 5V hot-swap controller with hysteretic control mechanism. Two additional features are added to make it compatible with the 12V hot-swap function. These features are an external charge pump and limiting operation of the MOSFET within its safe operating range. The maximum MOSFET gate drive voltage of ispPAC-POWR1014/A and ispPAC-POWR1220AT8 devices is 12V. However, to turn the N-Channel MOSFET on the 12V or 24V rail, one has to drive its gate voltage to 22V or 34V, respectively (about 10V above the rail voltage). To achieve this high voltage, the following circuit (Figure 5-6) implements an external charge pump using diodes, capacitors and a transistor. The operating principle of the external charge pump is as follows (Figure 5-6). The C_Pmp signal (ispPAC-POWR1014A HVOUT pin) toggles between 12V (for 32s) and 0V (for 8s) cyclically. When the C_Pmp signal is at 0V, the capacitor C1 gets charged to backplane voltage of 12V through the diode D1 . At this time the transistor Q2 is off. When the C-Pmp signal toggles up to 12V, the C1 voltage gets added to the C_Pmp pin voltage, resulting in the generation of approximately 24V at the junction of C1 and D1 . This voltage turns Q2 on and charges the capacitor C2 to about 22V through the diode D2 . This voltage is sufficient to turn the MOSFET Q1 on. The transistor Q3 , driven by the S_Dn signal, is used to shut the MOSFET Q1 off by discharging the MOSFET Q1 gate and C2 when there is a fault. Figure 5-6. 12V/24V Hot-Swap Controller Using an ispPAC-POWR1014A Device Limiting the Hot-Swap MOSFET Within its Safe Operating Area The ispPAC-POWR1014A device implements a hysteretic control loop to limit the current through the MOSFET within safe operating limits when charging the hold-off capacitor Ch . The HVOUT pin stops toggling when the current through the resistor RS exceeds the set threshold. When toggling is stopped, the Inp_12V Backplane Q1 Out_12V I_In Rs +3.3V R1 R2 Short_Ckt +3.3V D1 Q2 D2 C2 C1 12V Load Start_12V_Load C_Pmp S_Dn Q3 Ch VMON1 VMON2 VMON3 OUT3 HVOUT1 OUT4 ADC ispPAC-POWR1014A SCL IN1 SDA CSAPower 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-9 voltage at the MOSFET gate starts to drop down, reducing the current through the MOSFET. When the current drops below the threshold, the C-Pmp signal starts to toggle, turning the charge pump on again Figure 5-7. MOSFET Safe Operating Area (IRF7832) The safe operating area of the chosen MOSFET (IRF7832) is shown in Figure 5-7 as a log-log graph with the voltage across the MOSFET on the x-axis and the current through the MOSFET on the y-axis. The dashed lines in the graph show the maximum allowable current at a given voltage across the MOSFET for a given pulse width. The red line on the graph shows the operating current limit of this circuit. Throughout the power-on process, the MOSFET never exceeds its safe operating area limits. Figure 5-8. Inrush Current Through the MOSFET I D , Drain-to-Source Current (A) 100 µs 1 ms 10 ms Tc = 25° C Tj = 150° C Single Pulse 1000 100 10 1 V DS, Drain-to-Source Voltage (V) 1 10 100Power 2 You: A Guide to Power Supply Management and Control 5-10 Hot-Swap Controllers In the oscilloscope plot shown in Figure 5-8, the green trace is the current through the MOSFET and the pink trace is the voltage across the capacitor. As can be seen, the current is limited to 2A until the voltage across the capacitor reaches 6V, and after that the current is limited to 4A. Figure 5-9. Circuit Operation During Short Circuit When the circuit is turned on to a short circuit, the power feed begins as usual. If the capacitor voltage does not reach 9V within 10ms, the MOSFETs are turned off and the circuit waits for a retry command. Figure 5-9 shows the oscilloscope plot of the MOSFET turn-on current with the capacitor Ch replaced with a short. 12V Hot-Swap Controller Algorithm The hot-swap controller algorithm is divided into the following sections: • Logic equations for the external charge pump operation • Logic equations for hysteretic control and fast-acting MOSFET shut down during a short circuit event • Sequence control for overall hot-swap event control Toggle_C_Pump is an internal variable used to generate 8 s wide pulses. Equation 3 and Equation 4 use an on-chip hardware timer. There are four programmable timers in a ispPAC-POWR1014A device. Each timer delay can be set from 32s to 2 seconds. Timer count-down is iniEquation 3: Toggle_C_Pump.D = 32 s Timer Terminal Count Equation 4: 32 s Timer Gate.D = NOT Toggle_C_PumpPower 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-11 tiated by applying a logic 1 to the gate signal. The timer_TC signal transitions to logic 1 after the timer count-down is complete. When the timer gate signal is connected to the inverted Timer_TC (Figure 5- 10), the timer generates a 4s pulse every time the timer expires. Figure 5-10. Timer Configuration to Implement Programmable Frequency Clock If the timer delay is set to, say, 32s, the timer TC and the timer gate outputs will be: Figure 5-11. Generating 4µs Wide Pulses with Programmable Interval Using Timer Equation 3 latches the timer TC into a variable Toggle_C_Pump. This stretches the timer gate by another 4s. The waveform of Toggle_C_Pump is shown in Figure 5-12. Figure 5-12. Generating 8µs Wide Pulses with 32µs Interval Using Toggle_C_Pump Programmable Timer Timer Gate Timer TC 32µs to 2 seconds 4µs 32µs Timer Gate Timer TC 8µs 32µs Toggle_C_Pump Toggle_C_Pump Programmable Timer Timer Gate 32µs to 2 seconds Timer TC D Q D-FFPower 2 You: A Guide to Power Supply Management and Control 5-12 Hot-Swap Controllers Equation 5 controls the MOSFET drive circuit. The Toggle_C_Pump signal is used to drive the external charge pump circuit. This pulse train is modulated by: • En_Hot_Swap – Controlled by the sequence control • (NOT I_IN_2_A AND NOT OUT_12V_GT_6V) – Hysteretic control that limits the current to less than 2A when the voltage at Ch is less than 6V • (NOT I_IN_4_A AND NOT OUT_12V_GT_9V) – Hysteretic control that limits the current to 4A when the voltage at Ch is less than 9V • MOSFET_FULLY_ON – Term that turns the MOSFET fully on when the voltage at Ch is greater than 9V. This term is controlled by the sequence controller Equation 6 is a combinatorial equation that turns the MOSFET off as soon as the Short_Ckt signal is equal to logic 0 or when the operating current is greater than 4A. Sequence control: 1. Wait for 12V to be continuously on for 100ms and within tolerance by monitoring the Inp_12V signal. 2. Turn on the hysteric hot-swap action by turning on the En_Hot_swap signal. 3. Wait for the supply at 12V load to be within tolerance by monitoring the Out_12V signal within 10ms. If 10ms timer expires, set En_Hot_Swap signal to 0. 4. Set the TURN_MOSFET_ON_FULLY signal on. 5. Enable the 12V load through the Start_12V_Load signal. Programmable Features This circuit offers many programmable features that make it suitable for a wide range of applications. • Comparator thresholds can be changed to suit different backplane voltages, e.g., 12V or 24V. • Contact de-bounce period can be changed from 50ms to 2 seconds. • Over-current, and short circuit current levels can be set independently. Equation 5: C_Pmp.D = NOT Toggle_C_Pump AND En_Hot_swap AND ((NOT I_IN_2_A AND NOT OUT_12V_GT_6V) OR (NOT I_IN_4_A AND NOT OUT_12V_GT_9V) OR MOSFET_FULLY_ON) Equation 6: Shut_Dn = NOT Short_Ckt or (MOSFET_FULLY_ON AND I_IN_4_A)Power 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-13 • Design can be used to implement dual hot-swap controller for dual supply backplanes using two MOSFET drivers of the ispPAC-POWR1014 device. • Hold-off time programmable from 2 to 100ms (time during which the MOSFET should be left on under supply fault). After this period expires, the MOSFET is turned off. The ispPAC-POWR1014A Can Integrate Other Board Power Management Functions The hot-swap controller uses only about 25% of the ispPAC-POWR1014A device resources. The remaining resources can be used to implement power sequencing, voltage supervision, reset generation and watchdog timer functions for the board. Applicable Power Manager II Devices This example used the ispPAC-POWR1014A device to implement the hysteretic control hot-swap function. However, the hysteretic control can also be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014, and ispPAC-POWR607 devices. 5.3 Implementing a Negative Supply Hot-Swap Controller Figure 5-13 shows the circuit diagram of a -48V hot-swap controller using the ispPAC-POWR607 device. Figure 5-13. Hot-Swap Controller Circuit Using an ispPAC-POWR607 Device The ispPAC-POWR607 controls the MOSFET (STB120NF) shown at the bottom right of the circuit diagram, for inrush current control while operating the MOSFET in its SOA. The controller monitors the circuit current using the current sense resistor shown to the left of the MOSFET. The backplane voltage and -48V 43k 3.3k 6V 3.3k 6V .01µF .05(RS) Voltage Regulator ispPAC-POWR607 100k 100 HVOUT2 HVOUT1 VMON6 VMON5 VMON4 VMON3 VMON2 VMON1 GND VCC Vin_High Vin_OK VDS_2 VDS_1 Isense_2 Isense_1 Gate_Drive_2 Gate_Drive_1 Ch IN/OUT3 Enable_Load 43k IN2 Q2 Q3 VCC_607 GND_607 VCC_607 VCC_607 GND_607 IN/OUT4 Shut_Dn R2 R1 -48V Return Load STB120NFPower 2 You: A Guide to Power Supply Management and Control 5-14 Hot-Swap Controllers the voltage across the MOSFET are monitored using two potential dividers of 43K and 3.3K. The 6V zener diode is used to protect the ispPAC-POWR607’s input section. When the blade is plugged into the backplane, the ispPAC-POWR607 waits for the contact bounce to settle and then begins to charge the hold-off capacitor, using current pulses instead of a continuous current feed. The rate of current pulses is programmable to meet the MOSFET's power dissipation characteristics. Once the voltage reaches a preset threshold, the rate of current pulses is increased to hasten the charging of the hold- off capacitor. After the hold-off capacitor is completely charged, the MOSFET is fully turned on and the Power_Good Signal is activated. This signal is used to enable the DC-DC converter. The voltage across the MOSFET is monitored by the two voltage monitoring inputs of the ispPAC-POWR607. The programmable threshold set for the first voltage monitoring (Fast Charge Duty Cycle Threshold) input determines the changeover from slow charging to faster charging of the hold-off capacitor. The second threshold (End of Soft Start) indicates the completion of the charging of the holdoff capacitor and to fully turn on the MOSFET. The ispPAC-POWR607 waits for a preset period (determined by the short circuit watchdog timer) for the voltage across the MOSFET to drop below the fast charge threshold. If the voltage across the MOSFET does not drop below the fast charge threshold, the MOSFET is turned off, indicating a fault such as a short circuit. With this implementation, the MOSFET continues to operate within its Safe Operating Area, even if a short circuit is present. During normal operation, the ispPAC-POWR607 senses the beginning of a brownout period when the backplane voltage drops below a preset threshold and initiates an internal programmable timer of 10ms. If the power supply recovers within that time, the circuit continues to function normally. If the 10ms timer expires, the hot-swap controller classifies it as an under-voltage event and jumps to the power recycle routine, waiting for the supply to stabilize before initiating a recharge of the hold-off capacitor. During normal operation, when a card is plugged into the backplane, the backplane supply dips momentarily. During the voltage dip period, all cards use the hold-off capacitor to remain functional. Consequently, the hold-off capacitor loses some charge. When the backplane recovers, the charge in these capacitors is replenished. This results in a brief current spike, usually less than 100s. This should be ignored by the hot-swap controller. However, if there is a catastrophic current fault on the board, the hotswap controller should respond to this high current and shut the MOSFET down in less than 1s to prevent fault propagation and to prevent damages to the MOSFET. The transistor Q2 is used to protect the card when the current fault results in very high current. When the voltage across the current sense resistor exceeds 0.7V, the transistor Q2 turns on and applies a logical 0 to the digital input of the ispPACPOWR607. The logic equation within the ispPAC-POWR607 then turns on the transistor Q3 . Q3 discharges the MOSFET gate charge, resulting in turning the MOSFET off within 1s. Controlling Current Inrush While Operating the MOSFET in its Safe Operating Area The top trace of the oscilloscope in Figure 5-14 shows 10ms wide, 1.5A current pulses charging the holdoff capacitor. The bottom trace is the voltage across the MOSFET while charging a 4700F hold-off capacitor.Power 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-15 Figure 5-14. Hold-off Capacitor Charging Current and Voltage Across the MOSFET Two of the ispPAC-POWR607’s MOSFET drivers drive the MOSFET gate. One MOSFET driver maintains the current amplitude at 1.5A, and the second MOSFET driver controls the modulation rate. In this circuit, the duty cycle was limited deliberately to one 10ms pulse every 260ms. This limits the worst-case (during short circuit) average power dissipated by the MOSFET to 1.5A * 48V * 5ms / 260ms = 1.4W. Hot-Swap Controller Algorithm • The hot-swap controller algorithm is mainly implemented in an ispPAC-POWR607 device using sequence control. However, the short circuit over current is monitored using a combinatorial logic equation because of speed. Sequence control: 1. Turn-off MOSFET and wait for contact bounce to settle. 2. Until the voltage across the MOSFET drops below 25V, charge the capacitor using 10ms wide 1.5A pulses repeated once every 260ms. If the voltage does not drop below 25V within 512ms, stop hotswap. 3. After the voltage across the MOSFET drops below 25V, increase the duty cycle to 10ms wide 1.5A pulses repeated at a rate of 65ms. 4. Wait for the voltage across the MOSFET to drop below 1V and turn the MOSFET on fully. 5. If an over-current condition occurs, turn the MOSFET off and retry once in two seconds. Customizing the -48V Hot-Swap Controller The entire hot-swap algorithm can be implemented within the 16-macrocell PLD of the programmable hot-swap controller. Designers can customize this algorithm to suit their blade requirements. The following parameters of the programmable hot-swap controller can be customized: • Short circuit watchdog duration: If the hold-off capacitor does not charge in the specified time period, the MOSFET is shut off. If Short_ckt_Det (output of Q2 ) = 0 then turn on Q3 (Q3 discharges the MOSFET gate) INPUT CURRENT 1A/div FET VDS 20V/div 48V 1.5APower 2 You: A Guide to Power Supply Management and Control 5-16 Hot-Swap Controllers • Charging Current Pulse Duration: The pulse width is set to guarantee that the MOSFET operates within its SOA. • Charging Current Pulse Frequency: This parameter, along with the charging current pulse duration, determines the power dissipation for a given MOSFET. • Minimum Hold-off Time Before Recycling: This determines the blade’s immunity to brownouts. • Current Sense Scaling: This is set by the selection of the Rsense (RS ) resistor, R1 and R2. • Height of Charging Current Pulse: Determined by the RS resistor value, sets the amplitude of the charging current pulses. • Circuit Breaker Current: Maximum current value to initiate shut off and re-start. • End of Soft-start Operation: Sets the voltage at which the MOSFET is fully turned on and the Power_Good Signal is generated. • Transition to Fast Charge Duty Cycle: Determines the voltage at which the charge pulse frequency is increased to safely reduce the hold-off capacitor charging time. • Minimum Operating Voltage: Determines the backplane voltage below which the brownout process begins. • Over-Voltage Protection: Above this voltage, the MOSFET is shut off to protect the blade circuitry. Applicable Power Manager II Devices This design is implemented using an ispPAC-POWR607 device. However, the ispPAC-POWR1014A device can also be used to implement the hot-swap controller if the design requires voltage measurement through the I2 C interface. 5.4 CompactPCI Board Management Applications such as CompactPCI or CompactPCI Express use a backplane with multiple power supply rails. Figure 5-15 shows the requirements of the hot-swap controller for CompactPCI standard backplane with voltages of +12V, +5V, +3.3V & -12V. In this design, the +5V and +3.3V rails carry the bulk of the power.Power 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-17 Figure 5-15. CompactPCI Board Power Management Including Hot-Swap The Power Manager II ispPAC-POWR1220AT8 device has been used to implement not only the hotswap controller but also the entire circuit board’s power management, as shown in Figure 5-15. In this design, the 5V and 3.3V hot-swap controllers use the hysteretic current control mechanism (as described in the section “Hot-Swap Controller with Hysteretic Current Limit Mechanism” on page 5-4) and the +12 and -12V use the soft-start control mechanism (described under “Hot-Swap Controller Using Soft-start” on page 5-3). The +12V rail uses a P-Channel MOSFET. CompactPCI Board Management Algorithm The hot-swap controller, after initiating the hysteretic and soft-start functions, waits for the board supplies to reach normal operating levels within the watchdog time period and then activates the Healthy# signal. /BD_SEL +12V /PCI_RST /HEALTHY Board-level Power Management +12V Board +5V Board +3.3V Board -12V Board /Local_PCI_RST CPCI Bus Board-side Power POL 1.8V POL 1.2V 1.8V Board 1.2V Board /en /en +5V +3.3V -12VPower 2 You: A Guide to Power Supply Management and Control 5-18 Hot-Swap Controllers Figure 5-16. ispPAC-POWR1220AT8 Device – Complete CompactPCI Board Management If the hot-swap function fails, the Healthy# signal is not activated and the main system does not activate the PCI card. One can then re-initiate the hot-swap function by extracting and re-inserting the board into the backplane. After all hot-swapped rails reach normal operating value, the ispPAC-POWR1220AT8 device initiates the sequencing of 2.5V and 1.8V supplies. After all supplies are stable (including the onboard sequenced supplies), the CPU reset signal (CPU_RSTb) is activated. If any supply fails, the brown_out signal is activated. Programmable Features The circuit shown in Figure 5-16 can be customized for the following: • Over-current for 5V and 3.3V • Sequencing of board mounted voltage • Protecting against board faults – Turn off all hot-swap MOSFETs • Generating other board specific power management signals • Measuring voltage and current • Trimming and margining of supplies Applicable Power Manager II Devices This example shows CompactPCI Express board power management functions implemented using an ispPAC-POWR1220AT8 device. If the CompactPCI Express board required the hot-swap function and minimal board management, then a ispPAC-POWR1014A device would be sufficient. +12V +5V Q1 Q2 Ch 1.8V POL 2.5V POL BRD_SEL# PCI_RST_b Brown_Out CPU_RSTb 12V 1.8V 2.5V 5V 3.3V I_Sens3V3 FETDRV3V3 V_Sens3V3 I_Sens5V FETDRV5V V_Sens5V V_In_12V FETDRV12V V_Sens12V En_1V8 En_2V5 SCL SDA ispPAC-POWR1220AT8 -12V +3.3V En_Neg12 Healthy# -12V +3.3V CSA CSA Q3Power 2 You: A Guide to Power Supply Management and Control Hot Swap Controllers Hot-Swap Controllers 5-19 CompactPCI Express Board Management CompactPCI Express backplanes are similar to CompactPCI backplanes. However, the 12V supply is also required to carry the bulk of the power in addition to +5V and 3.3V rails. Figure 5-17. Complete CompactPCI Express Board Power Management The difference between the CompactPCI and CompactPCI Express board power management implementation (Figure 5-17) is that in this circuit the 12V hot-swap uses a hysteretic current control mechanism. The +5V and +3.3V hot-swap implementation is the same as the one described in “Hot-Swap Controller with Hysteretic Current Limit Mechanism” on page 5-4. The 12V hot-swap mechanism is described in “12V/24V Hot-Swap Controller” on page 5-8. Programmable Features • The secondary board power management section can be completely customized to meet board management needs. • Power rail voltage and current can be measured through I2 C. • 12V hot-swap behavior can be adjusted to meet the characteristics of any MOSFET. Applicable Power Manager II Devices This example shows CompactPCI Express board power management functions implemented using an ispPAC-POWR1220AT8 device. If the CompactPCI Express board required the hot-swap function and minimal board management, then a ispPAC-POWR1014A device would be sufficient. +12V +5V +3.3V Q5 Q1 Q2 D2 C2 C_Pmp S_Dn Q3 Ch 3.3V ATNSW# PRSNT# PWREN# PERST# MPWRGD 12V 1.8V 2.5V 5V 3.3V I_Sens3V3 FETDRV3V3 V_Sens3V3 I_Sens5V FETDRV5V V_Sens5V V_In_12V I_Sens12V FETDRV12V Sh V_Sens12V ut_Dn En_1V8 En_2V5 SCL SDA CSA CSA 1.8V POL 2.5V POL Q4 CSA ispPAC-POWR1220AT8Power 2 You: A Guide to Power Supply Management and Control 5-20 Hot-Swap Controllers This page intentionally left blank.CHAPTER 6 6-1 Power Supply OR’ing Controllers 6.1 What is Power Rail OR'ing? One method used to increase the reliability of high availability systems is through the use of systems that are powered by two or more (redundant) power supplies. These supplies are generated either by multiple sources or the system is connected to the main supply by the use of multiple paths. Boards connected to these redundant supplies derive a single high availability rail through the use of diodes, as shown in Figure 6-1. This arrangement is called a power rail OR’ing. Figure 6-1. N-supply OR’ing Control Using Diodes This is a simple arrangement. Only the supply that has the highest voltage drives the main board voltage. Also, if the supply voltages are roughly equal, the load power is shared between each source. If a supply fails, the load is transferred to other supplies automatically without any interruption. Although this is the simplest and most reliable way of OR’ing supplies, this circuit has a disadvantage: it wastes power. Diodes usually drop about 700mV. If the load current is, say, 2A, the power dissipated by the diode is 1.4W. If there are ten boards in a shelf, the power dissipated is 14W, which stresses the cooling system. In addition, diodes that can dissipate more than 2W must be used. These diodes are not only expensive but also are large, requiring more circuit board area. Vin A Vin B Vin N I = 2A Vdiode = 700mV Vin to Board Power Dissipated = 1.4WPower 2 You: A Guide to Power Supply Management and Control 6-2 Power Supply OR’ing Controllers To minimize the power dissipation, some designs use Schottky diodes. These diodes drop about 400mV, resulting in approximately half the power dissipation. Nonetheless, the dissipated power is still too high, and Schottky diodes are usually more expensive. Modern power OR’ing circuits use MOSFETS (Figure 6-2) to reduce the power dissipation significantly. Typical turn-on resistance of an N-channel MOSFET is about 25mΩ, so the power dissipated by this MOSFET at 2A is 100mW (2*2*25 E-3). In other words, the power dissipation is reduced by 93%. Figure 6-2. Power Supply OR’ing Control Using MOSFETs to Reduce Power Dissipation 6.2 Challenges of Designing a MOSFET OR’ing Circuit When turned on, MOSFETs allow current to flow in both directions. Consequently, a voltage difference between any two rails results in a reverse current flow into the lower voltage supply rail. For example, a 1V difference between VinA and VinB can result in 20A (1V / (0.025 +0.025)) flowing from the higher voltage supply into a lower supply rail. This causes overloading of supplies and, in some cases, damage to the supplies. To prevent reverse currents, a power supply OR’ing control circuit is required. There are two methods used for preventing the reverse current: • Monitor current through the MOSFET and turn off the MOSFET, which has less current than the threshold. Current dropping below the threshold can indicate reverse current build up in that limb. If the current in all the limbs is greater than the minimum threshold, all the MOSFETs are left turned on in order to enable load current sharing. • Monitor the voltage difference between the rails of the input supplies and turn off the MOSFET that is connected to the lower voltage rail. When the voltage difference between the two rails is less than a diode voltage drop, then both MOSFETs are left on, the current to be shared. The following section discusses positive voltage and negative voltage OR’ing circuits implemented using Lattice Power Manager II devices. Vin A Vin B Vin N Vin to Board V mosfet = 50mV Power Dissipated = 100mW I = 2APower 2 You: A Guide to Power Supply Management and Control Power Supply OR’ing Controllers Power Supply OR’ing Controllers 6-3 6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit The circuit in Figure 6-3 shows OR’ing of two 5V supply rails, 5V_a and 5V_b. The OR’ing control algorithm is implemented in a ispPAC-POWR1014A device. The current through each limb is monitored by the ispPAC-POWR1014A device through current sense amplifiers CSA_a and CSA_b. MOSFETs Q1 and Q2 implement the OR’ing function. The common 5V supply rail is derived by combining the drain terminals of Q1 and Q2 . When both MOSFETs are off, their body diodes provide an inefficient OR’ing mechanism. In Figure 6-3 the OR’d supply feeds a hot-swap controller. Figure 6-3. An ispPAC-POWR1014A Device Implementing Two-Rail 5V OR’ing Control The circuit starts with both MOSFETs turned off. The load is turned on by enabling the hot-swap controller. When the load starts drawing power, it automatically draws power from one of the MOSFET body diodes. If both voltages are very close, the load pulls current from both the MOSFET body diodes, and both are sensed by the respective current sense amplifiers. The ispPAC-POWR1014A device turns on the MOSFET on a limb only if the current through that limb is above a threshold value. If the current in both rails is above their thresholds, then both MOSFETs are turned on. The ispPAC-POWR1014A device continues to monitor the current level in both limbs. During operation, if the current through one of the MOSFETs drops below its low current threshold (due to a sudden drop of Inp_5Vb Hyst_Ctrl Q2 5V_Hot-swap Inp_5Va I_Inb Rs R2 Q1 Rs R1 5V_a Start 5V_Hot-swap CSA A VMON1 VMON2 VMON3 VMON4 HVOUT1 OUT3 SCL SDA ispPAC-POWR1014A 5V_b I_Ina ADC CSA B HVOUT2Power 2 You: A Guide to Power Supply Management and Control 6-4 Power Supply OR’ing Controllers that power rail’s voltage), then that MOSFET is instantly turned off. When the MOSFET is turned off its body diode blocks the reverse current. Because the MOSFET is turned off when the current drops below the positive threshold, the reverse current that would be driven back into the power supply is avoided. In effect, this circuit implements OR’ing of supply rails through a proactive reverse current avoidance method. Algorithm for Implementing OR’ing through MOSFETs Step 1 – Wait for at least one of the rails to reach operating voltage value. Step 2 – Enable the load or the hot-swap controller. Step 3 – Wait for the load to turn on. Step 4 – If the current in Limb A is greater than its turn-off threshold, turn on the MOSFET. Step 5 – If the current in Limb B is greater than its turn-off threshold, turn on the MOSFET. Step 6 – Wait for either of the currents in the MOSFETS that are turned on in a limb to drop below its turn-off threshold. If the current drops below the turn-off threshold, turn it off and wait for the current to increase above the turn-off threshold, then turn the MOSFET back on. Continue executing step 6. Programmable Features The following programmable features enable the design described above to meet the needs of a wide variety of OR’ing circuits. • Individually program thresholds of two comparators to implement hysteresis using a logic equation for MOSFET turn on current and MOSFET turn-off current levels. • Programmable thresholds for determining the valid input operating voltage range. Additional Functions That Can be Integrated into the ispPAC-POWR1014A Device • Hot-swap controller – Either soft start or hysteretic current controller. – One of the MOSFET drivers can be freed to implement the hot-swap controller by using the transistor circuit shown in Figure 6-4 on page 6-6. • Integrate sequencing. • Integrate voltage supervision, reset generation and watchdog timer functions. Applicable Power Manager II Devices Driving a 5V rail requires a MOSFET drive of 12V. This feature is supported in the ispPACPOWR1220AT8, ispPAC-POWR1014 and ispPAC-POWR1014A devices.Power 2 You: A Guide to Power Supply Management and Control Power Supply OR’ing Controllers Power Supply OR’ing Controllers 6-5 6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS A ispPAC-POWR1014 device supports two MOSFET drive circuits; however, each MOSFET drive can drive gates of multiple MOSFETs simultaneously. The circuit in Figure 6-4 makes use of this feature to implement N-supply rail OR’ing through a MOSFET using one HVOUT signal from the Power Manager II device. The operating principle of this circuit is the same as above. The only difference here is that a four-transistor circuit is used to drive the MOSFET gate, as shown in the inset block as OR MOSFET Control. The P1 PNP transistor is turned on to enable the voltage and current from HVOUT to the gate of the MOSFET. P1 is turned on when N2 turns on, which is when the OUT pin of the ispPAC-POWR1014 is at Logic 0 (N1 is off). At that time N3 is also off. To turn the OR MOSFET off, digital output is set to Logic 0. At that time N2 turns off and N3 turns on, draining the charge stored in the MOSFET gate, which turns it off immediately. The diode D1 is introduced in the base circuit of the N3 to delay turning on N3 compared to N1 , and to turn the N3 off before N1 . This avoids the condition where P1 and N3 are both on at the same time, preventing turning off the other MOSFETS in the OR circuit.Power 2 You: A Guide to Power Supply Management and Control 6-6 Power Supply OR’ing Controllers Figure 6-4. N-Channel OR’ing through MOSFETS Algorithm Implementing N-channel OR’ing through MOSFETs Step 1 – Wait for at least one of the rails to reach operating voltage value. Step 2 – Enable the load or the hot-swap controller. Step 3 – Wait for the load to turn on. Step 4 – If the current in Limb A is greater than the minimum threshold, turn on the MOSFET through the corresponding digital control. Step N – If the current in Limb N is greater than its minimum threshold, turn the MOSFET on. Step N+1 – Wait for either the current through the limb whose MOSFET is turned on to drop below the threshold and then turn it off, or wait for the current in the limb whose MOSFET is turned off to go above threshold and then turn that MOSFET on. Continue executing step N+1. 3.3V HVOUT1 Gate OUT OR MOSFET Control P1 N1 N2 N3 D1 Inp_5Vb Qn 5V_Hot-swap Inp_5Va I_Inn Rs Rn Q1 Rs R1 5V_a Start 5V_Hot-swap CSA a VMON1 VMON2 VMON3 VMON4 HVOUT1 OUT3 SCL SDA ispPAC-POWR1014A 5V_n I_Ina ADC CSA n OUT8 OUT9Power 2 You: A Guide to Power Supply Management and Control Power Supply OR’ing Controllers Power Supply OR’ing Controllers 6-7 (Steps N+1 is implemented using logic equations for all N-MOSFETs such that the circuit monitors and controls all MOSFETs in parallel.) Programmable Features The following programmable features enable the design described above to meet the needs of a wide variety of OR’ing circuits. • Individually program the thresholds of two comparators to implement hysteresis (using logic equations) for MOSFET turn-on current and MOSFET turn-off current levels. • Programmable thresholds for determining the valid input operating voltage range. Additional Functions That Can be Integrated Into the ispPAC-POWR1014A Device • Hot-swap controller – Either soft start or hysteretic current controller. The OR’ing circuit uses only one MOSFET drive output. The second MOSFET drive can then be used to implement the hot-swap controller. • Integrate sequencing. • Integrate voltage supervision, reset generation and watchdog timer functions. Applicable Power Manager II Devices Driving a 5V rail requires a MOSFET drive of 12V. This feature is supported in the ispPACPOWR1220AT8, ispPAC-POWR1014 and ispPAC-POWR1014A devices. 6.5 N-rail (12V/24V) OR’ing The operating principle of the N Rail 12V OR’ing with MOSFET is the same as that of the N-Rail 5V OR’ing with MOSFET. The difference is that the gate of the N-Channel MOSFET on the 12V rail requires higher voltage than the one supplied by the HVOUT pin of the ispPAC-POWR1014 device. In addition to the blocks shown in Figure 6-4, Figure 6-5 shows an additional c-pump block at the bottom right corner that implements an external charge pump to generate 20V at the MOSFET gate.Power 2 You: A Guide to Power Supply Management and Control 6-8 Power Supply OR’ing Controllers Figure 6-5. N- 12V Rail OR’ing through MOSFET Using an ispPAC-POWR1014A Device 3.3V CPOUT Gate OUT OR MOSFET Control P1 N1 N2 N3 D1 Inp_12Vb Qn 12V_Hot-swap Inp_12Va I_Inn Rs Rn Q1 Rs R1 12V_a Start 12V_Hot-swap CSA a VMON1 VMON2 VMON3 VMON4 HVOUT1 OUT8 SCL SDA ispPAC-POWR1014A 12V_n I_Ina ADC CSA n P2 C2 C1 D2 D3 OUT3 OUT9 CPOUT HVOUT 12V_n 12V_a C-PumpPower 2 You: A Guide to Power Supply Management and Control Power Supply OR’ing Controllers Power Supply OR’ing Controllers 6-9 Operating Principle of the C-Pump Block The HVOUT pin of the ispPAC-POWR1014A device toggles, outputting 12V for 32s and 0V for 8s. When the HVOUT pin is at 0V, the capacitor C1 gets charged to a voltage that is highest of all 12V rails through the diode D2. When the HVOUT pin is at 12V, this voltage is then added to the capacitor (C1 ) voltage and that turns the transistor P2 on and charges C2 through diode D3 to approximately 20V. This voltage is then routed to the MOSFET gates through the OR MOSFET control block. The ispPAC-POWR1014 device, like the N-rail (5V) OR’ing circuit operation, then monitors the currents through the rails and turns on the corresponding MOSFET if its current is higher than the turn-on threshold. Algorithm Implementing N-Channel OR’ing Through MOSFETS Step 1 – Wait for at least one of the rails to reach operating voltage value. Step 2 – Enable the load or the hot-swap controller. Step 3 – Wait for the load to turn on. Step 4 – If the current in Limb A is greater than the minimum threshold, turn on the MOSFET through the corresponding digital control. Step N – If the current in Limb N is greater than its minimum threshold, turn the MOSFET on. Step N+1 – Wait for either the current through the limb, whose MOSFET is turned on, to drop below the threshold and then turn it off, or wait for the current in the limb whose MOSFET is turned off to go above threshold and then turn that MOSFET on. Continue executing step N+1. (Steps N+1 is implemented using logic equations for all N-MOSFETs such that the circuit monitors and controls all MOSFETS in parallel) Programmable Features The following programmable features enable the design described above to meet the needs of a wide variety of OR’ing circuits. • Individually program the thresholds of two comparators to implement hysteresis through logic equations for MOSFET turn-on current and MOSFET turn-off current levels. • Programmable thresholds for determining the valid input operating voltage range. Additional Functions That can be Integrated Into the ispPAC-POWR1014A Device • Hysteretic current control hot-swap controller. The OR’ing circuit uses only one MOSFET drive output. The Second MOSFET drive then can be used to implement the hot-swap controller. • Integrate sequencing. • Integrate voltage supervision, reset generation and watchdog timer functions.Power 2 You: A Guide to Power Supply Management and Control 6-10 Power Supply OR’ing Controllers Applicable Power Manager II Devices 12V rail OR’ing using MOSFETS can be implemented using ispPAC-POWR607, ispPACPOWR1220AT8, ispPAC-POWR1014 and ispPAC-POWR1014A devices. 6.6 -48V Supply OR’ing Through MOSFETS The circuit shown in Figure 6-6 monitors the voltage difference between the two -48V voltage rails using a simple resistive voltage divider. In the following circuit there are two rails, -48VA and -48VB. Initially the MOSFET is off and the OR’ing function is performed by the body diodes. The voltage difference between the two rails is monitored by the resistors R1 through R4 . The values are selected such that when the voltage difference is greater than 0.4V, a Schottky turn-on voltage, the corresponding node A_Hi or B_Hi goes above 0.75V. The logic equation within the ispPAC-POWR607 device turns the MOSFET on and the less negative rail is turned off, preventing reverse current. If the voltage difference between the two rails is less than 0.4V, both MOSFETS will be turned on. Figure 6-6. Dual -48V MOSFET OR’ing Circuit Using an ispPAC-POWR607 Device Programmable Features The values of R1 , R2 , R3 and R4 are selected such that there is a dead band of 0.4V about the common - 48V rail. That is, if the -48VA and -48VB are within 0.4V of each other, both the MOSFETS are turned on. This dead band voltage value can be changed by selecting a different potential divider setting. Additional Functions That Can Be Integrated Into the ispPAC-POWR607 Device One of the useful functions that can be added to the circuit shown in Figure 6-6 is monitoring of -48VA and -48VB rails, as well as monitoring for fuse failure as shown in Figure 6-7. The voltage monitoring section generates two fault signals: Battery_Fail_VA and Battery_Fail_VB. These signals also become active when the corresponding fuse fails. If all the boards in the shelf show a battery failure, then it indiAlgorithm: If A_Hi is True, Turn on Q1 If B_Hi is True turn on Q2 -48VA -48VB 10K 10K A_Hi B_Hi A_On B_On Start_HS Q1 Q2 R1 R2 R3 R4 To Hot-swap Controller BRD -48V HVOUT2 GND HVOUT1 VMON6 VMON5 OUT5 ispPACPOWR607 3K 3KPower 2 You: A Guide to Power Supply Management and Control Power Supply OR’ing Controllers Power Supply OR’ing Controllers 6-11 cates the main battery failure. However if one of the cards indicate the battery failure, it indicates a fuse fault. Figure 6-7 shows the -48V voltage sensing circuit that uses two 50kΩ resistors (R1 and R2 ) to monitor the voltage. The voltage at the junction of R1 and R2 determines the current through the resistors R2 , R4 and the transistor P1 . The ispPAC-POWR607 monitors the voltage across the resistor R4 , which is proportional to the voltage across the resistors R1 and R2 . The second ispPAC-POWR607 device performs the hot-swap function in hot-swappable boards. The voltage monitoring, fuse fault monitoring, MOSFET OR'ing, and hot-swap control functions can be integrated into an ispPAC-POWR1014 device. In addition, if power measurement is required, one can use an ispPAC-POWR1014A device instead of the ispPAC-POWR1014 device and use a opamp circuit to amplify the current through the circuit. Figure 6-7. Voltage Monitoring in Addition to OR’ing Two -48V Rails Using an ispPAC-POWR607 Device Figure 6-8. -48V Rail Voltage Monitoring Circuit Shown as Vsense A and VSense B Blocks in Figure 6-7. Applicable Power Manager II Devices This circuit can be implemented using the ispPAC-POWR607 or ispPAC-POWR1014A devices. 48V Return 10K 10K 3K A48_OV A48_UV B48_OV B48_UV A_Hi B_Hi A_On B_On Battery_Fail_VA Battery_Fail_VB Start_HS Enable_Load On_Off HS_Complete L O A D Enable_Load IN1 IN2 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 HVOUT1 GND HVOUT2 OUT3 OUT4 OUT5 OUT6 ispPAC POWR607 Hot-Swap Controller ispPACPOWR607 #2 Vsense A Vsense B -48VA -48VB -48V Rtn -48V A/B 50K 50K 50K 3K VMON of ispPAC-POWR607 GND of ispPAC-POWR607 R1 R2 R3 R4 P1Power 2 You: A Guide to Power Supply Management and Control 6-12 Power Supply OR’ing Controllers This page intentionally left blank.CHAPTER 7 7-1 Power Feed Controllers 7.1 What are Power Feed Controllers? In many systems, including base stations, microwave add-drop multiplexers and MicroTCA shelves, a circuit board is required to feed power to an external system. In base stations, the power is for a remote radio head; in the case of a microwave system, an external modem and an antenna on a tower require power to be sourced from the system on the ground; and in the case of MicroTCA, the power module is needed to feed power to multiple Advanced Mezzanine cards plugged into the same shelf. In most of these cases, the power feed is required to monitor for faults such as over current and under current, as well as to provide short circuit protection. This chapter discusses -48V and 12V power feed arrangements because they are the most common. These designs can be modified to support other voltages as well. 7.2 Dual Rail -48V Supply Feed The circuit shown in Figure 7-1 uses MOSFETs to control the power feed to two -48V rails. To prevent damage to the MOSFETs during the power feed event, the current through the MOSFET is limited using a hysteretic current control mechanism for a fixed period. After that period, the MOSFET is fully turned on and the circuit goes on to monitor the currents for over current and under current faults. There are three types of current faults that can occur in power feed circuits: 1. No current fault – If the external cable is broken 2. Over current fault- External system draws more current than normal (not dangerously high current) 3. Short circuit current fault – Dangerously high current due to a short circuit in the power feed cable If a no-current or over-current fault is detected, the fault flag becomes active for that channel. If a short circuit is detected, the MOSFET is shut down in less than 500ns. After a fault is Power 2 You: A Guide to Power Supply Management and Control 7-2 Power Feed Controllers detected, the circuit tries continuously to restart the power feed as long as the enable signal is active for that channel. Figure 7-1. The ispPAC-POWR607 Device Implements a Dual-Channel -48V Power Feed Circuit Circuit Operation The circuit generates two channels of power, -48V_1 and -48V_2, through the MOSFETs Q1 and Q2 . The open circuit current limit (the value below which the circuit is assumed to be open) is set by the resistors RS 1 and RS 2. The monitoring threshold voltage of VMON1, VMON2, VMON3 and VMON4 pins of the ispPAC-POWR607 device are set to 0.075V. The values of series resistors RS 1 and RS 2 are selected such that at the lower current limit the voltage dropped across the RS 1 and RS 2 is 0.075V. The over current limit is set by the resistors R1 and R2 for the power feed 1, and R3 and R4 set the over current limit for power feed circuit 2. R1 and R2 are selected such that R1 / (R1 +R2 ) = 0.075V when maximum current is flowing through the RS 1 resistor. In other words, Imax * RS 1 * R1 / (R1 +R2 ) = 0.075V. The values of R4 and R5 are also selected using the same equation. When the enable signal is activated, the circuit turns on the MOSFET with the current limited to a value determined by the programmed over current limit for a period determined by the Timer 1 for power feed 1 and Timer 2 for the circuit 2. After Timer 1 or Timer 2 expires, the corresponding MOSFET is fully turned on and the circuit starts to monitor for over and under current. Note: The selected MOSFET should be able to handle the maximum current for the duration determined by Timer 1. After the MOSFET is fully turned on, if an over or under current condition is detected, the MOSFET is turned off through the transistor N1/ N2, and Timer 3 and Timer 4 (retry timers) are started. When the retry timer expires, the MOSFET is turned back on with an initial hysteretic control, as before. If the circuit detects a very high current (as detected by 0.7V across the series resistors RS 1, RS 2) the transistors N3, N4 pull down signal SC1 and SC2. These signals are connected to the digital inputs of the ispPAC-POWR607 device. The logic equations within the ispPAC-POWR607 device shut the MOSFET SC_2 Fault_1 R1 R2 R3 R4 Rs1 Rs2 Q2 N1 N2 100K 100K VMON 1 VMON 2 HVOUT1 VMON 3 VMON 4 HVOUT2 OUT3 OUT4 -48V_1 -48V_2 Fault_2 OUT6 OUT5 OC_SCb OUT7 ispPAC-POWR607 -48V_IN SC_1 GND -48V_Rtn 3V3 Reg Vcc SC_2 SC_1 En_2 En_1 VMON 6 VMON 5 IN1 IN2 N3 N4 Q1Power 2 You: A Guide to Power Supply Management and Control Power Feed Controllers Power Feed Controllers 7-3 Q1 , Q2 down immediately through N1 , N2 (in less than 500ns) and the retry timer is started. After the retry timer expires, the transistor N1 , N2 that shuts down the MOSFET is turned off. The Fault 1 and Fault 2 signals are controlled by a routine that monitors over and under current conditions in each of the circuits. When an over current fault occurs, the corresponding flag is set to high. Along with that, the UC_OCb (under current and over current flag) will be set to logic 0. If an under current event is detected, the UC_OCb signal will be set to Logic 1. If the fault exists in both circuits 1 and 2, then the status flag toggles between the conditions once every 8ms. Algorithm The design is implemented using logic equations to provide independent operation on each of the channels. The following algorithm makes use of simple logic equations. There are five equations that control the power feed for one of the circuits. All equations are active in parallel. For example, the short circuit monitoring section is always active and shuts the MOSFET down if a short circuit occurs when any one of the other four equations are operational. This algorithm (set of five equations) is repeated for the second channel power feed. The fault indication flags are controlled by the algorithm implemented in the sequence controller section of the algorithm. 1. Equation 1 circuit 1 – Waits for the enable signal to become active to begin the hysteretic controlled power feed. The Power feed is expected to be complete within a preset period set by the hysteretic control timer. The hysteretic control timer is also started when the enable signal gets activated and starts the hysteretic control timer. After the initial hysteretic control timer expires, the MOSFET is turned on fully. If a fault is detected, this equation waits for the retry timer to expire before initiating the hysteretic power feed. 2. Equation 2 circuit 1 – Waits for a short circuit condition detection. When a short circuit is detected, this equation turns the MOSFET off through a fast asynchronous reset signal. 3. Equation 3 circuit 1 – Monitors for over or under current conditions. When such a condition is detected, the MOSFET is turned off and a retry timer (2 seconds) is started. 4. Equation 4 circuit 1 – Monitors for the retry signal and the enable signal to begin the 5ms hysteretic control timer. This hysteretic control timer is used by equation 1. 5. Equation 5 circuit 1 – The fault flag is cleared to recapture the fault condition when the normal operation begins. The fault conditions are reported by the sequence controller. 1. When the circuit 1 is operating normally and a fault has not already been reported, check on circuit 1 for over or under current fault on circuit 1 and, if a fault is detected, activate the Fault_1 output. 2. If it is an over current condition or short circuit condition, turn the UC_UCb flag off. 3. When the circuit 2 is operating normally and a fault has not already been reported, check on circuit 2 for over or under current fault on circuit 2 and, if a fault is detected, activate the Fault_2 output.Power 2 You: A Guide to Power Supply Management and Control 7-4 Power Feed Controllers 4. If it is an over current condition or short circuit condition, turn the UC_UCb flag off or else turn it back on. Programmable Features of this Circuit 1. The over-current, no-current conditions can be set by selecting the RS 1, R1 and R2 for circuit 1 and RS 2, R3 and R4 for circuit 2. 2. Program the hysteretic current timer duration to meet the MOSFET’s safe operating area. Note: Both over current and the duration of hysteretic control duration are determined by the safe operating area of the MOSFET. 3. Retry duration can be set independently for both circuits. Applicable devices: This circuit uses the ispPAC-POWR607 device. 7.3 Three Channels of a +12V Power Feed System In some applications, two or more channels of 12V power feed are required. For such applications, the following three-channel power feed circuit is used. More than three channels of power feed requires multiple implementations of the following circuit. This design is modular in order to address implementations requiring less than three channels of power feed so that free resources can be used for other payload power management functions.Power 2 You: A Guide to Power Supply Management and Control Power Feed Controllers Power Feed Controllers 7-5 Figure 7-2. Three-Channel 12V Power Feed Circuit Figure 7-2 shows a ispPAC-POWR1014A device used to feed 12V to three channels. Each of the channels can be controlled independently. For each channel this circuit offers under current, over current and short circuit current protection, along with fault indication. After the fault is detected, the circuit retries continuously with a programmable delay between retries. The power is controlled through a MOSFET and the circuit ensures operation of the MOSFET in its safe operating area. All voltage and current during the operation can be measured using the on-chip ADC through I2 C. Circuit Operation The ispPAC-POWR1014A device derives its power from the input 12V supply. The operating principle of the external charge pump is as follows (Figure 7-2): The ispPAC-POWR1014A HVOUT pin toggles between 12V (for 32s) and 0V (for 8s) cyclically. When the HVOUT1 pin is at 0V, the capacitor C1 gets charged to backplane voltage of 12V through the diode D2 . At this time the transistor P2 is off. When the HVOUT1 toggles up to 12V, the C1 voltage is added to the HVOUT1 pin voltage, resulting in the generation of approximately 24V at the junction of C1 and D2 . This voltage turns P2 on and charges the capacitor C2 to about 22V through the diode D3 . This voltage is sufficient to turn on the MOSFETs Q1 through Q3 . Inp_12VIn Rs3 Q3 Rs2 Q2 12V_In P2 C2 CPOUT HVOUT C-Pump C1 D2 D3 Rs1 Q1 2 12V#1 12V#2 12V#3 CPOUT I_12V_1, Out_12V_1 SC_1 SC_2 SC_3 EN_1 EN_2 EN_3 SC_1,2,3 3.3V SC I_12V Out_12V CPOUT Drv S_Dn Gate 12V 12V_In Fault_1, Fault_2, Fault_3 ADC ispPAC-POWR1014A VMON1 VMON2,3 VMON4,5 SCL OUT3,4 HVOUT1 SDA VMON6,8 OUT5,6 OUT7,8 VMON9 VMON10 IN1 IN2,3,4 OUT9,10,11 2 2 2 2 2 3.3V CPOUT Gate Drv OR MOSFET Control P1 N1 N2 N3 D1 3.3V 3.3V S-Dn N4 CSAPower 2 You: A Guide to Power Supply Management and Control 7-6 Power Feed Controllers Once on, the device begins toggling the HVOUT1 pin to generate about 22V at the CPOUT pin and waits for a high on any of the 3 EN signals. After receiving the En signal, the corresponding MOSFET is turned on using the dual current level hysteretic control mechanism while monitoring for the output voltage. When, say, the EN_1 signal is turned on, the OUT3 pin is set to logic 0. This turns off the transistor N1 , which in turn turns on the transistor N2 . The transistor N2 provides the gate drive for the transistor P1 , turning it on. The transistor P1 then applies 22V from the CPOUT pin to the gate of the MOSFET Q1 through a resistor, turning it on. If a supply fault is detected, the OUT3 and the OUT4 pins are set to Logic 1. This turns off the transistor P2 and turns on the transistor N4 . The N4 then discharges the MOSFET gate to turn it off immediately. When power feed operation begins the MOSFET Q1 is turned on. As a result, the current through the MOSFET starts to increase significantly. This results in the MOSFET operating outside its safe operation area (SOA), resulting in damage to the transistor. To avoid that damage, the MOSFET is turned on with a hysteretic current control. The following section describes the MOSFET current control operation. Dual Current Level Hysteretic Control Figure 7-3 shows the safe operating area for a MOSFET. This is a Log-Log graph with voltage across the MOSFET (VDS) on the X-axis and current through the MOSFET on the Y-axis. The dotted lines represent the safe operation envelopes for different pulse width durations. When the power is applied to the MOSFET and begins to turn on, the point of operation is at the right bottom side of the graph. The red line indicates the current limit controlled by the hysteretic controller implemented in the ispPACPOWR1014A device. The current through the MOSFET is limited initially to the lower level. This current charges the capacitor on the load, reducing the voltage across the MOSFET. When the voltage across the MOSFET drops to approximately its mid point (for example, 6V), the current is doubled while operating completely within the safe operation area. The first set point current and the second set point values are determined by the safe operation area of the MOSFET as shown by the red line in Figure 7-3. Figure 7-3. Safe Operating Area of MOSFET – (IRF7832) I D , Drain-to-Source Current (A) 100 µs 1 ms 10 ms Tc = 25° C Tj = 150° C Single Pulse 1000 100 10 1 V DS, Drain-to-Source Voltage (V) 1 10 100Power 2 You: A Guide to Power Supply Management and Control Power Feed Controllers Power Feed Controllers 7-7 After the voltage at the load reaches the minimum operating value, the MOSFET is turned on fully. The circuit then begins to monitor for over current and no current faults. When a fault is detected, the corresponding fault output is activated and the circuit waits for the retry delay. During the retry waiting period, the fault indication is maintained. After the retry period, the circuit begins to restart the MOSFET current. If the output voltage does not reach its minimum operating value within 10ms, the fault flag is turned on and the circuit waits for another retry period. Algorithm for Each Power Feed Channel 1. Wait for enable signal. 2. Start power feed and wait for output voltage to reach its minimum operating level within 10ms. This step turns on the MOSFET with two current settings. 3. If the output voltage is within its safe operating level, turn the MOSFET on fully and begin monitoring the output current for over and under current faults. If a fault is observed, flag the fault, then turn the MOSFET off and jump to retry timer. 4. Wait for the retry timer to expire, then jump to step 1 to begin the power feed process. 5. During the four step sequence above, the following operations are performed in parallel: – 12V Power feed control with two-step current feed. – Monitor for short circuit current and turn the MOSFET off within 500ns when a fault is detected. – Monitor for the enable signal and turn off the MOSFET. Programmable Features of Power Feed The following section outlines all the programmable features of this design: 1. Customize the design to meet any MOSFET characteristics: two current levels can be programmed. If the design requires only one current level, the corresponding equation can be changed easily. 2. If faster turn-on times are required, the circuit can be modified to pump larger currents during start up. These new currents can be independent of the min and max operating current limits. 3. The timer used to monitor the initial supply turn-on period is programmable. This design used 10ms. It can be increased or decreased, depending on the design’s requirement. 4. Retry period – this design used a two second timer. It can be programmed from 32s to two seconds in 122 steps. 5. Over current and under current setting – this can be changed simply by altering the threshold of the comparator. Integrating Other Payload Power Management Functions into the ispPACPOWR1014A Device This circuit uses the ispPAC-POWR1014A device to implement three channel 12V power feed functions. Each channel uses three VMON signals, one digital input signal and four output signals. If the circuit requires fewer power feed channels, that portion of the design can be removed and the free resources can be used to integrate other payload power management functions, such as sequencing, monitoring and Power 2 You: A Guide to Power Supply Management and Control 7-8 Power Feed Controllers watchdog timers. This design can also be exported to a ispPAC-POWR1220AT8 device to implement the three channel power feed functions along with other payload power management functions. Applicable Power Manager II Devices This design used the ispPAC-POWR1014 device. However, the power feed algorithm can be integrated into a ispPAC-POWR1220AT8 device, or an ispPAC-POWR607 device can be used to implement the power feed algorithm for each channel. 7.4 2-Channel +12V & 3.3V Power Feed With MOSFET OR’ing In applications such as MicroTCA, the power module is required to implement 16 channels of 12V power feed circuits. Each channel provides power to an Advanced Mezzanine Card (AMC) slot. When an AMC is plugged into the back plane, the power module turns on the 3.3V to power the AMC’s management module. The management module then communicates with a shelf manager, which then orders the power module to turn-on 12V. In some cases, the 12V supply is turned on along with the 3.3V supply and the circuit does not wait for an independent payload power enable signal. The power module then begins to monitor for over current and, if an over current condition is detected, the MOSFET is turned off. During system operation, if the AMC card is extracted the Power Module is required to turn the power off within 100s. For reliability purposes, the 12V and 3.3V supplies are sourced from two different power module cards. Both of these supplies are OR’d on the backplane. At any given time only one of the power modules supplies power to the backplane. The standby power module sets its voltage to a value lower than the online module. To avoid wasting power, MOSFETs are used to provide OR’ing functionality. A detailed description of the MicroTCA power feed standard is beyond the scope of this document. The circuit in Figure 7-4 shows how a ispPAC-POWR1014A device can be used to implement a twochannel power feed.Power 2 You: A Guide to Power Supply Management and Control Power Feed Controllers Power Feed Controllers 7-9 Figure 7-4. One-Channel uTCA Power Feed Using Half of an ispPAC-POWR104A Device Circuit Operation Figure 7-4 shows the circuit required to implement one channel of 12V and 3.3V power feed. The 12V power feed is controlled through two MOSFETs, the Pass device (Q1 ) and the OR’ing (Q2 ) device, shown at the top right section of the circuit. The 3.3V power feed is controlled through a P-Channel MOSFET Q3 using the transistor N3 . When the Enable# signal is active, the 3.3V supply is turned on through the MOSFET Q3 . Subsequently, when the Payload_On signal becomes active, the 12V power is fed to the circuit through the Pass MOSFET Q1 . The pass MOSFET Q1 is turned on using the two-current hysteretic control mechanism. Because Q1 is on the 12V rail, its gate voltage should be at about 20V when it is turned on. The 20V gate drive is generated through the external charge pump implemented using C1 , D1 , P2 , D2 and C2 (the circuit operation described in “Dual Current Level Hysteretic Control” on page 7-6), to ensure that the MOSFET is operated within its SOA. Once the output power is above its minimum operating level, Q1 is fully turned on and the OR’ing MOSFET Q2 is turned on or off depending on the EMMC primary or redundant status. This ensures that only the primary supply wins the OR’ing arbitration. When an over current event is detected, the ispPAC-POWR1014A device shuts Q1 and Q2 down through the transistor N1 . EMMC Alert VMON Open Drain Digital Out HVOUT1 OUT VMON OUT EMMC Primary/ Redundant Enable# Payload On Mgmt Power Control Current Sensing Pass Device OR’ing Device Q1 Q2 12V Payload Power to Load 100 100 4.7M P1 4.7M 0.001µF C2 MMBT 2222A N1 47 D2 P2 0.01µF C1 2.2K Quick Shutoff Output Monitor Half of ispPACPOWR1014A OR-FET Control MMBT 2222A N2 Q3 3.3V Power to Load D1 Open Drain Digital Out Vcc 12V 3.3V + _ 47M 3K N3 6V 1K MMBT2907 Primary Power SourcePower 2 You: A Guide to Power Supply Management and Control 7-10 Power Feed Controllers During Operation 1. If the output supply drops below the minimum threshold (probably because the on-line supply has failed), the standby device turns on the OR’ing MOSFET Q2 and the primary device turns the OR’ing MOSFET off and flags the EMMC Alert signal. This ensures that the AMC does not see its 12V supply voltage dip below its operating level. 2. The current in the 12V supply is also monitored for fault. If the current exceeds the maximum operating level, the Pass MOSFET is turned off, activating the EMMC Alert signal. 3. Before the extraction of the AMC from its slot, the AMC usually sends a signal to the shelf manager. The shelf manager then deactivates its payload power supply by disabling the Payload_On signal. When the payload signal is turned off, the user can extract the AMC from its backplane. Subsequently, when the AMC is extracted, the enable signal gets deactivated and the 3.3V supply feed to the AMC is turned off within 100s. In some cases, the enable payload voltage signal does not exist. In such cases, the design can be modified to support only Step 4. 4. In the case of an accidental AMC card extraction process, both 12V and the 3.3V supplies are turned off at the same time within 100s from the time the enable signal becomes inactive. ispPAC-POWR1014A (MicroTCA) Power Feed Algorithm 1. Wait for the enable signal, and when it becomes active turn the 3.3V supply on. 2. Wait for the Payload_On signal and turn 12V on. This can be modified easily to turn 12V on when the enable signal is activated. If the 12V does not turn on within 10ms, turn 12V off and report the fault. 3. Turn OR’MOSFET on if the card is primary; otherwise, turn the OR’ing MOSFET off. 4. Start to monitor the following and take action: a. Current – Should be lower than the over current limit. If the current is more than the over current limit, shut the Pass MOSFET off and flag the error to EMMC. b. Output voltage – If the voltage is not higher than the lower threshold for primary, then turn the OR’ing MOSFET off and report the error. If the payload voltage is higher than the over-voltage limit, turn the Pass and OR’ing MOSFETs off and report the error to the EMMC. c. If the card is configured as secondary or redundant, and if the voltage is lower than the minimum primary voltage, turn the OR’ing MOSFET on and report the error back to EMMC. d. If the enable signal becomes inactive, turn the Pass and OR’ing MOSFETs off immediately. e. If the primary becomes secondary during operation, turn the OR’ing MOSFET off and monitor for lower than allowed voltage to turn the MOSFET on. f. If the secondary becomes primary, turn the OR’ing MOSFET on and start monitoring for a higher than allowed voltage range.Power 2 You: A Guide to Power Supply Management and Control Power Feed Controllers Power Feed Controllers 7-11 Programmable Features • The power feed turn on monitor duration can be programmed to meet the requirements of different MOSFETs. • The maximum value of the output current can be altered by reprogramming the ispPAC-POWR1014A device’s current monitor thresholds. Other Functional Enhancements • The voltage and current values can be measured through I2 C. • Not all MicroTCA implementations use all of the features specified in the standard. In such cases, one can keep the OR’ing MOSFET off when the current is below a lower threshold limit. This protects against reverse current flow from the secondary when its voltage is higher than the primary. Applicable Power Manager II Devices While up to four channels of Power Feed can be implemented in a ispPAC-POWR1220AT8 device, an ispPAC-POWR607 device can be used to power a single channel.Power 2 You: A Guide to Power Supply Management and Control Power Feed Controllers Power Feed Controllers 7-12 This page intentionally left blank.CHAPTER 8 8-1 Margining and Trimming 8.1 What is Voltage Margining? Margining is a test step that ensures a board is operational across the input variable range. A voltage margining test ensures that the board is functional across the operating range of its onboard and input supplies. Circuit boards are also subject to other margining tests such as temperature, timing and noise. For example, if the allowed tolerance of input supply is ±10%, the voltage margining test ensures that the board is functional when the input supply is at its margin-high (nominal voltage + 10%) value and when its supply is at margin-low (nominal voltage -10%) value. If the board has a number of board-mounted supplies, then the margining test should also cover the variation of individual board-mounted supplies. Semiconductor devices typically operate slowest when their operating temperature is at its highest value and applied voltages are at their lowest. Similarly, these devices are fastest when the operating temperature is at its lowest and the voltages are at their highest. To ensure that the design is stable across temperature and voltage, designers subject their circuit boards to high temperature in an environmental chamber with the operating voltages dialed down, and then check the operation at colder temperatures with their voltages dialed up. This is called 4-corner testing. Margining tests typically are conducted during board debug. In some cases, Quality and Reliability departments will require margining before they will approve manufactured boards. 8.2 Voltage Margining Implementation Figure 8-1 shows a DC-DC converter with a resistor connected to its Trim/ Feedback Node. The value of this resistor typically determines the nominal output voltage value of the DC-DC converter.Power 2 You: A Guide to Power Supply Management and Control 8-2 Margining and Trimming Figure 8-1. Supplies are Margined by Changing the Resistor Connected to the Trim/FB Node DC-DC converters usually require standard resistor values to set their output voltage to a standard value – e.g., 3.3V, 2.5V, 1.5V. To change the output voltage by ±5% of their nominal operating voltage, designers use either a potentiometer for each of the DC-DC converters or a series parallel combination of standard resistor values. One has to manually implement the resistor change to all the boards that will be subject to testing in an environmental chamber. Some disadvantages of manually altering resistor values for margining: • Increased Delay - finding resistor values that accurately alter the output voltage often require a series and/or parallel combination of standard resistors that must be manually soldered. Different resistor combinations for each of the supplies must be found. Sometimes the board failures in the environmental chamber could be due to bad solder joints caused by manual soldering. Even if a potentiometer is used, the moisture in the environmental chamber creates contact problems that delay the margin test. • Manually soldering a resistor for margining cannot be used for automated reliability testing. • Due to accuracy requirements, manual methods cannot be used for margining the low core supply voltages of modern VLSIs and CPUs. 8.3 What is Trimming? Modern circuit boards require multiple DC-DC converters with low voltages (1.2V or less) with high current capacity. A specification of 10A to 20A at such low voltages is not uncommon. In addition, ICs require very tight output voltage regulation of approximately 1.5% or less to ensure that there is enough headroom to meet the dynamic current requirements of the CPU/ASIC without violating the input voltage specs. Trimming is the process of accurately setting and maintaining the output voltage of a DC-DC converter close to a pre-determined value across voltage and temperature. Margining is a special case of trimming. Trimming also uses the same mechanism shown in Figure 8-1 to set a given voltage. However, to meet accuracy requirements of 1.5% or better, DC-DC converters use very high accuracy (0.1% or better) trim resistors to set the output voltage. In some cases, laser trimmed resistors and compensating resistors are used to allow for converter to converter output voltage accuracy differences. As can be seen, when the DC-DC converter is required to meet high accuracy demands, cost increases significantly. In some cases, digital power converters are used to meet these high power and high current demands. These DC-DC converters are more expensive, as they require ADCs, DACs and accurate voltage references. DC-DC Converter Trim/ FB V OUT R Margined voltage Note: Change R to increase or decrease the output nominal voltage by +/-5%. Power 2 You: A Guide to Power Supply Management and Control Margining and Trimming Margining and Trimming 8-3 Typical Applications That Require Power Supply Trimming Trimming is required for circuit boards using ICs that require low supply voltages (1.2V or lower) with high current ratings (5A or more). For example, a 1.2V DC-DC converter should guarantee a maximum of ±5% (±60mV) variation under all of the following conditions: • No-load to full-load average current variation • Output voltage ripple • Dynamic power demands by the IC during different average current levels • Component tolerances during manufacturing In general, to meet the voltage device spec under all of the above conditions safely, the DC-DC converter requires an initial operating voltage accuracy of 2% or better. These high accuracy, low voltage supplies are usually more expensive and require high precision resistors to set the voltage. Alternatively, the accuracy of a conventional lower cost DC-DC converter can be improved by using an external trimming mechanism. The next section describes trimming using the Lattice Power Manager II IC. 8.4 Trimming and Margining – Principle of Operation Figure 8-2 below shows a Lattice Power Manager II device implementing trimming and margining functions for an analog DC-DC converter. Figure 8-2. Supplies are Margined by Changing the Resistor Connected to the Trim/FB Node On the top portion of Figure 8-2 is a DC-DC converter supplying power to its load. The output voltage is determined by the components used in its feedback circuitry. The Power Manager II device at the bottom measures the voltage using the on-chip ADC though differential sense inputs. The Power Manager II can increase or decrease the output voltage of the DC-DC converter by increasing or decreasing the voltage or current applied to the DC-DC converter’s feedback node, using its on-chip DAC. For some DC-DC converters, increasing the feedback node current or voltage reduces its output voltage. PWM Controller Inductor & Filters Switcher Feedback Any DC-DC Converter ispPAC-POWR1220AT8/ ispPAC-POWR6AT6 Load Differential Voltage Sense I 2 C 2 Result: Voltage Error <1% At Load! (-40° to +85° C) Set Point +/-1 VIN DAC ADCPower 2 You: A Guide to Power Supply Management and Control 8-4 Margining and Trimming A set point register in the Power Manager II holds the required voltage value at the load. Once every 580s the Power Manager II device measures the voltage at the load using its on-chip ADC. The digital output of the ADC is compared against the set-point register contents. If the load voltage is higher, the DAC contents are decremented, which in turn reduces the voltage applied to the feedback node of the DC-DC converter. If the load voltage is lower, the DAC contents are incremented, applying higher voltage to the node. This is called the closed loop trim mechanism. It is possible to break the closed loop trim and load the DAC register directly through the I2 C bus. This method is used to implement margining. An external microprocessor directly loads a pre-selected DAC value into the Power Manager II, which will result in changing the output voltage by, for example, ±5%. The microprocessor can also measure the output voltage of the DC-DC converter using the Power Manager II’s ADC, and tweak the output voltage up and down as needed to implement closed loop margining. In a circuit board, there typically are multiple types of supplies providing different supply voltages. These individual supplies require different current levels to be injected into their feedback nodes. This in turn requires a unique resistor network for each type of DC-DC converter to be connected between the Power Manager II and the DC-DC converter feedback node. The next section briefly describes the Power Manager II’s architecture blocks and then explains the details of designing a resistor network connected between the DC-DC converter feedback node and the Power Manager II DAC output. Power Manager II TrimCell Architecture The DAC in Figure 8-2 stores the DAC codes for nominal output voltage, as well as for margining up and down. For example, to support margining (for example ±5%) and trimming of a low voltage set-point (for example 1.2V 10mV), the three individual DAC values must be stored in different DAC registers. The Power Manager II device supports six registers for each DAC. The block that includes the DAC and its associated registers is called a TrimCell. Figure 8-3 is a TrimCell block diagram.Power 2 You: A Guide to Power Supply Management and Control Margining and Trimming Margining and Trimming 8-5 Figure 8-3. TrimCell Architecture in a Power Manager II Device Six DAC registers are divided into four hardware addressable groups called Voltage Profiles. Of these six DAC codes, four are stored in on-chip EEPROM memory. The two remaining registers are volatile. One of the volatile registers can be loaded directly via the I2 C interface. The second register is controlled by the closed loop trim circuit. Voltage Profiles 3, 2 and 1, when selected by either the external hardware pins or internally by the PLD, load the corresponding codes stored in the EEPROM memory into the DAC. With this feature one can margin each supply high or low using the on-chip PLD, or through the hardware pins of the Power Manager II device. While operating in these profiles, the Power Manager II is said to be operating in an open-loop; that is, the DAC register contents are static and are not adjusted during operation, depending on the actual DC-DC converter output voltage. To support the controlling of output voltage to a very high degree of accuracy (Set-point voltage ±10mV), the Profile 0 should be used. There are three modes of operation in Profile 0: 1. Open Loop operation with the DAC code stored in the E2 CMOS® configuration memory. Operation in this mode is similar to that of the profiles 1, 2 and 3. 2. Open Loop/ External Closed Loop operation – Load the I2 C DAC register via the I2 C bus. This mode of operation is used by an external microcontroller to fine tune the output voltage, depending on the DC-DC converter’s actual output voltage. This is called an external closed loop mode of operation. 3. Closed Loop Trim – This mode of operation is used to trim a given DC-DC converter output voltage accurately. Tight control of the output voltage is maintained by the on-chip closed loop control circuitry. Closed loop circuitry gets activated once every 580s. It can also be programmed to be activated at a slower rate: 1.15ms, 9.2ms or 18.5ms. When activated, the on-chip closed loop control circuitry measures the DC-DC converter output voltage and compares it to the value stored in the set point register. Depending on the DC-DC converter’s output voltage excursion, the closed loop circuitry increments or decrements the DAC contents in a way that counters the output voltage excursion Voltage Profile 2 Voltage Profile 1 Voltage Profile 0 From Closed Loop Trim Circuit Voltage Profile 0 Mode Select (E2CMOS) Common Voltage Profile Control DAC Register 3 (E2CMOS) Voltage Profile 3 DAC Register 2 (E2CMOS) DAC Register 1 (E2CMOS) DAC Register 0 (E2CMOS) DAC Register (I2C) Profile Mux 11 8 10 01 00 DAC TRIMx Closed Loop Trim Register Mode Mux 8 8 8 8 2 8 8 8Power 2 You: A Guide to Power Supply Management and Control 8-6 Margining and Trimming direction. The ispPAC-POWR1220AT8 device supports eight TrimCells in its TrimBlock, as shown in Figure 8-4. Power Manager II Integrates Multiple TrimCells The ispPAC-POWR1220AT8 device supports eight TrimCells in its TrimBlock, as shown in Figure 8-4. Each of the TrimCells can be programmed independently to control a DC-DC converter. The Voltage profile selection is common to all TrimCells and is controlled by either the hardware control pins (VPS [0:1]) or through the on-chip PLD. Figure 8-4. The ispPAC-POWR1220AT8 Device Provides Eight TrimCells in its Trim Block When the Voltage proPOWR file is set to, for example, 3 in Figure 8-4 shown above, the DC-DC1 converter outputs 0.95V (5% below the normal operating voltage of 1V), while the DC-DC 2 converter outputs 1.14V (5% below the 1.2V nominal), and so on. When the voltage profile is set to, for example, 1, the DC-DC1 converter outputs 1V+5%. The DC-DC2 converter outputs 1.2V + 5%. This method is used to implement margining. TrimCell #1 (Closed Loop) TrimCell #2 (I2 C Update) TrimCell #3 (I2 C Update) TrimCell #8 (Register 0) DC-DC 1 Trim-in VIN 0 123 1V (CLT) 1.05V 0.97V 0.95V DC-DC Output Voltage Controlled by Profiles DC-DC 2 DC-DC 3 Digital Closed Loop and I 2 C Interface Control ispPAC-POWR1220AT8 Margin/Trim Block Trim 1 Trim 2 Trim 3 Trim 8 Trim-in Trim-in R1* R2* R3* R8* *Indicates resistor network PLD Control Signals PLD_CLT_EN, PLD_VPS[0:1] Input From ADC Mux Read – 10-bit ADC Code VPS[0:1] VIN VIN DC-DC 8 Trim-in VIN 1.2V (I2 C) 1.26V 1.16V 1.14V 1.5V (I2 C) 1.57V 1.45V 1.42V 3.3V (EE) 3.46V 3.20V 3.13VPower 2 You: A Guide to Power Supply Management and Control Margining and Trimming Margining and Trimming 8-7 When VPS [0:1] = 0 the DC-DC 1 converter outputs 1V and the DC-DC2 converter outputs 1.2V. However, TrimCell 0 maintains the DC-DC converter output voltage using the on-chip closed loop control mechanism, while TrimCell1 uses an external microcontroller to maintain the voltage at 1.2V. Closed Loop Trim - Mode Operation of TrimCell Figure 8-5 shows the connection between the TrimCell and the DC-DC converter when configured to operate in closed loop trim mode. The resistor between the Trim pin and the DC-DC converter Trim_in pin converts the voltage applied by the DAC into a current added to the Trim summing node of the DCDC converter. The ADC is used to measure the DC-DC converter voltage. The three-state comparator compares the ADC measured value with the set-point and the output increments, decrements or holds the content of the closed loop trim register as is. Figure 8-5. The ispPAC-POWR1220AT8 Device Closed Loop Trimming Mechanism When the Power Manager II device is powered on, the DAC output voltage starts at the bi-polar zero value. The bipolar zero voltage is determined by its offset voltage setting 0.6V, 0.8V, 1V and 1.25V. This results in starting the DC-DC converter output voltage very close to its nominal value. Using this value, all supplies are sequenced. Once the supply sequencing is complete, the closed loop trimming process is activated. The closed loop trimming circuitry operates on each of the TrimCells in a cycle. The closed loop trimming cycle can be activated using a programmable timer and can be set to 580s, 1.15ms, 9.2ms or 18.5ms. The closed loop trim circuitry consists of the ADC, three state comparator, set point register, channel polarity controller, the control loop register increment/ decrement control and the DAC. During a trim cycle, the closed loop trim circuitry performs the following functions for each of the TrimCells: 1. Measures the voltage of the DC-DC converter differentially through the ADC. 2. Compares the output of the ADC with the set point register. If the polarity is set as positive, the following are the effects of the comparison: a. If the DC-DC converter voltage is higher than set point, decrement the contents of the closed loop trim register. Three-State Digital Compare (+1/0/-1) Setpoint (E2 CMOS) Channel Polarity (E2 CMOS) E 2 CMOS Registers TRIMx VMONx TRIMIN DC-DC Converter VOUT GND ispPAC-POWR1220AT8 DAC Register 3 DAC Register 2 Closed Loop Trim Register DAC TrimCell DAC Register 1 DAC Register 0 DAC Register I2 C Profile 0 Mode Control (E2 CMOS) Profile Control (Pins/ PLD) Update Rate Control ADC +/-1Power 2 You: A Guide to Power Supply Management and Control 8-8 Margining and Trimming b. If the DC-DC converter voltage value is less than the set point register value, the closed loop trim register contents are incremented. c. If the ADC value is the same as that of the set point register, maintain the closed loop trim register value. If the polarity set is negative, the incrementing and decrementing register in steps a. and b. above are reversed. Closed loop trimming ensures that the voltage at the load is accurate within ±10mV from the set-point value This error includes the maximum ADC measurement steady state error and the DAC quantization error. According to the datasheet, the maximum ADC error (including its gain, offset, INL and DNL across process, voltage and temperature) is 8mV. The error from the DAC is due to its step size. This error is calculated as follows: Usually the resistors between the DAC and the DC-DC converters are calculated such that the full scale (128) swing of DAC results in swinging the output voltage of the DC-DC converter by 5%. This means that each step of the DAC code results in an output voltage step of 5% / 128 ~ 0.05%. For a 3.3V supply, the voltage variation due to a single step of DAC code results in changing the output voltage by 3.3*0.05/100*128 = 130V (approximately). In effect the major error component is the ADC error. Errors due to DC-DC converter components, DC-DC converter accuracy, etc. are compensated for by the closed loop trim mechanism, which maintains the output voltage accurately. Closed Loop Trim and Closed Loop Margining Using a Microcontroller Figure 8-6 shows the configuration used for closed loop trimming with a microcontroller. Here the microcontroller measures the DC-DC converter output voltage periodically, using the on-chip ADC through the I 2 C bus. The microcontroller then algorithmically calculates the new DAC value depending on the DCDC converter voltage and loads the new DAC code through the I2 C interface. The microcontroller-based margining is implemented entirely through the I2 C bus and uses profile 0 in the Power Manager II. To implement closed loop margining, the microcontroller loads the starting DAC code into the DAC register via I2 C and waits for the ADC voltage to stabilize. Depending on the stabilized voltage value, the microcontroller increments or decrements the DAC code. This method enables setting and controlling the margined voltage accurately.Power 2 You: A Guide to Power Supply Management and Control Margining and Trimming Margining and Trimming 8-9 Figure 8-6. Closed Loop Trimming and Margining Using a Microcontroller Interfacing Power Manager II with a DC-DC converter Interfacing a DC-DC converter with the DAC requires that the DC-DC converter output voltage is at its nominal value when the DAC register value is at its bipolar-zero voltage in Profile 0. It also requires that the DAC maximum or minimum code results in swinging the DC-DC converter voltage to its margin voltage value through appropriate current injection into the feedback node. The resistor values also should take into consideration the type of feedback node arrangements used in DC-DC converters, their internal reference type (current/ voltage), and type of feedback. To map all types of DC-DC converter variables to the DAC output voltage swing, a number of resistor network topologies, shown in Figure 8-7 through Figure 8-11 are required. Figure 8-7 shows a typical resistor network between a Power Manager II device and a DC-DC converter. As discussed earlier, the ispPAC-POWR1220AT8 device can monitor and trim up to eight DC-DC converters individually. The trim circuit of the Power Manager interfaces to different types of DC-DC converters through a resistor network, as shown in Figure 8-7. The resistors R1 and , R2 and R3 determine the starting voltage of the DC-DC converter. This is equivalent to connecting a resistor to ground from the trim pin. The values of these resistors are selected such that the voltage at the node between R1 and R3 , is equal to the DAC voltage at power up. The values of these three resistors are calculated by the PAC-Designer software using the following inputs: 1. Type of DC-DC Converter. There are four types of DC-DC converters: a. Fixed voltage b. Output voltage programmable through a resistor to ground connected to its trim input c Output voltage programmable through a resistor to the output voltage terminal d. Output voltage is determined by two resistors connected from its feedback node output voltage terminal and to ground Microcontroller E 2 CMOS Registers I 2 C Bus TRIMx VMONx TRIMIN DC-DC Converter VOUT GND POWR1220AT8/POWR6AT6 DAC Register 3 DAC Register 2 Closed Loop Trim Register DAC Trim Cell DAC Register 1 DAC Register 0 DAC Register I2 C Profile 0 Mode Control (E2 CMOS) Profile Control (Pins/ PLD) ADCPower 2 You: A Guide to Power Supply Management and Control 8-10 Margining and Trimming 2. Nominal operating voltage 3. Margining voltage range in positive and negative directions Figure 8-7. Resistor Network Topology #1 Connecting a TrimCell to a DC-DC Converter Not all DC-DC converter types require the same resistor network of R1 , R2 and R3 as that shown in Figure 8-7. The other possible types of resistor networks generated by the PAC-Designer software are shown in Figure 8-8, Figure 8-9, Figure 8-10 and Figure 8-11. Figure 8-8. Resistor Network Topology #2 Figure 8-9. Resistor Network Topology #3 Figure 8-10. Resistor Network Topology #4 ispPAC-POWR1220AT8 DC-DC Converter Trim V OUT V OUT R3 R1 R2 VIN TrimCell #N DAC V= output voltage of DAC at bipolar zero ispPACPOWR1220AT8 DC-DC Converter Trim V OUT R3 R1 R2 DAC ispPACPOWR1220AT8 DC-DC Converter R1 R3 DAC R2 ispPACPOWR1220AT8 DC-DC Converter R1 R3 DAC R2 Trim V OUTPower 2 You: A Guide to Power Supply Management and Control Margining and Trimming Margining and Trimming 8-11 Figure 8-11. Resistor Network Topology #5 Designing Trimming and Margining Networks using PAC-Designer Software Determining the required resistor topology involves finding a solution for a number of nodal equations and an understanding of the error amplifier architecture of the DC-DC converter. In addition, the design can be iterated until the solution yields standard resistor values. The PAC-Designer software automates the process of determining the resistor topology while using standard resistors in the resistor network. Calculating the resistor values shown in Figure 8-7 through Figure 8-11 using the PAC-Designer software is a two-step process: 1. Create a DC-DC Converter Library using the DC-DC converter’s feedback and trim section characteristics – This uses a few parameters commonly specified in a DC-DC converter datasheet. 2. Associate a DC-DC converter to a TrimCell and calculate the resistors for a given output trim and margin voltage specification for that DC-DC converter. Creating a DC-DC Converter Library Entry 1. To create a DC-DC converter library entry, open the ispPAC-POWR1220AT8 design and click on the button ‘DC-DC’ as shown in Figure 8-12 to open the DC-DC Model Selection menu. Click the
