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Farnell PDF
Schroff Main Catalog - Farnell Element 14
Schroff-Main Catalog Octobre 2012 - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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Main Catalog
24th Edition | October 2012
Equipment Protection Solutions
04 Desk-top cases .
Overview . . . . . 0 Desk-top cases
Cabinets . . . . . . 1
Wall mounted
cases . . . . . . . . 2
Accessories for
cabinets and wall
mounted cases 3
Climate control 4
Desk-top cases 5
Subracks/
19" chassis . . . 6
Front panels,
plug-in units . . 7
Systems . . . . . . 8
Power supply
units . . . . . . . . . 9
Backplanes . . 10
Connectors, front
panel component
system . . . . . . 11
Appendix . . . . 12 Downloads und weitere wichtige Informationen finden Sie
im Internet unter www.schroff.biz
5.0 Main Catalogue
E 10/2012
Main Catalogue
PROLINE
Y
The universal case with 19" compatible
dimensions e.g. for CompactPCI and VME64x
applications
- Aluminium case
- Height 2 ... 7 U
- High EMC shielding
i
The robust case for 19" compatible or custom
electronics assemblies
- Aluminium case with aluminium frame front
- Height 2 ... 6 U
- High EMC shielding
361009005 (12304003 10005004 05802001 06803006 05809001)
Desk-top cases
Main Catalogue 5.1
E 10/2012
Main Catalogue
Accessories
b
Desk-top or portable case
Design alternative to propacPRO
- Front and rear frame in aluminium
- Aluminium case
- Height 2 ... 6 U
- For 19" components or individual electronics
assemblies
J
Case to house
19" subracks or 19" chassis
- Case with aluminium frame to
front and rear
- High stability
- Height 3 ... 12 U
- Identical front and rear
- Internal mounting up to 40 kg
- Protection class IP 20
36109006 (02004001 02202003 05806006 02992004 05806008)
Overview . . . . 5.0
Introduction . . 5.2
ServicePLUS . . 5.4
ratiopacPRO . . 5.6
propacPRO . . . 5.44
compacPRO . . 5.76
comptec . . . . . . 5.100
Accessories
Handles . . . . . . . . 5.108
Strap handles . . . 5.111
Tip-up carrying
handles . . . . . . . . 5.112
Folding handles 5.113
Tray handles . . . 5.114
Feet . . . . . . . . . . 5.115
ServicePLUS . . 5.4
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.2 Main Catalogue
E 10/2012
Desk-top cases – Introduction
IntroductionMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days Desk-top enclosures
Our desk-top cases are used to house PCBs (euroboards) or
individual components
The choice is yours:
ratiopacPRO, the universal case with 19" compatible
dimensions and high EMC shielding,
e.g. for CompactPCI and VME64x applications
propacPRO, the robust case with high EMC shielding for
19"-compatible or custom electronics assemblies
compacPRO, Desk-top or portable case for unshielded
applications
19" cases
Our comptec cases are comparable with small cabinets and are
used to house 19" components such as subracks, 19" fan trays
or 19" front panels
All desk-top enclosures have a very low weight owing to the
materials used and are also suitable for mobile use
Main CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
The most important user domains for desk-top enclosures are:
Fitting with euroboards in accordance with IEC 60297
Fitting with individual electrical or mechanical components,
e.g.on mounting plates
Main CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Practical technology without time-consuming assembly. The
modular product platform of these cases allows a wide range
of possible uses with only a small number of components.
The intelligent design of all components results in an
astonishingly quick and easy assembly of the components.
With our PRO product platform we offer you full compatibility
of all individual components and accessories, also with our
europacPRO subracks.
Standard desk-top enclosures can also be adapted easily and
with little effort for mobile applications.
Case types: Desk-top enclosure/19" case
01810002 02202004
Desk-top enclosure,
ratiopacPRO
19" case, comptec
Applications for desk-top enclosures
02004079 05809004 05809004
Example above: for euroboards, below: for individual installation
One product platform and extensive accessories
05806008 05806006
02005003 02005006
5.3
Desk-top cases – Introduction
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
IntroductionMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Supplied in space-saving packs. Simply unpack parts and screw
together - done.
Depending on the kit chosen the threaded insert, the perforated rail
or the EMC gasket is pre-assembled on the horizontal rail.
We offer you three forms of delivery:
Pre-assembled kit for use with 160 mm deep euroboards,
frame fitted, cladding parts and guide rails supplied loose.
Pre-assembled kit for individual configuration, frame
assembled, cladding parts supplied loose.
Ready assembled cases to your specifications. With our
ServicePLUS option you can order ready-assembled cases,
with drilled holes and cut-outs and individual front panels -
if necessary even by express service.
Main CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Guide rails form the interface between the mechanics of the
case and the electronics assembled (PCBs, plug-in units, frame
type plug-in units, drive unit modules, etc.).
Robust snap-in fixings on the plastic rails assure that the
components are held securely, even when exposed to
vibrations.
Guide rails can also be screwed on.
Main CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Our case product platforms offer standard solutions for
achieving electromagnetic compatibility (EMC) and to avoid
electrostatic interference (ESD)
Shielding on the front and rear of the case is effected by front
panels with EMC gaskets
To prevent electrostatic discharge when inserting PCBs, ESD
contacts are clipped into the guide rails. These provide a
conductive connection between board and case earth/ground
Test reports are available on our website www.schroff.biz for
download
Forms of delivery for desk-top enclosures
06104001
Flat pack delivery to save space
Guide rail
06108084
83 81 79 77 75 73 1
13579 11
EMC and ESD
06108081
Shielding
04503050
Position of the ESD clip
30
0
20
40
60
80
100
120
dB
400 800 1200 1600 2000
Mhz
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.4 Main Catalogue
E 10/2012
Desk-top cases – ServicePLUS
ServicePLUSMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
configuration Simple. Fast. For the product you want.
Components can be varied and combined
freely
Online configuration: www.schroff.co.uk/configuration
assembly Assembled by professionals. Double benefit!
Fitting of all mechanical, electrical and
electronic components by our specialists
Professional and reliable, without extra costs
Ready for despatch within 10 working days
modification Small changes. Large impact.
Custom drillings, cut-outs and special colours
for off-the-shelf products
CAD data are available for you to download and further modify
from our website www.schroff.biz
Ready for despatch within 10 working days
solution Simple. Fast. From one source.
Integration and custom developments Flowtherm simulation to calculate heat paths; verification in our
own climate lab
Special sizes, custom solutions
express When fast has to be faster.
Delivery time to customer's request ServicePLUS assembly ready for despatch within 10 working
days
ServicePLUS modification and ServicePLUS solution ready for
despatch within 15 working days
academy Knowledge. Sharing. Partnerships.
Knowledge transfer and partnership Seminars held centrally or at your site.
CAD drawings, test reports, user manuals
5.5
Desk-top cases – ServicePLUS
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Text
Application examples
01809001 01809003
Application: ratiopacPRO-air case in special colour,
shielded board cage, filter mat top and bottom
Application: ratiopacPRO-air case with processed
front and rear panels
02009001 02009003
Application: compacPRO case, modified Application: compacPRO case with fitted horizontal rail
with lip and hinged front panel
02009002 02009004
Application: compacPRO case with fitted horizontal rail
with lip and folding front panel
Application: compacPRO with tip-up carrying handle and
front panel (without visible screws)
02109001 05809005
Application: inpac case with hinged and modified
front and rear panels
Application: propacPRO, EMC case in special colour with
mounting plates for individual construction
Desk-top cases –Y Overview . . . . . 0
Cabinets . . . . . . 1
Wall mounted
cases . . . . . . . . 2
Accessories for
cabinets and wall
mounted cases 3
Climate control 4
Desk-top cases 5
Subracks/
19" chassis . . . 6
Front panels,
plug-in units . . 7
Systems . . . . . . 8
Power supply
units . . . . . . . . . 9
Backplanes . . 10
Connectors, front
panel component
system . . . . . . 11
Appendix . . . . 12 Downloads and further important information can be found
on the Internet under www.schroff.biz
5.6 Main Catalogue
E 10/2012
YMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
06800002
06801005
ratiopacPRO
Designed for insertion/extractor handles in accordance with
IEC 60297-3-102 and IEEE 1101.10 for CompactPCI and
VME64x applications
ratiopacPRO air
Designed for insertion/extractor handles in
accordance with IEC 60297-3-102 and
IEEE 1101.10 for CompactPCI and VME64x
applications; 1 U extra for ventilation
(1/2 U top, 1/2 U bottom)
Standards
Inner and outer dimensions in accordance with:
IEC 60297-3-101 / IEEE 1101.1
IEC 60297-3-102 / IEEE 1101.10/11
Type of protection IP20 in accordance with
IEC 60529
Earthing connections in accordance with:
DIN EN 50178 / VDE 0160
DIN EN 60950 / VDE 0805
DIN EN 61010-1 / VDE 0411 part 1
DIN EN 61010-1A2 / VDE 0411 part 1/A1
EMC testing in accordance with
VG 95373 part 15
06812001 06800015
Case with mounting plate Prepared for CompactPCI and
VME64x applications
Desk-top cases –Y
Main Catalogue 5.7
E 10/2012
YMain Catalogue
The universal case with 19" compatible dimensions
e.g. for CompactPCI, VME64x and other applications
Base level of shielding in basic versions upwards,
additional EMC shielding can be retrofitted
Symmetrical construction, identical front and rear
(identical board cage for ratiopacPRO and ratiopacPRO air)
Converts simply from desktop to 19" rack-mounted case and back
No visible screws; cladding parts removable without tools
ratiopacPRO
Case with cover strip, front handles or 19" brackets
(height 2 U ... 6 U)
Complete case with cover strip and pre-mounted components,
with basic shielding (height 3 U, 6 U), additional EMC shielding
retrofittable
Tower case (width 4 U)
ratiopacPRO air
ratiopacPRO air with additional 1 U height for ventilation
Case with cover strips, front handles or 19" brackets (height 4
U, 5 U, 7 U)
Complete case with cover strips and pre-mounted
components, with basic shielding (height 4 U, 7 U),
additional EMC shielding retrofittable
06800005
06800005
ServicePLUS from page 5.4
e.g. modifications (special colours or sizes)
e.g. custom solutions (cut-outs in top cover,
base plate or side panels)
e.g. assembly service from 1 piece
www.schroff.biz/ServicePLUS
30407004
Overview . . . . 5.6
ratiopacPRO
Complete cases . 5.8
Dimensions . . . . . 5.9
Cases . . . . . . . . . . 5.10
Tower cases . . . . 5.12
ratiopacPRO air
Cases . . . . . . . . . 5.14
Complete cases . 5.13
Dimensions . . . . . 5.16
Radial fan units . 5.17
EMC gasketing . . 5.18
Accessories
Front panels . . . . 5.21
Rear panels . . . . . 5.22
Feet . . . . . . . . . . . 5.23
Air filters . . . . . . . 5.23
GND/earthing kit 5.24
Front handles . . . 5.24
19" brackets . . . . 5.25
Cable holder. . . . 5.26
Compartment
seals. . . . . . . . . . . 5.26
Strap handles . . . 5.26
Tip-up carrying
handles . . . . . . . . 5.27
Assembly kit. . . . 5.28
Fitting position
of horizontal rails
. . . . . . . . . . . 5.29
Horizontal rails. . 5.31
Threaded
inserts,
perforated strips,
insulation strips . 5.35
Z-rails,
perforated rails. . 5.35
Divider plates . . . 5.36
Mounting plates . 5.37
Horizontal board
assembly . . . . . . 5.38
Combined
mounting . . . . . . 5.39
Guide rails and
ESD clips . . . . . . 5.40
ServicePLUS . . 5.4
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.8 Main Catalogue
E 10/2012
Desk-top cases –Y
YMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Desk-top enclosure with pre-configured components, in
accordance to IEC 60297-3-101; prepared for 19" components,
e.g. plug-in units and euroboards
Ventilation slit in base plate
Rear panel perforated
Delivery comprises (in kit form)
Order Information
Note
Dimension drawings and mounting depths see page 5.9
Components see page 5.18
Front handles and 19" mounting brackets from page 5.24
Guide rails from page 5.40
ratiopacPRO complete cases
06812003
01802050
01808055
01808051
3 U
01808052
6 U
ServicePLUS see page 5.4
12
11
15
10
15
11
6, 7, 9
5, 7, 9
4, 7, 8,16
2
3
1
“X”
“Y”
“Z”
4
9 9
7 7
7
16 8
5
6
“X” “Y” “Z”
D - 20
W - 21.4 D
W
7.5 H
A A- A
A
D - 20
W - 21.4 D
W
7.5
A A- A
A
H
Item Qty Description
without
EMC
with
EMC
1 2 2 Side panel, AI, 2 mm, passivated
2 2 2 Side plate, Al, 1 mm, visible surfaces RAL 9006
3 4 4 Cover strip, Al die-cast, RAL 7016, pre-fitted
only on EMC version
4 4 4 Horizontal rail, type H-LD, Al, visible surfaces
RAL 7016
5 2 2 Horizontal rail, centre (top/bottom), type H-ST, Al
6 1 1 Horizontal rail, centre (on 6 U only), type ST, Al
7 6/8 6/8 3 U/6 U: threaded inserts, St, pre-mounted,
for indirect backplane mounting with insulation
strips
8 – 4 Perforated strip, Al, 1 mm, pre-fitted
9 4 4 Insulation strip, PBT, UL 94 V-0
10 1 1 Rear panel, perforated, Al, 2.5 mm
11 2 2 Top cover and base plate, Al, 1 mm, internal
surfaces conductive, visible surfaces RAL 9006,
with GND/earthing connection,
base plate with honeycomb grid ventilation
12 4 4 Case foot with anti-slip protection, UL 94 V-0,
PC black
14 – 1 EMC support profile for side panel,
pre-mounted (kit)
15 – 4 EMC contact strip for cover plate,
pre-mounted (kit)
16 – 4 EMC contact strip front panel - horizontal rails
17 1 1 GND/earthing kit, assembly kit
Height H Width W Depth D Unshielded EMC
shielded
U HP mm Part no. Part no.
3 28 255.5 24572-001 24572-050
3 42 255.5 24572-002 24572-051
3 42 315.5 24572-003 24572-052
3 63 315.5 24572-004 24572-053
3 84 315.5 24572-005 24572-054
3 84 375.5 24572-006 24572-055
3 84 435.5 24572-007 24572-056
6 42 315.5 24572-015 24572-064
6 63 315.5 24572-016 24572-065
6 84 315.5 24572-017 24572-066
6 84 375.5 24572-018 24572-067
6 84 435.5 24572-019 24572-068
5.9
Desk-top cases –Y
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 11/2013
Text
Dimension drawings ratiopacPRO
rppr6637 RatiopacPRO with A - bezel; B - front handle; C - 19" mounting bracket; D - 19" mounting bracket with front handle
Dimensions table ratiopacPRO
Height Width Depth
H h w W w1 w2 w D d D1 d2
in U in mm in mm in HP in mm in mm in mm in mm Total depth
in mm
Useable depth
in mm
Plug-in depth
in mm
Board depth
in mm
2 88.10 67.90
28 164.42 177.62 198.12 142.82
255.5 235.5
175.5 160
42 235.54 248.74 269.24 213.94 235.5 220
63 342.42 355.42 375.92 320.62
315.5 295.5
175.5 160
84 448.90 462.10 482.60 427.30 235.5 220
3 132.55 112.35
28 164.42 177.62 198.12 142.82 295.5 280
42 235.54 248.74 269.24 213.94
375.5 355.5
175.5 160
63 342.42 355.42 375.92 320.62 235.5 220
84 448.90 462.10 482.60 427.30 295.5 280
4 177.00 156.80
28 164.42 177.62 198.12 142.82 355.5 340
42 235.54 248.74 269.24 213.94
435.5 415.5
175.5 160
63 342.42 355.42 375.92 320.62 235.5 220
84 448.90 462.10 482.60 427.30 295.5 280
5 221.45 201.25
28 164.42 177.62 198.12 142.82 355.5 340
42 235.54 248.74 269.24 213.94
495.5 475.5
175.5 160
63 342.42 355.42 375.92 320.62 235.5 220
84 448.90 462.10 482.60 427.30 295.5 280
6 265.90 245.70
28 164.42 177.62 198.12 142.82 355.5 340
42 235.54 248.74 269.24 213.94
63 342.42 355.42 375.92 320.62
84 448.90 462.10 482.60 427.30
Components mountable in 15 mm depth grid
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.10 Main Catalogue
E 11/2013
Desk-top cases –Y
YMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Cases for individual assembly with 19" standard components or
specific internal mounting, e.g. with mounting plate
Unshielded (EMC shielding retrofittable)
Symmetrical design, identical front and rear side
Four versions:
– Bezels
– Front handles
– 19" mounting brackets
– 19" mounting brackets with front handles
For board depth 160 mm, 220 mm, 280 mm, and 340 mm
(depending on case depth)
Delivery comprises (kit)
3a, 3b, 3c or 3d according to selection
Note
Order information, see following page
Order Information
RatiopacPRO case
01805050 01805051 01805052 01813051
3a: Bezel 3b: Front handle 3c: 19" mounting
bracket
3d: 19" mounting
bracket with front
handle
01813065
Drawing with front cover strip
ServicePLUS see page 5.4
12
11
11
4
2
3a (3b/3c/3d)
1
3
Item Qty Description
1 2 Side panel, AI, 2 mm, chromated
2 2 Side plate, Al, 1 mm, visible surfaces powder-coated,
RAL 9006
3 2 Rear trim, Al die-cast, powder-coated, RAL 7016
3a 2 Bezel, Al die-cast, powder-coated, RAL 7016
3b 2 Front handle, Al die-cast, powder-coated, RAL 7016
3c 2 19" mounting bracket, Al diecast, powder-coated,
RAL 7016
3d 2 19" mounting bracket with front handle, Al diecast,
powder-coated, RAL 7016
4 4 Horizontal rail, type H-LD, Al, visible surfaces powdercoated,
RAL 7016
11 2 Top cover and base plate, Al, 1 mm, inner sides
conductive, visible surfaces powder-coated, RAL 9006,
with GND/earthing connections, base plate with
honeycomb grid ventilation
12 4 Case foot with anti-slip protection, UL 94 V-0, PC black
13 1 Fixing materials kit
Accessories
Earthing kit CU wire, 1.5 mm2, PVC sleeve, green/yellow,
1 kit 24571-380
Al diecast foot with tip-up silver, 1 piece (SPQ 10) 10603-002
Plastic tip-up foot silver, similar to RAL 9006, PU
4 pieces 20603-001
Plastic tip-up foot anthracite, similar to RAL 7016,
4 pieces 20603-002
Stacking aid silver, similar to RAL 9006, PA, UL 94 V-0,
PU 4 pieces 20603-004
Stacking aid anthracite, similar to RAL 7016, PA,
UL 94 V-0, PU 4 pieces 20603-003
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.11
Desk-top cases –Y
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 11/2013
Note
Dimension drawings and mounting depths see page 5.9
Components see page 5.18
RatiopacPRO case
Width
W
Depth
D
Case height H
2 U
HP mm Part no. Part no. Part no. Part no. Part no.
Side panel subdivision
(1 U-3 U-1 U) (3 U-2 U)
Cover strips 28 255.5 24572-500 24571-002 24571-050 24572-117 24572-261 24571-098
28 315.5 24572-503 24571-005 24571-053 24572-120 24572-264 24571-101
42 255.5 24572-510 24571-014 24571-062 24572-129 24572-273 24571-110
42 315.5 24572-513 24571-017 24571-065 24572-132 24572-276 24571-113
42 255.5 24572-514 24571-018 24571-066 24572-133 24572-277 24571-114
63 255.5 24572-520 24571-026 24571-074 24572-141 24572-285 24571-122
63 315.5 24572-523 24571-029 24571-077 24572-144 24572-288 24571-125
63 375.5 24572-524 24571-030 24571-078 24572-145 24572-289 24571-126
84 255.5 24572-530 24571-038 24571-086 24572-153 24572-297 24571-134
84 315.5 24572-533 24571-041 24571-089 24572-156 24572-300 24571-137
84 375.5 24572-534 24571-042 24571-090 24572-157 24572-301 24571-138
84 435.5 24572-535 24571-043 24571-091 24572-158 24572-302 24571-139
RPPR6629 84 495.5 24572-536 24571-044 24571-092 24572-159 24572-303 24571-140
Front handles 28 255.5 – 24571-702 24571-750 24572-213 24572-357 24571-798
28 315.5 – 24571-705 24571-753 24572-216 24572-360 24571-801
42 255.5 – 24571-714 24571-762 24572-225 24572-369 24571-810
42 315.5 – 24571-717 24571-765 24572-228 24572-372 24571-813
42 375.5 – 24571-718 24571-766 24572-229 24572-373 24571-814
63 255.5 – 24571-726 24571-774 24572-237 24572-381 24571-822
63 315.5 – 24571-729 24571-777 24572-240 24572-384 24571-825
63 375.5 – 24571-730 24571-778 24572-241 24572-385 24571-826
84 255.5 – 24571-738 24571-786 24572-249 24572-393 24571-834
84 315.5 – 24571-741 24571-789 24572-252 24572-396 24571-837
84 375.5 – 24571-742 24571-790 24572-253 24572-397 24571-838
84 435.5 – 24571-743 24571-791 24572-254 24572-398 24571-839
01805050 84 495.5 – 24571-744 24571-792 24572-255 24572-399 24571-840
19" mounting brackets 84 255.5 24572-570 24571-438 24571-486 24572-201 24572-345 24571-534
84 315.5 24572-573 24571-441 24571-489 24572-204 24572-348 24571-537
84 375.5 24572-574 24571-442 24571-490 24572-205 24572-349 24571-538
84 435.5 24572-575 24571-443 24571-491 24572-206 24572-350 24571-539
01805052
84 495.5 24572-576 24571-444 24571-492 24572-207 24572-351 24571-540
19" mounting brackets
with front handles 84 255.5 24572-620 24572-630 24572-640 – – 24572-660
84 315.5 24572-623 24572-633 24572-643 – – 24572-663
84 375.5 24572-624 24572-634 24572-644 – – 24572-664
84 435.5 24572-625 24572-635 24572-645 – – 24572-665
01813051
84 495.5 24572-626 24572-636 24572-646 – – 24572-666
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.12 Main Catalogue
E 10/2012
Desk-top cases –Y
06802001
01802054
1) = open space between the horizontal rails
2) = max. mounting depth
Y
Symmetrical design, identical front and rear side
Mounting space 4 U, 84 HP, depth 475 mm
Case based on ratiopacPRO
Unshielded (EMC shielding retrofittable)
Delivery comprises (in kit form)
Order Information
Note
Components see page 5.18
ratiopacPRO tower with 4 U width
ServicePLUS see page 5.4
4
4
6
3
5 1
2
3
156,8 475.5 2)
177 495.5
1)
221,5
448.7
462.25
427.3
Item Qty Description
1 2 Base/top cover, Al, 2 mm, passivated
2 4 Horizontal rail, type H-LD, Al, visible surface powdercoated,
RAL 7016
3 4 Cover, Al die-cast, RAL 7016
4 2 Lateral cover plate, Al, 1 mm, with GND/earthing
connection, visible surfaces powder-coated, internal
surface conductive, RAL 9006
5 1 Top cover plate, Al, 1 mm, visible surface powder-coated,
RAL 9006
6 2 Case foot with anti-slip protection, Al, powder-coated,
RAL 7016
7 1 Assembly kit
Width Part no.
U
4 24571-395
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.13
Desk-top cases –Yair
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
airY The case has 2 x 1/2 U clearance for ventilation
Case with cover strip; with pre-mounted components for
euroboards and backplane with insulation strip; no visible
screws
Symmetrical design, identical front and rear honeycomb grid
ventilation in top cover and base plate
Available in two versions:
– unshielded (EMC shielding retrofittable)
– with EMC shielding fitted
Delivery comprises (in kit form)
Order Information
Note
Dimension drawings and mounting depths see page 5.16
Components see page 5.18
Front handles and 19" mounting brackets from page 5.24
Guide rails from page 5.40
ratiopacPRO air complete cases
06811001
01802052
01808055
01808053
3 U
01808054
6 U
ServicePLUS see page 5.4
12
13
11
15
“X”
“Y”
“Z”
13
10
6, 7, 9
5, 7, 9
4, 7, 8, 16
2
3
1
15
14
17
11
4
9 9
7 7
7
16 8
5
6
“X” “Y” “Z”
D
w
7.5
h
H
A A - A
A
D
w
7.5
A A - A
A
h
H
Item Qty Description
without
EMC
with
EMC
1 2 2 Side panel, AI, 2 mm, passivated
2 2 2 Side plate, Al, 1 mm, visible surface RAL 9006
3 4 4 Cover, die-cast zinc, RAL 7016, pre-mounted on
EMC version only
4 4 4 Horizontal rail, type H-LD, Al,
visible surface RAL 7016
5 2 2 Horizontal rail, centre (top/bottom), type H-ST, Al
6 1 1 Horizontal rail, centre (on 6 U only), type ST, Al
7 6/8 6/8 4 U/7 U: threaded inserts, St, pre-mounted,
for indirect backplane mounting with insulation strips
8 – 4 Perforated strip, pre-mounted
9 4 4 Insulation strip, PBT, UL 94 V-0
10 1 1 Rear panel, Al, 2.5 mm
11 2 2 Top cover and base plate with honeycomb grid
ventilation, Al, 1 mm, internal surface conductive,
visible surface RAL 9006, with GND/earthing
connection
12 4 4 Case foot with anti-slip protection, UL 94 V-0,
PC, black
13 2 2 Air filter
14 – 1 EMC support profile for side panel, fitted (kit)
15 – 4 EMC contact strip for cover plate, pre-mounted (kit)
16 – 4 EMC contact strip front panel - horizontal rails
17 1 1 Compartment seal, PE foam, self-adhesive,
temperature range -20 °C ... +85 °C
18 1 1 GND/earthing kit, assembly kit
Case
height H
PCB height h Width
w
Depth
D
Unshielded EMC
shielded
U U HP mm Part no. Part no.
4 3 28 255.5 24572-025 24572-074
4 3 42 255.5 24572-026 24572-075
4 3 42 315.5 24572-027 24572-076
4 3 63 315.5 24572-028 24572-077
4 3 84 315.5 24572-029 24572-078
4 3 84 375.5 24572-030 24572-079
4 3 84 435.5 24572-031 24572-080
7 6 42 315.5 24572-040 24572-088
7 6 63 315.5 24572-041 24572-089
7 6 84 315.5 24572-042 24572-090
7 6 84 375.5 24572-043 24572-091
7 6 84 435.5 24572-044 24572-092
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.14 Main Catalogue
E 11/2013
Desk-top cases –Yair
airY The case has 2 x 1/2 U clearances for ventilation beneath and
above the board cage
Cases for individual assembly with 19" standard components or
specific internal mounting, e.g. with mounting plate
Unshielded (EMC shielding retrofittable)
Symmetrical design, identical front and rear side
For board depth 160 mm, 220 mm, 280 mm, and 340 mm
(depending on case depth)
Online download of 3D CAD data
Four versions:
– Bezels
– Front handles
– 19" mounting brackets
– With 19" mounting brackets and front handles
Delivery comprises (in kit form)
3a, 3b, 3c or 3d according to selection
Note
Order information see following page
Order Information
RatiopacPRO air case
06801005
01805055 01805056 01805057 01813057
3a: Bezel 3b: Front handle 3c: 19" mounting
bracket
3d: 19" mounting
bracket with front
handle
01813066
Drawing with front cover strip
ServicePLUS see page 5.4
12
13
11
11
13
4
2
3a (3b/3c/3d)
3
1
Item Qty Description
1 2 Side panel, AI, 2 mm, chromated
2 2 Side plate, Al, 1 mm, visible surfaces powder-coated,
RAL 9006
3 2 Rear trim, Al die-cast, powder-coated, RAL 7016
3a 2 Bezel, Al die-cast, powder-coated, RAL 7016
3b 2 Front handle, Al die-cast, powder-coated, RAL 7016
3c 2 19" mounting angle, Al die-cast, powder-coated,
RAL 7016
3d 2 19" mounting bracket with front handle, Al diecast,
powder-coated, RAL 7016
4 4 Horizontal rail, type H-LD, Al, visible surfaces powdercoated,
RAL 7016
11 2 1 Top cover and base plate, Al, 1 mm, internal surfaces
conductive,visible surfaces powder-coated, RAL 9006,
with
GND/earthing connection, top cover and base plate with
ventilation comb
12 4 Case foot with anti-slip protection, UL 94 V-0, PC black
13 2 Air filters
14 1 Fixing materials kit
Accessories
Earthing kit CU wire, 1.5 mm2, PVC sleeve, green/yellow,
1 kit 24571-380
Al diecast foot with tip-up silver, 1 piece (SPQ 10) 10603-002
Plastic tip-up foot silver, similar to RAL 9006, PU
4 pieces 20603-001
Plastic tip-up foot anthracite, similar to RAL 7016,
4 pieces 20603-002
Stacking aid silver, similar to RAL 9006, PA, UL 94 V-0,
PU 4 pieces 20603-004
Stacking aid anthracite, similar to RAL 7016, PA,
UL 94 V-0, PU 4 pieces 20603-003
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.15
Desk-top cases –Yair
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 11/2013
Note
Dimension drawings and mounting depths see page 5.16
Components see page 5.18
RatiopacPRO air case
Width W Depth D Case height H
4 U 5 U 7 U
PCB height h
HP mm Part no. Part no. Part no.
Bezels 28 255.5 24571-146 24571-194 24571-242
28 315.5 24571-149 24571-197 24571-245
42 255.5 24571-158 24571-206 24571-254
42 315.5 24571-161 24571-209 24571-257
42 375.5 24571-162 24571-210 24571-258
63 255.5 24571-170 24571-218 24571-266
63 315.5 24571-173 24571-221 24571-269
63 375.5 24571-174 24571-222 24571-270
63 435.5 24571-175 24571-223 24571-271
84 255.5 24571-182 24571-230 24571-278
84 315.5 24571-185 24571-233 24571-281
84 375.5 24571-186 24571-234 24571-282
84 435.5 24571-187 24571-235 24571-283
01805055 84 495.5 24571-188 24571-236 24571-284
Front handles 28 255.5 24571-846 24571-894 24571-942
28 315.5 24571-849 24571-897 24571-945
42 255.5 24571-858 24571-906 24571-954
42 315.5 24571-861 24571-909 24571-957
42 375.5 24571-862 24571-910 24571-958
42 435.5 24571-863 24571-911 24571-959
63 315.5 24571-873 24571-921 24571-969
63 375.5 24571-874 24571-922 24571-970
63 435.5 24571-875 24571-923 24571-971
84 255.5 24571-882 24571-930 24571-978
84 315.5 24571-885 24571-933 24571-981
84 375.5 24571-886 24571-934 24571-982
84 435.5 24571-887 24571-935 24571-983
01805056 84 495.5 24571-888 24571-936 24571-984
19" mounting brackets 84 255.5 24571-582 24571-630 24571-678
84 315.5 24571-585 24571-633 24571-681
84 375.5 24571-586 24571-634 24571-682
84 435.5 24571-587 24571-635 24571-683
01805057 84 495.5 24571-588 24571-636 24571-684
With 19" mounting brackets
and front handles
84 255.5 24572-670 – 24572-690
84 315.5 24572-673 – 24572-693
84 375.5 24572-674 – 24572-694
84 435.5 24572-675 – 24572-695
01805057
84 495.5 24572-676 – 24572-696
3
1
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.16 Main Catalogue
E 11/2013
Desk-top cases –Yair
Text
Text
RatiopacPRO air dimension drawings
01805058
RatiopacPRO air with A - bezel; B - front handle; C - 19" mounting bracket; D - 19" mounting bracket with front handle
Dimensions table RatiopacPRO air
Height Width Depth
H H W W1 W2 w D d D1 d2
in U in mm in mm in
HP
in mm in mm in mm in mm Total depth
in mm
Usable depth
in mm
Plug-in depth
in mm
Board depth
in mm
4 177.00 112.35
28 164.42 177.62 198.12 142.82
255.5 235.5
175 160
42 235.54 248.74 269.24 213.94 235 220
63 342.42 355.42 375.92 320.62
315.5 295.5
175 160
84 448.90 462.10 482.60 427.30 235 220
5 221.45 156.80
42 235.54 248.74 269.24 213.94 295 280
63 342.42 355.42 375.92 320.62
375.5 355.5
175 160
84 448.90 462.10 482.60 427.30 235 220
7 310.35 245.70
42 235.54 248.74 269.24 213.94 295 280
63 342.42 355.42 375.92 320.62 355 340
84 448.90 462.10 482.60 427.30
435.5 415.5
175 160
235 220
295 280
355 340
495.5 475.5
175 160
235 220
295 280
355 340
Components mountable in 15 mm depth grid
5.17
Desk-top cases –Yair
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
12309050
12309051
Depth D: 129.8 / 189.9 mm for 160 mm / 220 mm euroboards
Main Catalogue
Only 1/2 U height
Ball-bearing radial fans
Fan holder in 4 widths and 2 depths
Air capacity 36 m³/h (free blowing) per fan
Air exhaust via perforation in cover plate
No mechanical modification to case necessary
Simple mounting
No restriction to rear mounting space
Delivery comprises (Kit)
Order Information
Note
Further configurations available on request
Fans with tacho signal available on request
Radial fan unit for ratiopacPRO air
D
8
26,5
70
W
Item Qty Description
1 1 Fan support, Al, 1.5 mm, with crimp sockets for
mounting the fans
2 1-3 Radial fan, ball bearing, 12 VDC;
airflow volume (50 Hz) 36 m³/h, free blowing;
power consumption 6.7 W;
connecting cable 300 mm, without plug (AWG 26);
noise level in dB (A): 47.0;
max. static pressure in Pa: 190;
max. ambient temperature: 60 °C;
fan housing and rotor: UL 94 V-0
3 1 Compartment seal, PE foam, UL 94, self-adhesive,
temperature range -20 °C ... +85 °C
4 1 Terminal clamp, UL 90 V-0
5 1 Assembly kit
Width Width Number of
fans
Part no.
for PCB depth
HP mm 160 mm 220 mm
28 146.87 1 24572-404 24572-408
42 218.00 1 24572-405 24572-409
63 324.67 2 24572-406 24572-410
84 431.35 3 24572-407 24572-411
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
3
4
1
2
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.18 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
rppr6639
/ -airY For vertical EMC shielding between sub-assemblies and side
panel
Scope of delivery sufficient for one case
Delivery comprises (kit)
Order Information
RPPR6640
/ -airY For horizontal EMC shielding between side panels and cover
plates
Scope of delivery sufficient for one case
Delivery comprises (kit)
Order Information
EMC sealing front/rear panel to side panel
1
2
Item Qty Description
1 4 EMC support profile, Al extrusion
2 2 EMC sealing (textile), core: foam,
sleeve: textile cladding with CuNi coating
3 1 Assembly kit
For case height Part no.
U
2, 3-air 24571-334
3, 4-air 24571-331
4, 5-air 24571-332
6, 7-air 24571-333
5, 6-air 24571-335
EMC sealing side panel to cover plate
Item Qty Description
1 4 Contact strip, stainless steel
Depth Part no.
mm
255 24571-338
315 24571-339
375 24571-340
435 24571-341
495 24571-342
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.19
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
rppr6739
Main Catalogue
The contact strip is clipped onto the horizontal rail and sets up
the contact to front panel or rear panel
Can be used for rear horizontal rails (H-VT, L-VT) and all front
horizontal rails
Delivery comprises
Order Information
/ -airY For shielding of two horizontal rails located directly above each
other with vertical division of the mounting height
Delivery comprises
Order Information
EMC sealing front/rear panel to horizontal
rail
Item Qty Description
1 10/100 Stainless steel EMC gasket
Width Width Qty/PU Part no.
HP mm
28 131.78 10 24560-229
42 202.9 10 24560-231
63 304.8 10 24560-233
84 416.3 10 24560-235
84 416.3 100 24560-236
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
EMC sealing horizontal rail to horizontal rail
BPA46548 BZA45877
aza45937
Assembly tool
Item Qty Description
1 1 Cover strip, Al, 1 mm
2 2 Contact spring, St, stainless
Length Part no.
HP
20 24562-520
28 24562-528
40 24562-540
42 24562-542
63 24562-563
84 24562-584
Assembly tool for EMC sealing,
St, stainless (horizontal rails),1 piece 24560-271
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.20 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
/ -airYMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
No screws required for fixing
Special horizontal rails cover the edges of the front panel
(top and bottom) and prevent bowing of the front panel
Delivery comprises (Kit)
Order Information
Note
To obtain a shielded case, all EMC sealings must be fitted (front
panel/rear panel - side panel; side panel - cover plate; front
panel/rear panel - horizontal rail; horizontal rail - horizontal rail)
EMC sealing see from page 5.18
EMC front/rear panel, slotted, shielded
01811055
01811056
Front panel/horizontal rail
H
W
Item Qty Description
1 1 Full-width front panel, Al, 2.5 mm,
front: anodised, rear: colour passivated
2 2 Horizontal rail, front; special for this front panel
3 4 EMC support profile
4 2 Contact strip horizontal rail - front panel
5 3 EMC textile gasket
6 1 Fixing material kit, user manual
For case
height
Height H For case
width
Width W Part no.
U mm HP mm
2, 3-air 84.0 28 141.9 24572-599
2, 3-air 84.0 42 213.2 24572-600
2, 3-air 84.0 63 319.7 24572-601
2, 3-air 84.0 84 426.4 24572-602
3, 4-air 128.4 28 141.9 24572-603
3, 4-air 128.4 42 213.2 24572-604
3, 4-air 128.4 63 319.7 24572-605
3, 4-air 128.4 84 426.4 24572-606
4, 5-air 172.9 28 141.9 24572-607
4, 5-air 172.9 42 213.2 24572-608
4, 5-air 172.9 63 319.7 24572-609
4, 5-air 172.9 84 426.4 24572-610
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.21
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
06801502
/ -airY Front panels can also be used as rear panels
No screws required for fixing
Inserted between side panel and castings such as trim,
19" mounting bracket or handle
Delivery comprises
Order Information
Note
Screw-fixed front panels see chapter Front panels, page 7.4
Full-width front panel, slotted, unshielded
Item Qty Description
1 1 Front panel, Al, 2.5 mm,
front: anodised, rear: colour passivated
For case
height
Height H For case
width
Width W Part no.
U mm HP mm
2, 3-air 84 28 141.9 34571-617
2, 3-air 84 42 213.2 34571-618
2, 3-air 84 63 319.7 34571-619
2, 3-air 84 84 426.4 34571-620
3, 4-air 128.4 28 141.9 34571-605
3, 4-air 128.4 42 213.2 34571-606
3, 4-air 128.4 63 319.7 34571-607
3, 4-air 128.4 84 426.4 34571-608
4, 5-air 172.9 28 141.9 34571-609
4, 5-air 172.9 42 213.2 34571-610
4, 5-air 172.9 63 319.7 34571-611
4, 5-air 172.9 84 426.4 34571-612
5, 6-air 217.3 28 141.9 34571-621
5, 6-air 217.3 42 213.2 34571-622
5, 6-air 217.3 63 319.7 34571-623
5, 6-air 217.3 84 426.4 34571-624
6, 7-air 261.8 28 141.9 34571-613
6, 7-air 261.8 42 213.2 34571-614
6, 7-air 261.8 63 319.7 34571-615
6, 7-air 261.8 84 426.4 34571-616
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.22 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
01802055
Shieldable
01804050
Unshielded
/ -airY Two versions:
unshielded, Al, 2.5 mm;
shieldable, Al extrusion (textile EMC seal, retrofittable)
Mounting on horizontal rails (top and bottom)
Delivery comprises
Order Information
Please order textile EMC seals separately
Assembly parts see page Chapter 7, Front panels
Rear/front panels without perforation see Chapter 7,
Front panels
Rear panels with fan available on request
04602054
Front panels Delivery comprises
Order Information
Rear panels with ventilation slots
7,45 7,45
B
ø 5,9 x 3,3
W
Z
W - 2,58
3,2
7,2
25
2,5 3 3
H 3,7
3,7
2,5
Item Qty Description
1 1 Rear panel, Al, 2.5 mm, front: anodised, rear: iridescent
green chromated; unshielded or shieldable with
EMC seal (textile)
Height H Width W B unshielded shieldable
U mm HP mm mm Part no. Part no.
2, 3-air 84 28 141.9 – 30849-007 20848-679
2, 3-air 84 42 213 101.6 30849-014 20848-680
2, 3-air 84 63 319.7 157.5 30849-015 20848-681
2, 3-air 84 84 426.4 208.3 30849-016 20848-682
3, 4-air 128.4 28 141.9 – 30849-008 20848-633
3, 4-air 128.4 42 213 101.6 30849-021 20848-634
3, 4-air 128.4 63 319.7 157.5 30849-022 20848-635
3, 4-air 128.4 84 426.4 208.3 30849-023 20848-636
4, 5-air 172.9 28 141.9 – 30849-009 20848-656
4, 5-air 172.9 42 213 101.6 30849-028 20848-657
4, 5-air 172.9 63 319.7 157.5 30849-029 20848-658
4, 5-air 172.9 84 426.4 208.3 30849-030 20848-659
5, 6-air 217.3 28 141.9 – 30849-011 20848-744
5, 6-air 217.3 42 213 101.6 30849-171 20848-745
5, 6-air 217.3 63 319.7 157.5 30849-172 20848-746
5, 6-air 217.3 84 426.4 208.3 30849-173 20848-747
6, 7-air 261.8 28 141.9 – 30849-010 20848-640
6, 7-air 261.8 42 213 101.6 30849-035 20848-641
6, 7-air 261.8 63 319.7 157.5 30849-036 20848-642
6, 7-air 261.8 84 426.4 208.3 30849-037 20848-643
Textile EMC seals
Item Qty Description
1 10/100 Textile EMC seal, core: foam,
sleeve: textile cladding with CuNi coating
Height Height Qty/PU Part no.
U mm pieces
2, 3-air 52 10 21101-857
3, 4-air 97 100 21101-854
3, 4-air 97 10 21101-853
4, 5-air 142 10 21101-858
5, 6-air 187 10 21101-978
6, 7-air 232 100 21101-856
6, 7-air 232 10 21101-855
5.23
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
01802075
Tip-up foot
01802076
Stacking aid/design element
/ -airY Can be used instead of standard feet
Carrying capacity: 25 kg per foot
Mounting holes in bottom of casing
Delivery comprises ((kit))
Order Information
Note
Tip-up feet are required to mount the stacking aid
rppr6658
/ -airY Retrofit mounting without reworking and tools
Filter replacement without opening the case, IP protection
retained
Delivery comprises (kit)
Order Information
To optimise the air supply, tip-up feet must be fitted to the case,
see page 5.23
Tip-up feet and stacking aid/design element
Item Qty Description
1 4 Foot, PA, UL 94 V-0
2 4 Anti-slip protection, TPE
3 2 Tip-up device, PA, UL 94 V-0
4 1 Assembly kit
Description Part no.
Tip-up foot, silver, similar to RAL 9006 20603-001
Tip-up foot, anthracite, similar to RAL 7016 20603-002
Stacking aid/design element silver, similar to RAL 9006,
PA, UL 94 V-0, PU 4 pieces 20603-004
Stacking aid/design element anthracite, similar to
RAL 7016, PA, UL 94 V-0, PU 4 pieces 20603-003
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Air filters for ratiopacPRO air
Item Qty Description
1 1 Filter holder, Al, 1 mm, powder-coated, RAL 9006
2 1 Filter mat, synthetic fibre
3 1 Self-adhesive fixings
For case width Air filter Replacement
filter 1 piece
HP Part no. Part no.
28 24571-325 64571-033
42 24571-326 64571-034
63 24571-327 64571-035
84 24571-328 64571-036
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.24 Main Catalogue
E 11/2013
Desk-top cases –Y/ -air
aza43284
/ -airY Forms the GND/earthing connections between side panels,
base plate, top cover and rear panel
Protective GND/earthing connections in accordance with:
– DIN EN 50178/VDE 0160
– DIN EN 60950/VDE 0805
– DIN EN 61010-1/VDE 0411 part 1
– DIN EN 61010-1A2/VDE 0411 part 1/A1
VDE tested
Order Information
Earthing kit
Description Part no.
GND/earthing kit, Cu wire 1.5 mm2, PVC sleeve,
green/yellow 24571-380
5.25
Desk-top cases –Y
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 11/2013
Y
For conversion of cases with cover strip, 19" mounting bracket
or 19" mounting bracket with front handle
Delivery comprises
Order Information
Y
For conversion of cases with cover strip, front handle or 19"
mounting bracket with front handle
Delivery comprises
Order Information
YMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
For conversion of cases with cover strip, front handle or 19"
mounting bracket
Delivery comprises
Order Information
Front handles for retrofitting
RPPR6651
Item Qty Description
1 2 Front handle, Al die-cast, powder-coated, RAL 7016
Front handle for Part no.
RatiopacPRO 3 U 24571-301
RatiopacPRO 4 U 24571-302
RatiopacPRO 5 U 24571-993
RatiopacPRO 6 U 24571-303
RatiopacPRO air 3/4 U 24571-304
RatiopacPRO air 4/5 U 24571-305
RatiopacPRO air 6/7 U 24571-306
19" mounting brackets for retrofitting
RPPR6652
Qty Description
2 19" mounting bracket, Al diecast, powder-coated, RAL 7016
19" mounting angle Part no.
RatiopacPRO 2 U 24571-994
RatiopacPRO 3 U 24571-295
RatiopacPRO 4 U 24571-296
RatiopacPRO 5 U 24571-992
RatiopacPRO 6 U 24571-297
RatiopacPRO air 4 U 24571-298
RatiopacPRO air 5 U 24571-299
RatiopacPRO air 7 U 24571-300
19" mounting bracket with front handle for
conversion
01813056
Qty Description
2 19" mounting bracket with front handle, Al diecast, powdercoated,
RAL 7016
19" mounting angle Part no.
RatiopacPRO 2 U 24572-700
RatiopacPRO 3 U 24572-701
RatiopacPRO 4 U 24572-702
RatiopacPRO 6 U 24572-704
RatiopacPRO air 4 U 24572-705
RatiopacPRO air 7 U 24572-707
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.26 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Delivery comprises
Order Information
/ -airY The air baffle (item 1) closes the space (1/2 U) between the rear
horizontal rail and base plate
Delivery comprises (in kit form)
Order Information
Note
Fan rear panel available on request
Radial fan unit see page 5.17
06801515
/ -airY Retrofittable without mechanical modifications to the case
Static load-carrying capacity 20 kg per pair
Delivery comprises (kit)
Order Information
Cable holder
02908053 02908052
19 9
17
14
26,5
46
20,2
Ø 3 Ø 4,4
Ø4,4 Ø 3
Item Qty Description
1 2 Cable bracket, ABS, UL V-94 0, RAL 7016,
detent for cables between 8 mm and 12 mm
2 1 Drilling template, two drilled holes each per bracket are
needed in rear panel
3 1 Assembly kit
Description Part no.
Cable holder 24575-800
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Air baffles for ratiopacPRO air
01805059
Item Qty Description
1 1 Compartment seal, PE foam, UL 94 HF 1 + HF 2,
self-adhesive, temperature range: -40 °C ... +85 °C
For case width Length Part no.
HP mm
42 218.4 20833-351
63 325.1 20833-352
84 431.8 20833-353
Strap handles
Item Qty Description
1 1 Handle, steel spring, plastic-sheathed (flexible plastic),
RAL 7016
2 1 Side plate, Al, visible surfaces powder-coated, RAL 9006
3 2 Adaptor, Al die-cast
4 1 Assembly kit
For case depth For case height
3 U, 4 U air
For case height4
HE, 5 Uair
mm Part no. Part no.
315 24571-308 24571-314
375 24571-309 24571-315
435 24571-310 24571-316
5.27
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 03/2013
/ -airY Retrofittable without mechanical modifications to the case
Adjustable in 30° increments
Static load-carrying capacity 30 kg
Delivery comprises (kit)
Order Information
Note
Cannot be used in conjunction with front handles
Assembly kit is required for tip-up carrying handle, please order
separately
Tip-up carrying handles
06803006
RPA43897
For case height For case width A B C D
U HP mm mm mm mm
3, 4, 4-air, 5-air 42 283,4 279,4 247,4 115
3, 4, 4-air, 5-air 63 390,1 386,1 354,1 195
3, 4, 4-air, 5-air 84 496,8 492,8 460,8 195
rpa43898
Item Qty Description
1 1 Carrying bar, Al extrusion, powder coated, RAL 9006
2 1 Handle shell, ABS, UL 94 V-0, RAL 7016
3 2 Tip-up protection, ABS, UL 94 V-0, RAL 7016
4 2 Notch device, Al die-cast
5 2 Cover cap, ABS, UL 94 V-0, RAL 7016
For case
height
For case
width
For case
depth
Tip-up
carrying
handle
Assembly
kit
U HP mm Part no. Part no.
3, 4-air 42 255 24571-320 24571-352
3, 4-air 42 315 24571-320 24571-353
3, 4-air 42 375 24571-320 24571-354
3, 4-air 42 435 24571-320 24571-355
3, 4-air 42 495 24571-320 24571-356
3, 4-air 63 255 24571-321 24571-352
3, 4-air 63 315 24571-321 24571-353
3, 4-air 63 375 24571-321 24571-354
3, 4-air 63 435 24571-321 24571-355
3, 4-air 63 495 24571-321 24571-356
3, 4-air 84 255 24571-322 24571-352
3, 4-air 84 315 24571-322 24571-353
3, 4-air 84 375 24571-322 24571-354
3, 4-air 84 435 24571-322 24571-355
3, 4-air 84 495 24571-322 24571-356
4, 5-air 42 255 24571-320 24571-359
4, 5-air 42 315 24571-320 24571-360
4, 5-air 42 375 24571-320 24571-361
4, 5-air 42 435 24571-320 24571-362
4, 5-air 42 495 24571-320 24571-363
4, 5-air 63 255 24571-321 24571-359
4, 5-air 63 315 24571-321 24571-360
4, 5-air 63 375 24571-321 24571-361
4, 5-air 63 435 24571-321 24571-362
4, 5-air 63 495 24571-321 24571-363
4, 5-air 84 255 24571-322 24571-359
4, 5-air 84 315 24571-322 24571-360
4, 5-air 84 375 24571-322 24571-361
4, 5-air 84 435 24571-322 24571-362
4, 5-air 84 495 24571-322 24571-363
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.28 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
/ -airY Order Information
Main CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days Order Information
Order Information
Torx panhead screws
Description Application Material Dimension Qty/PU Part no.
Countersunk
screw with Torx
For horizontal rail to side panel, with GND/earthing
function
St,
zinc-plated M4 х 14 100 24571-371
AZA45923
Countersunk
screw with Torx
For horizontal rail to side panel, if guide rail is
bolted onto slot 1
St,
zinc-plated M4 х 10 100 24571-372
Nut
Description Application Material Dimension Qty/PU Part no.
AZA45921
Square nut For fixing: parts to side panels, support profiles,
mounting plates
St,
zinc-plated M4 100 24560-140
Assembly tools
Description Application Dimension Qty/PU Part no.
Torx screwdriver
T8 1 64560-026
AZA45925
T20 1 64560-027
aza45938
Assembly tool for
horizontal rails
Exclusively to fix stainless steel
EMC gaskets in horizontal rails – 1 24560-271
aza45937
Assembly tool for front
panels
For mounting stainless steel
EMC contact strips on front
panels with lateral slot
– 1 24560-270
5.29
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Text
Mounting position ratiopacPRO
horizontal rails/central rails
front rear front rear
2 U 3 U
01805060 01802057
4 U (3 U + 1 U)
01802058
5 U (1 U + 3 U + 1 U) 5 U (3 U + 2 U)
01805061 01805062
6 U 6 U (2 x 3 U)
01802059 01802060
Horizontal rails can be bolted on in 15 mm depth grid 01808050
H-LD H-LD
H-LD H-LD
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
100
H-LD H-LD
H-LD H-LD
100
H-KD / H-LD / L-KD
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
H-LD H-LD
H-LD H-LD
H-LD H-LD
H-LD H-LD
100
H-KD / H-LD / L-KD
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
H-LD H-LD
H-LD H-LD
233,35
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
ST / VT / MZ
H-LD H-LD
H-LD H-LD
L-ST / L-VT / L-MZ
H-ST / H-VT / H-MZ
100 100
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
H-KD / H-LD / L-KD
H-LD H-LD
H-LD H-LD
H-LD H-ST L-ST ST VT MZ
H-KD H-VT L-VT
L-KD H-MZ L-MZ
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.30 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Text
Mounting position ratiopacPRO air
horizontal rails/central rails
front rear front rear
4-air U (1/2 U + 3 U + 1/2 U)
01802061
5-air U (1/2 U + 3 U + 1U +1/2 U)
01802062
7-air U (1/2 U + 6 U + 1/2 U) 7-air U (1/2 U + 3 U + 3U 1/2 U)
01802063 01802064
Horizontal rails can be bolted on in 15 mm depth grid 01808050
100
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
H-LD H-LD
H-LD H-LD
H-KD / H-LD / L-KD
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
100
H-LD H-LD
H-LD H-LD
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
L-ST / L-VT / L-MZ
H-ST / H-VT / H-MZ
ST / VT / MZ
233,35
H-LD H-LD
H-LD H-LD
100 100
H-ST / H-VT / H-MZ
L-ST / L-VT / L-MZ
H-KD / H-LD / L-KD
H-LD H-LD
H-LD H-LD
H-LD H-ST L-ST ST VT MZ
H-KD H-VT L-VT
L-KD H-MZ L-MZ
5.31
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Front horizontal rails
With long lip for insertion/extraction of CompactPCI
and VME64x boards
"heavy" "heavy"
Type H-KD Type H-LD
short lip long lip
bza44980 06197008 06197009
Al extrusion, anodised finish, contact surface conducting, with
printed HP markings
Al extrusion, anodised finish, contact surface conducting, with
printed HP markings
Usable length Length 1 piece (SPQ 10)1) 1 piece (SPQ 10)1)
HP mm
28 147.32 34560-228 34560-328
42 218.44 34560-242 34560-342
63 325.12 34560-263 34560-363
84 431.80 34560-284 34560-384
M4 × 10, St, zinc-plated,
necessary if guide rail is
screwed to slot 1, PU 100 pieces
24571-372 24571-372
Threaded inserts see page 5.35 5.35
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
"light": loading capacity up to approx. 7.5 kg; "heavy": loading capacity > 7.5 kg
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.32 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Main Catalogue
Order Information
Rear horizontal rails
For indirect backplane fixing
with insulation strip
For direct backplane fixing For direct fixing of connectors to
EN 60603-2 (DIN 41612)
04400001 04400002 04400003
"heavy" "heavy" "heavy"
Type H-ST Type H-VT Type H-MZ
standard long lip with Z-rail
06105074 06197011 06197013 06197015
Al extrusion, anodised finish, contact
surface conducting, with printed HP
markings
Al extrusion, anodised finish, contact
surface conducting, with printed HP
markings
Al extrusion, anodised finish, contact
surface conducting, with printed HP
markings
Usable length Length 1 piece (SPQ 10)1) 1 piece (SPQ 10)1) 1 piece (SPQ 10)1)
HP mm
28 147.32 34560-528 34560-728 34560-928
42 218.44 34560-542 34560-742 34560-942
63 325.12 34560-563 34560-763 34560-963
84 431.80 34560-584 34560-784 34560-984
Torx panhead screw, 4 x 10 24571-372 24571-372 24571-372
Perforated rail for connector
mounting with insulation strip
see page
5.35 – –
Z-rail for connector mounting
without insulation strip see page 5.35 – –
Insulation strips see page 5.35 – –
Threaded inserts see page 5.35 5.35 5.35
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
"light": loading capacity up to approx. 7.5 kg; "heavy": loading capacity > 7.5 kg
5.33
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Order Information
Horizontal rails rear, centre
For indirect mounting of
backplanes via insulation strip
For direct backplane mounting For direct fixing of connectors to
EN 60603-2 (DIN 41612)
04400001 04400002 04400003
Type ST Type VT Type MZ
06108090 06197016 06197017 06197018
Al extrusion, finish anodised,
conductive contact surface;
horizontal rail type AB (AB = support)
is required to fix the 80 mm rear I/O boards;
without marking
Al extrusion, finish anodised,
conductive contact surface;
horizontal rail type AB (AB = support)
is required to fix the 80 mm rear I/O boards;
without marking
Al extrusion, finish anodised,
conductive contact surface;
horizontal rail type AB (AB = support)
is required to fix the 80 mm rear I/O boards;
without marking
Usable length Length 1 piece (SPQ 10)1) 1 piece (SPQ 10)1) 1 piece (SPQ 10)1)
HP mm
28 147.32 34561-028 34561-128 34561-228
42 218.44 34561-042 34561-142 34561-242
63 325.12 34561-063 34561-163 34561-263
84 431.80 34561-084 34561-184 34561-284
Torx panhead screw, 4 x 10 24571-372 24571-372 24571-372
Insulation strips see page 5.35 – –
Threaded inserts see page 5.35 5.35 5.35
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.34 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Main Catalogue
Order Information
Note
All horizontal rails without print
1000 mm version without M4 thread in end
Horizontal rails (type AB) for rear I/O guide rails
For CompactPCI in rear I/O area
06108009
Type AB
06108069 06197009
Al extrusion, finish anodised,
conductive contact surface;
horizontal rail type AB (AB = support)
is required to fix the 80 mm rear I/O boards;
without marking
Usable length Length 1 piece (SPQ 10)1)
HP mm
20 106.68 34561-520
28 147.32 34561-528
40 208.28 34561-540
42 218.44 34561-542
63 325.12 34561-563
84 431.80 34561-584
– 1000 34561-501
Screw, M4 x 14, PU 100 pieces, for fastening horizontal rail
to side panel 24560-130
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
"light": loading capacity up to approx. 7.5 kg; "heavy": loading capacity > 7.5 kg
H - KD
H - KD
H - ST AB
H - ST AB
12,75 15 12,75
9,75 3
5.35
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Threaded inserts, perforated strips, insulation strips
Threaded insert Perforated strip Insulation strip
M2.5 M3 (item 1)
06103056 BZA45853 BZ6749
Required for fixing the front panel to the horizontal rail; St,
zinc-plated; use collar screw 12.3 mm, see page
6.64
For centring shielded plug-in units,
Al, 1 mm, please order fixing grub screw
separately
For insulated mounting of backplane;
PBT UL 94 V-0, grey
Usable length Length Length Length
HP mm 1 piece
(SPQ 10)1)
1 piece
(SPQ 10)1)
mm 1 piece (SPQ 10)1) mm PU 10 pieces2)
28 146.82 34561-328 – 147.12 30845-197 144.20 24560-828
42 217.94 34561-342 – 218.24 30845-211 210.40 24560-842
63 324.62 34561-363 – 324.92 30845-232 316.88 24560-863
84 431.30 34561-384 34561-484 431.60 30845-253 428.64 24560-884
5
2
5,08
Accessories
Grub screw M2.5 x 8, PU
100 pieces 21100-276 – – –
Grub screw M2.5 x 9, PU
100 pieces – – 21101-359 –
Grub screw M3 x 8, PU
100 pieces – 21100-646 – –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least
the SPQ quantity or a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Z-rails, perforated rails
Z-rail for connectors Perforated rail
DIN EN 60603-2, DIN 41612
item 1
31-pin, DIN 41617 EN 606032, DIN 41612
item 1
BZA45849 BZA45850 BZA45848
06708063 06708051
For connector mounting with ST
horizontal rails, please order
threaded insert and screw
separately
For connector mounting with ST
horizontal rails, please order
threaded insert and screw
separately
For connector mounting with VT
horizontal rails, please order
threaded insert and screw
separately Usable length Length
HP mm 1 piece 1 piece PU 4 pieces
28 142.24 30822-033 – 20822-049
42 213.36 30822-047 – 20822-050
60 304.80 30822-065 30819-783 20822-047
84 426.70 30822-089 30819-808 20822-048
Torx panhead screw, to fix connector to
perforated rail,, M2.5 × 7, PU 100 piecesItem 3 24560-147 24560-147 24560-147
Torx panhead screw, to fix perforated rail to
horizontal rail, M2.5 × 10, PU 100 pieces Item 2 24560-148 24560-148 24560-148
172,5
172,5
175,5
2
1
3
3,0
9,75
12,75
2
1
3
12,75
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.36 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Order Information
Divider plates
Divider plates
Mounting position for
stainless steel EMC gasket
Mounting position for
textile EMC gasket
front rear front rear
bpa45911 06105078
bpa45912
Stainless steel, 1 mm, is mounted by clipping onto horizontal rail, space
requirement on component side 2 mm; mounting direction varies with
shielding design (EMC stainless steel or textile gasket); retrofitting the divider
plate in an already-assembled subrack/case will first require dismantling of
the horizontal rails; where front panels are unshielded, both mounting
directions are possible
Height Depth A B H
U mm mm mm mm 1 piece
3 160 158.3 135.0 113.5 34562-761
3 220 218.3 195.0 113.5 34562-762
6 160 158.3 135.0 246.9 34562-763
6 220 218.3 195.0 246.9 34562-764
5.37
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Note
Please order fixing material for assembly of mounting plate
separately
A guide rail can be mounted on the first and last slot position
4.4" and "reinforced" guide rails cannot be used
Mounting plates
Mounting plate Assembly strip for
partial widths
bpa45875 bpa46557
06812002
Al, 1.5 mm; for mounting over partial
width, please order assembly strips
separately
St, 2 mm, zinc-plated; is bolted from
front to rear onto the horizontal rails;
to fix mounting plates
Width Board lengths
HP mm mm 1 piece 1 piece
28 146.88 160 34562-745 30840-021
28 146.88 220 34562-749 30840-033
28 146.88 280 34562-753 30840-045
28 146.88 340 34562-757 30840-057
42 217.99 160 34562-746 30840-021
42 217.99 220 34562-750 30840-033
42 217.99 280 34562-754 30840-045
42 217.99 340 34562-758 30840-057
63 324.67 160 34562-747 30840-021
63 324.67 220 34562-751 30840-033
63 324.67 280 34562-755 30840-045
63 324.67 340 34562-759 30840-057
84 431.35 160 34562-748 30840-021
84 431.35 220 34562-752 30840-033
84 431.35 280 34562-756 30840-045
84 431.35 340 34562-760 30840-057
Assembly kit for mounting plate
PU 1 kit (Torx countersunk screw M4 x 5, St, zincplated,
12 pieces; screw M4 x 6, St, zinc-plated,
10 pieces; M4 square nut, St, zinc-plated,
10 pieces)
24560-184 –
Assembly kit for assembly strips of mounting
plate
Torx screw
M2.5 × 5, St, zinc-plated, PU 100 pieces
– 24560-146
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.38 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Order Information
Note
Please order front frame separately
Horizontal board installation
Horizontal board installation
Board cage Front frame for EMC
shielding
Front frame, unshielded
06102073 bpa45913 bza43061
bpa45914
Struts die-cast zinc;
horizontal rails front and rear;
threaded insert, St, zinc-plated;
fixing material kit;
for horizontal mounting of
double-height euroboards in
3 or 4 U high subracks/cases;
54 TE space required; please
order front frame for EMC
shielding separately
2 horizontal covers,
AI, 2.5 mm, front anodised,
rear iridescent green chromated;
2 vertical trims, Al extrusion,
clear passivated;
stainless steel EMC gasket;
front frame forms the contact
between subrack and the subassemblies
Al, 2.5 mm, clear anodised;
front frame with cut-out,
clear internal width w = 266.35 mm
Height Usable
height h
HP
Other dimensions and
options
U Horizontal rail,
front
Horizontal rail,
rear
PU 1 kit PU 1 kit 1 piece
3 20 24564-117 24564-109 34564-108
3 20 24564-118 24564-109 34564-109
4 28 24564-217 24564-209 34564-208
Assembly tool, for mounting the
EMC gasket (stainless steel) – 24560-270 –
* For direct backplane mounting
273.98 = 54TE
h
H
273,98=54TE
w
5.39
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Subdivision of the 6 U assembly area into:
– 2 x 3 U
– 1 x 6 U
Designed to accept Euroboards (100 mm high) and double
Euroboards (233.35 mm high)
Note
Please order EMC gasketing kit for horizontal rails separately,
see page 5.19
Please order perforated strips for horizontal rails separately, see
page 5.35
Please order rear centre horizontal rail separately, see page
5.33
Combined mountings (6 U and 2 x 3 U one above the other)
Combined mounting Alternative front panels for
combined mounting
Splitting extrusion
Horizontal and vertical
subdivision
(incl. front panel for
stainless steel EMC gasket)
Unshielded front
panel, 6 U, 2 HP
item 6
Front panel for
textile EMC gasket,
6 U, 2 HP
item 6
For combined
mounting
Item 2
bpa46549 bpa46549 bpa46549 bza45857
bza42182
Item 1: 2 front horizontal rails (H-KD),
Al extrusion, anodised;
item 2: 2 rear horizontal rails (AB),
Al extrusion, anodised;
item 3: threaded insert, St, zincplated;
item 4: Zn die-cast support member;
item 6: front panel 2 HP, 6 U,
shielded; with EMC stainless steel
gasket (84:0 without items 4, 6)
Al, 2.5 mm,
front anodised,
rear iridescent green
chromated
Al, 2.5 mm, U-profile
with notch, 6 U, 2 HP
6 U, die-cast zinc;
splitting extrusion is
inserted in the
grid holes of the
horizontal rail;
the splitting extrusion
can be bolted
Width pitch T1:T2
HP PU 1 kit 1 (SPQ 5) 1 piece (SPQ 5)1) 1 piece
20:62 24562-420
30847-472 30849-140 64560-010
40:42 24562-440
42:40 24562-442
63:19 24562-463
84:0 24562-484
Countersunk screw with Torx
M4 × 14, zinc-plated, PU 100 pieces
fixing splitting extrusion/horizontal rail
– – – 24560-145
Panhead screw
M2.5 × 10, St, zinc-plated, PU 100 pieces
fixing horizontal rail/splitting extrusion
– – – 24560-179
Pozidrive/slotted collar screw
M2.5 x 12.3, St, nickel-plated, PU 100 pieces – 21101-101 21101-101 –
Pozidrive/slotted collar screw
M2.5, black, zinc-plated, PU 100 pieces – 21101-102 21101-102 –
Washer, 2.7 x 5 x 1, plastic PA 6, PU 100 pieces – 21101-121 21101-121 –
Textile gasket, core: foam,
sleeve: textile cladding with CuNi coating,
UL 94 V-0, PU 10 pieces
– – 21101-855 –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
4
4
6
1,3
1,3
2
2
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.40 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Main Catalogue
Order Information
Guide rails for plug-in units and modules, one-piece,
groove width 2 mm and 2.5 mm
Assembly
- can be clipped into Al extruded
horizontal rails
- can be clipped into 1.5 mm thick
plates
Storage temperature
from -40 °C ... 130 °C
For plug-in units and frame type plug-in units
Standard With DIN connector fixing as standard
06101001 06101501
Up to 220 mm length, PBT, UL 94 V-0; from 280 mm length,
multi-piece, end piece PBT, UL 94 V-0,
central section Al extrusion
PBT, UL 94 V-0, red,
connector is clipped directly onto the guide rails;
for euroboards 100 x 160 mm or 100 x 220 mm only
Board
lengths
Groove
width
Colour
mm mm mm PU 10 pieces2) 1 pair (SPQ 10)1)
70 2 red – –
70 2 grey – –
160 2 red 24560-351 64560-074
220 2 red 24560-353 64560-075
280 2 red 24560-379 –
340 2 red 24560-380 –
160 2.5 red – –
220 2.5 red – –
Accessories
Retention screw,
PU 100 pieces 24560-141
ESD clip, PU 50 pieces 24560-255
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Description of accessories see from page 6.41
5.41
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Order Information
Guide rails type "accessories", one-piece,
groove width 2 mm and 2.5 mm
Assembly
- can be clipped into horizontal rails
in Al extrusion
- can be clipped into 1.5 mm thick
plate
Storage temperature
from -40 °C ... +130 °C
Guide rail type
"Accessories" "Accessories" strengthened For heavy modules,
Al extrusion, silver,
robust version
06102002 bza46554 06102005
Up to 220 mm length, PBT, UL 94 V-0;
> 280 mm length, multi-piece,
end piece PBT, UL 94V-0,
middle section Al extrusion
PBT UL 94V-0, red;
support beam of guide rails
adds to strengthening
Al extrusion; is screwed to horizontal rail
"heavy" with retention screws
Board
lengths
Groove
width
Colour
mm mm mm PU 10 pieces2) 1 piece (SPQ 50)1) 1 piece (SPQ 10)1)
100 2 red – – –
160 2 red 24560-373 64560-076 –
160 2 grey – – 34562-881
220 2 red 24560-374 64560-078 –
220 2 grey – – 34562-882
280 2 red/silver 24560-375 64560-080 34562-883
340 2 red/silver 24560-376 – 34562-884
400 2 red/silver – – 34562-885
160 2.5 silver – – 34564-881
220 2.5 silver – – 34564-882
280 2.5 silver – – 34564-883
340 2.5 silver – – 34564-884
400 2.5 silver – – 34564-885
Accessories
Retention screw,
PU 100 pieces 24560-141 24560-141 24560-157
ESD clip, PU 50 pieces 24560-255 –
Board locking, red,
PU 10 pieces 24560-377 –
Board handle, red,
PU 10 piecesdescription 24560-378 –
Identification strips for board
handle, red, PU 1 sheet =
438 pieces
60817-228 –
Coding see page 6.41 –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity
(SPQ); please order at least the SPQ quantity or a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Description of accessories see from page 6.41
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.42 Main Catalogue
E 10/2012
Desk-top cases –Y/ -air
Main Catalogue
Order Information
Note
Reinforcement for plastic profiles (PVC) > 280 mm depth
available on request
Guide rails for CompactPCI, VME64x with coding,
4.4" PCBs, groove width 2 mm and 2.5 mm
Assembly
- can be clipped into Al extruded
horizontal rails
- can be clipped into1.5 mm thick
plates
Storage temperature
from -40 °C ... 130 °C
For CompactPCI, VME64x with coding For 4.4" PCBs
In accordance with IEEE 1101.10
and IEC 60297-3-103
Offset 0.1" for power supply units in
accordance with IEEE 1101.10 and
IEC 60297-3-103
06106001 06106002 06104009
One-piece for groove width 2 mm, PBT,
UL 94 V-0;
multi-piece at groove width 2,5 mm,
end-piece PBT, UL 94 V-0,
center piece Al profile
PBT, UL 94 V-0,
for installation of power supplies in
CompactPCI systems or
plug-in units with SMD placement
One-piece, PBT, UL 94 V-0;
for 4.4" PCBs or drive units
Board
lengths
Groove
width
Colour PU 10 pieces2) PU 10 pieces2) PU 10 pieces
mm mm mm
70 2 red 24560-355 – –
70 2 grey 24560-360 – –
160 2 red 24560-356 – 24560-361
160 2 grey 24560-358 – –
160 2 green – 24560-359 –
220 2 red – – 24560-362
220 2 grey – – –
220 2 green – – –
160 2.5 red – – –
220 2.5 red 24561-330 – –
220 2.5 grey 24561-340 – –
280 2.5 red 24561-331 – –
280 2.5 grey 24561-341 – –
340 2.5 red 24561-332 – –
340 2.5 grey 24561-342 – –
Accessories
ESD clip, PU 50 pieces 24560-255 – –
ESD clips, for alignment pin,
PU 50 pieces 24560-256 24560-256 –
Retention screw, PU 100 pieces 24560-141 24560-141 24560-158
Coding peg, PU 100 pieces 20817-501 20817-501 –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Description of accessories see from page 6.41
5.43
Desk-top cases –Y/ -air
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Order Information
Note
Air baffle for 280 mm deep and for 80 mm rear I/O boards
available on request
Air baffle for slots
Air baffle Air baffle with front panel
without front panel front panel with lateral
groove for stainless steel
EMC gasket
U front panel
for textile EMC gasket
06108085 06108087 06108088
06101507
Al, 1 mm, incl. assembly kit;
prevents an air short circuit in
unoccupied slot positions;
is pushed into the groove
of the guide rails
Air baffle, Al, 1 mm;
front panel, Al, 2.5 mm,
front anodised, rear conductive;
EMC gasket (stainless steel);
fixing material kit prevents an air
short- circuit where slots are
unoccupied;
is pushed into the groove
of the guide rails
Air deflector, Al, 1 mm,
front panel, Al extrusion, 2.5 mm,
front anodised, rear conductive;
EMC gasket (textile);
fixing material kit prevents an air
short-circuit where slots are
unoccupied;
is pushed into the groove
of the guide rails
Depth Width Height
mm HP U 1 piece 1 piece 1 piece
160 4 3 34562-823 20848-712 20848-728
160 4 6 34562-826 20848-720 20848-736
160 8 3 34562-833 20848-714 20848-730
160 8 6 34562-836 20848-722 20848-738
160 12 3 34562-843 20848-716 20848-732
160 12 6 34562-846 20848-724 20848-740
220 4 3 34562-824 20848-713 20848-729
220 4 6 34562-827 20848-721 20848-736
220 8 3 34562-834 20848-715 20848-731
220 8 6 34562-837 20848-723 20848-739
220 12 3 34562-844 20848-717 20848-733
220 12 6 34562-847 20848-725 20848-741
Assembly tool
for EMC gasket (stainless steel),
1 piece – 24560-270 –
Desk-top cases –i Overview . . . . . 0
Cabinets . . . . . . 1
Wall mounted
cases . . . . . . . . 2
Accessories for
cabinets and wall
mounted cases 3
Climate control 4
Desk-top cases 5
Subracks/
19" chassis . . . 6
Front panels,
plug-in units . . 7
Systems . . . . . . 8
Power supply
units . . . . . . . . . 9
Backplanes . . 10
Connectors, front
panel component
system . . . . . . 11
Appendix . . . . 12 Downloads and further important information can be found
on the Internet under www.schroff.biz
5.44 Main Catalogue
E 10/2012
iMain Catalogue
05809001
05806052 05806050 05806055 05806056
Easy access provided by
removable cladding parts
Extremely robust
one-piece die-cast frame
Non-sensitive,
scratch-resistant finish
through powder coating
Low weight
05806054 05806053 05806051 noa44075
Wide accessory
programme with acrylic
glass front hoods,
carrying handles, ...
Assembly possibility
for euroboards and
backplanes
EMC version VDE-compliant
GND/earthing
Standards
Internal dimensions in accordance with
IEC 60297-3-101
Ingress protection IP 20 in accordance with
IEC 60529
EMC test in accordance with VG 95373 part 15
Protective GND/earth connections in accordance
with:
DIN EN 50178 / VDE 0160
DIN EN 60950 / VDE 0805
DIN EN 61010-1 / VDE 0411 part 1
DIN EN 61010-1A2 / VDE 0411 part 1/A1
Desk-top cases –i
Main Catalogue 5.45
E 10/2012
iMain Catalogue Aluminium case for 19" components to IEC 60297-3-100
or individual electronics assemblies
Front frame and side panels in aluminium
Extensive accessories, matched to portable applications
Basic level shielding from basic versions up,
extended EMC shielding retrofittable
Design alternative to compacPRO
Desktop cases
Complete case (pre-assembled)
– Prepared for 19" components to IEC 60297 for installation
of euroboards
– Basic level shielding from basic versions up, extended
EMC shielding retrofittable
– Height 3 U, 6 U
Cases
– Pre-assembled cases as basis for individual components
or 19" components (IEC 60297)
– Basic level shielding from basic versions up, extended
EMC shielding retrofittable
– Height: 2 U, 3 U, 4 U, 6 U
– 3 U and 4 U cases prepared for tip-up carrying handle
05809003 05806003
Accessories
05809002
ServicePLUS from page 5.4
e.g. modifications (special colours, special depths,
cut-outs in top cover, base plate or side panels)
e.g. assembly service from 1 piece
www.schroff.biz/ServicePLUS
30407004
Overview . . . . 5.44
propacPRO
Complete cases
3, 6 U,
unshielded/
shielded . . . . . . . 5.46
Cases 2, 3 U . . . . 5.50
Cases 4, 6 U . . . . 5.51
Cases for tip-up
carrying handle
3, 4 U. . . . . . . . . . 5.52
Dimensions . . . . . 5.53
EMC shielding . . 5.55
Accessories
Front panels . . . . 5.54
Rear panels . . . . . 5.55
Design elements 5.58
Lateral covers . . 5.59
Handles . . . . . . . . 5.60
Air filters . . . . . . . 5.61
Hoods . . . . . . . . . 5.62
Mounting plates . 5.64
GND/earthing kit 5.65
Cable holder . . . 5.65
Mounting
position
horizontal/
central rails . . . . 5.66
Horizontal rails . 5.67
Threaded inserts 5.68
Z-rails,
perforated rails . 5.69
Combined
mounting . . . . . . 5.70
Horizontal board
assembly . . . . . . 5.71
Tip-up feet . . . . . 5.72
Guide rails and
ESD clips . . . . . . 5.73
Divider plates . . . 5.75
Air flow barrier . . 5.75
ServicePLUS . . 5.4
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.46 Main Catalogue
E 11/2013
Desk-top enclosure –i
ServicePLUS see page 5.4
iMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Desk-top case with pre-configured components, in accordance
with IEC 60297-3-101; prepared for 19" components such as
plug-in units and euroboards
Ventilation slots in base plate
Rear panel with vent slots
Delivery comprises (Items 1-7, 9 and 10 fitted)
Complete case,
EMC shielded
05809004
3 U
05806106
Maximale Einbautiefe = D - 45
(Distanz: Frontplatte - Rückwand)
8
7
5
6
12
11
13
14
10 b
3
4
10 a
15
9
1
9
2
Item Qty Description
3 U 6 U
1 1 1 Frame, Al die-cast, powder-coated, RAL 7016
2 2 4 Side panel, Al extrusion, powder-coated, RAL 9006,
with EMC side panel gasketing
3 1 1 Cover plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006,
with GND/earthing tag
4 1 1 Base plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006, with GND/
earthing tag, base plate with 4 rows of ventilation slots
5 2 2 End piece for rear, ABS, RAL 7016, UL 94 V-0;
can be used as a foot when case is used in vertical
position
6 - 2 Adaptor bracket (only at 6 U)
7 - 2 Cover trim for side panel, Al extrusion,
powder-coated, RAL 9006
8 4 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0 (20603-002)
9 2 2 Lateral trim, Al extrusion, visible surface painted,
RAL 7016 with EMC sealing (textile)
10a 2 2 Horizontal rail, Al extrusion, with threaded insert, St,
M2.5; perforated strip, Al, 1 mm, EMC contact strip
between front panel - horizontal rail - cover plate
10b 2 2 Horizontal rail, Al extrusion, with threaded insert,
St, M2.5; EMC contact strip between rear panel -
horizontal rail - cover plate
11 2 2 Centre horizontal rail top/bottom, Al extrusion,
with threaded insert, St, M2.5 and insulation strip,
PBT, UL 94 V-0
(for indirect backplane mounting); enclosed loose
12 - 1 Centre horizontal rail, Al extrusion, anodised,
conductive surfaces, with two threaded inserts,
St, M2.5 and two insulation strips, PBT, UL 94 V-0
13 1 1 Rear panel with perforation, Al, 2.5 mm, anodised,
with EMC sealing (textile) affixed
14 2 2 EMC support profile rear, Al extrusion,
EMC sealing (textile) affixed
15 10/
20
10/
20
Guide rail for 160 mm board length, PBT, UL 94 V-0,
28/42 HP 10 pieces,
63/84 HP 20 pieces
16 1 1 GND/earthing kit
17 1 1 Assembly kit
5.47
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 11/2013
Main Catalogue Order Information
Note
Dimension drawings of side panel see from page 5.53
Complete cases, EMC shielded
05809051
05806060
3 U
05806062
6 U
155,5
130,0
112,3
289,0
262,8
245,7
W2
W1
121,95
150,9
D
32,5
15 Ø 4,6
4
7,2
121,95
265,9
15 Ø 4,6
4
7,2
121,95
284,3
D
32,5
Usable width Width W1 Depth D Height Part no.
W2 W2 W1 D
HP mm mm mm U
28 147.3 185.9 266 3 24576-101
28 147.3 185.9 326 3 24576-102
42 218.4 257 266 3 24576-103
42 218.4 257 326 3 24576-104
42 218.4 257 386 3 24576-105
63 325.1 363.7 266 3 24576-106
63 325.1 363.7 326 3 24576-107
63 325.1 363.7 386 3 24576-108
84 431.8 470.3 266 3 24576-109
84 431.8 470.3 326 3 24576-110
84 431.8 470.3 386 3 24576-111
84 431.8 470.3 446 3 24576-112
84 431.8 470.3 506 3 24576-113
84 431.8 470.3 326 6 24576-121
84 431.8 470.3 446 6 24576-122
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.48 Main Catalogue
E 11/2013
Desk-top enclosure –i
ServicePLUS see page 5.4
Main Catalogue
Desk-top case with pre-configured components, in accordance
with IEC 60297-3-101; prepared for 19" components such as
plug-in units and euroboards
Ventilation slots in base plate
Rear panel perforated
Delivery comprises (Items 1-7, 9 and 10 fitted)
Complete cases,
unshielded
05809004
3 U
05806105
Maximum mounting depth = D - 45
(Distance: front panel - rear panel)
7
5
6
13
12
14
1
9
2
11
3
4
10
15
9
8
Item Qty Description
3 U 6 U
1 1 1 Frame, Al die-cast, powder-coated, RAL 7016
2 2 4 Side panel, Al extrusion, powder-coated, RAL 9006
3 1 1 Cover plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006, with
GND/earthing tag
4 1 1 Base plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006, with GND/
earthing tag, base plate with 4 rows of ventilation slots
5 2 2 End piece for rear, ABS, RAL 7016, UL 94 V-0;
can be used as a foot for use in vertical position
6 - 2 Adaptor bracket (only at 6 U)
7 - 2 Cover trim for side panel, Al extrusion,
powder-coated, RAL 9006
8 4 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0 (20603-002)
9 2 2 Lateral trim, Al extrusion, visible surface painted,
RAL 7016 with EMC sealing (textile)
10 2 2 Horizontal rail, Al extrusion, with threaded insert,
St, M2.5
11 2 2 Rear horizontal rail, Al extrusion, with threaded insert,
St, M2.5 and insulation strips, PBT, UL 94 V-0
(for indirect backplane mounting)
12 - 1 Centre horizontal rail, Al extrusion, anodised,
conductive surfaces, with two threaded inserts,
St, M2.5 and two insulation strips, PBT, UL 94 V-0
13 1 1 Rear panel with perforation, Al, anodised, 2 mm
at 28, 42 and 63 HP, 2.5 mm at 84 HP
14 4 4 Support member for rear panel, Zn die-cast
15 10/
20
10/
20
Guide rail for 160 mm board length, PBT, UL 94 V-0,
28/42 HP 10 pieces, 63/84 HP 20 pieces
16 1 1 GND/earthing kit
17 1 1 Assembly kit
5.49
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 11/2013
Main Catalogue Order Information
Maximum mounting depth = D - 45
(Distance: front panel - rear panel)
Note
Dimension drawings of side panel see from page 5.53
Complete cases, unshielded
05809051
05806060
3 U
05806062
6 U
155,5
130,0
112,3
289,0
262,8
245,7
W2
W1
121,95
150,9
D
32,5
15 Ø 4,6
4
7,2
121,95
265,9
15 Ø 4,6
4
7,2
121,95
284,3
D
32,5
Usable width Width W1 Depth D Height Part no.
W2 W2
HP mm mm mm U
28 147.3 185.9 266 3 24576-001
28 147.3 185.9 326 3 24576-002
42 218.4 257 266 3 24576-003
42 218.4 257 326 3 24576-004
42 218.4 257 386 3 24576-005
63 325.1 363.7 266 3 24576-006
63 325.1 363.7 326 3 24576-007
63 325.1 363.7 386 3 24576-008
84 431.8 470.3 266 3 24576-009
84 431.8 470.3 326 3 24576-010
84 431.8 470.3 386 3 24576-011
84 431.8 470.3 446 3 24576-012
84 431.8 470.3 506 3 24576-013
84 431.8 470.3 326 6 24576-021
84 431.8 470.3 446 6 24576-022
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.50 Main Catalogue
E 10/2012
Desk-top enclosure –i
Main Catalogue
Desk-top case with pre-configured components, in accordance
with IEC 60297-3-101; prepared for 19" components such as
plug-in units and euroboards
Ventilation slots in base plate
Prepared for GND/earthing
Delivery comprises (kit, items 1 - 5 fitted)
Order Information
Maximum mounting depth = D - 45
(Distance: front panel - rear panel)
Note
Case, 3 U with side panel for tip-up carrying handle,
see page 5.52
Dimensions see page 5.48
Dimensions side panel, see page 5.53
Cases, 2 and 3 U, unshielded
05806001
05806057
05806077
Cross-section 2 U, 3 U
05806059 05806060
2 U 3 U
ServicePLUS see page 5.4
Item Qty Description
1 1 Frame, Al die-cast, powder-coated, RAL 7016
2 2 Side panel, Al extrusion, powder-coated, RAL 9006
3 1 Cover plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006,
with GND/earthing tag
4 1 Base plate, Al, 1 mm, internal surface conductive, visible
surface powder-coated, RAL 9006, with GND/earthing
tag, base plate with 4 rows of ventilation slots
5 2 End piece for rear, ABS, RAL 7016, UL 94 V-0;
can be used as a foot for use in vertical position
6 4 Case foot with anti-slip protection, PC, black, UL 94 V-0
7 1 Assembly kit
Usable width Width W1 Depth D 2 U 3 U
W2 W2 Part no. Part no.
HP mm mm mm
28 147.3 185.9 266 – 14576-101
28 147.3 185.9 326 – 14576-103
42 218.4 257 266 14576-021 14576-121
42 218.4 257 326 14576-023 14576-123
42 218.4 257 386 – 14576-125
63 325.1 363.7 266 14576-041 14576-141
63 325.1 363.7 326 14576-043 14576-143
63 325.1 363.7 386 14576-045 14576-145
84 431.8 470.3 266 – 14576-161
84 431.8 470.3 326 – 14576-163
84 431.8 470.3 386 – 14576-165
84 431.8 470.3 446 – 14576-167
84 431.8 470.3 506 – 14576-169
Accessories
GND/earthing kit Cu wire 1.5 mm2, PVC sleeve, green/
yellow, links side panels, base, cover and rear panel,
PU 1 piece
21102-001
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.51
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Desk-top case with pre-configured components, in accordance
with IEC 60297-3-101; prepared for 19" components such as
plug-in units and euroboards
Ventilation slots in base plate
Prepared for GND/earthing
Delivery comprises (kit, items 1 - 6 fitted)
Order Information
Maximum mounting depth = D - 45
(Distance: front panel - rear panel)
Note
Case, 4 U with side panel for tip-up carrying handle,
see page 5.52
Dimensions side panel, see page 5.53
Cases, 4 and 6 U, unshielded
05806003
05806058
05806078
05806061 05806062
4 U 6 U
ServicePLUS see page 5.4
Item Qty Description
4 U 6 U
1 1 1 Frame, Al die-cast, powder-coated, RAL 7016
2 2 4 Side panel, Al extrusion, powder-coated, RAL 9006
3 1 1 Cover plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006,
with GND/earthing tag
4 1 1 Base plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006, with GND/
earthing tag, base plate with 4 rows of ventilation slots
5 2 2 End piece for rear, ABS, RAL 7016, UL 94 V-0;
can be used as a foot for use in vertical position
6 – 2 Adaptor bracket, Al
7 2 2 Cover trim for side panel, Al extrusion,
powder-coated, RAL 9006
8 4 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0
9 1 1 Assembly kit
Usable width Width W1 Depth D 4 U 6 U
W2 W2 Part no. Part no.
HP mm mm mm
42 218.4 257 266 14576-221 –
42 218.4 257 326 14576-223 –
63 325.1 363.7 266 14576-241 –
63 325.1 363.7 326 14576-243 –
63 325.1 363.7 386 14576-245 –
63 325.1 363.7 446 14576-247 –
84 431.8 470.3 326 – 14576-463
84 431.8 470.3 386 14576-265 14576-465
84 431.8 470.3 446 14576-267 14576-467
84 431.8 470.3 506 14576-269 14576-469
Accessories
GND/earthing kit Cu wire 1.5 mm2, PVC sleeve, green/
yellow, links side panels, base, cover and rear panel ,
PU 1 piece
21102-001
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.52 Main Catalogue
E 10/2012
Desk-top enclosure –i
iMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Desk-top case with pre-configured components, in accordance
with IEC 60297-3-101; prepared for 19" components such as
plug-in units and euroboards
Ventilation slots in base plate
Prepared for GND/earthing
Prepared for fitting of tip-up carrying handle
Delivery comprises (kit, items 1 - 6 fitted)
Order Information
Note
Dimensions see page 5.48
Dimensions side panel, see page 5.53
3 U and 4 U cases, unshielded,
with holes for tip-up carrying handle
05812006
05812050
05812051
05812052 05812053
3 U 4 U
ServicePLUS see page 5.4
5
2
1
7
3
4
155,5
130,0
112,3
200,0
174,0
156,8
W2
W1
121,95
150,9
D
32,5
15 Ø 4,6
4
7,2
17,0 17,0 Ø 4,6 Ø 10,4
69,0
11,4
121,95
33,05
195,3
D
32,5 17,0 17,0
69,0
15 Ø 4,6
4
7,2
Ø 4,6 Ø 10,4
Item Qty Description
3 U 4 U
1 1 1 Frame, Al die-cast, powder-coated, RAL 7016
2 2 4 Side panel, Al extrusion, powder-coated, RAL 9006;
with drill holes for tip-up carrying handle
3 1 1 Cover plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006,
with GND/earthing tag
4 1 1 Base plate, Al, 1 mm, internal surface conductive,
visible surface powder-coated, RAL 9006,
with GND/earthing tag, base plate with 4 rows of
ventilation slots
5 2 2 End piece for rear, ABS, RAL 7016, UL 94 V-0;
can be used as a foot for use in vertical position
6 – 2 Cover trim for side panel, Al extrusion,
powder-coated, RAL 9006
7 4 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0
8 1 1 Assembly kit
Usable width Width W1 Depth D 3 U 4 U
W2 W2 Part no. Part no.
HP mm mm mm
42 218.4 257.0 326 14577-123 14577-223
42 218.4 257.0 386 14577-125 –
63 325.1 363.7 326 14577-143 14577-243
63 325.1 363.7 386 14577-145 14577-245
84 431.8 470.3 326 14577-163 –
84 431.8 470.3 386 14577-165 14577-265
Accessories
GND/earthing kit Cu wire 1.5 mm2, PVC sleeve, green/
yellow, links side panels, base, cover and rear panel , PU
1 piece
21102-001
Tip-up carrying handle for 42 HP case width, PU 1 kit 24576-071
Tip-up carrying handle for 63 HP case width, PU 1 kit 24576-072
Tip-up carrying handle for 84 HP case width, PU 1 kit 24576-073
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.53
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Text
Dimensions
Extruded side panel 2 U Extruded side panel 3 U
05806079 05806080
Extruded side panel 4 U, right Extruded side panel 4 U, left
05806081 05806082
Extruded side panel 6 U Dimensions table
For case depth D d n
mm mm mm
266 221.6 210 14
326 281.6 270 18
386 341.6 330 22
446 401.6 390 26
506 461.6 450 30
Note
A side panel for case 6 U consists of 2 pieces 3 U extruded side panels
Side panel with horizontal rail
05806083 05806107
D
12,25
e = D - 62,1
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.54 Main Catalogue
E 10/2012
Desk-top enclosure –i
05806063
PPA43756
Main Catalogue Delivery comprises
Order Information
EMC front panel see chapter Front Panels, page 7.7
05806064
05806065
Main Catalogue Delivery comprises
Order Information
Note
Please order items 2, 3 and 4 separately
Front panel, unshielded,
for mounting on case frame
Item Qty Description
1 1 Full-width front panel, Al, 2 mm (on 84 HP = 2.5 mm),
anodised, cut edges plain
2 1 Assembly kit
For case
height
For case
width
A B C D Part no.
U HP mm mm mm mm
2 42 238.7 230.0 74.0 84.0 20850-128
2 63 345.4 336.7 74.0 84.0 20850-129
2 84 452.0 443.3 74.0 84.0 20850-130
3 28 167.6 158.9 118.5 128.5 20850-134
3 42 238.7 230.0 118.5 128.5 20850-135
3 63 345.4 336.7 118.5 128.5 20850-136
3 84 452.0 443.3 118.5 128.5 20850-137
4 42 238.7 230.0 162.9 172.9 20850-142
4 63 345.4 336.7 162.9 172.9 20850-143
4 84 452.0 443.3 162.9 172.9 20850-144
6 84 452.0 443.3 251.8 261.8 20850-158
Front panel, 1 U, unshielded, for 4 U case,
for mounting on horizontal rails
Item Qty Description
1 1 Front panel, Al, 2.5 mm, front anodised,
rear iridescent green chromated
Width A B C Front panel
HP mm mm mm Part no.
28 141.9 127.0 – 20850-423
42 213.0 198.1 101.6 20850-424
63 319.7 304.8 157.5 20850-425
84 426.4 411.5 203.2 20850-426
Width Item 2
EMC gasket,
front panel/
horizontal rail
PU 10 pieces
Item 3
EMC gasketing kit
horizontal rails,
1 piece
Item 4
Horizontal rail
type H-KD,
1 piece (SPQ 10)1)
HP Part no. Part no. Part no.
28 24560-229 24562-528 34560-228
42 24560-231 24562-542 34560-242
63 24560-233 24562-563 34560-263
84 24560-235 24562-584 34560-284
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is
exclusively made in standard pack quantity (SPQ); please order at least the SPQ
quantity or a multiple thereof
5.55
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
01802055
01804050
Unshielded
01802055
Shieldable
Main Catalogue
Two versions: unshielded, Al, 2.5 mm
shieldable, Al extrusion (textile EMC gasketing retrofittable)
Delivery comprises
Order Information
Please order textile EMC gasket separately
EMC gasket rear panel - horizontal rail see page 5.65
Horizontal rails see page 5.67
Assembly parts see page 6.63
04602054
Main Catalogue
The textile EMC gasket is glue fixed laterally on the front panel,
always in the groove on the right-hand side of the profile
Temperature range -40 °C ... +70 °C
Delivery comprises ()
Order Information
Rear panel, perforated,
for mounting on horizontal rails
7,45 7,45
B
ø 5,9 x 3,3
W
Z
3,2
7,2
25
3 3
H
2,5
W - 2,58
2,5
3,7
3,7
Item Qty Description
1 1 Rear panel, Al, 2.5 mm,
front: anodised, rear: iridescent green chromated;
unshielded or shieldable with EMC sealing (textile)
Height H Width W B h unshielded shieldable
U mm HP mm mm mm Part no. Part no.
2 84 28 141.9 – 78 30849-007 20848-679
2 84 42 213 101.6 78 30849-014 20848-680
2 84 63 319.7 157.5 78 30849-015 20848-681
2 84 84 426.4 208.3 78 30849-016 20848-682
3 128.4 28 141.9 – 122.4 30849-008 20848-633
3 128.4 42 213 101.6 122.4 30849-021 20848-634
3 128.4 63 319.7 157.5 122.4 30849-022 20848-635
3 128.4 84 426.4 208.3 122.4 30849-023 20848-636
4 172.9 28 141.9 – 166.9 30849-009 20848-656
4 172.9 42 213 101.6 166.9 30849-028 20848-657
4 172.9 63 319.7 157.5 166.9 30849-029 20848-658
4 172.9 84 426.4 208.3 166.9 30849-030 20848-659
6 261.8 28 141.9 – 255.8 30849-010 20848-640
6 261.8 42 213 101.6 255.8 30849-035 20848-641
6 261.8 63 319.7 157.5 255.8 30849-036 20848-642
6 261.8 84 426.4 208.3 255.8 30849-037 20848-643
Textile EMC gasket
Item Qty Description
1 10/100 Textile EMC gasket, core: foam,
sleeve: textile cladding with CuNi coating
Height Height Qty/PU Part no.
U mm pieces
2 52 10 21101-857
3 97 100 21101-854
3 97 10 21101-853
4 142 10 21101-858
6 232 100 21101-856
6 232 10 21101-855
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.56 Main Catalogue
E 10/2012
Desk-top enclosure –i
05806066
ppa43882
Main Catalogue
Mounting with support brackets on case (right and left)
Versions with and without perforation
Delivery comprises
Order Information
05806067
Main Catalogue
Mounts on case (left, right)
Without perforation
Delivery comprises
Order Information
Rear panel, unshielded,
for mounting on case frame
Item Qty Description
1 1 Full-width rear panel, Al, anodised, cut edges blank
28, 42, 63 HP = 2 mm thickness
84 HP = 2.5 mm thickness
2 4 Support member, Zn die-cast
3 1 Assembly kit
Height H Width W w With
perforation
Without
perforation
U mm HP mm mm Part no. Part no.
2 84 42 213 190 24576-144 24576-044
2 84 63 320 298 24576-145 24576-045
2 84 84 426 406 24576-146 24576-046
3 128.5 28 142 118 24576-147 24576-047
3 128.5 42 213 190 24576-148 24576-048
3 128.5 63 320 298 24576-149 24576-049
3 128.5 84 426 406 24576-150 24576-050
4 172.9 42 213 190 24576-152 24576-052
4 172.9 63 320 298 24576-153 24576-053
4 172.9 84 426 406 24576-154 24576-054
6 261.8 84 426 406 24576-158 24576-058
Rear panel, shielded,
for mounting on case frame
Item Qty Description
1 1 Full-width EMC rear panel, Al 1.5 mm, passivated,
with GND/earthing connection (Faston 6.3 mm)
2 2 Textile EMC gasketing, for mounting top and bottom,
core: foam,
sleeve: textile cladding with CuNi coating
3 2 Textile EMC gasketing, for mounting left and right,
core: foam,
sleeve: textile cladding with CuNi coating
4 1 Assembly kit
Height H Height h Width W w Part no.
U mm mm HP mm mm
2 101.5 84 42 217.9 213 24576-244
2 101.5 84 63 324.6 319.7 24576-245
3 146 128.4 28 146.8 141.9 24576-247
3 146 128.4 42 217.9 213 24576-248
3 146 128.4 63 324.6 319.7 24576-249
3 146 128.4 84 431.3 426.4 24576-250
4 190.4 172.9 42 217.9 213 24576-252
4 190.4 172.9 63 324.6 319.7 24576-253
4 190.4 172.9 84 431.3 426.4 24576-254
6 279.3 261.8 84 431.3 426.4 24576-258
5.57
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
05806102
05806097
04602081
Main Catalogue
Front panel with textile EMC gasketing
Hinges can be fitted left or right
Suitable for europacPRO subrack and ratiopacPRO,
compacPRO and propacPRO cases
Delivery comprises (kit)
Order Information
Note
Usable width reduced by 2 HP (hinged side)
Horizontal rail (item 5) for front panel mounting is required,
please order separately
Lateral trim is necessary, please order separately, see page
5.59
05806068
Main Catalogue
For EMC shielding between side panel and top cover or base
plate (sufficient for at least 1 case)
Order Information
Front panel, hinged, shielded,
for mounting on horizontal rails
1
3
2
5
Item Qty Description
1 1 Front panel, hinged, Al, 2.5 mm,
front anodised, rear iridescent green chromated
2 2 Hinge, Zn die-cast, chrome-plated
3 1 Textile EMC gasket
core: foam, sleeve: textile cladding with CuNi coating
4 1 Assembly kit
Height Width H h W w Part no.
U HP mm mm mm mm
3 84 128.4 89.9 426.4 203.2 20848-611
6 84 261.8 223.2 426.4 203.2 20848-617
Item 5, Horizontal rail Type H-VT heavy duty, recessed
mounting 84 HP, 1 piece (SPQ 10) 34560-784
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
EMC side panel gasket
Item Description Qty/PU Part no.
1 Sealing cord, silicone, silver coated,
Ø 2.4 mm, length 2.1 m 1 30850-354
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.58 Main Catalogue
E 11/2013
Desk-top enclosure –i
Main Catalogue
To individualise case design
Delivery comprises
Order Information
Note
Size 28 HP and further colours available on request
Cannot be combined with front hood
Design elements
05809002
Qty Description
1 Design element, Al extrusion, powder-coated
1 Assembly kit
Description Width Light grey
RAL 7035
Brilliant
blue
RAL 5007
HP Part no. Part no.
Form 1
42 20850-184 20850-299
63 20850-185 20850-300
PPA43761
84 20850-186 20850-301
Form 2
42 20850-190 20850-315
63 20850-191 20850-316
PPA43762
84 20850-192 20850-317
Form 3
42 20850-196 20850-331
63 20850-197 20850-332
PPA43763
84 20850-198 20850-333
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.59
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
05806069
Main Catalogue
For lateral covering of frame and for producing a continuous
front with front panels and plug-in units
Serves for lateral shielding of side panels simultaneously
Delivery comprises (kit)
Order Information
05806103
Main Catalogue
For vertical EMC shielding between shielded front panels and
side panel
Delivery comprises
Order Information
Trim, front, for EMC shielding
Item Qty Description
1 2 Lateral trim, Al extrusion,
visible surface painted RAL 7016
2 1 Textile EMC gasket
3 1 Assembly kit
For case height h Part no.
U mm
2 84 24576-017
3 128.5 24576-117
4 172.9 24576-217
6 261.8 24576-417
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Trim, rear, for EMC shielding
Item Qty Description
1 2 EMC contact strip, Al extrusion
2 1 Textile EMC gasket
3 1 Assembly kit
Height Height Part no.
U mm
2 65.55 24576-018
3 110 24576-118
4 154.45 24576-218
6 243.35 24576-418
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.60 Main Catalogue
E 10/2012
Desk-top enclosure –i
Main Catalogue
With powder-coated carrying bar
Can be locked in 30° increments
Load-carrying capacity 20 kg
Delivery comprises (Kit)
Order Information
Note
To fit the tip-up carrying handle, holes must be drilled in the side
panel
Readily prepared cases (3 U and 4 U), for mounting the tip-up
carrying handle see page 5.52
05806098
Main Catalogue
Load-carrying capacity: 20 kg
Delivery comprises (Kit)
Order Information
Note
Holes must be drilled into the side panels to fix the strap handle
Side panels with holes already drilled available on request
Usable from case depth of D = 326 mm
Tip-up carrying handle
05806101
Item Qty Description
1 1 Carrying bar, Al extrusion, powder-coated, RAL 7016
2 2 Handle side part, Zn, die-cast, powder-coated,
length 180 mm
3 2 Safety insert, St, 1.5 mm, black
4 1 Assembly kit for side panel mounting
For case width Part no.
HP
28 24576-070
42 24576-071
63 24576-072
84 24576-073
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Strap handle
Item Qty Description
1 1 Band, spring steel,
handle, flexible plastic, grey, RAL 7016
2 2 Cover, grey, RAL 7016
3 1 Assembly kit
Description Part no.
Strap handle with adaptor 20850-249
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.61
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
05806070
Main Catalogue
Subsequent mounting possible without modification or tools
Filter change without opening the case, IP protection code not
affected
Delivery comprises (Kit)
Order Information
Note
For optimum ventilation feet must be fixed to the case, please
order separately
Air filter
2
3
1
Item Qty Description
1 1 Filter holder, Al, 1 mm, powder-coated, RAL 9006
2 1 Filter mat, synthetic fibre
3 1 Velcro
For case width Air filter Replacement
filter 1 piece
HP Part no. Part no.
28 24576-093 64571-033
42 24576-094 64571-034
63 24576-095 64571-035
84 24576-096 64571-036
Tip-up foot in plastic silver, similar to RAL 9006,
4 pieces 20603-001
Plastic tip-up foot anthracite, similar to RAL 7016,
4 pieces 20603-002
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.62 Main Catalogue
E 10/2012
Desk-top enclosure –i
05806071
05806072
1) Front panel
05806073
Lock for front hood
Main Catalogue
From acrylic glass, hinged, removable
Mounting of hinges at top or bottom
Lock (max. 2) retrofittable
Lateral cover (item 5) also serves as vertical EMC shielding of
side panels
Delivery comprises (kit)
Order Information
Note
Cannot be combined with design elements
Other heights available on request
Before assembly of hood feet must be fixed to case;
please order separately
Front hood 3 U
16
1)
147,2
11
180°
3
Item Qty Description
1 1 Hood, PMMA, tinted blue grey, acrylic glass, 3 mm
2 2 Hinge, PC, UL 94 V-0, RAL 7016
3 2 Handle, PC, UL 94 V-0, RAL 7016
4 2 Retainer, UL 94 V-0, PC, RAL 7016
5 2 Lateral trim, Al extrusion, visible surface painted
RAL 7016
6 1 Assembly kit
For case width Part no.
HP
28 24576-080
42 24576-081
63 24576-082
84 24576-083
Lock for front hood Locking cylinder, key, assembly kit,
PU 1 kit 60850-171
Plastic tip-up foot silver, similar to RAL 9006, 4 pieces 20603-001
Plastic tip-up foot anthracite, similar to RAL 7016,
4 pieces 20603-002
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.63
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
iMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Increases the distance between rear panel and parking surface
(when used vertically)
Simplifies cable routing
Increased shock and vibration damping
Required for mounting rear hood
Delivery comprises
Order Information
05806075
05806076
Main Catalogue Delivery comprises (kit)
Order Information
Note
To fit the rear hood, feet must be fitted to the rear panel;
please order separately
Foot for rear hood
ppa45113 ppa45106
Item Qty Description
1 2 Foot, PU foam
1 1 Assembly kit
For cabinet height Height H Part no.
U mm
3 147.9 24576-393
4 192.3 24576-394
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Rear hood
Item Qty Description
1 1 Hood, Al, 1 mm, RAL 9006, fixing with knurled screws
2 1 Assembly kit
HeightWidth A B C D E Part no.
U HP mm mm mm mm mm
3 42 246 230 213 145.9 64 24576-086
3 63 352.7 336.7 319.7 145.9 64 24576-087
3 84 459.4 443.4 426.4 145.9 64 24576-088
4 63 352.7 336.7 319.7 190.4 108.5 24576-091
4 84 459.4 443.4 426.4 190.4 108.5 24576-092
Foot for rear hood for case height 3 U, PU foam, black,
PU 2 pieces 24576-393
Foot for rear hood for case height 4 U, PU foam, black,
PU 2 pieces 24576-394
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.64 Main Catalogue
E 10/2012
Desk-top enclosure –i
Order Information
06103057
propacPRO:
D = board length - 47.5 mm; n = 1 for 160 mm board length;
n = 2 for 220 mm board length; n=4 for 340 mm board length
Note
Please order assembly kit for mounting plate separately
Fixing strips required for partial width, please order separately
Other versions on request
Dimensions side panel with horizontal rail see page 5.53
Mounting plates
Mounting plate for fixing of heavy components
Mounting plate over full width:
mounting is onto the side panels
Mounting plate over partial width:
mounting is onto one side panel and a fixing strip or
onto 2 fixing strips
Fixing strip for partial widths
05812001 06102501 05806100
Board lengths
Al, 1.5 mm; for mounting over partial width,
please order fixing strips separately
St, 2 mm, zinc-plated;
is bolted from front to rear onto the horizontal rails;
to fix mounting plates
Width W W
HP mm mm 1 piece 1 piece
42 217.99 160 34562-746 30840-021
42 217.99 220 34562-750 30840-033
63 324.67 160 34562-747 30840-021
63 324.67 220 34562-751 30840-033
84 431.35 160 34562-748 30840-021
84 431.35 220 34562-752 30840-033
84 431.35 340 34562-760 30840-057
Assembly kit for mounting plate, PU 1 kit
(Torx countersunk screw M4 x 5, St, zinc-plated,
12 pieces; screw M4 x 6, St, zinc-plated,
10 pieces; M4 square nut, St, zinc-plated,
10 pieces)
24560-184 –
Assembly kit for fixing strips for partial width
mounting plates, Torx screw M2.5 × 5, St,
zinc-plated, PU 100 pieces
M2.5 × 5, St, zinc-plated, PU 100 pieces
– 24560-146
5.65
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
05806109
Main Catalogue
The EMC contact strip is clipped onto the horizontal rail and
forms a conductive link to front or rear panel
Can be used for front/rear horizontal rails type VT (recessed)
Delivery comprises
Order Information
aza43284
Main Catalogue
Protective GND/earthing connections in accordance with:
– DIN EN 50178/VDE 0160
– DIN EN 60950/VDE 0805
– DIN EN 61010-1/VDE 0411 part 1
– DIN EN 61010-1A2/VDE 0411 part 1A1
VDE tested
Order Information
02908053
02908052
Main Catalogue Delivery comprises
Order Information
EMC gasket, stainless steel,
between front/rear panel and horizontal rail
Item Qty Description
1 10/100 EMC gasket, St, stainless
Width Length Qty/PU Part no.
HP mm pieces
28 131.78 10 24560-229
42 202.9 10 24560-231
63 304.5 10 24560-233
84 416.56 10 24560-235
84 416.56 100 24560-236
GND/earthing kit
Description Part no.
GND/earthing kit, Cu wire 1.5 mm2, PVC sleeve, green/
yellow, links side panels, base and rear panel, 1 piece 21102-001
Cable holder
19 9
17
14
26,5
46
20,2
Ø 3 Ø 4,4
Ø 4,4 Ø 3
Item Qty Description
1 2 Cable holder, ABS, UL V-94 0, RAL 7016,
detent for cables between 8 mm and 12 mm
2 1 Drilling template, two drill holes each per holder are
needed in rear panel
3 1 Assembly kit
Description Part no.
Cable holder 24575-800
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.66 Main Catalogue
E 10/2012
Desk-top enclosure –i
Text
Mounting position horizontal/central rails
2 U
05806084
3 U
05806085 05809050
4 U (3 + 1) "Z" (EMC shielding with 2 horizontal rails)
05806086 06106051
6 U 6 U (2 x 3)
05806087 05806088
H - VT H - VT
H - VT H - VT
H - VT
H - VT
H - VT
H - VT
H - ST
H - VT
H - MZ
H-VT H-ST
H-KD H-MZ
ST
H - VT
H - VT
2 x H - KD
H - VT
H - VT
H - ST
H - VT
H - MZ
H - VT
H - VT
H - VT
H - VT
ST
H - ST
H - VT
H - MZ
H - ST
H - VT
H - MZ
H - VT
“Z” “Z”
2 x H - KD
H - VT
H - VT
H - VT
H - ST
H - VT
H - MZ
H - ST
H - VT
H - MZ
H - ST
H - VT
H - MZ
5.67
Desk-top enclosure –i
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Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Order Information
Note
Further horizontal rails see from page 6.27
Fitting options see page 5.66
Horizontal rails to front/centre/rear
For indiect
backplane fixing
with insulation
strip
For direct
backplane fixing
For direct fixing
of connectors in
accordance with
EN 60603-2
(DIN 41612)
Front horizontal
rails
Stainless steel
EMC gasket
between
horizontal rail
and
horizontal rail
Horizontal rail
type H-VT
robust,
with EMC gasket
06197011 06197011 06197011 bza45877 06106052
"heavy" "heavy" "heavy" "heavy"
Type H-ST Type H-VT Type H-MZ Type H-KD
standard long lip with Z-rail short lip
06197011 06197009 06197015 06197008
Al extrusion,
anodised finish,
conductive surface,
with printed HP
markings
Al extrusion,
anodised finish,
conductive surface,
with printed HP
markings
Al extrusion,
anodised finish,
conductive surface,
with printed HP
markings
Al extrusion,
anodised finish,
conductive surface,
with printed HP
markings
item 1: metal strip,
Al, 1 mm,
item 2: EMC
stainless steel
gasket; for shielding
of 2 horizontal rails
positioned directly
one above the other
if assembly area is
divided vertically
horizontal rail:
Al extrusion,
anodised,
conductive contact
surface
for cover plates on
shielded cases
Usable length Length
HP mm 1 piece
(SPQ 10)1)
1 piece
(SPQ 10)1)
1 piece
(SPQ 10)1)
1 piece
(SPQ 10)1)
PU 1 kit 1 piece
28 147.32 34560-528 34560-728 34560-928 34560-228 24562-528 24576-028
42 218.44 34560-542 34560-742 34560-942 34560-242 24562-542 24576-042
63 325.12 34560-563 34560-763 34560-963 34560-263 24562-563 24576-063
84 431.80 34560-584 34560-784 34560-984 34560-284 24562-584 24576-084
Torx panhead screw , M4 × 14,
St, zinc-plated, PU 100 pieces 24571-371 24571-371 24571-371 24571-371 – 24571-371
Torx panhead screw , M 4 × 10,
St, zinc-plated, necessary if
guide rail is screwed to slot 1,
PU 100 pieces
– – 24571-372 24571-372 – 24571-372
Perforated rail for connector
mounting with insulation strip
see page
5.69 – – – – –
Z-rail for connector mounting
without insulation strip see page 5.69 – – – – –
Insulation strips see page – 5.68 – – – –
Threaded inserts see page 5.68 5.68 5.68 5.68
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.68 Main Catalogue
E 10/2012
Desk-top enclosure –i
05806089
Main Catalogue
For indirect backplane mounting (with insulation strip)
For 6 U propacPRO case
Delivery comprises (kit, item 1 to 4 are pre-mounted)
Order Information
Order Information
Horizontal rails, centre, type ST-C
Item Qty Description
1 1 Horizontal rail, Al extrusion, anodised, contact surfaces
conductive
2 2 Adaptor plate, Al
3 2 Threaded insert, M2.5, St, zinc-plated
4 2 Countersunk screw, M4 x 14
5 4 Pan head screw, M4 x 6
Usable width Length Part no.
HP mm
84 431.8 24575-474
Insulation strip 84 HP, PBT UL 94 V-0, grey,
PU 10 pieces 24560-884
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Threaded inserts, perforated strips, insulation strips
Threaded insert Perforated strip Insulation strip
M2.5 M3 (item 1)
06103056 BZA45853 BZ6749
Threaded insert
required for fixing the front panel to the
horizontal rail; St, zinc-plated;
use collar screw 12.3 mm, see page
6.64
Perforated strip
for centring shielded
plug-in units, Al, 1 mm,
please order
grub screw separately
Insulation strip
for insulated
backplane mounting;
PBT UL 94 V-0,
grey
Usable length Length Length Length
HP mm 1 piece
(SPQ 10)1)
1 piece
(SPQ 10)1)
mm 1 piece (SPQ 10)1) mm PU 10 pieces
28 146.82 34561-328 – 147.12 30845-197 144.20 24560-828
42 217.94 34561-342 – 218.24 30845-211 210.40 24560-842
63 324.62 34561-363 – 324.92 30845-232 316.88 24560-863
84 431.30 34561-384 34561-484 431.60 30845-253 428.64 24560-884
5
2
5,08
Accessories
Grub screw M2.5 x 8,
PU 100 pieces 21100-276 – – –
Grub screw M2.5 x 9,
PU 100 pieces – – 21101-359 –
Grub screw M3 x 8,
PU 100 pieces – 21100-646 – –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least
the SPQ quantity or a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
5.69
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Z-rails, perforated rails
Z-rail for connectors Perforated rail
DIN EN 60603-2, DIN 41612
item 1
31-pin, DIN 41617 EN 606032, DIN 41612
item 1
BZA45849 BZA45850 BZA45848
06708063 06708051
for connector mounting on
ST horizontal rails,
please order threaded insert and
screw separately
for connector mounting on
ST horizontal rails,
please order threaded insert and
screw separately
for connector mounting on
VT horizontal rails,
please order threaded insert and
screw separately Usable length Length
HP mm 1 piece 1 piece PU 4 pieces
28 142.24 30822-033 – 20822-049
42 213.36 30822-047 – 20822-050
60 304.80 30822-065 30819-783 20822-047
84 426.70 30822-089 30819-808 20822-048
Item 3, Torx panhead screw
to fix connector to perforated rail,, M2.5 × 7,
PU 100 pieces
24560-147 24560-147 24560-147
Item 2, Torx panhead screw,
to fix perforated rail to horizontal rail, M2.5 × 10,
PU 100 pieces
24560-148 24560-148 24560-148
172,5
172,5
175,5
2
1
3
3,0
9,75
12,75
2
1
3
12,75
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.70 Main Catalogue
E 10/2012
Desk-top enclosure –i
Order Information
Subdivision of the 6 U assembly area into:
– 2 x 3 U
– 1 x 6 U
Designed to accept euroboards (100 mm high) and double
euroboards (233.35 mm high)
Note
Please order EMC gasketing kit for horizontal rails separately,
see page 6.54
Please order perforated strips for horizontal rails separately, see
page 5.68
Please order rear centre horizontal rail separately, see page
5.68
Combined mounting (6 U and 2 x 3 U one above the other)
Combined mounting Splitting extrusion
Horizontal and
vertical subdivision
(incl. front panel for
stainless steel EMC gasket)
Unshielded
front panel,
6 U, 2 HP
item 5
Front panel for
textile EMC gasket,
6 U, 2 HP
item 5
for combined
mounting
item 2
05806108
bza45819 06102501 06102501 06102501
item 1: 2 front horizontal rails (H-KD),
Al extrusion, anodised;
item 2: 2 rear horizontal rails (AB),
Al extrusion, anodised;
item 3: threaded insert, St,
zinc-plated;
item 4: Zn die-cast support member;
item 5: front panel 2 HP, 6 U,
shielded;
with EMC stainless steel gasket;
84:0 without items 4, 5
Al, 2.5 mm,
front anodised,
rear iridescent green
chromated
Al, 2.5 mm,
U-profile with notch,
6 U, 2 HP
6 U, Zn die-cast;
splitting extrusion is
inserted in the grid
holes of the
horizontal rail;
the splitting extrusion
can be bolted
Width pitch T1:T2
HP PU 1 kit 1 (SPQ 5) 1 piece (SPQ 5)1) 1 piece
20:62 24562-420
30847-472 30849-140 64560-010
40:42 24562-440
42:40 24562-442
63:19 24562-463
84:0 24562-484
Torx countersunk screw
M4 × 14, zinc-plated, PU 100 pieces
for fixing splitting extrusion/horizontal rail
– – – 24560-145
Panhead screw
M2.5 × 10, St, zinc-plated, PU 100 pieces
for fixing horizontal rail/splitting extrusion
– – – 24560-179
Pozidrive/slotted collar screw
M2.5 x 12.3, St, nickel-plated, PU 100 pieces – 21101-101 21101-101 –
Pozidrive/slotted collar screw
M2.5, black, zinc-plated, PU 100 pieces – 21101-102 21101-102 –
Washer
2.7 x 5 x 1, plastic PA 6, PU 100 pieces – 21101-121 21101-121 –
Textile gasket, core: foam,
sleeve: textile cladding with CuNi coating,
UL 94 V-0, PU 10 pieces
– 21101-855
5.71
Desk-top enclosure –i
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Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Horizontal board mounting
Horizontal board mounting
Board cage Front frame for
EMC gasketing
Front frame, unshielded
05806092
05806091 bpa45913 bza43061
(1 TE = 1 HP, 1 HE = 1 U)
Struts die-cast zinc;
horizontal rails front and rear;
threaded insert, St, zinc-plated;
fixing material kit;
for horizontal mounting of
double-height euroboards in
3 or 4 U high
subracks/cases;
54 HP space required; please
order front frame for EMC
gasketing separately
2 horizontal trims,
AI 2.5 mm, front anodised,
rear iridescent green chromated;
2 vertical trims, Al extrusion,
clear passivated;
stainless steel EMC gasket;
front frame forms the
contact between subrack and the
sub-assemblies
Al, 2.5 mm, clear anodised;
front frame with cut-out,
clear internal width w = 266.35 mm
Height H Usable
height h
HP
Other dimensions and
options
U Horizontal rail,
front
Horizontal rail,
rear
PU 1 kit PU 1 kit 1 piece
3 20 24564-117 24564-109 34564-108
3 20 24564-118 24564-109 34564-109
4 28 24564-217 24564-209 34564-208
Assembly tool, for mounting the
EMC gasket (stainless steel) – 24560-270 –
* For direct backplane mounting
273.98= 54TE
h
H
273,98 = 54 TE
w
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.72 Main Catalogue
E 10/2012
Desk-top enclosure –i
05806093
02906050
Main Catalogue
Static load-carrying capacity 25 kg per foot
Tip-up feet can be used instead of the pre-mounted case feet
Fixing holes provided in bottom of case
Delivery comprises (kit)
Order Information
AZA43836
02908051
Can be used instead of the round standard feet
Fixing holes provided in bottom of case
Secure case stance with slip-proof rubber inserts
Load carrying capacity: 50 kg per foot, max. case weight 40 kg
Order Information
1) Part no. comprises 1 piece;
delivery is in standard pack quantity (SPQ):
please order a minimum of 10 feet or a multiple
Note
Delivery is in standard pack multiples;
pricing is per individual item
Plastic tip-up feet
Item Qty Description
1 4 Foot, PA, UL 94 V-0
2 4 Anti-slip protection, TPE
3 2 Tip-up device, PA, UL 94 V-0
4 1 Assembly kit
Description Part no.
Plastic tip-up foot anthracite, similar to
RAL 7016, 4 pieces 20603-002
Plastic tip-up foot silver, similar to
RAL 9006, 4 pieces 20603-001
Cheesehead screw with slot M4 × 12, St, zinc-plated,
PU 100 pieces 21101-211
Hexagon nut M4, St, zinc-plated, PU 100 pieces 21100-211
Spring washer A4, St, zinc-plated, PU 100 pieces 21100-207
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Tip-up feet made of die-cast aluminium
41
20
Ø7,8
15,5
Ø3,1 Ø4,6
15 20
16,6
1
Description Qty Part no.
Foot with tip-up,
Al die-cast, silver 1 piece (SPQ 10)1) 10603-002
Foot without tip-up,
Al die-cast, silver 1 piece (SPQ 10)1) 10603-001
Cheesehead screw with slot M4 × 12, St, zinc-plated,
PU 100 pieces 21101-211
Hexagon nut M4, St, zinc-plated, PU 100 pieces 21100-211
Spring washer A4, St, zinc-plated, PU 100 pieces 21100-207
5.73
Desk-top enclosure –i
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Guide rails for plug-in units and frame type plug-in units, one-piece,
groove width 2 mm
Assembly
- can be clipped into Al extruded
horizontal rails
- can be clipped into 1.5 mm thick
plates
Storage temperature
from -40 °C ... 130 °C
For plug-in units and frame type plug-in units
Standard With DIN connector fixing as standard
06102001 06101501
up to 220 mm length, PBT, UL 94 V-0;
multi-piece from 280 mm length,
end piece PBT, UL 94 V-0,
central section Al extrusion
PBT, UL 94 V-0, red,
connector is clipped directly onto the guide rails;
for euroboards, 100 x 160 mm or 100 x 220 mm only
Board
lengths
Groove
width
Colour
mm mm mm PU 10 pieces 1 pair (SPQ 10)1)
70 2 red – –
70 2 grey – –
160 2 red 24560-351 64560-074
220 2 red 24560-353 64560-075
280 2 red 24560-379 –
340 2 red 24560-380 –
Dimension drawings see page 6.40 6.40
Accessories
Retention screw,
PU 100 pieces 24560-141 24560-141
ESD clip, PU 50 pieces
description see page 6.41 24560-255 24560-255
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Further guide rails see page 6.35
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.74 Main Catalogue
E 10/2012
Desk-top enclosure –i
Order Information
Guide rails type "accessories", one-piece, groove width 2 mm and
2.5 mm
Assembly
- can be clipped into horizontal rails
in Al extrusion
- can be clipped into 1.5 mm thick
plates
storage temperature
from -40 °C ... +130 °C
Guide rails Guide rails Guide rails
"Accessories" "Accessories" strengthened for heavy modules,
Al extrusion, silver,
robust version
06102002 06102005 06102005
up to 280 mm length, PBT, UL 94 V-0;
multi-piece from 280 mm length,
end piece PBT, UL 94V-0,
middle section Al extrusion
PBT UL 94 V-0,
red support beam of guide rails adds to
strengthening
Al extrusion; is screwed to horizontal rail
"heavy" with retention screws
Board
lengths
Groove
width
Colour
mm mm mm PU 10 pieces 1 piece (SPQ 50) 1 piece (SPQ 50)1)
100 2 red – – –
160 2 red 24560-373 64560-076 –
160 2 grey – – 34562-881
220 2 red 24560-374 64560-078 –
220 2 grey – – 34562-882
280 2 red/
silver 24560-375 64560-080 34562-883
340 2 red/
silver 24560-376 – 34562-884
400 2 silver – 34562-885
160 2.5 silver – – 34564-881
220 2.5 silver – – 34564-882
280 2.5 silver – – 34564-883
340 2.5 silver – – 34564-884
400 2.5 silver – – 34564-885
Dimension drawings see page 6.40 6.40 6.40
Accessories
Retention screw,
PU 100 pieces 24560-141 24560-141 24560-157
ESD clip, PU 50 pieces
description see page 6.41 24560-255 24560-255 –
Board locking, red,
PU 10 pieces,
description see page 6.41
24560-377 24560-377 –
Board handle, red,
PU 10 pieces,
description see page 6.41
24560-378 24560-378 –
Identification strips for board
handle, red,
PU 1 sheet = 438 pieces,
description see page 6.41
60817-228 60817-228 –
Coding see page 6.41 6.41 –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity
(SPQ); please order at least the SPQ quantity or a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Further guide rails see page 6.35
5.75
Desk-top enclosure –i
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Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Order Information
Divider plate
Divider plate
Mounting position when
stainless steel EMC gasket is used
Mounting position when
textile EMC gasket is used
front rear front rear
bpa45911 06105078
bpa45912
Stainless steel, 1 mm, is mounted by clipping onto horizontal rail,
space requirement on component side 2 mm;
mounting direction varies with shielding design (EMC stainless steel or textile gasket);
retrofitting the divider plate in an already-assembled subrack/case
will first require dismantling of the horizontal rails;
where front panels are unshielded, both mounting directions are possible
Height Depth A B H
U mm mm mm mm PU 10 pieces
3 160 158.3 135.0 113.5 34562-761
3 220 218.3 195.0 113.5 34562-762
6 160 158.3 135.0 246.9 34562-763
6 220 218.3 195.0 246.9 34562-764
Air baffle for slots
Air baffle Air baffle with front panel
without front panel U front panel for textile EMC gasket
06108085 06108088
06101507
Al, 1 mm, incl. assembly kit;
prevents an air short circuit in unoccupied slot positions;
is pushed into the groove of the guide rails
Air deflector, Al, 1 mm,
front panel, Al extrusion, 2.5 mm,
front anodised, rear conductive;
EMC textile gasket, fixing materials kit prevents an air
short-circuit where slots are unoccupied;
is pushed into the groove of the guide rails
Depth Width Height
mm HP U 1 piece 1 piece
160 4 3 34562-823 20848-728
160 4 6 34562-826 20848-736
160 8 3 34562-833 20848-730
160 8 6 34562-836 20848-738
160 12 3 34562-843 20848-732
160 12 6 34562-846 20848-740
220 4 3 34562-824 20848-729
220 4 6 34562-827 20848-736
220 8 3 34562-834 20848-731
220 8 6 34562-837 20848-739
220 12 3 34562-844 20848-733
220 12 6 34562-847 20848-741
Desk-top cases –b Overview . . . . . 0
Cabinets . . . . . . 1
Wall mounted
cases . . . . . . . . 2
Accessories for
cabinets and wall
mounted cases 3
Climate control 4
Desk-top cases 5
Subracks/
19" chassis . . . 6
Front panels,
plug-in units . . 7
Systems . . . . . . 8
Power supply
units . . . . . . . . . 9
Backplanes . . 10
Connectors, front
panel component
system . . . . . . 11
Appendix . . . . 12 Downloads and further important information can be found
on the Internet under www.schroff.biz
5.76 Main Catalogue
E 10/2012
bMain Catalogue
02004009
02004079 Flexible expansion options, for 19" components e.g. plug-in unit units, or for individual expansion
Standards
Interior dimensions in accordance with: IEC 60297-3-101
Type of protection IP 20 in accordance with IEC 60529
GND/earth connections in accordance with:
DIN EN 50178 / VDE 0160
DIN EN 60950 / VDE 0805
DIN EN 61010-1 / VDE 0411 part 1
DIN EN 61010-1A2 / VDE 0411 part 1/A12
Desk-top cases –b
Main Catalogue 5.77
E 10/2012
bMain Catalogue
Robust desk-top case for 19" components in accordance with
IEC 60297-3-10x or for individual electronics assemblies
Front and rear identical, depth-symmetrical construction
Highly robust thanks to die-cast frame (front/rear)
Side panel with integrated handle function
Desk-top cases
Complete case
– Pre-configured case, prepared for 19" components
– Case height 3 U and 6 U
Case
– Case height 2 U, 3 U, 4 U and 6 U
02009005 02004006
Extensive accessory range
02004002
ServicePLUS from page 5.4
e.g. modifications (special colours, special depths,
cut-outs in top cover, base plate or side panels)
e.g. assembly service from 1 piece
www.schroff.biz/ServicePLUS
30407004
Overview . . . 5.76
compacPRO
Complete cases
3, 6 U . . . . . . . . . . 5.78
Cases 2, 3, 4 U . . 5.79
6 U cases . . . . . . . 5.80
Accessories
Filler angle . . . . . 5.81
Cable holder . . . . 5.81
Front panel/rear
panel . . . . . . . . . . 5.82
Rear feet . . . . . . . 5.83
Edge protection. 5.83
Hood . . . . . . . . . . 5.84
Front door . . . . . 5.85
Handle . . . . . . . . 5.86
GND/earthing . . . 5.86
Feet . . . . . . . . . . 5.87
Horizontal rail . 5.88
Threaded inserts 5.90
Guide rails and
ESD clips . . . . . . . 5.92
Mounting plates . 5.94
Combined
mounting . . . . . . 5.95
Horizontal board
assembly . . . . . . 5.96
Air flow barrier . . 5.97
Dimensions . . . . . 5.98
ServicePLUS . . 5.4
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.78 Main Catalogue
E 10/2012
Desk-top cases –b
02009005
02004054
02008050
bMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Desk-top case with pre-configured components in accordance
with IEC 60297-3-101; prepared for 19" components such as
plug-in units and euroboards
For backplane mounting with insulation strips
Ventilation slots in base plate
Ventilation slots in rear panel
Delivery comprises (Kit, items 1, 2, 6, 8 fitted)
Order Information
Maximum mounting depth = D - 21 (open space: front panel - rear panel)
Note
Dimensions of case, side panel see from page 5.98
Complete cases 3 and 6 U
ServicePLUS see page 5.4
20 20
D
w
W
5
h
H
1
9
2
4
8
12
7
5
11
10
6
3
Item Qty Description
3 U 6 U
1 2 4 Side panel, Al extrusion, powder-coated, RAL 7016
2 2 2 Frame, Al die-cast, powder-coated, RAL 7016
3 1 1 Cover plate, Al, 1.5 mm, powder-coated, RAL 9006,
with GND/earthing tag
4 1 1 Base plate with 4 rows of ventilation slots, Al, 1.5 mm,
powder-coated, RAL 9006, with GND/earthing tag
5 - 2 Side plate powder-coated, RAL 9006, Al, 0.8 mm
6 4 4 Tip-up foot with anti-slip protection, PA, RAL 7016,
UL 94 V-0
7 2 2 Cover bracket, Al extrusion, anodised, cut edges plain
8 2 2 Horizontal rail, Al extrusion, with threaded insert, St,
M2.5
9 2 2 Rear horizontal rail, Al extrusion, with threaded insert,
St, M2.5 and insulation strip, PBT, UL 94 V-0
(for indirect backplane mounting)
10 - 1 Centre horizontal rail, Al extrusion, anodised,
conductive surfaces, with two threaded inserts, St,
M2.5 and two insulation strips, PBT, UL 94 V-0
11 1 1 Rear panel with 1 row of ventilation slots, Al,
anodised, 2 mm for 28, 42 and 63 HP,
2.5 mm for 84 HP
12 10/
20
10/
20
Guide rail for 160 mm board length, PBT, UL 94 V-0,
28/42 HP 10 pieces, 63/84 HP 20 pieces
13 1 1 GND/earthing kit
14 1 1 Assembly kit, also allows the fitting of a full-width front
panel
Height H Width W Depth D Usable width Part no.
w w
U mm mm HP mm
3 186 271 28 148 14575-114
3 186 331 28 148 14575-115
3 257 271 42 219 14575-134
3 257 331 42 219 14575-135
3 257 391 42 219 14575-136
3 364 271 63 326 14575-154
3 364 331 63 326 14575-155
3 364 391 63 326 14575-156
3 471 271 84 432 14575-174
3 471 331 84 432 14575-175
3 471 391 84 432 14575-176
3 471 511 84 432 14575-178
6 471 391 84 432 14575-476
6 471 451 84 432 14575-477
5.79
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
b
Desk-top case, pre-configures, for individual assembly
For backplane mounting with insulation strips
Ventilation slots in base plate
Delivery comprises (Kit, items 1 and 2 fitted)
Order Information
Cases 2, 3 and 4 U
02004005
02004054
02004053
ServicePLUS see page 5.4
20 20
D
w
W
5
h
H
3
2
4
5
1
6
Item Qty Description
1 2 Side panel, Al extrusion, powder-coated, RAL 7016
2 2 Frame, Al die-cast, powder-coated, RAL 7016
3 1 Cover plate, Al, 1.5 mm, powder-coated, RAL 9006,
with GND/earthing connection
4 1 Base plate with 4 rows of ventilation slots, Al, 1.5 mm,
powder-coated RAL 9006, with earthing connection
5 4 Case foot with anti-slip protection, PC, black
6 8 Fixing adaptor for cover plate, prefitted
7 1 Assembly kit, also allows the fitting of a full-width front
panel, two cover brackets or a rear panel
Height Usable
width
Width
W
Width
w
Height
H
Height
h
Depth
D
Part no.
U HP mm mm mm mm mm
2 42 257 219 102.6 84.4 271 14575-023
2 42 257 219 102.6 84.4 331 14575-025
2 42 257 219 102.6 84.4 391 14575-027
2 84 471 432 102.6 84.4 271 14575-063
2 84 471 432 102.6 84.4 331 14575-065
2 84 471 432 102.6 84.4 391 14575-067
3 28 186 148 147.1 129.3 271 14575-103
3 28 186 148 147.1 129.3 331 14575-105
3 42 257 219 147.1 129.3 271 14575-123
3 42 257 219 147.1 129.3 331 14575-125
3 42 257 219 147.1 129.3 391 14575-127
3 63 364 326 147.1 129.3 271 14575-143
3 63 364 326 147.1 129.3 331 14575-145
3 63 364 326 147.1 129.3 391 14575-147
3 84 471 432 147.1 129.3 271 14575-163
3 84 471 432 147.1 129.3 331 14575-165
3 84 471 432 147.1 129.3 391 14575-167
3 84 471 432 147.1 129.3 451 14575-169
3 84 471 432 147.1 129.3 511 14575-171
4 42 257 219 191.6 173.8 271 14575-223
4 42 257 219 191.6 173.8 331 14575-225
4 63 364 326 191.6 173.8 271 14575-243
4 63 364 326 191.6 173.8 331 14575-245
4 63 364 326 191.6 173.8 391 14575-247
4 84 471 432 191.6 173.8 331 14575-265
4 84 471 432 191.6 173.8 391 14575-267
4 84 471 432 191.6 173.8 451 14575-269
4 84 471 432 191.6 173.8 511 14575-271
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.80 Main Catalogue
E 10/2012
Desk-top cases –b
02004006
02004055
02004056
b
Desk-top case, pre-configured, for individual assembly
For backplane mounting with insulation strips
Ventilation slots in base plate
Delivery comprises (Kit items 1, 2 and 5 fitted)
Order Information
6 U cases
ServicePLUS see page 5.4
4
7
6
5
3
2
1
20 20
D
w
W
5
h
H
Item Qty Description
1 4 Side panel parts, Al extrusion, powder-coated,
RAL 7016, 2 x 3 U
2 2 Frame, Al die-cast, powder-coated, RAL 7016
3 1 Cover plate, Al, 1.5 mm, powder-coated, RAL 9006,
with GND/earthing tag
4 1 Base plate with 4 rows of ventilation slots, Al, 1.5 mm,
powder-coated, RAL 9006, with GND/earthing tag
5 2 Side plate, Al, 0.8 mm, powder-coated, RAL 9006
6 4 Case foot with anti-slip protection, PC, black
7 8 Fixing adaptor for cover plate, prefitted
8 1 Assembly kit also allows the fitting of a full-width front
panel, two cover brackets or a rear panel
Usable
width
Width
W
Width
w
Height
H
Height
h
Depth
D
Part no.
HP mm mm mm mm mm
63 364 326 280.5 262.9 331 14575-445
63 364 326 280.5 262.9 391 14575-447
84 471 432 280.5 262.9 271 14575-463
84 471 432 280.5 262.9 331 14575-465
84 471 432 280.5 262.9 391 14575-467
84 471 432 280.5 262.9 451 14575-469
84 471 432 280.5 262.9 511 14575-471
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.81
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
02005002
02004062
b
To cover the sides of the frame and to create a continuous front
plane with plug-in units and partial-width front panels
This filler angle is recommended when fitting horizontal rails
Delivery comprises
Order Information
Note
Fixing material is supplied with case
02908053
02908052
AccessoriesI/B Delivery comprises (kit)
Order Information
Filler angle
Item Qty Description
1 2 Filler angle, Al extrusion, anodised, cut edges plain
Height Part no.
U
2 24575-019
3 24575-119
4 24575-219
6 24575-419
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Cable holder
19 9
17
14
26,5
46
20,2
Ø 3 Ø 4,4
Ø 4,4 Ø 3
Item Qty Description
1 2 Cable bracket, ABS, UL V-94 0, RAL 7016,
detent for cables between 8 mm and 12 mm
2 1 Drilling template, two drill holes each per bracket are
needed in rear panel
3 1 Assembly kit
Description Part no.
Cable holder 24575-800
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.82 Main Catalogue
E 10/2012
Desk-top cases –b
b
Front panels and rear panels are screwed on front or rear frame
of case
Delivery comprises (kit)
Order Information
Note
Assembly kit to fix one rear and one front panel is included with
the case
Cable holder and rear feet, see from page 5.81
02004061
bDelivery comprises (kit)
Order Information
Note
Cable holder and rear feet see from page 5.81
Front panel and rear panel
02005001
Rear panel/front panel
CPA30656
Item Qty Description
1 1 Rear panel with 4 rows of ventilation slots, AI, anodised,
cut edges plain; 28, 42, 63 HP = 2 mm thick;
84 HP = 2.5 mm thick
2 1 Front panel, Al, anodised, cut edges plain, 3 mm thick
Height Width Height
H
Height
h
Width Rear panel Front panel
B b
U HP mm mm mm mm Part no. Part no.
2 42 84 66 238.7 226.3 30823-015 30823-209
2 84 84 66 452.1 439.7 30823-512 30823-215
3 28 128.4 100 167.5 155.1 30823-021 30823-254
3 42 128.4 100 238.7 226.3 30823-024 30823-257
3 63 128.4 100 345.4 333.1 30823-027 30823-224
3 84 128.4 100 452.1 439.7 30823-515 30823-260
4 42 172.9 144.5 238.7 226.3 30823-033 30823-269
4 63 172.9 144.5 345.4 333.1 30823-036 30823-227
4 84 172.9 144.5 452.1 439.7 30823-518 30823-272
6 63 261.8 233.4 345.4 333.1 30823-045 30823-230
6 84 261.8 233.4 452.1 439.7 30823-521 30823-284
Front panel/rear panel with hidden fixing
Item Qty Description
1 1 Front panel, Al, anodised, cut edges plain, 2.5 mm
2 4 Fixing bracket
Height Width Height
H
Height
h
Width Part no.
B b
U HP mm mm mm mm
2 42 84.0 66.0 238.7 226.3 24575-035
2 84 84.0 66.0 452.1 439.7 24575-075
3 28 128.4 100.0 167.5 155.1 24575-115
3 42 128.4 100.0 238.7 226.3 24575-135
3 63 128.4 100.0 345.4 333.1 24575-155
3 84 128.4 100.0 452.1 439.7 24575-175
4 42 172.9 144.5 238.7 226.3 24575-235
4 63 172.9 144.5 345.4 333.1 24575-255
4 84 172.9 144.5 452.1 439.7 24575-275
6 63 261.8 233.4 345.4 333.1 24575-455
6 84 261.8 233.4 452.1 439.7 24575-475
5.83
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
02005004
02004063
bDelivery comprises
Order Information
02005005
02908054
bDelivery comprises
Order Information
Rear foot with rubber insert
A
23 8.5
16.5
ø 4.2
Item Qty Description
1 2 Foot with rubber insert, PC, UL 94 V-0, RAL 7016
2 1 Fixing material
For case height A Part no.
U mm
3 139 24575-114
4 183.5 24575-214
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Edge protection/rear foot
Item Qty Description
1 2 Edge protection, PU foam, black
2 1 Assembly kit
For case height A B C Part no.
U mm mm mm
3 159.1 114.0 100.0 20823-675
4 203.6 159.0 144.5 20823-676
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
20,2
C
B
A
A
A-A
A
35 27
27,5
Ø 8
Ø 4,5
5
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.84 Main Catalogue
E 10/2012
Desk-top cases –b
02004065
Dimensions for modifying the rear panel
02004066
bDelivery comprises
Order Information
Rear panel, see page 5.82
02005006
02004064
Cable support
A4-512
bDelivery comprises
Order Information
Note
Cable support can only be fitted in conjunction with rear foot for
hood
To fit the hood, the rear panel and the rear foot for hood must be
mounted on the case
Rear panel, see page 5.82
Rear foot for hood see page 5.84
Rear foot for hood
B
A
D
M6
M6
45 30
B
27.55 8 x 6.1
Item Qty Description
1 2 Foot, PU foam, black, 75° shore
2 1 Fixing material
Height A B D Part no.
U mm mm mm
3 133.5 95 65 20823-668
4 177.8 139.5 95 20823-669
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Hood
41.6 41.6 10
4
A 61.5
56 10°
156.5
ø 5.5
Item Qty Description
1 1 Hood, ABS, RAL 7016, wall thickness < 4 mm,
fixing with knurled screws
2 1 Assembly kit
Height Width A Part no.
U HP mm
3 42 267 24575-136
3 63 373.5 24575-156
3 84 480 24575-176
Cable support PC, black, UL 94 V-0, PU 2 pieces 20823-674
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.85
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
02005003
02004069
Front door, hinged
a4-2265
a4-225
1) Front panel
b
Assembly of the hinge to top or bottom
With snap-on latch
Lock retrofittable
Delivery comprises (kit)
Order Information
Dimensions table
Front door, acrylic glass, hinged
Item Qty Description
1 2 Side part, Al die-cast, powder-coated, RAL 7016
2 1 Front door, PMMA, tinted blue-grey, acrylic glass, 3 mm
3 1 Snap-on latch, PC, UL 94 V-0, black
4 2 Spacer plate, Al, 3 mm, passivated
5 1 Assembly kit
Height Width Part no.
U HP
3 42 24575-137
3 63 24575-157
3 84 24575-177
Lock for front door cylinder, 2 keys, assembly parts 21100-647
Height b H h B
U TE mm mm mm
3 42 139,50 128,40 229,60
3 63 139,50 128,40 336,40
3 84 139,50 128,40 443,00
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.86 Main Catalogue
E 10/2012
Desk-top cases –b
b
With powder-coated handle bar
Handle bar adjustable in 30 degree increments by pressing
button
Load-carrying capacity 20 kg
Delivery comprises (kit)
Order Information
Dimensions
aza43284
Main Catalogue
Protective GND/earth connections in accordance with
DIN EN 50178/VDE 0160,
DIN EN 60950/VDE 0805,
DIN EN 61010-1/VDE 0411 part 1,
DIN EN 61010-1A2 /VDE 0411 part 1/A1
VDE inpection requested
Order Information
Tip-up carrying handle
02004002
02004080
68.5
180
c
4 x 30°
4 x 30°
b
a
Item Qty Description
1 1 Carrying bar, AI profile, powder-coated, RAL 7016
2 2 Lateral section of handle, Zn die-cast, powder coated,
length 180 mm
3 2 Safety insert, St, 1.5 mm, black
4 1 Fixing material incl. drilling template for side panel
For case height Width Part no.
U HP
2 42 24575-038
2 84 24575-078
3, 4 28 24575-118
3, 4 42 24575-138
3, 4 63 24575-158
3, 4 84 24575-178
Case width a b c
HP mm mm mm
28 249.32 180.32 202.72
42 320.44 251.44 273.84
63 427.12 358.12 380.52
84 533.80 464.80 487,20
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
GND/earthing kit
Description Qty/PU Part no.
GND/earthing kit, CU wire 1.5 mm2,
PVC covered, green/yellow, links side panel,
base plate, cover and rear panel
1 24575-801
5.87
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
01802075 02006050
Static load-carrying capacity 25 kg per foot
Tip-up feet can be used instead of the case feet fitted as
standard
Fixing holes provided in bottom of case
Delivery comprises (kit)
Order Information
AZA43836
02908051
Static load-carrying capacity 50 kg per foot
Tip-up feet can be used instead of the case feet fitted as
standard
Fixing holes provided in bottom of case
Order Information
1) Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 10 pieces or a multiple. Pricing is per individual item.
Plastic tip-up feet
Item Qty Description
1 4 Foot, PA, UL 94 V-0
2 4 Anti-slip protection, TPE
3 2 Tip-up device, PA, UL 94 V-0
4 1 Assembly kit
Description RAL 7016
anthracite
RAL 9006
silver
Part no. Part no.
Plastic tip-up foot 20603-002 20603-001
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Al die-cast tip-up foot
41
20
Ø7,8
15,5
Ø3,1 Ø4,6
15 20
16,6
1
Description Qty Part no.
Foot without tip-up, Al die-cast, silver 1 piece (SPQ 10)1) 10603-001
Foot with tip-up, Al die-cast, silver 1 piece (SPQ 10)1) 10603-002
Accessories
Cheesehead screw with slot M4 × 12, St, zinc-plated,
PU 100 pieces 21101-211
Hexagon nut M4, St, zinc-plated, PU 100 pieces 21100-211
Spring washer A4, St, zinc-plated, PU 100 pieces 21100-207
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.88 Main Catalogue
E 10/2012
Desk-top cases –b
Text
Mounting position horizontal/central rail
Case, 2 U Case, 3 U + 4 U
02004073 02004074
Case, 6 U Case 2 x 3 U (6 U)
02004076 02004077
Horizontal rails
02004078
H-VT
H-VT H-VT
H-VT
H-ST / H-VT / H-MZ
H-VT
H-VT H-VT
H-VT
H-ST / H-VT / H-MZ
H-VT
H-VT H-VT
ST-C
H-VT H-VT
H-VT H-VT
H-VT
H-ST / H-VT / H-MZ
H-KD H-ST / H-VT / H-MZ
H-ST / H-VT / H-MZ
H-ST
H-VT
H-MZ
5.89
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Note
Further horizontal rails, see from page 6.27
Fitting options, see page 5.88
Horizontal rails to front/centre/rear
For indirect backplane
fixing with insulation strip
For direct backplane
fixing
For direct fixing of
connectors in
accordance with
EN 60603-2 (DIN 41612)
Front horizontal rails
04400001 04400002 04400003
"heavy" "heavy" "heavy" "heavy"
Type H-ST Type H-VT Type H-MZ Type H-KD
standard long lip with Z-rail short lip
06197011 06197013 06197015 06197008
Al extrusion, anodised finish,
conductive contact surface,
with printed HP markings
Al extrusion, anodised finish,
conductive contact surface,
with printed HP markings
Al extrusion, anodised finish,
conductive contact surface,
with printed HP markings
Al extrusion, anodised finish,
conductive contact surface,
with printed HP markings
Usable length Length
HP mm 1 piece (SPQ 10)1) 1 piece (SPQ 10)1) 1 piece (SPQ 10)1) 1 piece (SPQ 10)1)
28 147.32 34560-528 34560-728 34560-928 34560-228
42 218.44 34560-542 34560-742 34560-942 34560-242
63 325.12 34560-563 34560-763 34560-963 34560-263
84 431.80 34560-584 34560-784 34560-984 34560-284
Torx countersunk screw, ,
M4 × 14, St, zinc-plated,
PU 100 pieces
24571-371 24571-371 24571-371 24571-371
Torx countersunk screw, ,
M4 × 10, St, zinc-plated,
required if guide rail is screwed
to slot 1, PU 100 pieces
– – 24571-372 24571-372
Z-rail for connector mounting
without insulation strip see page 5.91 – – –
Insulation strips see page – 5.90 – –
Threaded inserts see page 5.90 5.90 5.90 5.90
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.90 Main Catalogue
E 10/2012
Desk-top cases –b
02005050
b
For indirect backplane mounting (with insulation strip)
For 6 U compacPRO case
Delivery comprises (Kit, items 1 to 4 are pre-mounted)
Order Information
Order Information
Horizontal rail, centre, type ST-C
3
2
4
1
5
Item Qty Description
1 1 Horizontal rail, Al extrusion, anodised, contact surfaces
conductive
2 2 Adaptor plate, Al
3 2 Threaded insert, M2.5, St, zinc-plated
4 2 Countersunk screw, M4 x 14
5 4 Panhead screw, M4 x 6
Usable width Length Part no.
HP mm
63 325.1 24575-454
84 431.8 24575-474
Threaded inserts, perforated strips, insulation strips
Threaded insert Insulation strip
M2.5 M3
06103056 BZ6749
Threaded insert
required for fixing the front panel to the horizontal rail;
St, zinc-plated; Use collar screw 12.3 mm, see page
6.64
Insulation strip
for insulated mounting of backplane;
PBT UL 94 V-0, grey
Usable length Length Length
HP mm 1 piece (SPQ 10)1) 1 piece (SPQ 10)1) mm PU 10 pieces
28 146.82 34561-328 – 144.20 24560-828
42 217.94 34561-342 – 210.40 24560-842
63 324.62 34561-363 – 316.88 24560-863
84 431.30 34561-384 34561-484 428.64 24560-884
5
2
5,08
Accessories
Grub screw M2.5 x 8, PU 100 pieces 21100-276 – –
Grub screw M3 x 8, PU 100 pieces – 21100-646 –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least
the SPQ quantity or a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
5.91
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Z-rails, perforated rails
Z-rail for connectors Perforated rail
DIN EN 60603-2, DIN 41612
item 1
31-pin, DIN 41617 EN 606032, DIN 41612
item 1
BZA45849 BZA45850 BZA45848
06708063 06708051
for connector mounting on ST
horizontal rails, please order
threaded insert and screw
separately
for connector mounting on ST
horizontal rails, please order
threaded insert and screw
separately
for connector mounting on VT
horizontal rails, please order
threaded insert and screw
separately Usable length Length
HP mm 1 piece 1 piece PU 4 pieces
28 142.24 30822-033 – 20822-049
42 213.36 30822-047 – 20822-050
60 304.80 30822-065 30819-783 20822-047
84 426.70 30822-089 30819-808 20822-048
Item 3, Torx panhead screw
to fix connector to perforated rail,, M2.5 × 7,
PU 100 pieces
24560-147 24560-147 24560-147
Item 2, Torx panhead screw,
to fix perforated rails to horizontal rail, M2.5 × 10,
PU 100 pieces
24560-148 24560-148 24560-148
172,5
172,5
175,5
2
1
3
3,0
9,75
12,75
2
1
3
12,75
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.92 Main Catalogue
E 10/2012
Desk-top cases –b
Order Information
Guide rails for plug-in units and modules, one-piece,
groove width 2 mm and 2.5 mm
Assembly
- can be clipped into Al extruded
horizontal rails
- can be clipped into 1.5 mm thick
plates
Storage temperature
from -40 °C ... 130 °C
For plug-in units and frame type plug-in units
standard standard, with DIN connector fixing
06102001 06101501
up to 220 mm length, PBT, UL 94 V-0;
from 280 mm length, multi-piece, end piece PBT, UL 94 V-0,
central section Al extrusion
PBT, UL 94 V-0, red,
connector is clipped directly onto the guide rails;
for euroboards, 100 x 160 mm or 100 x 220 mm only
Board
length
Groove
width
Colour
mm mm mm PU 10 pieces 1 pair (SPQ 10)1)
70 2 red – –
70 2 grey – –
160 2 red 24560-351 64560-074
220 2 red 24560-353 64560-075
280 2 red 24560-379 –
340 2 red 24560-380 –
160 2.5 red – –
220 2.5 red – –
Dimension drawings see page 6.40 6.40
Accessories
Retention screw,
PU 100 pieces 24560-141 24560-141
ESD clip, PU 50 pieces 24560-255 24560-255
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity (SPQ); please order at least the SPQ quantity or
a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Description of accessories see from page 6.41
5.93
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Order Information
Guide rails type "accessory", one-piece,
groove width 2 mm and 2.5 mm
Assembly
- can be clipped into horizontal rails
in Al extrusion
- can be clipped into 1.5 mm thick
plate
Storage temperature
from -40 °C ... +130 °C
Guide rails type
accessory accessory, strengthened for heavy modules,
Al extrusion, silver,
robust version
06102002 06102005 06102005
up to 280 mm length, PBT, UL 94 V-0;
> 280 mm length, multi-piece,
end piece PBT, UL 94V-0,
middle section Al extrusion
PBT UL 94 V?0,
red support beam of guide rails adds to
strengthening
Al extrusion;
is screwed to horizontal rail "heavy"
with retention screws
Board
length
Groove
width
Colour
mm mm mm PU 10 pieces 1 piece (SPQ 50) 1 piece (SPQ 10)1)
100 2 red – – –
160 2 red 24560-373 64560-076 –
160 2 grey – – 34562-881
220 2 red 24560-374 64560-078 –
220 2 grey – – 34562-882
280 2 red/silver 24560-375 64560-080 34562-883
340 2 red/silver 24560-376 – 34562-884
400 2 red/silver – – 34562-885
160 2.5 silver – – 34564-881
220 2.5 silver – – 34564-882
280 2.5 silver – – 34564-883
340 2.5 silver – – 34564-884
400 2.5 silver – – 34564-885
Dimension drawings see page 6.40 6.40 6.40
Accessories
Retention screw,
PU 100 pieces 24560-141 24560-141 24560-157
ESD clip, PU 50 pieces 24560-255 24560-255 –
Board locking, red,
PU 10 pieces 24560-377 24560-377 –
Board handle, red,
PU 10 piecesdescription 24560-378 24560-378 –
Identification strips for board
handle, red, PU 1 sheet =
438 pieces
60817-228 60817-228 –
Coding see page see page 6.41 –
1) SPQ (standard pack quantity): Order number includes 1 piece, but delivery is exclusively made in standard pack quantity
(SPQ); please order at least the SPQ quantity or a multiple thereof
2) Part no. includes one packing unit (PU); delivery is exclusively made in PU
Further guide rails see page 6.35
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.94 Main Catalogue
E 10/2012
Desk-top cases –b
Main Catalogue
Order Information
Note
For installation and assembly of heavier components
The mounting plate is as wide as the case and is fixed
to the side panels
A guide rail can be mounted on the first and last slot positions
4.4" and "strengthened" guide rails cannot be used
Mounting plates
Mounting plate for fixing of heavy components
Mounting plate over full width:
mounting is onto the side panels;
mounting plate over partial width:
mounting is onto one side panel and fixing strip or
onto 2 fixing strips
Assembly strip for partial widths
06102501 05806100
Width W Board length
mm
Al, 1.5 mm; for mounting over partial width,
please order assembly strips separately
St, 2 mm, zinc-plated;
is bolted from front to rear onto the horizontal rails;
to fix mounting plates
HP W
28 146.88 160 34562-745 30840-021
28 146.88 220 34562-749 30840-033
28 146.88 280 34562-753 30840-045
28 146.88 340 34562-757 30840-057
42 217.99 160 34562-746 30840-021
42 217.99 220 34562-750 30840-033
42 217.99 280 34562-754 30840-045
42 217.99 340 34562-758 30840-057
63 324.67 160 34562-747 30840-021
63 324.67 220 34562-751 30840-033
63 324.67 280 34562-755 30840-045
63 324.67 340 34562-759 30840-057
84 431.35 160 34562-748 30840-021
84 431.35 220 34562-752 30840-033
84 431.35 280 34562-756 30840-045
84 431.35 340 34562-760 30840-057
Assembly kit for mounting plate
PU 1 kit (Torx countersunk screw M4 x 5, St,
zinc-plated, 12 pieces; screw M4 x 6, St,
zinc-plated, 10 pieces; M4 square nut, St,
zinc-plated, 10 pieces)
24560-184 –
Assembly kit for assembly strips of mounting
plate,
Torx screw M2.5 × 5, St, zinc-plated,
PU 100 pieces
M2.5 × 5, St, zinc-plated, PU 100 pieces
– 24560-146
5.95
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Subdivision of the 6 U assembly area into:
– 2 x 3 U
– 1 x 6 U
Designed to accept Euroboards (100 mm high) and double
Euroboards (233.35 mm high)
Note
Please order perforated strips for horizontal rails separately, see
page 5.90
Please order rear centre horizontal rail separately, see page
5.89
Combined mountings (6 U and 2 x 3 U one above the other)
Combined mounting: Splitting extrusion
horizontal and vertical
subdivision
(incl. front panel for stainless
steel EMC gasket)
unshielded
front panel,
6 U, 2 HP
item 6
front panel for
textile EMC gasket,
6 U, 2 HP
item 6
for combined
mounting
Item 2
05806108
bza45819 06102501 06102501 06102501
item 1: 2 front horizontal rails (H-KD),
Al extrusion, anodised;
item 2: 2 rear horizontal rails (AB),
Al extrusion, anodised;
item 3: threaded insert, St,
zinc-plated;
item 4: Zn die-cast support member;
item 6: front panel 2 HP, 6 U,
shielded; with EMC stainless steel
gasket (84:0 without items 4, 6)
Al, 2.5 mm,
front anodised,
rear iridescent green
chromated
Al, 2.5 mm, U-profile
with notch, 6 U, 2 HP
6 U, die-cast zinc;
splitting extrusion is
inserted in the grid holes
of the horizontal rail;
the splitting extrusion
can be bolted
Width pitch T1:T2
HP PU 1 kit 1 piece (SPQ 5) 1 piece (SPQ 5)1) 1 piece
20:62 24562-420
30847-472 30849-140 64560-010
40:42 24562-440
42:40 24562-442
63:19 24562-463
84:0 24562-484
Torx countersunk screw
M4 × 14, zinc-plated, PU 100 pieces
fixing splitting extrusion/horizontal rail
– – – 24560-145
Panhead screw
M2.5 × 10, St, zinc-plated, PU 100 pieces
finxing horizontal rail/splitting extrusion
– – – 24560-179
Pozidrive/slotted collar screw
M2.5 x 12.3, St, nickel-plated, PU 100 pieces – 21101-101 21101-101 –
Pozidrive/slotted collar screw
M2.5, black, zinc-plated, PU 100 pieces – 21101-102 21101-102 –
Washer
2.7 x 5 x 1, plastic PA 6, PU 100 pieces – 21101-121 21101-121 –
Textile gasket, core: foam,
sleeve: textile cladding with CuNi coating,
UL 94 V-0, PU 10 pieces
– – 21101-855 –
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.96 Main Catalogue
E 10/2012
Desk-top cases –b
Order Information
Horizontal board installation
Horizontal board installation
Board cage Front frame for EMC
shielding
Front frame, unshielded
05806092
05806091 bpa45913 bza43061
H = usable height (1 TE = 1 HP, 1 HE = 1 U)
Struts die-cast zinc;
horizontal rails front and rear;
threaded insert, St, zinc-plated;
fixing material kit;
for horizontal mounting of
double-height euroboards in 3 or
4 U high subracks/cases;
54 HP space required;
please order front frame for
EMC shielding separately
2 horizontal covers, AI 2.5 mm,
front anodised,
rear iridescent green chromated;
2 vertical trims, Al extrusion,
clear passivated;
stainless steel EMC gasket;
front frame forms the contact
between subrack and the subassemblies
Al, 2.5 mm, clear anodised;
front frame with cut-out,
clear internal width w = 266.35 mm
Height Usable
height h
HP
Other dimensions and
options
U Horizontal rail,
front
Horizontal rail,
rear
PU 1 kit PU 1 kit 1 piece
3 20 24564-117 24564-109 34564-108
3 20 24564-118 24564-109 34564-109
4 28 24564-217 24564-209 34564-208
Assembly tool, for mounting the
EMC gasket (stainless steel) – 24560-270 –
* For direct backplane mounting
273.98 =54 TE
h
H
273,98 = 54 TE
w
5.97
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Order Information
Air baffle for slots
Air baffle
without front panel
06108085
06101507
Al, 1 mm, incl. assembly kit; prevents an air short circuit in unoccupied slot positions;
is pushed into the groove of the guide rails
Depth Width Height
mm HP U 1 piece
160 4 3 34562-823
160 4 6 34562-826
160 8 3 34562-833
160 8 6 34562-836
160 12 3 34562-843
160 12 6 34562-846
220 4 3 34562-824
220 4 6 34562-827
220 8 3 34562-834
220 8 6 34562-837
220 12 3 34562-844
220 12 6 34562-847
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.98 Main Catalogue
E 10/2012
Desk-top cases –b
Text
Dimensions
Note
Side panel for 6 U case consists of two 3 U extruded side panels
Dimensions
Extruded side panel 2 U Extruded side panel 3 U
02004057 02004058
Extruded side panel 4 U Extruded side panel 6 U
02004059 02004060
A
N x 15 = B
19.5
ø 8.5
Y
Y Z
ø 4.6
4.6
M4
3 15 M4
49
Z
49
For case depth Max. mounting
depth
Dimensions
mm mm A in mm B in mm
271 250 231 15 15 = 225
331 310 291 19 15 = 285
391 370 351 23 15 = 345
451 430 411 27 15 = 405
511 490 471 31 15 = 465
A
N x 15 = B
55.5
24
19.5
77.5
88.1
ø 8.5
Y
Y Z
Z
ø 4.6
4.6
M4
3 15 M4
A
N x 15 = B
99.95
49
19.5
121.95
132.55
ø 8.5
Y
Y Z
Z
ø 4.6
4.6
M4
3 15 M4
A
N x 15 = B
144.4
19.5
166.4
177
ø 8.5
Y
Y Z
Z
ø 4.6
4.6
M4
3 15 M4
49
93
A
N x 15 = B
99.95 99.95
19.5
121.95 121.95
132.55 132.55
265.9
ø 8.5
Y
Y Z
ø 4.6
4.6
M4
3 15 M4
49
Z
49
5.99
Desk-top cases –b
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Desk-top cases –J Overview . . . . . 0
Cabinets . . . . . . 1
Wall mounted
cases . . . . . . . . 2
Accessories for
cabinets and wall
mounted cases 3
Climate control 4
Desk-top cases 5
Subracks/
19" chassis . . . 6
Front panels,
plug-in units . . 7
Systems . . . . . . 8
Power supply
units . . . . . . . . . 9
Backplanes . . 10
Connectors, front
panel component
system . . . . . . 11
Appendix . . . . 12 Downloads and further important information can be found
on the Internet under www.schroff.biz
5.100 Main Catalogue
E 10/2012
JMain Catalogue
02202003
Standards
Internal dimensions in accordance with
IEC 60297-3-100
Type of protection IP 20 in accordance with
IEC 60529
Protective ground connections in accordance with:
DIN EN 50178/VDE 0160
DIN EN 60950/VDE 0805
DIN EN 61010-1/VDE 0411 part 1
DIN EN 61010-1A2/VDE 0411 part 1/A1
Desk-top cases –J
5.101
E 10/2012
J
Case to accept 19" subracks or 19" chassis
Internal assemblies of up to 40 kg
Up to six rows of ventilation slots in the base plate for optimal air inlet
High stability
Front and rear identical, depth-symmetrical construction
With handle strip or recessed grip
Text
Case
Al die-cast frame front and rear
Top cover and base plate can be subsequently removed
Top cover and base plate fitted with hidden GND/earth
connections
Case height 3, 4, 6, 7 and 9 U
(cladding parts in steel)
Case height 9 U and 12 U
(cladding parts in aluminium)
02202004
02202005
ServicePLUS from page 5.4
e.g. modifications (cut-outs, special colours)
e.g. custom solutions (special sizes)
e.g. assembly service from 1 piece
www.schroff.biz/ServicePLUS
30407004
Overview . . . . 5.100
comptec
3, 4 U, St . . . . . . 5.102
6, 7, 9 U, St . . . . 5.103
9, 12 U, Al . . . . . 5.104
Accessories
Folding handle 5.105
Slide rails . . . . . . 5.105
Earthing kit . . . . 5.106
Assembly kit . . . . 5.106
Tip-up feet . . . . . 5.107
ServicePLUS . . 5.4
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.102 Main Catalogue
E 10/2012
Desk-top cases –J
JMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Desk-top case (pre-fitted)
Top cover, base plate and rear panel in steel
Front and rear frames in die-cast Al
Ventilation slits in base plate
Ventilation gills in rear panel
Side panel with integral handle function
Delivery comprises (kit)
Items 1, 2, 5 and 9 fitted.
Order Information
Note
Please order GND/earthing kit separately, see page 5.106
The case foot, item 10, can be replaced by a tip-up foot,
see page. 5.107
Please order slide rails separately, see page 5.105
19" case, 3 U, 4 U
02202001
CTTP0001
Front view
CTA30677
h = case foot height, HE = U, internal usable height
Side view
CTA42313
Usable width b = B - 69 mm, h = height of case foot
ServicePLUS see page 5.4
7
1
8
9
2
5
10
H h
HE
B
b
Item Qty Description
1 1 Front frame, Al die-cast, RAL 7016, with 19" grid
2 1 Rear frame, Al die-cast, RAL 7016, with 19" grid
5 2 Side panel, Al extrusion, RAL 7016
7 1 Cover plate, Al, 1 mm, RAL 9006,
with GND/earthing tag
8 1 Base plate, Al, 1 mm, RAL 9006,
with GND/earthing tag
9 1 Rear panel, St, 1 mm, RAL 9006,
with GND/earthing tag
10 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0
11 1 Assembly kit
Height H h Depth D Usable
depth d
Width B Part no.
U mm mm mm mm mm
3 153 13.0 300 276 520 10225-601
3 153 13.0 400 376 520 10225-612
3 153 13.0 500 476 520 10225-623
4 198 13.0 300 276 520 10225-602
4 198 13.0 400 376 520 10225-613
4 198 13.0 500 476 520 10225-624
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.103
Desk-top cases –J
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
J
Desk-top case (pre-fitted)
With handle shell
Top cover, base plate and rear panel in steel
Front and rear frames in die-cast Al
Ventilation slits in rear panel and base
Delivery comprises (kit)
Items 1, 2, 3, 4, 5, 6 and 9 fitted.
Order Information
Note
Please order GND/earthing kit separately, see page 5.106
The case foot, item 10, can be replaced by a tip-up foot,
see page 5.107
Please order slide rails separately, see page 5.105
Handle shell, item 6, can be replaced by a folding handle,
see page 5.105
19" case, 6 U, 7 U, 9U
02202002
CTTP0002
Front view
CTA30676
h = case foot height, HE = U, internal usable height
Side view
CTA42312
Usable depth d = D - 24 mm
ServicePLUS see page 5.4
7
1
4
10
9
3
6
5
2
8
H h
HE
B
b
Item Qty Description
1 1 Front frame, Al die-cast, RAL 7016, with 19" grid
2 1 Rear frame, Al die-cast, RAL 7016, with 19" grid
3 2 Side profile at top, Al extrusion, RAL 7016
4 2 Side profile at bottom, Al extrusion, RAL 7016
5 2 Side panel, St, 1.5 mm, RAL 9006,
with GND/earthing tag
6 2 Handle shell, PC, RAL 7016, UL 94 V-0,
load-carrying capacity: 60 kg/pair
7 1 Cover plate, St, 1 mm, RAL 9006, with GND/earthing tag
8 1 Base plate, St, 1 mm, RAL 9006, with GND/earthing tag
9 1 Rear panel, St, 1 mm, RAL 9006, with GND/earthing tag
10 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0
11 1 Assembly kit
Height H h Depth D Usable
depth d
Width B Part no.
U mm mm mm mm mm
6 286 13 300 276 520 10225-604
6 286 13 400 376 520 10225-615
6 286 13 500 476 520 10225-626
6 286 13 600 576 520 10225-637
7 331 13 400 376 520 10225-616
7 331 13 500 476 520 10225-627
7 331 13 600 576 520 10225-638
9 420 13 400 376 520 10225-618
9 420 13 500 476 520 10225-629
9 420 13 600 576 520 10225-640
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.104 Main Catalogue
E 10/2012
Desk-top cases –J
02202006
CTTP0003
Front view
CTA30679
Usable width b = B - 69 mm, h = height of case foot
Side view
CTA42314
Usable depth d = D - 24 mm
ServicePLUS see page 5.4
J
Desk-top case (pre-fitted)
With handle shell
Top cover, base plate and rear panel in Al
Front and rear frames in die-cast Al
Ventilation slots in base plate
Air vents in rear panel
Delivery comprises (kit)
Items 1, 2, 3, 4, 5, 6 and 9 fitted.
Order Information
Note
Please order GND/earthing kit separately, see page 5.106
The case foot, item 10, can be replaced by a tip-up foot,
see page 5.107
Please order slide rails separately, see page 5.105
Handle shell, item 6, can be replaced by a folding handle,
see page 5.105
19" cases 9 and 12 U, aluminium
9
3
6
5
2
4
10
7
1
8
H h
HE
B
b
Item Qty Description
1 1 Front frame, Al die-cast, RAL 7016, with 19" grid
2 1 Rear frame, Al die-cast, RAL 7016, with 19" grid
3 2 Side profile at top, Al extrusion, RAL 7016
4 2 Side profile at bottom, Al extrusion, RAL 7016
5 2 Side panel, Al, 1.5 mm, RAL 9006,
with GND/earthing tag
6 2 Handle shell, PC, RAL 7016, UL 94 V-0,
load-carrying capacity: 60 kg/pair
7 1 Cover plate, Al, 1 mm, RAL 9006, with GND/earthing tag
8 1 Base plate, Al, 1 mm, RAL 9006, with GND/earthing tag
9 1 Rear panel, Al, 1 mm, RAL 9006, with GND/earthing tag
10 4 Case foot with anti-slip protection, PC, black,
UL 94 V-0
11 1 Assembly kit
Height H h Depth D Usable
depth d
Width B Part no.
U mm mm mm mm mm
9 420 13 400 376 520 10225-667
9 420 13 500 476 520 10225-682
9 420 13 600 576 520 10225-693
12 553 13 400 376 520 10225-670
12 553 13 500 476 520 10225-685
12 553 13 600 576 520 10225-696
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.105
Desk-top cases –J
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2013
CTTP0006
J
Folding handles can be used instead of the pre-fitted
handle shells
Load-carrying capacity: 50 kg/pair
Delivery comprises (kit)
Order Information
J
Slide rails are suitable as support for 19" subracks and
19" chassis
Delivery comprises
Order Information
Note
2 slide rails are required per subrack or 19" chassis
Slide rail cannot be used for shielded 19" subracks; special slide
rails available on request
Folding handle
Item Qty Description
1 2 Folding handle, AI die-cast, RAL 7016
2 1 Assembly kit
Description Part no.
Folding handle 20225-439
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Slide rails
CTTP0005
Item Qty Description
1 1 Slide rail, Al extrusion, anodised, cut edges plain,
static load-carrying capacity 10 kg
For case depth Part no.
mm
300 30225-089
400 30225-090
500 30225-091
600 30225-092
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.106 Main Catalogue
E 10/2012
Desk-top cases –J
aza43284
J
The GND/earthing kit allows VDE compliant earthing of cases
in accordance with:
EN 50178/VDE 0160
EN 60950/VDE 0805
EN 61010-1/VDE 0411 part 1
EN 61010-1A2/VDE 0411 part 1/A
VDE tested
Delivery comprises (kit)
Order Information
SC128XXX
06108055
J
For fitting subracks or 19" chassis in a comptec case
For fixing 19" front panels
Delivery comprises
Order Information
GND/earthing kit
Item Qty Description
1 1 GND/earthing kit, Cu wire, 1.5 mm2, PVC sheathing,
green/yellow, connects side panels, cover, base plate
and rear panel
Description Up to 4 U bigger than 4 U
Part no. Part no.
GND/earthing kit for cases with
steel covers 21100-490 21100-448
GND/earthing kit for cases with
aluminium covers – 21100-347
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
19" fixing
Item Description
1 Screw M6 × 16, zinc-plated with Pozidrive
2 Cage nut M6, zinc-plated
3 Plastic washer, ABS, black
Description Part no.
PU = 8 × screw, washer, nut 21100-435
PU = 50 each of M6 screw, washer and cage nut 21101-809
PU = 100 each of M6 screw, washer and cage nut 21101-810
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.107
Desk-top cases –J
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
01802075
J
Static load-carrying capacity 25 kg per foot
Tip-up feet can be used instead of the case feet fitted as
standard
Fixing holes provided in bottom of case
Delivery comprises (kit)
Order Information
AZA43836
J
Static load-carrying capacity 50 kg per foot
Tip-up feet can be used instead of the case feet fitted as
standard
Fixing holes provided in bottom of case
Order Information
1) Part no. comprises 1 piece;
delivery is in standard pack quantity (SPQ):
please order a minimum of 10 feet or a multiple
Plastic tip-up feet
Item Qty Description
1 4 Foot, PA, UL 94 V-0
2 4 Anti-slip protection, TPE
3 2 Tip-up device, PA, UL 94 V-0
4 1 Assembly kit
Description RAL 7016
anthracite
RAL 9006
silver
Part no. Part no.
Plastic tip-up foot 20603-002 20603-001
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Tip-up foot in die-cast Al
Description Qty Part no.
Foot with tip-up, Al die-cast, silver 1 piece (SPQ 10)1) 10603-002
Foot without tip-up, Al die-cast, silver 1 piece (SPQ 10)1) 10603-001
Cheesehead screw with slot M4 × 12, St, zinc-plated,
PU 100 pieces 21101-211
Hexagon nut M4, St, zinc-plated, PU 100 pieces 21100-211
Spring washer A4, St, zinc-plated, PU 100 pieces 21100-207
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.108 Main Catalogue
E 10/2012
Desk-top cases – Accessories
AccessoriesMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Front handles see page 5.108
Strap handles see page 5.111
Tip-up carrying handles, see page 5.112
Folding handles see page 5.113
Tray handle see page 5.114
Feet, see page 5.115
Screwdriver (Torx) 5.117
Measuring tape, see page 5.117
BZA42318
AccessoriesMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Static load-carrying capacity 10 kg/pair
Bolted from rear
Delivery comprises (kit)
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ):
Please order at least 10 pieces or a multiple.
Pricing is per individual item.
BZA42330
Accessories
Static load-carrying capacity 30 kg/pair
Bolted from rear
Delivery comprises (kit)
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ):
Please order at least 10 front handles or a multiple.
Pricing is per individual item.
Contents
06002052 05895003 02992004
aza43835 02992003 32506001
Front handle, one-piece, width 7 mm
Item Qty Description
1 1 Front handle, Al extrusion, anodised
A E Part no.
mm mm
48 40 10501-001
98 90 10501-002
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Front handle, one-piece, width 9 mm
Item Qty Description
1 1 Front handle, Al extrusion, anodised
Description Part no.
Front handle 10501-003
Pozidrive countersunk screw 14 × 10, zinc-plated,
PU 100 pieces 21101-381
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.109
Desk-top cases – Accessories
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Main Catalogue
Static load-carrying capacity 30 kg/pair
Bolted from front
Delivery comprises (kit)
Order Information
1 U
BZA42316
2 U ... 6 U
BZA42327
Main Catalogue
Static load-carrying capacity 30 kg/pair
Bolted from rear
Delivery comprises
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 10 front handles or a multiple. Pricing is per individual
item.
Note
Please order panhead screws separately
Front handle, one-piece, width 10 mm
02905050
H = 1 U
02905051
H ≥ 2 U
40
h
H
10
10
Ø 4,4
8,4 Ø
4
8
Item Qty Description
1 2 Front handle, Al extrusion, anodised
2 1 Assembly kit
Height H Height H Height h Part no.
U mm mm
1 40 28 20860-256
2 69 53 20860-257
3 113 97.5 20860-258
4 157.45 141.9 20860-259
5 201.9 186.4 20860-260
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Front handle, one-piece, width 12.2 mm
Item Qty Description
1 1 Front handle, AI extrusion, anodised
A E clear anodised black anodised
mm mm Part no. Part no.
41 25 10501-116 –
57.5 44.5 10501-016 –
69 55 10501-004 10501-025
102 88 10501-005 10501-026
132 120 10501-006 10501-027
146.4 133.4 10501-018 –
194 180 10501-007 10501-028
249 235 10501-008 10501-029
Panhead pozidrive screw self-locking, M5 × 12,
zinc-plated, PU 100 pieces 21100-788
Torx countersunk screw M5 × 12, zinc-plated,
100 pieces 24560-183
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.110 Main Catalogue
E 10/2012
Desk-top cases – Accessories
A3-227
Static load-carrying capacity 10 kg/pair
In three parts, middle section in Al extrusion, end pieces in glass
fibre reinforced plastic
Bolts on from front
Delivery comprises (kit)
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ):
Please order at least 10 front handles or a multiple.
Pricing is per individual item.
Note
Please order panhead screws separately
02908050
Item 1: front handle; item 2: end piece
Accessories Order Information
Front handle, multi-piece, width 12 mm
Item Qty Description
1 1 Front handle, Al extrusion, anodised
2 2 End piece, PA, black
A E Part no.
mm mm
87.5 73.5 10502-050
102.0 88 10502-057
134.0 120 10502-059
194.0 180 10502-063
249 235 10502-065
Panhead screw pozidrive self-locking, M5 × 12,
zinc-plated, PU 100 pieces 21100-788
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Front handle, multi-piece, width 12 mm
1000
40
12
1
2
Description Qty/PU Part no.
Item 1, front handle, Al extrusion,
anodised,1 m long 1 30502-051
Item 2, end piece, PA, black,
2 pieces each required 1 60502-003
Panhead pozidrive screw self-locking, M5 × 12,
zinc-plated, PU 100 pieces 21100-788
5.111
Desk-top cases – Accessories
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
05895003
02902050
Accessories
Static load-carrying capacity 20 kg
Delivery comprises (kit)
Order Information
02992006
Length 240 mm/170 mm
BZA42368
Accessories
Static load-carrying capacity 20 kg
Delivery comprises (kit)
Order Information
Strap handle, width 25 mm
Item Qty Description
1 1 Band, spring steel,
handle, flexible plastic, grey, RAL 7016
2 2 Cover, grey, RAL 7016
3 1 Assembly kit
Length Part no.
mm
230 20850-249
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Strap handle, width 22 mm
Item Qty Description
1 1 Band, spring steel, plastic-coated, black
2 2 Cover cap, St, chrome-plated
3 1 Assembly kit
Length Part no.
mm
170 10504-002
240 10504-003
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.112 Main Catalogue
E 10/2012
Desk-top cases – Accessories
AccessoriesMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
Static load-carrying capacity 25 kg
(with handle bars of 450 mm length)
02992002
A4-2361
Accessories
Handle can be adjusted in 30° grid by pressing button
Delivery comprises (kit)
Order Information
02992001
A4-2367
Accessories Delivery comprises (kit)
Order Information
Tip-up carrying handle in separate parts
02992002 02992001
Lateral handle parts
Item Qty Description
1 2 Lateral parts, die-cast zinc, painted (chrome decor)
2 2 Safety inserts, St, 1.5 mm, black
3 2 Adaptor/locking brackets
4 1 Assembly kit
Length Part no.
mm
180 10502-297
250 10502-296
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Handle bar
Item Qty Description
1 1 Handle bar, AI, black anodised
Length Part no.
mm
1000 30502-191
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.113
Desk-top cases – Accessories
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
Accessories
Static load-carrying capacity 30 kg/pair
For case ingress protection to IP 40
Locks in folded and opened positions
Equal cut-out for fitting in front of or behind case wall
Delivery comprises (kit)
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 10 pieces or a multiple. Pricing is per individual item.
02992005
Folding plastic handle
A2-123
Accessories
Static load-carrying capacity 20 kg/pair
For case ingress protection to IP 40
Locks in folded and opened positions
External mounting only
Delivery comprises (kit)
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 10 pieces or a multiple. Pricing is per individual item.
Folding metal handle
02992004
A4-2369
A4-2370
Item Qty Description
1 1 Handle, Al die-cast, RAL 9005, black
2 1 Handle shell, Al die-cast, RAL 9006, silver
Description Part no.
Folding metal handle 20505-032
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Folding plastic handle
Item Qty Description
1 1 Handle, PA, light grey
2 1 Handle shell, PA, dark grey
3 1 Assembly kit
Description Part no.
Folding plastic handle 10505-014
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.114 Main Catalogue
E 10/2012
Desk-top cases – Accessories
02992003
A3-0670a
Size 1, case cut-out 49 × 104 mm
A3-0670b
Size 2, case cut-out 73 × 171 mm
Accessories
Static load-carrying capacity 30 kg/pair
Delivery comprises
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ):
Please order a minimum of 10 tray handles or a multiple.
Pricing is per individual item.
Note
Please order spring clips for fixing to the case separately
Required:
– for handle size 1: 2 spring clips
– for handle size 2: 3 spring clips
Tray handle
Item Qty Description
1 1 Handle shell, PC, UL 94 V-0
Colour Size 1 for material
thickness 1.5 mm
Size 1 for material
thickness 2.5 mm
Size 2 for material
thickness 1.5 mm
Part no. Part no. Part no.
greybrown
60229-002 60229-001 60225-015
black 60229-004 60229-003 60225-012
RAL 7016 – – 20225-167
Spring clip PU 20 pieces 21100-089
Spring clip PU 100 pieces 21100-093
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.115
Desk-top cases – Accessories
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
A4-330
Accessories Delivery comprises
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 50 pieces or a multiple. Pricing is per individual item.
Note
Foot is inserted into mounting hole and then fixed by pressing
in the expanding pin
A4-2315
Accessories Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 50 pieces or a multiple. Pricing is per individual item.
Plastic foot
Pos. Menge Beschreibung
1 1 Plastic foot, PC, UL 94 V-0, black
Description Dimensions Hole
diameter
Part no.
A B C
mm mm mm mm
For material thickness 1 ... 3 16 7.2 4 7 60224-009
For material thickness 1.5 ... 3 21 15 7 7.7 60224-011
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Rubber foot
Dimensions Material Colour Qty Part no.
Height Hole diameter
mm mm
10 25 Rubber grey 1 60200-001
15 26 Rubber grey 1 60200-027
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
5.116 Main Catalogue
E 10/2012
Desk-top cases – Accessories
Accessories
Static load-carrying capacity 25 kg per foot
Can be used instead of standard feet
Fixing holes provided in bottom of case
Order Information
Delivery is exclusively in Standard Pack Quantity (SPQ):
Please order a minimum of 10 feet or a multiple.
Pricing is per individual item.
Note
Please order assembly kit separately.
0180207502906050
Accessories
Static load-carrying capacity 25 kg per foot
Can be used instead of standard feet
Fixing holes provided in bottom of case
Delivery comprises (kit)
Order Information
Plastic tip-up foot
AZA43835
02912050
78,4
47
20
38,4
13,9
Ø3,1 Ø4,8
13,3
15,8
14
1
5
Description Qty/PU grey black
Part no. Part no.
Foot with tip-up, PA, UL 94 HB 1 10603-023 10603-025
Foot without tip-up, PA, UL 94 HB 1 10603-024 10603-026
Pozidrive flathead screw M4 × 10, St,
zinc-plated, PU 100 pieces 21100-513
Hexagon nut M4, St, zinc-plated, PU 100 pieces 21100-211
Spring washer A4, St, zinc-plated, PU 100 pieces 21100-207
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Plastic tip-up feet
Item Qty Description
1 4 Foot, PA, UL 94 V-0
2 4 Anti-slip protection, TPE
3 2 Tip-up device, PA, UL 94 V-0
4 1 Assembly kit
Description RAL 7016
anthracite
RAL 9006
silver
Part no. Part no.
Plastic tip-up foot 20603-002 20603-001
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
5.117
Desk-top cases – Accessories
Part number in bold face type: ready for despatch within 2 working days
Part number in normal type: ready for despatch within 10 working days
Main Catalogue
E 10/2012
AZA43836
Accessories
Static load-carrying capacity 50 kg per foot
Can be used instead of standard feet
Fixing holes provided in bottom of case
Order Information
1) Delivery is exclusively in Standard Pack Quantity (SPQ): Please
order at least 10 pieces or a multiple. Pricing is per individual item.
Retention partsMain CataloguePart number in bold face type: ready for despatch within 2 working daysPart number in normal type: ready for despatch within 10 working days
T8: For mounting guide rails to horizontal rails
T20: For mounting horizontal rails and rear hoods to side panels,
cover plates, support brackets and front handles
Order Information
32506001
Main Catalogue
Measuring tape with cm, U-, HP-division (lenght 2 m)
Plastic cases, metal measuring tape with automatic collection
Order Information
Al die-cast tip-up foot
Description Qty Part no.
Foot without tip-up, Al die-cast, silver 1 piece (SPQ 10)1) 10603-001
Foot with tip-up, Al die-cast, silver 1 piece (SPQ 10)1) 10603-002
Accessories
Cheesehead screw with slot M4 × 12, St, zinc-plated,
PU 100 pieces 21101-211
Hexagon nut M4, St, zinc-plated, PU 100 pieces 21100-211
Spring washer A4, St, zinc-plated, PU 100 pieces 21100-207
Screwdriver
AZA45925
Torx screwdriver Qty/PU Part no.
pieces
M2.5 T 8 Torx 1 64560-026
M4 T 20 Torx 1 64560-027
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Measuring tape
Description Qty/PU Part no.
Measuring tape 1 89009-001
For further information www.schroff.biz/oneclick
oneClick search code = Part no.
Schroff gmbh, Langenalber Strass e 96–100, D-75334 Straubenhardt WWW.PENTA IREQUIPMENTPROTECT ION.COM
39601-641 © 2012 Pentair Equipment Protection
Electronics Packaging www.schroff.biz UK 04/2006 9.3
Power supplies– 19" compatible – AC/DC switched-mode power supply
11396002
DIJM0084
Connector pin-out
19" compatible – AC/DC switched-mode power supply
Wide range mains/line input voltage (from 90 – 264 VAC and
130 – 340 VDC)
Single output voltage
Redundancy operation with integrated decoupling diode
Active Current Share Bus (CSB)
Signalling: Output voltage OK
Efficiency up to 80%
Delivery comprises
Order Information
Note
Please order front panel separately
Output data at Ta= 0 ... 50 °C
Further accessories, see page 9.21
Single, 50 W ecopower
Pin Connection
4 Output + V1
6 Output + V1
8 Sense line + V1
10 Sense line 0 V1
12 Output 0 V1
14 Output 0 V1
16 -
18 -
20 -
22 CSB
24 Output OK
26 -
28 L
30 N
32 PE
Qty Description
1 19" compatible power supply
height 3 U
width A: 6 HP
depth 171.93 mm (160 mm deep boards)
connector H15M (assembled)
keying/coding peg (assembled)
Voltage Current Power Description Order no.
V A W
5 9 45 SEK 105 13100-043
12 4.2 51 SEK 112 13100-044
15 3.4 51 SEK 115 13100-041
24 2.1 51 SEK 124 13100-045
48 1.1 53 SEK 148 13100-046
Front panel 6 HP, Al, front anodised, rear colourless
chromated, with vertical slots for EMC contact strips,
incl. assembly kit, 1 piece
21006-943
EMC contact strips Stainless steel, 2 pieces per front
panel necessary, PU 10 pieces
21101-705
Connector H 15 F FASTON connection, 1 piece 69001-733
Coding PU (keying/coding peg, 1 piece, keying/coding pin
2 pieces)
60800-123
For further information www.schroff.biz/oneclick
oneClick code = Order no.
6
1
2
3
4
5
7
TE = HP = F
Aufbau / Exploded diagram / Montage
ELA44928
Maßbilder / Dimensions / Dimensions
DIJM0001
Fühlerleitungbetrieb (Last)
Die Fühlerleitungen werden polrichtig
direkt an der Last angeschlossen. Die
Leitungen müssen verdrillt oder abgeschirmt
sein (Schirm mit PE verbinden).
Für optimale Störspannungsunterdrückung
sollte negative Ausgangsleitung
mit Schutzleiter (PE, Pin
32) verbunden werden.
Fühlerleitungbetrieb (lokal)
Die Senseanschlüsse werden polrichtig
direkt am Power Supply gebrückt.
Betrieb ohne Fühlerleitung
Fühlerleitungsanschlüsse sind intern
mit einem Widerstand verbunden;
ohne Fühlerleitungsanschluß wird die
Ausgangsspannung ca. auf Nennspannung
geregelt.
Operation with sense lines
(load)
The sense lines are connected directly
to the load with the correct polarity.
The lines must be twisted or screened
(connect screen with PE). For optimum
interference suppression, the negative
output should be connected to the protective
GND/earth (PE, pin 32).
Operation with sense lines
(local)
The sense connections are bridged
directly to the power supply with the
correct polarity.
Operation without sense lines
Sense connections are connected
internally with a resistor; without sense
connection the output voltage is
approx. the same as the nominal
voltage.
Utilisation avec lignes de
compensation (charge)
Les lignes de compensation doivent être
raccordées directement à la charge en
respectant la correspondance des
polarités. Elles doivent être torsadées ou
blindées (raccorder le blindage au
conducteur de protection PE). Pour
obtenir une neutralisation optimale des
tensions parasites , la ligne négative
devrait être reliée au conducteur de
protection (PE, broche 32).
Utilisation avec lignes de
compensation (local)
Les lignes de compensation doivent être
pontées directement en sortie
d´alimentation en respectant la
correspondance des polarités.
Utilisation sans lignes de
compensation
Les raccordements des lignes de
compensation sont pontées dans
l´alimentation à l´aide d´une résistance.
Lorsque les lignes de compensation ne
sont pas raccordées en externe, la
tension de sortie est régulée
approximativement à la valeur nominale.
Pos.
Item
Repère
Benennung
Description
Désignation
Bestell-Nr.
Order No.
Référence
1
Netzgerät, Teileinsatz 3 HE nach DIN 41494, Teil 5
Power Supply, Plug-in unit 3 U to DIN 41494, part 5
Alimentation, Module enfichable 3 U, selon DIN 41494 partie 5
2
Steckverbinder Messerleiste
Male connector
Connecteur mâle
H 15 M, DIN 41612
3
Codierleiste, Kammleiste
Coding strip, Female strip
Détrompeur, Peigne
4
Steckverbinder-Gegenstück
Female connector
Connecteur femelle
69001-733
5
Codierleisten-Gegenstück
Coding strip
Réceptacle détrompeur
60800-123
6
HF Frontplatte (seitlich geschlitzt) mit Befestigungsmaterial
Front panel with slots incl. assembly parts
Face avant HF (avec fentes latérales) et pièces de fixation
21006-943
7
Sicherung
Fuse
Fusible secteur
Power
LED grün, versorgt durch die Ausgangsspannung
LED green, supplied by the ouput voltage
LED verte, alimentée par tension de sortie
D V
Einstellung der Ausgangsspannung V
Adjustment of the output voltages V
Réglage tensions de sortie V
Prinzipschaltbild, Steckerbelegung / Circuit diagram, Connector pin-out / Schéma de principe, Brochage
DIJM0002
PSU
+ Sense
- Sense
- V
+ V
12,14
4,6
8
10
R
C
+
PSU
+ Sense
- Sense
- V
+ V
12,14
4,6
8
10
R
DIJM0057
Uup Udown Hyst. typ.
SEK 105 4,6 ±0,2 V 4,5 ±0,2 V 60 mV
SEK 112 11,0 ±0,2 V 10,9 ±0,2 V 200 mV
SEK 115 13,9 ±0,2 V 13,7 ±0,2 V 200 mV
SEK 124 23 ±0,3 V 22,8 ±0,3 V 300 mV
SEK 148 46,9 ±0,4 V 45,5 ±0,4 V 600 mV
Rpullup
SEK 105 470 h
SEK 112 1k6 h
SEK 115 1k6 h
SEK 124 4k7 h
SEK 148 20k h
+
-
+
-
PSU 2
PSU 1
+
-
RL
V1
V1
Leistungsbegrenzung
Zum Schutz des Gerätes müssen die
maximalen Ausgangsströme mit steigender
Temperatur reduziert werden.
Das Derating setzt bei 50 °C ein.
Strombegrenzung
Die Geräte sind für Dauerkurzschluß
ausgelegt. Der Ausgangsstrom wird
gemäß einer I/U-Kennlinie begrenzt.
Wird die Ausgangsspannung vom
Anwender erhöht, muß er sicherstellen,
daß der maximale Ausgangstrom um
den gleichen Faktor verringert wird.
Das Netzgerät kann sonst zerstört werden.
Beispiel: UDC + 10 % => IDC - 10 %.
Überspannungsschutz
Der OVP ist werkseitig eingestellt
(siehe technische Daten). Beim
Ansprechen des Überspannungschutzes
wird der Regler abgeschaltet.
Wenn die Überspannung nicht mehr
ansteht schaltet sich das Netzgerät
wieder ein.
Serienschaltung
Sehen Sie am Ausgang externe Inversdioden
vor. Summenspannung von
200 V nicht überschreiten. Spricht bei
einem Gerät die Strombegrenzung an,
muß die Last kurz abgetrennt werden.
Bei Serienschaltung können am Ausgang
berührungsgefährliche Spannungen
auftreten:
SELV-Spannung nur bis 60 VDC.
Parallelschaltung
Zur Leistungserhöhung oder Redundanzbetrieb
werden die Ausgänge der
Netzgeräte parallel verbunden. Es
erfolgt eine geregelte Lastaufteilung
wenn der Current Share Bus der Netzgeräte
miteinander verbunden ist (Pin
22, max. 12 Geräte parallelschaltbar,
max. Ausgangsleistung ca. 0.9*Pmax.).
Damit im Redundanzbetrieb alle Netzgeräte
arbeiten ist eine Grundlast von
0,1*Pmax erforderlich.
Die Entkoppeldiode ist eingebaut.
Netzspannung
Die Power Supplies haben einen Weitbereichseingang
(90 VAC – 264 VAC,
130 VDC – 340 VDC).
Output OK Signal
Das Output OK Signal zeigt an, ob die
Ausgangsspannung vorhanden ist
(siehe Diagramm Output OK Signal).
Der Pullup Widerstand ist eingebaut.
Output power Limiting
In order to protect the unit the maximum
output currents reduced as the
temperature increases. Derating is
activated at 50 °C.
Current limiting
The power supply features short-circuit
protection. The output current is limited
according to an I/V curve. If the output
voltage is increased by the user, the
maximum output current must be
reduced by the same factor. The power
supply may otherwise be destroyed.
Example: VDC + 10 % => IDC - 10 %.
Over-voltage protection
The OVP is pre-set (see technical data).
When the over-voltage protection is
triggered the regulator is switched off.
The unit is automatically reset when
there is no longer any over-voltage.
Series operation
External inverse diodes should be used
at the output. Do not exceed a total
voltage of 200 V. If the current limiting is
triggered in a unit the load should be
removed briefly. Dangerous voltages
may occur at the output with series
operation:
SELV voltage only up to 60 VDC.
Parallel operation
The unit outputs are set up for parallel
operation to increase the output power
or for redundancy. The load share
control operates if the Current Share
Buses of the unit are linked together(Pin
22 max 12 units). max. output
performance approx. 0.9*Pmax. So that
all power supplies work in redundancy
mode, a basic load of 0.1*Pmax is
required.
The decoupling diode is built in.
Mains/line voltage
The power supplies have a broad
range input (90 VAC – 264 VAC, 130 VDC
– 340 VDC).
Output OK Signal
The Output OK Signal is on if there is an
existing output voltage(see diagram
Output OK Signal).
The pullup resistor is build in.
Limitation de puissance
Afin de protéger l’alimentation, les
courants de sortie max. diminuent á
mesure que la température augmente.
Le derating démarre à 50 °C.
Limitation de courant
Les alimentations sont conçues pour
pouvoir supporter un court-circuit
permanent. Le courant des sortie est
régulé selon une courbe caractéristique
I/V. Si l’utilisateur accroît la tension de
sortie, il doit veiller à réduire le courant
maximal de sortie dans la même
proportion, sinon l’alimentation risque
d’être détériorée.
Exemple: UDC + 10 % => IDC - 10 %.
Protection aux surtensions
L’OVP est prérèglé en usine (voir
Caractéristiques Techniques). Dans le
cas du déclenchement de la protection
aux surtensions, l’alimentation est
arrêtée. Lorsque la surtension disparait,
l’alimentation se remet en marche.
Branchement en série
Il faut prévoir des diodes de protection
contre les inversions de polarité. Ne pas
dépasser la tension totale de 200 V.
Lorsque l’un des appareils déclenche en
limitation de courant, il faut déconnecter la
charge pendant un court moment. Lors
d’une mise en série, des tensions
dangereuse peuvent apparaître à la
sortie:
tension SELV uniquement jusqu’à 60 VDC.
Branchement en parallèle
Pour accroitre la puissance ou pour une
utilisation en redondance des
alimentations les sorties seront reliées en
parallèle. Une répartition autonome de la
charge est assurée lorsque les sorties
Current Share Bus des alimentations sont
reliées entre elles (broche 22, max. 12
alimentations en parallèle, tension max.
de sortie env. 0.9*Pmax). Pour qu’en mode
de redondance toutes les alimentations
soient en service il faut une charge
minimale de 0,1*Pmax.
La diode de découplage est intégrée.
Adaptation de la tension secteur
L´alimentation dispose d´une plage
d´entrée secteur étendue. Elle s´adapte
automatiquement à la tension secteur
(90 VAC – 264 VAC, 130 VDC – 340 VDC).
Signal Output OK
Le signal Output OK indique la présence
ou non de la tension de sortie (voir
schéma Signal Output OK). La résistante
Pullup est intégrée.
Strombegrenzung
Current limiting
Limitation de courant
Parallelschaltung (CSB)
Parallel operation
Branchement en parallèle
Serienschaltung
Series operation
Branchement en série
V [ % ]
110 I [ % ]
100
+
+ +
I
-
-
PSU 2
PSU 1
+
-
-
PSU 3
RL
CSB
1
I 2
I n
Output OK Signal
Garantiebedingungen
Leistungsdauer
Für dieses Produkt leisten wir 2 Jahre Garantie.
Der Anspruch beginnt mit dem Tage der
Auslieferung.
Umfang der Mängelbeseitigung
Innerhalb der Garantiezeit beseitigen wir kostenlos
alle Funktionsfehler am Produkt, die auf mangelhafte
Ausführung bzw. Materialfehler zurückzuführen sind.
Weitergehende Ansprüche – insbesondere für
Folgeschäden – sind ausgeschlossen.
Garantieausschluß
Schäden und Funktionsstörungen verursacht durch
Nichtbeachten unserer Bedienungsanleitung sowie
Fall, Stoß, Verschmutzung oder sonstige unsachgemäße
Behandlung fallen nicht unter die Garantieleistung.
Die Garantie erlischt, wenn das Produkt von
unbefugter Seite geöffnet wurde. Eingriffe erfolgt
sind oder die Seriennummer am Produkt verändert
oder unkenntlich gemacht wurde.
Abwicklung des Garantieanspruches
Das vorliegende Produkt wurde sorgfältig geprüft
und eingestellt.
Bei berechtigten Beanstandungen schicken Sie uns
das Produkt bitte zurück. Zur Erhaltung Ihres
Garantieanspruches beachten Sie bitte folgendes:
Legen Sie eine möglichst genaue Beschreibung
des Defektes bei.
Das Produkt ist im Original-Karton oder gleichwertiger
Verpackung einzusenden und zwar
versichert und portofrei.
Warranty conditions
Duration
This product has a warranty of 2 years.
The warranty begins on the day of delivery
Cover of defects
Within the warranty period Schroff will repair free of
charge any faulty functioning of the product
resulting from faulty design or defective material.
All other claims under the warranty are excluded, in
particular consequential damage.
Warranty exclusion
The warranty does not cover damage or functional
defects caused by non-adherence to the
Company´s operating instructions or such caused
by dropping, knocking, contamination or other
untoward handling. The warranty is invalidated if
the product is opened by unauthorized personnel,
tampered with or the serial number on the product
has been changed or rendered illegible.
Claims under warranty
This product has been carefully checked. If you
have a valid claim, please return the product to
SCHROFF. In order to make a claim under the
warranty, ensure that the following is carried out:
Include a detailed description of the fault.
The product should be returned in the original
carton or similar packaging, insured and
post paid.
Garantie
Garantie contractuelle
Les conditions d‘applications de la garantie, et en
particulier la durée, l‘étendue et les cas d‘exclusion,
figurent dans nos conditions générales de ventes,
paragraphe 11 „Garantie contractuelle“.
Application de la garantie
Cette alimentation a été soigneusement contrôlée en
usine. En cas de réclamations, veuillez nous la
retourner accompagnée d‘une description la plus
précise possible du défaut constaté, et d‘une copie du
bon de livraison ou de la facture. Le produit doit nous
être retourné dans son emballage d‘origine port
assuré et payé.
Schroff n‘assume aucune responsabilité pour des
appareils non assurés et endommagés pendant le
transport.
Technische Daten Technical Data Caractéristiques techniques SEK 105 SEK 112 SEK 115 SEK 124 SEK 148
Eingangsgrößen Input parameters Valeurs d’entée 13100 - 043 - 044 - 041 - 045 - 046
Netzspannung Nennwerte VAC Mains/line voltage Nominal values VAC Tension secteur Valeurs nominales VAC 100 – 240 VAC
Arbeitsbereiche Operating ranges Plage de fonctionnement
90 – 264 VAC
128 – 370 VDC 4)
Netznennstrom bei 90 VAC / 187 VAC Mains/line current at 90 VAC / 187 VAC Courant nominal pour 90 VAC / 187 VAC 1,3 / 0,6 A
Netzfrequenzbereich Mains/line frequency Fréquence secteur 48 – 62 Hz
Leistungsfaktor cos j Performance factor cos j Facteur de puissance cos j 0,6
Wirkungsgrad typabhängig Efficiency, depending on type Rendement selon le type 69 – 80%
Einschaltstrom IP ( bei 230 VAC ) Current at switch-on IP ( at 230 VAC ) Courant d’appel IP ( pour 230 VAC ) < 20 A
Ableitstrom Leakage current Courant de fuite £ 500 μA
Ausgangsgrößen Output parameters Valeurs de sortie
Ausgangsleistung [ W ] Output [ W ] Puissance de sortie [ W ] 45 51 53
Ausgangsspannung
D V [ V ]
werkseitig 2) Output voltage D V
[ V ]
pre-set 2) Tension de sortie D V
[ V ]
Réglage usine 2) 5 12 15 24 48
Einstellbereich 1) Adjustment range 1) Plage de réglage 1) 4,2 – 6 11 –
13,5
13,5 –
16,5
21 –
25,5
43 – 50
Ausgangsstrom
(bei 90 - 264 VAC) [ A ]
0 ... 50 °C Output current
(at 90 - 264 VAC ) [ A ]
0 ... 50 °C Courant de sortie
(et 90 - 264 VAC ) [ A ]
0 ... 50 °C 9,0 4,2 3,4 2,1 1,1
70 °C 70 °C 70 °C 6,0 2,9 2,4 1,5 0,8
Kurzschlußstrom [ A ] Short-circuit current [ A ] Courant de court-circuit [ A ] < 11 < 6 < 4,5 < 3 < 2
Überspannungsschutz OVP(schaltet Netzgerät
ab), automatisch wiederkehrend,
werkseitig fest eingestellt [ V ]
Over-voltage protection pre-set (switches
power supply off) with automatic reset [ V ]
Protection surtensions OVP (coupe l’alimentation),
remise en marche automatique [ V ]
6 ±0,3 14 ±0,5 17 ±0,5 26 ± 0,5 52 ± 2
Restwelligkeit bei
[mVPP]
100 Hz Residual ripple at
[mVPP]
100 Hz Ondulation résiduelle
[mVPP]
100 Hz < 20 < 100 < 100 < 100 < 150
Taktfrequenz
(100 kHz)
Frequency
(100 kHz)
à la fréquence de
découpage (100 kHz)
< 40 < 50 < 50 < 50 < 60
Störspannung (BW: 100 MHz) [mVPP] Interference voltage (BW: 100 MHz) [mVPP] Tension parasite (BP: 100 MHz) [mVPP] < 100 < 200 < 200 < 200 < 200
Lastausregelung, statisch
( Lastwechsel 0 - 100 % ) [mV]
Load control, static
( load change 0 - 100 % ) [mV]
Régulation en charge statique
( variation charge 0 - 100 % ) [mV]
< 50 < 50 < 50 < 100 < 100
Netzausregelung 90 – 264 V [mV] Mains voltage change 90 – 264 V [mV] Régulation secteur 90 – 264 V [mV] < 10 < 25 < 25 < 100 < 100
Temperaturkoeffizient Temperature coefficient Coefficient de température - 0,015 %/K
CSB und Ausgang über Diode entkoppelt CSB and output via decoupling diode CSB et Sortie découpling par diode eingebaut / built in / monté
Dynamische Regelabweichungen
(Lastwechsel: 50 ... 100% mit 100 Hz;
dI/dt = 0,135 A/μs)
Dynamic control deviations
(Load change: 50 ... 100% at 100 Hz;
dI/dt = 0.135 A/μs)
Valeurs dynamiques de sortie
(Variation de charge: 50 ... 100% avec 100 Hz;
dI/dt = 0,135 A/μs)
Gesamtausregelzeit,
Toleranz 0,1% x V1 Nenn [ms]
Total control time,
Tolerance 0,1 % x V1 nom [ms]
Temps de réponse globall,
Tolérance 0,1% x V1 Nenn [ms]
< 1,5
Überschwingweite und Unterschwingweite
[ mV ]
Overshoot and undershoot [ mV ] Amplitude de dépassement et amplitude
négative [ mV ]
< 500 < 250 < 300 < 500
Schutz- und
Überwachungseinrichtungen
Protection and
control features
Dispositifs de protection
et surveillance
Einschaltzeit Soft start delay Temps de montée < 0,8 s
Netzsicherung, High Breaking träge Mains/line fuse, high breaking slow Fusible secteur, high breaking slow 4 A/250 VAC, 5 x 20 mm, DIN EN60127-2/V4)
Netzausfallüberbrückung bei
VAC = 187 VAC und 100 % Last
Mains/line failure buffer at
VAC = 187 VAC and 100 % load
Pontage microcoupures secteur avec
VAC = 187 VAC et charge 100 %
> 30 ms
Fernfühler kompensiert Remote control compensated Compensation max. 0,5 V
Strombegrenzungskennlinie Current limiting Limitation de courant U / I , V / I
Signalisierung „Ausgangsspannung ok“ “Output OK“ Signal Signalisation «tension de sortie OK» Output OK, low active, internal pull-up
max. 55 V / 50 mA
High Pegel [ V ] High Level [ V ] High signal [ V ] 5 12 15 24 48
Prüf- und Umweltbedingungen Test and environmental specifications Conditions de test et d’environnement
Klimaprüfung nach Climatic test to Epreuve climatique selon IEC 68-2-38
Schock- und Vibrationstest gemäß
Beschleunigung 2 g
Shock and vibration tests in accordance
Acceleration 2 g
Tests de chocs et vibrations selon
Accélération 2 g
EN 60068-2-6
Höhe 3 HE / Tiefe 160 mm / Breite [TE] Hight 3 U / depth 160mm / Width [HP] Hauteur 3 U / Prof. 160 mm, Largeur [F] 6
Gewicht (Masse) Weight Poids (masse) 0,55 kg
CE Störaussendung CE Transmission Compatibilité
électromagnétique
CE
Emission EN 50081-1
EN 55011class B, EN 55022 class B
Störfestigkeit,
Schärfeklasse 3
Susceptability,
degree of severity 3
CEM Immunité,
sévérity 3
EN 50082-2, EN 61000-4-2,EN 61000-4-3,
EN 61000-4-4 ,EN 61000-4-5, EN 61000-4-6
Sicherheit,
Schutzklasse 1
Safety,
Protection class 1
Sécurité,
Classe de protection 1
EN 60950 ( ERG )
Hochspannungsprüfung
nach EN 60950
Eingang-Ausgang High voltage test
to EN 60950
input-output Tests haute-tension
selon EN 60950
Entrée-Sortie 4,3 kVDC 3)
Eingang-PE input-PE Entrée-Masse 2,2 kVDC 3)
Ausgang-PE output-PE Sortie-Masse 0,7 kVDC 3)
UL 1950 UL 1950 UL 1950 No. E 153809
Netzgerät wartungsfrei Power supply, maintenance-free Alimentation sans entretien Ja / yes / oui
Kühlart Cooling Refroidissement Convection
Umgebungstemperatur Betrieb / Lagerung Ambient temperature Operation / Storage Température ambiante Service / Stockage 0 ... 70 °C / -20 ... + 85 °C
MTBF bei Vollast, TU = 40 °C MTBF at full load, Ta = 40 °C MTBF à pleine charge, Ta = 40 °C 500000 h
1) Bei Erhöhung der Ausgangsspannung DV
Strombegrenzung beachten.
2) Toleranz ± 100 mV.
3) ACHTUNG: Hochspannungsprüfung wurde durchgeführt.
Bei erneuter Prüfung darf max. 80% der Prüfspannung
angelegt werden. Bei unsachgemäßer
Prüfung (z.B. manche Bauteile müssen kurzgeschlossen
werden) kann das Gerät zerstört werden.
4) Für den DC-Betrieb ist eine geeignete Sicherung vorzuschalten,
zB. von Wickmann 19356 T 3,15 A
1) When increasing the output voltage DV check the
current limiting.
2) Tolerance ± 100 mV.
3) CAUTION: The high voltage test has been carried
out. Any repeat test must be carried out at max. 80%
of the test voltage. If the test is carried out incorrectly
(e.g. some components have to be short-circuited),
the unit may be destroyed.
4) For DC-operation you must put an additional fuse in
front, e.g. from Wickmann 19356 T 3,15 A
1) Lorsqu’on augmente la tension de sortie DV
il faut tenir compte de la limitation de courant.
2) Tolérance ± 100 mV.
3) ATTENTION: Les tests haute-tension ont été effectués.
En cas de répétition de ces tests, uniquement 80 % de
la tension d’essai peut être appliquée. En cas de tests
non appropriés (certains composants doivent être mis
en court-circuit), l’appareil peut être détruit.
5) L’utilisation d’un fusible adéquate est obligatoire pour le
fonctionnement en DC, par ex. Wickmann 19356
T 3,15 A
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Attention !
Observer les prescriptions et
règles de sécurité!
Avant la mise en service, lire la
notice d’utilisation.
Raccorder le conducteur de terre
(PE).
Si une protection contre les
contacts directs est nécessaire,
l’alimentation doit obligatoirement
être montée dans un boîtier.
L’appareil ne peut être ouvert que
par des personnes qualifiés!
La protection anti-feu est à
assurer par une enveloppe
indépendante de l’alimentation.
Consignes de sécurité
L’alimentation doit être munie d’une
face avant appropriée, afin d’éviter
tout contact avec des parties sous
tension.
Afin d’éviter les couplages parasites,
les câblages secteur et secondaires
doivent cheminer séparément.
Precautions!
Please read the safety
instructions carefully!
Please read these operating
instructions carefully before
switching on.
Connect the PE conductor before
operating.
The power supply should be
mounted in a case to avoid risk
of direct contact with live parts.
The power supply unit should be
opened by authorized service
personnel only!
Ensure correct installation for
conformity to fire regulations.
Safety instructions
To avoid interference, the mains/line
and output connections must be
physically separated from one
another.
Vorsicht!
Sicherheitsvorschriften,
-bestimmungen und -hinweise
beachten!
Vor dem Betrieb Bedienungsanleitung
lesen.
Vor dem Betrieb PE-Leiter
anschließen.
Direkter Berührschutz erfordert
unbedingt den Einbau in Gehäuse,
die das Berühren spannungsführender
Teile ausschließt.
Das Geräte darf nur von
Fachpersonal geöffnet werden!
Brandschutz ist durch das
übergeordnete Gefäßsystem
sicherzustellen
Sicherheitshinweise
Nur mit geeigneter Frontplatte
betreiben, um die Berührung
spannungsführender Teile zu
verhindern!
Um Störungseinkopplungen zu
vermeiden müssen Netz-/ und
Ausgangsleitungen getrennt verlegt
werden.
Jede Unterbrechung der Schutzleitung
innerhalb oder außerhalb
des Gerätes oder die Abkoppelung
des Schutzleiteranschlusses kann
das Gerät gefährlich machen;
absichtliche Unterbrechung ist
untersagt!
Vor dem Sicherungswechsel
Gerät vom Netz trennen.
Die Geräte sind werkseitig nur
einpolig abgesichert. Bei Netzanschluß
mit polverwechselbaren
Steckvorrichtungen ist eine zweite
Sicherung vorzusehen.
Durch Serienschaltung (Reihenschaltung)
mehrerer Stromversorgungen
können an den Ausgängen
lebensgefährliche Spannungen
(ab 60 VDC) auftreten
(SELV-Spannung nur bis 60 VDC)!
Beim Einbau des Gerätes Sicherheitsmaßnahmen
nach EN 60950
beachten!
Allgemeine Sicherheitsvorschriften
und -bestimmungen beachten!
Operate only with suitable front
panel to avoid contact with voltagebearing
parts!
The power supply should be
mounted in a case to avoid risk
of direct contact with live parts!
Do not disconnect ground/earth
inside or outside the power supply.
The company cannot be held
reponsible for unsafe operating
conditions resulting from deliberate
disconnection!
Disconnect the mains/line voltage
from the unit before changing the
fuse.
The units are fused for live only.
A second fuse should be used for
the neutral connection where the
polarity of the connectors can be
reversed.
When operating several power
supplies in series, dangerous
voltages may occur at the output
terminals; SELV voltage must be
limited to 60 VDC!
When mounting the unit read the
safety instructions to EN 60950!
Pour obtenir une protection contre
les contacts directs, l’appareil doit
obligatoirement être monté dans un
boîtier excluant toute possibilité de
contact avec des parties sous
tension.
Toute interruption de la ligne de
protection à l’intérieur ou à
l’extérieur de l’alimentation, de
même qu’une déconnexion de cette
ligne, peuvent rendre l’appareil
dangereux. Tout acte intentionnel
dans ce sens est strictement interdit.
Avant de remplacer le fusible,
couper l’appareil du secteur
L’alimentation ne dispose que d’une
protection unipolaire. Si le dispositif
de connexion au secteur est de
nature â favoriser une inversion
polaire, il faut prévoir un second
fusible.
Le couplage en série de plusieurs
alimentations peut occasionner des
tensions mortelles aux sorties ( à
partir de 60 VDC). Limite de tension
SELV = 60 VDC max.
Lors du montage de l’alimentation,
respecter les mesures de sécurité
prévues par la norme EN 60950.
Observer les prescriptions et règles
de sécurité générales.
EN 60950
Bedienungsanleitung
Operating instructions
Notice d’utilisation
SEK single (SEK 1xx)
(13100-041 – 13100-046)
Vor Inbetriebnahme diese Bedienungsanleitung sorgfältig lesen! Entstehen
durch Nichtbeachtung Schäden, erlöschen die Garantieansprüche.
Diese Dokumentation wurde mit größter Sorgfalt erstellt. Dennoch können
wir für die vollständige Richtigkeit keine Garantie übernehmen.
Please read these operating instructions carefully before applying power.
The warranty is subject to correct input voltages being applied. Repairs or
modifications made by anyone other than SCHROFF will invalidate the warranty.
This documentation has been compiled with the utmost care. We
cannot however guarantee its correctness in every respect.
Avant la mise en service, veuillez lire attentivement la présente notice
d'utilisation. Tout dommage dû à l'inobservation de nos instructions n'est
pas couvert par notre garantie. La présente documentation a été réalisée
avec le plus grand soin mais nous déclinons toute responsabilité en cas
d'erreur ou d'omission.
SCHROFF GMBH www.schroff.biz D/GB/F 11/06
Langenalber Straße 96-100, D-75334 Straubenhardt, Tel. +49 (7082) 794-0, Fax +49 (7082) 794-200
73972-035 Rev. 002
11396002
Basic-type Digital Temperature Controller E5CN/E5CN-U 1
Basic-type Digital Temperature Controller
E5CN/E5CN-U (48 x 48 mm)
New 48 x 48-mm Basic Temperature
Controller with Enhanced Functions and
Performance. Improved Indication
Accuracy and Preventive Maintenance
Function.
• Indication Accuracy
Thermocouple input: ±0.3% of PV (previous models: ±0.5%)
Pt input: ±0.2% of PV (previous models: ±0.5%)
Analog input: ±0.2% FS (previous models: ±0.5%)
• New E5CN-U Models (Plug-in Models) with analog inputs and
current outputs.
• A PV/SV-status display function can be set to alternate between
displaying the PV or SV and the status of the Temperature
Controller (auto/manual, RUN/STOP and alarms).
• Preventive maintenance for relays using a Control Output ON/OFF Counter.
Main I/O Functions
48 × 48-mm
E5CN
48 × 48-mm
E5CN-U
Refer to Safety Precautions on page 18.
Event Inputs
• None
• Two
Sensor Inputs
• Universal thermocouple/Pt inputs
(Models with temperature inputs)
• Analog current/voltage inputs
(Models with analog inputs)
Indication Accuracy
• Thermocouple input: ±0.3% of PV
• Pt input: ±0.2% of PV
• Analog input: ±0.2% FS
Sampling Period and control update
• 250 ms
Control Output 1
• Relay output
• Voltage output (for driving SSR)
• Current output
• Long-life relay output (hybrid)
Control Output 2
• None
• Voltage output
(for driving SSR)
2 Auxiliary Outputs
2 line Display: PV and SV 4-digit, 11 segment display
E5CN
• Auto/manual switching
• Temperature Controller status display
• Simple program function
• Control output ON/OFF count alarm
• PV change rate alarm
• Models optional with RS-485
communications
This data sheet is provided as a guideline for selecting products. Be sure to refer to the following user manuals for application precautions
and other information required for operation before attempting to use the product.
E5CN/E5AN/E5EN Digital Temperature Controllers User's Manual Basic Type (Cat. No. H156)
E5CN/E5AN/E5EN Digital Temperature Controllers Communications Manual Basic Type (Cat. No. H158)
2 Basic-type Digital Temperature Controller E5CN/E5CN-U
Lineup
Note: All models can be used for Heating, Cooling and Heating & Cooling control
Model Number Structure
Model Number Legend
Controllers
1. Control Output 1
R: Relay output
Q: Voltage output (for driving SSR)
C: Current output
Y: Long-life relay output (hybrid) ✽1
2. Auxiliary Outputs ✽2
2: Two outputs
3. Option
M: Option Unit can be mounted.
4. Input Type
T: Universal thermocouple/platinum resistance thermometer
L: Analog current/voltage input
5. Power Supply Voltage
Blank: 100 to 240 VAC
D: 24 VAC/VDC
6. Case Color
Blank: Black
W: Silver (contact your local sales for more information)
7. Terminal Cover
-500: With terminal cover
Option Units
1. Applicable Controller
CN: E5CN
2. Function 1
Blank: None
Q: Control output 2 (voltage for driving SSR)
P: Power supply for sensor
3. Function 2
Blank: None
H: Heater burnout/SSR failure/Heater overcurrent detection (CT1)
HH: Heater burnout/SSR failure/Heater overcurrent detection
(For 3-phase heater applications, 2x CT)
B: Two event inputs
03: RS-485 communications
H03: Heater burnout/SSR failure/Heater overcurrent detection
(CT1) + RS-485 communications
HB: Heater burnout/SSR failure/Heater overcurrent detection
(CT1) + Two event inputs
HH03: Heater burnout/SSR failure/Heater overcurrent detection
(For 3-phase heater applications, 2x CT)
4. Version
N2: Applicable only to models produced after January 2008
(Box marked with N6)
Note: Not all combinations of function 1 and function 2 specifications are possible for Option Units (E53-CN@@N2).
✽1. Always connect an AC load to a long-life relay output. The output will not turn OFF if a DC load is connected because a triac is used for
switching the circuit. For details, check the conditions in Ratings.
✽2. Auxiliary outputs are contact outputs that can be used to output alarms, control or results of logic operations.
Plug-in
Terminal block
E5CN
Basic Type
Analog input
Temperature input
2 control outputs
1 control output
2 control outputs
1 control output
2 auxiliary outputs
2 auxiliary outputs
2 auxiliary outputs
2 auxiliary outputs
Analog input
Temperature input
1 control output
1 control output 2 auxiliary outputs
2 auxiliary outputs
1 2 3 4 5 6 7
E5CN-@2M@@-@-500
1 2 3 4
E53-CN@@N2
Basic-type Digital Temperature Controller E5CN/E5CN-U 3
Ordering Information
Controllers with Terminal Blocks
Note: add power supply voltage to model to complete ordering code (ie. E5CN-R2MT-500 AC100-240 or E5CN-R2MTD-500 AC/DC24)
Option Units
One of the following Option Units can be mounted to provide the E5CN with additional functions.
Note: Option Units cannot be used for plug-in models.
These Option Units are applicable only to models produced after January 2008 (Box marked with N6).
Size Case color Power supply
voltage Input type Auxiliary outputs Control output 1 Model
1/16 DIN
48 × 48 × 78
(W × H × D)
Black
100 to 240 VAC
Thermocouple or
Resistance
thermometer
2
Relay output E5CN-R2MT-500
Voltage output (for driving SSR) E5CN-Q2MT-500
Current output E5CN-C2MT-500
Long-life relay output (hybrid) E5CN-Y2MT-500
24 VAC/VDC
Thermocouple or
Resistance
thermometer
2
Relay output E5CN-R2MTD-500
Voltage output (for driving SSR) E5CN-Q2MTD-500
Current output E5CN-C2MTD-500
100 to 240 VAC Analog
(current/voltage) 2
Relay output E5CN-R2ML-500
Voltage output (for driving SSR) E5CN-Q2ML-500
Current output E5CN-C2ML-500
Long-life relay output (hybrid) E5CN-Y2ML-500
24 VAC/VDC Analog
(current/voltage) 2
Relay output E5CN-R2MLD-500
Voltage output (for driving SSR) E5CN-Q2MLD-500
Current output E5CN-C2MLD-500
Functions Model
Event inputs E53-CNBN2
Event inputs Control output 2
(Voltage for driving SSR) E53-CNQBN2
Event inputs Heater burnout/SSR failure/Heater
overcurrent detection E53-CNHBN2
Event inputs External power supply for
ES1B E53-CNPBN2
Communications
RS-485 E53-CN03N2
Communications
RS-485
Control output 2
(Voltage for driving SSR) E53-CNQ03N2
Communications
RS-485
Heater burnout/SSR failure/Heater
overcurrent detection E53-CNH03N2
Communications
RS-485
3-phase heater burnout/SSR failure/
Heater overcurrent detection E53-CNHH03N2
Communications
RS-485
External power supply for
ES1B E53-CNP03N2
Heater burnout/SSR failure/Heater
overcurrent detection
Control output 2
(Voltage for driving SSR) E53-CNQHN2
3-phase heater burnout/SSR failure/
Heater overcurrent detection
Control output 2
(Voltage for driving SSR) E53-CNQHHN2
Heater burnout/SSR failure/Heater
overcurrent detection
External power supply for
ES1B E53-CNPHN2
4 Basic-type Digital Temperature Controller E5CN/E5CN-U
Model Number Structure
Model Number Legend (Plug-in-type Controllers)
1. Output Type
R: Relay output
Q: Voltage output (for driving SSR)
C: Current output
2. Number of Alarms
2: Two alarms
3. Input Type
T: Universal thermocouple/platinum resistance thermometer
L: Analog Input
4. Plug-in type
U: Plug-in type
Ordering Information
Plug-in-type Controllers
Note: add power supply voltage to model to complete ordering code. (ie. E5CN-R2TU AC100-240 or E5CN-R2TDU AC/DC24)
1 2 3 4
E5CN-@2@U
Size Case color Power supply voltage Input type Auxiliary outputs Control output 1 Model
1/16 DIN Black
100 to 240 VAC
Thermocouple
or resistance
thermometer
2
Relay output E5CN-R2TU
Voltage output (for driving SSR) E5CN-Q2TU
Current output E5CN-C2TU
Analog
(current/voltage) 2
Relay output E5CN-R2LU
Voltage output (for driving SSR) E5CN-Q2LU
Current output E5CN-C2LU
24 VAC/VDC
Thermocouple
or resistance
thermometer
2
Relay output E5CN-R2TDU
Voltage output (for driving SSR) E5CN-Q2TDU
Current output E5CN-C2TDU
Basic-type Digital Temperature Controller E5CN/E5CN-U 5
Accessories (Order Separately)
USB-Serial Conversion Cable
Terminal Cover
Note: The Terminal Cover comes with the E5CN-@@@-500 models.
Waterproof Packing
Note: The Waterproof Packing is included with the Controller only for
models with terminal blocks.
Current Transformers (CTs)
Adapter
Note: Use this Adapter when the panel has been previously prepared
for the E5B@ (72x72 mm panel cut-out).
Sockets (for Plug-in Models)
CX-Thermo Support Software
Model
E58-CIFQ1
Connectable models Terminal block models
Model E53-COV17
Model
Y92S-29
Hole diameter Model
5.8 dia. E54-CT1
12.0 dia. E54-CT3
Connectable models Model
Terminal block models Y92F-45
Type Model
Front-connecting Socket P2CF-11
Front-connecting Socket with Finger Protection P2CF-11-E
Back-connecting Socket P3GA-11
Terminal Cover for Back-connecting socket with
Finger Protection Y92A-48G
Model
EST2-2C-MV4
6 Basic-type Digital Temperature Controller E5CN/E5CN-U
Specifications
Ratings
Power supply voltage No D in model number: 100 to 240 VAC, 50/60 Hz
D in model number: 24 VAC, 50/60 Hz; 24 VDC
Operating voltage range 85% to 110% of rated supply voltage
Power
consumption
E5CN 100 to 240 VAC: 7.5 VA (max.) (E5CN-R2T at 100 VAC: 3.0 VA)
24 VAC/VDC: 5 VA/3 W (max.) (E5CN-R2TD at 24 VAC: 2.7 VA)
E5CN-U 100 to 240 VAC: 6 VA (max.)
24 VAC/VDC: 3 VA/2 W (max.) (models with current output: 4 VA/2 W)
Sensor input
Models with temperature inputs
Thermocouple: K, J, T, E, L, U, N, R, S, B, W, or PL II
Platinum resistance thermometer: Pt100 or JPt100
Infrared temperature sensor: 10 to 70° C, 60 to 120°C, 115 to 165° C, or 140 to 260°C
Voltage input: 0 to 50 mV
Models with analog inputs
Current input: 4 to 20 mA or 0 to 20 mA
Voltage input: 1 to 5 V, 0 to 5 V, or 0 to 10 V
Input impedance Current input: 150 Ω max., Voltage input: 1 MΩ min. (Use a 1:1 connection when connecting the ES2-HB.)
Control method ON/OFF control or 2-PID control (with auto-tuning)
Control
outputs
Relay output
E5CN SPST-NO, 250 VAC, 3 A (resistive load), electrical life: 100,000 operations, minimum applicable
load: 5 V, 10 mA
E5CN-U SPDT, 250 VAC, 3 A (resistive load), electrical life: 100,000 operations, minimum applicable load:
5 V, 10 mA
Voltage output
(for driving SSR)
E5CN
E5CN-U
Output voltage: 12 VDC ±15% (PNP), max. load current: 21 mA, with short-circuit protection
circuit
Current output E5CN 4 to 20 mA DC/0 to 20 mA DC, load: 600 Ω max., resolution: approx. 10,000
Long-life relay
output E5CN
SPST-NO, 250 VAC, 3 A (resistive load), electrical life: 1,000,000 operations, load power supply
voltage: 75 to 250 VAC (DC loads cannot be connected.), minimum applicable load: 5 V, 10 mA,
leakage current: 5 mA max. (250 VAC, 60 Hz)
Auxiliary
outputs
Number of outputs 2
Output specifications
Relay output: SPST-NO, 250 VAC, 3 A (resistive load), electrical life: 100,000 operations, minimum
applicable load: 5 V, 10 mA
Event
inputs
Number of inputs 2
External contact
input specifications
Contact input: ON: 1 kΩ max., OFF: 100 kΩ min.
Non-contact input: ON: Residual voltage: 1.5 V max., OFF: Leakage current: 0.1 mA max.
Current flow: Approx. 7 mA per contact
External power supply for ES1B 12 VDC ±10%, 20 mA, short-circuit protection circuit provided
Setting method Digital setting using front panel keys
Indication method 11-segment digital display and individual indicators (7-segment display emulation also possible)
Character height: PV: 11 mm, SV: 6.5 mm
Multi SP Up to four set points (SP0 to SP3) can be saved and selected using event inputs, key operations, or serial
communications.
Bank switching Not supported
Other functions
Manual output, heating/cooling control, loop burnout alarm, SP ramp, other alarm functions, heater burnout
detection, 40% AT, 100% AT, MV limiter, input digital filter, self-tuning, temperature input shift, run/stop,
protection functions, control output ON/OFF counter, extraction of square root, MV change rate limit, logic
operations, PV/SV status display, simple program, automatic cooling coefficient adjustment
Ambient operating temperature −10 to 55°C (with no condensation or icing), for 3-year warranty: −10 to 50°C
Ambient operating humidity 25% to 85%
Storage temperature −25 to 65°C (with no condensation or icing)
Basic-type Digital Temperature Controller E5CN/E5CN-U 7
Input Ranges
Thermocouple/Platinum Resistance Thermometer (Universal Inputs)
Models with Analog Inputs
Shaded settings are the default settings.
Input
Type
Platinum resistance
thermometer Thermocouple Infrared temperature
sensor
Analog
input
Name Pt100 JPt100 K J T E L U N R S B W PL
II
10 to
70°C
60 to
120
°C
115
to
165
°C
140
to
260
°C
0 to
50 mV
Temperature range (° C)
2300
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
−100.0
−200.0
2300
Usable
in the
following
ranges
by
scaling:
−1999 to
9999 or
−199.9 to
999.9
1800
1700 1700
1300 1300 1300
850 850 850
600
500.0 500.0 500.0
400.0 400 400.0 400 400.0
260
120 165
100.0 100.0 90
100
0.0 0.0 0 0 0 0 0 0 0 0
−20.0 −100 −20.0 −100
−200 −199.9 −199.9 −200 −200 −199.9 −200 −200 −199.9 −200
Setting
number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 24 25 19 20 21 22 23
Shaded settings are the default settings.
The applicable standards for the input types are as follows:
K, J, T, E, N, R, S, B: JIS C 1602-1995, IEC 584-1
L: Fe-CuNi, DIN 43710-1985
U: Cu-CuNi, DIN 43710-1985
W: W5Re/W26Re, ASTM E988-1990
JPt100: JIS C 1604-1989, JIS C 1606-1989
Pt100: JIS C 1604-1997, IEC 751
PL II: According to Platinel II electromotive force charts from BASF (previously
Engelhard)
Input Type Current Voltage
Input specification 4 to 20mA 0 to 20 mA 1 to 5 V 0 to 5 V 0 to 10 V
Setting range Usable in the following ranges by scaling:
−1999 to 9999, −199.9 to 999.9, −19.99 to 99.99 or −1.999 to 9.999
Setting number 0 1 2 3 4
8 Basic-type Digital Temperature Controller E5CN/E5CN-U
Alarm Outputs
Each alarm can be independently set to one of the following 13 alarm types. The default is 2: Upper limit.
Auxiliary outputs are allocated for alarms. ON delays and OFF delays (0 to 999 s) can also be specified.
Note: For models with heater burnout, SSR failure, and heater overcurrent detection, alarm 1 will be an OR output of the alarm selected from the
following alarm types and the alarms for heater burnout, SSR failure, and heater overcurrent. To output only a heater burnout alarm, SSR
failure alarm, and heater overcurrent alarm for alarm 1, set the alarm type to 0 (i.e., no alarm function).
✽1. With set values 1, 4 and 5, the upper and lower limit values can
be set independently for each alarm type, and are expressed as
“L” and “H.”
✽2. Set value: 1, Upper- and lower-limit alarm
✽3. Set value: 4, Upper- and lower-limit range
✽4. Set value: 5, Upper- and lower-limit with standby sequence
For Upper- and Lower-Limit Alarm Described Above
• Case 1 and 2
Always OFF when the upper-limit and lower-limit hysteresis
overlaps.
• Case 3: Always OFF
✽5. Set value: 5, Upper- and lower-limit with standby sequence
Always OFF when the upper-limit and lower-limit hysteresis
overlaps.
Set
value Alarm type
Alarm output operation
When X is
positive
When X is
negative
0 Alarm function
OFF Output OFF
1
✽1
Upper- and lowerlimit
✽2
2 Upper limit
3 Lower limit
4
✽1
Upper- and lowerlimit
range ✽3
5
✽1
Upper- and lowerlimit
with standby
sequence
✽4
6 Upper-limit with
standby sequence
7 Lower-limit with
standby sequence
8 Absolute-value
upper-limit
9 Absolute-value
lower-limit
10
Absolute-value
upper-limit with
standby sequence
11
Absolute-value
lower-limit with
standby sequence
12 LBA
(for alarm 1 only) ---
13 PV change rate
alarm ---
ON
OFF
SP
L H
SP
X
ON
OFF
SP
X
ON
OFF
SP
ON X
OFF
SP
ON X
OFF
SP
L H
ON
OFF
SP
L H
ON
OFF
✽5
SP
X
ON
OFF
SP
X
ON
OFF
SP
X
ON
OFF
SP
ON X
OFF
0
ON X
OFF
0
X
ON
OFF
0
X
ON
OFF
0
X
ON
OFF
0
X
ON
OFF
0
ON X
OFF
0
X
ON
OFF
0
X
ON
OFF
L H
H < 0, L > 0
⏐H⏐ < ⏐L⏐
SP
Case 1
L H
H > 0, L < 0
⏐H⏐ > ⏐L⏐
SP
Case 2
H L
H < 0, L < 0
SP
H L
H < 0, L > 0
SP ⏐H⏐ ≥ ⏐L⏐
H L
H > 0, L < 0
SP ⏐H⏐ ≤ ⏐L⏐
Case 3 (Always ON)
L H SP
Case 1
SP L H
Case 2
H SP L
L
L
H SP
SPH
Case 3 (Always OFF)
H < 0, L > 0
⏐H⏐ < ⏐L⏐
H > 0, L < 0
⏐H⏐ > ⏐L⏐
H < 0, L < 0
H < 0, L > 0
⏐H⏐ ≥ ⏐L⏐
H > 0, L < 0
⏐H⏐ ≤ ⏐L⏐
Basic-type Digital Temperature Controller E5CN/E5CN-U 9
Characteristics
✽1. The indication accuracy of K thermocouples in the −200 to 1300° C range, T and N thermocouples at a temperature of −100° C max., and U and L
thermocouples at any temperatures is ±2° C ±1 digit max. The indication accuracy of the B thermocouple at a temperature of 400° C max. is not specified.
The indication accuracy of B thermocouples in the 400 to 800° C range is ±3° C max. The indication accuracy of the R and S thermocouples at a
temperature of 200° C max. is ±3° C ±1 digit max. The indication accuracy of W thermocouples is ±0.3 of PV or ±3° C, whichever is greater, ±1 digit max.
The indication accuracy of PL II thermocouples is ±0.3 of PV or ±2° C, whichever is greater, ± 1 digit max.
✽2. Ambient temperature: −10° C to 23° C to 55° C, Voltage range: −15% to 10% of rated voltage
✽3. K thermocouple at −100°C max.: ±10° max.
✽4. “EU” stands for Engineering Unit and is used as the unit after scaling. For a temperature sensor, the EU is ° C or ° F.
✽5. When robust tuning (RT) is ON, the differential time is 0.0 to 999.9 (in units of 0.1 s).
✽6. External communications (RS-485) and cable communications for the Setup Tool can be used at the same time.
✽7. The E5CN-U plug-in model is certified for UL listing only when used together with the OMRON P2CF-11 Socket.
Indication accuracy
Thermocouple: ✽1
Terminal block models (E5CN): (±0.3% of indicated value or ±1° C, whichever is greater) ±1 digit max.
Plug-in models (E5CN-U): (±1% of indicated value or ±2° C, whichever is greater) ±1 digit max.
Platinum resistance thermometer input:
Terminal block models (E5CN) and plug-in models (E5CN-U): (±0.2% of indicated value or ±0.8° C, whichever is greater)
±1 digit max.
Analog input:
Terminal block models (E5CN) and plug-in models (E5CN-U): ±0.2% FS ±1 digit max.
CT input:
Terminal block models (E5CN): ±5% FS ±1 digit max.
Influence of temperature ✽2
Thermocouple input (R, S, B, W, PL II):
Terminal block models (E5CN): (±1% of PV or ±10° C, whichever is greater) ±1 digit max.
Plug-in models (E5CN-U): (±2% of PV or ±10° C, whichever is greater) ±1 digit max.
Other thermocouple input: ✽3
Terminal block models (E5CN): (±1% of PV or ±4° C, whichever is greater) ±1 digit max.
Plug-in models (E5CN-U): (±2% of PV or ±4° C, whichever is greater) ±1 digit max.
Platinum resistance thermometer input:
Terminal block models (E5CN) and plug-in models (E5CN-U):
(±1% of PV or ±2°C, whichever is greater) ±1 digit max.
Analog input:
Terminal block models (E5CN) and plug-in models (E5CN-U): (±1%FS) ±1 digit max.
Influence of voltage ✽2
Input sampling period 250 ms
Hysteresis
Models with thermocouple/platinum resistance thermometer input (universal input): 0.1 to 999.9 EU (in units of 0.1 EU) ✽4
Models with analog input: 0.01 to 99.99% FS (in units of 0.01% FS)
Proportional band (P)
Models with thermocouple/platinum resistance thermometer input (universal input): 0.1 to 999.9 EU (in units of 0.1 EU) ✽4
Models with analog input: 0.1 to 999.9% FS (in units of 0.1% FS)
Integral time (I) 0 to 3999 s (in units of 1 s)
Derivative time (D) 0 to 3999 s (in units of 1 s) ✽5
Control period 0.5, 1 to 99 s (in units of 1 s)
Manual reset value 0.0 to 100.0% (in units of 0.1%)
Alarm setting range −1999 to 9999 (decimal point position depends on input type)
Affect of signal source resistance
Thermocouple: 0.1° C/Ω max. (100 Ω max.)
Platinum resistance thermometer: 0.1° C/Ω max. (10 Ω max.)
Insulation resistance 20 MΩ min. (at 500 VDC)
Dielectric strength 2,300 VAC, 50 or 60 Hz for 1 min (between terminals with different charge)
Vibration
resistance
Malfunction 10 to 55 Hz, 20 m/s2 for 10 min each in X, Y, and Z directions
Destruction 10 to 55 Hz, 0.75-mm single amplitude for 2 hrs each in X, Y, and Z directions
Shock
resistance
Malfunction 100 m/s2, 3 times each in X, Y, and Z directions
Destruction 300 m/s2, 3 times each in X, Y, and Z directions
Weight
E5CN Controller: Approx. 150 g, Mounting Bracket: Approx. 10 g
E5CN-U Controller: Approx. 110 g, Mounting Bracket: Approx. 10 g
Degree of
protection
E5CN Front panel: IP66, Rear case: IP20, Terminals: IP00
E5CN-U Front panel: IP50, Rear case: IP20, Terminals: IP00
Memory protection Non-volatile memory (number of writes: 1,000,000 times)
Setup Tool CX-Thermo version 4.0 or higher
Setup Tool port
Provided on the bottom of the E5CN. Use this port to connect a computer to the E5CN when using the Setup Tool. An
E58-CIFQ1 USB-Serial Conversion Cable is required to connect the computer to the E5CN. ✽6
Standards
Approved
standards ✽7 UL 61010-1, CSA C22.2 No. 1010-1
Conformed
standards EN 61010-1 (IEC 61010-1): Pollution level 2, overcurrent category II
EMC
EMI: EN 61326
Radiated Interference Electromagnetic Field Strength: EN 55011 Group 1, class A
Noise Terminal Voltage: EN 55011 Group 1, class A
EMS: EN 61326
ESD Immunity: EN 61000-4-2
Electromagnetic Field Immunity: EN 61000-4-3
Burst Noise Immunity: EN 61000-4-4
Conducted Disturbance Immunity: EN 61000-4-6
Surge Immunity: EN 61000-4-5
Power Frequency Magnetic Field Immunity: EN 61000-4-8
Voltage Dip/Interrupting Immunity: EN 61000-4-11
10 Basic-type Digital Temperature Controller E5CN/E5CN-U
USB-Serial Conversion Cable
Note: A driver must be installed in the personal computer. Refer to
installation information in the operation manual for the
Conversion Cable.
Communications Specifications
✽ The baud rate, data bit length, stop bit length, and vertical parity can
be individually set using the Communications Setting Level.
Current Transformer (Order Separately)
Ratings
Heater Burnout Alarms, SSR Failure
Alarms, and Heater Overcurrent Alarms
✽1. For heater burnout alarms, the heater current will be measured
when the control output is ON, and the output assigned to the
alarm 1 function will turn ON if the heater current is lower than the
set value (i.e., heater burnout detection current value).
✽2. For SSR failure alarms, the heater current will be measured when
the control output is OFF, and the output assigned to the alarm 1
function will turn ON if the heater current is higher than the set
value (i.e., SSR failure detection current value).
✽3. For heater overcurrent alarms, the heater current will be
measured when the control output is ON, and the output assigned
to the alarm 1 function will turn ON if the heater current is higher
than the set value (i.e., heater overcurrent detection current
value).
Electrical Life Expectancy Curve for
Relays (Reference Values)
Note: Do not connect a DC load to a Controller with a Long-life Relay
Output.
Applicable OS Windows 2000, XP, or Vista
Applicable software
Thermo Mini, CX-Thermo version 4.0 or
higher
Applicable models
E5AN/E5EN/E5CN/E5CN-U/E5AN-H/
E5EN-H/E5CN-H
USB interface standard Conforms to USB Specification 1.1.
DTE speed 38400 bps
Connector
specifications
Computer: USB (type A plug)
Temperature Controller: Setup Tool port
(on bottom of Controller)
Power supply
Bus power (Supplied from USB host
controller.)
Power supply voltage 5 VDC
Current consumption 70 mA
Ambient operating
temperature
0 to 55°C (with no condensation or icing)
Ambient operating
humidity
10% to 80%
Storage temperature −20 to 60°C (with no condensation or
icing)
Storage humidity 10% to 80%
Altitude 2,000 m max.
Weight Approx. 100 g
Transmission line
connection method
RS-485: Multipoint
Communications RS-485 (two-wire, half duplex)
Synchronization
method
Start-stop synchronization
Protocol CompoWay/F, SYSWAY, or Modbus
Baud rate
1200, 2400, 4800, 9600, 19200, 38400, or
57600 bps
Transmission code ASCII
Data bit length ✽ 7 or 8 bits
Stop bit length ✽ 1 or 2 bits
Error detection
Vertical parity (none, even, odd)
Frame check sequence (FCS) with SYSWAY
Block check character (BCC) with
CompoWay/F or CRC-16 Modbus
Flow control None
Interface RS-485
Retry function None
Communications
buffer
217 bytes
Communications
response wait time
0 to 99 ms
Default: 20 ms
Dielectric strength 1,000 VAC for 1 min
Vibration resistance 50 Hz, 98 m/s2
Weight E54-CT1: Approx. 11.5 g, E54-CT3: Approx.
50 g
Accessories
(E54-CT3 only)
Armatures (2)
Plugs (2)
CT input
(for heater current detection)
Models with detection for single-phase
heaters: One input
Models with detection for single-phase
or three-phase heaters: Two inputs
Maximum heater current 50 A AC
Input current indication
accuracy ±5% FS ±1 digit max.
Heater burnout alarm
setting range ✽1
0.1 to 49.9 A (in units of 0.1 A)
Minimum detection ON time: 100 ms
SSR failure alarm setting
range ✽2
0.1 to 49.9 A (in units of 0.1 A)
Minimum detection OFF time: 100 ms
Heater overcurrent
alarm setting range ✽3
0.1 to 49.9 A (in units of 0.1 A)
Minimum detection ON time: 100 ms
500
300
100
50
30
10
5
3
1
0 1 2 3 4 5 6
E5CN
250 VAC, 30 VDC
(resistive load)
cosφ = 1
Switching current (A)
Life (× 104 operations)
Basic-type Digital Temperature Controller E5CN/E5CN-U 11
External Connections
• A voltage output (control output, for driving SSR) is not electrically insulated from the internal circuits. When using a grounding thermocouple,
do not connect any of the control output terminals to ground. (If the control output terminals are connected to ground, errors will occur in the
measured temperature values as a result of leakage current.)
• Consult with your OMRON representative before using the external power supply for the ES1B for any other purpose.
E5CN
Controllers
Option Units
E5CN-U
Note: For the Wiring Socket, purchase the P2CF-11 or PG3A-11 separately.
Relay output
250 VAC, 3 A (resistive load)
Voltage output (for driving SSR)
12 VDC, 21 mA
Current output
0 to 20 mA DC
Load: 600 Ω max.
4 to 20 mA DC
Long-life relay output
250 VAC, 3 A (resistive load)
Control output 1
+
−
A
B
B
+
−
Input power supply
Control output 1
Auxiliary outputs (relay outputs)
250 VAC, 3 A
(resistive load)
• 100 to 240 VAC
• 24 VAC/VDC (no polarity)
+
−
+
V −
Auxiliary output 2
mA
Auxiliary output 1
A heater burnout alarm, heater short alarm,
heater overcurrent alarm, or input alarm is
sent to the output to which the alarm 1
function is assigned.
DO NOT
USE
DO NOT
USE
DO NOT
USE
mA Volt T/c Pt
Analog input Temperature
input
1 1
1 2
1 3
1 4
1 5
E V 1
E V 2
E53-CNHBN2
Event inputs
and CT
1 1
1 2
1 3
1 4
1 5
E53-CNPBN2
Event Inputs and
External Power Supply
E V 1
E V 2
+
−
External
power supply
12 VDC,
20 mA
1 1
1 2
1 3
1 4
1 5
E53-CNPHN2
External Power
Supply and CT
+
−
External
power supply 12 VDC,
20 mA
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNP03N2
Communications (RS-485)
and External Power Supply
+
−
External
power supply
12 VDC,
20 mA
1 1
1 2
1 3
1 4
1 5
E53-CNQHN2
Control Output 2
and CT
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
E V 1
E V 2
E53-CNQBN2
Event Inputs and
Control Output 2
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNHH03N2
Communications
(RS-485) and CT2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNQ03N2
Communications
(RS-485) and
Control Output 2
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CN03N2
Communications
(RS-485)
1 1
1 2
1 3
1 4
1 5
E V 1
E V 2
E53-CNBN2
Event inputs
1 1
1 2
1 3
1 4
1 5
E53-CNQHHN2
Control Output 2
and CT2
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNH03N2
Communications
(RS-485) and CT
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
CT1 CT1
CT1
CT1 CT1
CT1
CT2
CT2
Voltage output (for driving SSR)
12 VDC, 21 mA
Control output 2
A
B
B
Auxiliary output
250 VAC, 3 A (resistive load)
Control output 1
Input power supply
• 100 to 240 VAC
• 24 VAC/VDC (no polarity)
Auxiliary output 1
(Relay outputs)
V
m A An input error is sent to the
output to which the alarm 1
function is assigned.
Current output
0 to 20 mA DC
Relay output
(three terminals used)
SPDT, 250 VAC, 3 A
(resistive load)
Voltage output
(for driving SSR)
12 VDC, 21 mA
Load: 600 W max.
4 to 20 mA DC
Control output 1
Auxiliary output 2
(Control output (cooling side))
DO NOT
USE
DO NOT
USE
DO NOT
USE
mA Volt T/c Pt
Analog input Temperature
input
12 Basic-type Digital Temperature Controller E5CN/E5CN-U
Nomenclature
Dimensions (Unit: mm)
Accessories (Order Separately)
USB-Serial Conversion Cable
Operation indicators
Level Key
Temperature unit
No.1 display
No. 2 display
Up Key
Mode Key Down Key
E5CN
E5CN-U
The front panel is the same for the E5CN and E5CN-U.
45+0.6
0
45+0.6
0
45+0.6
0
60 min.
(48 × number of units − 2.5)+1.0
0
Group mounting does not
allow waterproofing.
Panel Cutout
Mounted Separately Group Mounted
48 × 48
Terminal Cover
(E53-COV17)
(Accessory)
44.8 × 44.8 48.8
6
1.5
91
78
Mounting Adapter
(Accessory)
58
Waterproof
Packing
(Accessory)
E5CN
Terminal Models
Note: The terminal block cannot be removed.
• Recommended panel thickness is 1 to
5 mm.
• Group mounting is not possible in the
vertical direction. (Maintain the specified
mounting space between Controllers.)
• To mount the Controller so that it is
waterproof, insert the waterproof packing
onto the Controller.
• When two or more Controllers are
mounted, make sure that the surrounding
temperature does not exceed the
allowable operating temperature
specified in the specifications.
48 × 48
6 14.2
58 44.8 × 44.8
70.5
(84.7)
Mounting Adapter
(Accessory)
45+0.6
0
45+0.6
0
45+0.6
0
60 min.
(48 × number of units − 2.5)+1.0
0
Panel Cutout
Mounted Separately Group Mounted
E5CN-U
Plug-in Models
• Recommended panel thickness is 1 to 5
mm.
• Group mounting is not possible in the
vertical direction. (Maintain the specified
mounting space between Controllers.)
• When two or more Controllers are
mounted, make sure that the surrounding
temperature does not exceed the
allowable operating temperature specified
in the specifications.
(2,100)
250 1,765
USB connector (type A plug) Serial connector
LED indicator (RD)
LED indicator (SD)
E58-CIFQ1
Basic-type Digital Temperature Controller E5CN/E5CN-U 13
Current Transformers
48
48.8
22
9.1
Order the Waterproof Packing separately if it becomes lost or
damaged.
The Waterproof Packing can be used to achieve an IP66 degree of
protection.
(Deterioration, shrinking, or hardening of the waterproof packing may
occur depending on the operating environment. Therefore, periodic
replacement is recommended to ensure the level of waterproofing
specified in IP66. The time for periodic replacement depends on the
operating environment. Be sure to confirm this point at your site.
Consider one year a rough standard. OMRON shall not be liable for
the level of water resistance if the customer does not perform periodic
replacement.)
The Waterproof Packing does not need to be attached if a waterproof
structure is not required.
Terminal Cover
E53-COV17
Waterproof Packing
Y92S-29 (for DIN 48 × 48)
Note: The E53-COV10
cannot be used.
E54-CT3 Accessory
• Armature
30
21
15
5.8 dia.
25 3
40
10.5
2.8
7.5
10
Two, 3.5 dia.
40 × 40
30
12 dia.
9
2.36 dia.
15
30
Two, M3 (depth: 4)
Approx. 3 dia.
18
(22)
Approx. 6 dia.
Plug
Armature
Lead
E54-CT1
E54-CT3
Connection Example
• Plug
E54-CT1
Thru-current (Io) vs. Output Voltage
(Eo) (Reference Values)
Maximum continuous heater current: 50 A (50/60 Hz)
Number of windings: 400±2
Winding resistance: 18±2 Ω
Thru-current (Io) A (r.m.s.)
1 10 100 mA 1 10 100 1,000 A
Output voltage (Eo) V (r.m.s.)
100 V 50 Hz
Distortion
factor 10%
3%
1%
100 Ω
RL = 10 Ω
10 ∞
1
100 mV
10
1
100 μV
10
1 kΩ
E54-CT3
Thru-current (Io) vs. Output Voltage
(Eo) (Reference Values)
Maximum continuous heater current: 120 A (50/60 Hz)
(Maximum continuous heater current for the
Temperature Controller is 50 A.)
Number of windings: 400±2
Winding resistance: 8±0.8 Ω
3%
1%
1 kΩ
100 Ω
50 Ω
RL = 10 Ω
500 Ω
∞
Distortion
factor
10%
Thru-current (Io) A (r.m.s.)
1 10 100 mA 1 10 100 1,000 A
Output voltage (Eo) V (r.m.s.)
100 V 50 Hz
10
1
100 mV
10
1
100 μV
10
14 Basic-type Digital Temperature Controller E5CN/E5CN-U
Adapter
E5CN-U Wiring Socket
Note: A model with finger protection (P2CF-11-E) is also available.
Note: 1. Using any other sockets will adversely affect accuracy. Use only the specified sockets.
2. A Protective Cover for finger protection (Y92A-48G) is also available.
Fixture (Accessory)
69.6 to 77.6
67 × 67 87
72 × 72
4.7 76
72 × 72
48 × 48
Panel (1 to 8 mm)
77.3 (to back of E5CN)
2.2 4.7
Y92F-45 Note: Use this Adapter when the panel has already been prepared for the E5B@.
Mounted to E5CN
40±0.2
4.5
8 7 6 5
4
3
1 2
9
10 11
70 max.
4
Eleven, M3.5 × 7.5
sems screws 7.8
Two,
4.5-dia.
holes
50 max.
3
31.2 max.
35.4
Note: Can also be mounted to a DIN track.
Mounting Holes
Terminal Layout/Internal Connections
(Top View)
Two, 4.5 dia. mounting holes
Front-connecting Socket
P2CF-11
5 6 7 8
4
3
2
9
1 11 10
25.6
27 dia.
45
45
4.5 16.3 6.2
4 7 3
8.7
6
Terminal Layout/Internal Connections
(Bottom View)
Back-connecting Socket
P3GA-11
Basic-type Digital Temperature Controller E5CN/E5CN-U 15
Operation
Setting Levels Diagram
This diagram shows all of the setting levels. To move to the advanced function setting level and calibration level, you must enter passwords. Some
parameters are not displayed depending on the protect level setting and the conditions of use.
Control stops when you move from the operation level to the initial setting level.
Basic Type
✽1. You can return to the operation level by executing a software reset.
✽2. It is not possible to move to other levels from the calibration level by operating the keys on the front panel.
It can be done only by first turning OFF the power.
✽3. From the manual control level, key operations can be used to move to the operation level only.
Error Displays (Troubleshooting)
When an error occurs, the No.1 display shows the error code. Take necessary measure according to the error code, referring the table below.
Note: If the input value exceeds the display limit (-1999 to 9999), though it is within the control range, will be displayed under -1999 and
above 9999. Under these conditions, control output and alarm output will operate normally.
For details on the control range, refer to the E5CN/E5AN/E5EN Digital Temperature Controllers User's Manual Basic Type (Cat. No. H156).
✽These errors are displayed only when the PV/SP is displayed. Errors are not displayed for other displays.
No.1 display Meaning Action
Status at error
Control output Alarm output
s.err (S. Err)
Input error
✽
Check the wiring of inputs for miswiring, disconnections, and short-circuits and check the
input type. OFF Operates as above
the upper limit.
e333 (E333)
A/D
converter
error
Turn the power OFF then back ON again. If the display remains the same, the controller must
be repaired. If the display is restored to normal, then a probable cause can be external noise
affecting the control system. Check for external noise.
OFF OFF
e111 (E111)
Memory
error
Turn the power OFF then back ON again. If the display remains the same, the controller must
be repaired. If the display is restored to normal, then a probable cause can be external noise
affecting the control system. Check for external noise.
OFF OFF
Start in manual mode.
25
10 0
c
25
10 0
c
a- m
Power ON
✽3
Manual
mode
Press the O Key or the
PF Key for at least 1 s. ✽4
Press the O Key
for at least 3 s while
a-m is displayed.
(a-m will flash after
1st second.)
Operation
Level
Press the
O Key for
at least 1 s.
Press the O Key
for at least 1 s.
Input password.
Input password while
amoV is displayed. (Set
value −169)
Press the
O Key less than 1 s.
Press the O Key for at
least 3 s. (Display will flash
after 1st second.)
Control stops.
Press the
O Key for less than 1 s.
Press the
O+ M
Keys for at
least 3 s.
(Display
will flash
after 1st
second.)
Protect Level
Control in progress
Level change
Not displayed for some models
Control stopped
Start in automatic mode.
Adjustment
Level
Initial Setting
Level
Manual
Control Level
Advanced Function
Setting Level
Calibration Level
Communications
Setting
Level
Press the
O+ M
Keys for at
least 1 s.
*1
Note: The time taken to
move to the protect
level can be adjusted
by changing the
“Move to protect level
time” setting.
✽2
16 Basic-type Digital Temperature Controller E5CN/E5CN-U
M
M
M
M
M
M
M
psel
cwf
u-no
1
bps
9.6
len
7
sbit
2
prty
even
sdwt
20
Starting in manual mode.
M
M
M
M
M
M
pmov
0
oapt
0
pmsk
on
prlp
0
icpt
1
wtpt
off
25
M
M
M
M
M
M
M
M
M
M
ST (Self-tuning)
M
M
M
M
in-t
5
in-h
100
in-l
dp
d-u
sl-h
1300
sl-l
-200
cntl
onof
s-hc
stnd
st
on
ptrn
off
cp
20
c-cp
20
orev
or-r
0
0
c
M
M
M
l.adj
cmwt
off
at
off
M
M
M
M
M
M
ct1
0.0
0.0
0.0
hb1
0.0
hb2
0. 0
M
M
50.0
50.0
M
M
oc1
50.0
oc2
50.0
M
M
M
sp-0
0
sp-1
0
sp-2
0
sp-3
0
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
of-r
50.0
soak
1
c-sc
1.00
d
40
p
8.0
i
233
c-db
0.0
hys
1.0
chys
1.0
ol-l
-5.0
wt-b
off
mv-s
0.0
mv-e
0.0
ol-h
105.0
M
M
M
ins
0.0
insh
0.0
insl
0. 0
sprt
off
sqrp
0.0
M
M
M
a-m
25
25
0
M
M
M
M
M
M
M
sp-m
0
ct1
0.0
ct2
0.0
lcr1
0.0
lcr2
0.0
prst
rset
sktr
0
M
m-sp
0
r-s
run
M
M
M
M
M
M
M
M
M
M
M
M
c-o
0.0
al-1
0
al1h
0
al1l
0
al- 2
0
al2h
0
al2l
0
al-3
0
al3l
0
al3h
0
o
0.0
M
orl
0.0
M
ct2
lcr1
hs1
lcr2
hs2
0.0
0.0
alh1
0.2
M
alt1
2
M
Power ON
Starting in
automatic
mode.
Manual Control Level
PID
Control
only
PV/MV
Press the O Key less than 1 s.
Press the O Key less than 1 s.
Operation Level
Adjustment
Level
Adjustment Level
Display
Displayed only
once when
entering
adjustment level.
AT Execute/Cancel
Communications
Writing
Heater Current 1
Value Monitor
Heater Burnout
Detection 1
Heater Overcurrent
Detection 1
Heater Current 2
Value Monitor
Heater Burnout
Detection 2
Heater Overcurrent
Detection 2
Leakage Current 1
Monitor
Leakage Current 2
Monitor
HS Alarm 1
HS Alarm 2
C SP 0
C SP 1
C SP 2
SP used by
multi-SP
C SP 3
C
C
C
C
C
C
C Temperature Input Shift
1-point shift
2-point shift
Set either
of these
parameters.
Upper Limit
Temperature
Input Shift Value
Lower Limit
Temperature
Input Shift Value
Proportional Band
Integral Time
PID settings
Derivative Time
Cooling Coefficient
Heating/cooling
Dead Band
Manual Reset Value
Clear the offset during
stabilization of P or PD
control.
Hysteresis (Heating)
Hysteresis (Cooling)
Hysteresis settings
C
Soak Time
Wait Band
MV at Stop
MV at PV Error
C SP Ramp Set Value
MV Upper Limit
MV Lower Limit
MV Change Rate Limit
Extraction of Square Root
Low-cut Point
C Process Value
Added when Additional
PV display is ON.
C Process Value/
Set Point
C
C
C
Auto/Manual Switch
PID control only.
Added when
auto/manual select
addition is ON.
Multi-SP
Set Point Setting
Set Point During
SP Ramp
Heater Current 1 Value
Monitor
Heater Current 2 Value
Monitor
Leakage Current 1
Monitor
Leakage Current 2
Monitor
Program Start
Soak Time Remain
Press the O and M Keys for
at least 3 s.
Protect Level
Press the O and M Keys for at least 1 s.
Press the O Key
less than 1 s.
Communications
Setting Level
Note: The time taken to move to the protect
level can be adjusted by changing the
"Move to protect level time" setting.
Note: Displayed only for models with communications.
Changes are effective after cycling power or
after a software reset.
Move to Protect Level:
Displayed only when a password
is set. Restricts moving to protect
level.
Operation/Adjustment Protect:
Restricts displaying and
modifying menus in operation,
adjustment, and manual control
levels.
Initial Setting/
Communications Protect:
This protect level restricts movement
to the initial setting, communications
setting, and advanced function setting
levels.
Setting Change Protect:
Protects changes to setups by
operating the front panel keys.
Password to Move to Protect Level:
Password setting
Parameter Mask Enable:
Displayed only when a
parameter mask is set.
Protocol Setting:
Switches between
CompoWay/F (SYSWAY)
and Modbus.
Communications Unit No.
Communications
Baud Rate
CompoWay/F
(SYSWAY) only
Communications
Data Length
Communications
Stop Bits
Communications Parity
Send Data Wait Time
C
RUN/STOP
Alarm Value 1
Set either of these parameters.
Alarm Value
Upper Limit 1
Alarm Value
Lower Limit 1
C
C
C
C
Alarm Value 2
Set either of these parameters.
Alarm Value
Upper Limit 2
Alarm Value
Lower Limit 2
C Alarm Value 3
C
C
Alarm Value
Upper Limit 3
Alarm Value
Lower Limit 3
Set either of these parameters.
MV Monitor (Heating)
MV Monitor (Cooling)
Press the
O Key for
at least 1 s.
Press the O Key less than 1 s.
Initial Setting Level
Input Type
Scaling Upper Limit
Scaling Lower Limit
Decimal Point
For input type of analog
C
C
Temperature Unit
°C, °F
For input type of
temperature
SP Upper Limit
SP Lower Limit
Limit the set point
PID ON/OFF
Standard or
Heating/Cooling
For input type of
temperature, standard
control, or PID
Program Pattern
When assigning PID or
control output to ON/OFF
output
Control Period (Heating)
Control Period (Cooling)
Set the ON/OFF
output cycle.
Direct/Reverse Operation
C
Alarm 1 Type
Alarm 1
Hysteresis
Press the O Key for at least 3 s.
Other than the Auto/Manual Switch display
Press the
O Key for at
least 1 s.
Press the
O Key
for at
least 3 s.
Parameters
Basic Type
Some parameters are not displayed depending on
the model of the Controller and parameter settings.
For details, refer to the E5CN/E5AN/E5EN Digital
Temperature Controllers User's Manual Basic Type
(Cat. No. H156).
Basic-type Digital Temperature Controller E5CN/E5CN-U 17
M
M
M
M
M
M
a1lt
off
a2lt
off
a3lt
off
prlt
3
sero
off
cjc
on
rlrv
M
M
off
colr
red
pv-b
5.0
M
M
M
M
M
M
M
M
M
hsu
on
hsl
off
hsh
0.1
lba
0
lbal
8.0
lbab
3.0
out1
o
out2
none
M
init
off
M
M
M
M
M
M
M
M
mspu
off
spru
m
rest
a
sb1n
n-o
sb2n
n-o
sb3n
n-o
hbu
on
hbl
off
hbh
0.1
M
M
M
M
ra1m
0
ra2m
0
ra2
0
ra1
0
rac
0
M
M
M
M
M
spdp
4
odsl
o
pvdp
on
pvst
off
svst
off
M
M
cmov
0
inf
0.0
M
M
alfa
0.65
st-b
15.0
M
M
at-h
0.8
at-g
0.8
M
lcma
20.0
M M
M
M
M
M
a1on
0
a2on
0
a3 on
0
a1of
0
a2of
0
a3of
0
M
M
M
M
M
ocu
on
ocl
off
och
0.1
M
M
M
M
M
sub1
alm1
sub2
alm2
csel
on
t-u
m
alsp
sp-m
M
pvrp
4
csca
off
M
manl
off
M
M
M
pvad
off
o-dp
off
ret
off
M
istp
ins1
M
M
mvse
off
amad
off
rt
off
M
RT
M
M
M
M
M
M
alt2
2
a lt3
2
tr-t
off
tr-h
100.0
tr-l
0.0
M
o1-t
4-20
M
M
ev-m
1
ev-1
none
ev-2
stop
alh3
0.2
M
alh2
0.2
M
d. ref
0.2 5
Press the O Key for at least 1 s.
Advanced Function Setting Level
C
Alarm 2 Type
Alarm 3 Type
Alarm 2
Hysteresis
Alarm 3
Hysteresis
C
Transfer Output Type
Linear output
Transfer Output
Upper Limit
Transfer Output
Lower Limit
Linear Current Output
Linear output
Number of Multi-SP Uses
Two SPs: 1
Four SPs: 2
Event Input
Assignment 1
Event Input
Assignment 2
M
amov
0
M
sqr
off
M
Extraction of Square
Root Enable
Move to Advanced
Function Setting Level:
Displayed when initial
setting/communications
protect is set to 0.
Move by setting password (−169).
Parameter Initialization
Multi-SP Uses
SP Ramp Time Unit
Standby Sequence
Reset
Auxiliary Output 1
Open in Alarm
Auxiliary Output 2
Open in Alarm
Auxiliary Output 3
Open in Alarm
HB ON/OFF
Heater Burnout Latch
C
C
Heater Burnout
Hysteresis
ST Stable Range
AT Calculated Gain
α
C AT Hysteresis
Limit Cycle MV
Amplitude
Input Digital Filter
Additional PV Display
MV Display
Automatic Display
Return Time
Alarm 1 Latch
Alarm 2 Latch
Alarm 3 Latch
Move to Protect Level
Time
Input Error Output
Cold Junction
Compensation
Method
MB Command
Logic Switching
PV Change Color
PV Stable Band
Alarm 1 ON Delay
Alarm 2 ON Delay
Alarm 3 ON Delay
Alarm 1 OFF Delay
Alarm 2 OFF Delay
Alarm 3 OFF Delay
Input Shift Type
MV at Stop and Error
Addition
Auto/Manual Select
Addition
HS Alarm Use
HS Alarm Latch
HS Alarm Hysteresis
LBA Detection Time
C
C
LBA Level
LBA Band
Control Output 1
Assignment
Control Output 2
Assignment
Auxiliary Output 1
Assignment
Auxiliary Output 2
Assignment
Character Select
Soak Time Unit
Alarm SP Selection
Manual MV
Limit Enable
PV Rate of Change
Calculation Period
Automatic Cooling
Coefficient Adjustment
Heater Overcurrent
Use
Heater Overcurrent
Latch
Heater Overcurrent
Hysteresis
Move to Calibration
Level
"PV/SP" Display
Screen Selection
MV Display Selection
PV Decimal Point
Display
PV Status Display
Function
SV Status Display
Function
Display Refresh
Period
Control Output 1
ON/OFF Count
Monitor
Control Output 2
ON/OFF Count
Monitor
Control Output 1
ON/OFF Count
Alarm Set Value
Control Output 2
ON/OFF Count
Alarm Set Value
ON/OFF Counter
Reset
18 Basic-type Digital Temperature Controller E5CN/E5CN-U
Safety Precautions
!CAUTION
✽1. An SELV circuit is one separated from the power supply with
double insulation or reinforced insulation, that does not exceed
30 V r.m.s. and 42.4 V peak or 60 VDC.
✽2. A class 2 power supply is one tested and certified by UL as having
the current and voltage of the secondary output restricted to
specific levels.
✽3. The tightening torque for E5CN-U is 0.5 N·m.
Precautions for Safe Use
Be sure to observe the following precautions to prevent malfunction
or adverse affects on the performance or functionality of the product.
Not doing so may occasionally result in faulty operation.
1. This product is specifically designed for indoor use only.
Do not use this product in the following places:
• Places directly subject to heat radiated from heating equipment.
• Places subject to splashing liquid or oil atmosphere.
• Places subject to direct sunlight.
• Places subject to dust or corrosive gas (in particular, sulfide gas
and ammonia gas).
• Places subject to intense temperature change.
• Places subject to icing and condensation.
• Places subject to vibration and large shocks.
2. Use and store the product within the rated ambient temperature
and humidity.
Gang-mounting two or more Temperature Controllers, or mounting
Temperature Controllers above each other may cause heat to build
up inside the Temperature Controllers, which will shorten their
service life. In such a case, use forced cooling by fans or other
means of air ventilation to cool down the Temperature Controllers.
3. To allow heat to escape, do not block the area around the product.
Do not block the ventilation holes on the product.
4. Be sure to wire properly with correct polarity of terminals.
5. Use the specified size (M3.5, width 7.2 mm or less) crimped
terminals for wiring. To connect bare wires to the terminal block,
use stranded or solid copper wires with a gage of AWG24 to
AWG14 (equal to a cross-sectional area of 0.205 to 2.081 mm2).
(The stripping length is 5 to 6 mm.) Up to two wires of the same
size and type or two crimp terminals can be inserted into a single
terminal.
6. Do not wire the terminals that are not used.
7. To avoid inductive noise, keep the wiring for the product’s terminal
block away from power cables carry high voltages or large
currents. Also, do not wire power lines together with or parallel to
product wiring. Using shielded cables and using separate conduits
or ducts is recommended.
Attach a surge suppressor or noise filter to peripheral devices that
generate noise (in particular, motors, transformers, solenoids,
magnetic coils, or other equipment that have an inductance
component).
When a noise filter is used at the power supply, first check the
voltage or current, and attach the noise filter as close as possible
to the product.
Allow as much space as possible between the product and devices
that generate powerful high frequencies (high-frequency welders,
high-frequency sewing machines, etc.) or surge.
8. Use this product within the rated load and power supply.
9. Make sure that the rated voltage is attained within two seconds of
turning ON the power using a switch or relay contact. If the voltage
is applied gradually, the power may not be reset or output
malfunctions may occur.
10.Make sure that the Temperature Controller has 30 minutes or
more to warm up after turning ON the power before starting actual
control operations to ensure the correct temperature display.
Do not touch the terminals while power is being supplied.
Doing so may occasionally result in minor injury due to
electric shock.
Do not allow pieces of metal, wire clippings, or fine
metallic shavings or filings from installation to enter the
product. Doing so may occasionally result in electric
shock, fire, or malfunction.
Do not use the product where subject to flammable or
explosive gas. Otherwise, minor injury from explosion
may occasionally occur.
Do not leave the cable for the Support Software
connected to the product. Malfunction may occur due to
noise in the cable.
Do not use the Temperature Controller or Conversion
Cable if it is damaged. Doing so may occasionally result
in minor electric shock or fire.
Never disassemble, modify, or repair the product or touch
any of the internal parts. Minor electric shock, fire, or
malfunction may occasionally occur.
CAUTION - Risk of Fire and Electric Shock
a) This product is UL listed as Open Type Process
Control Equipment. It must be mounted in an
enclosure that does not allow fire to escape externally.
b) More than one disconnect switch may be required to
de-energize the equipment before servicing the
product.
c) Signal inputs are SELV, limited energy. ✽1
d) Caution: To reduce the risk of fire or electric shock, do
not interconnect the outputs of different Class 2
circuits. ✽2
If the output relays are used past their life expectancy,
contact fusing or burning may occasionally occur.
Always consider the application conditions and use the
output relays within their rated load and electrical life
expectancy. The life expectancy of output relays varies
considerably with the output load and switching
conditions.
Tighten the terminal screws to between 0.74 and
0.90 N·m. ✽3 Loose screws may occasionally result in
fire.
Set the parameters of the product so that they are
suitable for the system being controlled. If they are not
suitable, unexpected operation may occasionally result in
property damage or accidents.
A malfunction in the product may occasionally make
control operations impossible or prevent alarm outputs,
resulting in property damage. To maintain safety in the
event of malfunction of the product, take appropriate
safety measures, such as installing a monitoring device
on a separate line.
A semiconductor is used in the output section of long-life
relays. If excessive noise or surge is impressed on the
output terminals, a short-circuit failure is likely to occur. If
the output remains shorted, fire will occur due to
overheating of the heater or other cause. Take measures
in the overall system to prevent excessive temperature
increase and to prevent fire from spreading.
Do not allow pieces of metal or wire cuttings to get inside
the cable connector for the Support Software. Failure to
do so may occasionally result in minor electric shock, fire,
or damage to equipment.
Do not allow dust and dirt to collect between the pins in
the connector on the Conversion Cable. Failure to do so
may occasionally result in fire.
When inserting the body of the Temperature Controller
into the case, confirm that the hooks on the top and
bottom are securely engaged with the case. If the body of
the Temperature Controller is not inserted properly, faulty
contact in the terminal section or reduced water
resistance may occasionally result in fire or malfunction.
When connecting the Control Output Unit to the socket,
press it in until there is no gap between the Control Output
Unit and the socket. Otherwise contact faults in the
connector pins may occasionally result in fire or
malfunction.
Basic-type Digital Temperature Controller E5CN/E5CN-U 19
11.When executing self-tuning, turn ON power to the load (e.g.,
heater) at the same time as or before supplying power to the
product. If power is turned ON to the product before turning ON
power to the load, self-tuning will not be performed properly and
optimum control will not be achieved.
12.A switch or circuit breaker must be provided close to the product.
The switch or circuit breaker must be within easy reach of the
operator, and must be marked as a disconnecting means for this
unit.
13.Always turn OFF the power supply before pulling out the interior of
the product, and never touch nor apply shock to the terminals or
electronic components. When inserting the interior of the product,
do not allow the electronic components to touch the case.
14.Do not use paint thinner or similar chemical to clean with. Use
standard grade alcohol.
15.Design the system (e.g., control panel) considering the 2 seconds
of delay that the product's output to be set after power ON.
16.The output may turn OFF when shifting to certain levels. Take this
into consideration when performing control.
17.The number of EEPROM write operations is limited. Therefore,
use RAM write mode when frequently overwriting data during
communications or other operations.
18.Always touch a grounded piece of metal before touching the
Temperature Controller to discharge static electricity from your
body.
19.Do not remove the terminal block. Doing so may result in failure or
malfunction.
20.Control outputs (for driving SSR) that are voltage outputs are not
isolated from the internal circuits. When using a grounded
thermocouple, do not connect any of the control output terminals
to ground. (Doing so may result in an unwanted circuit path,
causing error in the measured temperature.)
21.When replacing the body of the Temperature Controller, check the
condition of the terminals. If corroded terminals are used, contact
failure in the terminals may cause the temperature inside the
Temperature Controller to increase, possibly resulting in fire. If the
terminals are corroded, replace the case as well.
22.Use suitable tools when taking the Temperature Controller apart
for disposal. Sharp parts inside the Temperature Controller may
cause injury.
23.Before connecting an Output Unit, confirm the specifications and
thoroughly read relevant information in the datasheet and manual
for the Temperature Controller.
24.Check the orientation of the connectors on the Conversion Cable
before connecting the Conversion Cable. Do not force a
connector if it does not connect smoothly. Using excessive force
may damage the connector.
25.Do not place heavy object on the Conversion Cable, bend the
cable past its natural bending radius, or pull on the cable with
undue force.
26.Do not connect or disconnect the Conversion Cable while
communications are in progress. Product faults or malfunction
may occur.
27.Make sure that the Conversion Cable's metal components are not
touching the external power terminals.
28.Do not touch the connectors on the Conversion Cable with wet
hands. Electrical shock may result.
29.Before using infrared communications, correctly attach the
enclosed Mounting Adapter to the cable for the Support Software.
When connecting the infrared port on the cable to the Support
Software into the Adapter, insert the connector to the specified
line. Communications may not be possible if the connector is not
connected properly.
Precautions for Correct Use
Service Life
1. Use the product within the following temperature and humidity
ranges:
Temperature: −10 to 55° C (with no icing or condensation)
Humidity: 25% to 85%
If the product is installed inside a control board, the ambient
temperature must be kept to under 55°C, including the
temperature around the product.
2. The service life of electronic devices like Temperature Controllers
is determined not only by the number of times the relay is switched
but also by the service life of internal electronic components.
Component service life is affected by the ambient temperature: the
higher the temperature, the shorter the service life and, the lower
the temperature, the longer the service life. Therefore, the service
life can be extended by lowering the temperature of the
Temperature Controller.
3. When two or more Temperature Controllers are mounted
horizontally close to each other or vertically next to one another,
the internal temperature will increase due to heat radiated by the
Temperature Controllers and the service life will decrease. In such
a case, use forced cooling by fans or other means of air ventilation
to cool down the Temperature Controllers. When providing forced
cooling, however, be careful not to cool down the terminals
sections alone to avoid measurement errors.
Measurement Accuracy
1. When extending or connecting the thermocouple lead wire, be sure
to use compensating wires that match the thermocouple types.
2. When extending or connecting the lead wire of the platinum
resistance thermometer, be sure to use wires that have low
resistance and keep the resistance of the three lead wires the
same.
3. Mount the product so that it is horizontally level.
4. If the measurement accuracy is low, check to see if input shift has
been set correctly.
Waterproofing
The degree of protection is as shown below. Sections without any
specification on their degree of protection or those with IP@0 are not
waterproof.
Front panel: IP66
Rear case: IP20, Terminal section: IP00
(E5CN-U: Front panel: IP50, rear case: IP20, terminals: IP00)
Operating Precautions
1. It takes approximately two seconds for the outputs to turn ON from
after the power supply is turned ON. Due consideration must be
given to this time when incorporating Temperature Controllers in a
sequence circuit.
2. When using self-tuning, turn ON power for the load (e.g., heater)
at the same time as or before supplying power to the Temperature
Controller. If power is turned ON for the Temperature Controller
before turning ON power for the load, self-tuning will not be
performed properly and optimum control will not be achieved.
3. When starting operation after the Temperature Controller has
warmed up, turn OFF the power and then turn it ON again at the
same time as turning ON power for the load. (Instead of turning
the Temperature Controller OFF and ON again, switching from
STOP mode to RUN mode can also be used.)
4. Avoid using the Controller in places near a radio, television set, or
wireless installing. These devices can cause radio disturbances
which adversely affect the performance of the Controller.
Others
1. The disk that is included with the Conversion Cable is designed for
a computer CD-ROM driver. Never attempt to play the disk in a
general-purpose audio player.
2. Do not connect or disconnect the Conversion Cable connector
repeatedly over a short period of time. The computer may
malfunction.
3. After connecting the Conversion Cable to the computer, check the
COM port number before starting communications. The computer
requires time to recognize the cable connection. This delay does
not indicate failure.
4. Do not connect the Conversion Cable through a USB hub. Doing
so may damage the Conversion Cable.
5. Do not use an extension cable to extend the Conversion Cable
length when connecting to the computer. Doing so may damage
the Conversion Cable.
20 Basic-type Digital Temperature Controller E5CN/E5CN-U
Mounting
Mounting to a Panel
For waterproof mounting, waterproof packing must be installed on the
Controller. Waterproofing is not possible when group mounting
several Controllers. Waterproof packing is not necessary when there
is no need for the waterproofing function.
1. The Panel Mounting Adapter is also included with the E5CN-U.
There is no waterproof packing included with the E5CN-U.
2. Insert the E5CN/E5CN-U into the mounting hole in the panel.
3. Push the adapter from the terminals up to the panel, and
temporarily fasten the E5CN/E5CN-U.
4. Tighten the two fastening screws on the adapter. Alternately
tighten the two screws little by little to maintain a balance. Tighten
the screws to a torque of 0.29 to 0.39 N·m.
Mounting the Terminal Cover
Make sure that the “UP” mark is facing up, and then attach the E53-
COV17 Terminal Cover to the holes on the top and bottom of the
Temperature Controller.
Removing the Temperature Controller from the
Case
The Temperature Controller can be removed from the case to perform
maintenance without removing the terminal leads. This is possible for
only the E5CN, E5AN, and E5EN, and not for the E5CN-U. Check the
specifications of the case and Temperature Controller before
removing the Temperature Controller from the case.
1. Insert a flat-blade screwdriver into the two tool insertion holes (one
on the top and one on the bottom) to release the hooks.
2. Insert the flat-blade screwdriver in the gap between the front panel
and rear case, and pull out the front panel slightly. Hold the top and
bottom of the front panel and carefully pull it out toward you,
without applying unnecessary force.
3. When inserting the body of the Temperature Controller into the
case, make sure the PCBs are parallel to each other, make sure
that the sealing rubber is in place, and press the E5CN toward the
rear case into position. While pushing the E5CN into place, push
down on the hooks on the top and bottom surfaces of the rear case
so that the hooks are securely locked in place. Be sure that
electronic components do not come into contact with the case.
Precautions when Wiring
• Separate input leads and power lines in order to prevent external
noise.
• Use wires with a gage of AWG24 (cross-sectional area:
0.205 mm2) to AWG14 (cross-sectional area: 2.081 mm2) twistedpair
cable (stripping length: 5 to 6 mm).
• Use crimp terminals when wiring the terminals.
• Tighten the terminal screws to a torque of 0.74 to 0.90 N·m,
however the terminal screws on the E5CN-U must be tightened to
a torque of 0.5 N·m.
• Use the following types of crimp terminals for M3.5 screws.
• Do not remove the terminal block. Doing so will result in
malfunction or failure.
E53-COV17
Terminal Cover
(Accessory) Adapter
(Accessory)
E5CN
E5CN-U
Waterproof packing
(Accessory) Panel
Order the P2CF-11 or
P3GA-11 Socket separately.
For Front-mounting Socket
(Panel mounting is also possible.
0.4 2.0
(1)
(2)
(3)
(1)
Flat-blade screwdriver
(Unit: mm)
Tool insertion hole
7.2 mm max.
7.2 mm max.
Basic-type Digital Temperature Controller E5CN/E5CN-U 21
Warranty and Application Considerations
Read and Understand This Catalog
Please read and understand this catalog before purchasing the products. Please consult your OMRON representative if you
have any questions or comments.
Warranty and Limitations of Liability
WARRANTY
OMRON's exclusive warranty is that the products are free from defects in materials and workmanship for a period of one year (or
other period if specified) from date of sale by OMRON.
OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, REGARDING NON-INFRINGEMENT,
MERCHANTABILITY, OR FITNESS FOR PARTICULAR PURPOSE OF THE PRODUCTS. ANY BUYER OR USER
ACKNOWLEDGES THAT THE BUYER OR USER ALONE HAS DETERMINED THAT THE PRODUCTS WILL SUITABLY MEET
THE REQUIREMENTS OF THEIR INTENDED USE. OMRON DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR
IMPLIED.
LIMITATIONS OF LIABILITY
OMRON SHALL NOT BE RESPONSIBLE FOR SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES, LOSS OF PROFITS,
OR COMMERCIAL LOSS IN ANY WAY CONNECTED WITH THE PRODUCTS, WHETHER SUCH CLAIM IS BASED ON
CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT LIABILITY.
In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which liability is asserted.
IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS REGARDING THE
PRODUCTS UNLESS OMRON'S ANALYSIS CONFIRMS THAT THE PRODUCTS WERE PROPERLY HANDLED, STORED,
INSTALLED, AND MAINTAINED AND NOT SUBJECT TO CONTAMINATION, ABUSE, MISUSE, OR INAPPROPRIATE
MODIFICATION OR REPAIR.
Application Considerations
SUITABILITY FOR USE
OMRON shall not be responsible for conformity with any standards, codes, or regulations that apply to the combination of
products in the customer's application or use of the products.
Take all necessary steps to determine the suitability of the product for the systems, machines, and equipment with which it will
be used.
Know and observe all prohibitions of use applicable to this product.
NEVER USE THE PRODUCTS FOR AN APPLICATION INVOLVING SERIOUS RISK TO LIFE OR PROPERTY WITHOUT
ENSURING THAT THE SYSTEM AS A WHOLE HAS BEEN DESIGNED TO ADDRESS THE RISKS, AND THAT THE OMRON
PRODUCTS ARE PROPERLY RATED AND INSTALLED FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR
SYSTEM.
Disclaimers
PERFORMANCE DATA
Performance data given in this catalog is provided as a guide for the user in determining suitability and does not constitute a
warranty. It may represent the result of OMRON's test conditions, and the users must correlate it to actual application
requirements. Actual performance is subject to the OMRON Warranty and Limitations of Liability.
CHANGE IN SPECIFICATIONS
Product specifications and accessories may be changed at any time based on improvements and other reasons. Consult with
your OMRON representative at any time to confirm actual specifications of purchased product.
DIMENSIONS AND WEIGHTS
Dimensions and weights are nominal and are not to be used for manufacturing purposes, even when tolerances are shown.
Cat. No. H04E-EN-01 In the interest of product improvement, specifications are subject to change without notice.
OMRON EUROPE B.V.
Wegalaan 67-69,
NL-2132 JD, Hoofddorp,
The Netherlands
Phone: +31 23 568 13 00
Fax: +31 23 568 13 88
www.industrial.omron.eu
ALL DIMENSIONS SHOWN ARE IN MILLIMETERS.
To convert millimeters into inches, multiply by 0.03937. To convert grams into ounces, multiply by 0.03527.
02/2008
GO FOR EXPERIENCE
The huge installed base of our easy-to-use control components, is proof of our experience.
Our control products with a display provide the clearest visibility and a perfect read-out.
Omron, your single source for all your control components needs.
We have been supplying quality components
for more than half a century
396
Control components
397
Control components
Control components – Table of contents
Temperature controllers 19
Product overview 398
Selection table 400
Basic temperature controllers K8AB-TH 402
E5L 403
E5C2 405
E5CSV 406
General purpose controllers E5_N 407
CelciuXº 410
Advanced and Multi-Loop controllers E5_N-H/E5_N-HT 412
E5_R/E5_R-T 414
Auxiliaries PRT1-SCU11/ES1B 416
ES1C 417
Power supplies 20
Product overview 418
Selection table 421
Single-phase S8VS 422
S8VM 423
S8JX-G 424
S8TS 425
S8T-DCBU-01/-02 426
Three-phase S8VT 427
Timers 21
Product overview 428
Selection table 430
Analogue solid state timers H3DS 432
H3DK 433
H3YN 434
H3CR 435
Digital timers H5CX 436
Motor timers H2C 437
Counters 22
Product overview 438
Selection table 440
Totalisers H7EC 442
H7ET 443
H7ER 444
Pre-set counters H8GN 445
H7CX 446
Cam positioners H8PS 447
Programmable relays 23
Product overview 448
Selection table 451
Programmable relays ZEN-10C 452
ZEN-20C 453
ZEN-8E 454
ZEN-PA 455
Digital panel indicators 24
Product overview 456
Selection table 458
1/32 DIN multi-function K3GN 460
1/8 DIN standard indicators K3MA-J, -L, -F 461
1/8 DIN advanced indicators –
analogue input
K3HB-X, -H, -V, -S 462
1/8 DIN advanced indicators –
digital input
K3HB-C, -P, -R 464
How many loops are required?
K8AB-TH E5C2 E5CSV
Single digital display
E5_N
What type of output?
No display Dual digital display
Voltage (pulse) Voltage (pulse)/
relay/mA linear
Relay
Basic General purpose
What type of output?
What type of control is needed?
Single loop
E5L
CELCIUXº – CONTROL AND CONNECTIVITY
The CelciuX° is designed to handle complex temperature profiles thanks to Omron’s unique Gradient Temperature Control (GTC)
algorithm and to offer easy program-less communication with Omron and third-party PLCs and HMI. Above all, the CelciuX°
incorporates all “simple to use” clever temperature control technology, like 2-PID, disturbance control and various ways of
tuning.
• Interfaces to a wide range of industrial networks
• Reduced engineering due to program-less communications, Smart Active Parts and Function Block Libraries
• One unit handling various types of input, such as Pt, Thermocouple, mA, and V input
Always the latest news on:
www.omron-industrial.com/celciux
CelciuXº – Multi Loop Temperature Controller
398
Temperature controllers
Page 402 Page 405 Page 403 Page 406 Page 407
E5_N-HT
SV programmer
Triple digital display
Advanced On-panel In-panel
CelciuXº
What type of mounting is required?
Multi-loop
E5_R
Standard
E5_R-T
SV programmer
E5_N-H
Standard
Triple digital display
Process
399
19 Temperature controllers
Page 412 Page 412 Page 414 Page 414 Page 410
400
Selection table
Category Alarm controller Analogue/digital
temperature
controller
Analogue
temperature
controller
Compact digital
temperature
controller
Digital temperature controller
Selection criteria
Model K8AB-TH E5L E5C2 E5CSV E5AN E5EN E5CN
Type Basic General purpose
Panel In-panel type In- & on-panel type On-panel type
Loops – Single loop
Size 22.5 mm wide 45x35 mm 1/16 DIN 1/16 DIN 1/4 DIN 1/8 DIN 1/16 DIN
Control mode
ON/OFF
PID – – *1
*1 P only
– – – –
2-PID *2
*2 2-PID is Omron´s easy to use high performance PID algorithm
– – –
Operation *3
*3 H = heat, H/C = heat or cool, H & C = heat and/or cool
– H/C H H/C H & C H & C H & C
Valve Control *4
*4 Valve control = relay up and down
– – – – – – –
Features
Accuracy ±2% ±1ºC – ±0.5% ±0.3% ±0.3% ±0.3%
Auto-tuning – – –
Self-tuning – – –
Transfer output – – – –
Remote input – – – – – – –
Number of alarms 1 – – 1 3 3 3
Heater alarm – – – – *5 *5 *5
IP rating front panel IP20 IP40 IP40 IP65 IP66 IP66 IP66
Display Rotary switch SV dial 3 digit
LCD
SV dial Single 3.5 digit Dual 4 digit
(colour change)
Dual 4 digit
(colour change)
Dual 4 digit
(colour change)
Supply
voltage
110/240 VAC
24 VAC/VDC – –
Comms *6
RS-232 – – – – –
RS-485 – – – –
Event IP – – –
QLP port *7 – – – –
DeviceNet – – – – – – –
Modbus – – – –
Control
output
Relay
SSR – – – – – – –
Voltage (pulse) – –
Linear voltage – – – – – – –
Linear current – – – –
Input type –
linear
mA – – – –
mV – – – –
V – – – –
Input type – thermocouple
K –
J – –
T – –
E – – –
L – –
U – – –
N – – –
R – –
S – – –
B – – –
W – – – –
PLII – – –
Input type –
RTD
Pt100 –
JPt100 – – –
THE – sensor provided – – –
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Temperature controllers
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19 Temperature controllers
*5. Heater alarm = heater burnout & SSR failure detection
*6. PROFIBUS-DP communication option via PRT1-SCU11 for E5_N(-H), E5_R, CelciuX°. More information on Page 416
*7. QLP: Quick Link Port to connected TC to PC using the smart USB cable E58-CIFQ1
*8. 3 Alarms per loop, 2 and 4 loop models are available.
Digital temperature controller Digital process controller
E5GN CelciuXº E5CN-H E5EN-H/AN-H E5_N-HT E5AR E5ER E5_R-T
General purpose Modular Universal SV Programmer Advanced SV Programmer
On-panel type In-panel type On-panel type
Same specification as corresponding E5_N-H
On-panel type
Same specifications as corresponding E5_R.
Single loop Multi-loop Single loop Multi-loop
1/32 DIN 31×96 mm 1/16 DIN 1/4, 1/8 DIN 1/4 DIN 1/8 DIN
– – – – – –
H & C H & C H & C H & C H & C H & C
– – –
±0.3% ±0.5% ±0.1% ±0.1% ±0.1% ±0.1%
– –
– – –
3 3 3 3 4 4
*5 *8 *5 *5 – –
IP66 – IP66 IP66 IP66 IP66
Dual 4 digit
(colour change)
LED Dual 5 digit
(colour change)
Triple 5 digit
(colour change)
Triple 5 digit Triple 5 digit
–
– – – –
– – –
–
– – – –
– – – –
– –
– –
– –
– – – – – –
407 410 412 375 414
402
K8AB-TH Basic temperature controllers
Protect your heating application
This temperature monitoring relay was designed specially for monitoring abnormal
temperatures to prevent excessive temperature increase and to protect equipment.
K8AB-TH provides temperature monitoring in slim design with a width of just
22.5 mm.
• Simple function settings using DIP switch
• Selectable alarm latch and SV setting protection
• Multi-input support for thermocouple or Pt100 sensor input
• Changeover relay: fail-safe selectable
• Alarm status identification with LED
Ordering information
Specifications
Input type Temperature setting range Setting unit Supply voltage Size in mm (HxWxD) Order code
Thermocouple/
Pt100
0 to 399°C/F 1°C/F 100 to 240 VAC 90x22.5x100 K8AB-TH11S AC100-240
24 VAC/VDC K8AB-TH11S AC/DC24
Thermocouple 0 to 1,800°C
0 to 3,200 °F *1
*1 Setting range depending on sensor type selected
10°C/F 100 to 240 VAC K8AB-TH12S AC100-240
24 VAC/VDC K8AB-TH12S AC/DC24
Item 100 to 240 VAC 50/60 Hz 24 VAC 50/60 Hz or 24 VDC
Allowable voltage range 85 to 110% of power supply voltage
Power consumption 5 VA max. 2 W max. (24 VDC), 4 VA max. (24 VAC)
Sensor inputs K8AB-TH11S Thermocouple: K, J, T, E; platinum-resistance thermometer: Pt100
K8AB-TH12S Thermocouple: K, J, T, E, B, R, S, PLII
Output relay One SPDT relay (3 A at 250 VAC, resistive load)
External inputs
(for latch setting)
Contact input ON: 1 k2 max., OFF: 100 k2 min.
Non-contact input ON residual voltage: 1.5 V max., OFF leakage current: 0.1 mA max.
Leakage current: Approx. 10 mA
Setting method Rotary switch setting (set of three switches)
Indicators Power (PWR): Green LED, relay output (ALM): Red LED
Other functions Alarm mode (upper limit/lower limit), output normally ON/OFF selection, output latch, setting protection,
fail-safe operation selectable, temperature unit°C/°F
Ambient operating temperature -10 to 55°C (with no condensation or icing); for 3-year guarantee: -10 to 50°C
Storage temperature -25 to 65°C (with no condensation or icing)
Setting accuracy ±2% of full scale
Hysteresis width 2°C
Output relay Resistive load 3 A at 250 VAC (cos= 1), 3 A at 30 VDC (L/R = 0 ms)
Inductive load 1 A at 250 VAC (cos= 0.4), 1 A at 30 VDC (L/R = 7 ms)
Minimum load 10 mA at 5 VDC
Maximum contact voltage 250 VAC
Maximum contact current 3 A AC
Maximum switching capacity 1,500 VA
Mechanical life 10,000,000 operations
Electrical life Make: 50,000 times, break: 30,000 times
Sampling cycle 500 ms
Weight 130 g
Degree of protection IP20
Memory protection Non-volatile memory (number or writes: 200,000)
Safety standards Approved standards EN 61010-1
Application standards EN 61326 and EN 61010-1 (pollution level 2, overvoltage category II)
Crimp terminals Two solid wires of 2.5 mm2 or two ferrules of 1.5 mm2 with insulation sleeves can be tightened together
Case colour Munsell 5Y8/1 (ivory)
Case material ABS resin (self-extinguishing resin)
Mounting Mounted to DIN-rail or with M4 screws
Size in mm (HxWxD) 90x22.5x100
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19 Temperature controllers
E5L Basic temperature controllers
Ideal for simple built-in control
This compact but powerful ON/OFF controller is provided with a sensor and is
available in an analogue or digital version. Mounting is in-panel with a standard
PTF14A-E socket.
• Available in 4 application specific ranges.
• Sensor provided to enable immediate usage.
• High capacity output of 10 A at 250 VAC for direct load switching.
• Simple operation and setting. Even simpler with digital model.
Ordering information
Options (Order separately)
Model Size Type Control Method Control Output Order code
E5L-A_ 45×35 mm Plug-in ON/OFF operation Relay E5L-A-30-20
E5L-A-0-50
E5L-A-0-100
E5L-A-100-200
E5L-C_ 45×35 mm Plug-in ON/OFF operation Relay E5L-C-30-20
E5L-C-0-100
E5L-C-100-200
Sockets
Type Order code
Front-connecting Socket PTF14A
PTF14A-E
E5L Basic temperature controllers
404
Specifications
* The accuracy of the accessory thermistor is not included.
Ratings
Item Model
E5L-A_ E5L-C_
Power supply voltage 100 to 240 VAC, 50/60 Hz
Operating voltage range 85% to 110% of the rated supply voltage
Power consumption Approx. 3 VA
Inputs Element-interchangeable thermistor
Control method ON/OFF control
Control output SPDT contacts, 250 VAC, 10 A, cos = 1 (resistive load) SPST-NO contacts, 250 VAC, 10 A, cos = 1 (resistive load)
Setting method Analogue setting Digital settings using keys on front panel
Indication method No display LCD digital display (character height: 12 mm)
Other functions Setting protection (key protection)
Input shift
Direct/reverse operation
Indication accuracy – ±(1°C + 1 digit) max.*
Setting accuracy – ±(1°C + 1 digit) max.*
Hysteresis -30 to 20°C models: Approx. 0.5 to 2.5°C (variable)
0 to 50°C models: Approx. 0.5 to 4°C (variable)
0 to 100°C models: Approx. 0.5 to 4°C (variable)
100 to 200°C models: Approx. 0.7 to 4°C (variable)
1 to 9°C (in increments of 1°C)
Repeat accuracy 1% FS max –
Minimum scale (standard scale) -30 to 20°C models and 0 to 50°C models: 5°C
0 to 100°C models and 100 to 200°C models: 10°C
–
Influence of temperature – ±([1% of PV or 2°C, whichever is greater]+ 1 digit) max.
Influence of voltage –
Sampling period – 2 s
Insulation resistance 100 MW max. (at 500 VDC)
Dielectric strength 2,300 VAC, 50/60 Hz for 1 min (between charged terminals and uncharged metallic parts, between power supply terminals and input
terminals, between power supply terminals and output terminals, and between input terminals and output terminals)
Vibration (malfunction) Frequency of 10 to 55 Hz, 0.5-mm double amplitude for 10 min each in X, Y, and Z directions
Vibration (destruction) Frequency of 10 to 55 Hz, 0.75-mm double amplitude for 2 h each in X, Y, and Z directions
Shock (malfunction) 147 m/s2, 3 times each in 6 directions 100 m/s2, 3 times each in 6 directions
Shock (destruction) 294 m/s2, 3 times each in 6 directions
Electrical life expectancy (control output relay) 100,000 operations min (at maximum applicable load)
Memory protection – Non-volatile memory (100,000 write operations)
Weight (Thermostat) Approx. 80 g (Thermostat only)
Degree of protection Front panel: IP40, Terminals: IP00
Approved standards –
Conformed standards EN 61010-1 (IEC 61010-1), Pollution Degree 2, Overvoltage Category II
EMC Directives EMI: EN61326-1
Radiated EMI: EN55011 Group 1 Class A
Conducted EMI: EN55011 Group 1 Class A
EMS: EN61326-1
Electrostatic discharge immunity: EN61000-4-2
Electromagnetic field strength immunity: EN61000-4-3
Burst noise immunity: EN61000-4-4
Conducted disturbance immunity: EN61000-4-6
Surge immunity: EN61000-4-5
Voltage dip and power interruption immunity: EN61000-4-11
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19 Temperature controllers
E5C2 Basic temperature controllers
Easy-to-use, basic temperature controller
with analogue dial setting
Omron's basic ON/OFF or PD controller features an analogue setting dial. This compact,
low-cost controller has a setting accuracy of 2% of full scale. It incorporates a
plug-in socket allowing for DIN-rail or flush mounting.
• Compact, cost-effective controller
• Control mode: ON/OFF or PD
• Control output: relay
• Power supply: 100-120 / 200-240VAC
• Thermocouple K: 0 to 1200°C, L: 0 to 400°C, Pt100: -50 to 200°C
Ordering information
Note: Specify either 100/110/120 VAC or 200/220/240 VAC when ordering.
Accessories
Specifications
Setting method Indication method Control mode Output Order code
Thermocouple Platinum resistance
thermometer Pt100
Thermistor THE
K (CA) chromel vs.
alumel
L (IC) iron
vs. constantan
Analogue setting No indication ON/OFF Relay E5C2-R20K E5C2-R20L-D E5C2-R20P-D E5C2-R20G
P Relay E5C2-R40K E5C2-R40L-D E5C2-R40P-D
Input ranges Thermocouple *1
*1 Values in ( ) are the minimum unit.
Platinum resistance thermometer Thermistor *2
*2 Values in ( ) are the thermistor resistive value.
K (CA) chromel vs. alumel L (IC) iron vs. constantan Pt100 THE
°C 0 to 200 (5),
0 to 300 (10),
0 to 400 (10),
0 to 600 (20),
0 to 800 (20),
0 to 1,000 (25),
0 to 1,200 (25)
0 to 200 (5),
0 to 300 (10),
0 to 400 (10)
5 to 450 (10)
-50 to 50 (2),
-20 to 80 (2),
0 to 50 (1),
0 to 100 (2),
0 to 200 (5),
0 to 300 (10),
0 to 400 (10)
-50 to 50 (2) (6 k at 0°C),
0 to 100 (2) (6 k at 0°C),
50 to 150 (2) (30 k at 0°C)
Functions Order code
Front connecting socket with finger protection P2CF-08-E
Back connecting socket (for flush mounting) P3G-08
Finger protection cover (for P3G-08) Y92A-48G
Protective front cover (IP66) Y92A-48B
Supply voltage 100/110/120 VAC or 200/220/240 VAC, 50/60 Hz
Thermocouple input type K, L (with sensor break detection)
RTD input type Pt100, THE
Control mode ON/OFF or P control
Setting method analogue setting
Output Relay, SPDT, 3 A at 250 VAC
Life expectancy Electrical: 100,000 operations min.
Setting accuracy ±2% FS max.
Hysteresis Approx. 0.5% FS (fixed)
Proportional band 3% FS (fixed)
Reset range 5 ±1% FS min.
Control period 20 s
IP Rating front panel IP40 (IP66 cover available)
IP rating terminals IP00
Ambient temperature -10 to 55°C
Size in mm (HxWxD) 48x48x96
406
E5CSV Basic temperature controllers
The easy way to perfect temperature control
This multi-range 1/16 DIN controller with alarm function offers field-selectable PID
control or ON/OFF control. The large, single display shows process value, direction of
deviation from set point, output and alarm status.
• All setting field configurable with switches
• Multi-input (Thermocouple/Pt100)
• Clearly visible 3.5 digit display with character height of 13.5 mm
• Control output: relay, voltage (for driving SSR)
• ON/OFF or 2-PID control with auto-tuning and self-tuning
Ordering information
Note:Other models are available on request.
Accessories
Specifications
Size in mm Supply voltage Number of alarm
points
Control output Order code
1/16 DIN
48Hx48Wx78D
100 to 240 VAC 1 Relay E5CSV-R1T-500
Voltage (for driving SSR) E5CSV-Q1T-500
24 VAC/VDC 1 Relay E5CSV-R1TD-500
Voltage (for driving SSR) E5CSV-Q1TD-500
Type Order code
Hard protective cover Y92A-48B
Supply voltage 100 to 240 VAC, 50/60 Hz or 24 VAC/VDC (depending on model)
Operating voltage range 85 to 110% of rated supply voltage
Power consumption 5 VA
Sensor input Multi-input (thermocouple/platinum resistance thermometer): K, J, L, T, U, N, R, Pt100, JPt100
Control output Relay output SPST-NO, 250 VAC, 3 A (resistive load)
Voltage output (for driving SSR) 12 VDC, 21 mA (with short-circuit protection circuit)
Control method ON/OFF or 2-PID (with auto-tune and self-tune)
Alarm output SPST-NO, 250 VAC, 1 A (resistive load)
Setting method Digital setting using front panel keys (functionality set-up with DIP switch)
Indication 7-segment digital display (character height: 13.5 mm) and deviation indicators
Ambient temperature -10 to 55°C (with no condensation or icing)
Setting/indication accuracy ±0.5% of indication value or ±1 °C, whichever is greater ±1 digit max.
Hysteresis (for ON/OFF control) 0.2% FS (0.1% FS for multi-input (thermocouple/platinum resistance thermometer) models)
Proportional band (P) 1 to 999°C (automatic adjustment using AT/ST)
Integral time (I) 0 to 1,999 s (automatic adjustment using AT/ST)
Derivative time (D) 0 to 1,999 s (automatic adjustment using AT/ST)
Control period 2/20 s
Sampling period 500 ms
Electrical life expectancy 100,000 operations min. (relay output models)
Weight Approx. 120 g (controller only)
Degree of protection Front panel: Equivalent to IP66; rear case: IP20; terminals: IP00
Memory protection EEPROM (non-volatile memory) (number of writes: 1,000,000)
Size in mm (HxWxD) 48x48x78
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19 Temperature controllers
E5_N General purpose controllers
Compact and intelligent
general purpose controllers
The E5_N general purpose line of temperature controllers is available in 4 standard
DIN formats. They all feature a high intensity dual LCD display with a wide viewing
angle. The whole series features 3 colour PV change for easy status recognition.
• Control mode: ON/OFF or 2-PID
• Control output: relay, hybrid relay, voltage (pulse) or linear current
• Power supply: 100/240 VAC or 24 VDC/VAC
• Easy PC connection for parameter cloning, setting and tuning
• Clear and intuitive set-up and operation
Ordering information
Note:- Output and Alarm Relays: 3 A/250 VAC, electrical life: 100,000 operations
- Output voltage (pulse): 12 V, 21 mA (ie. to drive solid state relays)
- Hybrid relay (long life relay) electrical life 1,000,000 operations
- Linear current: 0(4) to 20 mA
- Heater alarm / HA = heater burnout + SSR short detection + SSR overcurrent
- Voltage: Specify the power supply specifications (voltage) when ordering E5GN
Type Input Output Fixed option Alarms Order code
48x24 mm model (includes supply voltage indication)
On-panel temperature
(TC/Pt/mV)
relay – 1 relay E5GN-R1T-C AC100-240 E5GN-R1TD-C AC/DC24
RS-485 communication E5GN-R103T-C-FLK AC100-240 E5GN-R103TD-C-FLK AC/DC24
2 Event inputs E5GN-R1BT-C AC100-240 E5GN-R1BTD-C AC/DC24
voltage (pulse) – E5GN-Q1T-C AC100-240 E5GN-Q1TD-C AC/DC24
RS-485 communication E5GN-Q103T-C-FLK AC100-240 E5GN-Q103TD-C-FLK AC/DC24
2 Event inputs E5GN-Q1BT-C AC100-240 E5GN-Q1BTD-C AC/DC24
current (linear) – E5GN-C1T-C AC100-240 E5GN-C1TD-C AC/DC24
RS-485 communication E5GN-C103T-C-FLK AC100-240 E5GN-C103TD-C-FLK AC100-240
2 Event inputs E5GN-C1BT-C AC100-240 E5GN-C1BTD-C AC/DC24
relay – 2 relay E5GN-R2T-C AC100-240 E5GN-R2TD-C AC/DC24
RS-485 communication E5GN-R203T-C-FLK AC100-240 E5GN-R203TD-C-FLK AC100-240
2 Event inputs E5GN-R2BT-C AC100-240 E5GN-R2BTD-C AC/DC24
Heater Alarm E5GN-R2HT-C AC100-240 E5GN-R2HTD-C AC/DC24
voltage (pulse) – E5GN-Q2T-C AC100-240 E5GN-Q2TD-C AC/DC24
RS-485 communication E5GN-Q203T-C-FLK AC100-240 E5GN-Q203TD-C-FLK AC/DC24
2 Event inputs E5GN-Q2BT-C AC100-240 E5GN-Q2BTD-C AC/DC24
Heater Alarm E5GN-Q2HT-C AC100-240 E5GN-Q2HTD-C AC/DC24
analogue (mA/V) relay RS-485 communication 1 relay E5GN-R103L-FLK AC100-240 E5GN-R103LD-FLK AC/DC24
voltage (pulse) RS-485 communication E5GN-Q103L-FLK AC100-240 E5GN-Q103LD-FLK AC/DC24
current (linear) – E5GN-C1L-C AC100-240 E5GN-C1LD-C AC/DC24
Type Input Output Fixed option Alarms Order code
48x48 mm model (includes supply voltage indication)
On-panel temperature
(TC/Pt/mV)
relay – 2 relays E5CN-R2MT-500 AC100-240 E5CN-R2MTD-500 AC/DC24
voltage (pulse) E5CN-Q2MT-500 AC100-240 E5CN-Q2MTD-500 AC/DC24
linear current E5CN-C2MT-500 AC100-240 E5CN-C2MTD-500 AC/DC24
hybrid relay E5CN-Y2MT-500 AC100-240 –
analogue
(mA/V)
relay E5CN-R2ML-500 AC100-240 E5CN-R2MLD-500 AC/DC24
voltage (pulse) E5CN-Q2ML-500 AC100-240 E5CN-Q2MLD-500 AC/DC24
linear current E5CN-C2ML-500 AC100-240 E5CN-C2MLD-500 AC/DC24
hybrid relay E5CN-Y2ML-500 AC100-240 n/a
In-panel temperature
(TC/Pt/mV)
relay 2 relays E5CN-R2TU AC100-240 E5CN-R2TDU AC/DC24
voltage (pulse) E5CN-Q2TU AC100-240 E5CN-Q2TDU AC/DC24
linear current E5CN-C2TU AC100-240 E5CN-C2TDU AC/DC24
analogue
(mA/V)
relay E5CN-R2LU AC100-240 –
voltage (pulse) E5CN-Q2LU AC100-240 –
linear current E5CN-C2LU AC100-240 –
E5_N General purpose controllers
408
Accessories
E5CN option boards
(One slot available in each instrument; do no fit in E5CN-U types)
Note: Options with "N2" in the code, only fit in E5CN produced after January 2008 (marked N6
on the box)
E5CN series optional tools
Option Order code
2 Event inputs – – E53-CNBN2
– voltage (pulse) E53-CNQBN2
heater alarm – E53-CNHBN2
– power supply (12 VDC/20 mA) E53-CNPBN2
RS-485
serial
communications
(CompowayF/
Modbus RTU)
– – E53-CN03N2
– voltage (pulse) E53-CNQ03N2
heater alarm – E53-CNH03N2
3-phase HA – E53-CNHH03N2
– power supply (12 VDC/20 mA) E53-CNP03N2
– heater alarm voltage (pulse) E53-CNQHN2
3-phase HA voltage (pulse) E53-CNQHHN2
heater alarm power supply (12 VDC/20 mA) E53-CNPHN2
Option Order code
USB PC based configuration cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo
PC based parameter cloning software (free) ThermoMini
Standard 11 pin socket for E5CN-_ _ _ U type P2CF-11-E
E5_N General purpose controllers
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19 Temperature controllers
Note:- Output and Alarm Relays: 3 A/250 VAC, electrical life: 100,000 operations
- Output voltage (pulse): 12 V, 21 mA (ie. to drive solid state relays)
- Hybrid relay (long life relay) electrical life 1,000,000 operations
- Linear current: 0(4) to 20 mA
- Heater alarm / HA = heater burnout + SSR short detection + SSR overcurrent
E5AN/-EN option boards
(one slot available in each instrument) E5AN/-EN series optional tools
Specifications
Type Input Output Fixed option Alarms Order code (includes supply voltage indication)
48x96 mm model 96x96 mm model
On-panel temperature
(TC/Pt/mV)
relay – 3 relays E5EN-R3MT-500-N AC100-240 E5AN-R3MT-500-N AC100-240
E5EN-R3MTD-500-N AC/DC24 E5AN-R3MTD-500-N AC/DC24
heater alarm E5EN-R3HMT-500-N AC100-240 E5AN-R3HMT-500-N AC100-240
E5EN-R3HMTD-500-N AC/DC24 E5AN-R3HMTD-500-N AC/DC24
3-phase heater alarm E5EN-R3HHMT-500-N AC100-240 E5AN-R3HHMT-500-N AC100-240
E5EN-R3HHMTD-500-N AC/DC24 E5AN-R3HHMTD-500-N AC/DC24
voltage (pulse) E5EN-R3QMT-500-N AC100-240 E5AN-R3QMT-500-N AC100-240
hybrid relay E5EN-R3YMT-500-N AC100-240 E5AN-R3YMT-500-N AC100-240
power supply E5EN-R3PMT-500-N AC100-240 E5AN-R3PMT-500-N AC100-240
voltage (pulse) – E5EN-Q3MT-500-N AC100-240 E5AN-Q3MT-500-N AC100-240
E5EN-Q3MTD-500-N AC/DC24 E5AN-Q3MTD-500-N AC/DC24
heater alarm E5EN-Q3HMT-500-N AC100-240 E5AN-Q3HMT-500-N AC100-240
E5EN-Q3HMTD-500-N AC/DC24 E5AN-Q3HMTD-500-N AC/DC24
3-phase heater alarm E5EN-Q3HHMT-500-N AC100-240 E5AN-Q3HHMT-500-N AC100-240
E5EN-Q3HHMTD-500-N AC/DC24 E5AN-Q3HHMTD-500-N AC/DC24
voltage (pulse) E5EN-Q3QMT-500-N AC100-240 E5AN-Q3QMT-500-N AC100-240
hybrid relay E5EN-Q3YMT-500-N AC100-240 E5AN-Q3YMT-500-N AC100-240
power supply E5EN-Q3PMT-500-N AC100-240 E5AN-Q3PMT-500-N AC100-240
linear current – E5EN-C3MT-500-N AC100-240 E5AN-C3MT-500-N AC100-240
E5EN-C3MTD-500-N AC/DC24 E5AN-C3MTD-500-N AC/DC24
voltage (pulse) E5EN-C3QMT-500-N AC100-240 E5AN-C3QMT-500-N AC100-240
hybrid relay E5EN-C3YMT-500-N AC100-240 E5AN-C3YMT-500-N AC100-240
analogue
(mA/V)
relay – E5EN-R3ML-500-N AC100-240 E5AN-R3ML-500-N AC100-240
heater alarm E5EN-R3HML-500-N AC100-240 E5AN-R3HML-500-N AC100-240
voltage (pulse) – E5EN-Q3ML-500-N AC100-240 E5AN-Q3ML-500-N AC100-240
heater alarm E5EN-Q3HML-500-N AC100-240 E5AN-Q3HML-500-N AC100-240
hybrid relay E5EN-Q3YML-500-N AC100-240 E5AN-Q3YML-500-N AC100-240
linear current – E5EN-C3ML-500-N AC100-240 E5AN-C3ML-500-N AC100-240
Option Order code
RS-232C communications (CompoWay/F/Modbus) E53-EN01
RS-485 communications (CompoWay/F/Modbus) E53-EN03
event input E53-AKB
Option Order code
USB PC based configuration cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo
PC based parameter cloning software (free) ThermoMini
Supply voltage 100 to 240 VAC 50/60 Hz or 24 VAC, 50/60Hz; 24 VDC
Heater alarm yes, optional, choice of 1 or 3 phase
Thermocouple input type K, J, T, E, L, U, N, R, S, B, W or PL II
RTD input type Pt100, JPt100
Linear input type mV or "T" models
mA and V on "L" models
Control mode ON/OFF, 2-PID (heat or heat/cool)
Accuracy Thermocouple ± 0.3% (E5CN-U ± 1%)
Platinum resistance ± 0.2%
Analogue input ± 0.2% FS
Auto-tuning yes, 40% and 100% MV output limit selection. When using Heat/Cool: automatic cool gain adjustment
Self-tuning yes
RS-232C Only for AN/-EN: Optional, Protocol CompowayF or Modbus freely selectable
RS-485 optional, CompowayF or Modbus selectable
Event input optional
QLP port (USB connection PC) yes
Ambient temperature -10 to 55°C
IP Rating front panel IP66
Sampling period 250 ms
410
CelciuXº General purpose controllers
CelciuXº - Multi-Loop temperature control –
Control and Connectivity
CelciuXº is designed to handle complex temperature profiles thanks to Omron’s
unique Gradient temperature Control (GTC) algorithm and to offer easy program-less
communication with Omron and third-party PLCs and HMI. Above all, CelciuXº
incorporates all “simple to use” clever temperature control technology, like 2-PID,
disturbance control and various ways of tuning.
• Interfaces to a wide range of industrial networks
• Reduced engineering due to Program-less communications, Smart Active Parts
and Function Block Libraries
• Available with screw terminals and screw-less clamp terminals
• One unit handling various types of input, such as Pt, Thermocouple,
mA, and V input
• Gradient Temperature Control (GTC)
Ordering information
Accessories
Current transformer
Communications and cables
Type Control points Control outputs Auxiliary outputs Other functions Terminal Order code
Basic unit 2 2 voltage (puls) 2 transistor (NPN) *1
*1 For heating/cooling control applications, the auxiliary outputs on the 2-point models are used for cooling control.
On the 4-point models, heating/cooling control can be performed for two input points only.
2 CT input *2 + 2 event input
*2 When using the heater burnout alarm, purchase a Current Transformer (E54-CT1 or E54-CT3) separately.
M3 screws EJ1N-TC2A-QNHB
Basic unit 2 2 voltage (puls) 2 transistor (NPN) *1 2 CT input *2 + 2 event input Screw-less clamp EJ1N-TC2B-QNHB
Basic unit 2 2 current 2 transistor (NPN) *1 2 event input M3 screws EJ1N-TC2A-CNB
Basic unit 2 2 current 2 transistor (NPN) *1 2 event input Screw-less clamp EJ1N-TC2B-CNB
Basic unit 4 4 voltage (puls) – – M3 screws EJ1N-TC4A-QQ
Basic unit 4 4 voltage (puls) – – Screw-less clamp EJ1N-TC4B-QQ
High function unit – – 4 transistor (NPN) 4 event input M3 screws EJ1N-HFUA-NFLK
High function unit – – 4 transistor (NPN) 4 event input Screw-less clamp EJ1N-HFUB-NFLK
DeviceNet unit – – – – Screw connector EJ1N-HFUB-DRT
End unit *3
*3 An End unit is always required for connection to a Basic unit or an HFU. An HFU cannot operate without a Basic unit.
– – 2 transistor (NPN) – M3 screws EJ1C-EDUA-NFLK
End unit *3 – – 2 transistor (NPN) – Removable Connector EJ1C-EDUC-NFLK
Type Control points Control outputs Auxiliary outputs Other functions Terminal Order code
Basic unit 2 (GTC) 2 voltage (puls)*1
*1 Heating/cooling control is not supported for gradient temperature control.
2 transistor (NPN) 2 CT input*2
*2 When using the heater burnout alarm, use a Current Transformer (E54-CT1 or E54-CT3) (sold separately).
M3 screws EJ1G-TC2A-QNH
Basic unit 2 (GTC) 2 voltage (puls)*1 2 transistor (NPN) 2 CT input*2 Screw-less clamp EJ1G-TC2B-QNH
Basic unit 4 (GTC) 4 voltage (puls)*1 – – M3 screws EJ1G-TC4A-QQ
Basic unit 4 (GTC) 4 voltage (puls)*1 – – Screw-less clamp EJ1G-TC4B-QQ
High function unit – (GTC) – 4 transistor (NPN) – M3 screws EJ1G-HFUA-NFLK
High function unit – (GTC) – 4 transistor (NPN) – Screw-less clamp EJ1G-HFUB-NFLK
End unit*3
*3 An End-unit (EDU) is always required to connect an HFU and or a Basic TC unit for Communications and Power supply.
A GTC (Gradient Temperature Control) basic TC unit always requires a GTC HFU unit.
– – 2 transistor (NPN) – M3 screws EJ1C-EDUA-NFLK
End unit*3 – – 2 transistor (NPN) – Removable Connector EJ1C-EDUC-NFLK
Diameter Order code
5.8 dia. E54-CT1
12.0 dia. E54-CT3
Description Order code
G3ZA connecting cable 5 meter EJ1C-CBLA050
USB programming cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo EST2-2C-MV4
PROFIBUS Gateway PRT1-SCU11
CelciuXº General purpose controllers
411
19 Temperature controllers
Specifications
Item Type EJ1_-TC2 EJ1_-TC4
Power supply voltage 24 VDC
Operating voltage range 85% to 110% of rated voltage
Power consumption 4 W max. (at maximum load) 5 W max. (at maximum load)
Input (see note)*1
*1 Inputs are fully multi-input. Therefore, platinum resistance thermometer, thermocouple, infrared thermosensor, and analogue input can be selected.
Thermocouple: K, J, T, E, L, U, N, R, S, B, W, PLII
ES1B Infrared Thermosensor: 10 to 70°C, 60 to 120°C, 115 to 165°C, 140 to 260°C.
Analogue input: 4 to 20 mA, 0 to 20 mA, 1 to 5 V, 0 to 5 V, 0 to 10 V
Platinum resistance thermometer: Pt100, JPt100
Input impedance Current input: 150max., voltage input: 1 M min.
Control outputs Voltage output Output voltage: 12 VDC ±15%, max. load current: 21 mA (PNP models with short-circuit protection circuit)
Transistor output Max. operating voltage: 30 V, max. load current: 100 mA –
Current output Current output range: 4 to 20 mA or 0 to 20 mA DC
Load: 500 max. (including transfer output)
(Resolution: Approx: 2,800 for 4 to 20 mA DC,
approx. 3,500 for 0 to 20 mA DC)
–
Event inputs Input points 2 –
Contact input ON: 1 k max., OFF. 100 k min. –
Non-contact input ON: Residual voltage: 1.5 V max.,
OFF: Leakage current: 0.1 mA max.
–
Outflow current: approx. 4 mA per point –
Number of input and control points Input points: 2, control points: 2 Input points: 4, control points: 4
Setting method Via communications
Control method ON/OFF control or 2-PID (with autotuning, selftuning, Heat & Cool autotuning and non-linear cool output selection)
Other functions Two-point input shift, digital input filter, remote SP, SP ramp, manual manipulated variable, manipulated variable limiter, interference overshoot adjustment,
loop burnout alarm, RUN/STOP, banks, I/O allocations, etc.
Alarm output 2 points via End unit
Communication RS-485, PROFIBUS, Modbus, DeviceNet RS-485, PROFIBUS, Modbus, DeviceNet
Size in mm (WxHxD) 31x96x109
Weight 180 g
Ambient temperature range Operating -10°C to 55°C, Storage -25°C to 65°C (with no icing or condensation)
Ambient humidity range Operating. 25% to 85% (with no condensation)
412
E5_N-H/E5_N-HT Advanced and Multi-Loop controllers
Universal compact digital
process controllers
The E5_N-H series of process controllers take the proven concept of the general
purpose E5_N series to a process level. Main features of the E5_N-H series are
universal inputs, process outputs and options such as transfer output, remote setpoint
and setvalue programmer.
• Control mode: ON/OFF or 2-PID, Valve control on EN-H/AN-H
• Control output: relay, voltage (pulse), SSR, linear current and voltage
• Power supply: 100/240 VAC or 24 VDC/VAC
• Easy PC connection for parameter cloning, setting and tuning
• Clear and intuitive set-up and operation
Ordering information
Note: - Output and Alarm Relays: 3 A/250 VAC, electrical life: 100,000 operations
- Output voltage (pulse): 12 V, 21 mA (ie. to drive solid state relays)
- Linear current: 0(4) to 20 mA
- Linear voltage output: 0 to 10 V
Accessories
E5CN-H option boards
(One slot available in each instrument)
Type Input Output Fixed option Alarms Order code
48x48 mm model (includes supply voltage indication)
On-panel Universal
TC/Pt/mV
mA/V
Relay output – 3 software
alarms
2 SUB
outputs
E5CN-HR2M-500 AC100-240 E5CN-HR2MD-500 AC/DC24
Voltage (pulse) E5CN-HQ2M-500 AC100-240 E5CN-HQ2MD-500 AC/DC24
Current output E5CN-HC2M-500 AC100-240 E5CN-HC2MD-500 AC/DC24
Linear voltage output E5CN-HV2M-500 AC100-240 E5CN-HV2MD-500 AC/DC24
Relay output SV programmer
(8 programs of
32 segments
E5CN-HTR2M-500 AC100-240 E5CN-HTR2MD-500 AC/DC24
Voltage (pulse) E5CN-HTQ2M-500 AC100-240 E5CN-HTQ2MD-500 AC/DC24
Current output E5CN-HTC2M-500 AC100-240 E5CN-HTC2MD-500 AC/DC24
Linear voltage output E5CN-HTV2M-500 AC100-240 E5CN-HTV2MD-500 AC/DC24
Option Order code
Event inputs E53-CNBN2
Event inputs Control output 2
Voltage (for driving SSR)
E53-CNQBN2
Event inputs Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNHBN2
Event inputs Transfer output E53-CNBFN2
Communications
RS-232C
Control output 2
Voltage (for driving SSR)
E53-CN01N2
Communications
RS-232C
E53-CNQ01N2
Communications
RS-232C
Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNH01N2
Communications
RS-485
E53-CN03N2
Communications
RS-485
Control output 2
Voltage (for driving SSR)
E53-CNQO3N2
Communications
RS-485
Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNH03N2
Communications
RS-485
3-phase heater burnout/SSR failure/
Heater overcurrent detection
E53-CNHH03N2
Control output 2
Voltage (for driving SSR)
Transfer output E53-CNQFN2
Control output 2
Voltage (for driving SSR)
Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNQHN2
Control output 2
Voltage (for driving SSR)
3-phase heater burnout/SSR failure/
Heater overcurrent detection
E53-CNQHHN2
E5_N-H/E5_N-HT Advanced and Multi-Loop controllers
413
19 Temperature controllers
Note: - All E5EN-H/AN-H have 2 event inputs
- All E5EN-H/AN-H have Remote Setpoint 4 to 20 mA input
Specifications E5CN-H/EN-H/AN-H E5AN-H/EN-H output option boards
(2 slots available in E5_N-HAA__-500 models:
SS models have 2 fixed SSR output modules)
E5AN-H/EN-H option boards
(one slot available in each instrument)
E5AN-H/EN-H series optional tools
Control method Auxiliary output Control output 1/2 Heater burnout Transfer output Order code (includes supply voltage indication)
96x96 mm model 48x96 mm model
Basic 2 alarm relays none fitted, 2 slots 1-phase E5AN-HAA2HBM-500 AC100-240 E5EN-HAA2HBM-500 AC100-240
none fitted, 2 slots E5AN-HAA2HBMD-500 AC/DC24 E5EN-HAA2HBMD-500 AC/DC24
2 SSR output fitted E5AN-HSS2HBM-500 AC100-240 E5EN-HSS2HBM-500 AC100-240
2 SSR output fitted E5AN-HSS2HBMD-500 AC/DC24 E5EN-HSS2HBMD-500 AC/DC24
none fitted, 2 slots 3-phase 4 to 20 mA
output
E5AN-HAA2HHBFM-500 AC100-240 E5EN-HAA2HHBFM-500 AC100-240
none fitted, 2 slots E5AN-HAA2HHBFMD-500 AC/DC24 E5EN-HAA2HHBFMD-500 AC/DC24
2 SSR output fitted E5AN-HSS2HHBFM-500 AC100-240 E5EN-HSS2HHBFM-500 AC100-240
2 SSR output fitted E5AN-HSS2HHBFMD-500 AC/DC24 E5EN-HSS2HHBFMD-500 AC/DC24
3 alarm relays none fitted, 2 slots E5AN-HAA3BFM-500 AC100-240 E5EN-HAA3BFM-500 AC100-240
none fitted, 2 slots E5AN-HAA3BFMD-500 AC/DC24 E5EN-HAA3BFMD-500 AC/DC24
2 SSR output fitted E5AN-HSS3BFM-500 AC100-240 E5EN-HSS3BFM-500 AC100-240
2 SSR output fitted E5AN-HSS3BFMD-500 AC/DC24 E5EN-HSS3BFMD-500 AC/DC24
Valve controller 2 alarm relays 2 relay output fitted E5AN-HPRR2BM-500 AC100-240 E5EN-HPRR2BM-500 AC100-240
E5AN-HPRR2BMD-500 AC/DC24 E5EN-HPRR2BMD-500 AC/DC24
4 to 20 mA
output
E5AN-HPRR2BFM-500 AC100-240 E5EN-HPRR2BFM-500 AC100-240
E5AN-HPRR2BFMD-500 AC/DC24 E5EN-HPRR2BFMD-500 AC/DC24
SV programmer
(8 programs of
32 segments
2 alarm relays none fitted, 2 slots 1-phase E5AN-HTAA2HBM-500 E5EN-HTAA2HBM-500 AC100-240
E5AN-HTAA2HBMD-500 E5EN-HTAA2HBMD-500 AC/DC24
3-phase 4 to 20 mA
output
E5AN-HTAA2HHBFM-500 E5EN-HTAA2HHBFM-500
E5AN-HTAA2HHBFMD-500 E5EN-HTAA2HHBFMD-500
3 alarm relays E5AN-HTAA3BFM-500 E5EN-HTAA3BFM-500
E5AN-HTAA3BFMD-500 E5EN-HTAA3BFMD-500
SV programmer and
valve controller
2 alarm relays 2 relay output fitted E5AN-HTPRR2BM-500 E5EN-HTPRR2BM-500
E5AN-HTPRR2BMD-500 E5EN-HTPRR2BMD-500
4 to 20 mA
output
E5AN-HTPRR2BFM-500 E5EN-HTPRR2BFM-500
E5AN-HTPRR2BFMD-500 E5EN-HTPRR2BFMD-500
Supply voltage 100 to 240 VAC 50/60 Hz or 24 VAC, 50/60Hz; 24 VDC
Sensor input Thermocouple: K, J, T, E, L, U, N, R, S, B, W or PL II
Platinum resistance thermometer: Pt100 or JPt100
Current input: 4 to 20 mA or 0 to 20 mA
Voltage input: 1 to 5 V, 0 to 5 V or 0 to 10 V
Control mode ON/OFF, 2-PID and valve (PRR)
Accuracy Thermocouple: (± 0.1% of indicated value or ±1°C, whichever
is greater) ± digit max. *1
Platinum resistance thermometer: (± 0.1% of indicated value
or ± 0.5°C, whichever is greater) ± 1 digit max.
Analogue input: ± 0.1% FS ± 1 digit max.
Auto-tuning yes, 40% and 100% MV output limit selection. When using
Heat/Cool: automatic cool gain adjustment
Self-tuning yes
RS-232C/RS-422/RS-485 optional, CompowayF or Modbus selectable
Event input Optional (Standard 2 event input in EN-H/AN-H)
QLP port (USB connection PC) yes
Ambient temperature -10 to 55°C
IP Rating front panel IP66
Sampling period 60 ms
Option Order code
Relay E53-RN
Voltage (pulse) PNP 12VDC E53-QN
Voltage (pulse) NPN 12VDC E53-Q3
Voltage (pulse) NPN 24VDC E53-Q4
Linear 4 to 20 mA E53-C3N
Linear 0 to 20 mA E53-C3DN
Linear 0 to 10 V E53-V34N
Linear 0 to 5 V E53-V35N
Option Order code
RS-232C communications (CompoWay/F/Modbus) E53-EN01
RS-422 communications (CompoWay/F/Modbus) E53-EN02
RS-485 communications (CompoWay/F/Modbus) E53-EN03
event input E53-AKB
Option Order code
USB PC based configuration cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo EST2-2C-MV4
414
E5_R/E5_R-T Advanced and Multi-Loop controllers
Fast, accurate and equipped for
application specific needs
The E5_R series provides you with high accuracy inputs (0.01°C for Pt100) and
a 50 ms sample and control cycle for all four loops. Its unique Disturbance Overshoot
Reduction Adjustment ensures solid, robust control.
• Easy and clear read-out thanks to bright Liquid Crystal Display
• Exceptional versatility – multi-loop control, cascade control, and valve control
• Easy integration with DeviceNet, PROFIBUS or Modbus
• SV programmer optional, 32 programs with up to 256 segments
Ordering information
Note:- Voltage: Specify the power supply specifications (voltage) when ordering.
- Standard = heat and/or cool PID control, valve = valve positioning (relay up/down) (PRR)
- max 2 = 2 loops heat and/or cool or 1 loop cascade, ratio or remote SP
- max 4 = 4 loops heat and/or cool
- 1, 2 or 4 = number of analogue universal input 1 + pot = 1 universal and 1 slide wire feedback from valve
- QC = voltage (pulse) or current (switch), Q = voltage (pulse), C = current, 4R = 4 two pole relay, 2T = two transistor output NPN
Functions Loops Input Output Comms Order code
analogue Event Control Alarm 96x96 mm Supply voltage
standard 1 1 2 2 QC+Q 4R – E5AR-Q4B AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 4R RS-485 E5AR-Q43B-FLK AC100-240 –
standard 1 1 6 2 QC+Q 4R RS-485 E5AR-Q43DB-FLK AC100-240 –
standard 1 1 6 4 QC+Q+C+C 4R RS-485 E5AR-QC43DB-FLK AC100-240 or DC/AC 24
standard max 2 2 4 2 QC+Q 4R RS-485 E5AR-Q43DW-FLK AC100-240 –
standard max 2 2 4 4 QC+Q+QC+Q 4R RS-485 E5AR-QQ43DW-FLK AC100-240 or DC/AC 24
standard max 4 4 4 4 QC+Q+QC+Q 4R RS-485 E5AR-QQ43DWW-FLK AC100-240 –
standard 1 1 2 2 C+C 4R – E5AR-C4B AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R RS-485 E5AR-C43B-FLK AC100-240 –
standard 1 1 6 2 C+C 4R RS-485 E5AR-C43DB-FLK AC100-240 –
standard max 2 2 4 2 C+C 4R RS-485 E5AR-C43DW-FLK AC100-240 –
standard max 4 4 4 4 C+C+C+C 4R RS-485 E5AR-CC43DWW-FLK AC100-240 or DC/AC 24
valve 1 1 + pot 4 2 R+R 4R – E5AR-PR4DF AC100-240 or DC/AC 24
valve 1 1 + pot 4 4 R+R+QC+Q 4R RS-485 E5AR-PRQ43DF-FLK AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 4R DeviceNet E5AR-Q4B-DRT AC100-240 or DC/AC 24
standard 1 1 2 4 QC+Q+C+C 4R DeviceNet E5AR-QC4B-DRT AC100-240 or DC/AC 24
standard max 2 2 – 4 QC+Q+QC+Q 4R DeviceNet E5AR-QQ4W-DRT AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R DeviceNet E5AR-C4B-DRT AC100-240 or DC/AC 24
standard max 4 4 – 4 C+C+C+C 4R DeviceNet E5AR-CC4WW-DRT AC100-240 or DC/AC 24
valve 1 1 + pot – 2 R+R 4R DeviceNet E5AR-PR4F-DRT AC100-240 or DC/AC 24
valve 1 1 + pot – 4 R+R+QC+Q 4R DeviceNet E5AR-PRQ4F-DRT AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R – E5AR-TQ4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 C+C 4R – E5AR-TC4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R RS-485 E5AR-TQ43B-FLK AC100-240 –
SV programmer 1 1 2 2 C+C 4R RS-485 E5AR-TC43B-FLK AC100-240 –
SV programmer 1 1 10 2 QC+Q 10T RS-485 E5AR-TQE3MB-FLK AC100-240 –
SV programmer 1 1 10 2 C+C 10T RS-485 E5AR-TCE3MB-FLK AC100-240 –
SV programmer 1 1 10 4 QC+Q+C+C 10T RS-485 E5AR-TQCE3MB-FLK AC100-240 or DC/AC 24
SV programmer max 2 2 4 2 QC+Q 4R RS-485 E5AR-TQ43DW-FLK AC100-240 –
SV programmer max 2 2 4 2 C+C 4R RS-485 E5AR-TC43DW-FLK AC100-240 –
SV programmer max 2 2 8 4 QC+Q+QC+Q 10T RS-485 E5AR-TQQE3MW-FLK AC100-240 or DC/AC 24
SV programmer max 4 4 8 4 C+C+C+C 10T RS-485 E5AR-TCCE3MWW-FLK AC100-240 or DC/AC 24
SV programmer max 4 4 8 4 QC+Q+QC+Q 10T RS-485 E5AR-TQQE3MWW-FLK AC100-240 –
SV programmer + valve 1 1 + pot 4 2 R+R 4R – E5AR-TPR4DF AC100-240 or DC/AC 24
SV programmer + valve 1 1 + pot 8 4 R+R+QC+Q 10T RS-485 E5AR-TPRQE3MF-FLK AC100-240 or DC/AC 24
E5_R/E5_R-T Advanced and Multi-Loop controllers
415
19 Temperature controllers
Note:- Voltage: Specify the power supply specifications (voltage) when ordering.
- Standard = heat and/or cool PID control, valve = valve positioning (relay up/down) (PRR)
- max 2 = 2 loops heat and/or cool or 1 loop cascade, ratio or remote SP
- max 4 = 4 loops heat and/or cool
- 1, 2 or 4 = number of analogue universal input 1 + pot = 1 universal and 1 slide wire feedback from valve
- QC = voltage (pulse) or current (switch), Q = voltage (pulse), C = current, 4R = 4 two pole relay, 2T = two transistor output NPN
Accessories
E5_R/E5_R-T optional tools
Specifications
Functions Loops Input Output Comms Order code
analogue Event Control Alarm 48x96 mm Supply voltage
standard 1 1 2 2 QC+Q 4R – E5ER-Q4B AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 4R RS-485 E5ER-Q43B-FLK AC100-240 –
standard 1 1 2 4 QC+Q+C+C 4R RS-485 E5ER-QC43B-FLK AC100-240 or DC/AC 24
standard 1 1 6 2 QC+Q 2T RS-485 E5ER-QT3DB-FLK AC100-240 –
standard max 2 2 4 2 QC+Q 2T RS-485 E5ER-QT3DW-FLK AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R – E5ER-C4B AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R RS-485 E5ER-C43B-FLK AC100-240 –
standard 1 1 6 2 C+C 2T RS-485 E5ER-CT3DB-FLK AC100-240 –
standard max 2 2 4 2 C+C 2T RS-485 E5ER-CT3DW-FLK AC100-240 or DC/AC 24
valve 1 1 + pot 4 2 R+R 2T – E5ER-PRTDF AC100-240 or DC/AC 24
valve 1 1 + pot – 4 R+R+QC+Q 4R RS-485 E5ER-PRQ43F-FLK AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 2T DeviceNet E5ER-QTB-DRT AC100-240 or DC/AC 24
standard max 2 2 – 2 QC+Q 2T DeviceNet E5ER-QTW-DRT AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 2T DeviceNet E5ER-CTB-DRT AC100-240 or DC/AC 24
standard max 2 2 – 2 C+C 2T DeviceNet E5ER-CTW-DRT AC100-240 or DC/AC 24
valve 1 1 + pot – 2 R+R 2T DeviceNet E5ER-PRTF-DRT AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R – E5ER-TQ4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 C+C 4R – E5ER-TC4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R RS-485 E5ER-TQC43B-FLK AC100-240 or DC/AC 24
SV programmer max 2 2 4 2 QC+Q 2T RS-485 E5ER-TQT3DW-FLK AC100-240 or DC/AC 24
SV programmer max 2 2 4 2 C+C 2T RS-485 E5ER-TCT3DW-FLK AC100-240 or DC/AC 24
SV programmer + valve 1 1 + pot 4 2 R+R 2T – E5ER-TPRTDF AC100-240 or DC/AC 24
SV programmer + valve 1 1 + pot – 3 R+R + QC 4R RS-485 E5ER-TPRQ43F-FLK AC100-240 or DC/AC 24
Terminal covers Order code
Terminal cover for E5AR E53-COV14
Terminal cover for E5ER E53-COV15
Option Order code
PC based configuration and tuning software CX-Thermo EST2-2C-MV4
Thermocouple input type K, J, T, E, L, U, N, R, S, B, W
RTD input type Pt100
Linear input type mA, V
Control mode 2-PID or ON/OFF control
Accuracy ±0.1% FS
Auto-tuning yes
RS-485 optional
Event input optional
Ambient temperature -10 to 55°C
IP rating front panel IP66
Sampling period 50 ms
Size in mm (HxWxD) E5ER: 96x48x110
E5AR: 96x96x110
416
PRT1-SCU11 Auxiliaries
Omron’s intelligent PROFIBUS and
CompoWay/F gateway
This gateway supports all CompoWay/F equipped products, including
temperature controllers, digital panel indicators, etc. It can also be used for
connecting MCW151-E and E5_K series.
• Cost-effectively integrates basic instruments into a PROFIBUS network
• Requires no complex protocol conversion writing
• Has function blocks for drag-and-drop configuration
• Connects up to 15 instruments to a single PROFIBUS point
Ordering information
Supports all CompoWay/F equipped units,
but has "drag-and-drop" function blocks for
• E5AN/E5EN/E5CN/E5GN
• E5ZN and CelciuXº (EJ1)
• E5AR/E5ER
• E5AK/E5EK
Specifications
ES1B
Achieve low-cost measurements with an
infrared thermosensor
This infrared thermosensor provides an accurate, stable and cost-effective way to
measure the temperature of objects. It behaves just like a standard K-type thermocouple,
which enables it to operate with any temperature controller or alarm unit.
• Cost-effective infrared thermosensor
• Contactless, meaning no deterioration, unlike thermocouples
• 4 temperature ranges available: 10-70°C, 60-120°C, 115-165°C and 140-260°C
• Response speed 300 ms
Ordering information
Dimensions (unit: mm)
Specifications
Name Order code
PROFIBUS remote terminal serial communications unit PRT1-SCU11
Storage temperature -20 to +75°C
Ambient temperature 0 to 55°C
Ambient humidity 10 to 90% (non-condensing)
EMC compliance EN 50081-2, EN 61131-2
Power supply +24 VDC (+10%/-15%)
Current consumption 80 mA (typical)
Weight 125 g (typical)
Communication interface RS-485 based PROFIBUS-DP
RS-422A Host link
RS-485 CompoWay/F
RS-232C Peripheral
Port supporting connection to thermotools
Size in mm (HxWxD) 90x40x65
Appearance and sensing
characteristics
Specification Order code
10 to 70°C ES1B 10-70C
60 to 120°C ES1B 60-120C
115 to 165°C ES1B 115-165C
140 to 260°C ES1B 140-260C 2 dia. 20 dia.
2 mm 20 mm 40 mm 60 mm
40 dia. 60 dia.
14.2 dia.
36.5
17.8
15
6.5
44.5 3,000
ABS resin
PVC-covered
(−25°C to 70°C)
Polyolefin tube
Screw M18×1.0
Green, output +
White, output −
Orange, power +
Shield, power −
Power supply voltage 12/24 VDC
Current consumption 20 mA max.
Accuracy ±5°C ±2% PV or ±2°C, whichever is larger
±10°C ±4% PV or ±4°C, whichever is larger
±30°C ±6% PV or ±6°C, whichever is larger
±40°C ±8% PV or ±8°C, whichever is larger
Reproducibility ±1% PV or ±1°C, whichever is larger
Temperature drift 0.4°C/°C max.
Receiver element Thermopile
Response speed Approximately 300 ms at response rate of 63%
Operating temperature -25 to 70°C (with no icing or condensation)
Allowable ambient humidity 35 to 85%
Degree of protection IP65
Size in mm head: 17.8 dia.×44.5 (screw M18×1.0),
cable 3,000
417
19 Temperature controllers
ES1C Auxiliaries
Achieve Superior Environmental Resistance
and a Wide Measurement Range of 0 to
400°C.
This gateway supports all CompoWay/F equipped products, including
temperature controllers, digital panel indicators, etc. It can also be used for
connecting MCW151-E and E5_K series.
• Flexible placement with slim cylindrical shape and long focus with a distance of
500 mm and area diameter of 80 mm.
• The SUS body and silicon lens resist ambient operating temperatures of up to
70×C and resist dust and water to the equivalent of IP67.
• Fast measurement with high-speed response of 100 ms/90%.
• Strong resistance to noise with output of 4 to 20 mA.
Ordering information
Measurement Range
Ratings and Characteristics
Dimensions (unit: mm)
Specification (measuring temperature range) Order code
0 to 400°C ES1C-A40
110 dia.
80 dia. 70 dia.
300
500
1000
[mm]
Note: The measurement range is the measurement diameter for an optical response of
90%. Make sure that the actual object to be measured is sufficiently larger than the
measurement diameters in the above figure.
Item Model ES1C
Power supply voltage 12 to 24 VDC
Operating voltage range 90% to 110% of rated voltage
Current consumption 70 mA max.
Measuring temperature range 0 to 400C
Measurement accuracy 0 to 200C: 2C, 201 to 400C: 1% (emissivity: 0.95)
Response time 100 ms/90%
Reproducibility 1C of reading value
Measurement wavelength 8 to 14 m
Light-receiving element Thermopile
Emissivity 0.95 fixed
Current output 4 to 20 mA DC, Load: 250 max.
Ambient temperature range Operating: 0 to 70C, Storage: 20 to 70C
(with no icing or condensation)
Ambient humidity range Operating and storage: 35% to 85%
Vibration resistance
(destruction)
1.5-mm amplitude at 10 to 55 Hz for 2 hours each
in the X, Y, and Z directions
Weight 180 g
Degree of protection Equivalent to IP67
12 dia. (lens diameter)
M18×P1.0
(cable length)
24 120 2,000
60
(threaded section)
S8VS S8JX-G
Compact
S8VT
Single-phase
Supply voltage?? Power factor correction??
Three-phase
Slim
S8VM
Yes No
PREVENT YOUR SYSTEM FROM STOPPING
The buffer block prevents equipment stoppage, data loss and other problems resulting
from momentary power failures. One S8TS-DCBU-02 buffer block provides a back-up
time of 500 ms at an output current of 2.5 A. Can be wired to the 24 VDC output from
any switch mode power supply
• Connects to both single-phase and three-phase 24 VDC power supplies
• Connects to an S8TS power supply via an S8T-BUS03 bus line connector
• Parallel connection up to 4 units to increase back-up time and capacity
S8TS-DCBU-02 – Buffer block against momentary power failures
418
Page 422 Page 427
Power supplies
Page 423 Page 424
S8TS
Which type of power supply you are looking for?
S8T-DCBU-01
Modular
S8T-DCBU-02
DC back-up
S8TS DC battery
back-up up to
several minutes
S8TS buffer block
momentary up to
500 ms
419
20 Power supplies
Page 425 Page 426 Page 426
420
421
20 Power supplies
Selection table Power supplies
Category Compact
Power Supplies Slim Power Supplies Modular
Selection criteria
Model S8VS S8VT S8VM S8JX-G S8TS
Phases Single-phase
Rated voltage 100 to 240 VAC
Voltage 24 V 24 V 12 V 24 V 5 V 12 V 15 V 24 V 5 V 12 V 24 V
Power
3 W – – – – – – – – – – –
7.5 W – – – – – – – – – – –
10 W – – – – – – – – – – –
15 W 0.65 A – 1.3 A 0.65 A 3 A 1.3 A 1 A 0.65 A – – –
25 W – – – – – – – – 5 A – –
30 W 1.3 A – 2.5 A 1.3 A – – – – – 2.5 A –
35 W 7 A 3 A 2.4 A 1.5 A – 2.5 A –
50 W – – 4.3 A 2.2 A 10 A 4.2 A – 2.1 A – – –
60 W 2.5 A – – – – – – – – 5 A 2.5 A
90 W – – – – – – – – – 7.5 A –
100 W – – 8.5 A 4.5 A 20 A 8.5 A – 4.5 A – – –
120 W 5 A 5 A – – – – – – – 10 A 5 A
150 W – – 12.5 A 6.5 A – – – 6.5 A – – –
180 W – – – – – – – – – – 7.5 A
240 W 10 A 10 A – – – – – – – – 10 A
300 W – – 27 A 14 A – – – 14 A – – –
480 W 20 A 20 A – – – – – – – – –
600 W – – 53 A 27 A – – – 27 A – – –
960 W – 40 A – – – – – – – – –
1500 W – – – 70 A – – – – – – –
Features
Conforms to
EN61000-3-2
with PFC – – – – with
PFC
with
PFC
with
PFC
DC back-up – – – – – – – –
Capacitor back-up – – – – – – – –
Undervoltage alarm – – – – – –
Overvoltage protection
Overload protection
DIN-rail mounting
Screw mounting
(with bracket)
– only 40 A – – –
EMI Class B – – – – – –
UL Class 2 only 60 W – – – – – – –
N+1 redundancy – – – – – – – –
Parallel operation – – – – – – –
Series operation
Page 422 427 423 424 425
Standard Available – No/not available
422
S8VS Single-phase
Compact power supply
The S8VS is our standard industrial din-rail mounted power supply. It is built to last
forever. Up to 60 W we provide them into a plastic housing, from 120 W the S8VS
is built in strong metal case. The full ranges provide a very good dimension/output
power ratio to optimize panel space uses. The range covers 6 models at 24 VDC with
wattage of 15, 30, 60, 120, 240 and 480 W. The 15 and 30 W are also available in
5 or 12 VDC output voltage. The range withstands high vibration and shocks.
The S8VS are fan-less power supplies.
• Wide AC input range from 85 to 264 VAC
• Micro S8VS output power range 15 and 30 W at 5, 12 and 24 VDC
• Micro can mounted, standard din-rail, horizontal or facing horizontal
any direction is okay
• S8VS models available from 60 to 480 W at 24 VDC, 4 models
Ordering information
Specifications
Power Output voltage Output current Under-voltage control Size in mm (HxWxD) Order code
15 W 5 VDC 2 A (10 W) yes, red LED 85x22.5x96.4 S8VS-01505
12 VDC 1.2 A S8VS-01512
24 VDC 0.65 A S8VS-01524
30 W 5 VDC 4 A (20 W) yes, red LED 85x22.5x96.4 S8VS-03005
12 VDC 2.5 A S8VS-03012
24 VDC 1.3 A S8VS-03024
60 W 24 VDC 2.5 A no 95x40x108.3 S8VS-06024
120 W 24 VDC 5 A no 115x50x121.3 S8VS-12024
240 W 24 VDC 10 A no 115x100x125.3 S8VS-24024
480 W 24 VDC 20 A no 115x150x127.2 S8VS-48024
Specification 15 W 30 W 60 W 120 W 240 W 480 W
Efficiency 77% min. (24 V) 80% min. (24 V) 78% min. 80% min. 80% min. 83% min.
Power factor – – – 0.95 min. 0.95 min. 0.95 min.
Input voltage 100 to 240 VAC (85 to 264 VAC), single-phase
Output
voltage
Voltage adjustment ±10 to ±15% (with V. ADJ) min.
Ripple 2% p-p max. (at rated input/output voltage)
Input variation 0.5% max. (at 85 to 264 VAC input, 100% load)
Temperature
influence
0.05%/°C max.
Overload protection 105 to 160% of rated load current, voltage drop, automatic reset
Overvoltage protection yes yes yes yes yes yes
Input
current
100 V 0.45 A max. 0.9 A max. 1.7 A max. 1.9 A max. 3.8 A max. 7.4 A max.
200 V 0.25 A max. 0.6 A max. 1.0 A max. 1.1 A max. 2.0 A max. 3.9 A max.
230 V 0.19 A
(5 V: 0.14 A)
0.37 A
(5 V: 0.27 A)
0.7 A typ. 0.6 A typ. 1.2 A typ. 2.4 A typ.
Output indicator yes (green) yes (green) yes (green) yes (green) yes (green) yes (green) LED
Weight 160 g 180 g 330 g 550 g 1,150 g 1,700 g max.
Operating temperature -10 to 60°C -10 to 60°C *1
*1 For 30 W model 24 V: No derating, 12 & 5 V: Derating beyond 50°C.
-10 to 60°C, derating beyond 40°C, no icing or condensation
Series operation yes (24 V only) yes yes yes yes yes
423
20 Power supplies
S8VM Single-phase
Slim size S8VM power supplies
All models have the same height of only 84.5 mm. These ranges cover up-to
1,500 W. The output voltages are 5, 12, 15 or 24 VDC. In this series we have standard
types and versions with two alarms up-to 150 W models: one for short dip in the
24 VDC supply, second one when the voltage gradually drops in time. The models
form 300 W/600 W/1,500 W are equipped with an overload alarm function.
• Widest range in DC-output voltage (5 V, 12 V, 15 V & 24 V) & wattage
(15 up-to 1,500 W)
• LED indication power ON
• Transistor output & LED indication under-voltage alarm 1 & 2 or Power failure
• All models can be Din-rail mounted (except 1,500W)
• EMI Class B, UL Class 1 division 2, SEMI-F47 (200VAC input)
Ordering information
Specifications
Power ratings Output voltage Output current Size in mm (HxWXD) Order code
DIN-rail mounting Undervoltage alarm type
Sinking (NPN) Sourcing (PNP)
15 W 12 V 1.3 A 84.5x35.1x94.4 S8VM-01512CD – –
24 V 0.65 A S8VM-01524CD S8VM-01524AD *1
*1 No alarm output built-in.
30 W 12 V 2.5 A 84.5x35.1x109.4 S8VM-03012CD – –
24 V 1.3 A S8VM-03024CD S8VM-03024AD *1
50 W 12 V 4.3 A 84.5x35.1x124.5 S8VM-05012CD – –
24 V 2.2 A S8VM-05024CD S8VM-05024AD S8VM-05024PD
100 W 12 V 8.5 A 84.5x36.6x164.5 S8VM-10012CD – –
24 V 4.5 A S8VM-10024CD S8VM-10024AD S8VM-10024PD
150 W 12 V 12.5 A 84.5x45.6x164.5 S8VM-15012CD – –
24 V 6.5 A S8VM-15024CD S8VM-15024AD S8VM-15024PD
Power ratings Output voltage Output current Size in mm (HxWXD) Bottom mounting DIN-rail adaptor Power failure output
300 W 12 V 27 A 84.5x62.5x188 S8VM-30012C S82Y-VM30D overload,
overvoltage
and overheat
24 V 14 A S8VM-30024C
600 W 12 V 53 A 84.5x101.8x192 S8VM-60012C S82Y-VM60D
24 V 27 A S8VM-60024C –
1,500 W 24 V 70 A 84.5x126.5x327 S8VM-15224C – –
Item 15 W 30 W 50 W 100 W 150 W 300 W 600 W 1,500 W
Efficiency 12 V models 78% min. 79% min. 79% min. 81% min. 81% min. 78% min. 79% min. –
24 V models 80% min. 81% min. 80% min. 82% min. 83% min. 81% min. 81% min. 82% min.
Input voltage 100 to 240 VAC, (85 to 264 VAC), single phase
Output Voltage adjustment -20% to 20% with V. ADJ min. (S8VM-_ _ _ 24A_ /P_ : -10% to 20%)
Ripple 12 V models 1.5% (p-p) max. 1.5% (p-p) max. 2.0% (p-p) max. –
24 V models 1.0% (p-p) max. 0.75% (p-p) max. 1.25% (p-p) max. 1.25% (p-p) max.
Input variation 0.4% max.
Temperature influence 0.02%/°C max.
Overload protection 105% to 160% of rated load current, voltage drop, automatic reset
Overvoltage protection yes
Output indicator yes (green)
Weight 180 g max. 220 g max. 290 g max. 460 g max. 530 g max. 1,100 g max. 1,700 g max. 3,800 g max.
Series operation yes
Remote sensing function no no no yes
424
S8JX-G Single-phase
Slim & economic power supply
The S8JX-G is Omron’s cost effective power supply delivering Omron’s quality and
reliability. The range of this Power Supply covers up to 600 W, the output voltages are
5, 12 or 24 VDC. The low profile and multiple mounting options help you reduce panel
space. With a minimum life expectancy of 10 years and protection against over-voltage,
over-current and short circuiting, the S8JX-G is as reliable as you may expect
from Omron.
• Wide range in DC-output voltage (5 V, 12 V, 15 V & 24 V) & wattage (15 to 600 W)
• LED indication power ON
• Over-voltage, over-current, and short circuit protection
• Vibration resistance 4,5 g
• All models can be DIN-rail mounted
• Approvals: UL, cUL, UL508 Listed, CE, SEMI F47, VDE
Ordering information
Specifications
Power Output voltage Output current Size in mm (HxWxD) Order code
15 W 5 V 3 A 91x40x90 S8JX-G01505CD
12 V 1.3 A S8JX-G01512CD
15 V 1 A S8JX-G01515CD
24 V 0.65 A S8JX-G01524CD
35 W 5 V 7 A 91x40x90 S8JX-G03505CD
12 V 3 A S8JX-G03512CD
15 V 2.4 A S8JX-G03515CD
24 V 1.5 A S8JX-G03524CD
50 W 5 V 10 A 92x40x100 S8JX-G05005CD
12 V 4.2 A S8JX-G05012CD
24 V 2.1 A S8JX-G05024CD
100 W 5 V 20 A 92x50x150 S8JX-G10005CD
12 V 8.5 A S8JX-G10012CD
24 V 4.5 A S8JX-G10024CD
150 W 24 V 6.5 A 92x50x150 S8JX-G15024CD
300 W 24 V 14 A 92x110x167 S8JX-G30024CD
600 W 24 V 27 A 92x150x160 S8JX-G60024C*1
*1 Additional accessory is required for DIN-rail mounting.
Item 15 W 35 W 50 W 100 W 150 W 300 W 600 W
Efficiency 100 to 240 V input 68% min. 73% min. 76% min. 76% min. 86% min. – –
100/200 V (Selected) – – – – – 82% min. 80% min.
Input voltage 100 to 240 VAC (85 to 264 VAC) 100 to 120 VAC (85 to 132 VAC)
200 to 240 VAC (170 to 264 VAC)
(Switchable)
100 to 370 VDC
Note: This range is not applicable for the safety standards.
Output Voltage adjustment -10% to 15% (with V. ADJ)
Ripple 2% (p-p) max.
Input variation 0.4% max.
Temperature influence 0.05%/°C max. (at rated input and output) 0.05%/°C max.
Overload protection 105% to 160% of rated load current, voltage drop, intermittent, automatic reset 105% of rated load
current, voltage
drop, intermittent,
automatic reset
105% of rated load
current, Inverted L
voltage drop, the circuit
will be shut OFF
when the overload
exceeds 5 s.
Overvoltage protection yes
Output indicator yes (green)
Weight 250 g max. 250 g max. 300 g max. 550 g max. 600 g max. 1,600 g max. 2,500 g max.
Series operation yes (For up to two Power Supplies; external diodes required.)
425
20 Power supplies
S8TS Single-phase
Industrial use, modular power supply for
multiple configurations
The S8TS is an expandable power supply; standard units can easily be snapped
together in parallel to provide you with ultimate flexibility. Expandable up to 4 units,
it can deliver a total power of 240W at 24VDC or a multi-output configuration.
• Improves system reliability by building up N+1 redundancy
• Standard unit; 60 W at 24 VDC, 30 W at 12 VDC and 25 W at 5 VDC
• Battery back-up unit protects against power outage (see accessories)
• Buffer unit protects against power glitches and outage (see accessories)
• EMI Class B, UL Class 2, UL Class 1 division 2
Ordering information
Accessories
Specifications
Basic block Order code
Output
voltage
Output current Screw terminal type Connector terminal type
With bus line connectors*1
*1 One S8T-BUS01 connector and one S8T-BUS02 connector are included as accessories.
Without bus line connectors*2
*2 Bus line connectors can be ordered separately if necessary.
With bus line connectors*1 Without bus line connectors*2
24 V 2.5 A S8TS-06024-E1*3
*3 Conforms to EMI class B with DC minus terminal ground.
S8TS-06024 S8TS-06024F-E1 S8TS-06024F
12 V 2.5 A S8TS-03012-E1 S8TS-03012 S8TS-03012F-E1 S8TS-03012F
5 V 5 A – S8TS-02505 – S8TS-02505F
Bus line connector
Type Number of connectors Order code
AC line + DC line bus
(For parallel operation)
1 connector S8T-BUS01
10 connectors*1
*1 One package contains 10 S8T-BUS01 connectors.
S8T-BUS11
AC line bus (For series operation
or isolated operation)
1 connector S8T-BUS02
10 connectors*2
*2 One package contains 10 S8T-BUS02 connectors.
S8T-BUS12
Item 5 V models 24/12 V models
Single operation Single operation Parallel operation
Efficiency 62% min. 24 V models: 75%, 12 V models: 70% min.
Power factor 0.8 min. 24 V models: 0.9 min., 12 V models: 0.8 min.
Input voltage 100 to 240 VAC, (85 to 264 VAC), single-phase
Output
voltage
Voltage adjustment 5 V ±10% min. 24 V models: 22 to 28 V, 12 V models: 12 V ±10% min.
Ripple 2% (p-p) max. 2% (p-p) max. 2% (p-p) max.
Input variation 0.5% max. – –
Temperature influence 0.05%/°C max. (with rated input, 10 to 100% load)
Overcurrent protection 105 to 125% of rated load current, inverted L drop, automatic reset
Overvoltage protection yes yes yes
Output indicator yes (green) yes (green) yes (green)
Weight 450 g max. 450 g max. 450 g max.
Series operation yes yes yes
Parallel operation no yes yes
Size in mm (HxWxD) 120x43x120
426
S8T-DCBU-01/-02 Single-phase
S8T-DCBU-01
The S8T-DCBU-01 battery backup block supplies 24 VDC for a fixed period of time
during AC input outages to considerably improve system reliability.
• Supplies 24 VDC for a long period of time during AC input outages
• For system reliability improvement
• Block power supply basic block is connected by the bus line connector
• Simple system configuration
• Alarms indicated on main unit and via alarm signal output
Ordering information
Note:The S8TS DC back-up block is for S8TS power supplies only.
Specifications
S8T-DCBU-02
Prevents equipment stoppage, data loss and other problems resulting from
momentary power failures. One S8T-DCBU-02 buffer block provides a back-up time
of 500 ms at an output current of 2.5 A. Can be wired to the 24 VDC output from any
switch mode power supply.
• Connects to all Omron power supplies: S8TS, S8VS, S82J, S82K, S8VM, S8PE
• Connects to both single-phase and three-phase power supplies
• Connects to an S8TS power supply via an S8T-BUS03 bus line connector
• Parallel connection up to 4 units to increase back-up time and capacity
• Complies with Semi F47-0200 standard
Ordering information
Accessories
Specifications
Product Input voltage Output voltage Output current Order code
DC back-up block 24 to 28 VDC 24 V 3.7 A/8 A S8T-DCBU-01
Battery holder – – – S82Y-TS01
Product Input voltage Output voltage Output current Type Order code
Basic block
(use together with the DC
back-up block)
100 to 240 VAC 24 V 2.5 A Screw
terminal type
With bus line connectors S8TS-06024-E1
Without bus line connectors S8TS-06024
Connector
terminal type
With bus line connectors S8TS-06024F-E1
Without bus line connectors S8TS-06024F
Product Back-up time Overcurrent protection
operating point selector
Order code
Battery 8 min./3.7 A 5.7 A (typ.) – LC-R122R2PG
4 min./8.0 A 5.7 A (typ.) 11.7 A (typ.) LC-R123R4PG
Item Size in mm (HxWxD)
S8T-DCBU-01 120x43x130
Battery holder 82x185.7x222.25
Input voltage Output voltage (during back-up operation) Output current Order code
24 VDC (24 to 28 VDC) 22.5 V 2.5 A S8T-DCBU-02
Type Number of connectors Order code
DC bus line connector (for use with S8TS only) 1 connector S8T-BUS03
10 connectors S8T-BUS13
Item Size in mm(HxWxD)
S8T-DCBU-02 120x43x120
427
20 Power supplies
S8VT Three-phase
Compact 3-phase input power supply
To make the compact power supply range complete we have our 3-phase S8VT
series, which give you the best power to footprint ratio. The range exists of 4 models
with wattage of 120, 240, 480 and 960 W all at 24 VDC. This version is constructed
from a very robust metal housing and all models are din-rail mounting. The input
range cover 3 phase voltage input from 340 to 576 VAC and single phase DC input
from 480 to 810 VDC.
• 5, 10, 20 and 40A; 24VDC output
• 3-phase input (340-576VAC) or 1-phase 480 to 810 VDC
• Compact design with best footprint on the market
• UL60950 (CSA22.2-60950), UL508 listing (CSA22.2-14) and CE
• Parallel & serial operation possible (all models)
Ordering information
Specifications
Power ratings Output voltage Output current Size in mm (HxWxD) Order code
120 W 24 V 5 A 125x45x130 S8VT-F12024E
240 W 24 V 10 A 170x45x130 S8VT-F24024E
480 W 24 V 20 A 170x100x130 S8VT-F48024E
960 W 24 V 40 A 170x195x130 S8VT-F96024E
Item 5 A 10 A 20 A 40 A
Efficiency 88% 90% 91% 91%
Voltage range 340 to 576 VAC 3 AC resp, 480 to 810 VDC (1 phase)
Output
voltage
Voltage adjustment 22.5 to 26.4 VDC min.
Ripple 100 mV max.
Input variation ±0.5% max.
Temperature
influence
Less than 0.05%/°C
Overload protection yes
Overvoltage protection yes
Output indicator yes (green)
Weight 750 g 1.0 kg 1.8 kg 3.3 kg
Series operation yes (for 2 units)
Parallel operation yes (for 2 units)
H2C
Motor timer
WHEN TIMING ACCURACY MATTERS!
The H5CX series offers multiple-functions and -timing ranges for precise timing control, as well as
real twin-timing and memory function. These and other added-value features ensure that the H5CX
covers almost every possible user requirement in timers.
• 15 different time functions
• Three colour display value, red, orange or green
• Models with instantaneous contact outputs
• 0.001 s to 9999 h, 10 ranges
H5CX – The most complete digital timer
428
Page 437
Timers
H3DK
22.5 mm
H3DS H3CR
17.5 mm
Which size is required?
Which mounting method is required?
Which type of timer is needed?
H3YN
DIN-rail Plug/front
Analogue
H5CX
48x24 mm 48x48 mm
Which size is required?
Digital
H8GN
timer/counter
429
21 Timers
Page 432 Page 433 Page 434 Page 435 Page 445 Page 436
430
Selection table
Category Analogue solid state timer
Selection criteria
Model H3DS-M H3DS-S H3DS-A H3DS-F H3DS-G H3DS-X H3DK-M H3DK-S H3DK-F H3DK-G H3DK-H
Mounting DIN-rail
Size 17.5 mm 22.5 mm
Type Multi-functional Twin timer Star-delta Two-wired Multi-functional Twin
timer
Star-delta Power
OFF-delay
Contact configuration
Time limit
Instantaneous – – – – – – – – –
Programmable
contacts
– – – – – – – – –
14 pins – – – – – – – – – – –
11 pins – – – – – – – – – – –
8 pins – – – – – – – – – – –
Screw terminals
Screw-less clamp
terminals
– – – – –
Screw-less clamp
sockets
– – – – – – – – – – –
Inputs
Voltage input – – – – – –
Outputs
Transistor – – – – – – – – – – –
Relay –
SCR – – – – – – – – – –
Relay
output
type
SPDT – – (2x)
SPST-NO – – – – (2x) – – – – – –
DPDT – – – – – – – – –
4PDT – – – – – – – – – – –
Features
Time
range
Total time
range
0.1 s to
120 h
1 s to 120 h 2 s to 120 h 0.1 s to 12 h 1 s to 120 s 0.1 s to
120 h
0.1 s to
1,200 h
0.1 s to
1,200 h
0.1 s to
1,200 h
1 s to 120 s 0.1 s to 120 s
Number of
sub ranges
7 7 7 6 2 7 12 12 8 2 2 (model
dependent)
Supply voltage 24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
240 VAC/DC
or 12 VDC
24 to
240 VAC/DC
or 12 VDC
24 to
240 VAC/DC
or 12 VDC
24 to
240 VAC/DC,
240 to
440VAC,
12 VDC
100 to
120 VAC, 200
to 240 VAC,
24 to
48 VAC/DC
Number of operating
modes
8 4 1 2 1 1 8 4 1 1 1
Functions
ON-delay – – – – – –
Flicker OFF start – – – – – – –
Flicker ON start – – – – –
Signal
ON-/OFF-delay
– – – – – – – – –
Signal OFF-delay – – – – – – – –
Interval (signal or
power start)
– – – – – – –
One-shot output
(ON-delay)
– – – – – – –
ON-delay (fixed) – – – – – – – – –
Independent
ON/OFF time setting
– – – – – – – – – – –
Star-delta – – – – – – – – – –
Remarks
Transistor – – – – – – – – – –
Page 432 433
Timers
431
21 Timers
Category Analogue solid state timer Digital timer Motor timer
Selection criteria
Model H3YN H3CR-A H3CR-F H3CR-G H3CR-H H5CX H8GN H2C
Mounting Socket/on panel
Size 21.5 mm 1/16 DIN 1/32 DIN 1/16 DIN
Type Miniature Multifunctional
Twin timer Star-delta Power
OFF-delay
Multifunctional
Preset counter/
timer
Motor timer
Contact configuration
Time limit
Instantaneous – – –
Programmable
contacts
– – – – – –
14 pins – – – – – – –
11 pins – –
8 pins –
Screw terminals – – – – –
Screw-less clamp
terminals
– – – – – – – –
Screw-less clamp
sockets
– – – – – – –
Inputs
Voltage input – – – – – – –
Outputs
Transistor – – – – – –
Relay
SCR – – – – – – – –
Relay
output
type
SPDT – – –
SPST-NO – – – (2x) – – – –
DPDT – – – –
4PDT – – – – – – –
Features
Time
range
Total time
range
0.1 s to 10 h
(model
dependent)
0.05 s to 300 h,
0.1 s to 600 h
(model
dependent)
0.05 s to 30 h or
1.2 s to 300 h
(model
dependent)
0.5 s to 120 s 0.05 s to 12 s, 1.2
s to 12 min
0.001 s to 9999 h
(configurable)
0.000 s to 9999 h
(configurable)
0.2 s to 30 h
Number of
sub ranges
2 9 14 4 4 10 9 15
Supply voltage 24, 100 to 120,
200 to 230 VAC,
12, 24, 48, 100 to
110, 125 VDC
100 to 240 VAC,
100 to 125 VDC,
24 to 48 VAC,
12 to 48 VDC
100 to 240 VAC,
12 VDC,
24 VAC/DC, 48 to
125 VDC
100 to 120 VAC,
200 to 240 VAC
100 to 120 VAC,
200 to 240 VAC,
24 VAC/DC,
48 VDC, 100 to
125 VDC
100 to 240 VAC,
24 VAC,
12 to 24 VDC
24 VDC 24, 48, 100, 110,
115, 120, 200,
220, 240 VAC
Number of operating
modes
4 6 (model
dependent)
– 1 1 15 6 2
Functions
ON-delay – – –
Flicker OFF start – – –
Flicker ON start – – – –
Signal
ON-/OFF-delay
– – – – – –
Signal OFF-delay – – –
Interval (signal or
power start)
– – – –
One-shot output (ONdelay)
– – – – – –
ON-delay (fixed) – – – – – – –
Independent
ON/OFF time setting
– – – – – –
Star-delta – – – – – – –
Remarks
Transistor – – – – – –
Page 434 435 436 445 437
Standard Available – No/not available
432
H3DS Analogue solid state timers
DIN-rail mounted, standard 17.5 mm wide
solid state timer range
This broad range of timers includes many functionalities and has a wide AC/DC power
supply range. Models with screwless clamp connection available.
• 17.5 mm width, modular 45 mm
• DIN-rail mounting
• 24-48 VDC and 24-230 VAC
• 0.1 s to 120 h, 7 ranges
Ordering information
Specifications
Type Supply voltage Control output Time setting
range
Operating modes Order code
Screw
terminal type
Screw-less
clamp type
Multi-functional timer 24 to 230 VAC
(50/60 Hz)/
24 to 48 VDC
SPDT 0.1 s to120 h ON-delay, flicker OFF start, flicker ON start,
signal ON/OFF-delay, signal OFF-delay,
interval, one-shot
H3DS-ML H3DS-MLC
Standard timer ON-delay, flicker ON start, interval, oneshot
H3DS-SL H3DS-SLC
Single function timer ON-delay H3DS-AL H3DS-ALC
Twin timer Relay SPDT 0.1 s to 12 h Flicker OFF start, flicker ON start H3DS-FL H3DS-FLC
Star-delta timer 2x Relay SPST-NO 1 s to 120 s Star-delta H3DS-GL H3DS-GLC
Two-wired timer 24 to 230 VAC/VDC
(50/60 Hz)
SCR output 0.1 s to 120 h ON-delay H3DS-XL H3DS-XLC
Terminal block Screw terminal type: Clamps two 2.5 mm2 max. bar terminals without sleeves
Screw-less clamp type: Clamps two 1.5 mm2 max. bar terminals without sleeves
Mounting method DIN-rail mounting
Operating voltage range 85 to 110% of rated supply voltage
Power reset Minimum power-off time: 0.1 s, 0.5 s for H3DS-G
Reset voltage 2.4 VAC/VDC max., 1.0 VAC/VDC max. for H3DS-X
Voltage input Max. permissible capacitance between input lines (terminals B1 and A2): 2,000 pF
Load connectable in parallel with inputs (terminals B1 and A1)
H-level: 20.4 to 253 VAC/20.4 to 52.8 VDC
L-level: 0 to 2.4 VAC/VDC
Control output Contact output: 5 A at 250 VAC with resistive load (cos = 1)
5 A at 30 VDC with resistive load (cos = 1)
Ambient temperature Operating: -10 to 55°C (with no icing)
Storage: -25 to 65°C (with no icing)
Accuracy of operating time ±1% max. of FS (±1% ±10 ms max. at 1.2 s range)
Setting error ±10% ±50 ms max. of FS
Influence of voltage ±0.7% max. of FS (±0.7% ±10 ms max. at 1.2 s range)
Influence of temperature ±5% max. of FS (±5% ±10 ms max. at 1.2 s range)
Life expectancy (not H3DS-X) Mechanical: 10 million operations min. (under no load at 1,800 operations/h)
Electrical: 100,000 operations min. (5 A at 250 VAC, resistive load at 360 operations/h)
Size in mm(HxWxD) 80x17.5x73
433
21 Timers
H3DK Analogue solid state timers
DIN-rail mounted, standard 22.5 mm wide
solid state timer range
The H3DK series of timers provides a wide AC/DC power supply and time range to
reduce the number of items.
• Size in mm (HxWxD): 79x22.5x100
• DIN-rail mounting
• 12 VDC and 24-240 VAC/VDC (except -H). 240-440 VAC for -G
• Wide time setting range: 0.10 s - 1,200 h (except -H and -G), 12 ranges
(for -M and -S)
Ordering information
Specifications
Type Supply voltage Control output Time setting range Operating modes Order code
Multi-functional
standard timers
12 VDC SPDT 0.1 s to 1200 h ON-delay, flicker OFF start, flicker ON start,
signal ON/OFF-delay, signal OFF-delay, interval, one-shot
H3DK-M1A DC12
DPDT H3DK-M2A DC12 *1
*1 One output can be set to instantaneous.
SPDT ON-delay, flicker ON start, interval, one-shot H3DK-S1A DC12
DPDT H3DK-S2A DC12 *1
24 to 240 VAC/VDC SPDT ON-delay, flicker OFF start, flicker ON start,
signal ON/OFF-delay, signal OFF-delay, interval, one-shot
H3DK-M1 AC/DC24-240
DPDT H3DK-M2 AC/DC24-240 *1
SPDT ON-delay, flicker ON start, interval, one-shot H3DK-S1 AC/DC24-240
DPDT H3DK-S2 AC/DC24-240 *1
Twin timer 12 VDC SPDT 0.1 s to 12 h Flicker OFF start, flicker ON start H3DK-FA DC12
24 to 240 VAC/VDC H3DK-F AC/DC24-240
Star-delta timer 12 VDC 2x SPDT 1 to 120 s Star-delta H3DK-GA DC12
24 to 240 VAC/VDC H3DK-G AC/DC24-240
240 to 440 VAC H3DK-GE AC/DC240-440
Power OFF-delay timer 24 to 48 VAC/VDC SPDT 1 to 120 s Signal OFF-delay H3DK-HBL AC/DC24-48
0.1 to 12 s H3DK-HBS AC/DC24-48
100 to 120 VAC 1 to 120 s H3DK-HCL AC100-120V
0.1 to 12 s H3DK-HCS AC100-120V
200 to 240 VAC 1 to 120 s H3DK-HDL AC200-240V
0.1 to 12 s H3DK-HDS AC200-240V
Operating voltage range 85 to 110% of rated supply voltage (90 to 110% for the 12 VDC models).
Power reset Minimum power-off time: H3DK-M/S, H3DK-F: 0.1 s, H3DK-G: 0.5 s. (Not for H3DK-H)
Reset voltage 10% of rated voltage. (Not for H3DK-H)
Voltage input (H3DK-M/-S) 24 to 240 VAC/DC: H-level 20.4 to 264 VAC/VDC, L-level 0 to 2.4 VAC/VDC.
12 VDC: H-level 10.8 to 13.2 VDC, L-level 0 to 1.2 VDC.
Control output Contact output: 5 A at 250 VAC with resistive load (cos = 1), 5 A at 24 VDC (30 VDC for -M/-S) with resistive load (not for H3DK-GE)
Ambient temperature Operating: -20 to 55°C (with no icing), storage: -40 to 70°C (with no icing)
Accuracy of operating time ±1% of FS max. (±1% ±10 ms max. at 1.2 s range)
Setting error ±10% of FS ±0.05 s max.
Minimum input signal width 50 ms (start input) (Only for H3DK-M/S)
Influence of voltage ±0.5% of FS max. (±0.5% ±10 ms max. at 1.2 s range). For H3DK-G: ±0.5% of FS max.
Influence of temperature ±2% of FS max. (±2% ±10 ms max. at 1.2s range). For H3DK-G: ±2% of FS max.
Life expectancy Mechanical: 10 million operations min. (under no load at 1,800 operations/h)
Electrical: 100,000 operations min. (5 A at 250 VAC, resistive load at 360 operations/h)
Degree of protection IP30 (terminal block: IP20)
Terminal block Clamps two 2.5 mm2 max. bar terminals without sleeves
Size in mm (HxWxD) 79x22.5x100
434
H3YN Analogue solid state timers
Miniature timer with multiple time ranges
and multiple operating modes
H3YN features 4 multi-operating modes: ON-delay, interval,
flicker ON start and flicker OFF start.
• Size in mm (HxWxD): 28x21.5x52.6
• Plug-in
• All supply voltages available
• 0.1 s to 10 h
• DPDT (5A) or 4PDT (3A)
Ordering information
Accessories
Connecting socket Hold-down clips
Specifications
Supply voltage Functions Time-limit contact Order code
Short-time range model (0.1 s to 10 min) Long-time range model (0.1 min to 10 h)
12 VDC ON-delay
Interval
Flicker ON
Flicker OFF
DPDT H3YN-2 12DC H3YN-21 12DC
24 VAC H3YN-2 24AC H3YN-21 24AC
24 VDC H3YN-2 24DC H3YN-21 24DC
100 to 120 VAC H3YN-2 100-120AC H3YN-21 100-120AC
200 to 230 VAC H3YN-2 200-230AC H3YN-21 200-230AC
12 VDC 4PDT H3YN-4 12DC H3YN-41 12DC
24 VAC H3YN-4 24AC H3YN-41 24AC
24 VDC H3YN-4 24DC H3YN-41 24DC
100 to 120 VAC H3YN-4 100-120AC H3YN-41 100-120AC
200 to 230 VAC H3YN-4 200-230AC H3YN-41 200-230AC
Timer DIN-rail mounting/
front-connecting socket
Back-connecting socket
PCB terminal
H3YN-2/-21 PYF08A, PYF08A-N, PYF08A-E PY08-02
H3YN-4/-41 PYF14A, PYF14A-N, PYF14A-E PY14-02
Applicable socket Order code
PYF08A, PYF08A-N, PYF08A-E,
PYF14A, PYF14A-N, PYF14A-E
Y92H-3 (pair)
PY08, PY08-02, PY14-02 Y92H-4
Item H3YN-2/-4 H3YN-21/-41
Time ranges 0.1 s to 10 min (1 s, 10 s, 1 min, or 10 min max. selectable) 0.1 min to 10 h (1 min, 10 min, 1 h, or 10 h max. selectable)
Rated supply voltage 24, 100 to 120, 200 to 230 VAC (50/60 Hz)
12, 24, 48, 100 to 110, 125 VDC
Pin type Plug-in
Operating mode ON-delay, interval, flicker OFF start, or flicker ON start (selectable with DIP switch)
Operating voltage range 85 to 110% of rated supply voltage (12 VDC: 90 to 110% of rated supply voltage)
Reset voltage 10% min. of rated supply voltage
Control outputs DPDT: 5 A at 250 VAC, resistive load (cos = 1), 4PDT: 3 A at 250 VAC, resistive load (cos = 1)
Accuracy of operating time ±1% FS max. (1 s range: ±1% ±10 ms max.)
Setting error ±10% ±50 ms FS max.
Reset time Min. power-opening time: 0.1 s max. (including halfway reset)
Influence of voltage ±2% FS max.
Influence of temperature ±2% FS max.
Ambient temperature Operating: -10 to 50°C (with no icing), storage: -25 to 65°C (with no icing)
Degree of protection IP40
Size in mm (HxWxD) 28x21.5x52.6
435
21 Timers
H3CR Analogue solid state timers
DIN 48x48 mm multi-functional
timer series
This elaborate range of solid state timers provides you with
a multi-functional timer, twin timer, star-delta timer and a power
OFF-delay timer.
• 48x48 mm front-panel/plug-in
• High-/low-voltage models (except -H and -G)
• 0.05 s to 300 h (except -H and -G)
• DPDT, 5A at 250VAC
• Transistor 100mA at 30VDC
Ordering information
Accessories
Specifications
Output Number of pins Supply voltage Time range Operating mode Order code
Relay DPDT 11 100 to 240 VAC/100 to 125 VDC 0.05 s to 300 h ON-delay, flicker OFF start,
flicker ON start, signal ON/
OFF-delay, signal OFF-delay,
interval
H3CR-A 100-240AC/100-125DC
24 to 48 VAC/12 to 48 VDC H3CR-A 24-48AC/12-48DC
Transistor 24 to 48 VAC/12 to 48 VDC 0.05 s to 300 h H3CR-AS 24-48AC/12-48DC
Relay DPDT 8 100 to 240 VAC/100 to 125 VDC 0.05 s to 300 h ON-delay, flicker ON start,
interval, one-shot
H3CR-A8 100-240AC/100-125DC
24 to 48 VAC/12 to 48 VDC H3CR-A8 24-48AC/12-48DC
Transistor 24 to 48 VAC/12 to 48 VDC 0.05 s to 300 h H3CR-A8S 24-48AC/12-48DC
Relay SPDT 100 to 240 VAC/100 to 125 VDC H3CR-A8E 100-240AC/100-125DC
24 to 48 VAC/VDC H3CR-A8E 24-48AC/DC
Relay DPDT 11 100 to 240 VAC 0.05 s to 30 h Flicker OFF start H3CR-F 100-240AC
24 VAC/VDC H3CR-F 24AC/DC
8 100 to 240 VAC H3CR-F8 100-240AC
24 VAC/VDC H3CR-F8 24AC/DC
11 100 to 240 VAC 0.05 s to 30 h Flicker ON start H3CR-FN 100-240AC
24 VAC/VDC H3CR-FN 24AC/DC
8 100 to 240 VAC H3CR-F8N 100-240AC
24 VAC/VDC H3CR-F8N 24AC/DC
Time-limit contact and
instantaneous contact
100 to 120 VAC Star-delta H3CR-G8EL 100-120AC
200 to 240 VAC H3CR-G8EL 200-240AC
DPDT 8 100 to 120 VAC 0.05 to 12 s Power OFF-delay H3CR-H8LS 100-120AC
200 to 240 VAC H3CR-H8LS 200-240AC
24 VAC/VDC H3CR-H8LS 24AC/DC
100 to 120 VAC 0.05 to 12 m H3CR-H8LM 100-120AC
200 to 240 VAC H3CR-H8LM 200-240AC
24 VAC/VDC H3CR-H8LM 24AC/DC
Name/specifications Order code
Flush-mounting adapter Y92F-30
Protective cover Y92A-48B
Front connecting socket 8-pin, finger-safe
type, DIN-rail
P2CF-08-E
Front connecting socket 11-pin, finger-safe
type, DIN-rail
P2CF-11-E
Back connecting socket 8-pin P3G-08
11-pin P3GA-11
Name/specifications Order code
Time setting ring Setting a specific time Y92S-27
Limiting the setting range Y92S-28
Panel cover Light grey (5Y7/1) Y92P-48GL
Black (N1.5) Y92P-48GB
Accuracy of operating time ±0.2% FS max. (±0.2% ±10 ms max. in a range of 1.2 s)
Influence of voltage ±0.2% FS max. (±0.2% ±10 ms max. in a range of 1.2 s)
Influence of temperature ±1% FS max. (±1% ±10 ms max. in a range of 1.2 s)
Ambient temperature Operating: -10 to 55°C (with no icing),
storage: -25 to 65°C (with no icing)
Life expectancy Mechanical: 20,000,000 operations min. (under no load at 1,800 operations/h)
Electrical: 100,000 operations min. (5 A at 250 VAC, resistive load at 1,800 operations/h)
Size in mm (HxWxD) 48x48x66.6 (H3CR-A, -F), 48x48x78 (H3CR-G, -H)
Setting error ±5% FS ±50 ms
Degree of protection IP40 (panel surface)
Weight Approx. 90 g
436
H5CX Digital timers
The most complete digital standard timer on
the market
H5CX offers you the most complete series of products on the market today.
Based on extensive customer research, these new timers have been designed with
value added features that users both need and appreciate.
• Size in mm (HxWxD): 48x48x59 to 78 mm
• Three colour display value, red, green or orange
• Models with Instantaneous Contact Outputs
• 0.001 s to 9999 h, 10 ranges
• Input NPN, PNP and contact
Ordering information
Accessories
Specifications
Output type Supply voltage Functions External connection Size in mm (HxWxD) Inputs Order code
Contact output 100 to 240 VAC A: Signal ON-delay
A-1: Signal ON-delay 2
A-2: Power ON-delay 1
A-3: Power ON-delay 2
b: Repeat cycle 1
b-1: Repeat cycle 2
d: Signal OFF-delay
E: Interval
F: Cumulative
Z: ON/OFF-duty adjustable flicker
toff: Twin timer OFF start
ton: Twin timer ON start
Screw terminals 48x48x84 Signal, Reset, Gate
(NPN/PNP inputs)
H5CX-A-N
12 to 24 VDC/24 VAC 48x48x65 H5CX-AD-N
Transistor output 100 to 240 VAC 48x48x84 H5CX-AS-N
12 to 24 VDC/24 VAC 48x48x65 H5CX-ASD-N
Contact output 100 to 240 VAC 11-pin socket 48x48x69.7 Signal, Reset, Gate
(NPN/PNP inputs)
H5CX-A11-N
12 to 24 VDC/24 VAC H5CX-A11D-N
Transistor output 100 to 240 VAC H5CX-A11S-N
12 to 24 VDC/24 VAC H5CX-A11SD-N
Contact output 100 to 240 VAC 8-pin socket 48x48x69.7 Signal, Reset
(NPN inputs)
H5CX-L8-N
12 to 24 VDC/24 VAC H5CX-L8D-N
Transistor output 100 to 240 VAC H5CX-L8S-N
12 to 24 VDC/24 VAC H5CX-L8SD-N
Contact output
Models with instantaneous
contact outputs
100 to 240 VAC A-2: Power ON-delay 1
b: Repeat cycle 1
E: Interval
Z: ON/OFF-duty adjustable flicker
toff: Twin timer OFF start 1
ton: Twin timer ON start 1
– H5CX-L8E-N
12 to 24 VDC/24 VAC H5CX-L8ED-N
Transistor output 12 to 24 VDC A: Signal ON-delay 1
F: Cumulative
Screw terminals 48x48x65 Signal, Reset, Gate
(NPN/PNP inputs)
H5CX-BWSD-N
Name Order code
Flush-mounting adapter Y92F-30
Waterproof packing Y92S-29
Front-connecting socket 8-pin, finger safe type P2CF-08-E
11-pin, finger safe type P2CF-11-E
Back-connecting socket 8-pin P3G-08
11-pin P3GA-11
Hard cover Y92A-48
Soft cover Y92A-48F1
Front panels
(4-digit models)
Light gray Y92P-CXT4G
White Y92P-CXT4S
Item H5CX-A_ H5CX-A11_ H5CX-L8_
Display 7-segment, negative transmissive LCD
Present value: 12 mm high characters
red, orange or green (programmable) red
Set value: 6 mm high characters, green
Digits 4 digits
Total time range 0.001 s to 9,999 h (configurable)
Timer mode Elapsed time (Up), remaining time (Down) (selectable)
Input signals Signal, reset, gate Signal, reset
Key protection Yes
Memory backup EEPROM (overwrites: 100,000 times min.) that can store data for 10 years min.
Ambient temperature Operating: -10 to 55°C (no icing or condensation), side-by-side mounting: -10 to 50°C
Case colour Black (N1.5)
437
21 Timers
H2C Motor timers
DIN-sized (48x48) motor timer with
variable time ranges
This motor timer series provides you with many features, such as ON-delay,
time indicator, moving pointer and synchronous motor. Moreover, the LED indicator
shows the time operation, time range and the rated voltage.
• DIN-sized 48x48mm
• Front-panel/plug-in/DIN-rail
• All supply voltages available
• 0.2 s to 30 h
• SPDT, 6A at 250VAC
Ordering information
Note: Other voltages available on request
Accessories
Specifications
Operation/resetting system Internal connection Terminal Time-limit
contact
Instantaneou
s contact
Time range code Order code
Time-limit operation/
electric resetting
Separate motor and clutch connection 11-pin socket SPDT SPDT 1.25 s to 30 h
in 5 ranges
H2C-RSA 110AC
H2C-RSA 220AC
H2C-RSA 24AC
0.2 s to 6 h
in 5 ranges
H2C-RSB 110AC
H2C-RSB 220AC
H2C-RSB 24AC
0.5 s to 12 h
in 5 ranges
H2C-RSC 110AC
H2C-RSC 220AC
H2C-RSC 24AC
Time-limit operation/
self-resetting
Separate motor and clutch connection 11-pin socket SPDT SPDT 1.25 s to 30 h
in 5 ranges
H2C-SA 110AC
H2C-SA 220AC
H2C-SA 24AC
0.2 s to 6 h
in 5 ranges
H2C-SB 110AC
H2C-SB 220AC
H2C-SB 24AC
0.5 s to 12 h
in 5 ranges
H2C-SC 110AC
H2C-SC 220AC
H2C-SC 24AC
Name/specifications Order code
DIN-rail mounting/
front-connecting socket
8-pin, finger safe type P2CF-08-E
11-pin, finger safe type P2CF-11-E
Back-connecting socket 8-pin, screw terminal P3G-08
11-pin P3GA-11
Name/specifications Order code
Hold-down clip (pair) For PL08 and PL11 sockets Y92H-1
For PF085A socket Y92H-2
Flush mounting adapter Y92F-30
Time setting ring Y92A-Y1
Operating voltage range 85 to 110% of rated supply voltage
Reset voltage 10% max. of rated supply voltage
Reset time Min. power-opening time: 0.5 s, min. pulse width: 0.5 s
Control outputs 6 A at 250 VAC, resistive load (cos = 1)
Mounting method Flush mounting (except for H2C-F/-FR models), surface-mounting, DIN-rail mounting
Life expectancy Mechanical: 10,000,000 operations min.
Electrical: 500,000 operations min.
Motor life expectancy 20,000 h
Accuracy of operating time ±0.5% FS max. (±1% max. at 0.2 to 6 s for the time range code B or at 0.5 to 12 s for the time range code C)
Setting error ±2% FS max.
Reset time 0.5 s max.
Influence of voltage ±1% FS max.
Influence of temperature ±2% FS max.
Ambient temperature Operating: -10 to 50°C
Case colour Light grey (Munsell 5Y7/1)
Degree of protection IP40 (panel surface)
Size in mm (HxWxD) 48x48x77.5
H7ER
Speed
H7EC
Totalising
H7ET
Timer
Which type of application?
48x24 mm
(1/32 DIN)
Which size is required?
Totalising
MULTI-FUNCTIONAL PRESET COUNTER
The H7CX series offers the ultimate in versatility and intuitive programming.
• 7 basic functions in one
• Switching colour on threshold, green, orange & red
• Twin counter mode
• 12 different outputs modes
• Display 6 digits from -100 K +1 up to 1 M -1
H7CX – Designed with value added features
438
Page 442 Page 443 Page 444
Counters
H7CX
H8GN
counter/timer
48x24 mm
(1/32 DIN)
48x48 mm
(1/16 DIN)
Which size is required?
Pre-set counter
time count
What is the type of counting application?
H8PS
96x96 mm
(1/4 DIN)
Which size is required?
Cam positioner
439
22 Counters
Page 445 Page 446 Page 447
440
Selection table
Category Self-powered total Self-powered timer Self-powered tachometer
Selection criteria
Model H7EC H7ET H7ER
Display LCD
Size 1/32 DIN
Outputs
Control outputs – – –
5 stage – – –
Total –
Time – –
Preset – – –
Batch – – –
Dual – – –
Tachometer –
Inputs
Control inputs No-voltage, PNP/NPN, DC-voltage,
AC/DC multi-voltage
No-voltage, PNP/NPN, DC-voltage,
AC/DC multi-voltage
No-voltage,
PNP/NPN
Features
Dual operation – – –
Number of digits 8 7 4 or 5
NPN/PNP switch
Back-lit
External reset –
Manual reset –
Number of banks – – –
Built-in sensor power supply – – –
IP rating IP66 IP66 IP66
Terminals
Screw terminals
PCB terminals – – –
11-pin socket – – –
Supply
voltage
100 to 240 VAC – – –
12 to 24 VDC – – –
24 VDC
Comms – – –
Functions
Up –
Down – – –
Up/down – – –
Reversible – – –
Speed 0 to 30 Hz or 0 to 1 kHz – 1 or 10 kHz
Counting range 0 to 99999999 0.0 h to 999999.9 h <-->
0.0 h to 3999 d 23.9 h or
0 s to 999 h 59 min 59 s <-->
0.0 min to 9999 h 59.9 min
1000 s-1 or 1000 min-1; 1000 s-1 or
1000 min-1 <--> 10000 min-1
Colour
Beige
Black
Page 442 443 444
Counters
441
22 Counters
Counter type Pre-set counter/timer Pre-set counter Cam positioner
Selection criteria
Model H8GN H7CX H8PS
Display LCD negative transmissive LCD negative transmissive
Size 1/32 DIN 1/16 DIN 1/4 DIN
Outputs
Control outputs 1 relay (SPDT) 1 relay (SPDT), transistor NPN or PNP, cam outputs 8/16/32, run out,
tachometer
5 stage –
Total –
Time – –
Preset –
Batch –
Dual –
Tachometer – –
Inputs
Control inputs No-voltage No-voltage,
PNP/NPN
Encoder
Features
Dual operation
Number of digits PV: 4, SV: 4 PV: 4, SV: 4
or PV: 6, SV: 6
7
NPN/PNP switch – –
Back-lit –
External reset –
Manual reset 8 (16- and 32-output models only)
Number of banks 4 – –
Built-in sensor power supply – –
IP rating IP66 IP66 IP40
Terminals
Screw terminals
PCB terminals – –
11-pin socket – –
Supply
voltage
100 to 240 VAC – –
12 to 24 VDC – –
24 VDC –
Comms – –
Functions
Up –
Down –
Up/down – –
Reversible –
Speed 0 to 30 Hz or 0 to 5 kHz 0 to 30 Hz or 0 to 5 kHz –
Counting range -999 to 9999 -99999 to 999999 –
Colour
Beige – –
Black –
Page 445 446 447
Standard Available – No/not available
442
H7EC Totalisers
Self-powered LCD totaliser
The H7E series is available with large display with 8.6 mm character height.
It includes models with backlight for improved visibility in dimly lit places.
The H7E family includes total counters, time counters, tachometers and
PCB mounted counters.
• Size in mm (HxWxD): 24x48x55.5, 1/32 DIN size housing
• 8 digits, 8.6 mm character height
• Black or light-grey housing
• Dual input speed: 30 Hz <-> 1 kHz
• Short body: all models have a depth of 48.5 mm
Ordering information
Specifications
Count input Max. counting speed Display Order code
Light grey body Black body
No-voltage 30 Hz <-> 1 kHz (switchable) 7-segment LCD H7EC-N H7EC-N-B
PNP/NPN universal DC
voltage input
30 Hz <-> 1 kHz (switchable) 7-segment LCD H7EC-NV H7EC-NV-B
7-segment LCD with backlight H7EC-NV-H H7EC-NV-BH
AC/DC multi-voltage input 20 Hz 7-segment LCD H7EC-NFV H7EC-NFV-B
Item H7EC-NV-_/H7EC-NV-_H H7EC-NFV-_ H7EC-N-_
Operating mode Up type
Mounting method Flush mounting
External connections Screw terminals, optional wire-wrap terminals
Number of digits 8
Display 7-segment LCD with or without backlight, zero suppression (character height: 8.6 mm)
Max. counting speed 30 Hz/1 kHz 20 Hz 30 Hz/1 kHz
Case colour Light grey or black (-B models)
Attachment Waterproof packing, flush mounting bracket
Supply voltage Backlight model: 24 VDC (0.3 W max.)
(only for backlight)
No-backlight model: Not required
(powered by built-in battery)
Not required (powered by built-in battery)
Count input High (logic) level: 4.5 to 30 VDC
Low (logic) level: 0 to 2 VDC
(input impedance: Approx. 4.7 k)
High (logic) level:
24 to 240 VAC/VDC, 50/60 Hz
Low (logic) level:
0 to 2.4 VAC/VDC, 50/60 Hz
No voltage input
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Reset input No voltage input Minimum open impedance: 750 k min.
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Minimum open impedance: 750 k min.
Minimum signal width 20 Hz: 25 ms, 30 Hz: 16.7 ms, 1 KHz: 0.5 ms
Reset system External reset and manual reset: Minimum signal width of 20 ms
Ambient temperature Operating: -10 to 55°C (with no condensation or icing), storage: -25 to 65°C (with no condensation or icing)
Degree of protection Front-panel: IP66, NEMA4, terminal block: IP20
Battery life (reference) 7 years min. with continuous input at 25°C (lithium battery)
Size in mm (HxWxD) 24x48x55.5
443
22 Counters
H7ET Totalisers
Self-powered time counter
The H7E series is available with large display with 8.6mm character height.
It includes models with backlight for improved visibility in dimly lit places.
The H7E family includes total counters, time counters, tachometers and
PCB mounted counters.
• Size in mm (HxWxD) 24x48x55.5, 1/32 DIN size housing
• 7 digits, 8.6mm character height
• Black or light-grey housing
• Dual time range 999999.9 h <-> 3999 d 23.9 h
or 999 h 59 m 59 s <-> 9999 h 59.9m
Ordering information
Specifications
Timer input Display Order code
Time range 999999.9h <-> 3999d23.9h (switchable) Time range 999h59m59s <-> 9999h59.9m
Light grey body Black body Light grey body Black body
No-voltage input 7-segment LCD H7ET-N H7ET-N-B H7ET-N1 H7ET-N1-B
PNP/NPN universal
DC voltage input
7-segment LCD H7ET-NV H7ET-NV-B H7ET-NV1 H7ET-NV1-B
7-segment LCD with backlight H7ET-NV-H H7ET-NV-BH H7ET-NV1-H H7ET-NV1-BH
AC/DC multi-voltage input 7-segment LCD H7ET-NFV H7ET-NFV-B H7ET-NFV1 H7ET-NFV1-B
Item H7ET-NV_-_/H7ET-NV_-_H H7ET-NFV_-_ H7ET-N_-_
Operating mode Accumulating
Mounting method Flush mounting
External connections Screw terminals
Display 7-segment LCD with or without backlight, zero suppression (character height: 8.6 mm)
Number of digits 7
Case colour Light grey or black (-B models)
Attachment Waterproof packing, flush mounting bracket, time unit labels
Supply voltage Backlight model: 24 VDC (0.3 W max.)
(for backlight)
No-backlight model: Not required
(powered by built-in battery)
Not required (powered by built-in battery)
Timer input High (logic) level: 4.5 to 30 VDC
Low (logic) level: 0 to 2 VDC
(Input impedance: Approx. 4.7 k)
High (logic) level:
24 to 240 VAC/VDC, 50/60 Hz
Low (logic) level:
0 to 2.4 VAC/VDC, 50/60 Hz
No voltage input
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Reset input No voltage input Minimum open impedance: 750 k min.
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Minimum open impedance: 750 k min.
Minimum pulse width 1 s
Reset system External reset and manual reset: Minimum signal width of 20 ms
Ambient temperature Operating: -10 to 55°C (with no condensation or icing), storage: -25 to 65°C (with no condensation or icing)
Time accuracy ±100 ppm (25°C)
Degree of protection Front-panel: IP66, NEMA4 with waterproof packing, terminal block: IP20
Battery life (reference) 10 years min. with continuous input at 25°C (lithium battery)
Size in mm (HxWxD) 24x48x55.5
444
H7ER Totalisers
Self-powered tachometer
The H7E series is available with large display with 8.6mm character height.
It includes models with backlight for improved visibility in dimly lit places.
The H7E family includes total counters, time counters, tachometers and
PCB mounted counters.
• Size in mm (HxWxD) 24x48x53.5, 1/32 DIN size housing
• 5 digits, 8.6mm character height
• Black or light-grey housing
• Dual revolution display
Ordering information
Specifications
Count input Display Order code
Max. revolutions displayed (applicable encoder resolution)
1,000 s-1 (1 pulse/rev.)
1,000 min-1 (60 pulse/rev.)
1,000.0 s-1 (10 pulse/rev)
1,000.0 min-1 (600 pulse/rev) <->
10,000 min-1 (60 pulse/rev) (switchable)
Light grey body Black body Light grey body Black body
No-voltage input 7-segment LCD H7ER-N H7ER-N-B
PNP/NPN universal
DC voltage input
7-segment LCD H7ER-NV H7ER-NV-B H7ER-NV1 H7ER-NV1-B
7-segment LCD with backlight H7ER-NV-H H7ER-NV-BH H7ER-NV1-H H7ER-NV1-BH
Item H7ER-NV1-_/H7ER-NV1-_H H7ER-NV-_/H7ER-NV-_H H7ER-N-_
Operating mode Up type
Mounting method Flush mounting
External connections Screw terminals, wire-wrap terminals
Display 7-segment LCD with or without backlight, zero suppression (character height: 8.6 mm)
Number of digits 5 4
Max. revolutions displayed 1,000.0 s-1 (when encoder resolution
of 10 pulse/rev is used)
1,000.0 min-1 (when encoder resolution
of 600 pulse/rev is used)
<-> 10,000 min-1 (when encoder resolution
of 60 pulse/rev is used)
(switchable with switch)
1,000 s-1 (when encoder resolution of 1 pulse/rev is used)
1,000 min-1 (when encoder resolution of 60 pulse/rev is used)
Attachment Waterproof packing, flush mounting bracket, revolution unit labels
Supply voltage Backlight model: 24 VDC (0.3 W max.) (for backlight lit)
No-backlight model: Not required (powered by built-in battery)
Not required (powered by built-in battery)
Count input High (logic) level: 4.5 to 30 VDC
Low (logic) level: 0 to 2 VDC
(Input impedance: Approx. 4.7 k)
No voltage input
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Minimum open impedance: 750 k min.
Max. counting speed 10 kHz 1 kHz
Minimum signal width 10 kHz: 0.05 ms, 1 kHz: 0.5 ms
Ambient temperature Operating: -10 to 55°C (with no condensation or icing), storage: -25 to 65°C (with no condensation or icing)
Degree of protection Front-panel: IP66, NEMA4 with waterproof packing, terminal block: IP20
Battery life (reference) 7 years min. with continuous input at 25°C (lithium battery)
Size in mm (HxWxD) 24x48x53.5
445
22 Counters
H8GN Pre-set counters
World’s smallest compact preset
counter/timer
The H8GN is a 1/32 DIN timer and counter in one. It is simple to switch between the
timer and counter functions. During operation it is also possible to switch the display
to monitor the totalising count value in 8 digits. Many sophisticated functions come
as standard with H8GN.
• Size in mm (HxWxD) 24x48x83, 1/32 DIN size housing
• 8 digit display, 4 value and 4 set value
• Front mounting
• -999 to 9999
• 24 VDC
Ordering information
Specifications
Functions Supply voltage Output Order code
Communications
Counter Timer No communications RS-485
Counter: Up/down/reversible,
4 digits, N, F, C or K output modes
Total counter: 8 digits
A: ON-delay
B: Flicker
D: Signal OFF-delay
E: Interval
F: Accumulative
Z: ON/OFF-duty adjustable flicker
24 VDC Contact output (SPDT) H8GN-AD H8GN-AD-FLK
Rated supply voltage 24 VDC
Operating voltage range 85 to 110% of rated supply voltage
Power consumption 1.5 W max. (for max. DC load) (inrush current: 15 A max.)
Mounting method Flush-mounting
External connections Screw terminals (M3 screws)
Terminal screw tightening torque 0.5 Nm max.
Attachment Waterproof packing, flush-mounting bracket
Display 7-segment, negative transmissive LCD; time display (h, min, s); CMW, OUT, RST, TOTAL
Present value (red, 7 mm high characters); set value (green, 3.4 mm high characters)
Digits PV: 4 digits, SV: 4 digits, when total count value is displayed: 8 digits (zeros suppressed)
Memory backup EEPROM (non-volatile memory) (number of writes: 100,000 times)
Counter Maximum counting speed 30 Hz or 5 kHz
Counting range -999 to 9,999
Input modes Increment, decrement, individual, quadrature inputs
Timer Timer modes Elapsed time (up), remaining time (down)
Inputs Input signals For counter: CP1, CP2, and reset
For timer: Start, gate, and reset
Input method No-voltage input (contact short-circuit and open input)
Short-circuit (ON) impedance: 1 k max. (approx. 2 mA runoff current at 0 )
Short-circuit (ON) residual voltage: 2 VDC max.
Open (OFF) impedance: 100 k min.
Applied voltage: 30 VDC max.
Start, reset, gate Minimum input signal width: 1 or 20 ms (selectable)
Power reset Minimum power-opening time: 0.5 s
Control output SPDT contact output: 3 A at 250 VAC/30 VDC, resistive load (cos = 1)
Minimum applied load 10 mA at 5 VDC (failure level: P, reference value)
Reset system External, manual, and power supply resets (for timer in A, B, D, E, or Z modes)
Sensor waiting time 260 ms max.
(inputs cannot be received during sensor wait time if control outputs are turned OFF)
Timer function Accuracy of operating time and setting error
(including temperature and voltage effects)
Signal start: ±0.03% ±30 ms max.
Power-ON start: ±0.03% ±50 ms max.
Ambient
temperature
Operating storage -10 to 55°C (with no icing or condensation)
-25 to 65°C (with no icing or condensation)
Case colour Rear section: Grey smoke; front section: N1.5 (black)
Degree of protection Panel surface: IP66 and NEMA Type 4X (indoors); rear case: IP20, terminal block: IP20
Size in mm (HxWxD) 24x48x83
446
H7CX Pre-set counters
The most complete digital standard counter
on the market
H7CX offers you the most complete series of products on the market today.
Based on extensive customer research, these new counters have been designed with
value added features that users both need and appreciate.
• Size in mm (HxWxD) 48x48x59 to 78mm 1/16 DIN size housing
• Three colour display value, red, green or orange
• Twin counter mode
• 6 digit model -99,999 to 999,999, set value -99,999 to 999,999 or 0 to 999,999
• Input contact, NPN or PNP
Ordering information
Accessories
Specifications
Type External
connection
Sensor power
supply
Supply voltage Output type Digits Size in mm (HxWxD) Order code
1-stage counter
1-stage counter with total counter
2-stage counter
1-stage counter with batch counter
Dual counter (addition/subtraction)
Tachometer
Twin counter
Screw terminal 12 VDC 100 to 240 VAC Contact and transistor
output
6 48x48x84 H7CX-AU-N
12 to 24 VDC/24 VAC H7CX-AUD1-N
Transistor output (2x) H7CX-AUSD1-N
100 to 240 VAC Contact output (2x) H7CX-AW-N
12 to 24 VDC/24 VAC H7CX-AWD1-N
1-stage counter
1-stage counter with total counter
11-pin socket 12 VDC 100 to 240 VAC Contact output 48x48x69.7 H7CX-A11-N
12 to 24 VDC/24 VAC H7CX-A11D1-N
100 to 240 VAC Transistor output H7CX-A11S-N
12 to 24 VDC/24 VAC H7CX-A11SD1-N
Screw terminal 100 to 240 VAC Contact output 48x48x84 H7CX-A-N
100 to 240 VAC Transistor output H7CX-AS-N
Name Order code
Flush-mounting adapter Y92F-30
Waterproof packing Y92S-29
DIN-rail mounting/front-connecting socket 11-pin, finger safe type P2CF-11-E
Back-connecting socket 11-pin P3GA-11
Finger safe terminal cover for P3GA-11 Y92A-48G
Hard cover Y92A-48
Soft cover Y92A-48F1
Front panels
(4-digit models)
Light gray Y92P-CXC4G
White Y92P-CXC4S
Front panels
(6-digit models)
Light gray Y92P-CXC6G
White Y92P-CXC6S
Display 7-segment, negative transmissive LCD
Digits 6-digits: -99,999 to 999,999, SV range: -99999 to 999999 or 0 to 999999
Max. counting speed 30 Hz or 5 kHz (selectable, ON/OFF ratio 1:1)
Input modes Increment, decrement, increment/decrement (UP/DOWN A (command input), UP/DOWN B (individual inputs), or UP/DOWN C (quadrature inputs))
Control output Contact output: 3 A at 250 VAC/30 VDC, resistive load (cos= 1)
Minimum applied load: 10 mA at 5 VDC
Transistor output:NPN open collector, 100 mA at 30 VDC
Residual voltage: 1.5 VDC max. (approx. 1V)
Leakage current: 0.1 mA max.
Key protection Yes
Decimal point adjustment Yes (rightmost 3 digits)
Sensor waiting time 290 ms max.
Memory backup EEPROM (overwrites: 100,000 times min.) stores data 10 years min.
Ambient temperature Operating: -10 to 55°C (-10 to 50°C when mounted side by side)
Case colour Black (N1.5) (Optional Front Panels are available to change the Front Panel colour to light gray or white.)
Life expectancy Mechanical: 10,000,000 operations min.
Electrical: 100,000 operations min. (3 A at 250 VAC, resistive load)
Degree of protection Panel surface: IP66, NEMA 4 (indoors), and UL Type 4X (indoors)
447
22 Counters
H8PS Cam positioners
Compact, easy-to-use cam positioner
The H8PS provides high speed operation at 1,600 r/min and high-precision
settings to 0.5° ensuring widespread application. H8PS features a highly visible
display with back-lit negative transmissive LCD. Advance angle compensation
function compensates for output delays.
• 96 to 121.2Hx96Wx60.6 to 67.5D mm
• Front-panel / DIN-rail
• 24 VDC
• 8-, 16- and 32-outputs
• NPN/PNP 100 mA at 30 VDC
Ordering information
Encoders Accessories
Encoder accessories
Specifications
Number of
outputs
Mounting method Output configuration Bank function Size in mm (HxWxD) Order code
8-outputs Flush-mounting NPN transistor output No 96x96x67.5 H8PS-8B
PNP transistor output H8PS-8BP
Front-mounting/DIN-rail mounting NPN transistor output 96x96x60.6 H8PS-8BF
PNP transistor output H8PS-8BFP
16-outputs Flush-mounting NPN transistor output Yes 96x96x67.5 H8PS-16B
PNP transistor output H8PS-16BP
Front-mounting/DIN-rail mounting NPN transistor output 121.2x96x60.6 H8PS-16BF
PNP transistor output H8PS-16BFP
32-outputs Flush-mounting NPN transistor output 96x96x67.5 H8PS-32B
PNP transistor output H8PS-32BP
Front-mounting/DIN-rail mounting NPN transistor output 121.2x96x60.6 H8PS-32BF
PNP transistor output H8PS-32BFP
Type Resolution Cable length Order code
Economy 256 2 m E6CP-AG5C-C 256 2M
Standard 256 1 m E6C3-AG5C-C 256 1M
2 m E6C3-AG5C-C 256 2M
360 E6C3-AG5C-C 360 2M
720 E6C3-AG5C-C 720 2M
Rigid 256 2 m E6F-AG5C-C 256 2M
360 E6F-AG5C-C 360 2M
720 E6F-AG5C-C 720 2M
Name Specification Order code
Discrete wire output cable 2 m Y92S-41-200
Connector-type output cable 2 m E5ZE-CBL200
Support software CD-ROM H8PS-SOFT-V1
USB cable A miniB, 2 m Y92S-40
Parallel input adapter Two units can operate
in parallel
Y92C-30
Protective cover Y92A-96B
Watertight cover Y92A-96N
DIN-rail mounting base Y92F-91
Name Specification Order code
Shaft coupling for the E6CP Axis: 6 mm dia. E69-C06B
Shaft coupling for the E6C3 Axis: 8 mm dia. E69-C08B
Shaft coupling for the E6F Axis: 10 mm dia. E69-C10B
Extension cable 5 m (same for E6CP, E6C3, and E6F) E69-DF5
Rated supply voltage 24 VDC
Inputs Encoder input 8-output models: None; 16-/32-output models: Bank inputs 1/2/4, origin input, start input
External inputs Input signals 8-output models: None; 16-/32-output models: Bank inputs 1/2/4, origin input, start input
Input type No voltage inputs: ON impedance: 1 k max. (leakage current: Approx. 2 mA at 0 )
ON residual voltage: 2 V max., OFF impedance: 100 k min., applied voltage: 30 VDC max.
Minimum input signal width: 20 ms
Number of banks 8 banks (for 16-/32-output models only)
Display method 7-segment, negative transmissive LCD (main display: 11 mm (red), sub-display: 5.5 mm (green))
Memory backup method EEPROM (overwrites: 100,000 times min.) that can store data for 10 years min.
Ambient operating temperature -10 to 55°C (with no icing or condensation)
Storage temperature -25 to 65°C (with no icing or condensation)
Ambient humidity 25 to 85%
Degree of protection Panel surface: IP40, rear case: IP20
Case colour Light grey (Munsell 5Y7/1)
ZEN-10C2
10 (6 I, 4 O)
expandable
up to 34 I/O
ZEN-20C2
How many I/O points?
LED type
20 (12 I, 8 O)
expandable
up to 44 I/O
FLEXIBLE AUTOMATION EXPANDED
Our range is extended with a communication model. Now you have the possibility to
connect several ZEN in a network environment. This will enhance the ZEN series to
solve even more applications.
• RS-485 communication
• To connect up to 32 units
• Easy CompoWayF protocol
ZEN-C4 – More flexibility with RS-485 communication
448
Page 452 Page 453
Programmable relays
ZEN-10C1
What functionality is required?
ZEN-20C1 ZEN-10C3 ZEN-20C3 ZEN-10C4 ZEN-8E
10 (6 I, 4 O)
expandable
up to 34 I/O
20 (12 I, 8 O)
expandable
up to 44 I/O
10 (6 I, 4 O)
fixed I/O
20 (12 I, 8 O)
fixed I/O
10 (6 I, 4 O)
expandable
up to 33 I/O
with
communication
How many I/O points?
Display type with
buttons, calendar
and clock
Expansion
unit
8 I/O
(4 I, 4 O)
How many extra
I/O points?
449
23 Programmable relays
Page 452 Page 453 Page 452 Page 453 Page 452 Page 454
450
Programmable relays
451
23 Programmable relays
Model ZEN-10C ZEN-20C
Type CPU unit CPU unit
Features C1 With LCD Display,
program/control buttons,
calendar and real-time clock
With LCD display,
program/control buttons,
calendar and real-time clock
Features C2 With LED indication
Logic control
Programming by software
With LED indication
Logic control
Programming by software
Features C3 Same as C1 but not expandable. Same as C1 but not expandable.
Features C4 Same as C1 but instead of one output
relay you get RS-485 communication.
–
Features Starter kits Complete set with C1 CPU including
software, cable and manual
–
Number of I / O points 10 expandable up to 34 I/O
(C4 up to 33 I/O)
20 expandable up to 44 I/O
Inputs 6 12
Inputs/power supply 100 to 240 VAC or 12 to 24 VDC 100 to 240 VAC or 12 to 24 VDC
Outputs 4 relays (C4 = 3 relays) or
4 transistors
8 relays or 8 transistors
Page 452 453
– No/not available
Selection table
452
ZEN-10C Programmable relays
Flexible automation
The ZEN-10C offers simple logic control in a choice of four CPU units. Expansion is
possible on three of these CPU's of up to 34 I/O whereas the fourth (C3 Units) is fixed
at 10 I/O. All DC models have analogue input and a high-speed counter input up to
150 Hz.
• DC input/supply units have analogue input + high speed counter
• The ZEN-10C4 has RS-485 communication
• Expansion available with relay output or transistor output
• ZEN-Kits the best choice to start!
Ordering information
Specifications
Accessories
Name Number of
I/O points
Inputs (I)/
power supply
Outputs (Q) Type LCD, buttons
(B), calendar
and clock
Analogue
input/
comparators
(A)
8-digit
counter (F)/
comparators
(G)
No. of bits 16 No. of bits 8 Size in mm
(HxWxD)
Order code
CPU units 10
Expandable
up to
34 I/O
6 100 to 240 VAC 4 Relays LCD yes – – Work bits (M)
Holding bits (H)
Timers (T)
Counters (C)
Weekly timers (@)
LCD display (D)
Timer/counter
comparator (P)
Holding timers (#)
Button input (B)
90x70x56 ZEN-10C1AR-A-V2
LED – – – ZEN-10C2AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-10C1DR-D-V2
LED – yes / 4 yes / 4 ZEN-10C2DR-D-V2
Transistors
LCD yes yes / 4 yes / 4 ZEN-10C1DT-D-V2
LED – yes / 4 yes / 4 ZEN-10C2DT-D-V2
Fixed I/O 100 to 240 VAC Relays LCD yes – yes / 4 ZEN-10C3AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-10C3DR-D-V2
10
Expandable
up to
33 I/O
100 to 240 VAC 3 LCD/
Comm.
yes – yes / 4 ZEN-10C4AR-A-V2
12 to 24 VDC yes yes / 4 yes / 4 ZEN-10C4DR-D-V2
ZEN kit Set containing CPU unit (ZEN-10C1AR-A-V2), connecting cable,
ZEN support software and manual.
ZEN-KIT01-EV4
Set containing CPU unit (ZEN-10C1DR-D-V2), connecting cable,
ZEN support software and manual.
ZEN-KIT02-EV4
Item Specifications
ZEN-10C_AR-A-V2 ZEN-10C_D_-D-V2
Power supply voltage 100 to 240 VAC, 50/60 Hz 12 to 24 VDC (DC ripple rate: 5%)
Rated power supply voltage 85 to 264 VAC 10.8 to 28.8 VDC
Power consumption 9 VA max. 4 W max.
Inrush current 3 A max. 30 A max.
Ambient temperature 0°C to 55°C (-25°C to 55°C for ZEN-10C2 models (LED))
Ambient storage -20°C to 55°C (-40°C to 75°C for ZEN-10C2 models (LED))
Control method Stored program control
I/O control method Cyclic scan
Programming language Ladder diagram
Program capacity 96 lines (3 input conditions and 1 output per line)
LCD display 12 characters x 4 lines, with backlight (LCD-type CPU unit only)
Operation keys 8 (4 cursor keys and 4 operation keys) (LCD-type CPU unit only)
Super-capacitor holding time 2 days min. (25°C)
Battery life (ZEN-BAT01) 10 years min. (25°C)
Calendar & Clock function Accuracy: ± 15 s/month (at 25°C)
Name Description Order code
Memory Cassette EEPROM (for data security and copying) ZEN-ME01
Battery unit Battery (keeps time, date and bit values for 10 years at 25°C) ZEN-BAT01
Connecting Cable For the programming software, RS-232C cable, 9-way `D' connector for PC ZEN-CIF01
USB-Serial conversion cable USB-Serial conversion cable (to be used in combination with ZEN-CIF01) CS1W-CIF31
ZEN support software Runs on Windows ME, 2000, XP, NT4.0 Service Pack 3, Vista ZEN-SOFT01-V4
453
23 Programmable relays
ZEN-20C Programmable relays
Extended flexible automation
Ideal for small-scale control applications, the ZEN-20C provides an economical
alternative to discrete timers, counters and general purpose relays. With 12 Inputs
and 8 relay or transistor Outputs, and expansion possibilities of up to 44 I/O on C1
and C2 models, the ZEN-20C offers extended flexibility, with features such as
calendar and real time clock functionality.
• ZEN-20C1/C2 expandable up to 44 I/Os
• ZEN DC units have analogue input 0-10 VDC
• DC models have as well high speed counter 150 Hz
• Expansion available with relay output or transistor output
Ordering information
Specifications
Accessories
Name Number of
I/O points
Inputs (I)/
power supply
Outputs (Q) Type LCD, buttons
(B), calendar
and clock
Analogue
input/
comparators
(A)
8-digit
counter (F)/
comparators
(G)
No. of bits 16 No. of bits 8 Size in mm
(HxWxD)
Order code
CPU units 20 12 100 to 240 VAC 8 Relays LCD yes – – Work bits (M)
Holding bits (H)
Timers (T)
Counters (C)
Weekly timers (@)
LCD display (D)
Timer/counter
comparator (P)
Holding timers (#)
Button input (B)
90x122.5 x56 ZEN-20C1AR-A-V2
Expandable
up to 44 I/O
LED – – – ZEN-20C2AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-20C1DR-D-V2
LED – yes / 4 yes / 4 ZEN-20C1DR-D-V2
Transistors
LCD yes yes / 4 yes / 4 ZEN-20C1DT-D-V2
LED – yes / 4 yes / 4 ZEN-20C2DT-D-V2
Fixed I/O 100 to 240 VAC Relays LCD yes – yes / 4 ZEN-20C3AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-20C3DR-D-V2
Item Specifications
ZEN-20C_AR-A-V2 ZEN-20C_D_-D-V2
Power supply voltage 100 to 240 VAC, 50/60 Hz 12 to 24 VDC (DC ripple rate: 5%)
Rated power supply voltage 85 to 264 VAC 10.8 to 28.8 VDC
Power consumption 11 VA max. 5 W max.
Inrush current 4 A max. 30 A max.
Ambient temperature 0°C to 55°C (-25°C to 55°C for ZEN-20C2 models (LED))
Ambient storage -20°C to 55°C (-40°C to 75°C for ZEN-20C2 models (LED))
Control method Stored program control
I/O control method Cyclic scan
Programming language Ladder diagram
Program capacity 96 lines (3 input conditions and 1 output per line)
LCD display 12 characters x 4 lines, with backlight (LCD-type CPU unit only)
Operation keys 8 (4 cursor keys and 4 operation keys) (LCD-type CPU unit only)
Super-capacitor holding time 2 days min. (25°C)
Battery life (ZEN-BAT01) 10 years min. (25°C)
Calendar & Clock function Accuracy: ± 15 s/month (at 25°C) if applicable
Name Description Order code
Memory Cassette EEPROM (for data security and copying) ZEN-ME01
Battery unit Battery (keeps time, date and bit values for 10 years at 25°C) ZEN-BAT01
Connecting Cable For the programming software, RS-232C cable, 9-way `D' connector for PC ZEN-CIF01
USB-Serial conversion cable USB-Serial conversion cable (to be used in combination with ZEN-CIF01) CS1W-CIF31
ZEN support software Runs on Windows ME, 2000, XP, NT4.0 Service Pack 3, Vista ZEN-SOFT01-V4
454
ZEN-8E Programmable relays
ZEN Expansion units
To enlarge your ZEN application we provide three different expansion units in
only 35 mm width ZEN housing. All expansion units have standard 4 inputs and
4 outputs. You can add maximum 3 expansion units to one CPU.
• 4 inputs, 100 to 240VAC or 12 to 24VDC
• 4 outputs, either relays or transistors (only DC models)
• DIN-rail mounting
• Size in mm (HxWxD): 90x35x56
Ordering information
Specifications
Name Number of I/O points Inputs (X)/
power supply
Outputs (Y) Size in mm (HxWxD) Order code
Expansion I/O units 8 4 100 to 240 VAC 4 Relays 90x35x56 ZEN-8E1AR
12 to 24 VDC ZEN-8E1DR
Transistors ZEN-8E1DT
Item Specifications
ZEN-8E1AR ZEN-8E1D_
Power supply voltage 100 to 240 VAC, 50/60 Hz 12 to 24 VDC (DC ripple rate: 5% max.)
Rated power supply voltage 85 to 264 VAC 10.8 to 28.8 VDC
Power consumption 4 VA max. 2 W max.
Inrush current 1.5 A max. 15 A max.
Ambient temperature 0°C to 55°C (-25°C to 55°C for ZEN-10C2 models (LED))
Ambient storage -20°C to 55°C (-40°C to 75°C for ZEN-10C2 models (LED))
455
23 Programmable relays
ZEN-PA Programmable relays
ZEN Power Supply
The ZEN Power Supply has the same compact housing as our 10 I/O CPU units.
With a current/wattage output of 1.3 A/30 W it covers enough power to supply
the DC ZEN itself and the eventually used sensors. If needed parallel operation is
possible.
• Output voltage 24 VDC
• Output current 1.3 A
• Capacity 30 W
• Allows parallel operation
• Size in mm (HxWxD): 90x70x56
Ordering information
Specifications
Power rating Inputs voltage Output current Order code
30 W 100 to 240 VAC 1.3 A ZEN-PA03024
Item Specifications
Power rating 30 W
Efficiency 80% min. (24 V)
Input voltage 100 to 240 VAC (85 to 264 VAC), single-phase
Output voltage Voltage adjustment ±10% to ±15% (with V. ADJ) min. of rate output voltage
Ripple 2% (p-p) max. (-25°C to -10°C: 4% max.)
Input variation 0.5% max.
Temperature 0.05% / °C max.
Overload protection 105% to 135% of rated load current, inverted L drop, intermittent
Overvoltage protection yes
Input Current 100 V 0.8 A max.
200 V 0.45 A max.
Output indicator yes (green)
Weight 240 g max.
Operating temperature -10°C to 60°C
Parallel operation yes (2 units max.)
Which size is required?
K3GN K3MA-J K3MA-L K3MA-F
Which application is required?
Process Temperature
Frequency/
rate
Process/
frequency/
rate
General purpose
48x24 mm
(1/32 DIN)
LOOKING FOR PERFECT MEASURING & READ-OUT?
With our K3HB series we cover a wide range of applications. One of them is the
weighing indicator which performs perfect measurement in any weighing application.
The instrument can be equipped with a load-cell power supply of 10 V/100 mA.
Several option boards for communication, contact output boards or event inputs
are also available. On top of these you can get direct DeviceNet communication.
• High speed sampling 20 ms
• Equipped with position meter
• Two colour display for easy recognition
K3HB-V – For perfect weighing
456
Page 460 Page 461 Page 461 Page 461
Digital panel indicators
Which application is required?
K3HB-X
Process
K3HB-H
Temperature
Advanced
K3HB-V
Weighing
96x48 mm
(1/8 DIN)
K3HB-S
Linear sensor
K3HB-R
Rotary pulse
K3HB-P
Time interval
K3HB-C
Up/down
counting pulse
457
24 Digital panel indicators
Page 462 Page 462 Page 462 Page 462 Page 464 Page 464 Page 464
458
Selection table
Category Multifunctional digital
panel indicator Process indicator Temperature indicator Frequency/rate indicator Process indicator
Selection criteria
Model K3GN K3MA-J K3MA-L K3MA-F K3HB-X
Size 1/32 DIN 1/8 DIN
Features
Colour change display
Number of digits 5 5 4 5 5
Leading zero suppression
Forced zero function
Min./max. hold function
Average processing
User selectable inputs
Start-up compensating time – – –
Key protection
Decimal point position setting
Accuracy ±0.1% of full scale ±0.1% of full scale ±0.1% of full scale ±0.1% of full scale ±0.1% of full scale
(DC voltage &
DC current),
±0.5% of full scale
(AC voltage & AC current)
Input range 0 to 20 mA, 4 to 20 mA
or 0 to 5 V, 1 to 5 V,
-5 to 5 V, -10 to 10 V or
0 to 30 Hz or 0 to 5 kHz
0 to 20 mA, 4 to 20 mA
or 0 to 5 V, 1 to 5 V,
-5 to 5 V, -10 to 10 V
Pt100, JPt100 or
thermocouple K, J, T, E, L,
U, N, R, S, B
0 to 30 Hz or 0 to 5 kHz 0.000 to 10.000 A, 0.0000
to 19.999 mA, -199.99 to
199.99 mA, 4.000 to
20.000 mA, 0.0 to 400.0
V, 0.0000 to 1.999 V,
-199.99 to 199.99 V,
1.0000 to 5.0000 V
Sample rate 250 ms 250 ms 500 ms – 20 ms
Features Remote/local processing,
parameter initialisation,
programmable output
configuration,
process value hold
Teaching, comparative
output pattern selection,
parameter initialisation,
programmable output
configuration,
process value hold
Programmable output
configuration,
process value hold
Teaching, comparative
output pattern selection,
programmable output
configuration,
process value hold
Scaling, teaching,
averaging, output
hysteresis, output
OFF-delay, output test,
bank selection, reset,
comparative output
Sensor power supply – – –
Front
protection
IP rating IP66 IP66 IP66 IP66 IP66
Supply voltage 24 VDC 24 VAC/VDC or
100 to 240 VAC
24 VAC/VDC or
100 to 240 VAC
24 VAC/VDC or
100 to 240 VAC
100 to 240 VAC or
24 VAC/VDC
Inputs
NPN –
PNP –
Temperature – – – – –
Contact – – – –
Voltage pulse – – – –
Load cell – – – – –
DC voltage –
DC current – –
AC voltage – – – –
AC current – – – –
Outputs
Relay
NPN – – –
PNP – – –
Linear – – – –
BCD – – – – –
Comms – – –
Page 460 461 462
Digital panel indicators
459
24 Digital panel indicators
Temperature indicator Weighing indicator Linear sensor indicator Up/down counting pulse
indicator Time interval indicator Rotary pulse indicator
K3HB-H K3HB-V K3HB-S K3HB-C K3HB-P K3HB-R
1/8 DIN – –
5 5 5 5 5 5
– – – – –
Thermocouple: ±0.3%
of full scale,
Pt-100: ±0.2% of full scale
±0.1% of full scale One input: ±0.1%
of full scale,
two inputs: ±0.2%
of full scale
±0.08% rgd ±1 digit ±0.006% rgd ±1 digit
±0.02% rgd ±1 digit
Pt100, thermocouple K, J, T,
E, L, U, N, R, S, B, W
0.00 to 199.99 mV,
0.000 to 19.999 mV,
100.00 mV, 199.99 mV
0 to 20 mA, 4 to 20 mA,
0 to 5 V, -5 to 5 V,
-10 to 10 V
No voltage contact:
30 Hz, voltage pulse:
50 kHz, open collector:
50 kHz
No voltage contact:
30 Hz, voltage pulse:
50 kHz, open collector:
50 kHz
No voltage contact:
30 Hz, voltage pulse:
50 kHz, open collector:
50 kHz
20 ms 20 ms 0.5 ms – – –
Scaling, teaching, averaging,
output hysteresis, output
OFF-delay, output test, bank
selection, reset, comparative
output
Scaling, teaching, averaging,
output hysteresis, output
OFF-delay, output test, bank
selection, reset, comparative
output
Scaling, 2-input calculation,
teaching, averaging, output
hysteresis, output OFFdelay,
output test, bank
selection, reset, comparative
output
Scaling, measurement
operation selection, output
hysteresis, output OFFdelay,
output test, display
value selection, display
colour selection, key
protection, bank selection,
display refresh period,
maximum/minimum hold,
reset
Scaling, measurement
operation selection, output
hysteresis, output OFFdelay,
output test, teaching,
display value selection,
display colour selection, key
protection, bank selection,
display refresh period,
maximum/minimum hold,
reset
Scaling, measurement
operation selection,
averaging, previous average
value comparison, output
hysteresis, output
OFF-delay, output test,
teaching, display value
selection, display colour
selection, key protection,
bank selection,
display refresh period,
maximum /minimum hold,
reset
IP66 IP66 IP66 IP66 IP66 IP66
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
– – – – –
– – – – – –
– – –
– – – – –
– – – – –
– – – – –
– – – – – –
– – – – – –
– – –
462 464
Standard Available – No/not available
460
K3GN 1/32 DIN multi-function
Compact and intelligent digital
panel meter
The K3GN is able to cover a wide variety of applications with its 3 main functions:
process meter, RPM processor/tachometer and digital data display for PC/PLC.
Configuration is easy and the design is advanced and compact.
• Process indicator DC voltage/current
• RPM process/tachometer
• Digital data display for PC/PLC
• Very compact 1/32 DIN housing: Size in mm (HxWxD): 24x48x83mm
• 5-digit display with programmable display colour, in red or green
Ordering information
Specifications
Input type Supply voltage Output Order code
No communications RS-485
DC voltage/current, NPN 24 VDC Dual relays (SPST-NO) K3GN-NDC 24 DC K3GN-NDC-FLK 24 DC
Three NPN open collector K3GN-NDT1 24 DC K3GN-NDT1-FLK 24 DC
DC voltage/current, PNP Dual relays (SPST-NO) K3GN-PDC 24 DC K3GN-PDC-FLK 24 DC
Three PNP open collector K3GN-PDT2 24 DC K3GN-PDT2-FLK 24 DC
Supply voltage 24 VDC
Operating voltage range 85 to 110% of the rated supply voltage
Power consumption 2.5 W max. (at max. DC load with all indicators lit)
Ambient temperature Operating: -10 to 55°C (with no condensation or icing)
Storage: -25 to 65°C (with no condensation or icing)
Display refresh period Sampling period (sampling times multiplied by number of averaging times if average processing is selected)
Max. displayed digits 5 digits (-19999 to 99999)
Display 7-segment digital display, character height: 7.0 mm
Polarity display “-” is displayed automatically with a negative input signal
Zero display Leading zeros are not displayed
Scaling function Programmable with front-panel key inputs (range of display: -19999 to 99999).
The decimal point position can be set as desired.
External controls HOLD: (measurement value held)
ZERO: (forced-zero)
Hysteresis setting Programmable with front-panel key inputs (0001 to 9999)
Other functions Programmable colour display
Selectable output operating action
Teaching set values
Average processing (simple average)
Lockout configuration
Communications writing control (communications output models only)
Output Relays: 2 SPST-NO
Transistors: 3 NPN open collector
3 PNP open collector
Combinations:
Communications output (RS-485) + relay outputs
Communications output (RS-485) + transistor outputs
Communications output (RS-485) + transistor outputs (3 PNP open collector)
Communications Communications function: RS-485
Delay in comparative outputs (transistor outputs) 750 ms max.
Degree of protection Front-panel: NEMA4X for indoor use (equivalent to IP66)
Rear case: IEC standard IP20
Terminals: IEC standard IP20
Memory protection Non-volatile memory (EEPROM) (possible to rewrite 100,000 times)
Size in mm (HxWxD) 24x48x80
461
24 Digital panel indicators
K3MA-J, -L, -F 1/8 DIN standard indicators
Highly visible LCD display with
2 colour (red and green) LEDs
The K3MA series comes with a process meter, a frequency/rate meter and a temperature
meter of either 100 to 240 VAC or 24 VAC/VDC. All are equipped with the same
quality display and have the same short depth of 80 mm.
• 1/8 DIN size housing
• Highly visible, negative transmissive backlit LCD display
• 14.2 mm high characters
• 5 digits (-19,999 to 99,999), K3MA-L: 4 digits
• Front-panel IP66
Ordering information
Accessories
Specifications
Indicator Supply voltage Input type & ranges Output Order code
Process meter 100 to 240 VAC DC voltage: 0 to 5 V, 1 to 5 V, -5 to 5 V, -10 to 10 V
DC current: 0 to 20 mA, 4 to 20 mA
2 relay contact outputs (SPST-NO) K3MA-J-A2 100-240VAC
24 VAC/VDC 2 relay contact outputs (SPST-NO) K3MA-J-A2 24VAC/VDC
Temperature meter 100 to 240 VAC Platinum-resistance thermometer: Pt100, JPt100
or thermocouple K, J, T, E, L, U, N, R, S, B
1 relay contact output (SPDT) K3MA-L-C 100-240VAC
24 VAC/VDC 1 relay contact output (SPDT) K3MA-L-C 24VAC/VDC
Frequency/rate meter 100 to 240 VAC Rotary pulse: No voltage: 0.05 to 30.00 Hz;
open collector: 0.1 to 5000.0 Hz
2 relay contact outputs (SPST-NO) K3MA-F-A2 100-240VAC
24 VAC/VDC 2 relay contact outputs (SPST-NO) K3MA-F-A2 24VAC/VDC
Type Order code
Splash-proof soft cover K32-49SC
Hard cover K32-49HC
Item 100-240 VAC models 24 VAC/VDC models
Supply voltage 100 to 240 VAC 24 VAC (50/60 Hz), 24 VDC
Operating voltage range 85 to 110% of the rated supply voltage
Power consumption (under maximum load) 6 VA max. 4.5 VA max. (24 VAC) 4.5 W max. (24 VDC)
Ambient temperature Operating: -10 to 55°C (with no condensation or icing)
Storage: -25 to 65°C (with no condensation or icing)
Weight Approx. 200 g
Display 7-segment digital display, character height: 14.2 mm
Polarity display "-" is displayed automatically with a negative input signal
Zero display Leading zeros are not displayed
Hold function Max. hold (maximum value), min. hold (minimum value)
Hysteresis setting Programmable with front-panel key inputs (0001 to 9,999)
Delay in comparative outputs 1 s max.
Degree of protection Front-panel: NEMA4X for indoor use (equivalent to IP66)
Rear case: IEC standard IP20
Terminals: IEC standard IP00 + finger protection (VDE 0106/100)
Memory protection Non-volatile memory (EEPROM) (possible to rewrite 100,000 times)
Size in mm (HxWxD) 48x96x80
462
K3HB-X, -H, -V, -S 1/8 DIN advanced indicators - analogue input
Process, temperature, weighing and linear
sensor indicators
These indicators with analogue input feature a clear and easy-to-use colour change
display. All models are equipped with an IP66 housing. K3HB series is high speed,
with a sample rate of 50 Hz, and even 2,000 Hz for K3HB-S
• Position meter indication for easy monitoring
• Optional DeviceNet, RS-232C, RS-485
• Double display, with 5 digits, in two colours
• 1/8 DIN size housing
Ordering information
Option boards
Sensor power supply/output boards
Relay/transistor output boards
Event input boards
*1 CPA/CPB can be combined with relay outputs only.
*2 Only one of the following can be used by each digital indicator: RS-232C/RS-485 communications, a linear output, or DeviceNet communications.
K3HB has got three slots for option boards: Slot B, slot C and slot D.
Accessories
Type of indicator Input sensor type and range Supply voltage Order code
Process indicator
K3HB-X
AC current input, from 0.000 to 10.000 A, 0.0000 to 19.999 mA 100 to 240 VAC K3HB-XAA 100-240VAC
24 VAC/VDC K3HB-XAA 24VAC/VDC
DC current input, from ±199.99 mA, to 4.000 to 20.000 mA 100 to 240 VAC K3HB-XAD 100-240VAC
24 VAC/VDC K3HB-XAD 24VAC/VDC
AC voltage input, from 0.0 to 400.0 V to 0.0000 to 1.999 V 100 to 240 VAC K3HB-XVA 100-240VAC
24 VAC/VDC K3HB-XVA 24VAC/VDC
DC voltage input, from ±199.99 V to 1.0000 to 5.0000 V 100 to 240 VAC K3HB-XVD 100-240VAC
24 VAC/VDC K3HB-XVD 24VAC/VDC
Temperature indicator
K3HB-H
Temperature input Pt100, thermocouple K, J, T, E, L, U, N, R, S, B, W 100 to 240 VAC K3HB-HTA 100-240VAC
24 VAC/VDC K3HB-HTA 24VAC/VDC
Weighing indicator
K3HB-V
Load cell input (DC low voltage input), 0.00 to 199.99 mV, 0.000 to 19.999 mV,
100.00 mV, 199.999 mV
100 to 240 VAC K3HB-VLC 100-240 VAC
24 VAC/VDC K3HB-VLC 24VAC/VDC
Linear sensor indicator
K3HB-S
DC process input, 0 to 5 V, 1 to 5 V, -5 to 5 V, -10 to 10 V, 0 to 20 mA, 4 to 20 mA 24 VAC/VDC K3HB-SSD AC/DC24
100 to 240 VAC K3HB-SSD AC100-240
Slot Output Sensor power supply Communications Applicable indicator types Order code
B Relay PASS: SPDT 12 VDC ±10%, 80 mA – K3HB-X, -H, -S K33-CPA *1
Linear current DC0(4) - 20 mA – K3HB-X, -H, -S K33-L1 A *2
Linear voltage DC0(1) - 5 V, 0 to 10 V – K3HB-X, -H, -S K33-L2A *2
– – – K3HB-X, -H, -S K33-A *2
– – RS-232C K3HB-X, -H, -S K33-FLK1 A *2
– – RS-485 K3HB-X, -H, -S K33-FLK3A *2
Relay PASS: SPDT 10 VDC ±5%, 100 mA – K3HB-V K33-CPB *1
Linear current DC0(4) - 20 mA – K3HB-V K33-L1B *2
Linear voltage DC0(1) - 5 V, 0 to 10 V – K3HB-V K33-L2B *2
– – – K3HB-V K33-B *2
– – RS-232C K3HB-V K33-FLK1B *2
– – RS-485 K3HB-V K33-FLK3B *2
Slot Output Communications Order code
C Relay H/L: SPDT each – K34-C1
HH/H/LL/L: SPST-NO each – K34-C2
Transistor NPN open collector: HH/H/PASS/L/LL – K34-T1
PNP open collector: HH/H/PASS/L/LL – K34-T2
– – DeviceNet K34-DRT *2
Slot Input type Number of points Communications Order code
D NPN open collector 5 M3 terminal blocks K35-1
8 10-pin MIL connector K35-2
PNP open collector 5 M3 terminal blocks K35-3
8 10-pin MIL connector K35-4
Type Order code
Special cable (for event inputs with 8-pin connector) K32-DICN
K3HB-X, -H, -V, -S 1/8 DIN advanced indicators - analogue input
463
24 Digital panel indicators
Specifications
Power supply voltage 100 to 240 VAC (50/60 Hz), 24 VAC/VDC, DeviceNet power supply: 24 VDC
Allowable power supply voltage range 85 to 110% of the rated power supply voltage, DeviceNet power supply: 11 to 25 VDC
Power consumption 100 to 240 V: 18 VA max. (max. load), 24 VAC/DC: 11 VA/7 W max. (max. load)
Display method Negative LCD (backlit LED) display 7-segment digital display
(character height: PV: 14.2 mm (green/red); SV: 4.9 mm (green))
Ambient operating temperature -10 to 55°C (with no icing or condensation)
Display range -19,999 to 99,999
Weight Approx. 300 g (base unit only)
Degree of protection Front-panel Conforms to NEMA 4X for indoor use (equivalent to IP66)
Rear case IP20
Terminals IP00 + finger protection (VDE0106/100)
Memory protection EEPROM (non-volatile memory), number of rewrites: 100,000
Event input ratings Contact ON: 1 k max., OFF: 100 k min.
No-contact ON residual voltage: 2 V max., OFF leakage current: 0.1 mA max., load current: 4 mA max.
Maximum applied voltage: 30 VDC max.
Output ratings Transistor output Maximum load voltage 24 VDC
Maximum load current 50 mA
Leakage current 100 μA max.
Contact output
(resistive load)
Rated load 5 A at 250 VAC, 5 A at 30 VDC
Rated through current 5 A
Mechanical life expectancy 5,000,000 operations
Electrical life expectancy 100,000 operations
Linear output Allowable load impedance 500 max. (mA); 5 k min. (V)
Resolution Approx. 10,000
Output error ±0.5% FS
Size in mm (HxWxD) 48x96x100
464
K3HB-C, -P, -R 1/8 DIN advanced indicators - digital input
Rotary pulse, timer interval and
up/down counting pulse indicators
These indicators with analogue input feature a clear and easy-to-use colour change
display. All models are equipped with an IP66 housing. K3HB-R and -C are highspeed,
with a sample rate up to 50 kHz.
• Position meter indication for easy monitoring
• Optional DeviceNet, RS-232C, RS-485
• Double display, with 5 digits, in two colours
• 1/8 DIN size housing
Ordering information
Option boards
Sensor power supply/output boards
Relay/transistor output boards
Event input boards
*1 CPA can be combined with relay outputs only.
*2 Only one of the following can be used by each digital indicator: RS-232C/RS-485 communications, a linear output, or DeviceNet communications.
K3HB has got three slots for option boards: Slot B, slot C and slot D.
Accessories
Type of indicator Input ranges Supply voltage Input sensor Order code
Rotary pulse indicator K3HB-R No voltage contact: 30 Hz max.
Voltage pulse: 50 kHz max.
Open collector: 50 kHz max.
100 to 240 VAC NPN input/voltage pulse K3HB-RNB 100-240VAC
24 VAC/VDC K3HB-RNB 24VAC/VDC
100 to 240 VAC PNP input K3HB-RPB 100-240VAC
24 VAC/VDC K3HB-RPB 24VAC/VDC
100 to 240 VAC NPN K3HB-PNB 100-240VAC
100 to 240 VAC PNP K3HB-PPB 100-240VAC
Timer interval indicator K3HB-P 24 VAC/VDC PNP K3HB-PPB 24VAC/VDC
100 to 240 VAC NPN K3HB-CNB 100-240VAC
Up/down counting pulse indicator K3HB-C 24 VAC/VDC NPN K3HB-CNB 24VAC/VDC
24 VAC/VDC PNP K3HB-CPB 24VAC/VDC
Slot Output Sensor power supply Communications Order code
B Relay PASS: SPDT 12 VDC ±10%, 80 mA – K33-CPA *1
Linear current DC0(4) - 20 mA – K33-L1 A *2
Linear voltage DC0(1) - 5 V, 0 to 10 V – K33-L2A *2
– – – K33-A *2
– – RS-232C K33-FLK1 A *2
– – RS-485 K33-FLK3A *2
Slot Output Communications Order code
C Relay H/L: SPDT each – K34-C1
HH/H/LL/L: SPST-NO each – K34-C2
Transistor NPN open collector: HH/H/PASS/L/LL – K34-T1
PNP open collector: HH/H/PASS/L/LL – K34-T2
– DeviceNet K34-DRT *2
BCD + transistor NPN open collector: HH/H/PASS/L/LL – K34-BCD
Slot Input type Number of points Communications Order code
D NPN open collector 5 M3 terminal blocks K35-1
8 10-pin MIL connector K35-2
PNP open collector 5 M3 terminal blocks K35-3
8 10-pin MIL connector K35-4
Type Order code
Special cable (for event inputs with 8-pin connector) K32-DICN
Special BCD output cable K32-BCD
K3HB-C, -P, -R 1/8 DIN advanced indicators - digital input
465
24 Digital panel indicators
Specifications
Power supply voltage 100 to 240 VAC (50/60 Hz), 24 VAC/VDC, DeviceNet power supply: 24 VDC
Allowable power supply voltage range 85 to 110% of the rated power supply voltage, DeviceNet power supply: 11 to 25 VDC
Power consumption 100 to 240 V: 18 VA max. (max. load), 24 VAC/DC: 11 VA/7 W max. (max. load)
Display method Negative LCD (backlit LED) display 7-segment digital display
(character height: PV: 14.2 mm (green/red); SV: 4.9 mm (green))
Ambient operating temperature -10 to 55°C (with no icing or condensation)
Display range -19,999 to 99,999
Weight Approx. 300 g (base unit only)
Degree of protection Front-panel Conforms to NEMA 4X for indoor use (equivalent to IP66)
Rear case IP20
Terminals IP00 + finger protection (VDE0106/100)
Memory protection EEPROM (non-volatile memory), number of rewrites: 100,000
Event input ratings Contact ON: 1 k max., OFF: 100 k min.
No-contact ON residual voltage: 2 V max., OFF leakage current: 0.1 mA max., load current: 4 mA max.
Maximum applied voltage: 30 VDC max.
Output ratings Transistor output Maximum load voltage 24 VDC
Maximum load current 50 mA
Leakage current 100 μA max.
Contact output
(resistive load)
Rated load 5 A at 250 VAC, 5 A at 30 VDC
Rated through current 5 A
Mechanical life expectancy 5,000,000 operations
Electrical life expectancy 100,000 operations
Linear output Allowable load impedance 500 max. (mA); 5 k min. (V)
Resolution Approx. 10,000
Output error ±0.5% FS
Size in mm (HxWxD) 48x96x100
2010 Microchip Technology Inc. Preliminary DS41350E
PIC18F/LF1XK50
Data Sheet
20-Pin USB Flash Microcontrollers
with nanoWatt XLP Technology
DS41350E-page 2 Preliminary 2010 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-624-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc. Preliminary DS41350E-page 3
PIC18F/LF1XK50
Universal Serial Bus Features:
• USB V2.0 Compliant SIE
• Full Speed (12 Mb/s) and Low Speed (1.5 Mb/s)
• Supports Control, Interrupt, Isochronous and
Bulk Transfers
• Supports up to 16 Endpoints (8 bidirectional)
• 256-byte Dual Access RAM for USB
• Input-change interrupt on D+/D- for detecting
physical connection to USB host
High Performance RISC CPU:
• C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
- 256 bytes, data EEPROM
- Up to 16 Kbytes linear program memory
addressing
- Up to 768 bytes linear data memory
addressing
• Priority levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
Flexible Oscillator Structure:
• CPU divider to run the core slower than the USB
peripheral
• 16 MHz Internal Oscillator Block:
- Software selectable frequencies, 31 kHz to
16 MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User tunable to compensate for frequency
drift
• Four Crystal modes, up to 48 MHz
• External Clock modes, up to 48 MHz
• 4X Phase Lock Loop (PLL)
• Secondary oscillator using Timer1 at 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if primary or secondary
oscillator stops
• Two-speed Oscillator Start-up
Special Microcontroller Features:
• Full 5.5V Operation – PIC18F1XK50
• 1.8V-3.6V Operation – PIC18LF1XK50
• Self-programmable under Software Control
• Programmable Brown-out Reset (BOR)
- With software enable option
• Extended Watchdog Timer (WDT)
- Programmable period from 4ms to 131s
• Single-supply 3V In-Circuit Serial Programming™
(ICSP™) via two pins
Extreme Low-Power Management
PIC18LF1XK50 with nanoWatt XLP:
• Sleep mode: 24 nA
• Watchdog Timer: 450 nA
• Timer1 Oscillator: 790 nA @ 32 kHz
Analog Features:
• Analog-to-Digital Converter (ADC) module:
- 10-bit resolution, 9 external channels
- Auto acquisition capability
- Conversion available during Sleep
- Internal 1.024V Fixed Voltage Reference
(FVR) channel
- Independent input multiplexing
• Dual Analog Comparators
- Rail-to-rail operation
- Independent input multiplexing
• Voltage Reference module:
- Programmable (% of VDD), 16 steps
- Two 16-level voltage ranges using VREF pins
- Programmable Fixed Voltage Reference
(FVR), 3 levels
• On-chip 3.2V LDO Regulator – (PIC18F1XK50)
Peripheral Highlights:
• 14 I/O Pins plus 1 Input-only pin:
- High-current sink/source 25 mA/25 mA
- 7 Programmable weak pull-ups
- 7 Programmable Interrupt-on-change pins
- 3 programmable external interrupts
- Programmable slew rate
• Enhanced Capture/Compare/PWM (ECCP)
module:
- One, two, three, or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and Auto-restart
• Master Synchronous Serial Port (MSSP) module:
- 3-wire SPI (supports all 4 modes)
- I2C™ Master and Slave modes (Slave mode
address masking)
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:
- Supports RS-485, RS-232 and LIN 2.0
- RS-232 operation using internal oscillator
- Auto-Baud Detect
- Auto-Wake-up on Break
• SR Latch mode
20-Pin USB Flash Microcontrollers with nanoWatt XLP Technology
PIC18F/LF1XK50
DS41350E-page 4 Preliminary 2010 Microchip Technology Inc.
-
Pin Diagrams
Pin Diagrams
Device
Program Memory Data Memory
I/O(1)
10-bit
A/D
(ch)(2)
ECCP
(PWM)
MSSP
EUSART
Comp. Timers
Flash 8/16-bit USB
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes) SPI Master
I2C™
PIC18F13K50/
PIC18LF13K50
8K 4096 512(3) 256 15 11 1 Y Y 1 2 1/3 Y
PIC18F14K50/
PIC18LF14K50
16K 8192 768(3) 256 15 11 1 Y Y 1 2 1/3 Y
Note 1: One pin is input only.
2: Channel count includes internal Fixed Voltage Reference (FVR) and Programmable Voltage Reference (CVREF) channels.
3: Includes the dual port RAM used by the USB module which is shared with the data memory.
20-pin PDIP, SSOP, SOIC (300 MIL)
10
2
345
6
1
8
7
9
11
12
13
14
15
16
19
20
18
17
VDD
RA5/IOCA5/OSC1/CLKIN
RA4/AN3/IOCA3/OSC2/CLKOUT
RA3/IOCA3/MCLR/VPP
RC5/CCP1/P1A/T0CKI
RC4/P1B/C12OUT/SRQ
RC3/AN7/P1C/C12IN3-/PGM
RC6/AN8/SS/T13CKI/T1OSCI
RC7/AN9/SDO/T1OSCO
RB7/IOCB7/TX/CK
VSS
RA0/IOCA0/D+/PGD
RA1/IOCA1/D-/PGC
VUSB
RC0/AN4/C12IN+/INT0/VREF+
RC1/AN5/C12IN1-/INT1/VREFRC2/
AN6/P1D/C12IN2-/CVREF/INT2
RB4/AN10/IOCB4/SDI/SDA
RB5/AN11/IOCB5/RX/DT
RB6/IOCB6/SCK/SCL
PIC18F/LF1XK50
20-pin QFN (5x5)
8 9
23
1
14
15
16
10
11
6
12
13
20 19 18 17
7
5
4
PIC18F1XK50/
PIC18LF1XK50
RA3/MCLR/VPP
RC5/CCP1/P1A/T0CKI
RC4/P1B/C12OUT/SRQ
RC3/AN7/P1C/C12IN3-/PGM
RC6/AN8/SS/T13CKI/T1OSCI
RC7/AN9/SDO/T1OSCO
RB7/TX/CK
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
RC2/AN6/P1D/C12IN2-/CVREF/INT2
RC1/AN1/C12IN1-/INT1/VREFRC0/
AN4/C12IN+/INT0/VREF+
VUSB
RA1/D-/PGC
RA0/D+/PGD
Vss
VDD
RA4/AN3/OSC2/CLKO
RA5/OSC1/CLKI
2010 Microchip Technology Inc. Preliminary DS41350E-page 5
PIC18F/LF1XK50
TABLE 1: PIC18F/LF1XK50 PIN SUMMARY
Pin
I/O
Analog
Comparator
Reference
ECCP
EUSART
MSSP
Timers
Interrupts
Pull-up
USB
Basic
19 RA0 IOCA0 D+ PGD
18 RA1 IOCA1 D- PGC
4 RA3(1) IOCA3 Y MCLR/VPP
3 RA4 AN3 IOCA4 Y OSC2/CLKOUT
2 RA5 IOCA5 Y OSC1/CLKIN
13 RB4 AN10 SDI/SDA IOCB4 Y
12 RB5 AN11 RX/DT IOCB5 Y
11 RB6 SCL/SCK IOCB6 Y
10 RB7 TX/CK IOCB7 Y
16 RC0 AN4 C12IN+ VREF+ INT0
15 RC1 AN5 C12IN1- VREF- INT1
14 RC2 AN6 C12IN2- CVREF P1D INT2
7 RC3 AN7 C12IN3- P1C PGM
6 RC4 C12OUT P1B SRQ
5 RC5 CCP1/P1A T0CKI
8 RC6 AN8 SS T13CKI/T1OSCI
9 RC7 AN9 SDO T1OSCO
17 VUSB
1 VDD
20 VSS
Note 1: Input only.
PIC18F/LF1XK50
DS41350E-page 6 Preliminary 2010 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 15
3.0 Memory Organization ................................................................................................................................................................. 29
4.0 Flash Program Memory.............................................................................................................................................................. 51
5.0 Data EEPROM Memory ............................................................................................................................................................. 61
6.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 65
7.0 Interrupts .................................................................................................................................................................................... 67
8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 81
9.0 I/O Ports ..................................................................................................................................................................................... 83
10.0 Timer0 Module ......................................................................................................................................................................... 101
11.0 Timer1 Module ......................................................................................................................................................................... 105
12.0 Timer2 Module ......................................................................................................................................................................... 111
13.0 Timer3 Module ......................................................................................................................................................................... 113
14.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 117
15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 139
16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 181
17.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 209
18.0 Comparator Module.................................................................................................................................................................. 223
19.0 Power-Managed Modes ........................................................................................................................................................... 235
20.0 SR Latch................................................................................................................................................................................... 241
21.0 Voltage References.................................................................................................................................................................. 245
22.0 Universal Serial Bus (USB) ...................................................................................................................................................... 251
23.0 Reset ........................................................................................................................................................................................ 277
24.0 Special Features of the CPU.................................................................................................................................................... 291
25.0 Instruction Set Summary .......................................................................................................................................................... 309
26.0 Development Support............................................................................................................................................................... 359
27.0 Electrical Specifications............................................................................................................................................................ 363
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 397
29.0 Packaging Information.............................................................................................................................................................. 399
Appendix A: Revision History............................................................................................................................................................. 405
Appendix B: Device Differences......................................................................................................................................................... 406
Index .................................................................................................................................................................................................. 407
The Microchip Web Site ..................................................................................................................................................................... 417
Customer Change Notification Service .............................................................................................................................................. 417
Customer Support .............................................................................................................................................................................. 417
Reader Response .............................................................................................................................................................................. 418
Product Identification System............................................................................................................................................................. 419
2010 Microchip Technology Inc. Preliminary DS41350E-page 7
PIC18F/LF1XK50
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
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Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
PIC18F/LF1XK50
DS41350E-page 8 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 9
PIC18F1XK50/PIC18LF1XK50
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these features, the PIC18F/LF1XK50 family introduces
design enhancements that make these
microcontrollers a logical choice for many highperformance,
power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt XLP TECHNOLOGY
All of the devices in the PIC18F/LF1XK50 family incorporate
a range of features that can significantly reduce
power consumption during operation. Key items
include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The powermanaged
modes are invoked by user code during
operation, allowing the user to incorporate powersaving
ideas into their application’s software
design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 27.0 “Electrical Specifications”
for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F/LF1XK50 family offer
ten different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
• Four Crystal modes, using crystals or ceramic
resonators
• External Clock modes, offering the option of using
two pins (oscillator input and a divide-by-4 clock
output) or one pin (oscillator input, with the second
pin reassigned as general I/O)
• External RC Oscillator modes with the same pin
options as the External Clock modes
• An internal oscillator block which contains a
16 MHz HFINTOSC oscillator and a 31 kHz
LFINTOSC oscillator which together provide 8
user selectable clock frequencies, from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the high-speed crystal and internal
oscillator modes, which allows clock speeds of
up to 48 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 32 MHz – all without using
an external crystal or clock circuit.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the LFINTOSC. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F13K50 • PIC18F14K50
• PIC18LF13K50 • PIC18LF14K50
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 10 Preliminary 2010 Microchip Technology Inc.
1.2 Other Special Features
• Memory Endurance: The Flash cells for both
program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up to
1K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively
estimated to be greater than 40 years.
• Self-programmability: These devices can write
to their own program memory spaces under
internal software control. Using a bootloader
routine located in the code protected Boot Block,
it is possible to create an application that can
update itself in the field.
• Extended Instruction Set: The PIC18F/
LF1XK50 family introduces an optional extension
to the PIC18 instruction set, which adds 8 new
instructions and an Indexed Addressing mode.
This extension has been specifically designed to
optimize re-entrant application code originally
developed in high-level languages, such as C.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include:
- Auto-Shutdown, for disabling PWM outputs
on interrupt or other select conditions
- Auto-Restart, to reactivate outputs once the
condition has cleared
- Output steering to selectively enable one or
more of 4 outputs to provide the PWM signal.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution.
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit
postscaler, allowing an extended time-out range
that is stable across operating voltage and
temperature. See Section 27.0 “Electrical
Specifications” for time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F/LF1XK50 family are available in
20-pin packages. Block diagrams for the two groups
are shown in Figure 1-1.
The devices are differentiated from each other in the
following ways:
1. Flash program memory:
• 8 Kbytes for PIC18F13K50/PIC18LF13K50
• 16 Kbytes for PIC18F14K50/PIC18LF14K50
2. On-chip 3.2V LDO regulator for PIC18F13K50
and PIC18F14K50.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1 and I/O
description are in Table 1-2.
2010 Microchip Technology Inc. Preliminary DS41350E-page 11
PIC18F1XK50/PIC18LF1XK50
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F/LF1XK50 (20-PIN DEVICES)
Features PIC18F13K50 PIC18LF13K50 PIC18F14K50 PIC18LF14K50
LDO Regulator Yes No Yes No
Program Memory (Bytes) 8K 16K
Program Memory (Instructions) 4096 8192
Data Memory (Bytes) 512 768
Operating Frequency DC – 48 MHz
Interrupt Sources 30
I/O Ports Ports A, B, C
Timers 4
Enhanced Capture/ Compare/PWM Modules 1
Serial Communications MSSP, Enhanced USART, USB
10-Bit Analog-to-Digital Module 9 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 20-Pin PDIP, SSOP, SOIC (300 mil) and QFN (5x5)
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 12 Preliminary 2010 Microchip Technology Inc.
FIGURE 1-1: PIC18F/LF1XK50 BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA1
RA0
Data Latch
Data Memory
Address Latch
Data Address<12>
12
BSR FSR0 Access
FSR1
FSR2
inc/dec
logic
Address
4 12 4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
8
BITOP
8 8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
Note 1: RA3 is only available when MCLR functionality is disabled.
2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used
as digital I/O. Refer to Section 2.0 “Oscillator Module” for additional information.
3: PIC18F13K50/PIC18F14K50 only.
Comparator MSSP EUSART 10-bit
ADC
Timer0 Timer1 Timer2 Timer3
ECCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
VSS Band Gap
MCLR(1)
Block
LFINTOSC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
T1OSO
T1OSI
FVR
FVR FVR
CVREF
Address Latch
Program Memory
Data Latch
CVREF
RA3
RA4
RA5
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
(512/768 bytes)
VUSB USB
Module
USB
LDO(3)
Regulator
2010 Microchip Technology Inc. Preliminary DS41350E-page 13
PIC18F1XK50/PIC18LF1XK50
TABLE 1-2: PIC18F/LF1XK50 PINOUT I/O DESCRIPTIONS
Pin Name Pin
Number
Pin
Type
Buffer
Type Description
RA0/D+/PGD
RA0
D+
PGD
19
I
I/O
I/O
TTL
XCVR
ST
Digital input
USB differential plus line (input/output)
ICSP™ programming data pin
RA1/D-/PGC
RA1
DPGC
18
I
I/O
I/O
TTL
XCVR
ST
Digital input
USB differential minus line (input/output)
ICSP™ programming clock pin
RA3/MCLR/VPP
RA3
MCLR
VPP
4
IIP
ST
ST
—
Master Clear (input) or programming voltage (input)
Digital input
Active-low Master Clear with internal pull-up
High voltage programming input
RA4/AN3/OSC2/CLKOUT
RA4
AN3
OSC2
CLKOUT
3
I/O
IO
O
TTL
Analog
XTAL
CMOS
Digital I/O
ADC channel 3
Oscillator crystal output. Connect to crystal or resonator
in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
RA5/OSC1/CLKIN
RA5
OSC1
CLKIN
2
I/O
I
I
TTL
XTAL
CMOS
Digital I/O
Oscillator crystal input or external clock input
ST buffer when configured in RC mode; analog other
wise
External clock source input. Always associated with the
pin function OSC1 (See related OSC1/CLKIN, OSC2,
CLKOUT pins
RB4/AN10/SDI/SDA
RB4
AN10
SDI
SDA
13
I/O
II
I/O
TTL
Analog
ST
ST
Digital I/O
ADC channel 10
SPI data in
I2C™ data I/O
RB5/AN11/RX/DT
RB5
AN11
RX
DT
12
I/O
II I/O
TLL
Analog
ST
ST
Digital I/O
ADC channel 11
EUSART asynchronous receive
EUSART synchronous data (see related RX/TX)
RB6/SCK/SCI
RB6
SCK
SCI
11
I/O
I/O
I/O
TLL
ST
ST
Digital I/O
Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I2C™ mode
RB7/TX/CK
RB7
TX
CK
10
I/O
O
I/O
TLL
CMOS
ST
Digital I/O
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input I = Input
O = Output P = Power
XTAL= Crystal Oscillator XCVR = USB Differential Transceiver
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 14 Preliminary 2010 Microchip Technology Inc.
RC0/AN4/C12IN+/INT0/VREF+
RC0
AN4
C12IN+
INT0
VREF+
16
I/O
IIII
ST
Analog
Analog
ST
Analog
Digital I/O
ADC channel 4
Comparator C1 and C2 non-inverting input
External interrupt 0
Comparator reference voltage (high) input
RC1/AN5/C12IN-/INT1/VREFRC1
AN5
C12ININT1
VREF-
15
I/O
IIII
ST
Analog
Analog
ST
Analog
Digital I/O
ADC channel 5
Comparator C1 and C2 non-inverting input
External interrupt 0
Comparator reference voltage (low) input
RC2/AN6/P1D/C12IN2-/CVREF/INT2
RC2
AN6
P1D
C12IN2-
CVREF
INT2
14
I/O
IOIOI
ST
Analog
CMOS
Analog
Analog
ST
Digital I/O
ADC channel 6
Enhanced CCP1 PWM output
Comparator C1 and C2 inverting input
Comparator reference voltage output
External interrupt 0
RC3/AN7/P1C/C12IN3-/PGM
RC3
AN7
P1C
C12IN3-
PGM
7
I/O
IOI
I/O
ST
Analog
CMOS
Analog
ST
Digital I/O
ADC channel 7
Enhanced CCP1 PWM output
Comparator C1 and C2 inverting input
Low-Voltage ICSP Programming enable pin
RC4/P1B/C12OUT/SRQ
RC4
P1B
C12OUT
SRQ
6
I/O
OOO
ST
CMOS
CMOS
CMOS
Digital I/O
Enhanced CCP1 PWM output
Comparator C1 and C2 output
SR Latch output
RC5/CCP1/P1A/T0CKI
RC5
CCP1
P1A
T0CKI
5
I/O
I/O
OI
ST
ST
CMOS
ST
Digital I/O
Capture 1 input/Compare 1 output/PWM 1 output
Enhanced CCP1 PWM output
Timer0 external clock input
RC6/AN8/SS/T13CKI/T1OSCI
RC6
AN8
SS
T13CKI
T1OSCI
8
I/O
IIII
ST
Analog
TTL
ST
XTAL
Digital I/O
ADC channel 8
SPI slave select input
Timer0 and Timer3 external clock input
Timer1 oscillator input
RC7/AN9/SDO/T1OSCO
RC7
AN9
SDO
T1OSCO
9
I/O
IOO
ST
Analog
CMOS
XTAL
Digital I/O
ADC channel 9
SPI data out
Timer1 oscillator output
VSS 20 P — Ground reference for logic and I/O pins
VDD 1 P — Positive supply for logic and I/O pins
VUSB 17 P — Positive supply for USB transceiver
TABLE 1-2: PIC18F/LF1XK50 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Number
Pin
Type
Buffer
Type Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input I = Input
O = Output P = Power
XTAL= Crystal Oscillator XCVR = USB Differential Transceiver
2010 Microchip Technology Inc. Preliminary DS41350E-page 15
PIC18F/LF1XK50
2.0 OSCILLATOR MODULE
2.1 Overview
The oscillator module has a variety of clock sources
and features that allow it to be used in a wide range of
applications, maximizing performance and minimizing
power consumption. Figure 2-1 illustrates a block
diagram of the oscillator module.
Key features of the oscillator module include:
• System Clock Selection
- Primary External Oscillator
- Secondary External Oscillator
- Internal Oscillator
• Oscillator Start-up Timer
• System Clock Selection
• Clock Switching
• 4x Phase Lock Loop Frequency Multiplier
• CPU Clock Divider
• USB Operation
- Low Speed
- Full Speed
• Two-Speed Start-up Mode
• Fail-Safe Clock Monitoring
2.2 System Clock Selection
The SCS bits of the OSCCON register select between
the following clock sources:
• Primary External Oscillator
• Secondary External Oscillator
• Internal Oscillator
TABLE 2-1: SYSTEM CLOCK SELECTION
The default state of the SCS bits sets the system clock
to be the oscillator defined by the FOSC bits of the
CONFIG1H Configuration register. The system clock
will always be defined by the FOSC bits until the SCS
bits are modified in software.
When the Internal Oscillator is selected as the system
clock, the IRCF bits of the OSCCON register and the
INTSRC bit of the OSCTUNE register will select either
the LFINTOSC or the HFINTOSC. The LFINTOSC is
selected when the IRCF<2:0> = 000 and the INTSRC
bit is clear. All other combinations of the IRCF bits and
the INTSRC bit will select the HFINTOSC as the
system clock.
2.3 Primary External Oscillator
The Primary External Oscillator’s mode of operation is
selected by setting the FOSC<3:0> bits of the
CONFIG1H Configuration register. The oscillator can
be set to the following modes:
• LP: Low-Power Crystal
• XT: Crystal/Ceramic Resonator
• HS: High-Speed Crystal Resonator
• RC: External RC Oscillator
• EC: External Clock
Additionally, the Primary External Oscillator may be
shut-down under firmware control to save power.
Note: The frequency of the system clock will be
referred to as FOSC throughout this
document.
Configuration Selection
SCS <1:0> System Clock
1x Internal Oscillator
01 Secondary External Oscillator
00
(Default after Reset)
Oscillator defined by
FOSC<3:0>
PIC18F/LF1XK50
DS41350E-page 16 Preliminary 2010 Microchip Technology Inc.
FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
4 x PLL
FOSC<3:0>
OSC2
OSC1
Sleep
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
250 kHz
500 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000 31 kHz
31 kHz
LFINTOSC
Internal
Oscillator
Block
Clock
HFINTOSC Control SCS<1:0>
16 MHz
0
1
INTSRC
Primary
PIC18F/LF1XK50
Sleep
Sleep
System
Secondary
T1OSCEN
Enable
Oscillator
T1OSI
T1OSO
PCLKEN
PRI_SD
2
CPU
Divider 0
1
1
0
USBDIV
FOSC<3:0>
Low Speed USB
High Speed USB
PLLEN
SPLLEN
Oscillator
Watchdog
Timer
Oscillator
Fail-Safe
Clock
Two-Speed
Start-up
Clock
00
1x
01
2010 Microchip Technology Inc. Preliminary DS41350E-page 17
PIC18F/LF1XK50
2.3.1 PRIMARY EXTERNAL OSCILLATOR
SHUT-DOWN
The Primary External Oscillator can be enabled or disabled
via software. To enable software control of the
Primary External Oscillator, the PCLKEN bit of the
CONFIG1H Configuration register must be set. With
the PCLKEN bit set, the Primary External Oscillator is
controlled by the PRI_SD bit of the OSCCON2 register.
The Primary External Oscillator will be enabled when
the PRI_SD bit is set, and disabled when the PRI_SD
bit is clear.
2.3.2 LP, XT AND HS OSCILLATOR
MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 2-2). The mode selects a low,
medium or high gain setting of the internal inverteramplifier
to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is best suited
to drive resonators with a low drive level specification, for
example, tuning fork type crystals.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 2-2 and Figure 2-3 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 2-2: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
Note: The Primary External Oscillator cannot be
shut down when it is selected as the
System Clock. To shut down the oscillator,
the system clock source must be either
the Secondary Oscillator or the Internal
Oscillator.
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
PIC18F/LF1XK50
DS41350E-page 18 Preliminary 2010 Microchip Technology Inc.
FIGURE 2-3: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
2.3.3 EXTERNAL RC
The External Resistor-Capacitor (RC) mode supports
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. In RC mode, the RC circuit connects to OSC1,
allowing OSC2 to be configured as an IO or as
CLKOUT. The CLKOUT function is selected by the
FOSC bits of the CONFIG1H Configuration register.
When OSC2 is configured as CLKOUT, the frequency
at the pin is the frequency of the RC oscillator divided by
4. Figure 2-4 shows the external RC mode connections.
FIGURE 2-4: EXTERNAL RC MODES
The RC oscillator frequency is a function of the supply
voltage, the resistor REXT, the capacitor CEXT and the
operating temperature. Other factors affecting the
oscillator frequency are:
• Input threshold voltage variation
• Component tolerances
• Variation in capacitance due to packaging
2.3.4 EXTERNAL CLOCK
The External Clock (EC) mode allows an externally
generated logic level clock to be used as the system’s
clock source. When operating in this mode, the
external clock source is connected to the OSC1
allowing OSC2 to be configured as an I/O or as
CLKOUT. The CLKOUT function is selected by the
FOSC bits of the CONFIG1H Configuration register.
When OSC2 is configured as CLKOUT, the frequency
at the pin is the frequency of the EC oscillator divided
by 4.
Three different power settings are available for EC
mode. The power settings allow for a reduced IDD of the
device, if the EC clock is known to be in a specific
range. If there is an expected range of frequencies for
the EC clock, select the power mode for the highest
frequency.
EC Low power 0 – 250 kHz
EC Medium power 250 kHz – 4 MHz
EC High power 4 – 48 MHz
2.4 Secondary External Oscillator
The Secondary External Oscillator is designed to drive
an external 32.768 kHz crystal. This oscillator is
enabled or disabled by the T1OSCEN bit of the T1CON
register. See Section 11.0 “Timer1 Module” for more
information.
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator
OSC2/CLKOUT
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 or
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k
CEXT > 20 pF
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO clock mode.
I/O(2)
2010 Microchip Technology Inc. Preliminary DS41350E-page 19
PIC18F/LF1XK50
2.5 Internal Oscillator
The internal oscillator module contains two independent
oscillators which are:
• LFINTOSC: Low-Frequency Internal Oscillator
• HFINTOSC: High-Frequency Internal Oscillator
When operating with either oscillator, OSC1 will be an
I/O and OSC2 will be either an I/O or CLKOUT. The
CLKOUT function is selected by the FOSC bits of the
CONFIG1H Configuration register. When OSC2 is
configured as CLKOUT, the frequency at the pin is the
frequency of the Internal Oscillator divided by 4.
2.5.1 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a 31 kHz internal clock source. The LFINTOSC
oscillator is the clock source for:
• Power-up Timer
• Watchdog Timer
• Fail-Safe Clock Monitor
The LFINTOSC is enabled when any of the following
conditions are true:
• Power-up Timer is enabled (PWRTEN = 0)
• Watchdog Timer is enabled (WDTEN = 1)
• Watchdog Timer is enabled by software
(WDTEN = 0 and SWDTEN = 1)
• Fail-Safe Clock Monitor is enabled (FCMEM = 1)
• SCS1=1 and IRCF<2:0> = 000 and INTSRC = 0
• FOSC<3:0> selects the internal oscillator as the
primary clock and IRCF<2:0> = 000 and
INTSRC = 0
• IESO = 1 (Two-Speed Start-up) and
IRCF<2:0> = 000 and INTSRC = 0
2.5.2 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a precision oscillator that is factory-calibrated to
operate at 16 MHz. The output of the HFINTOSC
connects to a postscaler and a multiplexer (see
Figure 2-1). One of eight frequencies can be selected
using the IRCF<2:0> bits of the OSCCON register. The
following frequencies are available from the
HFINTOSC:
• 16 MHZ
• 8 MHZ
• 4 MHZ
• 2 MHZ
• 1 MHZ (Default after Reset)
• 500 kHz
• 250 kHz
• 31 kHz
The HFIOFS bit of the OSCCON register indicates
whether the HFINTOSC is stable.
The HFINTOSC is enabled if any of the following
conditions are true:
• SCS1 = 1 and IRCF<2:0> 000
• SCS1 = 1 and IRCF<2:0> = 000 and INTSRC = 1
• FOSC<3:0> selects the internal oscillator as the
primary clock and
- IRCF<2:0> 000 or
- IRCF<2:0> = 000 and INTSRC = 1
• IESO = 1 (Two-Speed Start-up) and
- IRCF<2:0> 000 or
- IRCF<2:0> = 000 and INTSRC = 1
• FCMEM=1 (Fail Safe Clock Monitoring) and
- IRCF<2:0> 000 or
- IRCF<2:0> = 000 and INTSRC = 1
Note 1: Selecting 31 kHz from the HFINTOSC
oscillator requires IRCF<2:0> = 000 and
the INTSRC bit of the OSCTUNE register
to be set. If the INTSRC bit is clear, the
system clock will come from the
LFINTOSC.
2: Additional adjustments to the frequency
of the HFINTOSC can made via the
OSCTUNE registers. See Register 2-3
for more details
PIC18F/LF1XK50
DS41350E-page 20 Preliminary 2010 Microchip Technology Inc.
2.6 Oscillator Control
The Oscillator Control (OSCCON) (Register 2-1) and the
Oscillator Control 2 (OSCCON2) (Register 2-2) registers
control the system clock and frequency selection
options.
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS(1) HFIOFS SCS1 SCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 16 MHz
110 = 8 MHz
101 = 4 MHz
100 = 2 MHz
011 = 1 MHz(3)
010 = 500 kHz
001 = 250 kHz
000 = 31 kHz(2)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2 HFIOFS: HFINTOSC Frequency Stable bit
1 = HFINTOSC frequency is stable
0 = HFINTOSC frequency is not stable
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary (Timer1) oscillator
00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]).
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Source selected by the INTSRC bit of the OSCTUNE register, see text.
3: Default output frequency of HFINTOSC on Reset.
2010 Microchip Technology Inc. Preliminary DS41350E-page 21
PIC18F/LF1XK50
REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-x
— — — — — PRI_SD HFIOFL LFIOFS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 PRI_SD: Primary Oscillator Drive Circuit shutdown bit
1 = Oscillator drive circuit on
0 = Oscillator drive circuit off (zero power)
bit 1 HFIOFL: HFINTOSC Frequency Locked bit
1 = HFINTOSC is in lock
0 = HFINTOSC has not yet locked
bit 0 LFIOFS: LFINTOSC Frequency Stable bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
PIC18F/LF1XK50
DS41350E-page 22 Preliminary 2010 Microchip Technology Inc.
2.6.1 OSCTUNE REGISTER
The HFINTOSC is factory calibrated, but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-3).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift,
while giving no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
The operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor
(FSCM) and peripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and SPLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.5.1 “LFINTOSC”.
The SPLLEN bit controls the operation of the frequency
multiplier. For more details about the function of the
SPLLEN bit see Section 2.9 “4x Phase Lock Loop
Frequency Multiplier”
REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator
bit 6 SPLLEN: Software Controlled Frequency Multiplier PLL bit
1 = PLL enabled (for HFINTOSC 8 MHz only)
0 = PLL disabled
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
• • •
000001 =
000000 = Oscillator module is running at the factory calibrated frequency.
111111 =
• • •
100000 = Minimum frequency
2010 Microchip Technology Inc. Preliminary DS41350E-page 23
PIC18F/LF1XK50
2.7 Oscillator Start-up Timer
The Primary External Oscillator, when configured for
LP, XT or HS modes, incorporates an Oscillator Start-up
Timer (OST). The OST ensures that the oscillator starts
and provides a stable clock to the oscillator module.
The OST times out when 1024 oscillations on OSC1
have occurred. During the OST period, with the system
clock set to the Primary External Oscillator, the program
counter does not increment suspending program
execution. The OST period will occur following:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Wake-up from Sleep
• Oscillator being enabled
• Expiration of Power-up Timer (PWRT)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Start-up
mode can be selected. See Section 2.12 “Two-Speed
Start-up Mode” for more information.
2.8 Clock Switching
The device contains circuitry to prevent clock “glitches”
due to a change of the system clock source. To
accomplish this, a short pause in the system clock
occurs during the clock switch. If the new clock source
is not stable (e.g., OST is active), the device will
continue to execute from the old clock source until the
new clock source becomes stable. The timing of a
clock switch is as follows:
1. SCS<1:0> bits of the OSCCON register are
modified.
2. The system clock will continue to operate from
the old clock until the new clock is ready.
3. Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
is ready.
4. The system clock is held low, starting at the next
falling edge of the old clock.
5. Clock switch circuitry waits for an additional two
rising edges of the new clock.
6. On the next falling edge of the new clock, the
low hold on the system clock is release and the
new clock is switched in as the system clock.
7. Clock switch is complete.
Refer to Figure 2-5 for more details.
FIGURE 2-5: CLOCK SWITCH TIMING
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time(1) Clock Sync Running
High Speed Low Speed
Select Old Select New
New Clk Ready
Low Speed High Speed
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time(1) Clock Sync Running
Select Old Select New
New Clk Ready
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
PIC18F/LF1XK50
DS41350E-page 24 Preliminary 2010 Microchip Technology Inc.
TABLE 2-2: EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING
2.9 4x Phase Lock Loop Frequency
Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower-frequency
external oscillator or to operate at 32 MHz with the
HFINTOSC. The PLL is designed for an input
frequency from 4 MHz to 12 MHz. The PLL multiplies
its input frequency by a factor of four when the PLL is
enabled. This may be useful for customers who are
concerned with EMI, due to high-frequency crystals.
Two bits control the PLL: the PLLEN bit of the
CONFIG1H Configuration register and the SPLLEN bit
of the OSCTUNE register. The PLL is enabled when
the PLLEN bit is set and it is under software control
when the PLLEN bit is cleared.
TABLE 2-3: PLL CONFIGURATION
2.9.1 32 MHZ INTERNAL OSCILLATOR
FREQUENCY SELECTION
The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz internal
clock source:
• The FOSC bits in CONFIG1H must be set to use
the INTOSC source as the device system clock
(FOSC<3:0> = 1000 or 1001).
• The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<3:0> in CONFIG1H (SCS<1:0> = 00).
• The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
(IRCF<2:0> = 110).
• The SPLLEN bit in the OSCTUNE register must
be set to enable the 4xPLL, or the PLLEN bit of
CONFIG1H must be progr mmed to a ‘1’.
The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.
2.10 CPU Clock Divider
The CPU Clock Divider allows the system clock to run
at a slower speed than the Low/Full Speed USB
module clock while sharing the same clock source.
Only the oscillator defined by the settings of the FOSC
bits of the CONFIG1H Configuration register may be
used with the CPU Clock Divider. The CPU Clock
Divider is controlled by the CPUDIV bits of the
CONFIG1L Configuration register. Setting the CPUDIV
bits will set the system clock to:
• Equal the clock speed of the USB module
• Half the clock speed of the USB module
• One third the clock speed of the USB module
• One fourth the clock speed of the USB module
For more information on the CPU Clock Divider, see
Figure 2-1 and Register 24-1 CONFIG1L.
Switch From Switch To Oscillator Delay
Sleep/POR LFINTOSC
HFINTOSC
Oscillator Warm-up Delay (TWARM)
Sleep/POR LP, XT, HS 1024 clock cycles
Sleep/POR EC, RC 8 clock cycles
PLLEN SPLLEN PLL Status
1 x PLL enabled
0 1 PLL enabled
0 0 PLL disabled
Note: When using the PLLEN bit of CONFIG1H,
the 4xPLL cannot be disabled by software
and the 8 MHz HFINTOSC option will no
longer be available.
2010 Microchip Technology Inc. Preliminary DS41350E-page 25
PIC18F/LF1XK50
2.11 USB Operation
The USB module is designed to operate in two different
modes:
• Low Speed
• Full Speed
Because of timing requirements imposed by the USB
specifications, the Primary External Oscillator is
required for the USB module. The FOSC bits of the
CONFIG1H Configuration register must be set to either
External Clock (EC) High-power or HS mode with a
clock frequency of 6, 12 or 48 MHz.
2.11.1 LOW SPEED OPERATION
For Low Speed USB operation, a 6 MHz clock is
required for the USB module. To generate the 6 MHz
clock, only 2 Oscillator modes are allowed:
• EC High-power mode
• HS mode
Table 2-4 shows the recommended Clock mode for
low-speed operation.
2.11.2 FULL-SPEED OPERATION
For full-speed USB operation, a 48 MHz clock is
required for the USB module. To generate the 48 MHz
clock, only 2 Oscillator modes are allowed:
• EC High-power mode
• HS mode
Table 2-5 shows the recommended Clock mode for fullspeed
operation.
Note: Users must run USB low speed operation
using a CPU clock frequency of 24 MHz or
slower (64 MHz is optimal). If anything
higher than 24 MHz is used, a firmware
delay of at least 14 instruction cycles is
required.
PIC18F/LF1XK50
DS41350E-page 26 Preliminary 2010 Microchip Technology Inc.
TABLE 2-4: LOW SPEED USB CLOCK SETTINGS
TABLE 2-5: FULL-SPEED USB CLOCK SETTINGS
Clock Mode Clock
Frequency USBDIV 4x PLL
Enabled CPUDIV<1:0> System Clock
Frequency (MHz)
EC High/HS
12 MHz 1
Yes
00 48
01 24
10 16
11 12
No
00 12
01 6
10 4
11 3
6 MHz 0
Yes
00 24
01 12
10 8
11 6
No
00 6
01 3
10 2
11 1.5
Note: The system clock frequency in Table 2-4
only applies if the OSCCON register bits
SCS<1:0> = 00. By changing these bits,
the system clock can operate down to
31 kHz.
Clock Mode Clock Frequency 4x PLL Enabled CPUDIV<1:0> System Clock Frequency
(MHz)
EC High 48 MHz No
00 48
01 24
10 16
11 12
EC High/HS 12 MHz Yes
00 48
01 24
10 16
11 12
Note: The system clock frequency in the above
table only applies if the OSCCON register
bits SCS<1:0> = 00. By changing these
bits, the system clock can operate down to
31 kHz.
2010 Microchip Technology Inc. Preliminary DS41350E-page 27
PIC18F/LF1XK50
2.12 Two-Speed Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
Oscillator Start-up Timer (OST) and code execution. In
applications that make heavy use of the Sleep mode,
Two-Speed Start-up will remove the OST period, which
can reduce the overall power consumption of the
device.
Two-Speed Start-up mode is enabled by setting the
IESO bit of the CONFIG1H Configuration register. With
Two-Speed Start-up enabled, the device will execute
instructions using the internal oscillator during the
Primary External Oscillator OST period.
When the system clock is set to the Primary External
Oscillator and the oscillator is configured for LP, XT or
HS modes, the device will not execute code during the
OST period. The OST will suspend program execution
until 1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator while the OST is
active. The system clock will switch back to the Primary
External Oscillator after the OST period has expired.
Two-speed Start-up will become active after:
• Power-on Reset (POR)
• Power-up Timer (PWRT), if enabled
• Wake-up from Sleep
The OSTS bit of the OSCCON register reports which
oscillator the device is currently using for operation.
The device is running from the oscillator defined by the
FOSC bits of the CONFIG1H Configuration register
when the OSTS bit is set. The device is running from
the internal oscillator when the OSTS bit is clear.
2.13 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC and RC).
FIGURE 2-6: FSCM BLOCK DIAGRAM
2.13.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 2-6. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire halfcycle
of the sample clock elapses before the primary
clock goes low.
2.13.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
PIC18F/LF1XK50
DS41350E-page 28 Preliminary 2010 Microchip Technology Inc.
2.13.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared by either one of the
following:
• Any Reset
• By toggling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external clock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
2.13.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
FIGURE 2-7: FSCM TIMING DIAGRAM
TABLE 2-6: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
CONFIG1H IESO FCMEN PCLKEN PLLEN FOSC3 FOSC2 FOSC1 FOSC0 296
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 286
OSCTUNE INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 105
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test Test Test
Clock Monitor Output
2010 Microchip Technology Inc. Preliminary DS41350E-page 29
PIC18F1XK50/PIC18LF1XK50
3.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for concurrent
access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 4.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 5.0 “Data EEPROM
Memory”.
3.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
This family of devices contain the following:
• PIC18F13K50: 8 Kbytes of Flash Memory, up to
4,096 single-word instructions
• PIC18F14K50: 16 Kbytes of Flash Memory, up to
8,192 single-word instructions
PIC18 devices have two interrupt vectors and one
Reset vector. The Reset vector address is at 0000h
and the interrupt vector addresses are at 0008h and
0018h.
The program memory map for PIC18F/LF1XK50
devices is shown in Figure 3-1. Memory block details
are shown in Figure 24-2.
FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F/LF1XK50 DEVICES
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
High Priority Interrupt Vector 0008h
User Memory Space
1FFFFFh
4000h
3FFFh
200000h
On-Chip
Program Memory
Read ‘0’
1FFFh
2000h
On-Chip
Program Memory
Read ‘0’
PIC18F14K50
PIC18F13K50
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 30 Preliminary 2010 Microchip Technology Inc.
3.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 3.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit (LSb) of PCL is
fixed to a value of ‘0’. The PC increments by 2 to
address sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
3.1.2 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack (TOS) Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
3.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 3-2). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU:TOSH:TOSL registers. These
values can be placed on a user defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 3-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack
000D58h
TOSU TOSH TOSL
00h 1Ah 34h
STKPTR<4:0>
Top-of-Stack Registers Stack Pointer
2010 Microchip Technology Inc. Preliminary DS41350E-page 31
PIC18F1XK50/PIC18LF1XK50
3.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 3-1) contains the Stack
Pointer value, the STKFUL (stack full) bit and the
STKUNF (stack underflow) bits. The value of the Stack
Pointer can be 0 through 31. The Stack Pointer increments
before values are pushed onto the stack and
decrements after values are popped off the stack. On
Reset, the Stack Pointer value will be zero. The user
may read and write the Stack Pointer value. This feature
can be used by a Real-Time Operating System
(RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow
Reset Enable) Configuration bit. (Refer to
Section 24.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
3.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by decrementing
the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
REGISTER 3-1: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 32 Preliminary 2010 Microchip Technology Inc.
3.1.2.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
3.1.3 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All interrupt
sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers by software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be used
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALL label, FAST instruction
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.
Example 3-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 3-1: FAST REGISTER STACK
CODE EXAMPLE
3.1.4 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
3.1.4.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 3-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 3-2: COMPUTED GOTO USING
AN OFFSET VALUE
3.1.4.2 Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per program
word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to or from program memory one
byte at a time.
Table read and table write operations are discussed
further in Section 4.1 “Table Reads and Table
Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
2010 Microchip Technology Inc. Preliminary DS41350E-page 33
PIC18F1XK50/PIC18LF1XK50
3.2 PIC18 Instruction Cycle
3.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
instruction register during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 3-3.
3.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 3-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 34 Preliminary 2010 Microchip Technology Inc.
3.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as either two bytes or four bytes
in program memory. The Least Significant Byte (LSB)
of an instruction word is always stored in a program
memory location with an even address (LSb = 0). To
maintain alignment with instruction boundaries, the PC
increments in steps of 2 and the LSb will always read
‘0’ (see Section 3.1.1 “Program Counter”).
Figure 3-4 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 3-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 3-4: INSTRUCTIONS IN PROGRAM MEMORY
3.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instruction always has
‘1111’ as its four Most Significant bits (MSb); the other
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 3-4 shows how this works.
EXAMPLE 3-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1 LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 3.6 “PIC18 Instruction
Execution and the Extended Instruction
Set” for information on two-word
instructions in the extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
2010 Microchip Technology Inc. Preliminary DS41350E-page 35
PIC18F1XK50/PIC18LF1XK50
3.3 Data Memory Organization
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. Figure 3-5 and
Figure 3-6 show the data memory organization for the
PIC18F/LF1XK50 devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the Bank
Select Register (BSR). Section 3.3.3 “Access Bank”
provides a detailed description of the Access RAM.
3.3.1 USB RAM
Part of the data memory is actually mapped to a special
dual access RAM. When the USB module is disabled,
the GPRs in these banks are used like any other GPR
in the data memory space.
When the USB module is enabled, the memory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use the areas of USB RAM
that are not allocated as USB buffers for normal
scratchpad memory or other variable storage. In
practice, the dynamic nature of buffer allocation makes
this risky at best. Additional information on USB RAM
and buffer operation is provided in Section 22.0
“Universal Serial Bus (USB)”
3.3.2 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished
with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR<3:0>). The upper four bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory; the 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSRs value and the bank division in data memory is
shown in Figure 3-5 and Figure 3-6.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory maps in
Figure 3-5 and Figure 3-6 indicate which banks are
implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 3.5 “Data Memory and the
Extended Instruction Set” for more
information.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 36 Preliminary 2010 Microchip Technology Inc.
FIGURE 3-5: DATA MEMORY MAP FOR PIC18F13K50/PIC18LF13K50 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access Bank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
Unused
Read 00h
F53h
SFR(1)
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank
(DPRAM)
2010 Microchip Technology Inc. Preliminary DS41350E-page 37
PIC18F1XK50/PIC18LF1XK50
FIGURE 3-6: DATA MEMORY MAP FOR PIC18F14K50/PIC18LF14K50 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
060h
05Fh
00h
5Fh
60h
FFh
Access Bank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
GPR
GPR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank
F60h
FFFh
F5Fh
FFh
00h
SFR
Unused
F53h
SFR(1)
(DPRAM)
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 38 Preliminary 2010 Microchip Technology Inc.
FIGURE 3-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
7 0
From Opcode(2)
0 0 0 0
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0 0 1 1 1 1 1 1 1 1 1 1
7 0
BSR(1)
2010 Microchip Technology Inc. Preliminary DS41350E-page 39
PIC18F1XK50/PIC18LF1XK50
3.3.3 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of memory
(00h-5Fh) in Bank 0 and the last 160 bytes of memory
(60h-FFh) in Block 15. The lower half is known as
the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 3-5 and Figure 3-
6).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 3.5.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
3.3.4 GENERAL PURPOSE REGISTER
FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
3.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top portion of Bank 15 (F60h to FFFh). A list of
these registers is given in Table 3-1 and Table 3-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 40 Preliminary 2010 Microchip Technology Inc.
TABLE 3-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F/LF1XK50 DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FD7h TMR0H FAFh SPBRG F87h —(2) F5Fh UEIR
FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2) F5Eh UFRMH
FFDh TOSL FD5h T0CON FADh TXREG F85h —(2) F5Dh UFRML
FFCh STKPTR FD4h —(2) FACh TXSTA F84h —(2) F5Ch UADDR
FFBh PCLATU FD3h OSCCON FABh RCSTA F83h —(2) F5Bh UEIE
FFAh PCLATH FD2h OSCCON2 FAAh — F82h PORTC F5Ah UEP7
FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h UEP6
FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h UEP5
FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh ANSELH F57h UEP4
FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh ANSEL F56h UEP3
FF5h TABLAT FCDh T1CON FA5h —(2) F7Dh —(2) F55h UEP2
FF4h PRODH FCCh TMR2 FA4h —(2) F7Ch —(2) F54h UEP1
FF3h PRODL FCBh PR2 FA3h —(2) F7Bh —(2) F53h UEP0
FF2h INTCON FCAh T2CON FA2h IPR2 F7Ah IOCB
FF1h INTCON2 FC9h SSPBUF FA1h PIR2 F79h IOCA
FF0h INTCON3 FC8h SSPADD FA0h PIE2 F78h WPUB
FEFh INDF0(1) FC7h SSPSTAT F9Fh IPR1 F77h WPUA
FEEh POSTINC0(1) FC6h SSPCON1 F9Eh PIR1 F76h SLRCON
FEDh POSTDEC0(1) FC5h SSPCON2 F9Dh PIE1 F75h —(2)
FECh PREINC0(1) FC4h ADRESH F9Ch —(2) F74h —(2)
FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h —(2)
FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h —(2)
FE9h FSR0L FC1h ADCON1 F99h —(2) F71h —(2)
FE8h WREG FC0h ADCON2 F98h —(2) F70h —(2)
FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh SSPMASK
FE6h POSTINC1(1) FBEh CCPR1L F96h —(2) F6Eh —(2)
FE5h POSTDEC1(1) FBDh CCP1CON F95h —(2) F6Dh CM1CON0
FE4h PREINC1(1) FBCh REFCON2 F94h TRISC F6Ch CM2CON1
FE3h PLUSW1(1) FBBh REFCON1 F93h TRISB F6Bh CM2CON0
FE2h FSR1H FBAh REFCON0 F92h TRISA F6Ah —(2)
FE1h FSR1L FB9h PSTRCON F91h —(2) F69h SRCON1
FE0h BSR FB8h BAUDCON F90h —(2) F68h SRCON0
FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h —(2)
FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h —(2)
FDDh POSTDEC2(1) FB5h —(2) F8Dh —(2) F65h —(2)
FDCh PREINC2(1) FB4h —(2) F8Ch —(2) F64h UCON
FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h USTAT
FDAh FSR2H FB2h TMR3L F8Ah LATB F62h UIR
FD9h FSR2L FB1h T3CON F89h LATA F61h UCFG
FD8h STATUS FB0h SPBRGH F88h —(2) F60h UIE
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
2010 Microchip Technology Inc. Preliminary DS41350E-page 41
PIC18F1XK50/PIC18LF1XK50
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 285, 30
TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 285, 30
TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 285, 30
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 285, 31
PCLATU — — — Holding Register for PC<20:16> ---0 0000 285, 30
PCLATH Holding Register for PC<15:8> 0000 0000 285, 30
PCL PC, Low Byte (PC<7:0>) 0000 0000 285, 30
TBLPTRU — — — Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 285, 54
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 285, 54
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 285, 54
TABLAT Program Memory Table Latch 0000 0000 285, 54
PRODH Product Register, High Byte xxxx xxxx 285, 65
PRODL Product Register, Low Byte xxxx xxxx 285, 65
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000x 285, 70
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 1111 -1-1 285, 71
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 285, 72
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 285, 47
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 285, 47
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 285, 47
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 285, 47
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
N/A 285, 47
FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 285, 47
FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 285, 47
WREG Working Register xxxx xxxx 285
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 285, 47
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 285, 47
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 285, 47
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 285, 47
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value
of FSR1 offset by W
N/A 285, 47
FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 286, 47
FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 286, 47
BSR — — — — Bank Select Register ---- 0000 286, 35
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 286, 47
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 286, 47
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 286, 47
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 286, 47
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value
of FSR2 offset by W
N/A 286, 47
FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 286, 47
FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 286, 47
STATUS — — — N OV Z DC C ---x xxxx 286, 45
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 42 Preliminary 2010 Microchip Technology Inc.
TMR0H Timer0 Register, High Byte 0000 0000 286, 103
TMR0L Timer0 Register, Low Byte xxxx xxxx 286, 103
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 286, 101
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOSF SCS1 SCS0 0011 qq00 286, 20
OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS ---- -10x 286, 21
WDTCON — — — — — — — SWDTEN --- ---0 286, 303
RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 277,
284, 79
TMR1H Timer1 Register, High Byte xxxx xxxx 286, 110
TMR1L Timer1 Register, Low Bytes xxxx xxxx 286, 110
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 286, 105
TMR2 Timer2 Register 0000 0000 286, 112
PR2 Timer2 Period Register 1111 1111 286, 112
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 286, 111
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 286,
143, 144
SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 286, 144
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 286,
137, 146
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 286,
137, 146
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 286, 147
ADRESH A/D Result Register, High Byte xxxx xxxx 287, 221
ADRESL A/D Result Register, Low Byte xxxx xxxx 287, 221
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 287, 215
ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 ---- 0000 287, 216
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 287, 217
CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 287, 138
CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 287, 138
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 287, 117
REFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 ---0 0000 287, 248
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 000- 00-0 287, 248
REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 0001 00-- 287, 247
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 287, 134
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 287, 192
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 287, 133
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 287, 129
TMR3H Timer3 Register, High Byte xxxx xxxx 287, 115
TMR3L Timer3 Register, Low Byte xxxx xxxx 287, 115
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 287, 113
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
2010 Microchip Technology Inc. Preliminary DS41350E-page 43
PIC18F1XK50/PIC18LF1XK50
SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 287, 181
SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 287, 181
RCREG EUSART Receive Register 0000 0000 287, 182
TXREG EUSART Transmit Register 0000 0000 287, 181
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 287, 190
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 287, 191
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 287, 52,
61
EEDATA EEPROM Data Register 0000 0000 287, 52,
61
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 287, 52,
61
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 287, 53,
61
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP – 1111 111- 288, 78
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF – 0000 000- 288, 74
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE – 0000 000- 288, 76
IPR1 – ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 288, 77
PIR1 – ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 288, 73
PIE1 – ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 288, 75
OSCTUNE INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 22, 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 288, 94
TRISB TRISB7 TRISB6 TRISB5 TRISB4 – – – – 1111 ---- 288, 89
TRISA – – TRISA5 TRISA4 – – – – --11 ---- 288, 83
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 288, 94
LATB LATB7 LATB6 LATB5 LATB4 – – – – xxxx ---- 288, 89
LATA – – LATA5 LATA4 – – – – --xx ---- 288, 83
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 288, 94
PORTB RB7 RB6 RB5 RB4 – – – – xxxx ---- 288, 89
PORTA – – RA5 RA4 RA3(2) – RA1(3) RA0(3) --xx x-xx 288, 83
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 288, 99
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 1111 1--- 288, 98
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 288, 89
IOCA — — IOCA5 IOCA4 IOCA3 — IOCA1 IOCA0 --00 0-00 288, 83
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 288, 89
WPUA — — WPUA5 WPUA4 WPUA3 — — — --11 1--- 285, 89
SLRCON — — — — — SLRC SLRB SLRA ---- -111 288, 100
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 288, 154
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 1000 288, 229
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000 288, 230
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 1000 288, 230
SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 288, 243
SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 288, 242
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 288, 252
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 44 Preliminary 2010 Microchip Technology Inc.
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 289, 256
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 289, 266
UCFG UTEYE — — UPUEN — FSEN PPB1 PPB0 0--0 -000 289, 254
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 289, 268
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 289, 269
UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 289, 252
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 289, 252
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 289, 258
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 289, 270
UEP7 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP6 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP5 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP4 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP3 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP2 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP1 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP0 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 285, 257
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
2010 Microchip Technology Inc. Preliminary DS41350E-page 45
PIC18F1XK50/PIC18LF1XK50
3.3.6 STATUS REGISTER
The STATUS register, shown in Register 3-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
If the STATUS register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the STATUS
register is updated according to the instruction performed.
Therefore, the result of an instruction with the
STATUS register as its destination may be different
than intended. As an example, CLRF STATUS will set
the Z bit and leave the remaining Status bits
unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 25-2 and
Table 25-3.
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
REGISTER 3-2: STATUS: STATUS REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 46 Preliminary 2010 Microchip Technology Inc.
3.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 3.5.1 “Indexed
Addressing with Literal Offset”.
3.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any argument
at all; they either perform an operation that globally
affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
3.4.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byteoriented
instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 3.3.4 “General
Purpose Register File”) or a location in the Access
Bank (Section 3.3.3 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 3.3.2 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original
contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
3.4.3 INDIRECT ADDRESSING
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations which are to be read
or written. Since the FSRs are themselves located in
RAM as Special File Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data structures,
such as tables and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 3-5.
EXAMPLE 3-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 3.5 “Data Memory
and the Extended Instruction Set” for
more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
2010 Microchip Technology Inc. Preliminary DS41350E-page 47
PIC18F1XK50/PIC18LF1XK50
3.4.3.1 FSR Registers and the INDF
Operand
At the core of indirect addressing are three sets of registers:
FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. Each FSR pair
holds a 12-bit value, therefore the four upper bits of the
FSRnH register are not used. The 12-bit FSR value can
address the entire range of the data memory in a linear
fashion. The FSR register pairs, then, serve as pointers
to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
3.4.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers which cannot be directly
read or written. Accessing these registers actually
accesses the location to which the associated FSR
register pair points, and also performs a specific action
on the FSR value. They are:
• POSTDEC: accesses the location to which the
FSR points, then automatically decrements the
FSR by 1 afterwards
• POSTINC: accesses the location to which the
FSR points, then automatically increments the
FSR by 1 afterwards
• PREINC: automatically increments the FSR by 1,
then uses the location to which the FSR points in
the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the location to which the result points in the
operation.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by that in the W register; however,
neither W nor the FSR is actually changed in the
operation. Accessing the other virtual registers
changes the value of the FSR register.
FIGURE 3-8: INDIRECT ADDRESSING
FSR1H:FSR1L
7 0
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
7 0
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
x x x x 1 1 1 0 1 1 0 0 1 1 0 0
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 48 Preliminary 2010 Microchip Technology Inc.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers
of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
3.4.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to either
the INDF2 or POSTDEC2 register will write the same
value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise the
appropriate caution that they do not inadvertently change
settings that might affect the operation of the device.
3.5 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the introduction
of a new addressing mode for the data memory
space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
3.5.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing), or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
3.5.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 3-9.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.
2010 Microchip Technology Inc. Preliminary DS41350E-page 49
PIC18F1XK50/PIC18LF1XK50
FIGURE 3-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is interpreted
as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is interpreted
as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F60h
FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
060h
100h
F00h
F60h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
001001da ffffffff
001001da ffffffff
000h
060h
100h
F00h
F60h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
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DS41350E-page 50 Preliminary 2010 Microchip Technology Inc.
3.5.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom section of Bank 0, this
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower boundary
of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 3.3.3 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 3-10.
Remapping of the Access Bank applies only to operations
using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.
3.6 PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 25.2 “Extended Instruction Set”.
FIGURE 3-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Data Memory
000h
100h
200h
F60h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR. Access Bank
00h
60h
FFh
SFRs
Bank 1 “Window”
Bank 0
Window
Example Situation:
120h
17Fh
5Fh
Bank 1
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PIC18F1XK50/PIC18LF1XK50
4.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed one byte at
a time. A write to program memory is executed on
blocks of 16 or 8 bytes at a time depending on the specific
device (See Table 4-1). Program memory is
erased in blocks of 64 bytes at a time. The difference
between the write and erase block sizes requires from
1 to 8 block writes to restore the contents of a single
block erase. A bulk erase operation can not be issued
from user code.
TABLE 4-1: WRITE/ERASE BLOCK SIZES
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
4.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The table read operation retrieves one byte of data
directly from program memory and places it into the
TABLAT register. Figure 4-1 shows the operation of a
table read.
The table write operation stores one byte of data from the
TABLAT register into a write block holding register. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 4.5 “Writing
to Flash Program Memory”. Figure 4-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. Tables containing
data, rather than program instructions, are not
required to be word aligned. Therefore, a table can start
and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 4-1: TABLE READ OPERATION
Device Write Block
Size (bytes)
Erase Block
Size (bytes)
PIC18F13K50 8 64
PIC18F14K50 16 64
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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DS41350E-page 52 Preliminary 2010 Microchip Technology Inc.
FIGURE 4-2: TABLE WRITE OPERATION
4.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
4.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 4-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
EEPGD is clear, any subsequent operations will
operate on the data EEPROM memory. When EEPGD
is set, any subsequent operations will operate on the
program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When CFGS is clear,
memory selection access is determined by EEPGD.
The FREE bit allows the program memory erase operation.
When FREE is set, an erase operation is initiated
on the next WR command. When FREE is clear, only
writes are enabled.
The WREN bit, when set, will allow a write operation.
The WREN bit is clear on power-up.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The WR
bit cannot be cleared, only set, by firmware. Then WR
bit is cleared by hardware at the completion of the write
operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine
where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 4.5 “Writing to Flash Program Memory”.
Program Memory Holding Registers
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
The EEIF flag stays set until cleared by
firmware.
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PIC18F1XK50/PIC18LF1XK50
REGISTER 4-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
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DS41350E-page 54 Preliminary 2010 Microchip Technology Inc.
4.2.2 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
4.2.3 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 4-2. These operations on the TBLPTR affect only
the low-order 21 bits.
4.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT register
is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (See Table 4-1).The 3, 4, or 5
LSbs of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWT operations.
When a program memory write is executed the entire
holding register block is written to the Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see Section 4.5 “Writing to
Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 4-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 4-2: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 4-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21 16 15 8 7 0
TABLE ERASE/WRITE TABLE WRITE
TABLE READ – TBLPTR<21:0>
TBLPTRU TBLPTRH TBLPTRL
TBLPTR<21:n+1>(1) TBLPTR(1)
Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.
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PIC18F1XK50/PIC18LF1XK50
4.3 Reading the Flash Program
Memory
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 4-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 4-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 4-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD TABLAT
TBLPTR = xxxxx1
FETCH Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVFW TABLAT, W ; get data
MOVF WORD_ODD
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DS41350E-page 56 Preliminary 2010 Microchip Technology Inc.
4.4 Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP™ control, can larger blocks of program memory
be bulk erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the Microcontroller
itself, a block of 64 bytes of program memory is
erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash program
memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 4.4.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
A long write is necessary for erasing the internal
Flash. Instruction execution is halted during the long
write cycle. The long write is terminated by the internal
programming timer.
4.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of
block being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the block erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 4-2: ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable block Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
2010 Microchip Technology Inc. Preliminary DS41350E-page 57
PIC18F1XK50/PIC18LF1XK50
4.5 Writing to Flash Program Memory
The programming block size is 8 or 16 bytes,
depending on the device (See Table 4-1). Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 4-1).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 8, or 16
times, depending on the device, for each programming
operation. All of the table write operations will essentially
be short writes because only the holding registers
are written. After all the holding registers have been
written, the programming operation of that block of
memory is started by configuring the EECON1 register
for a program memory write and performing the long
write sequence.
The long write is necessary for programming the internal
Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 4-5: TABLE WRITES TO FLASH PROGRAM MEMORY
4.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the block erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 8 or 16-byte block into the holding
registers with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
bytes are written.
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 4-3.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
TABLAT
TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxxYY(1)
Write Register
TBLPTR = xxxx02
Program Memory
Holding Register Holding Register Holding Register Holding Register
8 8 8 8
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 58 Preliminary 2010 Microchip Technology Inc.
EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
WRITE_BUFFER_BACK
MOVLW BlockSize ; number of bytes in holding register
MOVWF COUNTER
MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes
MOVWF COUNTER2
WRITE_BYTE_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
2010 Microchip Technology Inc. Preliminary DS41350E-page 59
PIC18F1XK50/PIC18LF1XK50
EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
4.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
4.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
4.5.4 PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
4.6 Flash Program Operation During
Code Protection
See Section 24.3 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 4-3: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
DECFSZ COUNTER ; loop until holding registers are full
BRA WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DCFSZ COUNTER2 ; repeat for remaining write blocks
BRA WRITE_BYTE_TO_HREGS ;
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 285
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 285
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 285
TABLAT Program Memory Table Latch 285
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
EECON2 EEPROM Control Register 2 (not a physical register) 287
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 287
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
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DS41350E-page 60 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 61
PIC18F/LF1XK50
5.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory,
which is used for long-term storage of program data. It
is not directly mapped in either the register file or
program memory space but is indirectly addressed
through the Special Function Registers (SFRs). The
EEPROM is readable and writable during normal
operation over the entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR register
pair hold the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chipto-
chip. Please refer to parameter US122 (Table 27-13
in Section 27.0 “Electrical Specifications”) for exact
limits.
5.1 EEADR Register
The EEADR register is used to address the data
EEPROM for read and write operations. The 8-bit
range of the register can address a memory range of
256 bytes (00h to FFh).
5.2 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 5-1) is the control
register for data and program memory access. Control
bit EEPGD determines if the access will be to program
or data EEPROM memory. When the EEPGD bit is
clear, operations will access the data EEPROM
memory. When the EEPGD bit is set, program memory
is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When the CFGS bit is set,
subsequent operations access Configuration registers.
When the CFGS bit is clear, the EEPGD bit selects
either program Flash or data EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The bit
can be set but not cleared by software. It is cleared only
by hardware at the completion of the write operation.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 4.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note: During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely terminated
by a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
It must be cleared by software.
PIC18F/LF1XK50
DS41350E-page 62 Preliminary 2010 Microchip Technology Inc.
REGISTER 5-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
2010 Microchip Technology Inc. Preliminary DS41350E-page 63
PIC18F/LF1XK50
5.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control
bit of the EECON1 register and then set control bit,
RD. The data is available on the very next instruction
cycle; therefore, the EEDATA register can be read by
the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
The basic process is shown in Example 5-1.
5.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data written
to the EEDATA register. The sequence in
Example 5-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
5.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 5-1: DATA EEPROM READ
EXAMPLE 5-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR_LOW ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
; User code execution
BCF EECON1, WREN ; Disable writes on write complete (EEIF set)
PIC18F/LF1XK50
DS41350E-page 64 Preliminary 2010 Microchip Technology Inc.
5.6 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 24.0
“Special Features of the CPU” for additional
information.
5.7 Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
5.8 Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. If this is the case, then an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
EXAMPLE 5-3: DATA EEPROM REFRESH ROUTINE
TABLE 5-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 287
EEDATA EEPROM Data Register 287
EECON2 EEPROM Control Register 2 (not a physical register) 287
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 287
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
2010 Microchip Technology Inc. Preliminary DS41350E-page 65
PIC18F/LF1XK50
6.0 8 x 8 HARDWARE MULTIPLIER
6.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications
previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 6-1.
6.2 Operation
Example 6-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 6-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 6-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 6-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply 13 69 6.9 s 27.6 s 69 s
Hardware multiply 1 1 100 ns 400 ns 1 s
8 x 8 signed
Without hardware multiply 33 91 9.1 s 36.4 s 91 s
Hardware multiply 6 6 600 ns 2.4 s 6 s
16 x 16 unsigned
Without hardware multiply 21 242 24.2 s 96.8 s 242 s
Hardware multiply 28 28 2.8 s 11.2 s 28 s
16 x 16 signed
Without hardware multiply 52 254 25.4 s 102.6 s 254 s
Hardware multiply 35 40 4.0 s 16.0 s 40 s
PIC18F/LF1XK50
DS41350E-page 66 Preliminary 2010 Microchip Technology Inc.
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 6-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES<3:0>).
EQUATION 6-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-4 shows the sequence to do a 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the arguments,
the MSb for each argument pair is tested and
the appropriate subtractions are done.
EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 6-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 216) +
(-1 ARG1H<7> ARG2H:ARG2L 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
2010 Microchip Technology Inc. Preliminary DS41350E-page 67
PIC18F/LF1XK50
7.0 INTERRUPTS
The PIC18F/LF1XK50 devices have multiple interrupt
sources and an interrupt priority feature that allows
most interrupt sources to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 0008h and the low priority interrupt vector is
at 0018h. A high priority interrupt event will interrupt a
low priority interrupt that may be in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files supplied
with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
7.1 Mid-Range Compatibility
When the IPEN bit is cleared (default state), the interrupt
priority feature is disabled and interrupts are compatible
with PIC® microcontroller mid-range devices. In
Compatibility mode, the interrupt priority bits of the IPRx
registers have no effect. The PEIE bit of the INTCON
register is the global interrupt enable for the peripherals.
The PEIE bit disables only the peripheral interrupt
sources and enables the peripheral interrupt sources
when the GIE bit is also set. The GIE bit of the INTCON
register is the global interrupt enable which enables all
non-peripheral interrupt sources and disables all
interrupt sources, including the peripherals. All interrupts
branch to address 0008h in Compatibility mode.
7.2 Interrupt Priority
The interrupt priority feature is enabled by setting the
IPEN bit of the RCON register. When interrupt priority
is enabled the GIE and PEIE global interrupt enable
bits of Compatibility mode are replaced by the GIEH
high priority, and GIEL low priority, global interrupt
enables. When set, the GIEH bit of the INTCON register
enables all interrupts that have their associated
IPRx register or INTCONx register priority bit set (high
priority). When clear, the GIEL bit disables all interrupt
sources including those selected as low priority. When
clear, the GIEL bit of the INTCON register disables only
the interrupts that have their associated priority bit
cleared (low priority). When set, the GIEL bit enables
the low priority sources when the GIEH bit is also set.
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are all set, the interrupt will
vector immediately to address 0008h for high priority,
or 0018h for low priority, depending on level of the
interrupting source’s priority bit. Individual interrupts
can be disabled through their corresponding interrupt
enable bits.
7.3 Interrupt Response
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. The
GIE bit is the global interrupt enable when the IPEN bit
is cleared. When the IPEN bit is set, enabling interrupt
priority levels, the GIEH bit is the high priority global
interrupt enable and the GIEL bit is the low priority
global interrupt enable. High priority interrupt sources
can interrupt a low priority interrupt. Low priority
interrupts are not processed while high priority
interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits in the INTCONx and PIRx
registers. The interrupt flag bits must be cleared by
software before re-enabling interrupts to avoid
repeating the same interrupt.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB interrupt-on-change, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one-cycle or two-cycle
PIC18F/LF1XK50
DS41350E-page 68 Preliminary 2010 Microchip Technology Inc.
instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding enable
bits or the global interrupt enable bit.
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers
while any interrupt is enabled. Doing so
may cause erratic microcontroller behavior.
2010 Microchip Technology Inc. Preliminary DS41350E-page 69
PIC18F/LF1XK50
FIGURE 7-1: PIC18 INTERRUPT LOGIC
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RABIF
RABIE
RABIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RABIF
RABIE
RABIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
SSPIF
SSPIE
SSPIP
SSPIF
SSPIE
SSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIEH/GIE
Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable.
(1)
(1)
PIC18F/LF1XK50
DS41350E-page 70 Preliminary 2010 Microchip Technology Inc.
7.4 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts including peripherals
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts including low priority.
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority interrupts
0 = Disables all low priority interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RABIE: RA and RB Port Change Interrupt Enable bit(2)
1 = Enables the RA and RB port change interrupt
0 = Disables the RA and RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared by software)
0 = The INT0 external interrupt did not occur
bit 0 RABIF: RA and RB Port Change Interrupt Flag bit(1)
1 = At least one of the RA <5:3> or RB<7:4> pins changed state (must be cleared by software)
0 = None of the RA<5:3> or RB<7:4> pins have changed state
Note 1: A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the
mismatch condition and allow the bit to be cleared.
2: RA and RB port change interrupts also require the individual pin IOCA and IOCB enable.
2010 Microchip Technology Inc. Preliminary DS41350E-page 71
PIC18F/LF1XK50
REGISTER 7-2: INTCON2: INTERRUPT CONTROL 2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RABPU: PORTA and PORTB Pull-up Enable bit
1 = All PORTA and PORTB pull-ups are disabled
0 = PORTA and PORTB pull-ups are enabled provided that the pin is an input and the corresponding
WPUA and WPUB bits are set.
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RABIP: RA and RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
PIC18F/LF1XK50
DS41350E-page 72 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-3: INTCON3: INTERRUPT CONTROL 3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared by software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared by software)
0 = The INT1 external interrupt did not occur
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
2010 Microchip Technology Inc. Preliminary DS41350E-page 73
PIC18F/LF1XK50
7.5 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the
state of its corresponding enable bit or the
Global Interrupt Enable bit, GIE of the
INTCON register.
2: User software should ensure the appropriate
interrupt flag bits are cleared prior
to enabling an interrupt and after servicing
that interrupt.
REGISTER 7-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared by software)
0 = TMR1 register did not overflow
PIC18F/LF1XK50
DS41350E-page 74 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)
0 = Device clock operating
bit 6 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator C1 output has changed (must be cleared by software)
0 = Comparator C1 output has not changed
bit 5 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator C2 output has changed (must be cleared by software)
0 = Comparator C2 output has not changed
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared by software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared by software)
0 = No bus collision occurred
bit 2 USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared by software)
0 = TMR3 register did not overflow
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 75
PIC18F/LF1XK50
7.6 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 7-6: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIC18F/LF1XK50
DS41350E-page 76 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 C1IE: Comparator C1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 C2IE: Comparator C2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 77
PIC18F/LF1XK50
7.7 IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Priority registers (IPR1 and IPR2). Using the priority bits
requires that the Interrupt Priority Enable (IPEN) bit be
set.
REGISTER 7-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
PIC18F/LF1XK50
DS41350E-page 78 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0
OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 C1IP: Comparator C1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 C2IP: Comparator C2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 79
PIC18F/LF1XK50
7.8 RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 23.1 “RCON
Register”.
REGISTER 7-10: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN(1) — RI TO PD POR(2) BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware or Power-on Reset)
0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a
code-executed Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit(3)
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 23.6 “Reset State of Registers” for additional information.
3: See Table 23-3.
PIC18F/LF1XK50
DS41350E-page 80 Preliminary 2010 Microchip Technology Inc.
7.9 INTn Pin Interrupts
External interrupts on the RC0/INT0, RC1/INT1 and
RC2/INT2 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RCx/INTx pin, the
corresponding flag bit, INTxF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxE. Flag bit, INTxF, must be cleared by software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1 and INT2) can wakeup
the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits,
INT1IP and INT2IP of the INTCON3 register. There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.10 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See Section 10.0 “Timer0 Module” for further details
on the Timer0 module.
7.11 PORTA and PORTB Interrupt-on-
Change
An input change on PORTA or PORTB sets flag bit,
RABIF of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing enable bit, RABIE
of the INTCON register. Pins must also be individually
enabled with the IOCA and IOCB register. Interrupt
priority for PORTA and PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RABIP of the INTCON2 register.
7.12 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 3.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 7-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
2010 Microchip Technology Inc. Preliminary DS41350E-page 81
PIC18F1XK50/PIC18LF1XK50
8.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC18F1XK50 devices differ from the
PIC18LF1XK50 devices due to an internal Low
Dropout (LDO) voltage regulator. The PIC18F1XK50
contain an internal LDO, while the PIC18LF1XK50 do
not.
The lithography of the die allows a maximum operating
voltage of the nominal 3.6V on the internal digital logic.
In order to continue to support 5.0V designs, a LDO
voltage regulator is integrated on the die. The LDO
voltage regulator allows for the internal digital logic to
operate at 3.3V, while I/O’s operate at 5.0V (VDD).
The LDO voltage regulator requires an external bypass
capacitor for stability. The VUSB pin is required to have
an external bypass capacitor. It is recommended that
the capacitor be a ceramic cap between 0.22 to 0.47 μF.
On power-up, the external capacitor will look like a
large load on the LDO voltage regulator. To prevent
erroneous operation, the device is held in Reset while
a constant current source charges the external
capacitor. After the cap is fully charged, the device is
released from Reset. For more information, refer to
Section 27.0 “Electrical Specifications”.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 82 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 83
PIC18F/LF1XK50
9.0 I/O PORTS
There are up to three ports available. Some pins of the
I/O ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The PORTA Data Latch (LATA register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
FIGURE 9-1: GENERIC I/O PORT
OPERATION
9.1 PORTA, TRISA and LATA Registers
PORTA is 5 bits wide. PORTA<5:4> bits are
bidirectional ports and PORTA<3,1:0> bits are inputonly
ports. The corresponding data direction register is
TRISA. Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enable the
output driver and put the contents of the output latch on
the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the PORT latch.
The PORTA Data Latch (LATA) register is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
All of the PORTA pins are individually configurable as
interrupt-on-change pins. Control bits in the IOCA
register enable (when set) or disable (when clear) the
interrupt function for each pin.
When set, the RABIE bit of the INTCON register
enables interrupts on all pins which also have their
corresponding IOCA bit set. When clear, the RABIE
bit disables all interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any pin configured as an output is
excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt flag
bit (RABIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTA to clear the mismatch
condition (except when PORTA is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RABIF.
A mismatch condition will continue to set the RABIF flag
bit. Reading or writing PORTA will end the mismatch
condition and allow the RABIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RABIF flag will continue to be set if a mismatch is present.
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
D Q
CK
D Q
CK
EN
Q D
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to VDD and VSS.
PIC18F/LF1XK50
DS41350E-page 84 Preliminary 2010 Microchip Technology Inc.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTA is only used for the interrupt-on-change
feature. Polling of PORTA is not recommended while
using the interrupt-on-change feature.
Each of the PORTA pins has an individually controlled
weak internal pull-up. When set, each bit of the WPUA
register enables the corresponding pin pull-up. When
cleared, the RABPU bit of the INTCON2 register
enables pull-ups on all pins which also have their corresponding
WPUA bit set. When set, the RABPU bit
disables all weak pull-ups. The weak pull-up is automatically
turned off when the port pin is configured as
an output. The pull-ups are disabled on a Power-on
Reset.
RA0 and RA1 are multiplexed with the USB module
and can serve as the differential data lines for the onchip
USB transceiver.
RA0 and RA1 do not have TRISA bits associated with
them. As digital port pins, they can only function as
digital inputs. When configured for USB operation, the
data direction is determined by the configuration and
status of the USB module at a given time.
RA3 is an input only pin. Its operation is controlled by
the MCLRE bit of the CONFIG3H register. When
selected as a port pin (MCLRE = 0), it functions as a
digital input only pin; as such, it does not have TRIS or
LAT bits associated with its operation.
Pins RA4 and RA5 are multiplexed with the main oscillator
pins; they are enabled as oscillator or I/O pins by
the selection of the main oscillator in the Configuration
register (see Section 24.1 “Configuration Bits” for
details). When they are not used as port pins, RA4 and
RA5 and their associated TRIS and LAT bits read as
‘0’.
Pin RA4 is multiplexed with an analog input. The operation
of pin RA4 as analog is selected by setting the
ANS3 bit in the ANSEL register which is the default setting
after a Power-on Reset.
EXAMPLE 9-1: INITIALIZING PORTA
Note 1: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the
RABIF interrupt flag may not get set. Furthermore,
since a read or write on a port
affects all bits of that port, care must be
taken when using multiple pins in Interrupt-
on-change mode. Changes on one
pin may not be seen while servicing
changes on another pin.
2: When configured for USB operation,
interrupt-on-change functionality on RA0
and RA1 is automatically disabled.
3: In order for the digital inputs to function
on the RA<1:0> port pins, the interrupton-
change pins must be enabled (IOCA
<1:0> = 11) and the USB module must be
disabled (USBEN = 0).
Note: On a Power-on Reset, RA4 is configured
as analog inputs by default and read as
‘0’; RA<1:0> and RA<5:3> are configured
as digital inputs.
Note: On a Power-on Reset, RA3 is enabled as
a digital input only if Master Clear
functionality is disabled.
Note: On a Power-on Reset, RA4 is configured
as analog inputs and read as ‘0’.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 030h ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<5:4> as output
2010 Microchip Technology Inc. Preliminary DS41350E-page 85
PIC18F/LF1XK50
REGISTER 9-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x R/W-x R-x U-0 R/W-x R/W-x
— — RA5 RA4 RA3 — RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 RA<5:3>: PORTA I/O Pin bit(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 2 Unimplemented: Read as ‘0’
bit 1-0 RA<1:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0).
Otherwise, RA3 reads as ‘0’. This bit is read-only.
REGISTER 9-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0
— — TRISA5 TRISA4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’
Note 1: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
PIC18F/LF1XK50
DS41350E-page 86 Preliminary 2010 Microchip Technology Inc.
REGISTER 9-3: WPUA: WEAK PULL-UP PORTA REGISTER
U-0 U-0 R/W-1 R/W-1 RW-1 U-0 U-0 U-0
— — WPUA5 WPUA4 WPUA3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 WPUA<5:3>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 2 Unimplemented: Read as ‘0’
bit 1-0 WPUA<1:0>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
REGISTER 9-4: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 U-0 R/W-0 R/W-0 R-0 U-0 R/W-0 R/W-0
— — IOCA5 IOCA4 IOCA3 — IOCA1 IOCA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 IOCA<5:3>: PORTA I/O Pin bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 2 Unimplemented: Read as ‘0’
bit 1-0 IOCA<1:0>: PORTA I/O Pin bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
REGISTER 9-5: LATA: PORTA DATA LATCH REGISTER
U-0 U-0 R/W-x R/W-x U-0 U-0 U-0 U-0
— — LATA5 LATA4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 LATA<5:4>: RA<5:4> Port I/O Output Latch Register bits
bit 3-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 87
PIC18F/LF1XK50
TABLE 9-1: PORTA I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RA0/IOCA0/D+/
PGD
RA0 —(1) I TTL PORTA<0> data input; disabled when USB enabled.
IOCA0 —(1) I TTL Interrupt-on-pin change; disabled when USB enabled.
D+ —(1) I XCVR USB bus differential plus line input (internal transceiver).
—(1) O XCVR USB bus differential plus line output (internal transceiver).
PGD —(1) O DIG Serial execution data output for ICSP™.
—(1) I ST Serial execution data input for ICSP™.
RA1/IOCA1/D-/
PGC
RA1 —(1) I TTL PORTA<1> data input; disabled when USB enabled.
IOCA1 —(1) I TTL Interrupt-on-pin change; disabled when USB enabled.
D- —(1) I XCVR USB bus differential minus line input (internal transceiver).
—(1) O XCVR USB bus differential minus line output (internal transceiver).
PGC —(1) O DIG Serial execution clock output for ICSP™.
—(1) I ST Serial execution clock input for ICSP™.
RA3/IOCA3/MCLR/
VPP
RA3 —(2) I ST PORTA<3> data input; enabled when MCLRE Configuration bit is
clear; Programmable weak pull-up.
IOCA3 —(1) I TTL Interrupt-on-pin change
MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is
set.
VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RA4/IOCA4/AN3/
OSC2/CLKOUT
RA4 0 O DIG LATA<4> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1 I TTL PORTA<4> data input; Programmable weak pull-up. Enabled in RCIO,
INTIO2 and ECIO modes only.
IOCA4 1 I TTL Interrupt-on-pin change
AN3 1 I ANA A/D input channel 3. Default configuration on POR.
OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKOUT x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
RA5/IOCA5/OSC1/
CLKIN
RA5 0 O DIG LATA<5> data output. Disabled in external oscillator modes.
1 I TTL PORTA<5> data input. Disabled in external oscillator modes; Programmable
weak pull-up.
IOCA5 1 I TTL Interrupt-on-pin change
OSC1 x I ANA Main oscillator input connection.
CLKIN x I ANA Main clock input connection.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RA0 and RA1 do not have corresponding TRISA bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
2: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.
PIC18F/LF1XK50
DS41350E-page 88 Preliminary 2010 Microchip Technology Inc.
TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
PORTA — — RA5(1) RA4(1) RA3(2) — RA1(3) RA0(3) 288
LATA — — LATA5(1) LATA4(1) — — — — 288
TRISA — — TRISA5(1) TRISA4(1) — — — — 288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
SLRCON — — — — — SLRC SLRB SLRA 288
IOCA — — IOCA5 IOCA4 IOCA3(2) — IOCA1(3) IOCA0(3) 288
WPUA — — WPUA5 WPUA4 WPUA3(2) — — — 288
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 288
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
3: RA1 and RA0 are only available as port pins when the USB module is disabled (UCON<3> = 0).
2010 Microchip Technology Inc. Preliminary DS41350E-page 89
PIC18F/LF1XK50
9.2 PORTB, TRISB and LATB
Registers
PORTB is an 4-bit wide, bidirectional port. The corresponding
data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The PORTB Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 9-2: INITIALIZING PORTB
All PORTB pins are individually configurable as
interrupt-on-change pins. Control bits in the IOCB register
enable (when set) or disable (when clear) the
interrupt function for each pin.
When set, the RABIE bit of the INTCON register
enables interrupts on all pins which also have their
corresponding IOCB bit set. When clear, the RABIE
bit disables all interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any pin configured as an output is
excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTB to clear the mismatch
condition (except when PORTB is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RABIF.
A mismatch condition will continue to set the RABIF flag
bit. Reading or writing PORTB will end the mismatch
condition and allow the RABIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RABIF flag will continue to be set if a mismatch is present.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
All PORTB pins have individually controlled weak internal
pull-up. When set, each bit of the WPUB register
enables the corresponding pin pull-up. When cleared,
the RABPU bit of the INTCON2 register enables pullups
on all pins which also have their corresponding
WPUB bit set. When set, the RABPU bit disables all
weak pull-ups. The weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0F0h ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<7:4> as outputs
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all
bits of that port, care must be taken when
using multiple pins in Interrupt-on-change
mode. Changes on one pin may not be
seen while servicing changes on another
pin.
Note: On a Power-on Reset, RB<5:4> are
configured as analog inputs by default and
read as ‘0’.
PIC18F/LF1XK50
DS41350E-page 90 Preliminary 2010 Microchip Technology Inc.
REGISTER 9-6: PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 RB<7:4>: PORTB I/O Pin bit
1 = Port pin is >VIH
0 = Port pin is : PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 91
PIC18F/LF1XK50
REGISTER 9-8: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 9-9: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-change bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 9-10: LATB: PORTB DATA LATCH REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
LATB7 LATB6 LATB5 LATB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits
bit 3-0 Unimplemented: Read as ‘0’
PIC18F/LF1XK50
DS41350E-page 92 Preliminary 2010 Microchip Technology Inc.
TABLE 9-3: PORTB I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RB4/IOCB4/AN10/
SDI/SDA
RB4 0 O DIG LATB<4> data output; not affected by analog input.
1 I TTL PORTB<4> data input; Programmable weak pull-up.
IOCB4 1 I TTL Interrupt-on-pin change.
AN10 1 I ANA ADC input channel 10.
SDI 1 I ST SPI data input (MSSP module).
SDA 1 I DIG I2C™ data output (MSSP module); takes priority over port data.
1 O I2C I2C™ data input (MSSP module); input type depends on module
setting.
RB5/IOCB5/AN11/
RX/DT
RB5 0 O DIG LATB<5> data output.
1 I TTL PORTB<5> data input; Programmable weak pull-up.
IOCB5 1 I TTL Interrupt-on-pin change.
AN11 1 I ANA ADC input channel 11.
RX 1 I ST Asynchronous serial receive data input (USART module).
DT 1 O DIGSynchronous serial data output (USART module); takes priority over
port data.
1 I STSynchronous serial data input (USART module). User must configure
as an input.
RB6/IOCB6/SCK/
SCL
RB6 0 O DIG LATB<6> data output.
1 I TTL PORTB<6> data input; Programmable weak pull-up.
IOCB6 1 I TTL Interrupt-on-pin change.
SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data.
1 I ST SPI clock input (MSSP module).
SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data.
1 I I2C I2C™ clock input (MSSP module); input type depends on module
setting.
RB7/IOCB7/TX/CK RB7 0 O DIG LATB<7> data output.
1 I TTL PORTB<7> data input; Programmable weak pull-up.
IOCB7 1 I TTL Interrupt-on-pin change.
TX 1 O DIGAsynchronous serial transmit data output (USART module); takes
priority over port data. User must configure as output.
CK 1 O DIGSynchronous serial clock output (USART module); takes priority over
port data.
1 I ST Synchronous serial clock input (USART module).
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010 Microchip Technology Inc. Preliminary DS41350E-page 93
PIC18F/LF1XK50
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTB RB7 RB6 RB5 RB4 — — — — 288
LATB LATB7 LATB6 LATB5 LATB4 — — — — 288
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 288
IOCB IOCB7 IOCB6 IOCB5 IOCB4 288
SLRCON — — — — — SLRC SLRB SLRA 288
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
PIC18F/LF1XK50
DS41350E-page 94 Preliminary 2010 Microchip Technology Inc.
9.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding
data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., disable the output driver). Clearing a
TRISC bit (= 0) will make the corresponding PORTC
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The PORTC Data Latch register (LATC) is also
memory mapped. Read-modify-write operations on the
LATC register read and write the latched output value
for PORTC.
All the pins on PORTC are implemented with Schmitt
Trigger input buffer. Each pin is individually configurable
as an input or output.
EXAMPLE 9-3: INITIALIZING PORTC
Note: On a Power-on Reset, RC<7:6> and
RC<3:0> are configured as analog inputs
and read as ‘0’.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
REGISTER 9-11: PORTC: PORTC REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 9-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
2010 Microchip Technology Inc. Preliminary DS41350E-page 95
PIC18F/LF1XK50
REGISTER 9-13: LATC: PORTC DATA LATCH REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits
PIC18F/LF1XK50
DS41350E-page 96 Preliminary 2010 Microchip Technology Inc.
TABLE 9-14: PORTC I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RC0/AN4/
C12IN+/VREF+/
INT0
RC0 0 O DIG LATC<0> data output.
1 I ST PORTC<0> data input.
AN4 1 I ANA A/D input channel 4.
C12IN+ 1 I ANA Comparators C1 and C2 non-inverting input. Analog select is
shared with ADC.
VREF+ 1 I ANA ADC and comparator voltage reference high input.
INT0 1 I ST External Interrupt 0 input.
RC1/AN5/
C12IN1-/VREF-/
INT1
RC1 0 O DIG LATC<1> data output.
1 I ST PORTC<1> data input.
AN5 1 I ANA A/D input channel 5.
C12IN1- 1 I ANA Comparators C1 and C2 inverting input. Analog select is
shared with ADC.
VREF- 1 I ANA ADC and comparator voltage reference low input.
INT1 1 I ST External Interrupt 1 input.
RC2/AN6/
C12IN2-/CVREF/
P1D/INT2
RC2 0 O DIG LATC<2> data output.
1 I ST PORTC<2> data input.
AN6 1 I ANA A/D input channel 6.
C12IN2- 1 I ANA Comparators C1 and C2 inverting input, channel 2. Analog select is
shared with ADC.
CVREF x O ANA Voltage reference output. Enabling this feature disables digital I/O.
P1D 0 O DIG ECCP1 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
INT2 1 I ST External Interrupt 2 input.
RC3/AN7/
C12IN3-/P1C/
PGM
RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
AN7 1 I ANA A/D input channel 7.
C12IN3- 1 I ANA Comparators C1 and C2 inverting input, channel 3. Analog select is
shared with ADC.
P1C 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
RC4/C12OUT/
P1B
RC4 0 O DIG LATC<4> data output.
1 I ST PORTC<4> data input.
C12OUT 0 O DIG Comparator 1 and 2 output; takes priority over port data.
P1B 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010 Microchip Technology Inc. Preliminary DS41350E-page 97
PIC18F/LF1XK50
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
RC5/CCP1/P1A/
T0CKI
RC5 0 O DIG LATC<5> data output.
1 I ST PORTC<5> data input.
CCP1 0 O DIG ECCP1 compare or PWM output; takes priority over port data.
1 I ST ECCP1 capture input.
P1A 0 0 DIG ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data
T0CKI 1 I ST Timer0 counter input.
RC6/AN8/SS/
T13CKI/T1OSCI
RC6 0 O DIG LATC<6> data output.
1 I ST PORTC<6> data input.
AN8 1 I ANA A/D input channel 8.
SS 1 I TTL Slave select input for SSP (MSSP module)
T13CKI 1 I ST Timer1 and Timer3 counter input.
T1OSCI x O ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
RC7/AN9/SDO/
T1OSCO
RC7 0 O DIG LATC<7> data output.
1 I ST PORTC<7> data input.
AN9 1 I ANA A/D input channel 9.
SDO 0 I DIG SPI data output (MSSP module); takes priority over port data.
T1OSCO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 288
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 287
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 287
PSTRCON — — — STRSYNC STRD STRC STRB STRA 287
SLRCON — — — — — SLRC SLRB SLRA 288
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 --- D1NSS 287
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 285
TABLE 9-14: PORTC I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I/O I/O
Type Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PIC18F/LF1XK50
DS41350E-page 98 Preliminary 2010 Microchip Technology Inc.
9.4 Port Analog Control
Some port pins are multiplexed with analog functions
such as the Analog-to-Digital Converter and comparators.
When these I/O pins are to be used as analog
inputs it is necessary to disable the digital input buffer
to avoid excessive current caused by improper biasing
of the digital input. Individual control of the digital input
buffers on pins which share analog functions is provided
by the ANSEL and ANSELH registers. Setting an
ANSx bit high will disable the associated digital input
buffer and cause all reads of that pin to return ‘0’ while
allowing analog functions of that pin to operate
correctly.
The state of the ANSx bits has no affect on digital
output functions. A pin with the associated TRISx bit
clear and ANSx bit set will still operate as a digital
output but the Input mode will be analog.
REGISTER 9-15: ANSEL: ANALOG SELECT REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0
ANS7 ANS6 ANS5 ANS4 ANS3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ANS7: RC3 Analog Select Control bit
1 = Digital input buffer of RC3 is disabled
0 = Digital input buffer of RC3 is enabled
bit 6 ANS6: RC2 Analog Select Control bit
1 = Digital input buffer of RC2 is disabled
0 = Digital input buffer of RC2 is enabled
bit 5 ANS5: RC1 Analog Select Control bit
1 = Digital input buffer of RC1 is disabled
0 = Digital input buffer of RC1 is enabled
bit 4 ANS4: RC0 Analog Select Control bit
1 = Digital input buffer of RC0 is disabled
0 = Digital input buffer of RC0 is enabled
bit 3 ANS3: RA4 Analog Select Control bit
1 = Digital input buffer of RA4 is disabled
0 = Digital input buffer of RA4 is enabled
bit 2-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 99
PIC18F/LF1XK50
REGISTER 9-16: ANSELH: ANALOG SELECT REGISTER 2
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 ANS11: RB5 Analog Select Control bit
1 = Digital input buffer of RB5 is disabled
0 = Digital input buffer of RB5 is enabled
bit 2 ANS10: RB4 Analog Select Control bit
1 = Digital input buffer of RB4 is disabled
0 = Digital input buffer of RB4 is enabled
bit 1 ANS9: RC7 Analog Select Control bit
1 = Digital input buffer of RC7 is disabled
0 = Digital input buffer of RC7 is enabled
bit 0 ANS8: RC6 Analog Select Control bit
1 = Digital input buffer of RC6 is disabled
0 = Digital input buffer of RC6 is enabled
PIC18F/LF1XK50
DS41350E-page 100 Preliminary 2010 Microchip Technology Inc.
9.5 Port Slew Rate Control
The output slew rate of each port is programmable to
select either the standard transition rate or a reduced
transition rate of 0.1 times the standard to minimize
EMI. The reduced transition time is the default slew
rate for all ports.
REGISTER 9-17: SLRCON: SLEW RATE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
— — — — — SLRC SLRB SLRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 SLRC: PORTC Slew Rate Control bit
1 = All outputs on PORTC slew at 0.1 times the standard rate
0 = All outputs on PORTC slew at the standard rate
bit 1 SLRB: PORTB Slew Rate Control bit
1 = All outputs on PORTB slew at 0.1 times the standard rate
0 = All outputs on PORTB slew at the standard rate
bit 0 SLRA: PORTA Slew Rate Control bit
1 = All outputs on PORTA slew at 0.1 times the standard rate(1)
0 = All outputs on PORTA slew at the standard rate
Note 1: The slew rate of RA4 defaults to standard rate when the pin is used as CLKOUT.
2010 Microchip Technology Inc. Preliminary DS41350E-page 101
PIC18F/LF1XK50
10.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or counter
in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
The T0CON register (Register 10-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 10-1. Figure 10-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
PIC18F/LF1XK50
DS41350E-page 102 Preliminary 2010 Microchip Technology Inc.
10.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit of the T0CON
register. In Timer mode (T0CS = 0), the module
increments on every clock by default unless a different
prescaler value is selected (see Section 10.3
“Prescaler”). Timer0 incrementing is inhibited for two
instruction cycles following a TMR0 register write. The
user can work around this by adjusting the value written
to the TMR0 register to compensate for the anticipated
missing increments.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of the T0CKI pin. The incrementing
edge is determined by the Timer0 Source Edge
Select bit, T0SE of the T0CON register; clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements (see
Table 27-6) to ensure that the external clock can be
synchronized with the internal phase clock (TOSC).
There is a delay between synchronization and the
onset of incrementing the timer/counter.
10.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0 which is neither directly readable nor
writable (refer to Figure 10-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without the need to verify that the read of the
high and low byte were valid. Invalid reads could
otherwise occur due to a rollover between successive
reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. Writing
to TMR0H does not directly affect Timer0. Instead, the
high byte of Timer0 is updated with the contents of
TMR0H when a write occurs to TMR0L. This allows all
16 bits of Timer0 to be updated at once.
FIGURE 10-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
PSA Internal Data Bus
T0PS<2:0>
Set
TMR0IF
on Overflow
3 8
8
2010 Microchip Technology Inc. Preliminary DS41350E-page 103
PIC18F/LF1XK50
FIGURE 10-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
10.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON register which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
10.3.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
10.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register
overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clearing
the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS<2:0>
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
8
8
8
Read TMR0L
Write TMR0L
8
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TMR0L Timer0 Register, Low Byte 286
TMR0H Timer0 Register, High Byte 286
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 286
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: Shaded cells are not used by Timer0.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
PIC18F/LF1XK50
DS41350E-page 104 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 105
PIC18F/LF1XK50
11.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates the
following features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable internal or external clock source and
Timer1 oscillator options
• Interrupt-on-overflow
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Figure 11-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 11-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 11-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON of the T1CON register.
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Main system clock is derived from Timer1 oscillator
0 = Main system clock is derived from another source
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from the T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC18F/LF1XK50
DS41350E-page 106 Preliminary 2010 Microchip Technology Inc.
11.1 Timer1 Operation
Timer1 can operate in one of the following modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS of the T1CON register. When TMR1CS is
cleared (= 0), Timer1 increments on every internal
instruction cycle (FOSC/4). When the bit is set, Timer1
increments on every rising edge of either the Timer1
external clock input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled, the digital
circuitry associated with the T1OSI and T1OSO pins is
disabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
FIGURE 11-1: TIMER1 BLOCK DIAGRAM
FIGURE 11-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSI/T13CKI
T1OSO
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
Clear TMR1 High Byte
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSI/T13CKI
T1OSO
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Timer1 Clock Input
2010 Microchip Technology Inc. Preliminary DS41350E-page 107
PIC18F/LF1XK50
11.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit of the
T1CON register is set, the address for TMR1H is
mapped to a buffer register for the high byte of Timer1.
A read from TMR1L will load the contents of the high
byte of Timer1 into the Timer1 high byte buffer. This
provides the user with the ability to accurately read all
16 bits of Timer1 without the need to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover or
carry between reads.
Writing to TMR1H does not directly affect Timer1.
Instead, the high byte of Timer1 is updated with the
contents of TMR1H when a write occurs to TMR1L.
This allows all 16 bits of Timer1 to be updated at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
11.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN of the T1CON register. The
oscillator is a low-power circuit rated for 32 kHz crystals.
It will continue to run during all power-managed modes.
The circuit for a typical LP oscillator is shown in
Figure 11-3. Table 11-1 shows the capacitor selection for
the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 11-3: EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
TABLE 11-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
11.3.1 USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> of the OSCCON register, to ‘01’, the
device switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit of the OSCCON register is cleared and a
SLEEP instruction is executed, the device enters
SEC_IDLE mode. Additional details are available in
Section 19.0 “Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN of
the T1CON register, is set. This can be used to determine
the controller’s current clocking mode. It can also
indicate which clock source is currently being used by
the Fail-Safe Clock Monitor. If the Clock Monitor is
enabled and the Timer1 oscillator fails while providing
the clock, polling the T1RUN bit will indicate whether
the clock is being provided by the Timer1 oscillator or
another source.
Note: See the Notes with Table 11-1 for additional
information about capacitor selection.
C1
C2
XTAL
T1OSI
T1OSO
32.768 kHz
27 pF
27 pF
PIC® MCU
Osc Type Freq C1 C2
LP 32 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values only as
a starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
PIC18F/LF1XK50
DS41350E-page 108 Preliminary 2010 Microchip Technology Inc.
11.3.2 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 11-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator
(such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 11-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 11-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
11.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in the TMR1IF interrupt flag bit of the
PIR1 register. This interrupt can be enabled or disabled
by setting or clearing the TMR1IE Interrupt Enable bit
of the PIE1 register.
11.5 Resetting Timer1 Using the CCP
Special Event Trigger
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Compare mode
(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will
reset Timer1. The trigger from CCP2 will also start an
A/D conversion if the A/D module is enabled (see
Section 14.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The Special Event Triggers from the
CCP2 module will not set the TMR1IF
interrupt flag bit of the PIR1 register.
2010 Microchip Technology Inc. Preliminary DS41350E-page 109
PIC18F/LF1XK50
11.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 11.3 “Timer1 Oscillator”
above) gives users the option to include RTC functionality
to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 11-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented on overflows of the less significant
counters.
Since the register pair is 16 bits wide, a 32.768 kHz
clock source will take 2 seconds to count up to overflow.
To force the overflow at the required one-second
intervals, it is necessary to preload it; the simplest
method is to set the MSb of TMR1H with a BSF instruction.
Note that the TMR1L register is never preloaded
or altered; doing so may introduce cumulative error
over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
EXAMPLE 11-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done
PIC18F/LF1XK50
DS41350E-page 110 Preliminary 2010 Microchip Technology Inc.
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
TMR1L Timer1 Register, Low Byte 286
TMR1H Timer1 Register, High Byte 286
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 111
PIC18F/LF1XK50
12.0 TIMER2 MODULE
The Timer2 module timer incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
(Register 12-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON of the
T2CON register, to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 12-1.
12.1 Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the prescaler control bits, T2CKPS<1:0> of the T2CON
register. The value of TMR2 is compared to that of the
period register, PR2, on each clock cycle. When the
two values match, the comparator generates a match
signal as the timer output. This signal also resets the
value of TMR2 to 00h on the next cycle and drives the
output counter/postscaler (see Section 12.2 “Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC18F/LF1XK50
DS41350E-page 112 Preliminary 2010 Microchip Technology Inc.
12.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) provides
the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF of the PIR1 register. The
interrupt is enabled by setting the TMR2 Match Interrupt
Enable bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> of the T2CON register.
12.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Additional
information is provided in Section 14.0 “Master
Synchronous Serial Port (MSSP) Module”.
FIGURE 12-1: TIMER2 BLOCK DIAGRAM
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
TMR2 Timer2 Register 286
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 286
PR2 Timer2 Period Register 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS<3:0>
T2CKPS<1:0>
Set TMR2IF
Internal Data Bus
8
Reset
TMR2/PR2
8 8
(to PWM or MSSP)
Match
2010 Microchip Technology Inc. Preliminary DS41350E-page 113
PIC18F/LF1XK50
13.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger
A simplified block diagram of the Timer3 module is
shown in Figure 13-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 13-2.
The Timer3 module is controlled through the T3CON
register (Register 13-1). It also selects the clock source
options for the CCP modules (see Section 14.1.1
“CCP Module and Timer Resources” for more
information).
REGISTER 13-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6 Unimplemented: Read as ‘0’
bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T3CCP1: Timer3 and Timer1 to CCP1 Enable bits
1 = Timer3 is the clock source for compare/capture of ECCP1
0 = Timer1 is the clock source for compare/capture of ECCP1
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
PIC18F/LF1XK50
DS41350E-page 114 Preliminary 2010 Microchip Technology Inc.
13.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS of the T3CON register. When TMR3CS is
cleared (= 0), Timer3 increments on every internal
instruction cycle (FOSC/4). When the bit is set, Timer3
increments on every rising edge of the Timer1 external
clock input or the Timer1 oscillator, if enabled.
As with Timer1, the digital circuitry associated with the
RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled
when the Timer1 oscillator is enabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 13-1: TIMER3 BLOCK DIAGRAM
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L
Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1 Special Event Trigger
CCP1 Select from T3CON<3>
Clear TMR3
Timer1 Clock Input
2010 Microchip Technology Inc. Preliminary DS41350E-page 115
PIC18F/LF1XK50
FIGURE 13-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
13.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 13-2). When the RD16 control bit of the
T3CON register is set, the address for TMR3H is
mapped to a buffer register for the high byte of Timer3.
A read from TMR3L will load the contents of the high
byte of Timer3 into the Timer3 High Byte Buffer register.
This provides the user with the ability to accurately read
all 16 bits of Timer1 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
13.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN bit of the T1CON register. To use
it as the Timer3 clock source, the TMR3CS bit must
also be set. As previously noted, this also configures
Timer3 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 11.0
“Timer1 Module”.
13.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF of the PIR2
register. This interrupt can be enabled or disabled by
setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE of the PIE2 register.
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T13CKI/T1OSI
T1OSO
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1 Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 Clock Input
CCP1 Select from T3CON<3>
Clear TMR3
PIC18F/LF1XK50
DS41350E-page 116 Preliminary 2010 Microchip Technology Inc.
13.5 Resetting Timer3 Using the CCP
Special Event Trigger
If CCP1 module is configured to use Timer3 and to generate
a Special Event Trigger in Compare mode
(CCP1M<3:0>), this signal will reset Timer3. It will also
start an A/D conversion if the A/D module is enabled
(see Section 17.2.8 “Special Event Trigger” for more
information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF CCP2IF 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE CCP2IE 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP CCP2IP 288
TMR3L Timer3 Register, Low Byte 287
TMR3H Timer3 Register, High Byte 287
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 117
PIC18F/LF1XK50
14.0 ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
PIC18F/LF1XK50 devices have one ECCP
(Capture/Compare/PWM) module. The module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
CCP1 is implemented as a standard CCP module with
enhanced PWM capabilities. These include:
• Provision for 2 or 4 output channels
• Output steering
• Programmable polarity
• Programmable dead-band control
• Automatic shutdown and restart.
The enhanced features are discussed in detail in
Section 14.4 “PWM (Enhanced Mode)”.
REGISTER 14-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 = Single output: P1A, P1B, P1C and P1D controlled by steering (See Section 14.4.7 “Pulse Steering
Mode”).
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in
CCPR1L.
bit 3-0 CCP1M<3:0>: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, start A/D conversion, sets
CC1IF bit)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
PIC18F/LF1XK50
DS41350E-page 118 Preliminary 2010 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has two additional registers
associated with Enhanced PWM operation and
auto-shutdown features. They are:
• PWM1CON (Dead-band delay)
• PSTRCON (output steering)
14.1 ECCP Outputs and Configuration
The enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC. The outputs that
are active depend on the CCP operating mode
selected. The pin assignments are summarized in
Table 14-2.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the P1M<1:0>
and CCP1M<3:0> bits. The appropriate TRISC
direction bits for the port pins must also be set as
outputs.
14.1.1 CCP MODULE AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 14-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 13-1). The interactions
between the two modules are summarized in
Figure 14-1. In Asynchronous Counter mode, the
capture operation will not work reliably.
CCP/ECCP Mode Timer Resource
Capture Timer1 or Timer3
Compare Timer1 or Timer3
PWM Timer2
2010 Microchip Technology Inc. Preliminary DS41350E-page 119
PIC18F/LF1XK50
14.2 Capture Mode
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCP1 pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP1M<3:0> of the CCP1CON register. When a capture
is made, the interrupt request flag bit, CCP1IF, is
set; it must be cleared by software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value is overwritten by the new captured
value.
14.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCP1 pin should be
configured as an input by setting the corresponding
TRIS direction bit.
14.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 14.1.1 “CCP Module and Timer
Resources”).
14.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit clear to avoid false interrupts.
The interrupt flag bit, CCP1IF, should also be
cleared following any such change in operating mode.
14.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP1M<3:0>). Whenever the
CCP module is turned off or Capture mode is disabled,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 14-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 pin
Prescaler
1, 4, 16
and
Edge Detect
TMR1
Enable
T3CCP1
T3CCP1
TMR3H TMR3L
4
4
PIC18F/LF1XK50
DS41350E-page 120 Preliminary 2010 Microchip Technology Inc.
14.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP1M<3:0>). At the same time, the interrupt
flag bit, CCP1IF, is set.
14.3.1 CCP PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
14.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
14.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
Only the CCP1IF interrupt flag is affected.
14.3.4 SPECIAL EVENT TRIGGER
The CCP module is equipped with a Special Event Trigger.
This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP1M<3:0> = 1011).
The Special Event Trigger resets the timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPR1 registers to
serve as a programmable period register for either timer.
The Special Event Trigger can also start an A/D conversion.
In order to do this, the A/D converter must already
be enabled.
FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch (depending
on device configuration) to the default
low level. This is not the PORTC I/O data
latch.
TMR1H TMR1L
TMR3H TMR3L
CCPR1H CCPR1L
Comparator
T3CCP1
Set CCP1IF
1
0
S Q
R
Output
Logic
Special Event Trigger
CCP1 pin
TRIS
CCP1CON<3:0>
4 Output Enable
(Timer1/Timer3 Reset, A/D Trigger)
Compare
Match
2010 Microchip Technology Inc. Preliminary DS41350E-page 121
PIC18F/LF1XK50
14.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Table 14-1 shows the pin assignments for each
Enhanced PWM mode.
Figure 14-3 shows an example of a simplified block
diagram of the Enhanced PWM module.
FIGURE 14-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
TABLE 14-2: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
Note: To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
R Q
S
Duty Cycle Registers
DC1B<1:0>
Clear Timer2,
toggle PWM pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
TRIS
CCP1/P1A
TRIS
P1B
TRIS
P1C
TRIS
P1D
Output
Controller
P1M<1:0>
2
CCP1M<3:0>
4
PWM1CON
CCP1/P1A
P1B
P1C
P1D
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: Outputs are enabled by pulse steering in Single mode. See Register 14-4.
PIC18F/LF1XK50
DS41350E-page 122 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-4: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
0
Period
00
10
01
11
Signal
PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 14.4.6 “Programmable Dead-Band Delay
mode”).
2010 Microchip Technology Inc. Preliminary DS41350E-page 123
PIC18F/LF1XK50
FIGURE 14-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
Signal
PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 14.4.6 “Programmable Dead-Band Delay
mode”).
PIC18F/LF1XK50
DS41350E-page 124 Preliminary 2010 Microchip Technology Inc.
14.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
Figure 14-6). This mode can be used for Half-Bridge
applications, as shown in Figure 14-7, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWM1CON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 14.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 14-6: EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FIGURE 14-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
Load
+
-
+
-
FET
Driver
FET
Driver
V+
Load
FET
Driver
FET
Driver
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
2010 Microchip Technology Inc. Preliminary DS41350E-page 125
PIC18F/LF1XK50
14.4.2 FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 14-8.
In the Forward mode, pin CCP1/P1A is driven to its
active state, pin P1D is modulated, while P1B and P1C
will be driven to their inactive state as shown in
Figure 14-9.
In the Reverse mode, P1C is driven to its active state,
pin P1B is modulated, while P1A and P1D will be driven
to their inactive state as shown Figure 14-9.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORT data latches. The associated TRIS bits must
be cleared to configure the P1A, P1B, P1C and P1D
pins as outputs.
FIGURE 14-8: EXAMPLE OF FULL-BRIDGE APPLICATION
P1A
P1C
FET
Driver
FET
Driver
V+
VLoad
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
QC
PIC18F/LF1XK50
DS41350E-page 126 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forward Mode
(1)
Period
Pulse Width
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as active-high.
2010 Microchip Technology Inc. Preliminary DS41350E-page 127
PIC18F/LF1XK50
14.4.2.1 Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the P1M1 bit in the CCP1CON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction control bit, the module will change to the new
direction on the next PWM cycle.
A direction change is initiated in software by changing
the P1M1 bit of the CCP1CON register. The following
sequence occurs prior to the end of the current PWM
period:
• The modulated outputs (P1B and P1D) are placed
in their inactive state.
• The associated unmodulated outputs (P1A and
P1C) are switched to drive in the opposite
direction.
• PWM modulation resumes at the beginning of the
next period.
See Figure 14-10 for an illustration of this sequence.
The Full-Bridge mode does not provide dead-band
delay. As one output is modulated at a time, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
Figure 14-11 shows an example of the PWM direction
changing from forward to reverse, at a near 100% duty
cycle. In this example, at time t1, the output P1A and
P1D become inactive, while output P1C becomes
active. Since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 14-8) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 14-10: EXAMPLE OF PWM DIRECTION CHANGE
Pulse Width
Period(1)
Signal
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
Period
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
Pulse Width
PIC18F/LF1XK50
DS41350E-page 128 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
14.4.3 START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCP1M<1:0> bits of the CCP1CON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output pins
(P1A/P1C and P1B/P1D). The PWM output polarities
must be selected before the PWM pin output drivers are
enabled. Changing the polarity configuration while the
PWM pin output drivers are enable is not recommended
since it may result in damage to the application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF bit of the PIR1 register
being set as the second PWM period begins.
Forward Period Reverse Period
P1A
TON
TOFF
T = TOFF – TON
P1B
P1C
P1D
External Switch D
Potential
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn on delay of power switch QC and its driver.
3: TOFF is the turn off delay of power switch QD and its driver.
External Switch C
t1
PW
PW
Note: When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external circuits
must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
2010 Microchip Technology Inc. Preliminary DS41350E-page 129
PIC18F/LF1XK50
14.4.4 ENHANCED PWM
AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPAS<2:0> bits of the ECCPAS register. A shutdown
event may be generated by:
• A logic ‘0’ on the INT0 pin
• A logic ‘1’ on a comparator (Cx) output
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 14.4.5 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCPAS register. Each pin pair may
be placed into one of three states:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
REGISTER 14-2: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits
000 = Auto-Shutdown is disabled
001 = Comparator C1OUT output is high
010 = Comparator C2OUT output is high
011 = Either Comparator C1OUT or C2OUT is high
100 = VIL on INT0 pin
101 = VIL on INT0 pin or Comparator C1OUT output is high
110 = VIL on INT0 pin or Comparator C2OUT output is high
111 = VIL on INT0 pin or Comparator C1OUT or Comparator C2OUT is high
bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits
00 = Drive pins P1A and P1C to ‘0’
01 = Drive pins P1A and P1C to ‘1’
1x = Pins P1A and P1C tri-state
bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits
00 = Drive pins P1B and P1D to ‘0’
01 = Drive pins P1B and P1D to ‘1’
1x = Pins P1B and P1D tri-state
PIC18F/LF1XK50
DS41350E-page 130 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
Note 1: The auto-shutdown condition is a
level-based signal, not an edge-based
signal. As long as the level is present, the
auto-shutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
4: Prior to an auto-shutdown event caused
by a comparator output or INT pin event,
a software shutdown can be triggered in
firmware by setting the CCPxASE bit to a
‘1’. The auto-restart feature tracks the
active status of a shutdown caused by a
comparator output or INT pin event only
so, if it is enabled at this time. It will immediately
clear this bit and restart the ECCP
module at the beginning of the next PWM
period.
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
Normal PWM
Start of
PWM Period
ECCPASE
Cleared by
Firmware
PWM Period
2010 Microchip Technology Inc. Preliminary DS41350E-page 131
PIC18F/LF1XK50
14.4.5 AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically
restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 14-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
Normal PWM
Start of
PWM Period
PWM Period
PIC18F/LF1XK50
DS41350E-page 132 Preliminary 2010 Microchip Technology Inc.
14.4.6 PROGRAMMABLE DEAD-BAND
DELAY MODE
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current
(shoot-through current) will flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In Half-Bridge mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 14-14 for
illustration. The lower seven bits of the associated
PWM1CON register (Register 14-3) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 14-14: EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FIGURE 14-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
V+
VLoad
+
V-
+
VStandard
Half-Bridge Circuit (“Push-Pull”)
2010 Microchip Technology Inc. Preliminary DS41350E-page 133
PIC18F/LF1XK50
REGISTER 14-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
PIC18F/LF1XK50
DS41350E-page 134 Preliminary 2010 Microchip Technology Inc.
14.4.7 PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once the Single Output mode is selected
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR bits of the
PSTRCON register, as shown in Table 14-2.
While the PWM Steering mode is active, CCP1M<1:0>
bits of the CCP1CON register select the PWM output
polarity for the P1 pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 14.4.4
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
Note: The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
REGISTER 14-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — STRSYNC STRD STRC STRB STRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
bit 2 STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
bit 1 STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
bit 0 STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
2010 Microchip Technology Inc. Preliminary DS41350E-page 135
PIC18F/LF1XK50
FIGURE 14-16: SIMPLIFIED STEERING
BLOCK DIAGRAM
1
0 TRIS
P1A pin
PORT Data
P1A Signal
STRA
1
0
TRIS
P1B pin
PORT Data
STRB
1
0
TRIS
P1C pin
PORT Data
STRC
1
0
TRIS
P1D pin
PORT Data
STRD
Note 1: Port outputs are configured as shown when
the CCP1CON register bits P1M<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
CCP1M1
CCP1M0
CCP1M1
CCP1M0
PIC18F/LF1XK50
DS41350E-page 136 Preliminary 2010 Microchip Technology Inc.
14.4.7.1 Steering Synchronization
The STRSYNC bit of the PSTRCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRCON register. In this case, the
output signal at the P1 pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 14-17 and 14-18 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
FIGURE 14-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
FIGURE 14-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRSYNC = 1)
PWM
P1n = PWM
STRn
P1 PORT Data
PWM Period
PORT Data
PWM
PORT Data
P1n = PWM
STRn
P1 PORT Data
2010 Microchip Technology Inc. Preliminary DS41350E-page 137
PIC18F/LF1XK50
14.4.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will continue
to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
14.4.8.1 Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the RC_RUN Power-Managed
mode and the OSCFIF bit of the PIR2 register will be
set. The ECCP will then be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See the previous section for additional details.
14.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F/LF1XK50
DS41350E-page 138 Preliminary 2010 Microchip Technology Inc.
TABLE 14-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
RCON IPEN SBOREN — RI TO PD POR BOR 284
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TMR1L Timer1 Register, Low Byte 286
TMR1H Timer1 Register, High Byte 286
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
TMR2 Timer2 Register 286
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 286
PR2 Timer2 Period Register 286
TMR3L Timer3 Register, Low Byte 287
TMR3H Timer3 Register, High Byte 287
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
CCPR1L Capture/Compare/PWM Register 1, Low Byte 287
CCPR1H Capture/Compare/PWM Register 1, High Byte 287
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 287
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 287
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
2010 Microchip Technology Inc. Preliminary DS41350E-page 139
PIC18F/LF1XK50
15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
15.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
15.2 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out – SDO
• Serial Data In – SDI
• Serial Clock – SCK
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 15-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 15-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR Reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
Prescaler TOSC
4, 16, 64
2
Edge
Select
2
4
TRIS bit
SDO
SSPBUF Reg
SDI/SDA
SS
SCK/SCL
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DS41350E-page 140 Preliminary 2010 Microchip Technology Inc.
15.2.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• SSPCON1 – Control Register
• SSPSTAT – STATUS register
• SSPBUF – Serial Receive/Transmit Buffer
• SSPSR – Shift Register (Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 register
is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
REGISTER 15-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.
2010 Microchip Technology Inc. Preliminary DS41350E-page 141
PIC18F/LF1XK50
REGISTER 15-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared by software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
PIC18F/LF1XK50
DS41350E-page 142 Preliminary 2010 Microchip Technology Inc.
15.2.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF of the
SSPSTAT register, and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must clear the WCOL bit to allow the following write(s)
to the SSPBUF register to complete successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur. Example 15-1
shows the loading of the SSPBUF (SSPSR) for data
transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP STATUS register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
2010 Microchip Technology Inc. Preliminary DS41350E-page 143
PIC18F/LF1XK50
15.2.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
15.2.4 TYPICAL CONNECTION
Figure 15-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed
clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 15-2: TYPICAL SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI Master SSPM<3:0> = 00xx
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDI
SDO
Processor 2
SCK
SPI Slave SSPM<3:0> = 010x
Serial Clock
SS
Slave Select
General I/O
(optional)
PIC18F/LF1XK50
DS41350E-page 144 Preliminary 2010 Microchip Technology Inc.
15.2.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register.
This then, would give waveforms for SPI
communication as shown in Figure 15-3, Figure 15-5
and Figure 15-6, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 64 MHz) of
16.00 Mbps.
Figure 15-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 15-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
bit 0
2010 Microchip Technology Inc. Preliminary DS41350E-page 145
PIC18F/LF1XK50
15.2.6 SLAVE MODE
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last bit
is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
15.2.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100). When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
is no longer driven, even if in the middle of a transmitted
byte and becomes a floating output. External
pull-up/pull-down resistors may be desirable depending
on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
FIGURE 15-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is
set to VDD.
2: When the SPI is used in Slave mode with
CKE set the SS pin control must also be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
PIC18F/LF1XK50
DS41350E-page 146 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
2010 Microchip Technology Inc. Preliminary DS41350E-page 147
PIC18F/LF1XK50
15.2.8 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In all Idle modes, a clock is provided to the peripherals.
That clock could be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 19.0 “Power-Managed
Modes” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in slave mode
• from Idle, in slave or master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/
reception will remain in that state until the devices
wakes. After the device returns to RUN mode, the module
will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
15.2.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.2.10 BUS MODE COMPATIBILITY
Table 15-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 15-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
SSPBUF SSP Receive Buffer/Transmit Register 286
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
SSPSTAT SMP CKE D/A P S R/W UA BF 286
Legend: Shaded cells are not used by the MSSP in SPI mode.
PIC18F/LF1XK50
DS41350E-page 148 Preliminary 2010 Microchip Technology Inc.
15.3 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock – SCL
• Serial data – SDA
FIGURE 15-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
15.3.1 REGISTERS
The MSSP module has seven registers for I2C
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
When the MSSP is configured in Master mode, the
SSPADD register acts as the Baud Rate Generator
reload value. When the MSSP is configured for I2C
slave mode the SSPADD register holds the slave
device address. The MSSP can be configured to
respond to a range of addresses by qualifying selected
bits of the address register with the SSPMSK register.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Note: The user must configure these pins as
inputs with the corresponding TRIS bits.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCK/SCL
SDI/SDA
Shift
Clock
MSb LSb
SSPMSK Reg
2010 Microchip Technology Inc. Preliminary DS41350E-page 149
PIC18F/LF1XK50
REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P(1) S(1) R/W(2, 3) UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received was an address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit (I2C mode only)(2, 3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the Master mode is active.
PIC18F/LF1XK50
DS41350E-page 150 Preliminary 2010 Microchip Technology Inc.
REGISTER 15-4: SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission
to be started (must be cleared by software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared by
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared
by software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
When enabled, the SDA and SCL pins must be properly configured as inputs.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
2010 Microchip Technology Inc. Preliminary DS41350E-page 151
PIC18F/LF1XK50
REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT(2) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Generate interrupt when a general call address 0x00 or 00h is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(2)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)(1)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)(1)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not
be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
PIC18F/LF1XK50
DS41350E-page 152 Preliminary 2010 Microchip Technology Inc.
15.3.2 OPERATION
The MSSP module functions are enabled by setting
SSPEN bit of the SSPCON1 register.
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits of the SSPCON1
register allow one of the following I2C modes to be
selected:
• I2C Master mode, clock = (FOSC/(4*(SSPADD + 1))
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRIS bits
15.3.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured
as inputs. The MSSP module will override the
input state with the output data when required
(slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse and load the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF bit of the SSPSTAT register,
is set before the transfer is received.
• The overflow bit, SSPOV bit of the SSPCON1
register, is set before the transfer is received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. The BF bit is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in Section 27.0 “Electrical
Specifications”.
15.3.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF of the PIR1 register,
is set (interrupt is generated, if enabled) on
the falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W of the SSPSTAT register must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
2. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
3. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set). If the address
matches then the SCL is held until the next step.
Otherwise the SCL line is not held.
5. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
6. Update the SSPADD register with the first (high)
byte of address. (This will clear bit UA and
release a held SCL line.)
7. Receive Repeated Start condition.
8. Receive first (high) byte of address with R/W bit
set (bits SSPIF, BF, R/W are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
10. Load SSPBUF with byte the slave is to transmit,
sets the BF bit.
11. Set the CKP bit to release SCL.
Note: To ensure proper operation of the module,
pull-up resistors must be provided externally
to the SCL and SDA pins.
2010 Microchip Technology Inc. Preliminary DS41350E-page 153
PIC18F/LF1XK50
15.3.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1
register is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF of the PIR1 register, must be
cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting the
CKP bit of the SSPCON1 register. See Section 15.3.4
“Clock Stretching” for more detail.
15.3.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin SCK/SCL is held low
regardless of SEN (see Section 15.3.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin
SCK/SCL should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 15-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is complete.
In this case, when the ACK is latched by the slave, the
slave logic is reset (resets SSPSTAT register) and the
slave monitors for another occurrence of the Start bit. If
the SDA line was low (ACK), the next transmit data must
be loaded into the SSPBUF register. Again, pin
SCK/SCL must be released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
PIC18F/LF1XK50
DS41350E-page 154 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared by software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ when SEN = 0)
2010 Microchip Technology Inc. Preliminary DS41350E-page 155
PIC18F/LF1XK50
FIGURE 15-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is written by software
Cleared by software
From SSPIF ISR
Data in
sampled
S
ACK
R/W = 0 Transmitting Data
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSPBUF is written by software
Cleared by software
From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CKP is set by software CKP is set by software
SCL held low
while CPU
responds to SSPIF
SSPBUF is read by software
Bus master
terminates software
PIC18F/LF1XK50
DS41350E-page 156 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
D2
6
(PIR1<3>)
Cleared by software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared by software Cleared by software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
2010 Microchip Technology Inc. Preliminary DS41350E-page 157
PIC18F/LF1XK50
FIGURE 15-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8
R/W=1
ACK ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
sends Stop
condition
A9
6
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
Cleared in software
Completion of
clears BF flag
CKP
CKP is set in software, initiates transmission
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
Bus Master
sends Restarts
condition
Dummy read of SSPBUF
to clear BF flag
PIC18F/LF1XK50
DS41350E-page 158 Preliminary 2010 Microchip Technology Inc.
15.3.3.4 SSP Mask Register
An SSP Mask (SSPMSK) register is available in I2C
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
This register must be initiated prior to setting
SSPM<3:0> bits to select the I2C Slave mode (7-bit or
10-bit address).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
REGISTER 15-6: SSPMSK: SSP MASK REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(1)
I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
Note 1: The MSK0 bit is used only in 10-bit slave mode. In all other modes, this bit has no effect.
2010 Microchip Technology Inc. Preliminary DS41350E-page 159
PIC18F/LF1XK50
REGISTER 15-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most significant address byte:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care.” Bit pattern
sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”
10-Bit Slave mode — Least significant address byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1 ADD<6:0>: 7-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”
PIC18F/LF1XK50
DS41350E-page 160 Preliminary 2010 Microchip Technology Inc.
15.3.4 CLOCK STRETCHING
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit of the SSPCON2 register allows clock
stretching to be enabled during receives. Setting SEN
will cause the SCL pin to be held low at the end of
each data receive sequence.
15.3.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit of the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another data transfer
sequence. This will prevent buffer overruns from
occurring (see Figure 15-13).
15.3.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
15.3.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock. This occurs regardless of the state of the
SEN bit.
The user’s ISR must set the CKP bit before transmission
is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another data transfer sequence (see
Figure 15-9).
15.3.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled
during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is automatic with the hardware
clearing CKP, as in 7-bit Slave Transmit mode
(see Figure 15-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge
of the ninth clock, the CKP bit will not be
cleared and clock stretching will not
occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit.
2010 Microchip Technology Inc. Preliminary DS41350E-page 161
PIC18F/LF1XK50
15.3.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 15-12).
FIGURE 15-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX DX – 1
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON1
CKP
Master device
deasserts clock
Master device
asserts clock
PIC18F/LF1XK50
DS41350E-page 162 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-13: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared by software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
2010 Microchip Technology Inc. Preliminary DS41350E-page 163
PIC18F/LF1XK50
FIGURE 15-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
D2
6
(PIR1<3>)
Cleared by software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared by software Cleared by software
SSPOV (SSPCON1<6>)
CKP written to ‘1’
Note: An update of the SSPADD register before
the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
by software
Clock is held low until
update of SSPADD has
taken place
of ninth clock of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because ACK = 1
PIC18F/LF1XK50
DS41350E-page 164 Preliminary 2010 Microchip Technology Inc.
15.3.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
GCEN bit of the SSPCON2 is set. Following a Start bit
detect, 8 bits are shifted into the SSPSR and the
address is compared against the SSPADD. It is also
compared to the general call address and fixed in
hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit of the SSPSTAT register is set. If the general call
address is sampled when the GCEN bit is set, while the
slave is configured in 10-bit Address mode, then the
second half of the address is not necessary, the UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 15-15).
FIGURE 15-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared by software
SSPBUF is read
R/W = 0
General Call Address ACK
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
‘0’
‘1’
2010 Microchip Technology Inc. Preliminary DS41350E-page 165
PIC18F/LF1XK50
15.3.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions.
The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN
Rate
Generator
SSPM<3:0>
Start bit Detect
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DS41350E-page 166 Preliminary 2010 Microchip Technology Inc.
15.3.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted,
an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains
the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning
and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 15.3.7 “Baud
Rate” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the PEN bit of the SSPCON2 register.
12. Interrupt is generated once the Stop condition is
complete.
2010 Microchip Technology Inc. Preliminary DS41350E-page 167
PIC18F/LF1XK50
15.3.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Figure 15-17). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting.
Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 15-1:
FIGURE 15-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 15-3: I2C™ CLOCK RATE W/BRG
FSCL FOSC
SSPADD + 14 = ----------------------------------------------
SSPM<3:0>
CLKOUT BRG Down Counter FOSC/2
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
FOSC FCY BRG Value FSCL
(2 Rollovers of BRG)
48 MHz 12 MHz 0Bh 1 MHz(1)
48 MHz 12 MHz 1Dh 400 kHz
48 MHz 12 MHz 77h 100 kHz
40 MHz 10 MHz 18h 400 kHz(1)
40 MHz 10 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 63h 100 kHz
16 MHz 4 MHz 09h 400 kHz(1)
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 02h 333 kHz(1)
4 MHz 1 MHz 09h 100 kHz
4 MHz 1 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
PIC18F/LF1XK50
DS41350E-page 168 Preliminary 2010 Microchip Technology Inc.
15.3.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 15-18).
FIGURE 15-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX DX – 1
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
2010 Microchip Technology Inc. Preliminary DS41350E-page 169
PIC18F/LF1XK50
15.3.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Generator
is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator
times out (TBRG), the SEN bit of the SSPCON2 register
will be automatically cleared by hardware; the Baud
Rate Generator is suspended, leaving the SDA line
held low and the Start condition is complete.
15.3.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 15-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sampled
low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I2C module is reset into its Idle
state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1,
SCL = 1 At completion of Start bit,
TBRG Write to SSPBUF occurs here
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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DS41350E-page 170 Preliminary 2010 Microchip Technology Inc.
15.3.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
I2C logic module is in the Idle state. When the RSEN bit
is set, the SCL pin is asserted low. When the SCL pin
is sampled low, the Baud Rate Generator is loaded and
begins counting. The SDA pin is released (brought
high) for one Baud Rate Generator count (TBRG). When
the Baud Rate Generator times out, if SDA is sampled
high, the SCL pin will be deasserted (brought high).
When SCL is sampled high, the Baud Rate Generator
is reloaded and begins counting. SDA and SCL must
be sampled high for one TBRG. This action is then followed
by assertion of the SDA pin (SDA = 0) for one
TBRG while SCL is high. Following this, the RSEN bit of
the SSPCON2 register will be automatically cleared
and the Baud Rate Generator will not be reloaded,
leaving the SDA pin held low. As soon as a Start condition
is detected on the SDA and SCL pins, the S bit of
the SSPSTAT register will be set. The SSPIF bit will not
be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
15.3.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
on falling edge of ninth clock, Write to SSPBUF occurs here
end of Xmit
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change).
SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
RSEN bit set by hardware
2010 Microchip Technology Inc. Preliminary DS41350E-page 171
PIC18F/LF1XK50
15.3.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next transmission.
Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter SP106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time specification
parameter SP107). When the SCL pin is
released high, it is held that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some hold time after the next falling edge of SCL. After
the eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA. This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received properly.
The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 15-21).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit of the
SSPCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
15.3.10.1 BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
15.3.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
WCOL must be cleared by software before the next
transmission.
15.3.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowledge
when it has recognized its address (including a
general call), or when the slave has properly received
its data.
15.3.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the contents
of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
15.3.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.3.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
15.3.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
PIC18F/LF1XK50
DS41350E-page 172 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Cleared by software service routine
SSPBUF is written by software
from SSP interrupt
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared by software
SSPBUF written
PEN
R/W
Cleared by software
2010 Microchip Technology Inc. Preliminary DS41350E-page 173
PIC18F/LF1XK50
FIGURE 15-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
S
SDA A7 A6 A5 A4 A3 A2 A1
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
Bus master
terminates
transfer
ACK
Receiving Data from Slave Receiving Data from Slave
ACK D7 D6 D5 D4 D3 D2 D1 D0
Transmit Address to Slave R/W = 0
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here,
ACK from Slave
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared by software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared by software Cleared by software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknowledge
sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start condition
Cleared by software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
RCEN
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
RCEN cleared
automatically
ACK from Master
SDA = ACKDT = 0
RCEN cleared
automatically
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DS41350E-page 174 Preliminary 2010 Microchip Technology Inc.
15.3.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate
an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 15-23).
15.3.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
15.3.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 15-24).
15.3.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 15-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
SSPIF set at
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SSPIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
2010 Microchip Technology Inc. Preliminary DS41350E-page 175
PIC18F/LF1XK50
15.3.14 SLEEP OPERATION
While in Sleep mode, the I2C Slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
15.3.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.3.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
15.3.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration.
When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 15-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination
of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 15-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
PIC18F/LF1XK50
DS41350E-page 176 Preliminary 2010 Microchip Technology Inc.
15.3.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 15-26).
b) SCL is sampled low before SDA is asserted low
(Figure 15-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 15-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 15-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following
the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF and BCLIF are
cleared by software
Set BCLIF,
Start condition. Set BCLIF.
2010 Microchip Technology Inc. Preliminary DS41350E-page 177
PIC18F/LF1XK50
FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 15-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN
bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
by software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’ ‘0’
‘0’ ‘0’
SDA
SCL
SEN
Set S
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
set SSPIF by software
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPIF
‘0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable START
sequence if SDA = 1, SCL = 1
PIC18F/LF1XK50
DS41350E-page 178 Preliminary 2010 Microchip Technology Inc.
15.3.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to 0. The SCL pin is then deasserted and when
sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 15-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 15-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 15-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 15-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared by software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
by software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 179
PIC18F/LF1XK50
15.3.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 15-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 15-32).
FIGURE 15-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 15-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
PIC18F/LF1XK50
DS41350E-page 180 Preliminary 2010 Microchip Technology Inc.
TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on
page
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master
Mode.
286
SSPBUF SSP Receive Buffer/Transmit Register 286
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 286
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 288
SSPSTAT SMP CKE D/A P S R/W UA BF 286
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by I2C™.
2010 Microchip Technology Inc. Preliminary DS41350E-page 181
PIC18F/LF1XK50
16.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
FIGURE 16-1: EUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8) 0
TX9
TRMT SPEN
TX/CK pin
Pin Buffer
and Control
8
SPBRGH SPBRG
BRG16
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
Baud Rate Generator
• • •
PIC18F/LF1XK50
DS41350E-page 182 Preliminary 2010 Microchip Technology Inc.
FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 16-1,
Register 16-2 and Register 16-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RX/DT and TX/CK pins should
be set to ‘1’. The EUSART control will automatically
reconfigure the pin from input to output, as needed.
RX/DT pin
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR
FERR
MSb RSR Register LSb
RX9D RCREG Register
FIFO
RCIF Interrupt
RCIE
Data Bus
8
Stop (8) 7 1 0 START
RX9
• • •
SPBRGH SPBRG
BRG16
RCIDL
FOSC ÷ n
+ 1 Multiplier x4 x16 x64 n
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
Baud Rate Generator
2010 Microchip Technology Inc. Preliminary DS41350E-page 183
PIC18F/LF1XK50
16.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 16-5
for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
16.1.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
16.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
16.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
16.1.1.3 Transmit Data Polarity
The polarity of the transmit data can be controlled with
the CKTXP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true transmit
idle and data bits. Setting the CKTXP bit to ‘1’ will invert
the transmit data resulting in low true idle and data bits.
The CKTXP bit controls transmit data polarity only in
Asynchronous mode. In Synchronous mode the
CKTXP bit has a different function.
Note 1: When the SPEN bit is set the RX/DT I/O
pin is automatically configured as an input,
regardless of the state of the corresponding
TRIS bit and whether or not the
EUSART receiver is enabled. The RX/DT
pin data can be read via a normal PORT
read but PORT latch data output is precluded.
2: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
PIC18F/LF1XK50
DS41350E-page 184 Preliminary 2010 Microchip Technology Inc.
16.1.1.4 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
16.1.1.5 TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
16.1.1.6 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSART will shift 9 bits out for each character transmitted.
The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 16.1.2.8 “Address
Detection” for more information on the Address mode.
16.1.1.7 Asynchronous Transmission Set-up:
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 16.3 “EUSART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9 control
bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
4. Set the CKTXP control bit if inverted transmit
data polarity is desired.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
2010 Microchip Technology Inc. Preliminary DS41350E-page 185
PIC18F/LF1XK50
FIGURE 16-3: ASYNCHRONOUS TRANSMISSION
FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
TXREG EUSART Transmit Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Word 1
Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RB7/TX/CK
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
pin
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
RB7/TX/CK
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
PIC18F/LF1XK50
DS41350E-page 186 Preliminary 2010 Microchip Technology Inc.
16.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode would typically be used in
RS-232 systems. The receiver block diagram is shown
in Figure 16-2. The data is received on the RX/DT pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter operating at 16
times the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
16.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The RX/DT I/O
pin must be configured as an input by setting the
corresponding TRIS control bit. If the RX/DT pin is
shared with an analog peripheral the analog I/O function
must be disabled by clearing the corresponding ANSEL
bit.
16.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 16.1.2.5 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
16.1.2.3 Receive Data Polarity
The polarity of the receive data can be controlled with
the DTRXP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true receive idle
and data bits. Setting the DTRXP bit to ‘1’ will invert the
receive data resulting in low true idle and data bits. The
DTRXP bit controls receive data polarity only in
Asynchronous mode. In synchronous mode the
DTRXP bit has a different function.
Note: When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or
not the EUSART transmitter is enabled.
The PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 16.1.2.6
“Receive Overrun Error” for more
information on overrun errors.
2010 Microchip Technology Inc. Preliminary DS41350E-page 187
PIC18F/LF1XK50
16.1.2.4 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting the following
bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
16.1.2.5 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
16.1.2.6 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
16.1.2.7 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set, the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
16.1.2.8 Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
PIC18F/LF1XK50
DS41350E-page 188 Preliminary 2010 Microchip Technology Inc.
16.1.2.9 Asynchronous Reception Set-up:
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 16.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit
and the RX/DT pin TRIS bit. The SYNC bit must
be clear for asynchronous operation.
3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the DTRXP if inverted receive polarity is
desired.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
16.1.2.10 9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 16.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
4. Enable 9-bit reception by setting the RX9 bit.
5. Enable address detection by setting the ADDEN
bit.
6. Set the DTRXP if inverted receive polarity is
desired.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 16-5: ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1 bit 7/8 Stop bit 0 bit 7/8
bit
Start
bit
Start
bit 7/8 Stop bit
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
2010 Microchip Technology Inc. Preliminary DS41350E-page 189
PIC18F/LF1XK50
TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
PIC18F/LF1XK50
DS41350E-page 190 Preliminary 2010 Microchip Technology Inc.
16.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block output
(HFINTOSC). However, the HFINTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two methods
may be used to adjust the baud rate clock, but both
require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 2.6.1
“OSCTUNE Register” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 16.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
2010 Microchip Technology Inc. Preliminary DS41350E-page 191
PIC18F/LF1XK50
REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
PIC18F/LF1XK50
DS41350E-page 192 Preliminary 2010 Microchip Technology Inc.
REGISTER 16-3: BAUDCON: BAUD RATE CONTROL REGISTER
R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been detected and the receiver is active
Synchronous mode:
Don’t care
bit 5 DTRXP: Data/Receive Polarity Select bit
Asynchronous mode:
1 = Receive data (RX) is inverted (active-low)
0 = Receive data (RX) is not inverted (active-high)
Synchronous mode:
1 = Data (DT) is inverted (active-low)
0 = Data (DT) is not inverted (active-high)
bit 4 CKTXP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is low
0 = Idle state for transmit (TX) is high
Synchronous mode:
1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock
0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used (SPBRGH:SPBRG)
0 = 8-bit Baud Rate Generator is used (SPBRG)
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling
edge. WUE will automatically clear on the rising edge.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
2010 Microchip Technology Inc. Preliminary DS41350E-page 193
PIC18F/LF1XK50
16.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH:SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 16-3 contains the formulas for determining the
baud rate. Example 16-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 16-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 16-1: CALCULATING BAUD
RATE ERROR
TABLE 16-3: BAUD RATE FORMULAS
TABLE 16-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRG:
Desired Baud Rate FOSC
64[SPBRGH:SPBRG] + 1 = --------------------------------------------------------------------
= 25.042 = 25
Calculated Baud Rate 16000000
6425 + 1 = ---------------------------
= 9615
Error Calc. Baud Rate – Desired Baud Rate
Desired Baud Rate
= --------------------------------------------------------------------------------------------
9615 – 9600
9600
= ---------------------------------- = 0.16%
FOSC X = 64 * (Desired Baud Rate)
( )-1
16,000,000
= 64 * 9600
( )-1
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]
0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
PIC18F/LF1XK50
DS41350E-page 194 Preliminary 2010 Microchip Technology Inc.
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — — — — — — — — — —
1200 — — — 1200 0.00 239 1202 0.16 155 1200 0.00 143
2400 — — — 2400 0.00 119 2404 0.16 77 2400 0.00 71
9600 9615 0.16 77 9600 0.00 29 9375 -2.34 19 9600 0.00 17
10417 10417 0.00 71 10286 -1.26 27 10417 0.00 17 10165 -2.42 16
19.2k 19.23k 0.16 38 19.20k 0.00 14 18.75k -2.34 9 19.20k 0.00 8
57.6k 57.69k 0.16 12 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 — — — 9600 0.00 119 9615 0.16 77 9600 0.00 71
10417 — — — 10378 -0.37 110 10417 0.00 71 10473 0.53 65
19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 38 19.20k 0.00 35
57.6k 57.69k 0.16 51 57.60k 0.00 19 57.69k 0.16 12 57.60k 0.00 11
115.2k 115.38k 0.16 25 115.2k 0.00 9 — — — 115.2k 0.00 5
2010 Microchip Technology Inc. Preliminary DS41350E-page 195
PIC18F/LF1XK50
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 300.0 0.00 9999 300.0 0.00 3839 300 0.00 2499 300.0 0.00 2303
1200 1200.1 0.00 2499 1200 0.00 959 1200 0.00 624 1200 0.00 575
2400 2400 0.00 1249 2400 0.00 479 2404 0.16 311 2400 0.00 287
9600 9615 0.16 311 9600 0.00 119 9615 0.16 77 9600 0.00 71
10417 10417 0.00 287 10378 -0.37 110 10417 0.00 71 10473 0.53 65
19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 38 19.20k 0.00 35
57.6k 57.69k 0.16 51 57.60k 0.00 19 57.69k 0.16 12 57.60k 0.00 11
115.2k 115.38k 0.16 25 115.2k 0.00 9 — — — 115.2k 0.00 5
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC18F/LF1XK50
DS41350E-page 196 Preliminary 2010 Microchip Technology Inc.
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 300 0.00 39999 300.0 0.00 15359 300 0.00 9999 300.0 0.00 9215
1200 1200 0.00 9999 1200 0.00 3839 1200 0.00 2499 1200 0.00 2303
2400 2400 0.00 4999 2400 0.00 1919 2400 0.00 1249 2400 0.00 1151
9600 9600 0.00 1249 9600 0.00 479 9615 0.16 311 9600 0.00 287
10417 10417 0.00 1151 10425 0.08 441 10417 0.00 287 10433 0.16 264
19.2k 19.20k 0.00 624 19.20k 0.00 239 19.23k 0.16 155 19.20k 0.00 143
57.6k 57.69k 0.16 207 57.60k 0.00 79 57.69k 0.16 51 57.60k 0.00 47
115.2k 115.38k 0.16 103 115.2k 0.00 39 115.38k 0.16 25 115.2k 0.00 23
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
2010 Microchip Technology Inc. Preliminary DS41350E-page 197
PIC18F/LF1XK50
16.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 16-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 16-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH:SPBRG register pair, the ABDEN
bit is automatically cleared, and the RCIF interrupt flag
is set. A read operation on the RCREG needs to be
performed to clear the RCIF interrupt. RCREG content
should be discarded. When calibrating for modes that
do not use the SPBRGH register the user can verify
that the SPBRG register did not overflow by checking
for 00h in the SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 16-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
TABLE 16-6: BRG COUNTER CLOCK RATES
FIGURE 16-6: AUTOMATIC BAUD RATE CALIBRATION
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 16.3.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRG
register pair.
BRG16 BRGH BRG Base
Clock
BRG ABD
Clock
0 0 FOSC/64 FOSC/512
0 1 FOSC/16 FOSC/128
1 0 FOSC/16 FOSC/128
1 1 FOSC/4 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Set by User Auto Cleared
XXXXh 0000h
Edge #1
bit 2 bit 3
Edge #2
bit 4 bit 5
Edge #3
bit 6 bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
SPBRG XXh 1Ch
SPBRGH XXh 00h
RCIDL
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DS41350E-page 198 Preliminary 2010 Microchip Technology Inc.
16.3.2 AUTO-BAUD OVERFLOW
During the course of automatic baud detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRG register
pair. After the ABDOVF has been set, the counter continues
to count until the fifth rising edge is detected on
the RX pin. Upon detecting the fifth RX edge, the hardware
will set the RCIF Interrupt Flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG
register. The ABDOVF flag of the BAUDCON register
can be cleared by software directly.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit of the BAUDCON register. The ABDOVF bit will
remain set if the ABDEN bit is not cleared first.
16.3.3 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 16-7), and asynchronously if
the device is in Sleep mode (Figure 16-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
16.3.3.1 Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared by
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared by software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
2010 Microchip Technology Inc. Preliminary DS41350E-page 199
PIC18F/LF1XK50
FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1Q2 Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit set by user Auto Cleared
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit Set by User Auto Cleared
Cleared due to User Read of RCREG
Sleep Command Executed
Note 1
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
PIC18F/LF1XK50
DS41350E-page 200 Preliminary 2010 Microchip Technology Inc.
16.3.4 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character transmission
is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 16-9 for the timing of
the Break character sequence.
16.3.4.1 Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
16.3.5 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 16.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
FIGURE 16-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
interrupt Flag)
TX (pin)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(send Break
control bit)
SENDB Sampled Here Auto Cleared
2010 Microchip Technology Inc. Preliminary DS41350E-page 201
PIC18F/LF1XK50
16.4 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and
transmit shift registers. Since the data line is
bidirectional, synchronous operation is half-duplex
only. Half-duplex refers to the fact that master and
slave devices can receive and transmit data but not
both simultaneously. The EUSART can operate as
either a master or slave device.
Start and Stop bits are not used in synchronous
transmissions.
16.4.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
The TRIS bits corresponding to the RX/DT and TX/CK
pins should be set.
16.4.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a master transmits the clock on the TX/CK line. The
TX/CK pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
data bits.
16.4.1.2 Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the CKTXP
bit of the BAUDCON register. Setting the CKTXP bit
sets the clock Idle state as high. When the CKTXP bit
is set, the data changes on the falling edge of each
clock and is sampled on the rising edge of each clock.
Clearing the CKTXP bit sets the Idle state as low. When
the CKTXP bit is cleared, the data changes on the
rising edge of each clock and is sampled on the falling
edge of each clock.
16.4.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automatically
enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the previous
character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character commences
immediately following the transfer of the data
to the TSR from the TXREG.
Each data bit changes on the leading edge of the master
clock and remains valid until the subsequent leading
clock edge.
16.4.1.4 Data Polarity
The polarity of the transmit and receive data can be
controlled with the DTRXP bit of the BAUDCON register.
The default state of this bit is ‘0’ which selects high
true transmit and receive data. Setting the DTRXP bit
to ‘1’ will invert the data resulting in low true transmit
and receive data.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
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DS41350E-page 202 Preliminary 2010 Microchip Technology Inc.
16.4.1.5 Synchronous Master Transmission
Set-up:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 16.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Set the
TRIS bits corresponding to the RX/DT and
TX/CK I/O pins.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE, GIE and
PEIE interrupt enable bits.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
FIGURE 16-10: SYNCHRONOUS TRANSMISSION
FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 7
Word 1
bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit
‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
pin
TX/CK pin
TX/CK pin
(SCKP = 0)
(SCKP = 1)
RX/DT pin
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
2010 Microchip Technology Inc. Preliminary DS41350E-page 203
PIC18F/LF1XK50
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
16.4.1.6 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial character
is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two
character receive FIFO. The Least Significant eight bits
of the top character in the receive FIFO are available in
RCREG. The RCIF bit remains set as long as there are
un-read characters in the receive FIFO.
16.4.1.7 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver must be disabled by setting the
associated TRIS bit when the device is configured for
synchronous slave transmit or receive operation. Serial
data bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are data bits.
16.4.1.8 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TXREG EUSART Transmit Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
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DS41350E-page 204 Preliminary 2010 Microchip Technology Inc.
16.4.1.9 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
16.4.1.10 Synchronous Master Reception
Set-up:
1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Disable
RX/DT and TX/CK output drivers by setting the
corresponding TRIS bits.
3. Ensure bits CREN and SREN are clear.
4. If using interrupts, set the GIE and PEIE bits of
the INTCON register and set RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
7. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)
2010 Microchip Technology Inc. Preliminary DS41350E-page 205
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TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
16.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
16.4.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 16.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
16.4.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
2. Clear the CREN and SREN bits.
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
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DS41350E-page 206 Preliminary 2010 Microchip Technology Inc.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
16.4.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 16.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
16.4.2.4 Synchronous Slave Reception
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
2. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
3. If 9-bit reception is desired, set the RX9 bit.
4. Set the CREN bit to enable reception.
5. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
6. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TXREG EUSART Transmit Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
2010 Microchip Technology Inc. Preliminary DS41350E-page 207
PIC18F/LF1XK50
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
PIC18F/LF1XK50
DS41350E-page 208 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 209
PIC18F/LF1XK50
17.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD, or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 17-1 shows the block diagram of the ADC.
FIGURE 17-1: ADC BLOCK DIAGRAM
ADC
AN4
AVDD
VREF+
ADON
GO/DONE
CHS<3:0>
ADRESH ADRESL
10
10
ADFM
VSS
AN5
AN6
AN7
AN3
AN8
AN9
AN10
AN11
AVSS
VREFNVCFG[
1:0] = 00
FVR
0000
0001
0010
0011
0100
0101
0111
0110
1000
1001
1010
1011
1100
1101
1110
1111
Unused
Unused
0 = Left Justify
1 = Right Justify
Unused
Unused
Unused
DAC
NVCFG[1:0] = 01
FVR
PVCFG[1:0] = 00
PVCFG[1:0] = 01
PVCFG[1:0] = 10
PIC18F/LF1XK50
DS41350E-page 210 Preliminary 2010 Microchip Technology Inc.
17.1 ADC Configuration
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
17.1.1 PORT CONFIGURATION
The ANSEL, ANSELH, TRISA, TRISB and TRISE registers
all configure the A/D port pins. Any port pin
needed as an analog input should have its corresponding
ANSx bit set to disable the digital input buffer and
TRISx bit set to disable the digital output driver. If the
TRISx bit is cleared, the digital output level (VOH or
VOL) will be converted.
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
17.1.2 CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 17.2
“ADC Operation” for more information.
17.1.3 ADC VOLTAGE REFERENCE
The PVCFG and NVCFG bits of the ADCON1 register
provide independent control of the positive and
negative voltage references, respectively. The positive
voltage reference can be either VDD, FVR or an
external voltage source. The negative voltage
reference can be either VSS or an external voltage
source.
17.1.4 SELECTING AND CONFIGURING
ACQUISITION TIME
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 TAD. When the GO/DONE bit is set, the A/D
module continues to sample the input for the selected
acquisition time, then automatically begins a conversion.
Since the acquisition time is programmed, there is
no need to wait for an acquisition time between selecting
a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
17.1.5 CONVERSION CLOCK
The source of the conversion clock is software selectable
via the ADCS bits of the ADCON2 register. There
are seven possible clock options:
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
• FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 17-3.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Table 27-9 for more information. Table 17-1 gives
examples of appropriate ADC clock selections.
Note 1: When reading the PORT register, all pins
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx bit set) will be accurately
converted.
2: Analog levels on any pin with the corresponding
ANSx bit cleared may cause
the digital input buffer to consume current
out of the device’s specification limits.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
2010 Microchip Technology Inc. Preliminary DS41350E-page 211
PIC18F/LF1XK50
17.1.6 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 17.1.6
“Interrupts” for more information.
TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
17.1.7 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 17-2 shows the two output formats.
FIGURE 17-2: 10-BIT A/D CONVERSION RESULT FORMAT
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 48 MHz 16 MHz 4 MHz 1 MHz
FOSC/2 000 41.67 ns(2) 125 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 83.33 ns(2) 250 ns(2) 1.0 s 4.0 s
FOSC/8 001 167 ns(2) 500 ns(2) 2.0 s 8.0 s(3)
FOSC/16 101 333 ns(2) 1.0 s 4.0 s 16.0 s(3)
FOSC/32 010 667 ns(2) 2.0 s 8.0 s(3) 32.0 s(3)
FOSC/64 110 1.33 s 4.0 s 16.0 s(3) 64.0 s(3)
FRC x11 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.7 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB
bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
PIC18F/LF1XK50
DS41350E-page 212 Preliminary 2010 Microchip Technology Inc.
17.2 ADC Operation
17.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depending
on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 17-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 TAD acquisition time
before the conversion starts.
FIGURE 17-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 17.2.9 “A/D Conversion
Procedure”.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TCY - TAD TAD9 TAD10
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
On the following cycle:
2 TAD
Discharge
1 2 3 4 5 6 7 8 11
Set GO bit
(Holding capacitor is disconnected from analog input)
9 10
Conversion starts
1 2 3 4
(Holding capacitor continues
acquiring input)
TACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
2 TAD
Discharge
2010 Microchip Technology Inc. Preliminary DS41350E-page 213
PIC18F/LF1XK50
17.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
conversion result
17.2.3 DISCHARGE
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged after every
sample. This feature helps to optimize the unity-gain
amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
17.2.4 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared by software. The
ADRESH:ADRESL registers will be updated with the
partially complete Analog-to-Digital conversion
sample. Unconverted bits will match the last bit
converted.
17.2.5 DELAY BETWEEN CONVERSIONS
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, the currently selected
channel is reconnected to the charge holding capacitor
commencing the next acquisition.
17.2.6 ADC OPERATION IN POWERMANAGED
MODES
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D FRC
clock source should be selected.
17.2.7 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion
to be aborted and the ADC module is turned off,
although the ADON bit remains set.
17.2.8 SPECIAL EVENT TRIGGER
The CCP1 Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 or Timer3 counter resets to zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
See Section 14.3.4 “Special Event Trigger” for more
information.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
PIC18F/LF1XK50
DS41350E-page 214 Preliminary 2010 Microchip Technology Inc.
17.2.9 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
• Select acquisition delay
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 17-1: A/D CONVERSION
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Software delay required if ACQT bits are
set to zero delay. See Section 17.3 “A/D
Acquisition Requirements”.
;This code block configures the ADC
;for polling, Vdd and Vss as reference, Frc
clock and AN4 input.
;
;Conversion start & polling for completion
; are included.
;
MOVLW B’10101111’ ;right justify, Frc,
MOVWF ADCON2 ; & 12 TAD ACQ time
MOVLW B’00000000’ ;ADC ref = Vdd,Vss
MOVWF ADCON1 ;
BSF TRISC,0 ;Set RC0 to input
BSF ANSEL,4 ;Set RC0 to analog
MOVLW B’00010001’ ;AN4, ADC on
MOVWF ADCON0 ;
BSF ADCON0,GO ;Start conversion
ADCPoll:
BTFSC ADCON0,GO ;Is conversion done?
BRA ADCPoll ;No, test again
; Result is complete - store 2 MSbits in
; RESULTHI and 8 LSbits in RESULTLO
MOVFF ADRESH,RESULTHI
MOVFF ADRESL,RESULTLO
2010 Microchip Technology Inc. Preliminary DS41350E-page 215
PIC18F/LF1XK50
17.2.10 ADC REGISTER DEFINITIONS
The following registers are used to control the operation
of the ADC.
Note: Analog pin control is performed by the
ANSEL and ANSELH registers. For
ANSEL and ANSELH registers, see
Register 9-15 and Register 9-16,
respectively.
REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = Reserved
1101 = Reserved
1110 = DAC
1111 = FVR
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: Selecting reserved channels will yield unpredictable results as unimplemented input channels are left
floating.
PIC18F/LF1XK50
DS41350E-page 216 Preliminary 2010 Microchip Technology Inc.
REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 PVCFG<1:0>: Positive Voltage Reference select bit
00 = Positive voltage reference supplied internally by VDD.
01 = Positive voltage reference supplied externally through VREF+ pin.
10 = Positive voltage reference supplied internally through FVR.
11 = Reserved.
bit 1-0 NVCFG<1:0>: Negative Voltage Reference select bit
00 = Negative voltage reference supplied internally by VSS.
01 = Negative voltage reference supplied externally through VREF- pin.
10 = Reserved.
11 = Reserved.
2010 Microchip Technology Inc. Preliminary DS41350E-page 217
PIC18F/LF1XK50
REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge
holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until
conversions begins.
000 = 0(1)
001 = 2 TAD
010 = 4 TAD
011 = 6 TAD
100 = 8 TAD
101 = 12 TAD
110 = 16 TAD
111 = 20 TAD
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction
cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.
PIC18F/LF1XK50
DS41350E-page 218 Preliminary 2010 Microchip Technology Inc.
REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0 — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — — — — — ADRES9 ADRES8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 17-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
2010 Microchip Technology Inc. Preliminary DS41350E-page 219
PIC18F/LF1XK50
17.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 17-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 17-5.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 17-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
EQUATION 17-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacitor Charging = + Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 5μs + TC + Temperature - 25°C0.05μs/°C
TC = –CHOLDRIC + RSS + RS ln(1/2047)
= –13.5pF1k + 700 + 10k ln(0.0004885)
= 1.20μs
TACQ = 5μs + 1.20μs + 50°C- 25°C0.05μs/°C
= 7.45μs
VAPPLIED 1 e
–Tc
-R----C----
–
VAPPLIED 1 1
– -2---0---4---7-
=
VAPPLIED 1 1
– -2---0---4---7-
= VCHOLD
VAPPLIED 1 e
–TC
--R----C---
–
= VCHOLD
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Assumptions: Temperature = 50°C and external impedance of 10k 3.0V VDD
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
PIC18F/LF1XK50
DS41350E-page 220 Preliminary 2010 Microchip Technology Inc.
FIGURE 17-5: ANALOG INPUT MODEL
FIGURE 17-6: ADC TRANSFER FUNCTION
VA CPIN
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE(1)
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 13.5 pF
VSS/VREF-
2.5V
Rss (k)
2.0V
1.5V
.1 1 10
VDD
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
Discharge
Switch
3.0V
3.5V
100
Note 1: See Section 27.0 “Electrical Specifications”.
3FFh
3FEh
ADC Output Code
3FDh
3FCh
004h
003h
002h
001h
000h
Full-Scale
3FBh
1/2 LSB ideal
VSS/VREF- Zero-Scale
Transition
VDD/VREF+
Transition
1/2 LSB ideal
Full-Scale Range
Analog Input Voltage
2010 Microchip Technology Inc. Preliminary DS41350E-page 221
PIC18F/LF1XK50
TABLE 17-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
ADRESH A/D Result Register, High Byte 287
ADRESL A/D Result Register, Low Byte 287
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 287
ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 287
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 287
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
TRISA – – TRISA5 TRISA4 – – – – 288
TRISB TRISB7 TRISB6 TRISB5 TRISB4 – – – – 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
PIC18F/LF1XK50
DS41350E-page 222 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 223
PIC18F/LF1XK50
18.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The Analog
Comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
• Programmable Speed/Power optimization
• PWM shutdown
• Programmable and fixed voltage reference
18.1 Comparator Overview
A single comparator is shown in Figure 18-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
FIGURE 18-1: SINGLE COMPARATOR
–
VIN+ +
VINOutput
Output
VIN+
VINNote:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
PIC18F/LF1XK50
DS41350E-page 224 Preliminary 2010 Microchip Technology Inc.
FIGURE 18-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
MUX
C1
C1POL
C1OUT To PWM Logic
0
1
2
3
C1ON(1)
C1CH<1:0>
2
0
1
C1R
MUX
RD_CM1CON0
Set C1IF
To
C1VINC1VIN+
AGND
C12IN1-
C12IN2-
C12IN3-
C1IN+
D Q
Q1 EN
Data Bus
D Q
EN
CL
Q3*RD_CM1CON0
NReset
+
-
0
1
MUX
VREF
C1RSEL
FVR
C1SP
C1VREF C1OE
C12OUT
0
1
C1SYNC
From TMR1L[0](4)
D Q
SYNCC1OUT
C2OE
2010 Microchip Technology Inc. Preliminary DS41350E-page 225
PIC18F/LF1XK50
FIGURE 18-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
MUX
C2
C2POL
C2OUT To PWM Logic
0
1
2
3
C2ON(1)
C2CH<1:0>
2 D Q
EN
D Q
EN
CL
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2VINC2VIN+
C12OUT pin
AGND
C12IN1-
C12IN2-
C12IN3-
Data Bus
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
0
1
C2R
MUX
C2IN+
0
1
MUX
VREF
C2RSEL
FVR
C2SP
C2VREF
0
1
C2SYNC
C20E
D Q
From TMR1L[0] SYNCC2OUT (4)
PIC18F/LF1XK50
DS41350E-page 226 Preliminary 2010 Microchip Technology Inc.
18.2 Comparator Control
Each comparator has a separate control and
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
18-1 and 18-2, respectively) contain the control and
status bits for the following:
• Enable
• Input selection
• Reference selection
• Output selection
• Output polarity
• Speed selection
18.2.1 COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
18.2.2 COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
18.2.3 COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting input of the comparator. See
Section 21.0 “VOLTAGE REFERENCES” for more
information on the Internal Voltage Reference module.
18.2.4 COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Both comparators share the same output pin
(C12OUT). Priority is determined by the states of the
C1OE and C2OE bits.
TABLE 18-1: COMPARATOR OUTPUT
PRIORITY
18.2.5 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 18-2 shows the output state versus input
conditions, including polarity control.
18.2.6 COMPARATOR SPEED SELECTION
The trade-off between speed or power can be optimized
during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propagation
delay by clearing the CxSP bit to ‘0’.
18.3 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 27.0
“Electrical Specifications” for more details.
Note: To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the
corresponding TRIS bits must also be set
to disable the output drivers.
C10E C2OE C12OUT
0 0 I/O
0 1 C2OUT
1 0 C1OUT
1 1 C2OUT
Note 1: The CxOE bit overrides the PORT data
latch. Setting the CxON has no impact on
the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
TABLE 18-2: COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition CxPOL CxOUT
CxVIN- > CxVIN+ 0 0
CxVIN- < CxVIN+ 0 1
CxVIN- > CxVIN+ 1 1
CxVIN- < CxVIN+ 1 0
2010 Microchip Technology Inc. Preliminary DS41350E-page 227
PIC18F/LF1XK50
18.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusiveor
gate (see Figure 18-2 and Figure 18-3). One latch is
updated with the comparator output level when the
CMxCON0 register is read. This latch retains the value
until the next read of the CMxCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the interrupt
flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures 18-4
and 18-5.
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE and GIE bits of the INTCON
register must all be set to enable comparator interrupts.
If any of these bits are cleared, the interrupt is not
enabled, although the CxIF bit of the PIR2 register will
still be set if an interrupt condition occurs.
18.4.1 PRESETTING THE MISMATCH
LATCHES
The comparator mismatch latches can be preset to the
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the CxPOL bit to the desired CxOUT
non-interrupt level while the CxON bit is cleared. Then,
configure the desired CxPOL level in the same instruction
that the CxON bit is set. Since all register writes are
performed as a Read-Modify-Write, the mismatch
latches will be cleared during the instruction Read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final Write phase.
FIGURE 18-4: COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 18-5: COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate
correctly regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read operation
is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt flags before enabling comparator
interrupts.
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
Reset by Software
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
Cleared by CMxCON0 Read Reset by Software
PIC18F/LF1XK50
DS41350E-page 228 Preliminary 2010 Microchip Technology Inc.
18.5 Operation During Sleep
The comparator, if enabled before entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in the
Section 27.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator. Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE2 register
and the PEIE bit of the INTCON register must be set.
The instruction following the SLEEP instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
18.6 Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their Off
states.
2010 Microchip Technology Inc. Preliminary DS41350E-page 229
PIC18F/LF1XK50
REGISTER 18-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1ON: Comparator C1 Enable bit
1 = Comparator C1 is enabled
0 = Comparator C1 is disabled
bit 6 C1OUT: Comparator C1 Output bit
If C1POL = 1 (inverted polarity):
C1OUT = 0 when C1VIN+ > C1VINC1OUT
= 1 when C1VIN+ < C1VINIf
C1POL = 0 (non-inverted polarity):
C1OUT = 1 when C1VIN+ > C1VINC1OUT
= 0 when C1VIN+ < C1VINbit
5 C1OE: Comparator C1 Output Enable bit
If C2OE = 0 (C2 output disable)
0 = C1OUT is internal only
1 = C1OUT is present on the C12OUT pin(1)
If C2OE = 1 (C2 output enable)
0 = C1OUT is internal only
1 = C2OUT is present on the C12OUT pin(1)
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 C1SP: Comparator C1 Speed/Power Select bit
1 = C1 operates in normal power, higher speed mode
0 = C1 operates in low-power, low-speed mode
bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input)
1 = C1VIN+ connects to C1VREF output
0 = C1VIN+ connects to C12IN+ pin
bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit
00 = C1VIN- connects to AGND
01 = C12IN1- pin of C1 connects to C1VIN-
10 = C12IN2- pin of C1 connects to C1VIN-
11 = C12IN3- pin of C1 connects to C1VINNote
1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port
TRIS bit = 0.
PIC18F/LF1XK50
DS41350E-page 230 Preliminary 2010 Microchip Technology Inc.
REGISTER 18-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2ON: Comparator C2 Enable bit
1 = Comparator C2 is enabled
0 = Comparator C2 is disabled
bit 6 C2OUT: Comparator C2 Output bit
If C2POL = 1 (inverted polarity):
C2OUT = 0 when C2VIN+ > C2VINC2OUT
= 1 when C2VIN+ < C2VINIf
C2POL = 0 (non-inverted polarity):
C2OUT = 1 when C2VIN+ > C2VINC2OUT
= 0 when C2VIN+ < C2VINbit
5 C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on C12OUT pin(1)
0 = C2OUT is internal only
bit 4 C2POL: Comparator C2 Output Polarity Select bit
1 = C2OUT logic is inverted
0 = C2OUT logic is not inverted
bit 3 C2SP: Comparator C2 Speed/Power Select bit
1 = C2 operates in normal power, higher speed mode
0 = C2 operates in low-power, low-speed mode
bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2VIN+ connects to C2VREF
0 = C2VIN+ connects to C2IN+ pin
bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits
00 = C1VIN- connects to AGND
01 = C12IN1- pin of C2 connects to C2VIN-
10 = C12IN2- pin of C2 connects to C2VIN-
11 = C12IN3- pin of C2 connects to C2VINNote
1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.
2010 Microchip Technology Inc. Preliminary DS41350E-page 231
PIC18F/LF1XK50
18.7 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 18-6. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 18-6: ANALOG INPUT MODEL
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
VA
Rs < 10K
CPIN
5 pF
VDD
VT 0.6V
VT 0.6V
RIC
ILEAKAGE(1)
Vss
AIN
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See Section 27.0 “Electrical Specifications”.
PIC18F/LF1XK50
DS41350E-page 232 Preliminary 2010 Microchip Technology Inc.
18.8 Additional Comparator Features
There are four additional comparator features:
• Simultaneous read of comparator outputs
• Internal reference selection
• Hysteresis selection
• Output Synchronization
18.8.1 SIMULTANEOUS COMPARATOR
OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.
18.8.2 INTERNAL REFERENCE
SELECTION
There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the Fixed Voltage Reference (FVR) and the
other is the variable Comparator Voltage Reference
(CVREF). The CxRSEL bit of the CM2CON register
determines which of these references is routed to the
Comparator Voltage reference output (CXVREF). Further
routing to the comparator is accomplished by the
CxR bit of the CMxCON0 register. See Section 21.1
“Voltage Reference” and Figure 18-2 and Figure 18-3
for more detail.
18.8.3 COMPARATOR HYSTERESIS
The Comparator Cx have selectable hysteresis. The
hysteresis can be enable by setting the CxHYS bit of
the CM2CON1 register. See Section 27.0 “Electrical
Specifications” for more details.
18.8.4 SYNCHRONIZING COMPARATOR
OUTPUT TO TIMER 1
The Comparator Cx output can be synchronized with
Timer1 by setting the CxSYNC bit of the CM2CON1
register. When enabled, the Cx output is latched on
the rising edge of the Timer1 source clock. If a prescaler
is used with Timer1, the comparator output is
latched after the prescaling function. To prevent a
race condition, the comparator output is latched on
the rising edge of the Timer1 clock source and Timer1
increments on the rising edge of its clock source. See
the Comparator Block Diagram (Figure 18-2 and
Figure 18-3) and the Timer1 Block Diagram
(Figure 18-2) for more information.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
2010 Microchip Technology Inc. Preliminary DS41350E-page 233
PIC18F/LF1XK50
REGISTER 18-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MC1OUT: Mirror Copy of C1OUT bit
bit 6 MC2OUT: Mirror Copy of C2OUT bit
bit 5 C1RSEL: Comparator C1 Reference Select bit
1 = FVR routed to C1VREF input
0 = CVREF routed to C1VREF input
bit 4 C2RSEL: Comparator C2 Reference Select bit
1 = FVR routed to C2VREF input
0 = CVREF routed to C2VREF input
bit 3 C1HYS: Comparator C1 Hysteresis Enable bit
1 = Comparator C1 hysteresis enabled
0 = Comparator C1 hysteresis disabled
bit 2 C2HYS: Comparator C2 Hysteresis Enable bit
1 = Comparator C2 hysteresis enabled
0 = Comparator C2 hysteresis disabled
bit 1 C1SYNC: C1 Output Synchronous Mode bit
1 = C1 output is synchronous to rising edge to TMR1 clock
0 = C1 output is asynchronous
bit 0 C2SYNC: C2 Output Synchronous Mode bit
1 = C2 output is synchronous to rising edge to TMR1 clock
0 = C2 output is asynchronous
PIC18F/LF1XK50
DS41350E-page 234 Preliminary 2010 Microchip Technology Inc.
TABLE 18-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 288
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 288
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 288
REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 287
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 287
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 288
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 235
PIC18F/LF1XK50
19.0 POWER-MANAGED MODES
PIC18F/LF1XK50 devices offer a total of seven operating
modes for more efficient power management.
These modes provide a variety of options for selective
power conservation in applications where resources
may be limited (i.e., battery-powered devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several powersaving
features offered on previous PIC® microcontroller
devices. One is the clock switching feature which allows
the controller to use the Timer1 oscillator in place of the
primary oscillator. Also included is the Sleep mode,
offered by all PIC® microcontroller devices, where all
device clocks are stopped.
19.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Whether or not the CPU is to be clocked
• The selection of a clock source
The IDLEN bit of the OSCCON register controls CPU
clocking, while the SCS<1:0> bits of the OSCCON
register select the clock source. The individual modes,
bit settings, clock sources and affected modules are
summarized in Table 19-1.
19.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<3:0>
Configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block
19.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. Refer to
Section 2.8 “Clock Switching” for more information.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit of the OSCCON register.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 19-1: POWER-MANAGED MODES
Mode
OSCCON Bits Module Clocking
Available Clock and Oscillator Source
IDLEN(1) SCS<1:0> CPU Peripherals
Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal
Oscillator Block(2).
This is the normal full power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)
PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.
PIC18F/LF1XK50
DS41350E-page 236 Preliminary 2010 Microchip Technology Inc.
19.1.3 MULTIPLE FUNCTIONS OF THE
SLEEP COMMAND
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit of the OSCCON register at the time the
instruction is executed. All clocks stop and minimum
power is consumed when SLEEP is executed with the
IDLEN bit cleared. The system clock continues to supply
a clock to the peripherals but is disconnected from
the CPU when SLEEP is executed with the IDLEN bit
set.
19.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
19.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled (see Section 2.12 “Two-Speed Start-up
Mode” for details). In this mode, the device operated
off the oscillator defined by the FOSC bits of the
CONFIGH Configuration register.
19.2.2 SEC_RUN MODE
In SEC_RUN mode, the CPU and peripherals are
clocked from the secondary external oscillator. This
gives users the option of lower power consumption
while still using a high accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits of the OSCCON register to ‘01’. When SEC_RUN
mode is active all of the following are true:
• The main clock source is switched to the
secondary external oscillator
• Primary external oscillator is shut down
• T1RUN bit of the T1CON register is set
• OSTS bit is cleared.
19.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator. In this mode, the
primary external oscillator is shut down. RC_RUN
mode provides the best power conservation of all the
Run modes when the LFINTOSC is the system clock.
RC_RUN mode is entered by setting the SCS1 bit.
When the clock source is switched from the primary
oscillator to the internal oscillator, the primary oscillator
is shut down and the OSTS bit is cleared. The IRCF bits
may be modified at any time to immediately change the
clock speed.
Note: The secondary external oscillator should
already be running prior to entering
SEC_RUN mode. If the T1OSCEN bit is
not set when the SCS<1:0> bits are set to
‘01’, entry to SEC_RUN mode will not
occur until T1OSCEN bit is set and secondary
external oscillator is ready.
2010 Microchip Technology Inc. Preliminary DS41350E-page 237
PIC18F/LF1XK50
19.3 Sleep Mode
The Power-Managed Sleep mode in the PIC18F/
LF1XK50 devices is identical to the legacy Sleep mode
offered in all other PIC® microcontroller devices. It is
entered by clearing the IDLEN bit of the OSCCON
register and executing the SLEEP instruction. This shuts
down the selected oscillator (Figure 19-1) and all clock
source status bits are cleared.
Entering the Sleep mode from either Run or Idle mode
does not require a clock switch. This is because no
clocks are needed once the controller has entered
Sleep. If the WDT is selected, the LFINTOSC source
will continue to operate. If the Timer1 oscillator is
enabled, it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 19-2), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 24.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
19.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected by the SCS<1:0> bits; however, the CPU
will not be clocked. The clock source status bits are not
affected. Setting IDLEN and executing a SLEEP instruction
provides a quick method of switching from a given
Run mode to its corresponding Idle mode.
If the WDT is selected, the LFINTOSC source will continue
to operate. If the Timer1 oscillator is enabled, it
will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out, or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD while it
becomes ready to execute code. When the CPU
begins executing code, it resumes with the same clock
source for the current Idle mode. For example, when
waking from RC_IDLE mode, the internal oscillator
block will clock the CPU and peripherals (in other
words, RC_RUN mode). The IDLEN and SCS bits are
not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
FIGURE 19-1: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 19-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4
OSC1
Peripheral
Sleep
Program
Q1 Q1
Counter
Clock
CPU
Clock
PC PC + 2
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 4 PC + 6
Q1 Q2 Q3 Q4
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit set
PC + 2
PIC18F/LF1XK50
DS41350E-page 238 Preliminary 2010 Microchip Technology Inc.
19.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction.
If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 19-3).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wakeup,
the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 19-4).
19.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting
the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing
code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 19-
4).
FIGURE 19-3: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 19-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE
mode. If the T1OSCEN bit is not set when
the SLEEP instruction is executed, the
main system clock will continue to operate
in the previously selected mode and the
corresponding IDLE mode will be entered
(i.e., PRI_IDLE or RC_IDLE).
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
2010 Microchip Technology Inc. Preliminary DS41350E-page 239
PIC18F/LF1XK50
19.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals
continue to be clocked from the internal oscillator
block from the HFINTOSC multiplexer output. This
mode allows for controllable power conservation during
Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the HFINTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the HFINTOSC output is enabled.
The IOSF bit becomes set, after the HFINTOSC output
becomes stable, after an interval of TIOBST. Clocks to
the peripherals continue while the HFINTOSC source
stabilizes. If the IRCF bits were previously at a nonzero
value, or INTSRC was set before the SLEEP
instruction was executed and the HFINTOSC source
was already stable, the IOSF bit will remain set. If the
IRCF bits and INTSRC are all clear, the HFINTOSC
output will not be enabled, the IOSF bit will remain clear
and there will be no indication of the current clock
source.
When a wake event occurs, the peripherals continue to
be clocked from the HFINTOSC multiplexer output.
After a delay of TCSD following the wake event, the CPU
begins executing code being clocked by the
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
19.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
• an interrupt
• a Reset
• a Watchdog Time-out
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 19.2 “Run Modes”,
Section 19.3 “Sleep Mode” and Section 19.4 “Idle
Modes”).
19.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The PEIE bIt must also
be set If the desired interrupt enable bit is in a PIE
register. The exit sequence is initiated when the
corresponding interrupt flag bit is set.
The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching (see Section 7.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
19.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 19.2 “Run
Modes” and Section 19.3 “Sleep Mode”). If the
device is executing code (all Run modes), the time-out
will result in a WDT Reset (see Section 24.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by any one
of the following:
• executing a SLEEP instruction
• executing a CLRWDT instruction
• the loss of the currently selected clock source
when the Fail-Safe Clock Monitor is enabled
• modifying the IRCF bits in the OSCCON register
when the internal oscillator block is the device
clock source
PIC18F/LF1XK50
DS41350E-page 240 Preliminary 2010 Microchip Technology Inc.
19.5.3 EXIT BY RESET
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 23.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in Table 19-2.
19.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval TCSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 19-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up Exit Delay Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
TCSD HSPLL (1) OSTS
EC, RC
HFINTOSC(2) IOSF
T1OSC or LFINTOSC(1)
LP, XT, HS TOST(3)
HSPLL TOST + tPLL OSTS
(3)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOSF
HFINTOSC(2)
LP, XT, HS TOST(4)
HSPLL TOST + tPLL OSTS
(3)
EC, RC TCSD(1)
HFINTOSC(1) None IOSF
None
(Sleep mode)
LP, XT, HS TOST(3)
HSPLL TOST + tPLL OSTS
(3)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOSF
Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
required delays (see Section 19.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer. tPLL is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, TIOBST.
2010 Microchip Technology Inc. Preliminary DS41350E-page 241
PIC18F/LF1XK50
20.0 SR LATCH
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as selectable latch output.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available internally/externally
• Selectable Q and Q output
• Firmware Set and Reset
20.1 Latch Operation
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by CxOUT,
INT1 pin, or variable clock. Additionally the SRPS and
the SRPR bits of the SRCON0 register may be used to
Set or Reset the SR Latch, respectively. The latch is
reset-dominant, therefore, if both Set and Reset inputs
are high the latch will go to the Reset state. Both the
SRPS and SRPR bits are self resetting which means
that a single write to either of the bits is all that is
necessary to complete a latch Set or Reset operation.
20.2 Latch Output
The SRQEN and SRNQEN bits of the SRCON0 register
control the latch output selection. Only one of the SR
latch’s outputs may be directly output to an I/O pin at a
time. Priority is determined by the state of bits SRQEN
and SRNQEN in registers SRCON0.
TABLE 20-1: SR LATCH OUTPUT
CONTROL
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
20.3 Effects of a Reset
Upon any device Reset, the SR latch is not initialized.
The user’s firmware is responsible to initialize the latch
output before enabling it to the output pins.
FIGURE 20-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRLEN SRQEN SRNQEN SR Latch Output
to Port I/O
0 X X I/O
1 0 0 I/O
1 0 1 Q
1 1 0 Q
1 1 1 Q
SRPS
S
R
Q
Q
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2: Pulse generator causes a 2 Q-state pulse width.
3: Output shown for reference only. See I/O port pin block diagram for more detail.
4: Name denotes the source of connection at the comparator output.
Pulse
Gen(2)
SR
Latch(1)
SRNQEN
SRQ pin(3)
SRQEN
SRNQEN
SRSPE
SRSC2E
INT1
SRSCKE
SRCLK
SYNCC2OUT(4)
SRSC1E
SYNCC1OUT(4)
SRPR Pulse
Gen(2)
SRRPE
SRRC2E
INT1
SRRCKE
SRCLK
SYNCC2OUT(4)
SRRC1E
SYNCC1OUT(4)
SRLEN
SRLEN
PIC18F/LF1XK50
DS41350E-page 242 Preliminary 2010 Microchip Technology Inc.
TABLE 20-2: SRCLK FREQUENCY TABLE
SRCLK Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz
111 512 25.6 s 32 s 64 s 128 s 512 s
110 256 12.8 s 16 s 32 s 64 s 256 s
101 128 6.4 s 8 s 16 s 32 s 128 s
100 64 3.2 s 4 s 8 s 16 s 64 s
011 32 1.6 s 2 s 4 s 8 s 32 s
010 16 0.8 s 1 s 2 s 4 s 16 s
001 8 0.4 s 0.5 s 1 s 2 s 8 s
000 4 0.2 s 0.25 s 0.5 s 1 s 4 s
REGISTER 20-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SRLEN: SR Latch Enable bit(1)
1 = SR latch is enabled
0 = SR latch is disabled
bit 6-4 SRCLK<2:0>(1): SR Latch Clock divider bits
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
bit 3 SRQEN: SR Latch Q Output Enable bit
If SRNQEN = 0
1 = Q is present on the RC4 pin
0 = Q is internal only
bit 2 SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the RC4 pin
0 = Q is internal only
bit 1 SRPS: Pulse Set Input of the SR Latch
1 = Pulse input
0 = Always reads back ‘0’
bit 0 SRPR: Pulse Reset Input of the SR Latch
1 = Pulse input
0 = Always reads back ‘0’
Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
2010 Microchip Technology Inc. Preliminary DS41350E-page 243
PIC18F/LF1XK50
TABLE 20-3: REGISTERS ASSOCIATED WITH THE SR LATCH
REGISTER 20-2: SRCON1: SR LATCH CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SRSPE: SR Latch Peripheral Set Enable bit
1 = INT1 pin status sets SR Latch
0 = INT1pin status has no effect on SR Latch
bit 6 SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = Set input of SR latch is not pulsed with SRCLK
bit 5 SRSC2E: SR Latch C2 Set Enable bit
1 = C2 Comparator output sets SR Latch
0 = C2 Comparator output has no effect on SR Latch
bit 4 SRSC1E: SR Latch C1 Set Enable bit
1 = C1 Comparator output sets SR Latch
0 = C1 Comparator output has no effect on SR Latch
bit 3 SRRPE: SR Latch Peripheral Reset Enable bit
1 = INT1 pin resets SR Latch
0 = INT1 pin has no effect on SR Latch
bit 2 SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with SRCLK
0 = Reset input of SR latch is not pulsed with SRCLK
bit 1 SRRC2E: SR Latch C2 Reset Enable bit
1 = C2 Comparator output resets SR Latch
0 = C2 Comparator output has no effect on SR Latch
bit 0 SRRC1E: SR Latch C1 Reset Enable bit
1 = C1 Comparator output resets SR Latch
0 = C1 Comparator output has no effect on SR Latch
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 288
SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 288
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 288
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 285
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: Shaded cells are not used with the comparator voltage reference.
PIC18F/LF1XK50
DS41350E-page 244 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 245
PIC18F/LF1XK50
21.0 VOLTAGE REFERENCES
There are two independent voltage references
available:
• Programmable Voltage Reference
• 1.024V Fixed Voltage Reference
21.1 Voltage Reference
The Voltage Reference module provides an internally
generated voltage reference for the comparators and
the DAC module. The following features are available:
• Independent from Comparator operation
• Single 32-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• 1.024V Fixed Reference Voltage (FVR)
The REFCON1 register (Register 21-2) controls the
Voltage Reference module shown in Figure 21-1.
21.1.1 INDEPENDENT OPERATION
The voltage reference is independent of the
comparator configuration. Setting the D1EN bit of the
REFCON1 register will enable the voltage reference by
allowing current to flow in the VREF voltage divider.
When the D1EN bit is cleared, current flow in the VREF
voltage divider is disabled minimizing the power drain
of the voltage reference peripheral.
21.1.2 OUTPUT VOLTAGE SELECTION
The VREF voltage reference has 32 voltage level
ranges. The 32 levels are set with the DAC1R<4:0>
bits of the REFCON2 register.
The VREF output voltage is determined by the following
equations:
EQUATION 21-1: VREF OUTPUT VOLTAGE
21.1.3 OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the VREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 27.0
“Electrical Specifications”.
21.1.4 VOLTAGE REFERENCE OUTPUT
The VREF voltage reference can be output to the device
CVREF pin by setting the DAC1OE bit of the REFCON1
register to ‘1’. Selecting the reference voltage for output
on the VREF pin automatically overrides the digital
output buffer and digital input threshold detector functions
of that pin. Reading the CVREF pin when it has
been configured for reference voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to CVREF. Figure 21-2 shows an example
buffering technique.
21.1.5 OPERATION DURING SLEEP
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the RECON1 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
21.1.6 EFFECTS OF A RESET
A device Reset affects the following:
• Voltage reference is disabled
• Fixed voltage reference is disabled
• VREF is removed from the CVREF pin
• The DAC1R<4:0> range select bits are cleared
VOUT VSOURCE – VSOURCE x DAC1R[4:0]
25 -------------------------------- + VSOURCE
= -
IF D1EN = 1
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 11111:
VOUT = VSOURCE+
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 00000:
VOUT = VSOURCE-
+ -
PIC18F/LF1XK50
DS41350E-page 246 Preliminary 2010 Microchip Technology Inc.
21.2 FVR Reference Module
The FVR reference is a stable fixed voltage reference,
independent of VDD, with a nominal output voltage of
1.024V. This reference can be enabled by setting the
FVR1EN bit of the REFCON0 register to ‘1’. The FVR
voltage reference can be routed to the comparators or
an ADC input channel.
21.2.1 FVR STABILIZATION PERIOD
When the Fixed Voltage Reference module is enabled, it
will require some time for the reference and its amplifier
circuits to stabilize. The user program must include a
small delay routine to allow the module to settle. The
FVR1ST stable bit of the REFCON0 register also
indicates that the FVR reference has been operating long
enough to be stable. See Section 27.0 “Electrical
Specifications” for the minimum delay requirement.
FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM
16-to-1 MUX
DAC1R<4:0>
R
VDD
VREF+
D1PSS<1:0> = 00
D1NSS = 0
VREF- D1NSS = 1
R
R
R
R
R
R
32 Steps
VREF
FVR1
D1PSS<1:0> = 01
D1PSS<1:0> = 10
CVREF pin
DAC1OE
FVR1S<1:0>
X1
X2
X4
2
FVR
+
_
FVR1EN
FVR1ST
1.024V Fixed
Reference
D1EN
D1LPS
R
D1EN
D1LPS
2010 Microchip Technology Inc. Preliminary DS41350E-page 247
PIC18F/LF1XK50
FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
REGISTER 21-1: REFCON0: REFERENCE CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-1 U-0 U-0 U-0 U-0
FVR1EN FVR1ST FVR1S1 FVR1S0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FVR1EN: Fixed Voltage Reference 1 Enable bit
0 = FVR is disabled
1 = FVR is enabled
bit 6 FVR1ST: Fixed Voltage Reference 1 Stable bit
0 = FVR is not stable
1 = FVR is stable
bit 5-4 FVR1S<1:0>: Fixed Voltage Reference 1 Voltage Select bits
00 = Reserved, do not use
01 = 1.024V (x1)
10 = 2.048V (x2)
11 = 4.096V (x4)
bit 3-0 Unimplemented: Read as ‘0’
Buffered CVREF Output
+–
CVREF
Module
Voltage
Reference
Output
Impedance
R(1)
CVREF
Note 1: R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR.
PIC18F1XK50/
PIC18LF1XK50
PIC18F/LF1XK50
DS41350E-page 248 Preliminary 2010 Microchip Technology Inc.
REGISTER 21-2: REFCON1: REFERENCE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0
D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 --- D1NSS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 D1EN: DAC 1 Enable bit
0 = DAC 1 is disabled
1 = DAC 1 is enabled
bit 6 D1LPS: DAC 1 Low-Power Voltage State Select bit
0 = VDAC = DAC1 Negative reference source selected
1 = VDAC = DAC1 Positive reference source selected
bit 5 DAC1OE: DAC 1 Voltage Output Enable bit
1 = DAC 1 voltage level is also outputed on the RC2/AN6/P1D/C12IN2-/CVREF/INT2 pin
0 = DAC 1 voltage level is disconnected from RC2/AN6/P1D/C12IN2-/CVREF/INT2 pin
bit 4 Unimplemented: Read as ‘0’
bit 3-2 D1PSS<1:0>: DAC 1 Positive Source Select bits
00 = VDD
01 = VREF+
10 = FVR output
11 = Reserved, do not use
bit 1 Unimplemented: Read as ‘0’
bit 0 D1NSS: DAC1 Negative Source Select bits
0 = VSS
1 = VREFREGISTER
21-3: REFCON2: REFERENCE CONTROL REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
--- --- --- DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 DAC1R<4:0>: DAC1 Voltage Output Select bits
VOUT = ((VSOURCE+) - (VSOURCE-))*(DAC1R<4:0>/(2^5)) + VSOURCENote
1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
2010 Microchip Technology Inc. Preliminary DS41350E-page 249
PIC18F/LF1XK50
TABLE 21-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 287
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 287
REFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: Shaded cells are not used with the comparator voltage reference.
PIC18F/LF1XK50
DS41350E-page 250 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 251
PIC18F/LF1XK50
22.0 UNIVERSAL SERIAL BUS
(USB)
This section describes the details of the USB
peripheral. Because of the very specific nature of the
module, knowledge of USB is expected. Some
high-level USB information is provided in
Section 22.10 “Overview of USB” only for application
design reference. Designers are encouraged to refer to
the official specification published by the USB Implementers
Forum (USB-IF) for the latest information.
USB Specification Revision 2.0 is the most current
specification at the time of publication of this document.
22.1 Overview of the USB Peripheral
PIC18F1XK50/PIC18LF1XK50 devices contain a
full-speed and low-speed, compatible USB Serial Interface
Engine (SIE) that allows fast communication
between any USB host and the PIC® microcontroller.
The SIE can be interfaced directly to the USB by
utilizing the internal transceiver.
Some special hardware features have been included to
improve performance. Dual access port memory in the
device’s data memory space (USB RAM) has been
supplied to share direct memory access between the
microcontroller core and the SIE. Buffer descriptors are
also provided, allowing users to freely program endpoint
memory usage within the USB RAM space.
Figure 22-1 presents a general overview of the USB
peripheral and its features.
FIGURE 22-1: USB PERIPHERAL AND OPTIONS
256 byte
USB RAM
USB
SIE
USB Control and
Transceiver
P
P
D+
DInternal
Pull-ups
External 3.3V
Supply
FSEN
UPUEN
USB Clock from the
Oscillator Module
Optional
External
Pull-ups(1)
(Full (Low
PIC18F1XK50/PIC18LF1XK50 Family
USB Bus
FS
Speed) Speed)
Note 1: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.
2: PIC18F13K50/PIC18F14K50 only.
Configuration
VUSB
3.3V LDO Regulator(2)
PIC18F/LF1XK50
DS41350E-page 252 Preliminary 2010 Microchip Technology Inc.
22.2 USB Status and Control
The operation of the USB module is configured and
managed through three control registers. In addition, a
total of 14 registers are used to manage the actual USB
transactions. The registers are:
• USB Control register (UCON)
• USB Configuration register (UCFG)
• USB Transfer Status register (USTAT)
• USB Device Address register (UADDR)
• Frame Number registers (UFRMH:UFRML)
• Endpoint Enable registers 0 through 7 (UEPn)
22.2.1 USB CONTROL REGISTER (UCON)
The USB Control register (Register 22-1) contains bits
needed to control the module behavior during transfers.
The register contains bits that control the following:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend mode
• Packet Transfer Disable
In addition, the USB Control register contains a status
bit, SE0 (UCON<5>), which is used to indicate the
occurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be monitored
to determine whether the differential data lines
have come out of a single-ended zero condition. This
helps to differentiate the initial power-up state from the
USB Reset signal.
The overall operation of the USB module is controlled
by the USBEN bit (UCON<3>). Setting this bit activates
the module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. This bit also activates the internal
pull-up resistors, if they are enabled. Thus, this bit
can be used as a soft attach/detach to the USB.
Although all Status and control bits are ignored when
this bit is clear, the module needs to be fully preconfigured
prior to setting this bit. This bit cannot be set until
the USB module is supplied with an active clock
source. If the PLL is being used, it should be enabled
at least two milliseconds (enough time for the PLL to
lock) before attempting to set the USBEN bit.
REGISTER 22-1: UCON: USB CONTROL REGISTER
U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST SE0 PKTDIS USBEN(1) RESUME SUSPND —
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit(1)
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit cannot be set if the USB module does not have an appropriate clock source.
2010 Microchip Technology Inc. Preliminary DS41350E-page 253
PIC18F/LF1XK50
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong Buffer
Pointers are set to the Even buffers. PPBRST has
to be cleared by firmware. This bit is ignored in buffering
modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing Resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on “resume signaling”,
see the “Universal Serial Bus Specification
Revision 2.0”.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry in a Low-Power mode. The input
clock to the SIE is also disabled. This bit should be set
by the software in response to an IDLEIF interrupt. It
should be reset by the microcontroller firmware after an
ACTVIF interrupt is observed. When this bit is active,
the device remains attached to the bus but the transceiver
outputs remain Idle. The voltage on the VUSB pin
may vary depending on the value of this bit. Setting this
bit before a IDLEIF request will result in unpredictable
bus behavior.
22.2.2 USB CONFIGURATION REGISTER
(UCFG)
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 22-2).The UFCG register
contains most of the bits that control the system level
behavior of the USB module. These include:
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• Ping-Pong Buffer Usage
The UTEYE bit, UCFG<7>, enables eye pattern generation,
which aids in module testing, debugging and
USB certifications.
22.2.2.1 Internal Transceiver
The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed capable transceiver, internally connected
to the SIE. This feature is useful for low-cost,
single chip applications. Enabling the USB module
(USBEN = 1) will also enable the internal transceiver.
The FSEN bit (UCFG<2>) controls the transceiver
speed; setting the bit enables full-speed operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The internal USB transceiver obtains power from the
VUSB pin. In order to meet USB signalling level
specifications, VUSB must be supplied with a voltage
source between 3.0V and 3.6V. The best electrical
signal quality is obtained when a 3.3V supply is used
and locally bypassed with a high quality ceramic
capacitor. The capacitor should be placed as close as
possible to the VUSB and VSS pins found on the same
edge of the package (i.e., route ground of the capacitor
to VSS pin 20 on 20-lead PDIP, SOIC, SSOP and QFN
packaged parts).
The D+ and D- signal lines can be routed directly to
their respective pins on the USB connector or cable (for
hard-wired applications). No additional resistors,
capacitors, or magnetic components are required as
the D+ and D- drivers have controlled slew rate and
output impedance intended to match with the
characteristic impedance of the USB cable.
In order to meet the USB specifications, the traces
should be less than 30 cm long. Ideally, these traces
should be designed to have a characteristic impedance
matching that of the USB cable.
Note: While in Suspend mode, a typical
bus-powered USB device is limited to
500 A of current. This is the complete
current which may be drawn by the PIC
device and its supporting circuitry. Care
should be taken to assure minimum
current draw when the device enters
Suspend mode.
Note: The USB speed, transceiver and pull-up
should only be configured during the module
setup phase. It is not recommended to
switch these settings while the module is
enabled.
PIC18F/LF1XK50
DS41350E-page 254 Preliminary 2010 Microchip Technology Inc.
REGISTER 22-2: UCFG: USB CONFIGURATION REGISTER
R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
UTEYE — — UPUEN(1) — FSEN(1) PPB1 PPB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(1)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2 FSEN: Full-Speed Enable bit(1)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1: The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values
must be preconfigured prior to enabling the module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 255
PIC18F/LF1XK50
22.2.2.2 Internal Pull-up Resistors
The PIC18F1XK50/PIC18LF1XK50 devices have
built-in pull-up resistors designed to meet the requirements
for low-speed and full-speed USB. The UPUEN
bit (UCFG<4>) enables the internal pull-ups.
Figure 22-1 shows the pull-ups and their control.
22.2.2.3 External Pull-up Resistors
External pull-up may also be used. The VUSB pin may be
used to pull up D+ or D-. The pull-up resistor must be
1.5 k (±5%) as required by the USB specifications.
Figure 22-2 shows an example.
FIGURE 22-2: EXTERNAL CIRCUITRY
22.2.2.4 Ping-Pong Buffer Configuration
The usage of ping-pong buffers is configured using the
PPB<1:0> bits. Refer to Section 22.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
22.2.2.5 Eye Pattern Test Enable
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certification
tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
Note: The official USB specifications require
that USB devices must never source any
current onto the +5V VBUS line of the USB
cable. Additionally, USB devices must
never source any current on the D+ and
D- data lines whenever the +5V VBUS line
is less than 1.17V. In order to meet this
requirement, applications which are not
purely bus powered should monitor the
VBUS line and avoid turning on the USB
module and the D+ or D- pull-up resistor
until VBUS is greater than 1.17V. VBUS can
be connected to and monitored by any 5V
tolerant I/O pin for this purpose.
PIC®
Microcontroller
Host
Controller/HUB
VUSB
D+
DNote:
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
1.5 k
PIC18F/LF1XK50
DS41350E-page 256 Preliminary 2010 Microchip Technology Inc.
22.2.3 USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 22-3).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will reassert the
interrupt within 6 TCY of clearing TRNIF. If no additional
data is present, TRNIF will remain clear; USTAT data
will no longer be reliable.
FIGURE 22-3: USTAT FIFO
Note: The data in the USB Status register is
valid two SIE clocks after the TRNIF interrupt
flag is asserted.
In low-speed operation with the system
clock operating at 48 MHz, a delay may
be required between receiving the TRNIF
interrupt and processing the data in the
USTAT register.
Note: If an endpoint request is received while
the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
Data Bus
USTAT from SIE
4-Byte FIFO
for USTAT
Clearing TRNIF
Advances FIFO
REGISTER 22-3: USTAT: USB STATUS REGISTER
U-0 U-0 R-x R-x R-x R-x R-x U-0
— — ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 ENDP<2:0>: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
111 = Endpoint 7
110 = Endpoint 6
....
001 = Endpoint 1
000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.
2010 Microchip Technology Inc. Preliminary DS41350E-page 257
PIC18F/LF1XK50
22.2.4 USB ENDPOINT CONTROL
Each of the 8 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ represents
the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 22-4.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transactions.
Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or disable
USB OUT transactions from the host. Setting this
bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that endpoint
pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
REGISTER 22-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP7)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0 EPSTALL: Endpoint STALL Enable bit(1)
1 = Endpoint n is stalled
0 = Endpoint n is not stalled
Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.
PIC18F/LF1XK50
DS41350E-page 258 Preliminary 2010 Microchip Technology Inc.
22.2.5 USB ADDRESS REGISTER
(UADDR)
The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
22.2.6 USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number registers are primarily used for
isochronous transfers. The contents of the UFRMH and
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND (UCON<1>) bit = 1).
22.3 USB RAM
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual access memory that is
mapped into the normal data memory space in Bank 2
(200h to 2FFh) for a total of 256 bytes (Figure 22-4).
Bank 2 (200h through 27Fh) is used specifically for
endpoint buffer control. Depending on the type of buffering
being used, all but 8 bytes of Bank 2 may also be
available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 22.4.1.1 “Buffer
Ownership”.
FIGURE 22-4: IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
200h
2FFh
Buffer Descriptors,
USB Data or User Data
SFRs
1FFh
000h
F60h
FFFh
Banks 2
(USB RAM)
F5Fh
F53h
F52h
300h
Banks 3
to 14
User Data
Unused
Banks 15
USB Data or
User Data
27Fh
280h
Banks 0
to 1
2010 Microchip Technology Inc. Preliminary DS41350E-page 259
PIC18F/LF1XK50
22.4 Buffer Descriptors and the Buffer
Descriptor Table
The registers in Bank 2 are used specifically for endpoint
buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four registers,
where n represents one of the 32 possible BDs
(range of 0 to 31):
• BDnSTAT: BD Status register
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1) (in hexadecimal)
from 200h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(Section 22.4.4 “Ping-Pong Buffering”), there are up
to 16, 17 or 32 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB specification mandates that every device must
have Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 128 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint corresponding
to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
An example of a BD for a 64-byte buffer, starting at
280h, is shown in Figure 22-5. A particular set of BD
registers is only valid if the corresponding endpoint has
been enabled using the UEPn register. All BD registers
are available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
22.4.1 BD STATUS AND CONFIGURATION
Buffer descriptors not only define the size of an endpoint
buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.
FIGURE 22-5: EXAMPLE OF A BUFFER
DESCRIPTOR
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
22.4.1.1 Buffer Ownership
Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can configure
the basic operation of the peripheral through the
BDnSTAT bits. During this time, the byte count and buffer
location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
200h
USB Data
Buffer
Buffer
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
201h
202h
203h
280h
2BFh
Descriptor
Note: Memory regions not to scale.
40h
00h
05h
Starting
Size of Block
(xxh)
Address Registers Contents
Address
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DS41350E-page 260 Preliminary 2010 Microchip Technology Inc.
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
22.4.1.2 BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s parity
against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 22-1.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands specified
in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control register
is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD<9:8> bits (BDnSTAT<1:0>) store the two Most
Significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register.
See Section 22.4.2 “BD Byte Count” for more
information.
TABLE 22-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
OUT Packet
from Host
BDnSTAT Settings Device Response after Receiving Packet
DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0 1 0 ACK 0 1 Updated
DATA1 1 0 ACK 1 0 Not Updated
DATA0 1 1 ACK 1 0 Not Updated
DATA1 1 1 ACK 0 1 Updated
Either 0 x ACK 0 1 Updated
Either, with error x x NAK 1 0 Not Updated
Legend: x = don’t care
2010 Microchip Technology Inc. Preliminary DS41350E-page 261
PIC18F/LF1XK50
REGISTER 22-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS(2) —(3) —(3) DTSEN BSTALL BC9 BC8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UOWN: USB Own bit(1)
0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5-4 Unimplemented: These bits should always be programmed to ‘0’(3).
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC<9:8>: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as
‘0’.
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DS41350E-page 262 Preliminary 2010 Microchip Technology Inc.
22.4.1.3 BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 22-6. Once the
UOWN bit is set, any data or control settings previously
written there by the user will be overwritten with data
from the SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
BDnSTAT<5:3>. The transfer count in the corresponding
BDnCNT register is updated. Values that overflow
the 8-bit register carry over to the two Most Significant
digits of the count, stored in BDnSTAT<1:0>.
22.4.2 BD BYTE COUNT
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
22.4.3 BD ADDRESS VALIDATION
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
No mechanism is available in hardware to validate the
BD address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB
applications, the user may want to consider the
inclusion of software-based address validation in their
code.
REGISTER 22-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD31STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU)
R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN — PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID<3:0>: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC<9:8>: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
2010 Microchip Technology Inc. Preliminary DS41350E-page 263
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22.4.4 PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
except Endpoint 0
The ping-pong buffer settings are configured using the
PPB<1:0> bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 22-6 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 22-2. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
FIGURE 22-6: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP1 IN
EP7 IN
EP1 OUT
EP0 OUT
PPB<1:0> = 00
EP0 IN
EP1 IN
No Ping-Pong
EP7 IN
EP0 IN
EP0 OUT Even
PPB<1:0> = 01
EP0 OUT Odd
EP1 OUT
Ping-Pong Buffer
EP7 IN Odd
EP0 IN Even
EP0 OUT Even
PPB<1:0> = 10
EP0 OUT Odd
EP0 IN Odd
Ping-Pong Buffers
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
200h
2FFh 2FFh 2FFh
200h 200h
23Fh
243h
Available
as
Data RAM Available
as
Data RAM
Maximum Memory
Used: 64 bytes
Maximum BDs:
16 (BD0 to BD15)
Maximum Memory
Used: 68 bytes
Maximum BDs:
17 (BD0 to BD16)
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
Note: Memory area not shown to scale.
Descriptor
Descriptor
Descriptor
Descriptor
Buffers on EP0 OUT on all EPs
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP7 IN Odd
EP0 OUT
PPB<1:0> = 11
EP0 IN
Ping-Pong Buffers
Descriptor
Descriptor
Descriptor
2FFh
200h
Maximum Memory
Used: 120 bytes
Maximum BDs:
30 (BD0 to BD29)
on all other EPs
except EP0
Available
as
Data RAM
277h
27Fh
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DS41350E-page 264 Preliminary 2010 Microchip Technology Inc.
TABLE 22-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
TABLE 22-3: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Endpoint
BDs Assigned to Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 2
(Ping-Pong on all EPs)
Mode 3
(Ping-Pong on all other EPs,
except EP0)
Out In Out In Out In Out In
0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1
1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)
5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2)
DTSEN(3)
PID0(2)
BSTALL(3)
BC9 BC8
BDnCNT(1) Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 31. For the sake of brevity, all 32 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.
2010 Microchip Technology Inc. Preliminary DS41350E-page 265
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22.5 USB Interrupts
The USB module can generate multiple interrupt conditions.
To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<2>), in the microcontroller’s
interrupt logic.
Figure 22-7 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
Status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 22-8 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 22-7: USB INTERRUPT LOGIC FUNNEL
FIGURE 22-8: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
STALLIF
STALLIE
ACTVIF
ACTVIE
URSTIF
URSTIE
UERRIF
UERRIE
USBIF
Second Level USB Interrupts
(USB Error Conditions)
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
UIR (Flag) and UIE (Enable) Registers
USB Reset
RESET SOF SETUP DATA STATUS SOF
SETUPToken Data ACK
Start-of-Frame (SOF) OUT Token Empty Data ACK
IN Token Data ACK
SOFIF
URSTIF
1 ms Frame
Differential Data
From Host From Host To Host
From Host To Host From Host
From Host From Host To Host
Transaction
Control Transfer(1)
Transaction
Complete
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
Set TRNIF
Set TRNIF
Set TRNIF
PIC18F/LF1XK50
DS41350E-page 266 Preliminary 2010 Microchip Technology Inc.
22.5.1 USB INTERRUPT STATUS
REGISTER (UIR)
The USB Interrupt Status register (Register 22-7) contains
the flag bits for each of the USB Status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller’s interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.
REGISTER 22-7: UIR: USB INTERRUPT STATUS REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIF: Start-of-Frame Token Interrupt bit
1 = A Start-of-Frame token received by the SIE
0 = No Start-of-Frame token received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
2010 Microchip Technology Inc. Preliminary DS41350E-page 267
PIC18F/LF1XK50
22.5.1.1 Bus Activity Detect Interrupt Bit
(ACTVIF)
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the
USB module is suspended. A few clock cycles are
required to synchronize the internal hardware state
machine before the ACTVIF bit can be cleared by
firmware. Clearing the ACTVIF bit before the internal
hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 48 MHz PLL source, then after
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 48 MHz
PLL to lock. The application code should clear the
ACTVIF flag as shown in Example 22-1.
Only one ACTVIF interrupt is generated when resuming
from the USB bus Idle condition. If user firmware
clears the ACTVIF bit, the bit will not immediately
become set again, even when there is continuous bus
traffic. Bus traffic must cease long enough to generate
another IDLEIF condition before another ACTVIF
interrupt can be generated.
EXAMPLE 22-1: CLEARING ACTVIF BIT (UIR<2>)
Assembly:
BCF UCON, SUSPND
LOOP:
BTFSS UIR, ACTVIF
BRA DONE
BCF UIR, ACTVIF
BRA LOOP
DONE:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
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DS41350E-page 268 Preliminary 2010 Microchip Technology Inc.
22.5.2 USB INTERRUPT ENABLE
REGISTER (UIE)
The USB Interrupt Enable register (Register 22-8)
contains the enable bits for the USB Status interrupt
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
The values in this register only affect the propagation
of an interrupt condition to the microcontroller’s interrupt
logic. The flag bits are still set by their interrupt
conditions, allowing them to be polled and serviced
without actually generating an interrupt.
REGISTER 22-8: UIE: USB INTERRUPT ENABLE REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIE: Start-of-Frame Token Interrupt Enable bit
1 = Start-of-Frame token interrupt enabled
0 = Start-of-Frame token interrupt disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled
2010 Microchip Technology Inc. Preliminary DS41350E-page 269
PIC18F/LF1XK50
22.5.3 USB ERROR INTERRUPT STATUS
REGISTER (UEIR)
The USB Error Interrupt Status register (Register 22-9)
contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources is
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.
Each error bit is set as soon as the error condition is
detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’.
REGISTER 22-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER
R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
bit 7 bit 0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTSEF: Bit Stuff Error Flag bit
1 = A bit stuff error has been detected
0 = No bit stuff error
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed
PIC18F/LF1XK50
DS41350E-page 270 Preliminary 2010 Microchip Technology Inc.
22.5.4 USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)
The USB Error Interrupt Enable register
(Register 22-10) contains the enable bits for each of
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the microcontroller’s
interrupt logic. The flag bits are still set by
their interrupt conditions, allowing them to be polled
and serviced without actually generating an interrupt.
REGISTER 22-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled
2010 Microchip Technology Inc. Preliminary DS41350E-page 271
PIC18F/LF1XK50
22.6 USB Power Modes
Many USB applications will likely have several different
sets of power requirements and configuration. The
most common power modes encountered are Bus
Power Only, Self-Power Only and Dual Power with
Self-Power Dominance. The most common cases are
presented here. Also provided is a means of estimating
the current consumption of the USB transceiver.
22.6.1 BUS POWER ONLY
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 22-9). This is effectively
the simplest power method for the device.
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 μF. If not, some kind of inrush liming is
required. For more details, see section 7.2.4 of the
USB 2.0 specification.
According to the USB 2.0 specification, all USB devices
must also support a Low-Power Suspend mode. In the
USB Suspend mode, devices must consume no more
than 500 A (or 2.5 mA for high powered devices that
are remote wake-up capable) from the 5V VBUS line of
the USB cable.
The host signals the USB device to enter the Suspend
mode by stopping all USB traffic to that device for more
than 3 ms. This condition will cause the IDLEIF bit in
the UIR register to become set.
During the USB Suspend mode, the D+ or D- pull-up
resistor must remain active, which will consume some
of the allowed suspend current: 500 A/2.5 mA budget.
FIGURE 22-9: BUS POWER ONLY
22.6.2 SELF-POWER ONLY
In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled from
the USB. Figure 22-10 shows an example.
In order to meet compliance specifications, the USB
module (and the D+ or D- pull-up resistor) should not
be enabled until the host actively drives VBUS high.
The application should never source any current onto
the 5V VBUS pin of the USB cable.
FIGURE 22-10: SELF-POWER ONLY
VDD
VUSB
VSS
VBUS
VDD
VUSB
VSS
VSELF
PIC18F/LF1XK50
DS41350E-page 272 Preliminary 2010 Microchip Technology Inc.
22.6.3 DUAL POWER WITH SELF-POWER
DOMINANCE
Some applications may require a dual power option.
This allows the application to use internal power primarily,
but switch to power from the USB when no internal
power is available. Figure 22-11 shows a simple
Dual Power with Self-Power Dominance mode example,
which automatically switches between Self-Power
Only and USB Bus Power Only modes.
Dual power devices must also meet all of the special
requirements for inrush current and Suspend mode
current and must not enable the USB module until
VBUS is driven high. See Section 22.6.1 “Bus Power
Only” and Section 22.6.2 “Self-Power Only” for
descriptions of those requirements. Additionally, dual
power devices must never source current onto the 5V
VBUS pin of the USB cable.
FIGURE 22-11: DUAL POWER EXAMPLE
22.6.4 USB TRANSCEIVER CURRENT
CONSUMPTION
The USB transceiver consumes a variable amount of
current depending on the characteristic impedance of
the USB cable, the length of the cable, the VUSB supply
voltage and the actual data patterns moving across the
USB cable. Longer cables have larger capacitances
and consume more total energy when switching output
states.
Data patterns that consist of “IN” traffic consume far
more current than “OUT” traffic. IN traffic requires the
PIC® device to drive the USB cable, whereas OUT
traffic requires that the host drive the USB cable.
The data that is sent across the USB cable is NRZI
encoded. In the NRZI encoding scheme, ‘0’ bits cause
a toggling of the output state of the transceiver (either
from a “J” state to a “K” state, or vise versa). With the
exception of the effects of bit-stuffing, NRZI encoded ‘1’
bits do not cause the output state of the transceiver to
change. Therefore, IN traffic consisting of data bits of
value, ‘0’, cause the most current consumption, as the
transceiver must charge/discharge the USB cable in
order to change states.
More details about NRZI encoding and bit-stuffing can
be found in the USB 2.0 specification’s section 7.1,
although knowledge of such details is not required to
make USB applications using the
PIC18F1XK50/PIC18LF1XK50 of microcontrollers.
Among other things, the SIE handles bit-stuffing/
unstuffing, NRZI encoding/decoding and CRC
generation/checking in hardware.
The total transceiver current consumption will be
application-specific. However, to help estimate how
much current actually may be required in full-speed
applications, Equation 22-1 can be used.
Example 22-2 shows how this equation can be used for
a theoretical application.
Note: Users should keep in mind the limits for
devices drawing power from the USB.
According to USB Specification 2.0, this
cannot exceed 100 mA per low-power
device or 500 mA per high-power device.
VDD
VUSB
VSS
VBUS
VSELF
~5V
~5V
100 k
2010 Microchip Technology Inc. Preliminary DS41350E-page 273
PIC18F/LF1XK50
EQUATION 22-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION
EXAMPLE 22-2: CALCULATING USB TRANSCEIVER CURRENT†
IXCVR = + IPULLUP
(60 mA • VUSB • PZERO • PIN • LCABLE)
(3.3V • 5m)
Legend: VUSB: Voltage applied to the VUSB pin in volts. (Should be 3.0V to 3.6V.)
PZERO: Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’.
PIN: Percentage (in decimal) of total bus bandwidth that is used for IN traffic.
LCABLE: Length (in meters) of the USB cable. The USB 2.0 specification requires that full-speed applications
use cables no longer than 5m.
IPULLUP: Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable. On
the host or hub end of the USB cable, 15 k nominal resistors (14.25 k to 24.8 k) are present which
pull both the D+ and D- lines to ground. During bus Idle conditions (such as between packets or during
USB Suspend mode), this results in up to 218 A of quiescent current drawn at 3.3V.
IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2 mA when the USB bandwidth
is fully utilized (either IN or OUT traffic) for data that drives the lines to the “K” state most of the time.
For this example, the following assumptions are made about the application:
• 3.3V will be applied to VUSB and VDD, with the core voltage regulator enabled.
• This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every
1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have additional
traffic on OUT endpoints.
• A regular USB “B” or “mini-B” connector will be used on the application circuit board.
In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through
the IN endpoint. All 64 kBps of data could potentially be bytes of value, 00h. Since ‘0’ bits cause toggling of the
output state of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the
cable. In this case, 100% of the data bits sent can be of value ‘0’. This should be considered the “max” value, as
normal data will consist of a fair mix of ones and zeros.
This application uses 64 kBps for IN traffic out of the total bus bandwidth of 1.5 MBps (12 Mbps), therefore:
Since a regular “B” or “mini-B” connector is used in this application, the end user may plug in any type of cable up
to the maximum allowed 5 m length. Therefore, we use the worst-case length:
LCABLE = 5 meters
Assume IPULLUP = 2.2 mA. The actual value of IPULLUP will likely be closer to 218 A, but allow for the worst-case.
USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application
is plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on
the bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP
current above the base 218 A, it is safest to allow for the worst-case of 2.2 mA.
Therefore:
The calculated value should be considered an approximation and additional guardband or application-specific product
testing is recommended. The transceiver current is “in addition to” the rest of the current consumed by the
PIC18F1XK50/PIC18LF1XK50 device that is needed to run the core, drive the other I/O lines, power the various
modules, etc.
Pin =
64 kBps
1.5 MBps = 4.3% = 0.043
IXCVR = (60 mA • 3.3V • 1 • 0.043 • 5m) + 2.2 mA = 4.8 mA
(3.3V • 5m)
PIC18F/LF1XK50
DS41350E-page 274 Preliminary 2010 Microchip Technology Inc.
22.7 Oscillator
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed. Available
clocking options are described in detail in Section 2.11
“USB Operation”.
22.8 Interrupt-On-Change for D+/Dpins
The PIC18F/LF1XK50 has interrupt-on-change functionality
on both D+ and D- data pins. This feature
allows the device to detect voltage level changes
when first connected to a USB host/hub.
The USB host/hub has 15K pull-down resistors on the D+
and D- pins. When the PIC18F/LF1XK50 attaches to the
bus the D+ and D- pins can detect voltage changes.
External resistors are needed for each pin to maintain a
high state on the pins when detached.
The USB module must be disable (USBEN = 0) for the
interrupt-on-change to function. Enabling the USB
module (USBEN = 1) will automatically disable the
interrupt-on-change for D+ and D- pins. Refer to
Section 7.11 “PORTA and PORTB Interrupt-
on-Change” for mode detail.
22.9 USB Firmware and Drivers
Microchip provides a number of application-specific
resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.
TABLE 22-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on
Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 70
IPR2 OSCFIP C1IP C2IP EEIP BCL1IP USBIP TMR3IP — 78
PIR2 OSCFIF C1IF C2IF EEIF BCL1IF USBIF TMR3IF — 74
PIE2 OSCFIE C1IE C2IE EEIE BCL1IE USBIE TMR3IE — 76
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 252
UCFG UTEYE — — UPUEN — FSEN PPB1 PPB0 254
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 256
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 258
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 252
UFRMH — — — — — FRM10 FRM9 FRM8 252
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 266
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 268
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 269
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 270
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 22-3.
2010 Microchip Technology Inc. Preliminary DS41350E-page 275
PIC18F/LF1XK50
22.10 Overview of USB
This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
section serves as a basic, high-level refresher of USB.
22.10.1 LAYERED FRAMEWORK
USB device functionality is structured into a layered
framework graphically shown in Figure 22-12. Each
level is associated with a functional level within the
device. The highest layer, other than the device, is the
configuration. A device may have multiple configurations.
For example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always a
control endpoint and by default, when the device is on
the bus, Endpoint 0 must be available to configure the
device.
22.10.2 FRAMES
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 22-8 shows an example of a
transaction within a frame.
22.10.3 TRANSFERS
There are four transfer types defined in the USB
specification.
• Isochronous: This type provides a transfer
method for large amounts of data (up to
1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This is
good for streaming applications where small data
loss is not critical, such as audio.
• Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
• Interrupt: This type of transfer provides for
ensured timely delivery for small blocks of data,
plus data integrity is ensured.
• Control: This type provides for device setup
control.
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.
22.10.4 POWER
Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an external
source, while bus powered devices use power supplied
from the bus.
FIGURE 22-12: USB LAYERS
Device
Configuration
Interface
Endpoint
Interface
Endpoint Endpoint Endpoint Endpoint
To other Configurations (if any)
To other Interfaces (if any)
PIC18F/LF1XK50
DS41350E-page 276 Preliminary 2010 Microchip Technology Inc.
The USB specification limits the power taken from the
bus. Each device is ensured 100 mA at approximately
5V (one unit load). Additional power may be requested,
up to a maximum of 500 mA. Note that power above
one unit load is a request and the host or hub is not
obligated to provide the extra current. Thus, a device
capable of consuming more than one unit load must be
able to maintain a low-power configuration of a one unit
load or less, if necessary.
The USB specification also defines a Suspend mode.
In this situation, current must be limited to 500 A,
averaged over 1 second. A device must enter a
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode
must drop current consumption within 10 ms after
Suspend. Likewise, when signaling a wake-up, the
device must signal a wake-up within 10 ms of drawing
current above the Suspend limit.
22.10.5 ENUMERATION
When the device is initially attached to the bus, the host
enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,
gathering information such as power consumption, data
rates and sizes, protocol and other descriptive
information; descriptors contain this information. A
typical enumeration process would be as follows:
1. USB Reset: Reset the device. Thus, the device
is not configured and does not have an address
(address 0).
2. Get Device Descriptor: The host requests a
small portion of the device descriptor.
3. USB Reset: Reset the device again.
4. Set Address: The host assigns an address to the
device.
5. Get Device Descriptor: The host retrieves the
device descriptor, gathering info such as
manufacturer, type of device, maximum control
packet size.
6. Get configuration descriptors.
7. Get any other descriptors.
8. Set a configuration.
The exact enumeration process depends on the host.
22.10.6 DESCRIPTORS
There are eight different standard descriptor types of
which five are most important for this device.
22.10.6.1 Device Descriptor
The device descriptor provides general information,
such as manufacturer, product number, serial number,
the class of the device and the number of configurations.
There is only one device descriptor.
22.10.6.2 Configuration Descriptor
The configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this configuration.
There may be more than one configuration for a
device (i.e., low-power and high-power configurations).
22.10.6.3 Interface Descriptor
The interface descriptor details the number of endpoints
used in this interface, as well as the class of the
interface. There may be more than one interface for a
configuration.
22.10.6.4 Endpoint Descriptor
The endpoint descriptor identifies the transfer type
(Section 22.10.3 “Transfers”) and direction, as well
as some other specifics for the endpoint. There may be
many endpoints in a device and endpoints may be
shared in different configurations.
22.10.6.5 String Descriptor
Many of the previous descriptors reference one or
more string descriptors. String descriptors provide
human readable information about the layer
(Section 22.10.1 “Layered Framework”) they
describe. Often these strings show up in the host to
help the user identify the device. String descriptors are
generally optional to save memory and are encoded in
a unicode format.
22.10.7 BUS SPEED
Each USB device must indicate its bus presence and
speed to the host. This is accomplished through a
1.5 k resistor which is connected to the bus at the
time of the attachment event.
Depending on the speed of the device, the resistor
either pulls up the D+ or D- line to 3.3V. For a
low-speed device, the pull-up resistor is connected to
the D- line. For a full-speed device, the pull-up resistor
is connected to the D+ line.
22.10.8 CLASS SPECIFICATIONS AND
DRIVERS
USB specifications include class specifications which
operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
Communications and Human Interface (HID). In most
cases, a driver is required at the host side to ‘talk’ to the
USB device. In custom applications, a driver may need
to be developed. Fortunately, drivers are available for
most common host systems for the most common
classes of devices. Thus, these drivers can be reused.
2010 Microchip Technology Inc. Preliminary DS41350E-page 277
PIC18F/LF1XK50
23.0 RESET
The PIC18F/LF1XK50 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 3.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 23-1.
23.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 23-1). The lower five bits of the register
indicate that a specific Reset event has occurred.
In most cases, these bits can only be cleared by the
event and must be set by the application after the
event. The state of these flag bits, taken together, can
be read to indicate the type of Reset that just occurred.
This is described in more detail in Section 23.6 “Reset
State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 7.0 “Interrupts”. BOR is covered in
Section 23.4 “Brown-out Reset (BOR)”.
FIGURE 23-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
LFINTOSC
POR Pulse
OST(2)
10-bit Ripple Counter
PWRT(2)
11-bit Ripple Counter
Enable OST(1)
Enable PWRT
Note 1: See Table 23-2 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR. See Sections 23.3 and 23.4.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
32 s 65.5 ms
MCLRE
S
R Q
Chip_Reset
PIC18F/LF1XK50
DS41350E-page 278 Preliminary 2010 Microchip Technology Inc.
REGISTER 23-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN(1) — RI TO PD POR(2) BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware or Power-on Reset)
0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a
code-executed Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit(3)
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 23.6 “Reset State of Registers” for additional information.
3: See Table 23-3.
2010 Microchip Technology Inc. Preliminary DS41350E-page 279
PIC18F/LF1XK50
23.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F/LF1XK50 devices, the MCLR input can be
disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See
Section 9.1 “PORTA, TRISA and LATA Registers”
for more information.
23.3 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit of the RCON
register. The state of the bit is set to ‘0’ whenever a
POR occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user must manually set
the bit to ‘1’ by software following any POR.
FIGURE 23-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 1 k will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
D R
VDD
MCLR
VDD
PIC® MCU
PIC18F/LF1XK50
DS41350E-page 280 Preliminary 2010 Microchip Technology Inc.
23.4 Brown-out Reset (BOR)
PIC18F/LF1XK50 devices implement a BOR circuit that
provides the user with a number of configuration and
power-saving options. The BOR is controlled by the
BORV<1:0> and BOREN<1:0> bits of the CONFIG2L
Configuration register. There are a total of four BOR
configurations which are summarized in Table 23-1.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below VBOR for greater than
TBOR will reset the device. A Reset may or may not
occur if VDD falls below VBOR for less than TBOR. The
chip will remain in Brown-out Reset until VDD rises
above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT. If VDD drops
below VBOR while the Power-up Timer is running, the
chip will go back into a Brown-out Reset and the
Power-up Timer will be initialized. Once VDD rises
above VBOR, the Power-up Timer will execute the
additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
23.4.1 SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
SBOREN control bit of the RCON register. Setting
SBOREN enables the BOR to function as previously
described. Clearing SBOREN disables the BOR
entirely. The SBOREN bit operates only in this mode;
otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very small,
it may have some impact in low-power applications.
23.4.2 DETECTING BOR
When BOR is enabled, the BOR bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR and BOR bits are reset to
‘1’ by software immediately after any POR event. If
BOR is ‘0’ while POR is ‘1’, it can be reliably assumed
that a BOR event has occurred.
23.4.3 DISABLING BOR IN SLEEP MODE
When BOREN<1:0> = 10, the BOR remains under
hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 23-1: BOR CONFIGURATIONS
Note: Even when BOR is under software control,
the BOR Reset voltage level is still set
by the BORV<1:0> Configuration bits. It
cannot be changed by software.
BOR Configuration Status of
SBOREN
(RCON<6>)
BOR Operation
BOREN1 BOREN0
0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
0 1 Available BOR enabled by software; operation controlled by SBOREN.
1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during
Sleep mode.
1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the
Configuration bits.
2010 Microchip Technology Inc. Preliminary DS41350E-page 281
PIC18F/LF1XK50
23.5 Device Reset Timers
PIC18F/LF1XK50 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
23.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18F/LF1XK50
devices is an 11-bit counter which uses the LFINTOSC
source as the clock input. This yields an
approximate time interval of 2048 x 32 s = 65.6ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See Section 27.0 “Electrical
Specifications” for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
23.5.2 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from all power-managed modes that stop the external
oscillator.
23.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (TPLL) is typically 2 ms and follows
the oscillator start-up time-out.
23.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 23-3,
Figure 23-4, Figure 23-5, Figure 23-6 and Figure 23-7
all depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 23-3 through 23-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately (Figure 23-5). This is
useful for testing purposes or to synchronize more than
one PIC18F1XK50/PIC18LF1XK50 device operating in
parallel.
TABLE 23-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
PWRTEN = 0 PWRTEN = 1 Power-Managed Mode
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) — —
RC, RCIO 66 ms(1) — —
INTIO1, INTIO2 66 ms(1) — —
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
PIC18F/LF1XK50
DS41350E-page 282 Preliminary 2010 Microchip Technology Inc.
FIGURE 23-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 23-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 23-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
2010 Microchip Technology Inc. Preliminary DS41350E-page 283
PIC18F/LF1XK50
FIGURE 23-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 23-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
PIC18F/LF1XK50
DS41350E-page 284 Preliminary 2010 Microchip Technology Inc.
23.6 Reset State of Registers
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 23-3.
These bits are used by software to determine the
nature of the Reset.
Table 23-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 23-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition Program
Counter
RCON Register STKPTR Register
SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
Brown-out Reset 0000h u(2) 1 1 1 u 0 u u
MCLR during Power-Managed
Run Modes
0000h u(2) u 1 u u u u u
MCLR during Power-Managed
Idle Modes and Sleep Mode
0000h u(2) u 1 0 u u u u
WDT Time-out during Full Power
or Power-Managed Run Mode
0000h u(2) u 0 u u u u u
MCLR during Full Power
Execution
0000h u(2) u u u u u u u
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
Stack Underflow Reset
(STVREN = 1)
0000h u(2) u u u u u u 1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h u(2) u u u u u u 1
WDT Time-out during
Power-Managed Idle or Sleep
Modes
PC + 2 u(2) u 0 0 u u u u
Interrupt Exit from
Power-Managed Modes
PC + 2(1) u(2) u u 0 u u u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’.
2010 Microchip Technology Inc. Preliminary DS41350E-page 285
PIC18F/LF1XK50
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Address Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU FFFh ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH FFEh 0000 0000 0000 0000 uuuu uuuu(3)
TOSL FFDh 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR FFCh 00-0 0000 uu-0 0000 uu-u uuuu(3)
PCLATU FFBh ---0 0000 ---0 0000 ---u uuuu
PCLATH FFAh 0000 0000 0000 0000 uuuu uuuu
PCL FF9h 0000 0000 0000 0000 PC + 2(2)
TBLPTRU FF8h ---0 0000 ---0 0000 ---u uuuu
TBLPTRH FF7h 0000 0000 0000 0000 uuuu uuuu
TBLPTRL FF6h 0000 0000 0000 0000 uuuu uuuu
TABLAT FF5h 0000 0000 0000 0000 uuuu uuuu
PRODH FF4h xxxx xxxx uuuu uuuu uuuu uuuu
PRODL FF3h xxxx xxxx uuuu uuuu uuuu uuuu
INTCON FF2h 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 FF1h 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 FF0h 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 FEFh N/A N/A N/A
POSTINC0 FEEh N/A N/A N/A
POSTDEC0 FEDh N/A N/A N/A
PREINC0 FECh N/A N/A N/A
PLUSW0 FEBh N/A N/A N/A
FSR0H FEAh ---- 0000 ---- 0000 ---- uuuu
FSR0L FE9h xxxx xxxx uuuu uuuu uuuu uuuu
WREG FE8h xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 FE7h N/A N/A N/A
POSTINC1 FE6h N/A N/A N/A
POSTDEC1 FE5h N/A N/A N/A
PREINC1 FE4h N/A N/A N/A
PLUSW1 FE3h N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 23-3 for Reset value for specific condition.
5: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
PIC18F/LF1XK50
DS41350E-page 286 Preliminary 2010 Microchip Technology Inc.
FSR1H FE2h ---- 0000 ---- 0000 ---- uuuu
FSR1L FE1h xxxx xxxx uuuu uuuu uuuu uuuu
BSR FE0h ---- 0000 ---- 0000 ---- uuuu
INDF2 FDFh N/A N/A N/A
POSTINC2 FDEh N/A N/A N/A
POSTDEC2 FDDh N/A N/A N/A
PREINC2 FDCh N/A N/A N/A
PLUSW2 FDBh N/A N/A N/A
FSR2H FDAh ---- 0000 ---- 0000 ---- uuuu
FSR2L FD9h xxxx xxxx uuuu uuuu uuuu uuuu
STATUS FD8h ---x xxxx ---u uuuu ---u uuuu
TMR0H FD7h 0000 0000 0000 0000 uuuu uuuu
TMR0L FD6h xxxx xxxx uuuu uuuu uuuu uuuu
T0CON FD5h 1111 1111 1111 1111 uuuu uuuu
OSCCON FD3h 0011 qq00 0011 qq00 uuuu uuuu
OSCCON2 FD2h ---- -10x ---- -10x ---- -uuu
WDTCON FD1h ---- ---0 ---- ---0 ---- ---u
RCON(4) FD0h 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H FCFh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L FCEh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON FCDh 0000 0000 u0uu uuuu uuuu uuuu
TMR2 FCCh 0000 0000 0000 0000 uuuu uuuu
PR2 FCBh 1111 1111 1111 1111 1111 1111
T2CON FCAh -000 0000 -000 0000 -uuu uuuu
SSPBUF FC9h xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD FC8h 0000 0000 0000 0000 uuuu uuuu
SSPSTAT FC7h 0000 0000 0000 0000 uuuu uuuu
SSPCON1 FC6h 0000 0000 0000 0000 uuuu uuuu
SSPCON2 FC5h 0000 0000 0000 0000 uuuu uuuu
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Address Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 23-3 for Reset value for specific condition.
5: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
2010 Microchip Technology Inc. Preliminary DS41350E-page 287
PIC18F/LF1XK50
ADRESH FC4h xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL FC3h xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 FC2h --00 0000 --00 0000 --uu uuuu
ADCON1 FC1h ---- 0000 ---- 0000 ---- uuuu
ADCON2 FC0h 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H FBFh xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L FBEh xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON FBDh 0000 0000 0000 0000 uuuu uuuu
REFCON2 FBCh ---0 0000 ---0 0000 ---u uuuu
REFCON1 FBBh 000- 00-0 000- 00-0 uuu- uu-u
REFCON0 FBAh 0001 00-- 0001 00-- uuuu uu--
PSTRCON FB9h ---0 0001 ---0 0001 ---u uuuu
BAUDCON FB8h 0100 0-00 0100 0-00 uuuu u-uu
PWM1CON FB7h 0000 0000 0000 0000 uuuu uuuu
ECCP1AS FB6h 0000 0000 0000 0000 uuuu uuuu
TMR3H FB3h xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L FB2h xxxx xxxx uuuu uuuu uuuu uuuu
T3CON FB1h 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH FB0h 0000 0000 0000 0000 uuuu uuuu
SPBRG FAFh 0000 0000 0000 0000 uuuu uuuu
RCREG FAEh 0000 0000 0000 0000 uuuu uuuu
TXREG FADh 0000 0000 0000 0000 uuuu uuuu
TXSTA FACh 0000 0010 0000 0010 uuuu uuuu
RCSTA FABh 0000 000x 0000 000x uuuu uuuu
EEADR FAAh 0000 0000 0000 0000 uuuu uuuu
EEDATA FA8h 0000 0000 0000 0000 uuuu uuuu
EECON2 FA7h 0000 0000 0000 0000 0000 0000
EECON1 FA6h xx-0 x000 uu-0 u000 uu-0 u000
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Address Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 23-3 for Reset value for specific condition.
5: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
PIC18F/LF1XK50
DS41350E-page 288 Preliminary 2010 Microchip Technology Inc.
IPR2 FA2h 1111 111- 1111 111- uuuu uuu-
PIR2 FA1h 0000 000- 0000 000- uuuu uuu-(1)
PIE2 FA0h 0000 000- 0000 000- uuuu uuu-
IPR1 F9Fh -111 1111 -111 1111 -uuu uuuu
PIR1 F9Eh -000 0000 -000 0000 -uuu uuuu(1)
PIE1 F9Dh -000 0000 -000 0000 -uuu uuuu
OSCTUNE F9Bh 0000 0000 0000 0000 uuuu uuuu
TRISC F95h 1111 1111 1111 1111 uuuu uuuu
TRISB F94h 1111 ---- 1111 ---- uuuu ----
TRISA F93h --11 ---- --11 ---- --uu ----
LATC F8Bh xxxx xxxx uuuu uuuu uuuu uuuu
LATB F8Ah xxxx ---- uuuu ---- uuuu ----
LATA F89h --xx ---- --uu ---- --uu ----
PORTC F82h xxxx xxxx uuuu uuuu uuuu uuuu
PORTB F81h xxxx ---- uuuu ---- uuuu ----
PORTA F80h --xx x-xx --xx x-xx --uu u-uu
ANSELH(5) F7Fh ---- 1111 ---- 1111 ---- uuuu
ANSEL F7Eh 1111 1--- 1111 1--- uuuu u---
IOCB F7Ah 0000 ---- 0000 ---- uuuu ----
IOCA F79h --00 0-00 --00 0-00 --uu u-uu
WPUB F78h 1111 ---- 1111 ---- uuuu ----
WPUA F77h --11 1--- --11 1--- --uu u---
SLRCON F76h ---- -111 ---- -111 ---- -uuu
SSPMSK F6Fh 1111 1111 1111 1111 uuuu uuuu
CM1CON0 F6Dh 0000 0000 0000 0000 uuuu uuuu
CM2CON1 F6Ch 0000 0000 0000 0000 uuuu uuuu
CM2CON0 F6Bh 0000 0000 0000 0000 uuuu uuuu
SRCON1 F69h 0000 0000 0000 0000 uuuu uuuu
SRCON0 F68h 0000 0000 0000 0000 uuuu uuuu
UCON F64h -0x0 000- -0x0 000- -uuu uuu-
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Address Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 23-3 for Reset value for specific condition.
5: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
2010 Microchip Technology Inc. Preliminary DS41350E-page 289
PIC18F/LF1XK50
USTAT F63h -xxx xxx- -xxx xxx- -uuu uuu-
UIR F62h -000 0000 -000 0000 -uuu uuuu
UCFG F61h 0--0 -000 0--0 -000 u--u -uuu
UIE F60h -000 0000 -000 0000 -uuu uuuu
UEIR F5Fh 0--0 0000 0--0 0000 u--u uuuu
UFRMH F5Eh ---- -xxx ---- -xxx ---- -uuu
UFRML F5Dh xxxx xxxx xxxx xxxx uuuu uuuu
UADDR F5Ch -000 0000 -000 0000 -uuu uuuu
UEIE F5Bh 0--0 0000 0--0 0000 u--u uuuu
UEP7 F5Ah ----0 0000 ----0 0000 ----u uuuu
UEP6 F59h ----0 0000 ----0 0000 ----u uuuu
UEP5 F58h ----0 0000 ----0 0000 ----u uuuu
UEP4 F57h ----0 0000 ----0 0000 ----u uuuu
UEP3 F56h ----0 0000 ----0 0000 ----u uuuu
UEP2 F55h ----0 0000 ----0 0000 ----u uuuu
UEP1 F54h ----0 0000 ----0 0000 ----u uuuu
UEP0 F53h ----0 0000 ----0 0000 ----u uuuu
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Address Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 23-3 for Reset value for specific condition.
5: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
PIC18F/LF1XK50
DS41350E-page 290 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 291
PIC18F/LF1XK50
24.0 SPECIAL FEATURES OF
THE CPU
PIC18F/LF1XK50 devices include several features
intended to maximize reliability and minimize cost through
elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Module”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F/LF1XK50 devices
have a Watchdog Timer, which is either permanently
enabled via the Configuration bits or software controlled
(if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
PIC18F/LF1XK50
DS41350E-page 292 Preliminary 2010 Microchip Technology Inc.
24.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 4.5 “Writing
to Flash Program Memory”.
TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
300000h CONFIG1L — — USBDIV CPUDIV1 CPUDIV0 — — — --00 0---
300001h CONFIG1H IESO FCMEN PCLKEN PLLEN FOSC3 FOSC2 FOSC1 FOSC0 0010 0111
300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — HFOFST — — — 1--- 1---
300006h CONFIG4L BKBUG(2) ENHCPU — — BBSIZ LVP — STVREN -0-- 01-1
300008h CONFIG5L — — — — — — CP1 CP0 ---- --11
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 qqqq qqqq(1)
3FFFFFh DEVID2(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’
Note 1: See Register 24-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
2: BKBUG is only used for the ICD device. Otherwise, this bit is unimplemented and reads as ‘1’.
2010 Microchip Technology Inc. Preliminary DS41350E-page 293
PIC18F/LF1XK50
REGISTER 24-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW
U-0 U-0 R/P-0 R/P-0 R/P-0 U-0 U-0 U-0
— — USBDIV CPUDIV1 CPUDIV0 — — —
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 USBDIV: USB Clock Selection bit
Selects the clock source for Low-speed USB operation
1 = USB clock comes from the OSC1/OSC2 divided by 2
0 = USB clock comes directly from the OSC1/OSC2 Oscillator block; no divide
bit 4-3 CPUDIV<1:0>: CPU System Clock Selection bits
11 = CPU system clock divided by 4
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide
bit 2-0 Unimplemented: Read as ‘0’
PIC18F/LF1XK50
DS41350E-page 294 Preliminary 2010 Microchip Technology Inc.
REGISTER 24-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH
R/P-0 R/P-0 R/P-1 R/P-0 R/P-0 R/P-1 R/P-1 R/P-1
IESO FCMEN PCLKEN PLLEN FOSC3 FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 IESO: Internal/External Oscillator Switchover bit
1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 5 PCLKEN: Primary Clock Enable bit
1 = Primary Clock enabled
0 = Primary Clock is under software control
bit 4 PLLEN: 4 X PLL Enable bit
1 = Oscillator multiplied by 4
0 = PLL is under software control
bit 3-0 FOSC<3:0>: Oscillator Selection bits
1111 = External RC oscillator, CLKOUT function on OSC2
1110 = External RC oscillator, CLKOUT function on OSC2
1101 = EC (low)
1100 = EC, CLKOUT function on OSC2 (low)
1011 = EC (medium)
1010 = EC, CLKOUT function on OSC2 (medium)
1001 = Internal RC oscillator, CLKOUT function on OSC2
1000 = Internal RC oscillator
0111 = External RC oscillator
0110 = External RC oscillator, CLKOUT function on OSC2
0101 = EC (high)
0100 = EC, CLKOUT function on OSC2 (high)
0011 = External RC oscillator, CLKOUT function on OSC2
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
2010 Microchip Technology Inc. Preliminary DS41350E-page 295
PIC18F/LF1XK50
REGISTER 24-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2)
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1)
11 = VBOR set to 1.9V nominal
10 = VBOR set to 2.2V nominal
01 = VBOR set to 2.7V nominal
00 = VBOR set to 3.0V nominal
bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2)
11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode
(SBOREN is disabled)
01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset disabled in hardware and software
bit 0 PWRTEN: Power-up Timer Enable bit(2)
1 = PWRT disabled
0 = PWRT enabled
Note 1: See Table 27-5 for specifications.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.
PIC18F/LF1XK50
DS41350E-page 296 Preliminary 2010 Microchip Technology Inc.
REGISTER 24-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT is always enabled. SWDTEN bit has no effect
0 = WDT is controlled by SWDTEN bit of the WDTCON register
2010 Microchip Technology Inc. Preliminary DS41350E-page 297
PIC18F/LF1XK50
REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1 U-0 U-0 U-0 R/P-1 U-0 U-0 U-0
MCLRE — — — HFOFST — — —
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RA3 input pin disabled
0 = RA3 input pin enabled; MCLR disabled
bit 6-4 Unimplemented: Read as ‘0’
bit 3 HFOFST: HFINTOSC Fast Start-up bit
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize.
0 = The system clock is held off until the HFINTOSC is stable.
bit 2-0 Unimplemented: Read as ‘0’
REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW
R/W-1(1) R/W-0 U-0 U-0 R/P-0 R/P-1 U-0 R/P-1
BKBUG ENHCPU — — BBSIZ LVP — STVREN
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 BKBUG: Background Debugger Enable bit(1)
1 = Background debugger disabled
0 = Background debugger functions enabled
bit 6 ENHCPU: Enhanced CPU Enable bit
1 = Enhanced CPU enabled
0 = Enhanced CPU disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3 BBSIZ: Boot BLock Size Select bit
1 = 2 kW boot block size for PIC18F14K50/PIC18LF14K50 (1 kW boot block size for
PIC18F13K50/PIC18LF13K50)
0 = 1 kW boot block size for PIC18F14K50/PIC18LF14K50 (512 W boot block size for
PIC18F13K50/PIC18LF13K50)
bit 2 LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: BKBUG is only used for the ICD device. Otherwise, this bit is unimplemented and reads as ‘1’.
PIC18F/LF1XK50
DS41350E-page 298 Preliminary 2010 Microchip Technology Inc.
REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — CP1 CP0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-2 Unimplemented: Read as ‘0’
bit 1 CP1: Code Protection bit
1 = Block 1 not code-protected
0 = Block 1 code-protected
bit 0 CP0: Code Protection bit
1 = Block 0 not code-protected
0 = Block 0 code-protected
REGISTER 24-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH
R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
CPD CPB — — — — — —
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7 CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
bit 6 CPB: Boot Block Code Protection bit
1 = Boot block not code-protected
0 = Boot block code-protected
bit 5-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 299
PIC18F/LF1XK50
REGISTER 24-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — WRT1 WRT0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-2 Unimplemented: Read as ‘0’
bit 1 WRT1: Write Protection bit
1 = Block 1 not write-protected
0 = Block 1 write-protected
bit 0 WRT0: Write Protection bit
1 = Block 0 not write-protected
0 = Block 0 write-protected
REGISTER 24-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH
R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0
WRTD WRTB WRTC(1) — — — — —
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7 WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
bit 6 WRTB: Boot Block Write Protection bit
1 = Boot block not write-protected
0 = Boot block write-protected
bit 5 WRTC: Configuration Register Write Protection bit(1)
1 = Configuration registers not write-protected
0 = Configuration registers write-protected
bit 4-0 Unimplemented: Read as ‘0’
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
PIC18F/LF1XK50
DS41350E-page 300 Preliminary 2010 Microchip Technology Inc.
REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — EBTR1 EBTR0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-2 Unimplemented: Read as ‘0’
bit 1 EBTR1: Table Read Protection bit
1 = Block 1 not protected from table reads executed in other blocks
0 = Block 1 protected from table reads executed in other blocks
bit 0 EBTR0: Table Read Protection bit
1 = Block 0 not protected from table reads executed in other blocks
0 = Block 0 protected from table reads executed in other blocks
REGISTER 24-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH
U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
— EBTRB — — — — — —
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7 Unimplemented: Read as ‘0’
bit 6 EBTRB: Boot Block Table Read Protection bit
1 = Boot block not protected from table reads executed in other blocks
0 = Boot block protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 301
PIC18F/LF1XK50
REGISTER 24-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1XK50/PIC18LF1XK50
R R R R R R R R
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-5 DEV<2:0>: Device ID bits
010 = PIC18F13K50
011 = PIC18F14K50
bit 4-0 REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 24-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1XK50/PIC18LF1XK50
R R R R R R R R
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
bit 7-0 DEV<10:3>: Device ID bits
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the
part number.
0010 0000 = PIC18F1XK50/PIC18LF1XK50 devices
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified
by using the entire DEV<10:0> bit sequence.
PIC18F/LF1XK50
DS41350E-page 302 Preliminary 2010 Microchip Technology Inc.
24.2 Watchdog Timer (WDT)
For PIC18F/LF1XK50 devices, the WDT is driven by
the LFINTOSC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the LFINTOSC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configuration
Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.
FIGURE 24-1: WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits of
the OSCCON register clears the WDT
and postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
LFINTOSC Source
WDT
Wake-up
Reset
WDT Counter
Programmable Postscaler
1:1 to 1:32,768
Enable WDT
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
4
from Power
Reset
All Device Resets
Sleep
128
Change on IRCF bits
Managed Modes
2010 Microchip Technology Inc. Preliminary DS41350E-page 303
PIC18F/LF1XK50
24.2.1 CONTROL REGISTER
Register 24-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS
24.3 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® microcontroller devices.
The user program memory is divided into five blocks.
One of these is a boot block of 0.5K or 2K bytes,
depending on the device. The remainder of the memory
is divided into individual blocks on binary boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
REGISTER 24-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — SWDTEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
RCON IPEN SBOREN — RI TO PD POR BOR 278
WDTCON — — — — — — — SWDTEN 286
CONFIG2H WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 296
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
PIC18F/LF1XK50
DS41350E-page 304 Preliminary 2010 Microchip Technology Inc.
FIGURE 24-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F/LF1XK50
Device
Address (from/to) 14K50 13K50
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
0000h
01FFh
Boot Block, 2 KW
CPB, WRTB, EBTRB
Boot Block, 1 KW
CPB, WRTB, EBTRB
Boot Block, 1 KW
CPB, WRTB, EBTRB
Boot Block, 0.512 KW
CPB, WRTB, EBTRB
0200h
03FFh
Block 0
1.512 KW
0400h CP0, WRT0, EBTR0
05FFh
Block 0
3 KW
CP0, WRT0, EBTR0
Block 0
1 KW
0600h CP0, WRT0, EBTR0
07FFh
0800h
0FFFh
Block 0
2 KW
CP0, WRT0, EBTR0
Block 1
2 KW
CP1, WRT1, EBTR1
Block 1
2 KW
CP1, WRT1, EBTR1
1000h
1FFFh
Block 1
4 KW
CP1, WRT1, EBTR1
Block 1
4 KW
CP1, WRT1, EBTR1
Reads all ‘0’s Reads all ‘0’s
2000h
27FFh
Reads all ‘0’s Reads all ‘0’s
2800h
2FFFh
3000h
37FFh
3800h
3FFFh
4000h
47FFh
4800h
4FFFh
5000h
57FFh
5800h
5FFFh
6000h
67FFh
6800h
6FFFh
7000h
77FFh
7800h
7FFFh
8000h
FFFFh
Note: Refer to the test section for requirements on test memory mapping.
2010 Microchip Technology Inc. Preliminary DS41350E-page 305
PIC18F/LF1XK50
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
24.3.1 PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit cleared to ‘0’, a table READ instruction that executes
from within that block is allowed to read. A table read
instruction that executes from a location outside of that
block is not allowed to read and will result in reading ‘0’s.
Figures 24-3 through 24-5 illustrate table write and table
read protection.
FIGURE 24-3: TABLE WRITE (WRTn) DISALLOWED
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — — — — CP1 CP0
300009h CONFIG5H CPD CPB — — — — — —
30000Ah CONFIG6L — — — — — — WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC — — — — —
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
Note: Code protection bits may only be written
to a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code protection
bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLWT*
TBLPTR = 0008FFh
PC = 001FFEh
PC = 005FFEh TBLWT*
Register Values Program Memory Configuration Bit Settings
Results: All table writes disabled to Blockn whenever WRTn = 0.
PIC18F/LF1XK50
DS41350E-page 306 Preliminary 2010 Microchip Technology Inc.
FIGURE 24-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLRD*
TBLPTR = 0008FFh
PC = 003FFEh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
Register Values Program Memory Configuration Bit Settings
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLRD*
TBLPTR = 0008FFh
PC = 001FFEh
Register Values Program Memory Configuration Bit Settings
Results: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
2010 Microchip Technology Inc. Preliminary DS41350E-page 307
PIC18F/LF1XK50
24.3.2 DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can always read data EEPROM
under normal operation, regardless of the protection bit
settings.
24.3.3 CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
24.4 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.
24.5 In-Circuit Serial Programming
PIC18F/LF1XK50 devices can be serially programmed
while in the end application circuit. This is simply done
with two lines for clock and data and three other lines
for power, ground and the programming voltage. This
allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
24.6 In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 24-4 shows which resources are
required by the background debugger.
TABLE 24-4: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the
microcontroller, the design must implement In-Circuit
Serial Programming connections to the following pins:
• MCLR/VPP/RA3
• VDD
• VSS
• RA0
• RA1
This will interface to the In-Circuit Debugger module
available from Microchip or one of the third party
development tool companies.
24.7 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply
Programming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/VPP/RA3 pin, but the RC3/PGM pin
is then dedicated to controlling Program mode entry and
is not available as a general purpose I/O pin.
While programming, using Single-Supply Programming
mode, VDD is applied to the MCLR/VPP/RA3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RC3/PGM then
becomes available as the digital I/O pin, RC3. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RA3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required.
I/O pins: RA0, RA1
Stack: 2 levels
Program Memory: 512 bytes
Data Memory: 10 bytes
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: By default, Single-Supply ICSP is
enabled in unprogrammed devices (as
supplied from Microchip) and erased
devices.
3: When Single-Supply Programming is
enabled, the RC3 pin can no longer be
used as a general purpose I/O pin.
4: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
PIC18F/LF1XK50
DS41350E-page 308 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 309
PIC18F/LF1XK50
25.0 INSTRUCTION SET SUMMARY
PIC18F/LF1XK50 devices incorporate the standard set
of 75 PIC18 core instructions, as well as an extended set
of 8 new instructions, for the optimization of code that is
recursive or that utilizes a software stack. The extended
set is discussed later in this section.
25.1 Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC® MCU instruction sets. Most instructions are a single
program memory word (16 bits), but there are four
instructions that require two program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the operation
is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction.
In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 25-1 shows the general formats that the instructions
can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 25-2,
lists the standard instructions recognized by the
Microchip Assembler (MPASMTM).
Section 25.1.1 “Standard Instruction Set” provides
a description of each instruction.
PIC18F/LF1XK50
DS41350E-page 310 Preliminary 2010 Microchip Technology Inc.
TABLE 25-1: OPCODE FIELD DESCRIPTIONS
Field Description
a RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs 12-bit Register file address (000h to FFFh). This is the source address.
fd 12-bit Register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n The relative address (2’s complement number) for relative branch instructions or the direct address for
CALL/BRANCH and RETURN instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
s Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
u Unused or unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs 7-bit offset value for indirect addressing of register files (source).
zd 7-bit offset value for indirect addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text) The contents of text.
[expr] Specifies bit n of the register indicated by the pointer expr.
Assigned to.
< > Register bit field.
In the set of.
italics User defined term (font is Courier).
2010 Microchip Technology Inc. Preliminary DS41350E-page 311
PIC18F/LF1XK50
FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (literal)
15 12 11 0
1111 f (Destination FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 7Fh
GOTO Label
15 8 7 0
OPCODE n<7:0> (literal)
15 12 11 0
1111 n<19:8> (literal)
CALL MYFUNC
15 11 10 0
OPCODE n<10:0> (literal)
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
S
PIC18F/LF1XK50
DS41350E-page 312 Preliminary 2010 Microchip Technology Inc.
TABLE 25-2: PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected Notes
MSb LSb
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and CARRY bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
11111
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
112
111111111
11
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da0
0da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
44
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
2010 Microchip Technology Inc. Preliminary DS41350E-page 313
PIC18F/LF1XK50
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
11
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
nnnnnnnnn
n, s
——n
————n
s
ks
—
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
112
1111212
221
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
4
TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
PIC18F/LF1XK50
DS41350E-page 314 Preliminary 2010 Microchip Technology Inc.
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
kkk
f, k
kkkkkk
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSR(f) 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1112
111211
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
2
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
2010 Microchip Technology Inc. Preliminary DS41350E-page 315
PIC18F/LF1XK50
25.1.1 STANDARD INSTRUCTION SET
ADDLW ADD literal to W
Syntax: ADDLW k
Operands: 0 k 255
Operation: (W) + k W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to W
Example: ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF ADD W to f
Syntax: ADDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: ADDWF REG, 0, 0
Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
PIC18F/LF1XK50
DS41350E-page 316 Preliminary 2010 Microchip Technology Inc.
ADDWFC ADD W and CARRY bit to f
Syntax: ADDWFC f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the CARRY flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: ADDWFC REG, 0, 1
Before Instruction
CARRY bit = 1
REG = 02h
W = 4Dh
After Instruction
CARRY bit = 0
REG = 02h
W = 50h
ANDLW AND literal with W
Syntax: ANDLW k
Operands: 0 k 255
Operation: (W) .AND. k W
Status Affected: N, Z
Encoding: 0000 1011 kkkk kkkk
Description: The contents of W are AND’ed with the
8-bit literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’
Process
Data
Write to W
Example: ANDLW 05Fh
Before Instruction
W = A3h
After Instruction
W = 03h
2010 Microchip Technology Inc. Preliminary DS41350E-page 317
PIC18F/LF1XK50
ANDWF AND W with f
Syntax: ANDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .AND. (f) dest
Status Affected: N, Z
Encoding: 0001 01da ffff ffff
Description: The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: ANDWF REG, 0, 0
Before Instruction
W = 17h
REG = C2h
After Instruction
W = 02h
REG = C2h
BC Branch if Carry
Syntax: BC n
Operands: -128 n 127
Operation: if CARRY bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the CARRY bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If CARRY = 1;
PC = address (HERE + 12)
If CARRY = 0;
PC = address (HERE + 2)
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BCF Bit Clear f
Syntax: BCF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
BN Branch if Negative
Syntax: BN n
Operands: -128 n 127
Operation: if NEGATIVE bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the NEGATIVE bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If NEGATIVE = 1;
PC = address (Jump)
If NEGATIVE = 0;
PC = address (HERE + 2)
2010 Microchip Technology Inc. Preliminary DS41350E-page 319
PIC18F/LF1XK50
BNC Branch if Not Carry
Syntax: BNC n
Operands: -128 n 127
Operation: if CARRY bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the CARRY bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If CARRY = 0;
PC = address (Jump)
If CARRY = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: BNN n
Operands: -128 n 127
Operation: if NEGATIVE bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the NEGATIVE bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If NEGATIVE = 0;
PC = address (Jump)
If NEGATIVE = 1;
PC = address (HERE + 2)
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DS41350E-page 320 Preliminary 2010 Microchip Technology Inc.
BNOV Branch if Not Overflow
Syntax: BNOV n
Operands: -128 n 127
Operation: if OVERFLOW bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the OVERFLOW bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If OVERFLOW= 0;
PC = address (Jump)
If OVERFLOW= 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: BNZ n
Operands: -128 n 127
Operation: if ZERO bit is ‘0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the ZERO bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If ZERO = 0;
PC = address (Jump)
If ZERO = 1;
PC = address (HERE + 2)
2010 Microchip Technology Inc. Preliminary DS41350E-page 321
PIC18F/LF1XK50
BRA Unconditional Branch
Syntax: BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have incremented
to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: BSF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f
Status Affected: None
Encoding: 1000 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
PIC18F/LF1XK50
DS41350E-page 322 Preliminary 2010 Microchip Technology Inc.
BTFSC Bit Test File, Skip if Clear
Syntax: BTFSC f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: BTFSS f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f) = 1
Status Affected: None
Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
2010 Microchip Technology Inc. Preliminary DS41350E-page 323
PIC18F/LF1XK50
BTG Bit Toggle f
Syntax: BTG f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f) f
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [75h]
After Instruction:
PORTC = 0110 0101 [65h]
BOV Branch if Overflow
Syntax: BOV n
Operands: -128 n 127
Operation: if OVERFLOW bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the OVERFLOW bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If OVERFLOW= 1;
PC = address (Jump)
If OVERFLOW= 0;
PC = address (HERE + 2)
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BZ Branch if Zero
Syntax: BZ n
Operands: -128 n 127
Operation: if ZERO bit is ‘1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the ZERO bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If ZERO = 1;
PC = address (Jump)
If ZERO = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: CALL k {,s}
Operands: 0 k 1048575
s [0,1]
Operation: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(Status) STATUSS,
(BSR) BSRS
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>,
PUSH PC to
stack
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE CALL THERE, 1
Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS= Status
2010 Microchip Technology Inc. Preliminary DS41350E-page 325
PIC18F/LF1XK50
CLRF Clear f
Syntax: CLRF f {,a}
Operands: 0 f 255
a [0,1]
Operation: 000h f
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: CLRF FLAG_REG, 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CLRWDT Clear Watchdog Timer
Syntax: CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the postscaler
of the WDT. Status bits, TO and
PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
No
operation
Example: CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO = 1
PD = 1
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COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest
Status Affected: N, Z
Encoding: 0001 11da ffff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W = ECh
CPFSEQ Compare f with W, skip if f = W
Syntax: CPFSEQ f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)
2010 Microchip Technology Inc. Preliminary DS41350E-page 327
PIC18F/LF1XK50
CPFSGT Compare f with W, skip if f > W
Syntax: CPFSGT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) –W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W = ?
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
CPFSLT Compare f with W, skip if f < W
Syntax: CPFSLT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W = ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG W;
PC = Address (NLESS)
PIC18F/LF1XK50
DS41350E-page 328 Preliminary 2010 Microchip Technology Inc.
DAW Decimal Adjust W Register
Syntax: DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>;
If [W<7:4> + DC > 9] or [C = 1] then
(W<7:4>) + 6 + DC W<7:4>;
else
(W<7:4>) + DC W<7:4>
Status Affected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register W
Process
Data
Write
W
Example1:
DAW
Before Instruction
W = A5h
C = 0
DC = 0
After Instruction
W = 05h
C = 1
DC = 0
Example 2:
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0
DECF Decrement f
Syntax: DECF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: DECF CNT, 1, 0
Before Instruction
CNT = 01h
Z = 0
After Instruction
CNT = 00h
Z = 1
2010 Microchip Technology Inc. Preliminary DS41350E-page 329
PIC18F/LF1XK50
DECFSZ Decrement f, skip if 0
Syntax: DECFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT - 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, skip if not 0
Syntax: DCFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = TEMP – 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
PIC18F/LF1XK50
DS41350E-page 330 Preliminary 2010 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: GOTO allows an unconditional branch
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO is always a two-cycle
instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increment f
Syntax: INCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: INCF CNT, 1, 0
Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1
2010 Microchip Technology Inc. Preliminary DS41350E-page 331
PIC18F/LF1XK50
INCFSZ Increment f, skip if 0
Syntax: INCFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT 0;
PC = Address (NZERO)
INFSNZ Increment f, skip if not 0
Syntax: INFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
PIC18F/LF1XK50
DS41350E-page 332 Preliminary 2010 Microchip Technology Inc.
IORLW Inclusive OR literal with W
Syntax: IORLW k
Operands: 0 k 255
Operation: (W) .OR. k W
Status Affected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to W
Example: IORLW 35h
Before Instruction
W = 9Ah
After Instruction
W = BFh
IORWF Inclusive OR W with f
Syntax: IORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .OR. (f) dest
Status Affected: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h
2010 Microchip Technology Inc. Preliminary DS41350E-page 333
PIC18F/LF1XK50
LFSR Load FSR
Syntax: LFSR f, k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description: The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example: LFSR 2, 3ABh
After Instruction
FSR2H = 03h
FSR2L = ABh
MOVF Move f
Syntax: MOVF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write W
Example: MOVF REG, 0, 0
Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h
PIC18F/LF1XK50
DS41350E-page 334 Preliminary 2010 Microchip Technology Inc.
MOVFF Move f to f
Syntax: MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description: The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
(src)
Process
Data
No
operation
Decode No
operation
No dummy
read
No
operation
Write
register ‘f’
(dest)
Example: MOVFF REG1, REG2
Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h
MOVLB Move literal to low nibble in BSR
Syntax: MOVLW k
Operands: 0 k 255
Operation: k BSR
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Description: The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’,
regardless of the value of k7:k4.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
Example: MOVLB 5
Before Instruction
BSR Register = 02h
After Instruction
BSR Register = 05h
2010 Microchip Technology Inc. Preliminary DS41350E-page 335
PIC18F/LF1XK50
MOVLW Move literal to W
Syntax: MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Description: The eight-bit literal ‘k’ is loaded into W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to W
Example: MOVLW 5Ah
After Instruction
W = 5Ah
MOVWF Move W to f
Syntax: MOVWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) f
Status Affected: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: MOVWF REG, 0
Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh
PIC18F/LF1XK50
DS41350E-page 336 Preliminary 2010 Microchip Technology Inc.
MULLW Multiply literal with W
Syntax: MULLW k
Operands: 0 k 255
Operation: (W) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero result
is possible but not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example: MULLW 0C4h
Before Instruction
W = E2h
PRODH = ?
PRODL = ?
After Instruction
W = E2h
PRODH = ADh
PRODL = 08h
MULWF Multiply W with f
Syntax: MULWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) x (f) PRODH:PRODL
Status Affected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example: MULWF REG, 1
Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h
2010 Microchip Technology Inc. Preliminary DS41350E-page 337
PIC18F/LF1XK50
NEGF Negate f
Syntax: NEGF f {,a}
Operands: 0 f 255
a [0,1]
Operation: ( f ) + 1 f
Status Affected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]
NOP No Operation
Syntax: NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
Example:
None.
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POP Pop Top of Return Stack
Syntax: POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
POP TOS
value
No
operation
Example: POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: PUSH
Operands: None
Operation: (PC + 2) TOS
Status Affected: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example: PUSH
Before Instruction
TOS = 345Ah
PC = 0124h
After Instruction
PC = 0126h
TOS = 0126h
Stack (1 level down) = 345Ah
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PIC18F/LF1XK50
RCALL Relative Call
Syntax: RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
PUSH PC to
stack
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: RESET
Operands: None
Operation: Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset by software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
Reset
No
operation
No
operation
Example: RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
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RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Status and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
Example: RETFIE 1
After Interrupt
PC = TOS
W = WS
BSR = BSRS
Status = STATUSS
GIE/GIEH, PEIE/GIEL = 1
RETLW Return literal to W
Syntax: RETLW k
Operands: 0 k 255
Operation: k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn
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PIC18F/LF1XK50
RETURN Return from Subroutine
Syntax: RETURN {s}
Operands: s [0,1]
Operation: (TOS) PC,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, Status and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
Example: RETURN
After Instruction:
PC = TOS
RLCF Rotate Left f through Carry
Syntax: RLCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest,
(f<7>) C,
(C) dest<0>
Status Affected: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1
C register f
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RLNCF Rotate Left f (No Carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest,
(f<7>) dest<0>
Status Affected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest,
(f<0>) C,
(C) dest<7>
Status Affected: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
C register f
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PIC18F/LF1XK50
RRNCF Rotate Right f (No Carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest,
(f<0>) dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0
Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0 f 255
a [0,1]
Operation: FFh f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: SETF REG, 1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh
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SLEEP Enter Sleep mode
Syntax: SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-down Status bit (PD) is
cleared. The Time-out Status bit (TO)
is set. Watchdog Timer and its postscaler
are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
Go to
Sleep
Example: SLEEP
Before Instruction
TO = ?
PD = ?
After Instruction
TO = 1 †
PD = 0
† If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with borrow
Syntax: SUBFWB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) – (f) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register ‘f’ and CARRY flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: SUBFWB REG, 1, 0
Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0
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PIC18F/LF1XK50
SUBLW Subtract W from literal
Syntax: SUBLW k
Operands: 0 k 255
Operation: k – (W) W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to W
Example 1: SUBLW 02h
Before Instruction
W = 01h
C = ?
After Instruction
W = 01h
C = 1 ; result is positive
Z = 0
N = 0
Example 2: SUBLW 02h
Before Instruction
W = 02h
C = ?
After Instruction
W = 00h
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBLW 02h
Before Instruction
W = 03h
C = ?
After Instruction
W = FFh ; (2’s complement)
C = 0 ; result is negative
Z = 0
N = 1
SUBWF Subtract W from f
Syntax: SUBWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: SUBWF REG, 1, 0
Before Instruction
REG = 3
W = 2
C = ?
After Instruction
REG = 1
W = 2
C = 1 ; result is positive
Z = 0
N = 0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction
REG = FFh ;(2’s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1
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SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract W and the CARRY flag
(borrow) from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: SUBWFB REG, 1, 0
Before Instruction
REG = 19h (0001 1001)
W = 0Dh (0000 1101)
C = 1
After Instruction
REG = 0Ch (0000 1011)
W = 0Dh (0000 1101)
C = 1
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
After Instruction
REG = F5h (1111 0100)
; [2’s comp]
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1 ; result is negative
SWAPF Swap f
Syntax: SWAPF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: SWAPF REG, 1, 0
Before Instruction
REG = 53h
After Instruction
REG = 35h
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PIC18F/LF1XK50
TBLRD Table Read
Syntax: TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write TABLAT)
TBLRD Table Read (Continued)
Example1: TBLRD *+ ;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 00A357h
Example2: TBLRD +* ;
Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 01A358h
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TBLWT Table Write
Syntax: TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register;
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 4.0
“Flash Program Memory” for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-MByte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register )
TBLWT Table Write (Continued)
Example1: TBLWT *+;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLDING REGISTER
(00A356h) = FFh
After Instructions (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLDING REGISTER
(00A356h) = 55h
Example 2: TBLWT +*;
Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = FFh
After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = 34h
2010 Microchip Technology Inc. Preliminary DS41350E-page 349
PIC18F/LF1XK50
TSTFSZ Test f, skip if 0
Syntax: TSTFSZ f {,a}
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT 00h,
PC = Address (NZERO)
XORLW Exclusive OR literal with W
Syntax: XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W
Status Affected: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to W
Example: XORLW 0AFh
Before Instruction
W = B5h
After Instruction
W = 1Ah
PIC18F/LF1XK50
DS41350E-page 350 Preliminary 2010 Microchip Technology Inc.
XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: XORWF REG, 1, 0
Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h
2010 Microchip Technology Inc. Preliminary DS41350E-page 351
PIC18F/LF1XK50
25.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F/LF1XK50 devices also provide
an optional extension to the core CPU functionality.
The added features include eight additional
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing mode for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
A summary of the instructions in the extended instruction
set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 25-1
(page 310) apply to both the standard and extended
PIC18 instruction sets.
25.2.1 EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. MPASM™ Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byteoriented
and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 25.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Note: The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is provided
as a reference for users who may be
reviewing code that has been generated
by a compiler.
Note: In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
MSb LSb Affected
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
f, k
k
zs, fd
zs, zd
k
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store literal at FSR2,
decrement FSR2
Subtract literal from FSR
Subtract literal from FSR2 and
return
1222
2
1
12
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
None
None
None
None
None
None
None
None
PIC18F/LF1XK50
DS41350E-page 352 Preliminary 2010 Microchip Technology Inc.
25.2.2 EXTENDED INSTRUCTION SET
ADDFSR Add Literal to FSR
Syntax: ADDFSR f, k
Operands: 0 k 63
f [ 0, 1, 2 ]
Operation: FSR(f) + k FSR(f)
Status Affected: None
Encoding: 1110 1000 ffkk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
FSR
Example: ADDFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 0422h
ADDULNK Add Literal to FSR2 and Return
Syntax: ADDULNK k
Operands: 0 k 63
Operation: FSR2 + k FSR2,
(TOS) PC
Status Affected: None
Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
Example: ADDULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
2010 Microchip Technology Inc. Preliminary DS41350E-page 353
PIC18F/LF1XK50
CALLW Subroutine Call Using WREG
Syntax: CALLW
Operands: None
Operation: (PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
Status Affected: None
Encoding: 0000 0000 0001 0100
Description First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, Status or BSR.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
WREG
PUSH PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CALLW
Before Instruction
PC = address (HERE)
PCLATH = 10h
PCLATU = 00h
W = 06h
After Instruction
PC = 001006h
TOS = address (HERE + 2)
PCLATH = 10h
PCLATU = 00h
W = 06h
MOVSF Move Indexed to f
Syntax: MOVSF [zs], fd
Operands: 0 zs 127
0 fd 4095
Operation: ((FSR2) + zs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.)
1110
1111
1011
ffff
0zzz
ffff
zzzzs
ffffd
Description: The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘zs’ in the first word to the value of
FSR2. The address of the destination
register is specified by the 12-bit literal
‘fd’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine
source addr
Determine
source addr
Read
source reg
Decode No
operation
No dummy
read
No
operation
Write
register ‘f’
(dest)
Example: MOVSF [05h], REG2
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h
PIC18F/LF1XK50
DS41350E-page 354 Preliminary 2010 Microchip Technology Inc.
MOVSS Move Indexed to Indexed
Syntax: MOVSS [zs], [zd]
Operands: 0 zs 127
0 zd 127
Operation: ((FSR2) + zs) ((FSR2) + zd)
Status Affected: None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
Description The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine
source addr
Determine
source addr
Read
source reg
Decode Determine
dest addr
Determine
dest addr
Write
to dest reg
Example: MOVSS [05h], [06h]
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h
PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: PUSHL k
Operands: 0k 255
Operation: k (FSR2),
FSR2 – 1 FSR2
Status Affected: None
Encoding: 1111 1010 kkkk kkkk
Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
data
Write to
destination
Example: PUSHL 08h
Before Instruction
FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
After Instruction
FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
2010 Microchip Technology Inc. Preliminary DS41350E-page 355
PIC18F/LF1XK50
SUBFSR Subtract Literal from FSR
Syntax: SUBFSR f, k
Operands: 0 k 63
f [ 0, 1, 2 ]
Operation: FSR(f) – k FSRf
Status Affected: None
Encoding: 1110 1001 ffkk kkkk
Description: The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: SUBFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 03DCh
SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBULNK k
Operands: 0 k 63
Operation: FSR2 – k FSR2
(TOS) PC
Status Affected: None
Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
No
Operation
No
Operation
No
Operation
No
Operation
Example: SUBULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)
PIC18F/LF1XK50
DS41350E-page 356 Preliminary 2010 Microchip Technology Inc.
25.2.3 BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 3.5.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses
embedded in opcodes are treated as literal memory
locations: either as a location in the Access Bank (‘a’ =
0), or in a GPR bank designated by the BSR (‘a’ = 1).
When the extended instruction set is enabled and ‘a’ =
0, however, a file register argument of 5Fh or less is
interpreted as an offset from the pointer value in FSR2
and not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and bitoriented
instructions, or almost half of the core PIC18
instructions – may behave differently when the
extended instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 25.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand conditions
shown in the examples are applicable to all
instructions of these types.
25.2.3.1 Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM™ assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
25.2.4 CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruction
set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F/LF1XK50, it
is very important to consider the type of code. A large,
re-entrant application that is written in ‘C’ and would
benefit from efficient compilation will do well when
using the instruction set extensions. Legacy applications
that heavily use the Access Bank will most likely
not benefit from using the extended instruction set.
Note: Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
2010 Microchip Technology Inc. Preliminary DS41350E-page 357
PIC18F/LF1XK50
ADDWF ADD W to Indexed
(Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d}
Operands: 0 k 95
d [0,1]
Operation: (W) + ((FSR2) + k) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01d0 kkkk kkkk
Description: The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data
Write to
destination
Example: ADDWF [OFST] , 0
Before Instruction
W = 17h
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents
of 0A2Ch = 20h
BSF Bit Set Indexed
(Indexed Literal Offset mode)
Syntax: BSF [k], b
Operands: 0 f 95
0 b 7
Operation: 1 ((FSR2) + k)
Status Affected: None
Encoding: 1000 bbb0 kkkk kkkk
Description: Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: BSF [FLAG_OFST], 7
Before Instruction
FLAG_OFST = 0Ah
FSR2 = 0A00h
Contents
of 0A0Ah = 55h
After Instruction
Contents
of 0A0Ah = D5h
SETF Set Indexed
(Indexed Literal Offset mode)
Syntax: SETF [k]
Operands: 0 k 95
Operation: FFh ((FSR2) + k)
Status Affected: None
Encoding: 0110 1000 kkkk kkkk
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data
Write
register
Example: SETF [OFST]
Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh
PIC18F/LF1XK50
DS41350E-page 358 Preliminary 2010 Microchip Technology Inc.
25.2.5 SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set of the PIC18F/LF1XK50 family of devices. This
includes the MPLAB® C18 C compiler, MPASM
assembly language and MPLAB Integrated
Development Environment (IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing mode. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompanying
their development systems for the appropriate
information.
2010 Microchip Technology Inc. Preliminary DS41350E-page 359
PIC18F1XK50/PIC18LF1XK50
26.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
26.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 360 Preliminary 2010 Microchip Technology Inc.
26.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers.
These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
26.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor,
and one-step driver, and can run on multiple
platforms.
26.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
26.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
2010 Microchip Technology Inc. Preliminary DS41350E-page 361
PIC18F1XK50/PIC18LF1XK50
26.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating
the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software
simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment,
making it an excellent, economical software
development tool.
26.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit
debugger systems (RJ11) or with the new highspeed,
noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
26.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's
most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal
Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers
and dsPIC® DSCs with the powerful, yet easyto-
use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected
to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
26.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming
of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement
in-circuit debugging and In-Circuit Serial Programming
™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 362 Preliminary 2010 Microchip Technology Inc.
26.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface
for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers.
In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint,
the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
26.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular,
detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
26.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional
systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/
development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2010 Microchip Technology Inc. Preliminary DS41350E-page 363
PIC18F/LF1XK50
27.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC18F1XK50 .......................................................................... -0.3V to +6.0V
Voltage on VDD with respect to VSS, PIC18LF1XK50 ........................................................................ -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on VUSB pin with respect to VSS ............................................................................................ -0.3V to +4.0V
Voltage on D+ and D- pins with respect to VSS ...................................................................... -0.3V to (VUSB + 0.3V)
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin ...................................................................................................................... 95 mA
Maximum current into VDD pin ......................................................................................................................... 95 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by all ports ................................................................................................................... 90 mA
Maximum current sourced by all ports ............................................................................................................. 90 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
2: Vusb must always be VDD + 0.3V
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
PIC18F/LF1XK50
DS41350E-page 364 Preliminary 2010 Microchip Technology Inc.
27.1 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param.
No.
Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage
PIC18LF1XK50 1.8
2.7
——
3.6
3.6
VV
FOSC < = 20 MHz
FOSC < = 48 MHz
D001 PIC18F1XK50 1.8
2.7
——
5.5
5.5
VV
FOSC < = 20 MHz
FOSC < = 48 MHz
D002* VDR RAM Data Retention Voltage(1)
PIC18LF1XK50 1.5 — — V Device in Sleep mode
D002* PIC18F1XK50 1.7 — — V Device in Sleep mode
VPOR* Power-on Reset Release Voltage — 1.6 — V
VPORR* Power-on Reset Rearm Voltage — 0.8 — V
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05 — — V/ms
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2010 Microchip Technology Inc. Preliminary DS41350E-page 365
PIC18F/LF1XK50
FIGURE 27-1: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
VSS
NPOR
TPOR(3)
POR REARM
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
TVLOW(2)
PIC18F/LF1XK50
DS41350E-page 366 Preliminary 2010 Microchip Technology Inc.
27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics Min Typ† Max Units
Conditions
VDD Note
Supply Current (IDD)(1, 2)
D009 LDO Regulator — 30 — A —
— 5 — A — LP Clock mode and Sleep (requires FVR and
BOR to be disabled)
D010 — 6.0 9 A 1.8 FOSC = 32 kHz
LP Oscillator(4),
-40°C TA +85°C
— 7 12 A 3.0
D010 — 6 11 A 1.8 FOSC = 32 kHz
LP Oscillator(4),
-40°C TA +85°C
— 7 17 A 3.0
— 12 20 A 5.0
D011* — 6.0 12 A 1.8 FOSC = 32 kHz
LP Oscillator
-40°C TA +125°C
— 9.0 16 A 3.0
D011* — 8.0 15 A 1.8 FOSC = 32 kHz
LP Oscillator (4)
-40°C TA +125°C
— 11 25 A 3.0
— 12 35 A 5.0
D011* — 170 220 A 1.8 FOSC = 1 MHz
— 280 370 A 3.0 XT Oscillator
D011* — 200 250 A 1.8 FOSC = 1 MHz
— 310 400 A 3.0 XT Oscillator
— 380 490 A 5.0
D011* — 75 110 A 1.8 FOSC = 1 MHz
XT Oscillator
CPU Idle
— 130 190 A 3.0
D011* — 90 130 A 1.8 FOSC = 1 MHz
XT Oscillator
CPU Idle
— 140 210 A 3.0
— 160 250 A 5.0
* These parameters are characterized but not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 330 nF capacitor on VUSB pin.
2010 Microchip Technology Inc. Preliminary DS41350E-page 367
PIC18F/LF1XK50
Supply Current (IDD)(1, 2)
D012 — 300 700 A 1.8 FOSC = 4 MHz
— 500 1200 A 3.0 XT Oscillator
D012 — 330 700 A 1.8 FOSC = 4 MHz
— 530 1200 A 3.0 XT Oscillator
— 730 1400 A 5.0
D012A — 240 300 A 1.8 FOSC = 4 MHz,
XT Oscillator
CPU Idle
— 440 550 A 3.0
D012A — 230 300 A 1.8 FOSC = 4 MHz
XT Oscillator
CPU Idle
— 400 550 A 3.0
— 470 640 A 5.0
D013 — 140 180 A 1.8 FOSC = 1 MHz
— 230 300 A 3.0 EC Oscillator (medium power)
D013 — 160 210 A 1.8 FOSC = 1 MHz
EC Oscillator (medium power)(5)
— 250 310 A 3.0
— 290 380 A 5.0
D013A — 50 64 A 1.8 FOSC = 1 MHz
EC Oscillator (medium power)
CPU Idle
— 86 110 A 3.0
D013A — 70 100 A 1.8 FOSC = 1 MHz
EC Oscillator (medium power)
CPU Idle(5) — 100 150 A 3.0
— 120 170 A 5.0
D014 — 500 640 A 1.8 FOSC = 4 MHz
— 830 1100 A 3.0 EC Oscillator (medium power)
D014 — 520 770 A 1.8 FOSC = 4 MHz
EC Oscillator (medium power)(5)
— 860 1200 A 3.0
— 1000 1370 A 5.0
27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics Min Typ† Max Units
Conditions
VDD Note
* These parameters are characterized but not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 330 nF capacitor on VUSB pin.
PIC18F/LF1XK50
DS41350E-page 368 Preliminary 2010 Microchip Technology Inc.
Supply Current (IDD)(1, 2)
D014A — 200 250 A 1.8 FOSC = 4 MHz
EC Oscillator (medium power)
CPU Idle
— 340 440 A 3.0
D014A — 210 303 A 1.8 FOSC = 4 MHz
EC Oscillator (medium power)
CPU Idle(5) — 360 520 A 3.0
— 430 670 A 5.0
D015 — 820 1000 A 1.8 FOSC = 6 MHz
— 1500 1900 A 3.0 EC Oscillator (high power)
D015 — 830 1100 A 1.8 FOSC = 6 MHz
EC Oscillator (high power)(5)
— 1500 1900 A 3.0
— 1700 2300 A 5.0
D015A — 300 370 A 1.8 FOSC = 6 MHz
EC Oscillator (high power)
CPU Idle
— 510 660 A 3.0
D015A — 320 430 A 1.8 FOSC = 6 MHz
EC Oscillator (high power)
CPU Idle(5) — 530 690 A 3.0
— 640 840 A 5.0
D015B — 4.7 6.0 mA 3.0 FOSC = 24 MHz
6 MHz EC Oscillator (high power)
PLL enabled
D015B — 4.7 6.1 mA 3.0 FOSC = 24 MHz
6 MHz EC Oscillator (high power)
PLL enabled(5) — 5.6 7.4 mA 5.0
D015C — 2.0 2.5 mA 3.0 FOSC = 24 MHz
6 MHz EC Oscillator (high power)
PLL enabled, CPU Idle
D015C — 2.0 2.5 mA 3.0 FOSC = 24 MHz
6 MHz EC Oscillator (high power)
PLL enabled, CPU Idle(5) — 2.3 3.0 mA 5.0
27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics Min Typ† Max Units
Conditions
VDD Note
* These parameters are characterized but not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 330 nF capacitor on VUSB pin.
2010 Microchip Technology Inc. Preliminary DS41350E-page 369
PIC18F/LF1XK50
27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics Min Typ† Max Units
Conditions
VDD Note
Supply Current (IDD)(1, 2)
D016 — 2.6 3.3 mA 3.0 FOSC = 12 MHz
EC Oscillator (high power)
D016 — 2.6 3.3 mA 3.0 FOSC = 12 MHz
EC Oscillator (high power)(5)
— 3.1 4.1 mA 5.0
D017 — 1.0 1.3 mA 3.0 FOSC = 12 MHz
EC Oscillator (high power)
CPU Idle
D017 — 1.0 1.3 mA 3.0 FOSC = 12 MHz
EC Oscillator (high power)
CPU Idle(5) — 1.2 1.6 mA 5.0
D017A — 9 12 mA 3.0 FOSC = 48 MHz
12 MHz EC Oscillator (high power)
PLL enabled
D017A — 8.9 12 mA 3.0 FOSC = 48 MHz
12 MHz EC Oscillator (high power)
PLL enabled(5) — 11 14 mA 5.0
D017B — 3.9 5.0 mA 3.0 FOSC = 48 MHz
12 MHz EC Oscillator (high power)
PLL enabled, CPU Idle
D017B — 3.9 5.0 mA 3.0 FOSC = 48 MHz
12 MHz EC Oscillator (high power)
PLL enabled, CPU Idle(5) — 4.7 6.0 mA 5.0
D018 — 19 38 A 1.8 FOSC = 32 kHz
LFINTOSC Oscillator mode(3, 5)
— 23 44 A 3.0
D018 — 21 40 A 1.8 FOSC = 32 kHz
LFINTOSC Oscillator mode(3, 5)
— 25 46 A 3.0
— 26 48 A 5.0
D019 — 16 33 A 1.8 FOSC = 32 kHz
LFINTOSC Oscillator
CPU Idle
— 18 38 A 3.0
D019 — 18 35 A 1.8 FOSC = 32 kHz
LFINTOSC Oscillator
CPU Idle — 20 40 A 3.0 (5)
— 21 42 A 5.0
Supply Current (IDD)(1, 2)
* These parameters are characterized but not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 330 nF capacitor on VUSB pin.
PIC18F/LF1XK50
DS41350E-page 370 Preliminary 2010 Microchip Technology Inc.
D020 — 320 470 A 1.8 FOSC = 500 kHz
— 460 670 A 3.0 LFINTOSC Oscillator
D020 — 350 500 A 1.8 FOSC = 500 kHz
LFINTOSC Oscillator(5)
— 490 700 A 3.0
— 540 780 A 5.0
D021 — 380 600 A 1.8 FOSC = 1 MHz
— 550 870 A 3.0 HFINTOSC Oscillator
D021 — 410 600 A 1.8 FOSC = 1 MHz
HFINTOSC Oscillator(5)
— 580 870 A 3.0
— 650 970 A 5.0
D021A — 290 600 A 1.8 FOSC = 1 MHz
HFINTOSC Oscillator
CPU Idle
— 410 760 A 3.0
D021A — 320 620 A 1.8 FOSC = 1 MHz
HFINTOSC Oscillator
CPU Idle(5) — 440 770 A 3.0
— 490 880 A 5.0
D022 — 1.2 1.6 mA 1.8 FOSC = 8 MHz
— 2.1 2.9 mA 3.0 HFINTOSC Oscillator
D022 — 1.2 1.6 mA 1.8 FOSC = 8 MHz
HFINTOSC Oscillator(5)
— 2.1 2.9 mA 3.0
— 2.4 3.5 mA 5.0
D023 — 2.0 2.7 mA 1.8 FOSC = 16 MHz
— 3.5 4.8 mA 3.0 HFINTOSC Oscillator
D023 — 2.0 2.7 mA 1.8 FOSC = 16 MHz
HFINTOSC Oscillator(5)
— 3.5 4.8 mA 3.0
— 4.0 6.0 mA 5.0
D023A — 0.9 1.3 mA 1.8 FOSC = 16 MHz
HFINTOSC Oscillator
CPU Idle
— 1.5 2.1 mA 3.0
D023A — 0.9 1.3 mA 1.8 FOSC = 16 MHz
HFINTOSC Oscillator
CPU Idle(5) — 1.5 2.1 mA 3.0
— 1.7 2.6 mA 5.0
Supply Current (IDD)(1, 2)
27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics Min Typ† Max Units
Conditions
VDD Note
* These parameters are characterized but not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 330 nF capacitor on VUSB pin.
2010 Microchip Technology Inc. Preliminary DS41350E-page 371
PIC18F/LF1XK50
D024 — 0.5 0.7 mA 1.8 FOSC = 4 MHz
— 0.9 1.1 mA 3.0 EXTRC Oscillator mode
D024 — 0.5 0.7 mA 1.8 FOSC = 4 MHz
EXTRC Oscillator mode(5)
— 0.9 1.1 mA 3.0
— 1.0 1.4 mA 5.0
D025 — 1.0 1.5 mA 1.8 FOSC = 6 MHz
— 1.7 2.1 mA 3.0 HS Oscillator
D025 — 1.0 1.5 mA 1.8 FOSC = 6 MHz
HS Oscillator(5)
— 1.7 2.1 mA 3.0
— 2.1 2.5 mA 5.0
D025A — 5.4 6.0 mA 3.0 FOSC = 24 MHz
6 MHz HS Oscillator
PLL enabled
D025A — 5.4 6.0 mA 3.0 FOSC = 24 MHz
6 MHz HS Oscillator
PLL enabled(5) — 7.4 7.6 mA 5.0
D026 — 3.2 3.3 mA 3.0 FOSC = 12 MHz
HS Oscillator
D026 — 3.2 3.3 mA 3.0 FOSC = 12 MHz
HS Oscillator(5)
— 4.8 4.2 mA 5.0
D026A — 10 12 mA 3.0 FOSC = 48 MHz,
12 MHz HS Oscillator
PLL enabled
D026A — 10 12 mA 3.0 FOSC = 48 MHz,
12 MHz HS Oscillator
PLL enabled(5) — 13 15 mA 5.0
27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics Min Typ† Max Units
Conditions
VDD Note
* These parameters are characterized but not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 330 nF capacitor on VUSB pin.
PIC18F/LF1XK50
DS41350E-page 372 Preliminary 2010 Microchip Technology Inc.
27.3 DC Characteristics: PIC18F/LF1XK50-I/E (Power-Down)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min Typ† Max
+85°C
Max
+125°C Units
Conditions
VDD Note
Power-down Base Current (IPD)(2)
D027 — 0.024 0.7 6.7 A 1.8 WDT, BOR, FVR, Voltage
Regulator and T1OSC disabled,
all Peripherals Inactive
— 0.078 1.9 8.5 A 3.0
D027 — 6.0 7.0 13 A 1.8 WDT, BOR, FVR and T1OSC
— 7.0 10 15 A 3.0 disabled, all Peripherals Inactive
— 8.0 12 19 A 5.0
Power-down Module Current
D028 — 0.45 1.3 4.4 A 1.8 LPWDT Current(1)
— 0.75 2.0 6.0 A 3.0
D028 — 6.5 7.0 10.5 A 1.8 LPWDT Current(1)
— 9.6 10.6 17.6 A 3.0
— 10.5 16.5 20 A 5.0
D029 — 12 17 23 A 1.8 FVR current (3)
— 22 19 25 A 3.0
D029 — 28 42 50 A 1.8 FVR current(3, 5)
— 35.6 45.6 55 A 3.0
— 38.5 49 60 A 5.0
D030 — — 21 27 A 3.0 BOR Current(1, 3)
D030 — 27 48 51 A 3.0 BOR Current(1, 3, 5)
— 36.5 51 55 A 5.0
D031 — 0.79 3.6 5.3 A 1.8 T1OSC Current(1)
— 1.8 2.9 6.9 A 3.0
D031 — 8.0 7.5 10 A 1.8 T1OSC Current(1)
— 8.5 10.5 15 A 3.0
— 10.5 12.5 24 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled
4: A/D oscillator source is FRC
5: 330 f capacitor on VUSB pin.
2010 Microchip Technology Inc. Preliminary DS41350E-page 373
PIC18F/LF1XK50
Power-down Module Current
D032 — — 1.8 8 A 1.8 A/D Current(1, 4), no conversion in
— — 3 10 A 3.0 progress
D032 — — 6 12 A 1.8 A/D Current(1, 4), no conversion in
— — 10 17 A 3.0 progress
— — 11.5 22 A 5.0
D033 — — 38 44 A 1.8 Comparator Current, low power
— — 40 47 A 3.0
D033 — 30 40 49 A 2.0 Comparator Current, low power
— 34 44 53 A 3.0
— 36 50 60 A 5.0
D033A — — 239 244 A 1.8 Comparator Current, high power
— — 242 249 A 3.0
D033A — 144 243 250 A 2.0 Comparator Current, high power
— 146 247 256 A 3.0
— 151 253 264 A 5.0
D034 — — 18 23 A 1.8 Voltage Reference Current
— — 30 35 A 3.0
D034 — 35 36 44 A 2.0 Voltage Reference Current
— 43 44 60 A 3.0
— 55 65 74 A 5.0
27.3 DC Characteristics: PIC18F/LF1XK50-I/E (Power-Down) (Continued)
PIC18LF1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC18F1XK50
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min Typ† Max
+85°C
Max
+125°C Units
Conditions
VDD Note
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled
4: A/D oscillator source is FRC
5: 330 f capacitor on VUSB pin.
PIC18F/LF1XK50
DS41350E-page 374 Preliminary 2010 Microchip Technology Inc.
27.4 DC Characteristics: PIC18F/LF1XK50-I/E
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O PORT:
D036 with TTL buffer — — 0.8 V 4.5V VDD 5.5V
D036A — — 0.15 VDD V 1.8V VDD 4.5V
D037 with Schmitt Trigger buffer — — 0.2 VDD V 1.8V VDD 5.5V
with I2C levels — — 0.3 VDD V
D038 MCLR, OSC1 (RC mode)(1) — — 0.2 VDD V
D039A OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O ports: — —
D040 with TTL buffer 2.0 — — V 4.5V VDD 5.5V
D040A 0.25 VDD +
0.8
— — V 1.8V VDD 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD — — V 1.8V VDD 5.5V
with I2C levels 0.7 VDD — — V
D042 MCLR 0.8 VDD — — V
D043A OSC1 (HS mode) 0.7 VDD — — V
D043B OSC1 (RC mode) 0.9 VDD — — V (Note 1)
IIL Input Leakage Current(2)
D060 I/O ports — ± 5 ± 100 nA VSS VPIN VDD, Pin at
high-impedance
D061 MCLR(3) — ± 50 ± 200 nA VSS VPIN VDD
IPUR PORTB Weak Pull-up Current
D070* 50 250 400 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(4)
D080 I/O ports
— —
VSS+0.6
VSS+0.6
VSS+0.6
V
IOH = 8mA, VDD = 5V
IOH = 6mA, VDD = 3.3V
IOH = 1.8mA, VDD = 1.8V
VOH Output High Voltage(4)
D090 I/O ports VDD-0.7
VDD-0.7
VDD-0.7
— — V
IOL = 3.5mA, VDD = 5V
IOL = 3mA, VDD = 3.3V
IOL = 1mA, VDD = 1.8V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
2010 Microchip Technology Inc. Preliminary DS41350E-page 375
PIC18F/LF1XK50
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
Flash Memory
D130 EP Cell Endurance 10K
100K
— — E/W Program Flash Memory
Data Flash Memory
D131 VDD for Read VMIN — — V
Voltage on MCLR/VPP during
Erase/Program
8.0 — 9.0 V Temperature during programming:
-40°C TA 85°C
VDD for Bulk Erase 2.7 — VDD Max V Temperature during programming:
10°C TA 40°C
D132 VPEW VDD for Write or Row Erase VDD Min — VDD Max V VMIN = Minimum operating voltage
VMAX = Maximum operating
voltage
IPPPGM Current on MCLR/VPP during
Erase/Write
— — 1.0 mA
IDDPGM Current on VDD during
Erase/Write
— 5.0 mA
D133 TPEW Erase/Write cycle time — 4.0 5.0 ms
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
VUSB Capacitor Charging
D135 Charging current — 200 — A
D135A Source/sink capability when
charging complete
— 0.0 — mA
27.4 DC Characteristics: PIC18F/LF1XK50-I/E (Continued)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
PIC18F/LF1XK50
DS41350E-page 376 Preliminary 2010 Microchip Technology Inc.
27.5 USB Module Specifications
Operating Conditions-40°C TA +85°C (unless otherwise state)
Param
No. Sym Characteristic Min Typ Max Units Conditions
D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB pin must be in
this range for proper USB
operation
D314 IIL Input Leakage on pin — — ± 1 A VSS VPIN VDD pin athigh
impedance
D315 VILUSB Input Low Voltage for USB
Buffer
— — 0.8 V For VUSB range
D316 VIHUSB Input High Voltage for USB
Buffer
2.0 — — V For VUSB range
D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and
D- must exceed this value while
VCM is met
D319 VCM Differential Common Mode
Range
0.8 — 2.5 V
D320 ZOUT Driver Output Impedance(1) 28 — 44
D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kload connected to 3.6V
D322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kload connected to ground
Note 1: The D+ and D- signal lines have been built-in impedance matching resistors. No external resistors,
capacitors or magnetic components are necessary on the D+/D- signal paths between the
PIC18F1XK50/PIC18LF1XK50 family device and USB cable.
2010 Microchip Technology Inc. Preliminary DS41350E-page 377
PIC18F/LF1XK50
27.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym Characteristic Typ Units Conditions
TH01 JA Thermal Resistance Junction to Ambient 62.4 C/W 20-pin PDIP package
85.2 C/W 20-pin SOIC package
108.1 C/W 20-pin SSOP package
TBD C/W 20-pin QFN 5x5mm package
TH02 JC Thermal Resistance Junction to Case 31.4 C/W 20-pin PDIP package
24 C/W 20-pin SOIC package
24 C/W 20-pin SSOP package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Legend: TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
PIC18F/LF1XK50
DS41350E-page 378 Preliminary 2010 Microchip Technology Inc.
27.7 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
FIGURE 27-2: LOAD CONDITIONS
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
VSS
CL
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
Load Condition
Pin
2010 Microchip Technology Inc. Preliminary DS41350E-page 379
PIC18F/LF1XK50
27.8 AC Characteristics: PIC18F1XK50/PIC18LF1XK50-I/E
FIGURE 27-3: CLOCK TIMING
FIGURE 27-4: PIC18F1XK50 VOLTAGE FREQUENCY GRAPH, -40°C TA +85°C
OSC1/CLKIN
OSC2/CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
OS02
OS03
OS04 OS04
OSC2/CLKOUT
(LP,XT,HS Modes)
(CLKOUT Mode)
1.8
0
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.
10 20 40 48
5.5
3.6
2.7
PIC18F/LF1XK50
DS41350E-page 380 Preliminary 2010 Microchip Technology Inc.
FIGURE 27-5: PIC18LF1XK50 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
FIGURE 27-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
1.8
2.7
0
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.
10 20 40 48
3.6
125
25
2.0
0
60
85
VDD (V)
4.0 4.5 5.0
Temperature (°C)
1.8 2.5 3.0 3.5 5.5
Note 1: This chart covers both regulator enabled and regulator disabled states.
2: Regulator Nominal voltage
3.3(2)
-40
-20
± 5% ± 2%
± 3%
± 5%
± 5%
2010 Microchip Technology Inc. Preliminary DS41350E-page 381
PIC18F/LF1XK50
TABLE 27-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz EC Oscillator mode (low)
DC — 4 MHz EC Oscillator mode (medium)
DC — 48 MHz EC Oscillator mode (high)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 20 MHz HS Oscillator mode
DC — 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode
250 — ns XT Oscillator mode
50 — ns HS Oscillator mode
20.80 — ns EC Oscillator mode
Oscillator Period(1) — — — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 83 TCY DC ns TCY = 4/FOSC
OS04* TosH,
TosL
External CLKIN High,
External CLKIN Low
2 — — s LP oscillator
100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
0 — ns LP oscillator
0 — ns XT oscillator
0 — ns HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption.
All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
PIC18F/LF1XK50
DS41350E-page 382 Preliminary 2010 Microchip Technology Inc.
TABLE 27-2: OSCILLATOR PARAMETERS
TABLE 27-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 42.7V TO 5.5V)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Freq.
Tolerance Min Typ† Max Units Conditions
OS08 HFOSC Internal Calibrated HFINTOSC
Frequency(2)
2%
3%
——
16.0
16.0
——
MHz
MHz
0°C TA +60°C
60°C TA +85°C
5% — 16.0 — MHz -40°C TA +125°C
OS10* TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
— — 5 8 s VDD = 2.0V, -40°C to +85°C
— — 5 8 s VDD = 3.0V, -40°C to +85°C
— — 5 8 s VDD = 5.0V, -40°C to +85°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
Param
No. Sym Characteristic Min Typ† Max Units Conditions
F10 FOSC Oscillator Frequency Range 4 — 12 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 48 MHz
F12 trc PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2010 Microchip Technology Inc. Preliminary DS41350E-page 383
PIC18F/LF1XK50
FIGURE 27-7: CLKOUT AND I/O TIMING
TABLE 27-4: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
OS11 TosH2ckL Fosc to CLKOUT (1) — — 70 ns VDD = 3.0-5.0V
OS12 TosH2ckH Fosc to CLKOUT (1) — — 72 ns VDD = 3.0-5.0V
OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns
OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.0-5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
50 — — ns VDD = 3.0-5.0V
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
20 — — ns
OS18 TioR Port output rise time —
—
90
55
140
80
ns VDD = 2.0V
VDD = 3.3-5.0V
OS19 TioF Port output fall time —
—
60
44
80
60
ns VDD = 2.0V
VDD = 3.3-5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Trbp PORTB interrupt-on-change new input
level time
TCY — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
FOSC
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17
OS16
OS14
OS12
OS18
Old Value New Value
Cycle Write Fetch Read Execute
PIC18F/LF1XK50
DS41350E-page 384 Preliminary 2010 Microchip Technology Inc.
FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 27-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
33
32
30
31/
34
I/O pins
34
Note 1: Asserted low.
Reset(1)
31A
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33(1)
37
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms
delay if PWRTE = 0.
Reset
(due to BOR)
VBOR and VHYST
TBORREJ
2010 Microchip Technology Inc. Preliminary DS41350E-page 385
PIC18F/LF1XK50
TABLE 27-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
30 TMCL MCLR Pulse Width (low) 2
5
——
——
s
s
VDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
31 TWDT Standard Watchdog Timer Time-out
Period(5)
10
10
17
17
27
30
ms
ms
VDD = 3.3V-5V, -40°C to +85°C
VDD = 3.3V-5V
31A TWDTLP Low Power Watchdog Timer
Time-out Period
10
10
18
18
27
33
ms
ms
VDD = 3.3V-5V, -40°C to +85°C
VDD = 3.3V-5V
32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3)
33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ I/O high-impedance from MCLR Low
or Watchdog Timer Reset
— — 2.0 s
35 VBOR Brown-out Reset Voltage 1.8
2.09
2.57
2.71
1.9
2.2
2.7
2.85
2.05
2.35
2.85
3.0
VVVV
BORV = 1.9V
BORV = 2.2V
BORV = 2.7V
BORV = 2.85V
36* VHYST Brown-out Reset Hysteresis 25 50 75 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response
Time
0 1 40 s VDD VBOR
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
5: Design Target. If unable to meet this target, the maximum can be increased, but the minimum cannot be
changed.
PIC18F/LF1XK50
DS41350E-page 386 Preliminary 2010 Microchip Technology Inc.
FIGURE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 27-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* TT1H T1CKI High
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with
Prescaler
15 — — ns
Asynchronous
30 — — ns
46* TT1L T1CKI Low
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input
Period
Synchronous Greater of:
30 or TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Asynchronous 60 — — ns
48 FT1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4 32.768 33.1 kHz
49* TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC — 7 TOSC — Timers in Sync mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
T0CKI
T1CKI
40 41
42
45 46
47 49
TMR0 or
TMR1
2010 Microchip Technology Inc. Preliminary DS41350E-page 387
PIC18F/LF1XK50
FIGURE 27-11: CAPTURE/COMPARE/PWM TIMINGS (CCP)
TABLE 27-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
TABLE 27-8: PIC18F1XK50/PIC18LF1XK50 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC03* TccP CCPx Input Period 3TCY + 40
N
— — ns N = prescale value (1, 4 or 16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Standard Operating Conditions (unless otherwise stated)
Operating temperature TA 25°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — — ±2 LSb VREF = 3.0V
AD03 EDL Differential Error — — 1.5 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — — ±3 LSb VREF = 3.0V
AD05 EGN Gain Error — — ±3 LSb VREF = 3.0V
AD06 VREF Change in Reference Voltage =
VREF+ - VREF-(3)
1.8 — VDD V 1.8 VREF+ VDD + 0.3V
VSS - 0.3V VREF- VREF+ - 1.8V
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
— — 2.5 k Can go higher if external 0.01F capacitor is
present on input pin.
AD09* IREF VREF Input Current(3) 10 — 1000 A During VAIN acquisition.
Based on differential of VHOLD to VAIN.
— — 10 A During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
Note: Refer to Figure 27-2 for load conditions.
(Capture mode)
CC01 CC02
CC03
CCPx
PIC18F/LF1XK50
DS41350E-page 388 Preliminary 2010 Microchip Technology Inc.
FIGURE 27-12: A/D CONVERSION TIMING
TABLE 27-9: A/D CONVERSION REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D Clock Period 0.7 25.0(1) s TOSC based, VREF 3.0V
0.7 1 s A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)(2)
11 12 TAD
132 TACQ Acquisition Time(3) 1.4
TBD
——
s
s
-40C to +85C
0C to +85C
135 TSWC Switching Time from Convert Sample — (Note 4)
TBD TDIS Discharge Time 0.2 — s
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50
.
4: On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
9 8 7 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
.. . . . .
TCY
2010 Microchip Technology Inc. Preliminary DS41350E-page 389
PIC18F/LF1XK50
TABLE 27-10: COMPARATOR SPECIFICATIONS
TABLE 27-11: CVREF VOLTAGE REFERENCE SPECIFICATIONS
TABLE 27-12: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Param
No. Sym Characteristics Min Typ Max Units Comments
CM01 VIOFF Input Offset Voltage ——
±7.5
—
±50
±80
mV
mV
High Power Mode
Low Power Mode
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio 55 — — dB
CM04 TRESP Response Time — 150 400 ns Note 1
CM05 TMC2OV Comparator Mode Change to
Output Valid*
— — 10 s
CM06 CHYSTER Comparator Hysteresis — 65 — mV
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Param
No. Sym Characteristics Min Typ Max Units Comments
CV01* CLSB Step Size(2) ——
VDD/24
VDD/32
——
VV
Low Range (VRR = 1)
High Range (VRR = 0)
CV02* CACC Absolute Accuracy —
—
——
1/4
1/2
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
CV03* CR Unit Resistor Value (R) — 2k —
CV04* CST Settling Time(1) — — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).
VR Voltage Reference Specifications
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C
-40°C TA +125°C
Param
No. Sym. Characteristics Min. Typ. Max. Units Comments
D003 VADFVR Fixed Voltage Reference Voltage -7
-8
-7
-8
-7
-8
——————
666666
% 1.024V, VDD 2.5V, 85°C
1.024V, VDD 2.5V, 125°C
2.048V, VDD 2.5V, 85°C
2.048V, VDD 2.5V, 125°C
4.096V, VDD 4.75V, 85°C
4.096V, VDD 4.75V, 125°C
D003C* TCVFVR Temperature Coefficient, Fixed Voltage
Reference
— -114 — ppm/°C
D003D* VFVR/
VIN
Line Regulation, Fixed Voltage Reference
— 0.225 — %/V
D004* SVDD VDD Rise Rate to ensure internal
Power-on Reset signal
0.05 — — V/ms See Section 6.1 “Power-on
Reset (POR)” for details.
* These parameters are characterized but not tested.
PIC18F/LF1XK50
DS41350E-page 390 Preliminary 2010 Microchip Technology Inc.
FIGURE 27-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 27-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 27-14: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 27-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V — 80 ns
1.8-5.5V — 100 ns
US121 TCKRF Clock out rise time and fall time
(Master mode)
3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK (DT hold time) 15 — ns
Note: Refer to Figure 27-2 for load conditions.
US121 US121
US120 US122
CK
DT
Note: Refer to Figure 27-2 for load conditions.
US125
US126
CK
DT
2010 Microchip Technology Inc. Preliminary DS41350E-page 391
PIC18F/LF1XK50
FIGURE 27-15: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 27-16: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP73
SP74
SP75, SP76
SP79 SP78
SP80
SP78 SP79
MSb bit 6 - - - - - -1 LSb
MSb In bit 6 - - - -1 LSb In
Note: Refer to Figure 27-2 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP81
SP71 SP72
SP74
SP75, SP76
SP78
SP80
MSb
SP79
SP73
MSb In
bit 6 - - - - - -1
bit 6 - - - -1 LSb In
LSb
Note: Refer to Figure 27-2 for load conditions.
PIC18F/LF1XK50
DS41350E-page 392 Preliminary 2010 Microchip Technology Inc.
FIGURE 27-17: SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 27-18: SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP73
SP74
SP75, SP76 SP77
SP79 SP78
SP80
SP78 SP79
MSb bit 6 - - - - - -1 LSb
MSb In bit 6 - - - -1 LSb In
SP83
Note: Refer to Figure 27-2 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP82
SP74
SP75, SP76
MSb bit 6 - - - - - -1 LSb
SP77
MSb In bit 6 - - - -1 LSb In
SP80
SP83
Note: Refer to Figure 27-2 for load conditions.
2010 Microchip Technology Inc. Preliminary DS41350E-page 393
PIC18F/LF1XK50
TABLE 27-15: SPI MODE REQUIREMENTS
FIGURE 27-19: I2C™ BUS START/STOP BITS TIMING
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
SP70* TSSL2SCH,
TSSL2SCL
SS to SCK or SCK input TCY — — ns
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH,
TDIV2SCL
Setup time of SDI data input to SCK edge 100 — — ns
SP74* TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK edge 100 — — ns
SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time
(Master mode)
3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV,
TSCL2DOV
SDO data output valid after
SCK edge
3.0-5.5V — — 50 ns
1.8-5.5V — — 145 ns
SP81* TDOV2SCH,
TDOV2SCL
SDO data output setup to SCK edge Tcy — — ns
SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns
SP83* TSCH2SSH,
TSCL2SSH
SS after SCK edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 27-2 for load conditions.
SP91
SP92
SP93
SCL
SDA
Start
Condition
Stop
Condition
SP90
PIC18F/LF1XK50
DS41350E-page 394 Preliminary 2010 Microchip Technology Inc.
TABLE 27-16: I2C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 27-20: I2C™ BUS DATA TIMING
Param
No. Symbol Characteristic Min Typ Max Units Conditions
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
Note: Refer to Figure 27-2 for load conditions.
SP90
SP91 SP92
SP100
SP101
SP103
SP106
SP107
SP109 SP109
SP110
SP102
SCL
SDA
In
SDA
Out
2010 Microchip Technology Inc. Preliminary DS41350E-page 395
PIC18F/LF1XK50
TABLE 27-17: I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
SP102* TR SDA and SCL rise
time
100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall
time
100 kHz mode — 250 ns
400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP90* TSU:STA Start condition
setup time
100 kHz mode 4.7 — s Only relevant for
400 kHz mode 0.6 — s Repeated Start condition
SP91* THD:STA Start condition hold
time
100 kHz mode 4.0 — s After this period the first
400 kHz mode 0.6 — s clock pulse is generated
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup
time
100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP92* TSU:STO Stop condition
setup time
100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
SP109* TAA Output valid from
clock
100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
SP CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
PIC18F/LF1XK50
DS41350E-page 396 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 397
PIC18F/LF1XK50
28.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
PIC18F/LF1XK50
DS41350E-page 398 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 399
PIC18F/LF1XK50
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
e3
e3
20-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PICXXFXXXX-I/P
0810017
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PICXXFXXXX
-I/SS
0810017
20-Lead SOIC (.300”)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
Example
PICXXFXXXX-I
/SO
0810017
XXXXXXX
20-Lead QFN
XXXXXXX
YYWWNNN
18F14K50
Example
-I/ML
0810017
PIC18F/LF1XK50
DS41350E-page 400 Preliminary 2010 Microchip Technology Inc.
29.2 Package Details
The following sections give the technical details of the packages.
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b
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2010 Microchip Technology Inc. Preliminary DS41350E-page 401
PIC18F/LF1XK50
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PIC18F/LF1XK50
DS41350E-page 402 Preliminary 2010 Microchip Technology Inc.
$ $ '( )&% $*
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1 2 3
NOTE 1
A
A1
A2
h
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c
L1
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α
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* , 1
2010 Microchip Technology Inc. Preliminary DS41350E-page 403
PIC18F/LF1XK50
20-Lead Plastic Quad Flat, No Lead Package (MQ) 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-120A
PIC18F/LF1XK50
DS41350E-page 404 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 405
PIC18F/LF1XK50
APPENDIX A: REVISION HISTORY
Revision A (May 2008)
Original data sheet for PIC18F1XK50/PIC18LF1XK50
devices.
Revision B (June 2008)
Revised 27.4 DC Characteristics table.
Revision C (04/2009)
Revised data sheet title; Revised Features section;
Revised Table 1-2; Revised Table 3-1, Table 3-2;
Added Note 3 in Section 9.1; Revised Register 14-1;
Revised Example 16-1; Revised Section 18.8.4;
Revised Register 18-3; Revised Table 20-2; Revised
Sections 22.2.1, 22.2.2, 22.5.1.1, 22.7; Revised Tables
23-4, 27-1, 27-2, 27-3 27-4, 27-8.
Revision D (05/2010)
Revised the 20-pin PDIP, SSOP, SOIC Diagram;
Added the 20-pin QFN Diagram; Revised Table 1,
Table 1-1; Revised Figure 2-1; Added Note below Section
2.11.1 (Low Speed Operation); Revised Table 3-1,
Table 3-2; Revised Section 4 (Flash Program Memory)
and Section 5 (Data EEPROM Memory); Revised
Example 5-2, Table 5-1; Deleted Note 1 from Registers
7-4, 7-8; Revised Tables 9-1, 9-3; Revised Sections
14.1 (ECCP Outputs and Configuration), 14.4.4
(Enhanced PWM Auto-Shutdown Mode); Added Note 4
below Register 14-2; Revised Figure 14-10; Revised
Equation 17-1; Revised Table 18-3 and Table 20-3;
Revised Equation 21-1; Deleted Section 21.1.3 (Output
Clamped to VSS); Revised Figure 21-1; Revised Table
21-1, Table 23-4 and Table 24-1; Added Note 2 to Table
24-1; Revised Register 24-6; Deleted Note 1 from
Table 24-3; Revised Section 27 (tables); Added 20-
Lead QFN Package Marking Information and Package
Details; Revised the Product Identification System
Section; Other minor corrections.
Revision E (10/2010)
Updated Section 27.0 Electrical Specifications.
PIC18F/LF1XK50
DS41350E-page 406 Preliminary 2010 Microchip Technology Inc.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Features PIC18F13K50 PIC18F14K50 PIC18LF13K50 PIC18F26K20 PIC18LF14K50 PIC18F44K20 PIC18F45K20 PIC18F46K20
Program Memory
(Bytes)
8192 16384 32768 65536 8192 16384 32768 65536
Program Memory
(Instructions)
4096 8192 16384 32768 4096 8192 16384 32768
Interrupt Sources 19 19 19 19 20 20 20 20
I/O Ports Ports A, B, C,
(E)
Ports A, B, C,
(E)
Ports A, B, C,
(E)
Ports A, B, C,
(E)
Ports A, B, C,
D, E
Ports A, B, C,
D, E
Ports A, B, C,
D, E
Ports A, B, C,
D, E
Capture/Compare/
PWM Modules
1 1 1 1 1 1 1 1
Enhanced
Capture/Compare/
PWM Modules
1 1 1 1 1 1 1 1
Parallel
Communications
(PSP)
No No No No Yes Yes Yes Yes
10-bit Analog-to-
Digital Module
11 input
channels
11 input
channels
11 input
channels
11 input
channels
14 input
channels
14 input
channels
14 input
channels
14 input
channels
Packages 20-pin PDIP
20-pin SOIC
20-pin SSOP
20-pin QFN
20-pin PDIP
20-pin SOIC
20-pin SSOP
20-pin QFN
20-pin PDIP
20-pin SOIC
20-pin SSOP
20-pin QFN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
20-pin PDIP
20-pin SOIC
20-pin SSOP
20-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
2010 Microchip Technology Inc. Preliminary DS41350E-page 407
PIC18F/LF1XK50
INDEX
A
A/D
Analog Port Pins, Configuring .................................. 221
Associated Registers ............................................... 221
Conversions ............................................................. 212
Discharge ................................................................. 213
Selecting and Configuring Acquisition Time ............ 210
Specifications ........................................................... 387
Absolute Maximum Ratings ............................................. 363
AC Characteristics
Industrial and Extended ........................................... 379
Load Conditions ....................................................... 378
Access Bank
Mapping with Indexed Literal Offset Mode ................. 50
ACKSTAT ........................................................................ 171
ACKSTAT Status Flag ..................................................... 171
ADC ................................................................................. 209
Acquisition Requirements ........................................ 219
Block Diagram .......................................................... 209
Calculating Acquisition Time .................................... 219
Channel Selection .................................................... 210
Configuration ............................................................ 210
Conversion Clock ..................................................... 210
Conversion Procedure ............................................. 214
Internal Sampling Switch (RSS) IMPEDANCE ............. 219
Interrupts .................................................................. 211
Operation ................................................................. 212
Operation During Sleep ........................................... 213
Port Configuration .................................................... 210
Power Management ................................................. 213
Reference Voltage (VREF) ........................................ 210
Result Formatting ..................................................... 211
Source Impedance ................................................... 219
Special Event Trigger ............................................... 213
Starting an A/D Conversion ..................................... 211
ADCON0 Register ............................................................ 215
ADCON1 Register .................................................... 216, 217
ADDFSR .......................................................................... 352
ADDLW ............................................................................ 315
ADDULNK ........................................................................ 352
ADDWF ............................................................................ 315
ADDWFC ......................................................................... 316
ADRESH Register (ADFM = 0) ........................................ 218
ADRESH Register (ADFM = 1) ........................................ 218
ADRESL Register (ADFM = 0) ......................................... 218
ADRESL Register (ADFM = 1) ......................................... 218
Analog Input Connection Considerations ......................... 231
Analog-to-Digital Converter. See ADC
ANDLW ............................................................................ 316
ANDWF ............................................................................ 317
ANSEL (PORT Analog Control) ......................................... 98
ANSEL Register ................................................................. 98
ANSELH Register .............................................................. 99
Assembler
MPASM Assembler .................................................. 360
B
Bank Select Register (BSR) ............................................... 35
Baud Rate Generator ....................................................... 167
BAUDCON Register ......................................................... 192
BC .................................................................................... 317
BCF .................................................................................. 318
BF .................................................................................... 171
BF Status Flag ................................................................. 171
Block Diagrams
ADC ......................................................................... 209
ADC Transfer Function ............................................ 220
Analog Input Model .......................................... 220, 231
Baud Rate Generator .............................................. 167
Capture Mode Operation ......................................... 119
Clock Source ............................................................. 16
Comparator 1 ........................................................... 224
Comparator 2 ........................................................... 225
Crystal Operation ....................................................... 17
EUSART Receive .................................................... 182
EUSART Transmit ................................................... 181
External POR Circuit (Slow VDD Power-up) ............ 279
External RC Mode ..................................................... 18
Fail-Safe Clock Monitor (FSCM) ................................ 26
Generic I/O Port ......................................................... 83
Interrupt Logic ............................................................ 69
MSSP (I2C Master Mode) ........................................ 165
MSSP (I2C Mode) .................................................... 148
MSSP (SPI Mode) ................................................... 139
On-Chip Reset Circuit .............................................. 277
PIC18F1XK50/PIC18LF1XK50 .................................. 12
PWM (Enhanced) .................................................... 121
Reads from Flash Program Memory ......................... 55
Resonator Operation ................................................. 18
Table Read Operation ............................................... 51
Table Write Operation ............................................... 52
Table Writes to Flash Program Memory .................... 57
Timer0 in 16-Bit Mode ............................................. 103
Timer0 in 8-Bit Mode ............................................... 102
Timer1 ..................................................................... 106
Timer1 (16-Bit Read/Write Mode) ............................ 106
Timer2 ..................................................................... 112
Timer3 ..................................................................... 114
Timer3 (16-Bit Read/Write Mode) ............................ 115
USB Interrupt Logic ................................................. 265
USB Peripheral and Options ................................... 251
Voltage Reference ................................................... 246
Voltage Reference Output Buffer Example ............. 247
Watchdog Timer ...................................................... 302
BN .................................................................................... 318
BNC ................................................................................. 319
BNN ................................................................................. 319
BNOV .............................................................................. 320
BNZ ................................................................................. 320
BOR. See Brown-out Reset.
BOV ................................................................................. 323
BRA ................................................................................. 321
Break Character (12-bit) Transmit and Receive .............. 200
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ................................................... 280
Detecting ................................................................. 280
Disabling in Sleep Mode .......................................... 280
Software Enabled .................................................... 280
Specifications .......................................................... 385
Timing and Characteristics ...................................... 384
BSF .................................................................................. 321
BTFSC ............................................................................. 322
BTFSS ............................................................................. 322
BTG ................................................................................. 323
BZ .................................................................................... 324
PIC18F/LF1XK50
DS41350E-page 408 Preliminary 2010 Microchip Technology Inc.
C
C Compilers
MPLAB C18 ............................................................. 360
CALL ................................................................................ 324
CALLW ............................................................................. 353
Capture (CCP Module) ..................................................... 119
CCP Pin Configuration ............................................. 119
CCPRxH:CCPRxL Registers ................................... 119
Prescaler .................................................................. 119
Software Interrupt .................................................... 119
Timer1/Timer3 Mode Selection ................................ 119
Capture/Compare/PWM (CCP)
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................118
Compare Mode. See Compare.
CCP1CON Register ......................................................... 117
Clock Accuracy with Asynchronous Operation ................ 190
Clock Sources
Associated registers ...................................................27
External Modes
HS ......................................................................17
LP ....................................................................... 17
XT ......................................................................17
CLRF ................................................................................ 325
CLRWDT .......................................................................... 325
CM1CON0 Register ......................................................... 229
CM2CON0 Register ......................................................... 230
CM2CON1 Register ......................................................... 233
Code Examples
16 x 16 Signed Multiply Routine ................................66
16 x 16 Unsigned Multiply Routine ............................66
8 x 8 Signed Multiply Routine .................................... 65
8 x 8 Unsigned Multiply Routine ................................65
A/D Conversion ........................................................ 214
Changing Between Capture Prescalers ................... 119
Clearing RAM Using Indirect Addressing ................... 46
Computed GOTO Using an Offset Value ................... 32
Data EEPROM Read .................................................63
Data EEPROM Refresh Routine ................................64
Data EEPROM Write .................................................63
Erasing a Flash Program Memory Row ..................... 56
Fast Register Stack .................................................... 32
Implementing a Timer1 Real-Time Clock ................. 109
Initializing PORTA ...................................................... 84
Initializing PORTB ...................................................... 89
Initializing PORTC ...................................................... 94
Loading the SSPBUF (SSPSR) Register ................. 142
Reading a Flash Program Memory Word .................. 55
Saving Status, WREG and BSR Registers in RAM ... 80
Writing to Flash Program Memory ....................... 58–59
Code Protection ............................................................... 291
COMF ............................................................................... 326
Comparator
Associated Registers ...............................................234
Operation ................................................................. 223
Operation During Sleep ........................................... 228
Response Time ........................................................ 226
Comparator Module ......................................................... 223
C1 Output State Versus Input Conditions ................ 226
Comparator Specifications ...............................................389
Comparator Voltage Reference (CVREF)
Associated Registers ...............................................249
Effects of a Reset ............................................. 228, 245
Operation During Sleep ........................................... 245
Overview .................................................................. 245
Comparator Voltage Reference (CVREF)
Response Time ........................................................ 226
Comparators
Effects of a Reset .................................................... 228
Compare (CCP Module) .................................................. 120
CCPRx Register ...................................................... 120
Pin Configuration ..................................................... 120
Software Interrupt .................................................... 120
Special Event Trigger ...................................... 116, 120
Timer1/Timer3 Mode Selection ................................ 120
Computed GOTO ............................................................... 32
CONFIG1H Register ................................................ 293, 294
CONFIG1L Register ........................................................ 293
CONFIG2H Register ........................................................ 296
CONFIG2L Register ........................................................ 295
CONFIG3H Register ........................................................ 297
CONFIG4L Register ........................................................ 297
CONFIG5H Register ........................................................ 298
CONFIG5L Register ........................................................ 298
CONFIG6H Register ........................................................ 299
CONFIG6L Register ........................................................ 299
CONFIG7H Register ........................................................ 300
CONFIG7L Register ........................................................ 300
Configuration Bits ............................................................ 292
Configuration Register Protection .................................... 307
Context Saving During Interrupts ....................................... 80
CPFSEQ .......................................................................... 326
CPFSGT .......................................................................... 327
CPFSLT ........................................................................... 327
Customer Change Notification Service ............................ 417
Customer Notification Service ......................................... 417
Customer Support ............................................................ 417
CVREF Voltage Reference Specifications ........................ 389
D
Data Addressing Modes .................................................... 46
Comparing Addressing Modes with the Extended Instruction
Set Enabled ........................................ 49
Direct ......................................................................... 46
Indexed Literal Offset ................................................ 48
Instructions Affected .......................................... 48
Indirect ....................................................................... 46
Inherent and Literal .................................................... 46
Data EEPROM
Code Protection ....................................................... 307
Data EEPROM Memory ..................................................... 61
Associated Registers ................................................. 64
EEADR Register ........................................................ 61
EECON1 and EECON2 Registers ............................. 61
Operation During Code-Protect ................................. 64
Protection Against Spurious Write ............................. 64
Reading ..................................................................... 63
Using ......................................................................... 64
Write Verify ................................................................ 63
Writing ....................................................................... 63
Data Memory ..................................................................... 35
Access Bank .............................................................. 39
and the Extended Instruction Set .............................. 48
Bank Select Register (BSR) ...................................... 35
General Purpose Registers ....................................... 39
Map for PIC18F13K50/PIC18LF13K50 ..................... 36
Map for PIC18F14K50/PIC18LF14K50 ..................... 37
Special Function Registers ........................................ 39
USB RAM .................................................................. 35
DAW ................................................................................ 328
DC and AC Characteristics
2010 Microchip Technology Inc. Preliminary DS41350E-page 409
PIC18F/LF1XK50
Graphs and Tables .................................................. 397
DC Characteristics
Extended and Industrial ........................................... 374
Industrial and Extended ........................................... 364
DCFSNZ .......................................................................... 329
DECF ............................................................................... 328
DECFSZ ........................................................................... 329
Development Support ...................................................... 359
Device Differences ........................................................... 406
Device Overview .................................................................. 9
Details on Individual Family Members ....................... 10
Features (28-Pin Devices) ......................................... 11
New Core Features ...................................................... 9
Other Special Features .............................................. 10
Device Reset Timers ........................................................ 281
Oscillator Start-up Timer (OST) ............................... 281
PLL Lock Time-out ................................................... 281
Power-up Timer (PWRT) ......................................... 281
Time-out Sequence .................................................. 281
DEVID1 Register .............................................................. 301
DEVID2 Register .............................................................. 301
Direct Addressing ............................................................... 47
E
ECCPAS Register ............................................................ 129
EECON1 Register ........................................................ 53, 62
Effect on Standard PIC Instructions ................................. 356
Electrical Specifications ................................................... 363
Enhanced Capture/Compare/PWM (ECCP) .................... 117
Associated Registers ............................................... 138
Enhanced PWM Mode ............................................. 121
Auto-Restart ..................................................... 131
Auto-shutdown ................................................. 129
Direction Change in Full-Bridge Output Mode . 127
Full-Bridge Application ..................................... 125
Full-Bridge Mode ............................................. 125
Half-Bridge Application .................................... 124
Half-Bridge Application Examples ................... 132
Half-Bridge Mode ............................................. 124
Output Relationships (Active-High and Active-Low)
.................................................................. 122
Output Relationships Diagram ......................... 123
Programmable Dead Band Delay .................... 132
Shoot-through Current ..................................... 132
Start-up Considerations ................................... 128
Outputs and Configuration ....................................... 118
Specifications ........................................................... 387
Enhanced Universal Synchronous Asynchronous Receiver
Transmitter (EUSART) ............................................. 181
Equations
Estimating USB Transceiver Current Consumption . 273
Errata ................................................................................... 7
EUSART .......................................................................... 181
Asynchronous Mode ................................................ 183
12-bit Break Transmit and Receive ................. 200
Associated Registers, Receive ........................ 189
Associated Registers, Transmit ....................... 185
Auto-Wake-up on Break .................................. 198
Baud Rate Generator (BRG) ........................... 193
Clock Accuracy ................................................ 190
Receiver ........................................................... 186
Setting up 9-bit Mode with Address Detect ...... 188
Transmitter ....................................................... 183
Baud Rate Generator (BRG)
Associated Registers ....................................... 193
Auto Baud Rate Detect .................................... 197
Baud Rate Error, Calculating ........................... 193
Baud Rates, Asynchronous Modes ................. 194
Formulas .......................................................... 193
High Baud Rate Select (BRGH Bit) ................. 193
Clock polarity
Synchronous Mode .......................................... 201
Data polarity
Asynchronous Receive .................................... 186
Asynchronous Transmit ................................... 183
Synchronous Mode .......................................... 201
Interrupts
Asynchronous Receive .................................... 187
Asynchronous Transmit ................................... 184
Synchronous Master Mode .............................. 201, 205
Associated Registers, Receive ........................ 205
Associated Registers, Transmit ............... 203, 206
Reception ........................................................ 203
Transmission ................................................... 201
Synchronous Slave Mode
Associated Registers, Receive ........................ 207
Reception ........................................................ 206
Transmission ................................................... 205
Extended Instruction Set
ADDFSR .................................................................. 352
ADDULNK ............................................................... 352
and Using MPLAB Tools ......................................... 358
CALLW .................................................................... 353
Considerations for Use ............................................ 356
MOVSF .................................................................... 353
MOVSS .................................................................... 354
PUSHL ..................................................................... 354
SUBFSR .................................................................. 355
SUBULNK ................................................................ 355
Syntax ...................................................................... 351
F
Fail-Safe Clock Monitor ............................................. 26, 291
Fail-Safe Condition Clearing ...................................... 27
Fail-Safe Detection .................................................... 26
Fail-Safe Operation ................................................... 26
Reset or Wake-up from Sleep ................................... 27
Fast Register Stack ........................................................... 32
Firmware Instructions ...................................................... 309
Flash Program Memory ..................................................... 51
Associated Registers ................................................. 59
Control Registers ....................................................... 52
EECON1 and EECON2 ..................................... 52
TABLAT (Table Latch) Register ........................ 54
TBLPTR (Table Pointer) Register ...................... 54
Erase Sequence ........................................................ 56
Erasing ...................................................................... 56
Operation During Code-Protect ................................. 59
Reading ..................................................................... 55
Table Pointer
Boundaries Based on Operation ....................... 54
Table Pointer Boundaries .......................................... 54
Table Reads and Table Writes .................................. 51
Write Sequence ......................................................... 57
Writing To .................................................................. 57
Protection Against Spurious Writes ................... 59
Unexpected Termination ................................... 59
Write Verify ........................................................ 59
G
General Call Address Support ......................................... 164
GOTO .............................................................................. 330
PIC18F/LF1XK50
DS41350E-page 410 Preliminary 2010 Microchip Technology Inc.
H
Hardware Multiplier ............................................................ 65
Introduction ................................................................ 65
Operation ................................................................... 65
Performance Comparison .......................................... 65
I
I/O Ports ............................................................................. 83
I2C
Associated Registers ...............................................180
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 174
Baud Rate Generator ...............................................167
Bus Collision
During a Repeated Start Condition .................. 178
During a Stop Condition ................................... 179
Clock Arbitration ....................................................... 168
Clock Stretching ....................................................... 160
10-Bit Slave Receive Mode (SEN = 1) ............. 160
10-Bit Slave Transmit Mode ............................. 160
7-Bit Slave Receive Mode (SEN = 1) ............... 160
7-Bit Slave Transmit Mode ............................... 160
Clock Synchronization and the CKP bit (SEN = 1) .. 161
Effects of a Reset ..................................................... 175
General Call Address Support ................................. 164
I2C Clock Rate w/BRG ............................................. 167
Master Mode ............................................................ 165
Operation ......................................................... 166
Reception ......................................................... 171
Repeated Start Condition Timing ..................... 170
Start Condition Timing ..................................... 169
Transmission .................................................... 171
Multi-Master Communication, Bus Collision and Arbitration
................................................................... 175
Multi-Master Mode ...................................................175
Operation ................................................................. 152
Read/Write Bit Information (R/W Bit) ............... 152, 153
Registers .................................................................. 148
Serial Clock (RC3/SCK/SCL) ................................... 153
Slave Mode .............................................................. 152
Addressing ....................................................... 152
Reception ......................................................... 153
Transmission .................................................... 153
Sleep Operation ....................................................... 175
Stop Condition Timing .............................................. 174
ID Locations ............................................................. 291, 307
INCF ................................................................................. 330
INCFSZ ............................................................................ 331
In-Circuit Debugger .......................................................... 307
In-Circuit Serial Programming (ICSP) ...................... 291, 307
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 356
Indexed Literal Offset Mode ............................................. 356
Indirect Addressing ............................................................ 47
INFSNZ ............................................................................ 331
Initialization Conditions for all Registers .................. 285–289
Instruction Cycle ................................................................. 33
Clocking Scheme ....................................................... 33
Instruction Flow/Pipelining .................................................33
Instruction Set .................................................................. 309
ADDLW ....................................................................315
ADDWF ....................................................................315
ADDWF (Indexed Literal Offset Mode) .................... 357
ADDWFC ................................................................. 316
ANDLW ....................................................................316
ANDWF .................................................................... 317
BC ............................................................................ 317
BCF ......................................................................... 318
BN ............................................................................ 318
BNC ......................................................................... 319
BNN ......................................................................... 319
BNOV ...................................................................... 320
BNZ ......................................................................... 320
BOV ......................................................................... 323
BRA ......................................................................... 321
BSF .......................................................................... 321
BSF (Indexed Literal Offset Mode) .......................... 357
BTFSC ..................................................................... 322
BTFSS ..................................................................... 322
BTG ......................................................................... 323
BZ ............................................................................ 324
CALL ........................................................................ 324
CLRF ....................................................................... 325
CLRWDT ................................................................. 325
COMF ...................................................................... 326
CPFSEQ .................................................................. 326
CPFSGT .................................................................. 327
CPFSLT ................................................................... 327
DAW ........................................................................ 328
DCFSNZ .................................................................. 329
DECF ....................................................................... 328
DECFSZ .................................................................. 329
Extended Instruction Set ......................................... 351
General Format ........................................................ 311
GOTO ...................................................................... 330
INCF ........................................................................ 330
INCFSZ .................................................................... 331
INFSNZ .................................................................... 331
IORLW ..................................................................... 332
IORWF ..................................................................... 332
LFSR ....................................................................... 333
MOVF ...................................................................... 333
MOVFF .................................................................... 334
MOVLB .................................................................... 334
MOVLW ................................................................... 335
MOVWF ................................................................... 335
MULLW .................................................................... 336
MULWF .................................................................... 336
NEGF ....................................................................... 337
NOP ......................................................................... 337
Opcode Field Descriptions ....................................... 310
POP ......................................................................... 338
PUSH ....................................................................... 338
RCALL ..................................................................... 339
RESET ..................................................................... 339
RETFIE .................................................................... 340
RETLW .................................................................... 340
RETURN .................................................................. 341
RLCF ....................................................................... 341
RLNCF ..................................................................... 342
RRCF ....................................................................... 342
RRNCF .................................................................... 343
SETF ....................................................................... 343
SETF (Indexed Literal Offset Mode) ........................ 357
SLEEP ..................................................................... 344
SUBFWB ................................................................. 344
SUBLW .................................................................... 345
SUBWF .................................................................... 345
SUBWFB ................................................................. 346
SWAPF .................................................................... 346
2010 Microchip Technology Inc. Preliminary DS41350E-page 411
PIC18F/LF1XK50
TBLRD ..................................................................... 347
TBLWT ..................................................................... 348
TSTFSZ ................................................................... 349
XORLW .................................................................... 349
XORWF .................................................................... 350
INTCON Register ............................................................... 70
INTCON Registers ....................................................... 70–72
INTCON2 Register ............................................................. 71
INTCON3 Register ............................................................. 72
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block
INTOSC
Specifications ........................................... 382, 383
Internal RC Oscillator
Use with WDT .......................................................... 302
Internal Sampling Switch (RSS) IMPEDANCE ..................... 219
Internet Address ............................................................... 417
Interrupt Sources ............................................................. 291
ADC ......................................................................... 211
Capture Complete (CCP) ......................................... 119
Compare Complete (CCP) ....................................... 120
Interrupt-on-Change (RB7:RB4) .......................... 83, 89
INTn Pin ..................................................................... 80
PORTB, Interrupt-on-Change .................................... 80
TMR0 ......................................................................... 80
TMR0 Overflow ........................................................ 103
TMR1 Overflow ........................................................ 105
TMR3 Overflow ................................................ 113, 115
Interrupts ............................................................................ 67
INTOSC Specifications ............................................ 382, 383
IOCA Register .................................................................... 86
IOCB Register .................................................................... 91
IORLW ............................................................................. 332
IORWF ............................................................................. 332
IPR Registers ..................................................................... 77
IPR1 Register ..................................................................... 77
IPR2 Register ..................................................................... 78
L
LATA Register .................................................................... 86
LATB Register .................................................................... 91
LATC Register ................................................................... 95
LFSR ................................................................................ 333
Load Conditions ............................................................... 378
Low-Voltage ICSP Programming. See Single-Supply ICSP
Programming
M
Master Clear (MCLR) ....................................................... 279
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ......................................................... 29
Data Memory ............................................................. 35
Program Memory ....................................................... 29
Microchip Internet Web Site ............................................. 417
MOVF ............................................................................... 333
MOVFF ............................................................................ 334
MOVLB ............................................................................ 334
MOVLW ........................................................................... 335
MOVSF ............................................................................ 353
MOVSS ............................................................................ 354
MOVWF ........................................................................... 335
MPLAB ASM30 Assembler, Linker, Librarian .................. 360
MPLAB Integrated Development Environment Software . 359
MPLAB PM3 Device Programmer ................................... 362
MPLAB REAL ICE In-Circuit Emulator System ................ 361
MPLINK Object Linker/MPLIB Object Librarian ............... 360
MSSP
ACK Pulse ....................................................... 152, 153
I2C Mode. See I2C Mode.
Module Overview ..................................................... 139
SPI Mode. See SPI Mode.
SSPBUF Register .................................................... 144
SSPSR Register ...................................................... 144
MULLW ............................................................................ 336
MULWF ............................................................................ 336
N
NEGF ............................................................................... 337
NOP ................................................................................. 337
O
OSCCON Register ....................................................... 20, 21
Oscillator Module ............................................................... 15
Oscillator Parameters ...................................................... 382
Oscillator Selection .......................................................... 291
Oscillator Specifications ................................................... 381
Oscillator Start-up Timer (OST) ....................................... 281
Specifications .......................................................... 385
Oscillator Switching
Fail-Safe Clock Monitor ............................................. 26
Oscillator, Timer1 ..................................................... 105, 115
Oscillator, Timer3 ............................................................. 113
OSCTUNE Register ........................................................... 22
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/PWM
(ECCP) .................................................................... 121
Packaging Information ..................................................... 399
Marking .................................................................... 399
PIE Registers ..................................................................... 75
PIE1 Register .................................................................... 75
PIE2 Register .................................................................... 76
Pinout Descriptions
PIC18F1XK50/PIC18LF1XK50 .................................. 13
PIR Registers ..................................................................... 73
PIR1 Register .................................................................... 73
PIR2 Register .................................................................... 74
POP ................................................................................. 338
POR. See Power-on Reset.
PORTA
Associated Registers ................................................. 88
LATA Register ........................................................... 83
PORTA Register ........................................................ 83
Specifications .......................................................... 383
TRISA Register .......................................................... 83
PORTA Register ................................................................ 85
PORTB
Associated Registers ................................................. 93
LATB Register ........................................................... 89
PORTB Register ........................................................ 89
TRISB Register .......................................................... 89
PORTB Register .......................................................... 90, 94
PORTC
Associated Registers ................................................. 97
LATC Register ........................................................... 94
PORTC Register ........................................................ 94
RC3/SCK/SCL Pin ................................................... 153
Specifications .......................................................... 383
TRISC Register ......................................................... 94
Power Managed Modes ................................................... 235
and A/D Operation ................................................... 213
and PWM Operation ................................................ 137
PIC18F/LF1XK50
DS41350E-page 412 Preliminary 2010 Microchip Technology Inc.
and SPI Operation ...................................................147
Entering ....................................................................235
Exiting Idle and Sleep Modes .................................. 239
by Interrupt ....................................................... 239
by Reset ........................................................... 240
by WDT Time-out ............................................. 239
Without a Start-up Delay .................................. 240
Idle Modes ............................................................... 237
PRI_IDLE ......................................................... 238
RC_IDLE .......................................................... 239
SEC_IDLE ........................................................ 238
Multiple Sleep Functions .......................................... 236
Run Modes ............................................................... 236
PRI_RUN ......................................................... 236
RC_RUN .......................................................... 236
SEC_RUN ........................................................ 236
Selecting .................................................................. 235
Sleep Mode .............................................................. 237
Summary (table) ...................................................... 235
Power-on Reset (POR) .................................................... 279
Power-up Timer (PWRT) ......................................... 281
Time-out Sequence .................................................. 281
Power-up Timer (PWRT)
Specifications ........................................................... 385
Precision Internal Oscillator Parameters ..........................383
Prescaler, Timer0 ............................................................. 103
PRI_IDLE Mode ............................................................... 238
PRI_RUN Mode ............................................................... 236
Program Counter ................................................................ 30
PCL, PCH and PCU Registers ................................... 30
PCLATH and PCLATU Registers ..............................30
Program Memory
and Extended Instruction Set ..................................... 50
Code Protection ....................................................... 305
Instructions ................................................................. 34
Two-Word .......................................................... 34
Interrupt Vector .......................................................... 29
Look-up Tables .......................................................... 32
Map and Stack (diagram) ........................................... 29
Reset Vector .............................................................. 29
Program Verification and Code Protection ....................... 303
Associated Registers ...............................................305
Programming, Device Instructions ................................... 309
PSTRCON Register ......................................................... 134
Pulse Steering .................................................................. 134
PUSH ............................................................................... 338
PUSH and POP Instructions .............................................. 31
PUSHL ............................................................................. 354
PWM (ECCP Module)
Effects of a Reset ..................................................... 137
Operation in Power Managed Modes ...................... 137
Operation with Fail-Safe Clock Monitor ................... 137
Pulse Steering .......................................................... 134
Steering Synchronization ......................................... 136
PWM Mode. See Enhanced Capture/Compare/PWM .....121
PWM1CON Register ........................................................ 133
R
RAM. See Data Memory.
RC_IDLE Mode ................................................................ 239
RC_RUN Mode ................................................................ 236
RCALL .............................................................................. 339
RCON Register .......................................................... 79, 278
Bit Status During Initialization .................................. 284
RCREG ............................................................................ 188
RCSTA Register ............................................................... 191
Reader Response ............................................................ 418
RECON0 (Reference Control 0) Register ........................ 247
RECON1 (Reference Control 1) Register ........................ 248
RECON2 (Reference Control 2) Register ........................ 248
Register
RCREG Register ..................................................... 197
Register File ....................................................................... 39
Register File Summary ...................................................... 41
Registers
ADCON0 (ADC Control 0) ....................................... 215
ADCON1 (ADC Control 1) ............................... 216, 217
ADRESH (ADC Result High) with ADFM = 0) ......... 218
ADRESH (ADC Result High) with ADFM = 1) ......... 218
ADRESL (ADC Result Low) with ADFM = 0) ........... 218
ADRESL (ADC Result Low) with ADFM = 1) ........... 218
ANSEL (Analog Select 1) .......................................... 98
ANSEL (PORT Analog Control) ................................. 98
ANSELH (Analog Select 2) ........................................ 99
ANSELH (PORT Analog Control) .............................. 99
BAUDCON (EUSART Baud Rate Control) .............. 192
BDnSTAT (Buffer Descriptor n Status, CPU Mode) 261
BDnSTAT (Buffer Descriptor n Status, SIE Mode) .. 262
CCP1CON (Enhanced Capture/Compare/PWM Control)
.......................................................................... 117
CM1CON0 (C1 Control) ........................................... 229
CM2CON0 (C2 Control) ........................................... 230
CM2CON1 (C2 Control) ........................................... 233
CONFIG1H (Configuration 1 High) .................. 293, 294
CONFIG1L (Configuration 1 Low) ........................... 293
CONFIG2H (Configuration 2 High) .......................... 296
CONFIG2L (Configuration 2 Low) ........................... 295
CONFIG3H (Configuration 3 High) .......................... 297
CONFIG4L (Configuration 4 Low) ........................... 297
CONFIG5H (Configuration 5 High) .......................... 298
CONFIG5L (Configuration 5 Low) ........................... 298
CONFIG6H (Configuration 6 High) .......................... 299
CONFIG6L (Configuration 6 Low) ........................... 299
CONFIG7H (Configuration 7 High) .......................... 300
CONFIG7L (Configuration 7 Low) ........................... 300
DEVID1 (Device ID 1) .............................................. 301
DEVID2 (Device ID 2) .............................................. 301
ECCPAS (Enhanced CCP Auto-shutdown Control) 129
EECON1 (Data EEPROM Control 1) ................... 53, 62
INTCON (Interrupt Control) ........................................ 70
INTCON2 (Interrupt Control 2) ................................... 71
INTCON3 (Interrupt Control 3) ................................... 72
IOCA (Interrupt-on-Change PORTA) ......................... 86
IOCB (Interrupt-on-Change PORTB) ......................... 91
IPR1 (Peripheral Interrupt Priority 1) ......................... 77
IPR2 (Peripheral Interrupt Priority 2) ......................... 78
LATA (PORTA Data Latch) ........................................ 86
LATB (PORTB Data Latch) ........................................ 91
LATC (PORTC Data Latch) ....................................... 95
OSCCON (Oscillator Control) .............................. 20, 21
OSCTUNE (Oscillator Tuning) ................................... 22
PIE1 (Peripheral Interrupt Enable 1) .......................... 75
PIE2 (Peripheral Interrupt Enable 2) .......................... 76
PIR1 (Peripheral Interrupt Request 1) ....................... 73
PIR2 (Peripheral Interrupt Request 2) ....................... 74
PORTA ...................................................................... 85
PORTB ................................................................ 90, 94
PSTRCON (Pulse Steering Control) ........................ 134
PWM1CON (Enhanced PWM Control) .................... 133
RCON (Reset Control) ....................................... 79, 278
RCSTA (Receive Status and Control) ..................... 191
2010 Microchip Technology Inc. Preliminary DS41350E-page 413
PIC18F/LF1XK50
REFCON0 ................................................................ 247
REFCON1 ................................................................ 248
REFCON2 ................................................................ 248
SLRCON (PORT Slew Rate Control) ....................... 100
SRCON0 (SR Latch Control 0) ................................ 242
SRCON1 (SR Latch Control 1) ................................ 243
SSPADD (MSSP Address and Baud Rate, SPI Mode) ..
159
SSPCON1 (MSSP Control 1, I2C Mode) ................. 150
SSPCON1 (MSSP Control 1, SPI Mode) ................. 141
SSPCON2 (MSSP Control 2, I2C Mode) ................. 151
SSPMSK (SSP Mask) .............................................. 158
SSPSTAT (MSSP Status, SPI Mode) .............. 140, 149
STATUS ..................................................................... 45
STKPTR (Stack Pointer) ............................................ 31
T0CON (Timer0 Control) .......................................... 101
T1CON (Timer1 Control) .......................................... 105
T2CON (Timer2 Control) .......................................... 111
T3CON (Timer3 Control) .......................................... 113
TRISA (Tri-State PORTA) .......................................... 85
TRISB (Tri-State PORTB) .................................... 90, 94
TXSTA (Transmit Status and Control) ..................... 190
UCFG (USB Configuration) ...................................... 254
UCON (USB Control) ............................................... 252
UEIE (USB Error Interrupt Enable) .......................... 270
UEIR (USB Error Interrupt Status) ........................... 269
UEPn (USB Endpoint n Control) .............................. 257
UIE (USB Interrupt Enable) ...................................... 268
UIR (USB Interrupt Status) ...................................... 266
USTAT (USB Status) ............................................... 256
WDTCON (Watchdog Timer Control) ...................... 303
WPUA (Weak Pull-up PORTA) .................................. 86
WPUB (Weak Pull-up PORTB) .................................. 91
RESET ............................................................................. 339
Reset State of Registers .................................................. 284
Resets ...................................................................... 277, 291
Brown-out Reset (BOR) ........................................... 291
Oscillator Start-up Timer (OST) ............................... 291
Power-on Reset (POR) ............................................ 291
Power-up Timer (PWRT) ......................................... 291
RETFIE ............................................................................ 340
RETLW ............................................................................ 340
RETURN .......................................................................... 341
Return Address Stack ........................................................ 30
Return Stack Pointer (STKPTR) ........................................ 31
Revision History ............................................................... 405
RLCF ................................................................................ 341
RLNCF ............................................................................. 342
RRCF ............................................................................... 342
RRNCF ............................................................................ 343
S
SCK .................................................................................. 139
SDI ................................................................................... 139
SDO ................................................................................. 139
SEC_IDLE Mode .............................................................. 238
SEC_RUN Mode .............................................................. 236
Serial Clock, SCK ............................................................ 139
Serial Data In (SDI) .......................................................... 139
Serial Data Out (SDO) ..................................................... 139
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 343
Shoot-through Current ..................................................... 132
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 139
Slave Select Synchronization .......................................... 145
SLEEP ............................................................................. 344
Sleep Mode ..................................................................... 237
SLRCON Register ........................................................... 100
Software Simulator (MPLAB SIM) ................................... 361
SPBRG ............................................................................ 193
SPBRGH ......................................................................... 193
Special Event Trigger ...................................................... 213
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ........................................... 291
Special Function Registers ................................................ 39
Map ............................................................................ 40
SPI Mode
Typical Master/Slave Connection ............................ 143
SPI Mode (MSSP)
Associated Registers ............................................... 147
Bus Mode Compatibility ........................................... 147
Effects of a Reset .................................................... 147
Enabling SPI I/O ...................................................... 143
Master Mode ............................................................ 144
Operation ................................................................. 142
Operation in Power Managed Modes ...................... 147
Serial Clock ............................................................. 139
Serial Data In ........................................................... 139
Serial Data Out ........................................................ 139
Slave Mode .............................................................. 145
Slave Select ............................................................. 139
Slave Select Synchronization .................................. 145
SPI Clock ................................................................. 144
Typical Connection .................................................. 143
SR Latch .......................................................................... 241
Associated Registers ............................................... 243
SRCON0 Register ........................................................... 242
SRCON1 Register ........................................................... 243
SS .................................................................................... 139
SSP
Typical SPI Master/Slave Connection ..................... 143
SSPADD Register ............................................................ 159
SSPCON1 Register ................................................. 141, 150
SSPCON2 Register ......................................................... 151
SSPMSK Register ........................................................... 158
SSPOV ............................................................................ 171
SSPOV Status Flag ......................................................... 171
SSPSTAT Register .................................................. 140, 149
R/W Bit ............................................................ 152, 153
Stack Full/Underflow Resets .............................................. 32
Standard Instructions ....................................................... 309
STATUS Register .............................................................. 45
STKPTR Register .............................................................. 31
SUBFSR .......................................................................... 355
SUBFWB ......................................................................... 344
SUBLW ............................................................................ 345
SUBULNK ........................................................................ 355
SUBWF ............................................................................ 345
SUBWFB ......................................................................... 346
SWAPF ............................................................................ 346
T
T0CON Register .............................................................. 101
T1CON Register .............................................................. 105
T2CON Register .............................................................. 111
T3CON Register .............................................................. 113
Table Pointer Operations (table) ........................................ 54
Table Reads/Table Writes ................................................. 32
TBLRD ............................................................................. 347
TBLWT ............................................................................ 348
Thermal Considerations ................................................... 377
PIC18F/LF1XK50
DS41350E-page 414 Preliminary 2010 Microchip Technology Inc.
Time-out in Various Situations (table) ..............................281
Timer0 .............................................................................. 101
Associated Registers ...............................................103
Operation ................................................................. 102
Overflow Interrupt .................................................... 103
Prescaler .................................................................. 103
Prescaler Assignment (PSA Bit) ..............................103
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 103
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................102
Source Edge Select (T0SE Bit) ................................ 102
Source Select (T0CS Bit) ......................................... 102
Specifications ........................................................... 386
Switching Prescaler Assignment ..............................103
Timer1 .............................................................................. 105
16-Bit Read/Write Mode ........................................... 107
Associated Registers ...............................................110
Interrupt ....................................................................108
Operation ................................................................. 106
Oscillator .......................................................... 105, 107
Oscillator Layout Considerations ............................. 108
Overflow Interrupt .................................................... 105
Resetting, Using the CCP Special Event Trigger .....108
Specifications ........................................................... 386
TMR1H Register ...................................................... 105
TMR1L Register ....................................................... 105
Use as a Real-Time Clock ....................................... 109
Timer2 .............................................................................. 111
Associated Registers ...............................................112
Interrupt ....................................................................112
Operation ................................................................. 111
Output ......................................................................112
Timer3 .............................................................................. 113
16-Bit Read/Write Mode ........................................... 115
Associated Registers ...............................................116
Operation ................................................................. 114
Oscillator .......................................................... 113, 115
Overflow Interrupt ............................................ 113, 115
Special Event Trigger (CCP) .................................... 116
TMR3H Register ...................................................... 113
TMR3L Register ....................................................... 113
Timing Diagrams
A/D Conversion ........................................................ 388
Acknowledge Sequence .......................................... 174
Asynchronous Reception ......................................... 188
Asynchronous Transmission .................................... 185
Asynchronous Transmission (Back to Back) ........... 185
Auto Wake-up Bit (WUE) During Normal Operation 199
Auto Wake-up Bit (WUE) During Sleep ................... 199
Automatic Baud Rate Calculator ..............................197
Baud Rate Generator with Clock Arbitration ............ 168
BRG Reset Due to SDA Arbitration During Start Condition
................................................................... 177
Brown-out Reset (BOR) ........................................... 384
Bus Collision During a Repeated Start Condition (Case
1) ......................................................................178
Bus Collision During a Repeated Start Condition (Case
2) ......................................................................178
Bus Collision During a Start Condition (SCL = 0) .... 177
Bus Collision During a Stop Condition (Case 1) ...... 179
Bus Collision During a Stop Condition (Case 2) ...... 179
Bus Collision During Start Condition (SDA only) .....176
Bus Collision for Transmit and Acknowledge ........... 175
CLKOUT and I/O ...................................................... 383
Clock Synchronization ............................................. 161
Clock Timing ............................................................ 379
Clock/Instruction Cycle .............................................. 33
Comparator Output .................................................. 223
Enhanced Capture/Compare/PWM (ECCP) ............ 387
Fail-Safe Clock Monitor (FSCM) ................................ 27
First Start Bit Timing ................................................ 169
Full-Bridge PWM Output .......................................... 126
Half-Bridge PWM Output ................................. 124, 132
I2C Bus Data ............................................................ 394
I2C Bus Start/Stop Bits ............................................ 393
I2C Master Mode (7 or 10-Bit Transmission) ........... 172
I2C Master Mode (7-Bit Reception) .......................... 173
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 156
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 163
I2C Slave Mode (10-Bit Transmission) .................... 157
I2C Slave Mode (7-bit Reception, SEN = 0) ............ 154
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 162
I2C Slave Mode (7-Bit Transmission) ...................... 155
I2C Slave Mode General Call Address Sequence (7 or
10-Bit Address Mode) ...................................... 164
I2C Stop Condition Receive or Transmit Mode ........ 174
Internal Oscillator Switch Timing ............................... 23
PWM Auto-shutdown
Auto-restart Enabled ........................................ 131
Firmware Restart ............................................. 130
PWM Direction Change ........................................... 127
PWM Direction Change at Near 100% Duty Cycle .. 128
PWM Output (Active-High) ...................................... 122
PWM Output (Active-Low) ....................................... 123
Repeat Start Condition ............................................ 170
Reset, WDT, OST and Power-up Timer .................. 384
Send Break Character Sequence ............................ 200
Slave Synchronization ............................................. 145
Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT)
.......................................................................... 283
SPI Master Mode (CKE = 1, SMP = 1) .................... 391
SPI Mode (Master Mode) ......................................... 144
SPI Mode (Slave Mode, CKE = 0) ........................... 146
SPI Mode (Slave Mode, CKE = 1) ........................... 146
SPI Slave Mode (CKE = 0) ...................................... 392
SPI Slave Mode (CKE = 1) ...................................... 392
Synchronous Reception (Master Mode, SREN) ...... 204
Synchronous Transmission ..................................... 202
Synchronous Transmission (Through TXEN) .......... 202
Time-out Sequence on POR w/PLL Enabled (MCLR Tied
to VDD) ............................................................. 283
Time-out Sequence on Power-up (MCLR Not Tied to
VDD, Case 1) ................................................... 282
Time-out Sequence on Power-up (MCLR Not Tied to
VDD, Case 2) ................................................... 282
Time-out Sequence on Power-up (MCLR Tied to VDD,
VDD Rise < TPWRT) .......................................... 282
Timer0 and Timer1 External Clock .......................... 386
Transition for Entry to Sleep Mode .......................... 237
Transition for Wake from Sleep (HSPLL) ................ 237
Transition Timing for Entry to Idle Mode .................. 238
Transition Timing for Wake from Idle to Run Mode . 238
USART Synchronous Receive (Master/Slave) ........ 390
USART Synchronous Transmission (Master/Slave) 390
Timing Diagrams and Specifications
A/D Conversion Requirements ................................ 388
PLL Clock ................................................................ 382
Timing Parameter Symbology ......................................... 378
Timing Requirements
I2C Bus Data ............................................................ 395
2010 Microchip Technology Inc. Preliminary DS41350E-page 415
PIC18F/LF1XK50
I2C Bus Start/Stop Bits ............................................ 394
SPI Mode ................................................................. 393
Top-of-Stack Access .......................................................... 30
TRISA Register .................................................................. 85
TRISB Register ............................................................ 90, 94
TSTFSZ ........................................................................... 349
Two-Speed Start-up ......................................................... 291
Two-Word Instructions
Example Cases .......................................................... 34
TXREG ............................................................................. 183
TXSTA Register ............................................................... 190
BRGH Bit ................................................................. 193
U
Universal Serial Bus
Address Register (UADDR) ..................................... 258
Associated Registers ............................................... 274
Buffer Descriptor Table ............................................ 259
Buffer Descriptors .................................................... 259
Address Validation ........................................... 262
Assignment in Different Buffering Modes ........ 264
BDnSTAT Register (CPU Mode) ..................... 260
BDnSTAT Register (SIE Mode) ....................... 262
Byte Count ....................................................... 262
Example ........................................................... 259
Memory Map .................................................... 263
Ownership ........................................................ 259
Ping-Pong Buffering ......................................... 263
Register Summary ........................................... 264
Status and Configuration ................................. 259
Class Specifications and Drivers ............................. 276
Descriptors ............................................................... 276
Endpoint Control ...................................................... 257
Enumeration ............................................................. 276
External Pull-up Resistors ........................................ 255
Eye Pattern Test Enable .......................................... 255
Firmware and Drivers ............................................... 274
Frame Number Registers ......................................... 258
Frames ..................................................................... 275
Internal Pull-up Resistors ......................................... 255
Internal Transceiver ................................................. 253
Interrupts .................................................................. 265
and USB Transactions ..................................... 265
Layered Framework ................................................. 275
Oscillator Requirements ........................................... 274
Overview .......................................................... 251, 275
Ping-Pong Buffer Configuration ............................... 255
Power ....................................................................... 275
Power Modes ........................................................... 271
Bus Power Only ............................................... 271
Dual Power with Self-Power Dominance ......... 272
Self-Power Only ............................................... 271
RAM ......................................................................... 258
Memory Map .................................................... 258
Speed ....................................................................... 276
Status and Control ................................................... 252
Transfer Types ......................................................... 275
UFRMH:UFRML Registers ...................................... 258
USART
Synchronous Master Mode
Requirements, Synchronous Receive ............. 390
Requirements, Synchronous Transmission ..... 390
Timing Diagram, Synchronous Receive .......... 390
Timing Diagram, Synchronous Transmission .. 390
USB Module Electrical Specifications .............................. 376
USB RAM
Serial Interface Engine (SIE) ..................................... 35
USB. See Universal Serial Bus.
V
Voltage Reference (VR)
Specifications .......................................................... 389
Voltage Reference. See Comparator Voltage Reference
(CVREF)
Voltage References
Fixed Voltage Reference (FVR) .............................. 246
VR Stabilization ....................................................... 246
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ........................................................... 198
Watchdog Timer (WDT) ........................................... 291, 302
Associated Registers ............................................... 303
Control Register ....................................................... 303
Programming Considerations .................................. 302
Specifications .......................................................... 385
WCOL ...................................................... 169, 170, 171, 174
WCOL Status Flag ................................... 169, 170, 171, 174
WDTCON Register .......................................................... 303
WPUA Register .................................................................. 86
WPUB Register .................................................................. 91
WWW Address ................................................................ 417
WWW, On-Line Support ...................................................... 7
X
XORLW ........................................................................... 349
XORWF ........................................................................... 350
PIC18F/LF1XK50
DS41350E-page 416 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 417
PIC18F1XK50/PIC18LF1XK50
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PIC18F1XK50/PIC18LF1XK50
DS41350E-page 418 Preliminary 2010 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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PIC18F1XK50/PIC18LF1XK50 DS41350E
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
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2010 Microchip Technology Inc. Preliminary DS41350E-page 419
PIC18F/LF1XK50
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Temperature Package Pattern
Range
Device
Device: PIC18F13K50(1), PIC18F14K50(1),
PIC18LF13K50(1), PIC18LF14K50
Packaging Option: Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range:
E = -40C to +125C (Extended)
I = -40°C to +85°C (Industrial)
Package: P = PDIP
SO = SOIC
SS = SSOP
MQ = QFN
Pattern: QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18F14K50-E/P 301 = Extended temp.,
PDIP package, Extended VDD limits, QTP pattern
#301.
b) PIC18LF14K50-E/SO = Extended temp., SOIC
package.
c) PIC18LF14K50-E/P = Extended temp., PDIP
package.
d) PIC18LF14K50-E/MQ = Extended temp., QFN
package.
e) PIC18F14K50-I/P = Industrial temp., PDIP
package.
Note 1: Tape and Reel option is available for ML,
MV, PT, SO and SS packages with industrial
Temperature Range only.
X
Packaging
Option
DS41350E-page 420 Preliminary 2010 Microchip Technology Inc.
AMERICAS
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08/04/10
ULINKpro Debug and Trace Unit
The Keil ULINKpro Debug and Trace Unit connects your PC's USB port to your target system (via a JTAG, Cortex Debug, or Cortex Debug+ETM connector). It allows you to program, debug, and analyze your applications using its unique streaming trace technology.
ULINKpro, together with MDK-ARM, provides extended on-the-fly debug capabilities for Cortex-M devices. You are able to control the processor, set breakpoints, and read/write memory contents, all while the processor is running at full speed. High-Speed data and instruction trace are streamed directly to your PC enabling you to analyze detailed program behaviour.
Features
Supports ARM7, ARM9, Cortex-M0, Cortex-M1, Cortex-M3, and Cortex-M4 devices
JTAG support for ARM7, ARM9, and Cortex-M
Serial Wire Debug (SWD) support for Cortex-M
Serial Wire Viewer (SWV) Data and Event Trace for Cortex-M up to 100Mbit/s (Manchester mode)
Instruction Trace (ETM) for Cortex-M3 and Cortex-M4 up to 800Mbit/s
Unique Streaming Trace direct to your PC, provides unlimited trace buffer
JTAG Clock Speed up to 50MHz
Supports Cortex-M devices running at up to 200MHz
High-Speed Memory Read/Write up to 1MBytes/sec
Seamless integration with the Keil μVision IDE & Debugger
Wide target voltage range: 1.2V - 3.3V, 5V tolerant
Support for 5V only devices using optional 5V Adapter
Optional Isolation Adapter provides electrical isolation from the target system
USB 2.0 High-Speed connection
USB powered (no power supply required)
Target Connectors
10-pin (0.05") - Cortex Debug Connector
20-pin (0.10") - ARM Standard JTAG Connector
20-pin (0.05") - Cortex Debug+ETM Connector
The unique streaming trace capabilities of ULINKpro delivers sophisticated analysis features such as:
Complete Code Coverage information about your program's execution ensures thorough application testing and verification
Performance Analysis using the Execution Profiler and Performance Analyzer enable you to identify program bottlenecks, optimize your application, and to isolate problems
Streaming instruction trace requires the target device to have ETM (Embedded Trace Macrocell)
www.element14.com
www.farnell.com
www.newark.com
Page <1>
V1.0
30/07/13
Raspberry PI Heat Sink Kit
The Farnell Raspberry PI heat sink kit will ensure your Raspberry PI remains cool with no need for Fans. They will also help extend the life of your Raspberry PI and thereby reduce hardware failures.
The heat sink kit comprises of 3 high quality Pressfin heat sinks which are designed to fit the 3 main heat sources on the Raspberry PI. Included in the kit is a 30mm × 30mm piece of thermal adhesive tape to securely fix the heat sinks in place and to ensure a good thermal transfer bond.
Dimensions : Millimetres
Important Notice : This data sheet and its contents (the “Information”) belong to the members of the Premier Farnell group of companies (the “Group”) or are licensed to it. No licence is granted for the use of it other than for information purposes in connection with the products to which it relates. No licence of any intellectual property rights is granted. The Information is subject to change without notice and replaces all data sheets previously supplied. The Information supplied is believed to be accurate but the Group assumes no responsibility for its accuracy or completeness, any error in or omission from it or for any use made of it. Users of this data sheet should check for themselves the Information and the suitability of the products for their purpose and not make any
assumptions based on information included or omitted. Liability for loss or damage resulting from any reliance on the Information or use of it (including liability resulting from negligence or where the Group was aware of the possibility of such loss or damage arising) is excluded. This will not operate to limit or restrict the Group’s liability for death or personal injury resulting from its negligence. Multicomp is the registered trademark of the Group. © Premier Farnell plc 2012.
Part Number Table
Description
Part Number
Raspberry PI Heat Sink Kit
2319947
Raspberry Pi Power Supply
UK version
Features:
Built specifically for use with Raspberry Pi
Class II design 5vdc 1A output via Micro USB
Energy efficienct to ErP stage 2
ĞƐĐƌŝƉƟŽŶ͗
This 5vdc 1A UK Micro USB power supply is manufactured specifically
for use with the Raspberry Pi device. It offers a highly efficient output
ŵĞĞƟŶŐ ůĂƚĞƐƚ ƌW ƐƚĂŐĞ Ϯ ƌĞƋƵŝƌĞŵĞŶƚƐ ĂŶĚ ŝƐ ƐĂĨĞƚLJ ĂƉƉƌŽǀ ĞĚ͘ dŚŝƐ
unit has a fixed UK pin and a 1.8 metre output cable and features
ƐŚŽƌƚ ĐŝƌĐƵŝƚ ĂŶĚ Žǀ Ğƌ ĐƵƌƌĞŶƚ ƉƌŽƚĞĐƟŽŶ ĂƐ ƐƚĂŶĚĂƌĚ͘ dŚŝƐ ZĂƐƉďĞƌƌLJ
Pi power supply has M.T.B.F of 50K hours at 25 degrees C.
Part Number PW03060
Output 5vdc 1A maximum
Current Min. 0.01A
WŽǁ Ğƌ ;ǁ ĂƩ ƐͿ 5W
Line Reg +/-5% at rated load
dŽƚĂů K ƵƚƉƵƚ ZĞŐƵůĂƟŽŶ +/-5 % at 0—100% load
Ripple & Noise (mV p-p) 200mV P-P
WƌŽƚĞĐƟŽŶƐ Over Current and Short Circuit
Case Size 54 x 50 x 42mm
Weight (approx.) 70g
DC Cord 1.8 Metres
DC Plug Micro USB
Rated Input Voltage 100-240Vac
Full Input Voltage Range 90-264Vac
Rated Frequency 50-60Hz
Full Frequency Range 47-63Hz
Efficiency 68.17%
Leakage Current shall not exceed 0.25mA
Input Power 7.72W max
Input Current (RMS Max.) 0.18A max
Hi-Pot Spec 3000Vac 10mA 1 min. (I.P. to O.P.)
E Ž ůŽĂĚ ƉŽǁ Ğƌ ĐŽŶƐƵŵƉƟŽŶ 0.3W max
K ƉĞƌĂƟŶŐ dĞŵƉĞƌĂƚƵƌĞ 0 to 40 degrees C
Storage Temperature -20 to 80 degrees C
K ƉĞƌĂƟŶŐ , ƵŵŝĚŝƚLJ 10% to 90%
Safety Approvals BS EN60950-1 / CE marked
EMC Standards EN55022:2006+A1:2007
/ EN6100-3-2 / EN6100-3-3
Pb-free Yes RoHS Compliant
MTBF 50K Hours at 25 degrees C
See mechanical drawing and DC cable drawing on page 2.
Full spec sheet on this PSU is available on request. Premier Farnell Ltd accepts
ŶŽ ƌĞƐƉŽŶƐŝďŝůŝƚLJ ĨŽƌ ƚLJƉŽŐƌĂƉŚŝĐĂů ĞƌƌŽƌƐ ŝŶ ƚŚĞ ƉƌŽĚƵĐƟŽŶ ŽĨ ƚŚŝƐ ůĞĂŇĞƚ͘
WƌŽĚƵĐƚ ƐƉĞĐŝĮ ĐĂƟŽŶƐ ĂƌĞ ƐƵďũĞĐƚ ƚŽ ĐŚĂŶŐĞ ǁ ŝƚŚŽƵƚ ŶŽƟĐĞ
Raspberry Pi Power Supply
UK version
Mechanical drawing:
Output connector
Keyboard, Mouse and Cable Bundles for the
Raspberry Pi
Kit Contents:
HDMI Bundle DVI Bundle
RPI-CABLE+ACC/HDMI RPI-CABLE+ACC/DVI
Mini QWERTY Keyboard
Optical USB Mouse
3.5mm Stereo Jack Plug Cable – 2m
Stereo Phono (RCA) to 3.5mm Stereo Jack Plug Cable – 1.8m
Cat5e Patch Cable, RJ45 Plug to RJ45 Plug – 3m
High Speed HDMI Cable – 2m HDMI to DVI Cable – 2m
LM3S6952 Microcontroller
DATA SHEET
DS-LM3S6952-1972 Copyright © 2007 Luminary Micro, Inc.
PRELIMINARY
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office
or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these
for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark
of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2 November 30, 2007
Preliminary
Table of Contents
About This Document .................................................................................................................... 20
Audience .............................................................................................................................................. 20
About This Manual ................................................................................................................................ 20
Related Documents ............................................................................................................................... 20
Documentation Conventions .................................................................................................................. 20
1 Architectural Overview ...................................................................................................... 22
1.1 Product Features ...................................................................................................................... 22
1.2 Target Applications .................................................................................................................... 28
1.3 High-Level Block Diagram ......................................................................................................... 29
1.4 Functional Overview .................................................................................................................. 29
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 30
1.4.2 Motor Control Peripherals .......................................................................................................... 30
1.4.3 Analog Peripherals .................................................................................................................... 31
1.4.4 Serial Communications Peripherals ............................................................................................ 32
1.4.5 System Peripherals ................................................................................................................... 33
1.4.6 Memory Peripherals .................................................................................................................. 34
1.4.7 Additional Features ................................................................................................................... 35
1.4.8 Hardware Details ...................................................................................................................... 35
2 ARM Cortex-M3 Processor Core ...................................................................................... 37
2.1 Block Diagram .......................................................................................................................... 38
2.2 Functional Description ............................................................................................................... 38
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 38
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 39
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 39
2.2.4 ROM Table ............................................................................................................................... 39
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 39
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 39
3 Memory Map ....................................................................................................................... 43
4 Interrupts ............................................................................................................................ 45
5 JTAG Interface .................................................................................................................... 48
5.1 Block Diagram .......................................................................................................................... 49
5.2 Functional Description ............................................................................................................... 49
5.2.1 JTAG Interface Pins .................................................................................................................. 50
5.2.2 JTAG TAP Controller ................................................................................................................. 51
5.2.3 Shift Registers .......................................................................................................................... 52
5.2.4 Operational Considerations ........................................................................................................ 52
5.3 Initialization and Configuration ................................................................................................... 55
5.4 Register Descriptions ................................................................................................................ 55
5.4.1 Instruction Register (IR) ............................................................................................................. 55
5.4.2 Data Registers .......................................................................................................................... 57
6 System Control ................................................................................................................... 59
6.1 Functional Description ............................................................................................................... 59
6.1.1 Device Identification .................................................................................................................. 59
6.1.2 Reset Control ............................................................................................................................ 59
November 30, 2007 3
Preliminary
LM3S6952 Microcontroller
6.1.3 Power Control ........................................................................................................................... 62
6.1.4 Clock Control ............................................................................................................................ 62
6.1.5 System Control ......................................................................................................................... 64
6.2 Initialization and Configuration ................................................................................................... 65
6.3 Register Map ............................................................................................................................ 65
6.4 Register Descriptions ................................................................................................................ 66
7 Hibernation Module .......................................................................................................... 120
7.1 Block Diagram ........................................................................................................................ 121
7.2 Functional Description ............................................................................................................. 121
7.2.1 Register Access Timing ........................................................................................................... 121
7.2.2 Clock Source .......................................................................................................................... 122
7.2.3 Battery Management ............................................................................................................... 122
7.2.4 Real-Time Clock ...................................................................................................................... 122
7.2.5 Non-Volatile Memory ............................................................................................................... 123
7.2.6 Power Control ......................................................................................................................... 123
7.2.7 Interrupts and Status ............................................................................................................... 123
7.3 Initialization and Configuration ................................................................................................. 124
7.3.1 Initialization ............................................................................................................................. 124
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 124
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 124
7.3.4 External Wake-Up from Hibernation .......................................................................................... 125
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 125
7.4 Register Map .......................................................................................................................... 125
7.5 Register Descriptions .............................................................................................................. 126
8 Internal Memory ............................................................................................................... 139
8.1 Block Diagram ........................................................................................................................ 139
8.2 Functional Description ............................................................................................................. 139
8.2.1 SRAM Memory ........................................................................................................................ 139
8.2.2 Flash Memory ......................................................................................................................... 140
8.3 Flash Memory Initialization and Configuration ........................................................................... 141
8.3.1 Flash Programming ................................................................................................................. 141
8.3.2 Nonvolatile Register Programming ........................................................................................... 142
8.4 Register Map .......................................................................................................................... 142
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 143
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 150
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 163
9.1 Functional Description ............................................................................................................. 163
9.1.1 Data Control ........................................................................................................................... 164
9.1.2 Interrupt Control ...................................................................................................................... 165
9.1.3 Mode Control .......................................................................................................................... 166
9.1.4 Commit Control ....................................................................................................................... 166
9.1.5 Pad Control ............................................................................................................................. 166
9.1.6 Identification ........................................................................................................................... 166
9.2 Initialization and Configuration ................................................................................................. 166
9.3 Register Map .......................................................................................................................... 168
9.4 Register Descriptions .............................................................................................................. 169
4 November 30, 2007
Preliminary
Table of Contents
10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 205
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Test Modes ............................................................................................................................. 266
12.2.6 Internal Temperature Sensor .................................................................................................... 266
12.3 Initialization and Configuration ................................................................................................. 267
12.3.1 Module Initialization ................................................................................................................. 267
12.3.2 Sample Sequencer Configuration ............................................................................................. 267
12.4 Register Map .......................................................................................................................... 268
12.5 Register Descriptions .............................................................................................................. 269
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
13.4 Register Map .......................................................................................................................... 302
November 30, 2007 5
Preliminary
LM3S6952 Microcontroller
13.5 Register Descriptions .............................................................................................................. 303
14 Synchronous Serial Interface (SSI) ................................................................................ 337
14.1 Block Diagram ........................................................................................................................ 337
14.2 Functional Description ............................................................................................................. 337
14.2.1 Bit Rate Generation ................................................................................................................. 338
14.2.2 FIFO Operation ....................................................................................................................... 338
14.2.3 Interrupts ................................................................................................................................ 338
14.2.4 Frame Formats ....................................................................................................................... 339
14.3 Initialization and Configuration ................................................................................................. 346
14.4 Register Map .......................................................................................................................... 347
14.5 Register Descriptions .............................................................................................................. 348
15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374
15.1 Block Diagram ........................................................................................................................ 374
15.2 Functional Description ............................................................................................................. 374
15.2.1 I2C Bus Functional Overview .................................................................................................... 375
15.2.2 Available Speed Modes ........................................................................................................... 377
15.2.3 Interrupts ................................................................................................................................ 378
15.2.4 Loopback Operation ................................................................................................................ 378
15.2.5 Command Sequence Flow Charts ............................................................................................ 379
15.3 Initialization and Configuration ................................................................................................. 385
15.4 I2C Register Map ..................................................................................................................... 386
15.5 Register Descriptions (I2C Master) ........................................................................................... 387
15.6 Register Descriptions (I2C Slave) ............................................................................................. 400
16 Ethernet Controller .......................................................................................................... 409
16.1 Block Diagram ........................................................................................................................ 410
16.2 Functional Description ............................................................................................................. 410
16.2.1 Internal MII Operation .............................................................................................................. 410
16.2.2 PHY Configuration/Operation ................................................................................................... 411
16.2.3 MAC Configuration/Operation .................................................................................................. 412
16.2.4 Interrupts ................................................................................................................................ 414
16.3 Initialization and Configuration ................................................................................................. 415
16.4 Ethernet Register Map ............................................................................................................. 415
16.5 Ethernet MAC Register Descriptions ......................................................................................... 417
16.6 MII Management Register Descriptions ..................................................................................... 434
17 Analog Comparators ....................................................................................................... 453
17.1 Block Diagram ........................................................................................................................ 454
17.2 Functional Description ............................................................................................................. 454
17.2.1 Internal Reference Programming .............................................................................................. 456
17.3 Initialization and Configuration ................................................................................................. 457
17.4 Register Map .......................................................................................................................... 457
17.5 Register Descriptions .............................................................................................................. 458
18 Pulse Width Modulator (PWM) ........................................................................................ 466
18.1 Block Diagram ........................................................................................................................ 466
18.2 Functional Description ............................................................................................................. 466
18.2.1 PWM Timer ............................................................................................................................. 466
18.2.2 PWM Comparators .................................................................................................................. 467
18.2.3 PWM Signal Generator ............................................................................................................ 468
6 November 30, 2007
Preliminary
Table of Contents
18.2.4 Dead-Band Generator ............................................................................................................. 469
18.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 469
18.2.6 Synchronization Methods ......................................................................................................... 469
18.2.7 Fault Conditions ...................................................................................................................... 470
18.2.8 Output Control Block ............................................................................................................... 470
18.3 Initialization and Configuration ................................................................................................. 470
18.4 Register Map .......................................................................................................................... 471
18.5 Register Descriptions .............................................................................................................. 472
19 Quadrature Encoder Interface (QEI) ............................................................................... 501
19.1 Block Diagram ........................................................................................................................ 501
19.2 Functional Description ............................................................................................................. 502
19.3 Initialization and Configuration ................................................................................................. 504
19.4 Register Map .......................................................................................................................... 504
19.5 Register Descriptions .............................................................................................................. 505
20 Pin Diagram ...................................................................................................................... 518
21 Signal Tables .................................................................................................................... 519
22 Operating Characteristics ............................................................................................... 533
23 Electrical Characteristics ................................................................................................ 534
23.1 DC Characteristics .................................................................................................................. 534
23.1.1 Maximum Ratings ................................................................................................................... 534
23.1.2 Recommended DC Operating Conditions .................................................................................. 534
23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 535
23.1.4 Power Specifications ............................................................................................................... 535
23.1.5 Flash Memory Characteristics .................................................................................................. 537
23.2 AC Characteristics ................................................................................................................... 537
23.2.1 Load Conditions ...................................................................................................................... 537
23.2.2 Clocks .................................................................................................................................... 537
23.2.3 Analog-to-Digital Converter ...................................................................................................... 538
23.2.4 Analog Comparator ................................................................................................................. 539
23.2.5 I2C ......................................................................................................................................... 539
23.2.6 Ethernet Controller .................................................................................................................. 540
23.2.7 Hibernation Module ................................................................................................................. 543
23.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 543
23.2.9 JTAG and Boundary Scan ........................................................................................................ 545
23.2.10 General-Purpose I/O ............................................................................................................... 546
23.2.11 Reset ..................................................................................................................................... 547
24 Package Information ........................................................................................................ 549
A Serial Flash Loader .......................................................................................................... 551
A.1 Serial Flash Loader ................................................................................................................. 551
A.2 Interfaces ............................................................................................................................... 551
A.2.1 UART ..................................................................................................................................... 551
A.2.2 SSI ......................................................................................................................................... 551
A.3 Packet Handling ...................................................................................................................... 552
A.3.1 Packet Format ........................................................................................................................ 552
A.3.2 Sending Packets ..................................................................................................................... 552
A.3.3 Receiving Packets ................................................................................................................... 552
November 30, 2007 7
Preliminary
LM3S6952 Microcontroller
A.4 Commands ............................................................................................................................. 553
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 553
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 553
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 553
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 554
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 554
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 554
B Register Quick Reference ............................................................................................... 556
C Ordering and Contact Information ................................................................................. 575
C.1 Ordering Information ................................................................................................................ 575
C.2 Kits ......................................................................................................................................... 575
C.3 Company Information .............................................................................................................. 575
C.4 Support Information ................................................................................................................. 576
8 November 30, 2007
Preliminary
Table of Contents
List of Figures
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 29
Figure 2-1. CPU Block Diagram ......................................................................................................... 38
Figure 2-2. TPIU Block Diagram ........................................................................................................ 39
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 49
Figure 5-2. Test Access Port State Machine ....................................................................................... 52
Figure 5-3. IDCODE Register Format ................................................................................................. 57
Figure 5-4. BYPASS Register Format ................................................................................................ 58
Figure 5-5. Boundary Scan Register Format ....................................................................................... 58
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 60
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 121
Figure 8-1. Flash Block Diagram ...................................................................................................... 139
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 164
Figure 9-2. GPIODATA Write Example ............................................................................................. 165
Figure 9-3. GPIODATA Read Example ............................................................................................. 165
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211
Figure 11-1. WDT Module Block Diagram .......................................................................................... 240
Figure 12-1. ADC Module Block Diagram ........................................................................................... 264
Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 267
Figure 13-1. UART Module Block Diagram ......................................................................................... 297
Figure 13-2. UART Character Frame ................................................................................................. 298
Figure 13-3. IrDA Data Modulation ..................................................................................................... 300
Figure 14-1. SSI Module Block Diagram ............................................................................................. 337
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346
Figure 15-1. I2C Block Diagram ......................................................................................................... 374
Figure 15-2. I2C Bus Configuration .................................................................................................... 375
Figure 15-3. START and STOP Conditions ......................................................................................... 375
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376
Figure 15-7. Master Single SEND ...................................................................................................... 379
Figure 15-8. Master Single RECEIVE ................................................................................................. 380
Figure 15-9. Master Burst SEND ....................................................................................................... 381
November 30, 2007 9
Preliminary
LM3S6952 Microcontroller
Figure 15-10. Master Burst RECEIVE .................................................................................................. 382
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384
Figure 15-13. Slave Command Sequence ............................................................................................ 385
Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410
Figure 16-2. Ethernet Controller ......................................................................................................... 410
Figure 16-3. Ethernet Frame ............................................................................................................. 412
Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 454
Figure 17-2. Structure of Comparator Unit .......................................................................................... 455
Figure 17-3. Comparator Internal Reference Structure ........................................................................ 456
Figure 18-1. PWM Module Block Diagram .......................................................................................... 466
Figure 18-2. PWM Count-Down Mode ................................................................................................ 467
Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 468
Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 468
Figure 18-5. PWM Dead-Band Generator ........................................................................................... 469
Figure 19-1. QEI Block Diagram ........................................................................................................ 501
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503
Figure 20-1. Pin Connection Diagram ................................................................................................ 518
Figure 23-1. Load Conditions ............................................................................................................ 537
Figure 23-2. I2C Timing ..................................................................................................................... 540
Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 542
Figure 23-4. Hibernation Module Timing ............................................................................................. 543
Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 544
Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 544
Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 545
Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 546
Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 546
Figure 23-10. JTAG TRST Timing ........................................................................................................ 546
Figure 23-11. External Reset Timing (RST) .......................................................................................... 547
Figure 23-12. Power-On Reset Timing ................................................................................................. 548
Figure 23-13. Brown-Out Reset Timing ................................................................................................ 548
Figure 23-14. Software Reset Timing ................................................................................................... 548
Figure 23-15. Watchdog Reset Timing ................................................................................................. 548
Figure 24-1. 100-Pin LQFP Package .................................................................................................. 549
10 November 30, 2007
Preliminary
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 20
Table 3-1. Memory Map ................................................................................................................... 43
Table 4-1. Exception Types .............................................................................................................. 45
Table 4-2. Interrupts ........................................................................................................................ 46
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 50
Table 5-2. JTAG Instruction Register Commands ............................................................................... 55
Table 6-1. System Control Register Map ........................................................................................... 65
Table 7-1. Hibernation Module Register Map ................................................................................... 125
Table 8-1. Flash Protection Policy Combinations ............................................................................. 141
Table 8-2. Flash Resident Registers ............................................................................................... 142
Table 8-3. Flash Register Map ........................................................................................................ 142
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 167
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 167
Table 9-3. GPIO Register Map ....................................................................................................... 168
Table 10-1. Available CCP Pins ........................................................................................................ 205
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208
Table 10-3. Timers Register Map ...................................................................................................... 214
Table 11-1. Watchdog Timer Register Map ........................................................................................ 241
Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264
Table 12-2. ADC Register Map ......................................................................................................... 268
Table 13-1. UART Register Map ....................................................................................................... 302
Table 14-1. SSI Register Map .......................................................................................................... 347
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
Table 16-1. TX & RX FIFO Organization ........................................................................................... 413
Table 16-2. Ethernet Register Map ................................................................................................... 416
Table 17-1. Comparator 0 Operating Modes ..................................................................................... 455
Table 17-2. Comparator 1 Operating Modes ..................................................................................... 455
Table 17-3. Comparator 2 Operating Modes ...................................................................................... 456
Table 17-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 456
Table 17-5. Analog Comparators Register Map ................................................................................. 458
Table 18-1. PWM Register Map ........................................................................................................ 471
Table 19-1. QEI Register Map .......................................................................................................... 504
Table 21-1. Signals by Pin Number ................................................................................................... 519
Table 21-2. Signals by Signal Name ................................................................................................. 523
Table 21-3. Signals by Function, Except for GPIO ............................................................................. 527
Table 21-4. GPIO Pins and Alternate Functions ................................................................................. 531
Table 22-1. Temperature Characteristics ........................................................................................... 533
Table 22-2. Thermal Characteristics ................................................................................................. 533
Table 23-1. Maximum Ratings .......................................................................................................... 534
Table 23-2. Recommended DC Operating Conditions ........................................................................ 534
Table 23-3. LDO Regulator Characteristics ....................................................................................... 535
Table 23-4. Detailed Power Specifications ........................................................................................ 536
Table 23-5. Flash Memory Characteristics ........................................................................................ 537
Table 23-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 537
November 30, 2007 11
Preliminary
LM3S6952 Microcontroller
Table 23-7. Clock Characteristics ..................................................................................................... 537
Table 23-8. Crystal Characteristics ................................................................................................... 538
Table 23-9. ADC Characteristics ....................................................................................................... 538
Table 23-10. Analog Comparator Characteristics ................................................................................. 539
Table 23-11. Analog Comparator Voltage Reference Characteristics .................................................... 539
Table 23-12. I2C Characteristics ......................................................................................................... 539
Table 23-13. 100BASE-TX Transmitter Characteristics ........................................................................ 540
Table 23-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 540
Table 23-15. 100BASE-TX Receiver Characteristics ............................................................................ 540
Table 23-16. 10BASE-T Transmitter Characteristics ............................................................................ 540
Table 23-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 541
Table 23-18. 10BASE-T Receiver Characteristics ................................................................................ 541
Table 23-19. Isolation Transformers ................................................................................................... 541
Table 23-20. Ethernet Reference Crystal ............................................................................................ 542
Table 23-21. External XTLP Oscillator Characteristics ......................................................................... 542
Table 23-22. Hibernation Module Characteristics ................................................................................. 543
Table 23-23. SSI Characteristics ........................................................................................................ 543
Table 23-24. JTAG Characteristics ..................................................................................................... 545
Table 23-25. GPIO Characteristics ..................................................................................................... 547
Table 23-26. Reset Characteristics ..................................................................................................... 547
Table C-1. Part Ordering Information ............................................................................................... 575
12 November 30, 2007
Preliminary
Table of Contents
List of Registers
System Control .............................................................................................................................. 59
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 67
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 69
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 70
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 71
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 72
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 73
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 74
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 75
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 79
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 80
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 82
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 83
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 85
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 86
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 88
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 90
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 96
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 98
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 103
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 106
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 109
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 111
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 113
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 115
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 116
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 118
Hibernation Module ..................................................................................................................... 120
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 127
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 128
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 129
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 130
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 131
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 133
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 134
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 135
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 136
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 137
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 138
Internal Memory ........................................................................................................................... 139
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 144
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 145
November 30, 2007 13
Preliminary
LM3S6952 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 146
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 148
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 149
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 150
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 151
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 152
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 153
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 154
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 155
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 156
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 157
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 158
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 159
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 160
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 161
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 162
General-Purpose Input/Outputs (GPIOs) ................................................................................... 163
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202
14 November 30, 2007
Preliminary
Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203
General-Purpose Timers ............................................................................................................. 204
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239
Watchdog Timer ........................................................................................................................... 240
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262
Analog-to-Digital Converter (ADC) ............................................................................................. 263
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 270
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 271
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 272
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 273
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 274
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 275
November 30, 2007 15
Preliminary
LM3S6952 Microcontroller
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 278
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 279
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 280
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 281
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 282
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 284
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 287
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 287
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 287
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 287
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 288
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 288
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 288
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 288
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 289
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 289
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 290
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 290
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 292
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 293
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 294
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336
16 November 30, 2007
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Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 337
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408
Ethernet Controller ...................................................................................................................... 409
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 418
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 420
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 421
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 422
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 423
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 424
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 426
November 30, 2007 17
Preliminary
LM3S6952 Microcontroller
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 427
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 428
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 429
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 430
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 431
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 432
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 433
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 434
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 435
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 437
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 439
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 440
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 441
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 443
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 444
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 445
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 447
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 449
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 450
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 451
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 452
Analog Comparators ................................................................................................................... 453
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 459
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 460
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 461
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 462
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 463
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 463
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 463
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 464
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 464
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 464
Pulse Width Modulator (PWM) .................................................................................................... 466
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 473
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 474
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 475
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 476
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 477
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 478
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 479
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 480
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 481
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 482
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 482
18 November 30, 2007
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Table of Contents
Register 12: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 484
Register 13: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 484
Register 14: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 486
Register 15: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 486
Register 16: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 487
Register 17: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 487
Register 18: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 488
Register 19: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 488
Register 20: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 489
Register 21: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 489
Register 22: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 490
Register 23: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 490
Register 24: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 491
Register 25: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 491
Register 26: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 492
Register 27: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 492
Register 28: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 495
Register 29: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 495
Register 30: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 498
Register 31: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 498
Register 32: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 499
Register 33: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 499
Register 34: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 500
Register 35: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 500
Quadrature Encoder Interface (QEI) .......................................................................................... 501
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 506
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 508
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 509
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 510
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 511
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 512
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 513
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 514
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 515
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 516
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 517
November 30, 2007 19
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LM3S6952 Microcontroller
About This Document
This data sheet provides reference information for the LM3S6952 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 20.
Table 1. Documentation Conventions
Notation Meaning
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
bit A single bit in a register.
bit field Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 43.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
20 November 30, 2007
Preliminary
About This Document
Notation Meaning
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
deassert a signal Change the value of the signal from the logically True state to the logically False state.
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
November 30, 2007 21
Preliminary
LM3S6952 Microcontroller
1 Architectural Overview
The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris® family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris®
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris® LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris® LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris® LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
The LM3S6952 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S6952 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S6952 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S6952 microcontroller perfectly for
battery applications.
In addition, the LM3S6952 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6952 microcontroller is code-compatible
to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S6952 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
22 November 30, 2007
Preliminary
Architectural Overview
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 34 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
November 30, 2007 23
Preliminary
LM3S6952 Microcontroller
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
24 November 30, 2007
Preliminary
Architectural Overview
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Three 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 500 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Three independent integrated analog comparators
November 30, 2007 25
Preliminary
LM3S6952 Microcontroller
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– Two PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
26 November 30, 2007
Preliminary
Architectural Overview
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 6-43 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
November 30, 2007 27
Preliminary
LM3S6952 Microcontroller
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
28 November 30, 2007
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Architectural Overview
1.3 High-Level Block Diagram
Figure 1-1 on page 29 represents the full set of features in the Stellaris® 6000 series of devices;
not all features may be available on the LM3S6952 microcontroller.
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6952 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 575.
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LM3S6952 Microcontroller
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 37)
All members of the Stellaris® product family, including the LM3S6952 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 37 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S6952 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 34 interrupts.
“Interrupts” on page 45 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6952 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
30 November 30, 2007
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Architectural Overview
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S6952, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 466)
The LM3S6952 PWM module consists of two PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 210)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.2.2 QEI (see page 501)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S6952 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S6952 microcontroller offers three analog comparators.
1.4.3.1 ADC (see page 263)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S6952 ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 453)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
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LM3S6952 Microcontroller
The LM3S6952 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S6952 controller supports both asynchronous and synchronous serial communications
with:
■ Three fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
■ Ethernet controller
1.4.4.1 UART (see page 296)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S6952 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 337)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S6952 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
32 November 30, 2007
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The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 374)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S6952 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Ethernet Controller (see page 409)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 163)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris® GPIO module is composed of seven physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 6-43 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
519 for the signals available to each GPIO pin).
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The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Three Programmable Timers (see page 204)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 240)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S6952 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 139)
The LM3S6952 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 140)
The LM3S6952 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
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1.4.7 Additional Features
1.4.7.1 Memory Map (see page 43)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S6952 controller can be found in “Memory Map” on page 43. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 48)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 59)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.4 Hibernation Module (see page 120)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 518
■ “Signal Tables” on page 519
■ “Operating Characteristics” on page 533
■ “Electrical Characteristics” on page 534
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■ “Package Information” on page 549
36 November 30, 2007
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2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
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LM3S6952 Microcontroller
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris® implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 38. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
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2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 39.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S6952 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
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The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
All NVIC registers and system debug registers are little endian regardless of the endianness state
of the processor.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S6952 microcontroller supports 34 interrupts with eight priority
levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
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Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:17 reserved RO 0
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
16 COUNTFLAG R/W 0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
15:3 reserved RO 0
0 = external reference clock. (Not implemented for Stellaris microcontrollers.)
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
2 CLKSOURCE R/W 0
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler. Software can use the
COUNTFLAG to determine if ever counted to 0.
1 TICKINT R/W 0
1 = counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the COUNTFLAG to
1 and optionally pends the SysTick handler, based on TICKINT. It then loads the
Reload value again, and begins counting.
0 = counter disabled.
0 ENABLE R/W 0
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
31:24 reserved RO 0
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LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
23:0 RELOAD W1C - Value to load into the SysTick Current Value Register when the counter reaches 0.
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:24 reserved RO 0
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
23:0 CURRENT W1C -
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
42 November 30, 2007
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3 Memory Map
The memory map for the LM3S6952 controller is provided in Table 3-1 on page 43.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 43, addresses not listed are reserved.
Table 3-1. Memory Mapa
For details on
registers, see
page ...
Start End Description
Memory
0x0000.0000 0x0003.FFFF On-chip flash b 143
0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAMc 143
0x2010.0000 0x21FF.FFFF Reserved non-bit-banded SRAM space -
0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 139
0x2400.0000 0x3FFF.FFFF Reserved non-bit-banded SRAM space -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 242
0x4000.4000 0x4000.4FFF GPIO Port A 169
0x4000.5000 0x4000.5FFF GPIO Port B 169
0x4000.6000 0x4000.6FFF GPIO Port C 169
0x4000.7000 0x4000.7FFF GPIO Port D 169
0x4000.8000 0x4000.8FFF SSI0 348
0x4000.C000 0x4000.CFFF UART0 303
0x4000.D000 0x4000.DFFF UART1 303
0x4000.E000 0x4000.EFFF UART2 303
Peripherals
0x4002.0000 0x4002.07FF I2C Master 0 387
0x4002.0800 0x4002.0FFF I2C Slave 0 400
0x4002.4000 0x4002.4FFF GPIO Port E 169
0x4002.5000 0x4002.5FFF GPIO Port F 169
0x4002.6000 0x4002.6FFF GPIO Port G 169
0x4002.8000 0x4002.8FFF PWM 472
0x4002.C000 0x4002.CFFF QEI0 505
0x4003.0000 0x4003.0FFF Timer0 215
0x4003.1000 0x4003.1FFF Timer1 215
0x4003.2000 0x4003.2FFF Timer2 215
0x4003.8000 0x4003.8FFF ADC 269
0x4003.C000 0x4003.CFFF Analog Comparators 453
0x4004.8000 0x4004.8FFF Ethernet Controller 417
0x400F.C000 0x400F.CFFF Hibernation Module 126
November 30, 2007 43
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LM3S6952 Microcontroller
For details on
registers, see
page ...
Start End Description
0x400F.D000 0x400F.DFFF Flash control 143
0x400F.E000 0x400F.EFFF System control 66
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
Private Peripheral Bus
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM)
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT)
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB)
0xE000.3000 0xE000.DFFF Reserved
0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC)
0xE000.F000 0xE003.FFFF Reserved
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU)
0xE004.1000 0xE004.1FFF Reserved -
0xE004.2000 0xE00F.FFFF Reserved -
0xE010.0000 0xFFFF.FFFF Reserved for vendor peripherals -
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
44 November 30, 2007
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Memory Map
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 45 lists all the exceptions. Software can set eight priority levels on seven of these
exceptions (system handlers) as well as on 34 interrupts (listed in Table 4-2 on page 46).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower the
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Note: In Table 4-2 on page 46 interrupts not listed are reserved.
Table 4-1. Exception Types
Exception Type Position Prioritya Description
- 0 - Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
Reset 1 -3 (highest)
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
Non-Maskable 2 -2
Interrupt (NMI)
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
Hard Fault 3 -1
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
Memory Management 4 settable
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Bus Fault 5 settable
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Usage Fault 6 settable
- 7-10 - Reserved.
SVCall 11 settable System service call with SVC instruction. This is synchronous.
November 30, 2007 45
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LM3S6952 Microcontroller
Exception Type Position Prioritya Description
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Debug Monitor 12 settable
- 13 - Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
PendSV 14 settable
SysTick 15 settable System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the NVIC
(prioritized). These are all asynchronous. Table 4-2 on page 46 lists the
interrupts on the LM3S6952 controller.
16 and settable
above
Interrupts
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt (Bit in Interrupt Registers) Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3 GPIO Port D
4 GPIO Port E
5 UART0
6 UART1
7 SSI0
8 I2C0
9 PWM Fault
10 PWM Generator 0
11 PWM Generator 1
13 QEI0
14 ADC Sequence 0
15 ADC Sequence 1
16 ADC Sequence 2
17 ADC Sequence 3
18 Watchdog timer
19 Timer0 A
20 Timer0 B
21 Timer1 A
22 Timer1 B
23 Timer2 A
24 Timer2 B
25 Analog Comparator 0
26 Analog Comparator 1
27 Analog Comparator 2
28 System Control
29 Flash Control
30 GPIO Port F
46 November 30, 2007
Preliminary
Interrupts
Interrupt (Bit in Interrupt Registers) Description
31 GPIO Port G
33 UART2
42 Ethernet Controller
43 Hibernation Module
November 30, 2007 47
Preliminary
LM3S6952 Microcontroller
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions:
– BYPASS instruction
– IDCODE instruction
– SAMPLE/PRELOAD instruction
– EXTEST instruction
– INTEST instruction
■ ARM additional instructions:
– APACC instruction
– DPACC instruction
– ABORT instruction
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
48 November 30, 2007
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JTAG Interface
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TRST
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 49. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 55 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 545 for JTAG timing diagrams.
November 30, 2007 49
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5.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 50. Detailed information on each pin
follows.
Table 5-1. JTAG Port Pins Reset State
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
5.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 52.
50 November 30, 2007
Preliminary
JTAG Interface
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 52. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
November 30, 2007 51
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LM3S6952 Microcontroller
Figure 5-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 0 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 55.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
52 November 30, 2007
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JTAG Interface
5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Recovering a "Locked" Device
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
11. Perform the SWD-to-JTAG switch sequence.
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LM3S6952 Microcontroller
12. Release the RST signal.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 54. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
54 November 30, 2007
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JTAG Interface
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 55. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
0000 EXTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
0001 INTEST
Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
0010 SAMPLE / PRELOAD
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
1110 IDCODE
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
November 30, 2007 55
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LM3S6952 Microcontroller
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 58 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 58 for more
information.
5.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 58 for more information.
5.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 58 for more information.
56 November 30, 2007
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5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 57 for more
information.
5.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 57 for
more information.
5.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 57. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
5.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 58. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
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LM3S6952 Microcontroller
Figure 5-4. BYPASS Register Format
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 58. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
O TDO TDI O IN
E UT
O O IN
U E
T
O O IN
E UT
O O IN
U E
T
I
N ... ...
GPIO PB6 GPIO m RST GPIO m+1 GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 59
■ Local control, such as reset (see “Reset Control” on page 59), power (see “Power
Control” on page 62) and clock control (see “Clock Control” on page 62)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 64
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 59.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 60.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 60.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 61.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 61.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 48). The external reset sequence is as
follows:
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1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 23-11 on page 547.
6.1.2.4 Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 60.
Figure 6-1. External Circuitry to Extend Reset
R1
C1
R2
RST
Stellaris
D1
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 23-12 on page 548.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
6.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
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Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 23-13 on page 548.
6.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 64). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 23-14 on page 548.
6.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 23-15 on page 548.
6.1.3 Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two
means: an external single-ended clock source is connected to the OSC0 input pin, or an external
crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed
depends on whether the main oscillator is used as the clock reference source to the PLL. If so,
the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192
MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit in
the RCC register (see page 75).
■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 120) and may
also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (sysclk), is derived from any of the four sources plus two others: the output
of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the
PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
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The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 75) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.3 PLL Frequency Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software configures the PLL input reference clock source, specifies the output divisor to set the
system clock frequency, and enables the PLL to drive the output.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG)
register (see page 79). The internal translation provides a translation within ± 1% of the targeted
PLL VCO frequency.
The Crystal Value field (XTAL) on page 75 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.4.4 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 75 and page 80).
6.1.4.5 PLL Operation
If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
23-6 on page 537). During this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
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LM3S6952 Microcontroller
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
6.1.5 System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
64 November 30, 2007
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System Control
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 65 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
Offset Name Type Reset Description page
0x000 DID0 RO - Device Identification 0 67
0x004 DID1 RO - Device Identification 1 83
0x008 DC0 RO 0x00FF.007F Device Capabilities 0 85
0x010 DC1 RO 0x0011.32FF Device Capabilities 1 86
0x014 DC2 RO 0x0707.1117 Device Capabilities 2 88
0x018 DC3 RO 0x0F07.BFCF Device Capabilities 3 90
0x01C DC4 RO 0x5000.007F Device Capabilities 4 92
0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 69
0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 70
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LM3S6952 Microcontroller
See
Offset Name Type Reset Description page
0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 115
0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 116
0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 118
0x050 RIS RO 0x0000.0000 Raw Interrupt Status 71
0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 72
0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 73
0x05C RESC R/W - Reset Cause 74
0x060 RCC R/W 0x07AE.3AD1 Run-Mode Clock Configuration 75
0x064 PLLCFG RO - XTAL to PLL Translation 79
0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 80
0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 94
0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 100
0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 109
0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 96
0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 103
0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 111
0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 98
0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 106
0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 113
0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 82
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved VER reserved CLASS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
First revision of the DID0 register format, for Stellaris®
Fury-class devices .
0x1
30:28 VER RO 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:24 reserved RO 0x0
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x0 Stellaris® Sandstorm-class devices.
0x1 Stellaris® Fury-class devices.
23:16 CLASS RO 0x1
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Bit/Field Name Type Reset Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
15:8 MAJOR RO -
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
7:0 MINOR RO -
68 November 30, 2007
Preliminary
System Control
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BORIOR reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1 BORIOR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
November 30, 2007 69
Preliminary
LM3S6952 Microcontroller
Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VADJ
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value VOUT (V)
0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55
5:0 VADJ R/W 0x0
70 November 30, 2007
Preliminary
System Control
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLRIS reserved BORRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
6 PLLLRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
1 BORRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
November 30, 2007 71
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LM3S6952 Microcontroller
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLIM reserved BORIM reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
6 PLLLIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
1 BORIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
72 November 30, 2007
Preliminary
System Control
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 71).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLMIS reserved BORMIS reserved
Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
6 PLLLMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
1 BORMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
November 30, 2007 73
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LM3S6952 Microcontroller
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LDO SW WDT BOR POR EXT
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
5 LDO R/W -
Software Reset
When set, indicates a software reset is the cause of the reset event.
4 SW R/W -
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
3 WDT R/W -
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
2 BOR R/W -
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
1 POR R/W -
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
0 EXT R/W -
74 November 30, 2007
Preliminary
System Control
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x07AE.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved
Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS
Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0x0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
27 ACG R/W 0
November 30, 2007 75
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LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0x0 reserved reserved
0x1 /2 reserved
0x2 /3 reserved
0x3 /4 50 MHz
0x4 /5 40 MHz
0x5 /6 33.33 MHz
0x6 /7 28.57 MHz
0x7 /8 25 MHz
0x8 /9 22.22 MHz
0x9 /10 20 MHz
0xA /11 18.18 MHz
0xB /12 16.67 MHz
0xC /13 15.38 MHz
0xD /14 14.29 MHz
0xE /15 13.33 MHz
0xF /16 12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 75), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
26:23 SYSDIV R/W 0xF
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
22 USESYSDIV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21 reserved RO 0
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
20 USEPWMDIV R/W 0
76 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
19:17 PWMDIV R/W 0x7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16:14 reserved RO 0
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
13 PWRDN R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note: The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
11 BYPASS R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10 reserved RO 0
November 30, 2007 77
Preliminary
LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Crystal Frequency (MHz)
Using the PLL
Crystal Frequency (MHz)
Not Using the PLL
Value
0x0 1.000 reserved
0x1 1.8432 reserved
0x2 2.000 reserved
0x3 2.4576 reserved
0x4 3.579545 MHz
0x5 3.6864 MHz
0x6 4 MHz
0x7 4.096 MHz
0x8 4.9152 MHz
0x9 5 MHz
0xA 5.12 MHz
0xB 6 MHz (reset value)
0xC 6.144 MHz
0xD 7.3728 MHz
0xE 8 MHz
0xF 8.192 MHz
9:6 XTAL R/W 0xB
Oscillator Source
Picks among the four input sources for the OSC. The values are:
Value Input Source
0x0 Main oscillator (default)
0x1 Internal oscillator (default)
0x2 Internal oscillator / 4 (this is necessary if used as input to PLL)
0x3 reserved
5:4 OSCSRC R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
1 IOSCDIS R/W 0
Main Oscillator Disable
0: Main oscillator is enabled.
1: Main oscillator is disabled (default).
0 MOSCDIS R/W 1
78 November 30, 2007
Preliminary
System Control
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 75).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved F R
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0
PLL F Value
This field specifies the value supplied to the PLL’s F input.
13:5 F RO -
PLL R Value
This field specifies the value supplied to the PLL’s R input.
4:0 R RO -
November 30, 2007 79
Preliminary
LM3S6952 Microcontroller
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USERCC2 reserved SYSDIV2 reserved
Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved
Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Use RCC2
When set, overrides the RCC register fields.
31 USERCC2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:29 reserved RO 0x0
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
28:23 SYSDIV2 R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:14 reserved RO 0x0
Power-Down PLL
When set, powers down the PLL.
13 PWRDN2 R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
Bypass PLL
When set, bypasses the PLL for the clock source.
11 BYPASS2 R/W 1
80 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0x0
System Clock Source
Value Description
0x0 Main oscillator (MOSC)
0x1 Internal oscillator (IOSC)
0x2 Internal oscillator / 4
0x3 30 kHz internal oscillator
0x7 32 kHz external oscillator
6:4 OSCSRC2 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
November 30, 2007 81
Preliminary
LM3S6952 Microcontroller
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved DSDIVORIDE reserved
Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DSOSCSRC reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:29 reserved RO 0x0
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
28:23 DSDIVORIDE R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:7 reserved RO 0x0
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
Value Name Description
0x0 NOORIDE No override to the oscillator clock source is done
0x1 IOSC Use internal 12 MHz oscillator as source
0x3 30kHz Use 30 kHz internal oscillator
0x7 32kHz Use 32 kHz external oscillator
6:4 DSOSCSRC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x0
82 November 30, 2007
Preliminary
System Control
Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VER FAM PARTNO
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOUNT reserved TEMP PKG ROHS QUAL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 1 0 1 1 - -
Bit/Field Name Type Reset Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
First revision of the DID1 register format, indicating a Stellaris
Fury-class device.
0x1
31:28 VER RO 0x1
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
27:24 FAM RO 0x0
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x78 LM3S6952
23:16 PARTNO RO 0x78
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2 100-pin package
15:13 PINCOUNT RO 0x2
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LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x1 Industrial temperature range (-40°C to 85°C)
7:5 TEMP RO 0x1
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
0x1 LQFP package
4:3 PKG RO 0x1
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
2 ROHS RO 1
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified
1:0 QUAL RO -
84 November 30, 2007
Preliminary
System Control
Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAMSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASHSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value Description
0x00FF 64 KB of SRAM
31:16 SRAMSZ RO 0x00FF
Flash Size
Indicates the size of the on-chip flash memory.
Value Description
0x007F 256 KB of Flash
15:0 FLASHSZ RO 0x007F
November 30, 2007 85
Preliminary
LM3S6952 Microcontroller
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0011.32FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Module Present
When set, indicates that the PWM module is present.
20 PWM RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC Module Present
When set, indicates that the ADC module is present.
16 ADC RO 1
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
15:12 MINSYSDIV RO 0x3
Max ADC Speed
Indicates the maximum rate at which the ADC samples data.
Value Description
0x2 500K samples/second
11:8 MAXADCSPD RO 0x2
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Bit/Field Name Type Reset Description
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
7 MPU RO 1
Hibernation Module Present
When set, indicates that the Hibernation module is present.
6 HIB RO 1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
5 TEMPSNS RO 1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
4 PLL RO 1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
3 WDT RO 1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
2 SWO RO 1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1 SWD RO 1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
0 JTAG RO 1
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Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x0707.1117
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
26 COMP2 RO 1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
25 COMP1 RO 1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
24 COMP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
18 TIMER2 RO 1
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
17 TIMER1 RO 1
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
16 TIMER0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
12 I2C0 RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Present
When set, indicates that QEI module 0 is present.
8 QEI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Present
When set, indicates that SSI module 0 is present.
4 SSI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Present
When set, indicates that UART module 2 is present.
2 UART2 RO 1
UART1 Present
When set, indicates that UART module 1 is present.
1 UART1 RO 1
UART0 Present
When set, indicates that UART module 0 is present.
0 UART0 RO 1
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Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x0F07.BFCF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CCP3 CCP2 CCP1 CCP0 reserved ADC2 ADC1 ADC0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT reserved C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved PWM3 PWM2 PWM1 PWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
27 CCP3 RO 1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
26 CCP2 RO 1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
25 CCP1 RO 1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
24 CCP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
ADC2 Pin Present
When set, indicates that ADC pin 2 is present.
18 ADC2 RO 1
ADC1 Pin Present
When set, indicates that ADC pin 1 is present.
17 ADC1 RO 1
ADC0 Pin Present
When set, indicates that ADC pin 0 is present.
16 ADC0 RO 1
PWM Fault Pin Present
When set, indicates that the PWM Fault pin is present.
15 PWMFAULT RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
13 C2PLUS RO 1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
12 C2MINUS RO 1
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
11 C1O RO 1
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
10 C1PLUS RO 1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
9 C1MINUS RO 1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
8 C0O RO 1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
7 C0PLUS RO 1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
6 C0MINUS RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
3 PWM3 RO 1
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
2 PWM2 RO 1
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
1 PWM1 RO 1
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
0 PWM0 RO 1
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Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
Ethernet PHY0 Present
When set, indicates that Ethernet PHY module 0 is present.
30 EPHY0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
Ethernet MAC0 Present
When set, indicates that Ethernet MAC module 0 is present.
28 EMAC0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
GPIO Port G Present
When set, indicates that GPIO Port G is present.
6 GPIOG RO 1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
5 GPIOF RO 1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
4 GPIOE RO 1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
3 GPIOD RO 1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
2 GPIOC RO 1
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Bit/Field Name Type Reset Description
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1 GPIOB RO 1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
0 GPIOA RO 1
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Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
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Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
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Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
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Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
100 November 30, 2007
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System Control
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
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Bit/Field Name Type Reset Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
102 November 30, 2007
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System Control
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
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Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
104 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
106 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
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Bit/Field Name Type Reset Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
108 November 30, 2007
Preliminary
System Control
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
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Bit/Field Name Type Reset Description
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
110 November 30, 2007
Preliminary
System Control
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
112 November 30, 2007
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System Control
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Reset Control
Reset control for PWM module.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Reset Control
Reset control for SAR ADC module 0.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:7 reserved RO 0
HIB Reset Control
Reset control for the Hibernation module.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Reset Control
Reset control for Watchdog unit.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comp 2 Reset Control
Reset control for analog comparator 2.
26 COMP2 R/W 0
Analog Comp 1 Reset Control
Reset control for analog comparator 1.
25 COMP1 R/W 0
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
18 TIMER2 R/W 0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
17 TIMER1 R/W 0
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Reset Control
Reset control for I2C unit 0.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
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Bit/Field Name Type Reset Description
QEI0 Reset Control
Reset control for QEI unit 0.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Reset Control
Reset control for SSI unit 0.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Reset Control
Reset control for UART unit 2.
2 UART2 R/W 0
UART1 Reset Control
Reset control for UART unit 1.
1 UART1 R/W 0
UART0 Reset Control
Reset control for UART unit 0.
0 UART0 R/W 0
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Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Reset Control
Reset control for Ethernet PHY unit 0.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Reset Control
Reset control for Ethernet MAC unit 0.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Reset Control
Reset control for GPIO Port G.
6 GPIOG R/W 0
Port F Reset Control
Reset control for GPIO Port F.
5 GPIOF R/W 0
Port E Reset Control
Reset control for GPIO Port E.
4 GPIOE R/W 0
Port D Reset Control
Reset control for GPIO Port D.
3 GPIOD R/W 0
Port C Reset Control
Reset control for GPIO Port C.
2 GPIOC R/W 0
Port B Reset Control
Reset control for GPIO Port B.
1 GPIOB R/W 0
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Bit/Field Name Type Reset Description
Port A Reset Control
Reset control for GPIO Port A.
0 GPIOA R/W 0
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7 Hibernation Module
The Hibernation Module manages removal and restoration of power to the rest of the microcontroller
to provide a means for reducing power consumption. When the processor and peripherals are idle,
power can be completely removed with only the Hibernation Module remaining powered. Power
can be restored based on an external signal, or at a certain time using the built-in real-time clock
(RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power
supply.
The Hibernation module has the following features:
■ Power-switching logic to discrete external regulator
■ Dedicated pin for waking from an external signal
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time counter (RTC)
■ Two 32-bit RTC match registers for timed wake-up and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
■ RTC predivider trim for making fine adjustments to the clock rate
■ 64 32-bit words of non-volatile memory
■ Programmable interrupts for RTC match, external wake, and low battery events
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7.1 Block Diagram
Figure 7-1. Hibernation Module Block Diagram
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
Pre-Divider
/128
XOSC0
XOSC1
HIBCTL.CLK32EN
HIBCTL.CLKSEL
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
RTC
Interrupts
Power
Sequence
Logic
MATCH0/1
WAKE
Interrupts
to CPU
Low Battery
Detect
LOWBAT
VDD
VBAT
HIB
HIBCTL.LOWBATEN HIBCTL.PWRCUT
HIBCTL.EXTWEN
HIBCTL.RTCWEN
HIBCTL.VABORT
Non-Volatile
Memory
HIBDATA
7.2 Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off. The Hibernation module power is determined dynamically.
The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the
battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power
switch selects the appropriate voltage source. The Hibernation module also has a separate clock
source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external
voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the
internal RTC reaches a certain value. The Hibernation module can also detect when the battery
voltage is low, and optionally prevent hibernation when this occurs.
Power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at
tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 543).
7.2.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
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restriction on timing for back-to-back reads from the Hibernation module. Refer to “Register
Descriptions” on page 126 for details about which registers are subject to this timing restriction.
7.2.2 Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature will not be
used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator
can be connected to the XOSC0 pin.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a
32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay
of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation
module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for
the clock source, no delay is needed.
7.2.3 Battery Management
The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage becomes too
low. When this happens, an interrupt can be generated. The module can also be configured so that
it will not go into Hibernate mode if the battery voltage is too low.
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD
is available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 123).
7.2.4 Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 122). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register. This register has a nominal value of 0x7FFF, and is
used for one second out of every 64 seconds to divide the input clock. This allows the software to
make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.
The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
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the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 123).
7.2.5 Non-Volatile Memory
The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The non-volatile memory can be accessed through the HIBDATA registers.
7.2.6 Power Control
The Hibernation module controls power to the processor through the use of the HIB pin, which is
intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or
2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external
regulator is turned off and no longer powers the microcontroller. The Hibernation module remains
powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation
mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing
this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC
match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can
detect that the power-on was due to a wake from hibernation by examining the raw interrupt status
register (see “Interrupts and Status” on page 123) and by looking for state data in the non-volatile
memory (see “Non-Volatile Memory” on page 123).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.
7.2.7 Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.
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7.3 Initialization and Configuration
The Hibernation module can be configured in several different combinations. The following sections
show the recommended programming sequence for various scenarios. The examples below assume
that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register
set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because
the Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must
allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 121). The registers that require a delay are denoted with a footnote in
Table 7-1 on page 125.
7.3.1 Initialization
The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal
is used, perform the following steps:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.
If a 32.678-kHz oscillator is used, then perform the following steps:
1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
2. No delay is necessary.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
7.3.2 RTC Match Functionality (No Hibernation)
The following steps are needed to use the RTC match functionality of the Hibernation module:
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
7.3.3 RTC Match/Wake-Up from Hibernation
The following steps are needed to use the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
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4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
7.3.4 External Wake-Up from Hibernation
The following steps are needed to use the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
7.3.5 RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
7.4 Register Map
Table 7-1 on page 125 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 121.
Table 7-1. Hibernation Module Register Map
See
Offset Name Type Reset Description page
0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 127
0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 128
0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 129
0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 130
0x010 HIBCTL R/W 0x0000.0000 Hibernation Control 131
0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 133
0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 134
0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 135
0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 136
0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 137
0x030- HIBDATA R/W 0x0000.0000 Hibernation Data 138
0x12C
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7.5 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
RTC Counter
A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.
31:0 RTCC RO 0x0000.0000
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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM0 R/W 0xFFFF.FFFF
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Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM1 R/W 0xFFFF.FFFF
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Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is the 32-bit value loaded into the RTC counter.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
31:0 RTCLD R/W 0xFFFF.FFFF
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Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Power Cut Abort Enable
0: Power cut occurs during a low-battery alert
1: Power cut is aborted
7 VABORT R/W 0
32-kHz Oscillator Enable
0: Disabled
1: Enabled
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
6 CLK32EN R/W 0
Low Battery Monitoring Enable
0: Disabled
1: Enabled
When set, low battery voltage detection is enabled.
5 LOWBATEN R/W 0
External WAKE Pin Enable
0: Disabled
1: Enabled
When set, an external event on the WAKE pin will re-power the device.
4 PINWEN R/W 0
RTC Wake-up Enable
0: Disabled
1: Enabled
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
3 RTCWEN R/W 0
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Bit/Field Name Type Reset Description
Hibernation Module Clock Select
0: Use Divide by 128 output. Use this value for a 4-MHz crystal.
1: Use raw output. Use this value for a 32-kHz oscillator.
2 CLKSEL R/W 0
Hibernation Request
0: Disabled
1: Hibernation initiated
After a wake-up event, this bit is cleared by hardware.
1 HIBREQ R/W 0
RTC Timer Enable
0: Disabled
1: Enabled
0 RTCEN R/W 0
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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Interrupt Mask
0: Masked
1: Unmasked
3 EXTW R/W 0
Low Battery Voltage Interrupt Mask
0: Masked
1: Unmasked
2 LOWBAT R/W 0
RTC Alert1 Interrupt Mask
0: Masked
1: Unmasked
1 RTCALT1 R/W 0
RTC Alert0 Interrupt Mask
0: Masked
1: Unmasked
0 RTCALT0 R/W 0
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Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Raw Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status
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Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Masked Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status
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Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
3 EXTW R/W1C 0
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
2 LOWBAT R/W1C 0
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
1 RTCALT1 R/W1C 0
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
0 RTCALT0 R/W1C 0
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Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
15:0 TRIM R/W 0x7FFF
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Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store any non-volatile state data and will not lose power during a power
cut operation.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
31:0 RTD R/W 0x0000.0000 Hibernation Module NV Registers[63:0]
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8 Internal Memory
The LM3S6952 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
8.1 Block Diagram
Figure 8-1. Flash Block Diagram
Flash Control
FMA
FCMISC
FCIM
FCRIS
FMC
FMD
Flash Timing
USECRL
Flash Protection
FMPREn
FMPPEn
Flash Array
SRAM Array
Bridge
Cortex-M3
ICode
DCode
System Bus
APB
User Registers
USER_REG0
USER_REG1
USER_DBG
8.2 Functional Description
This section describes the functionality of both the flash and SRAM memories.
8.2.1 SRAM Memory
The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
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bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
8.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 551 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
8.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
8.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed. The contents of the memory
block are prohibited from being accessed as data and traversing the DCode bus.
The policies may be combined as shown in Table 8-1 on page 141.
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Table 8-1. Flash Protection Policy Combinations
FMPPEn FMPREn Protection
Execute-only protection. The block may only be executed and may not be written or erased. This mode
is used to protect code.
0 0
1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used.
Read-only protection. The block may be read or executed but may not be written or erased. This mode
is used to lock the block from further modification while allowing any read or execute access.
0 1
1 1 No protection. The block may be written, erased, executed or read.
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt
may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers
of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. Details on
programming these bits are discussed in “Nonvolatile Register Programming” on page 142.
8.3 Flash Memory Initialization and Configuration
8.3.1 Flash Programming
The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
8.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
8.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
8.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
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8.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the flash memory itself.
These registers exist in a separate space from the main flash array and are not affected by an
ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit
in the FMC register to activate a write operation. For the USER_DBG register, the data to be written
must be loaded into the FMD register before it is "committed". All other registers are R/W and can
have their operation tried before committing them to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by the user and there is no
mechanism for the user to erase them back to a 1 value.
In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective
registers to indicate that they are available for user write. These three registers can only be written
once whereas the flash protection registers may be written multiple times. Table 8-2 on page 142
provides the FMA address required for commitment of each of the registers and the source of the
data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.
After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to
complete.
Table 8-2. Flash Resident Registersa
Register to be Committed FMA Value Data Source
FMPRE0 0x0000.0000 FMPRE0
FMPRE1 0x0000.0002 FMPRE1
FMPRE2 0x0000.0004 FMPRE2
FMPRE3 0x0000.0008 FMPRE3
FMPPE0 0x0000.0001 FMPPE0
FMPPE1 0x0000.0003 FMPPE1
FMPPE2 0x0000.0005 FMPPE2
FMPPE3 0x0000.0007 FMPPE3
USER_REG0 0x8000.0000 USER_REG0
USER_REG1 0x8000.0001 USER_REG1
USER_DBG 0x7510.0000 FMD
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device.
8.4 Register Map
Table 8-3 on page 142 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers
are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL,
USER_DBG, and USER_REGn registers are relative to the System Control base address of
0x400F.E000.
Table 8-3. Flash Register Map
See
Offset Name Type Reset Description page
Flash Control Offset
0x000 FMA R/W 0x0000.0000 Flash Memory Address 144
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See
Offset Name Type Reset Description page
0x004 FMD R/W 0x0000.0000 Flash Memory Data 145
0x008 FMC R/W 0x0000.0000 Flash Memory Control 146
0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 148
0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 149
0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 150
System Control Offset
0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 152
0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 152
0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 153
0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 153
0x140 USECRL R/W 0x31 USec Reload 151
0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 154
0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 155
0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 156
0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 157
0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 158
0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 159
0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 160
0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 161
0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 162
8.5 Flash Register Descriptions (Flash Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved OFFSET
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:18 reserved RO 0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register Programming” on page
142 for details on values for this field).
17:0 OFFSET R/W 0x0
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Data Value
Data value for write operation.
31:0 DATA R/W 0x0
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 144). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 145) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRKEY
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved COMT MERASE ERASE WRITE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
31:16 WRKEY WO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:4 reserved RO 0x0
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
3 COMT R/W 0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
2 MERASE R/W 0
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Bit/Field Name Type Reset Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
1 ERASE R/W 0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 μs.
0 WRITE R/W 0
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIS ARIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Raw Interrupt Status
This bit indicates the current state of the programming cycle. If set, the
programming cycle completed; if cleared, the programming cycle has
not completed. Programming cycles are either write or erase actions
generated through the Flash Memory Control (FMC) register bits (see
page 146).
1 PRIS RO 0
Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If set, the program
tried to access the flash counter to the policy as set in the Flash Memory
Protection Read Enable (FMPREn) and Flash Memory Protection
Program Enable (FMPPEn) registers. Otherwise, no access has tried
to improperly access the flash.
0 ARIS RO 0
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMASK AMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
1 PMASK R/W 0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
0 AMASK R/W 0
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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMISC AMISC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 148) is also
cleared when the PMISC bit is cleared.
1 PMISC R/W1C 0
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
0 AMISC R/W1C 0
8.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved USEC
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
USEC should be set to 0x31 (50 MHz) whenever the flash is being erased
or programmed.
7:0 USEC R/W 0x31
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Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.D000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.D000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA DBG1 DBG0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Bit/Field Name Type Reset Description
User Debug Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:2 DATA R/W 0x1FFFFFFF
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1 DBG1 R/W 1
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0 DBG0 R/W 0
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Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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9 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module is
FiRM-compliant and supports 6-43 programmable input/output pins, depending on the peripherals
being used.
The GPIO module has the following features:
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ 5-V-tolerant input/outputs
■ Bit masking in both read and write operations through address lines
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
9.1 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 164). The LM3S6952 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
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Figure 9-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
DEMUX MUX MUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
9.1.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
9.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 171) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
9.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 170) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
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For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 9-2 on page 165, where u is data unchanged by the write.
Figure 9-2. GPIODATA Write Example
0 0 1 0 0 1 1 0 1 0
u u 1 u u 0 1 u
9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 1
7 6 5 4 3 2 1 0
GPIODATA
0xEB
0x098
ADDR[9:2]
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 165.
Figure 9-3. GPIODATA Read Example
0 0 1 1 0 0 0 1 0 0
0 0 1 1 0 0 0 0
9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 0
7 6 5 4 3 2 1 0
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
9.1.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 172)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 173)
■ GPIO Interrupt Event (GPIOIEV) register (see page 174)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 175).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 176 and page 177). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
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In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for
PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer
Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 178).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
9.1.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
9.1.4 Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
9.1.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
9.1.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 167
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 9-2 on page 167 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
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Table 9-1. GPIO Pad Configuration Examples
Configuration GPIO Register Bit Valuea
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Input (GPIO) 0 0 0 1 ? ? X X X X
Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ?
Open Drain Input 0 0 1 1 X X X X X X
(GPIO)
Open Drain Output 0 1 1 1 X X ? ? ? ?
(GPIO)
Open Drain 1 X 1 1 X X ? ? ? ?
Input/Output (I2C)
Digital Input (Timer 1 X 0 1 ? ? X X X X
CCP)
Digital Input (QEI) 1 X 0 1 ? ? X X X X
Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ?
Digital Output (Timer 1 X 0 1 ? ? ? ? ? ?
PWM)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(SSI)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(UART)
Analog Input 0 0 0 0 0 0 X X X X
(Comparator)
Digital Output 1 X 0 1 ? ? ? ? ? ?
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-2. GPIO Interrupt Configuration Example
Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register
7 6 5 4 3 2 1 0
0=edge X X X X X 0 X X
1=level
GPIOIS
0=single X X X X X 0 X X
edge
1=both
edges
GPIOIBE
0=Low level, X X X X X 1 X X
or negative
edge
1=High level,
or positive
edge
GPIOIEV
0=masked 0 0 0 0 0 1 0 0
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
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9.3 Register Map
Table 9-3 on page 168 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
Important: The GPIO registers in this chapter are duplicated in each GPIO block, however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins, with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-commitable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 9-3. GPIO Register Map
See
Offset Name Type Reset Description page
0x000 GPIODATA R/W 0x0000.0000 GPIO Data 170
0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 171
0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 172
0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 173
0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 174
0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 175
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See
Offset Name Type Reset Description page
0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 176
0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 177
0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 178
0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 179
0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 181
0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 182
0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 183
0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 184
0x510 GPIOPUR R/W - GPIO Pull-Up Select 185
0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 186
0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 187
0x51C GPIODEN R/W - GPIO Digital Enable 188
0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 189
0x524 GPIOCR - - GPIO Commit 190
0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 192
0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 193
0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 194
0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 195
0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 196
0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 197
0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 198
0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 199
0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 200
0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 201
0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 202
0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 203
9.4 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 171).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 164 for examples of
reads and writes.
7:0 DATA R/W 0x00
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0 Pins are inputs.
1 Pins are outputs.
7:0 DIR R/W 0x00
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IS
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0 Edge on corresponding pin is detected (edge-sensitive).
1 Level on corresponding pin is detected (level-sensitive).
7:0 IS R/W 0x00
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 172) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 174). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IBE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 174).
0
1 Both edges on the corresponding pin trigger an interrupt.
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
7:0 IBE R/W 0x00
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 172). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IEV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
7:0 IEV R/W 0x00
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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x410
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IME
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.
7:0 IME R/W 0x00
November 30, 2007 175
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 175). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x414
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0 Corresponding pin interrupt requirements not met.
1 Corresponding pin interrupt has met requirements.
7:0 RIS RO 0x00
176 November 30, 2007
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for
PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer
Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x418
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0 Corresponding GPIO line interrupt not active.
1 Corresponding GPIO line asserting interrupt.
7:0 MIS RO 0x00
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LM3S6952 Microcontroller
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0 Corresponding interrupt is unaffected.
1 Corresponding interrupt is cleared.
7:0 IC W1C 0x00
178 November 30, 2007
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x420
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AFSEL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
November 30, 2007 179
Preliminary
LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0 Software control of corresponding GPIO line (GPIO mode).
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 AFSEL R/W -
180 November 30, 2007
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV2
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV2 R/W 0xFF
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LM3S6952 Microcontroller
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x504
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV4
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV4 R/W 0x00
182 November 30, 2007
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General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x508
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV8
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV8 R/W 0x00
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LM3S6952 Microcontroller
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 188). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open
drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output
when set to 1.
When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for
PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 166).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ODE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0 Open drain configuration is disabled.
1 Open drain configuration is enabled.
7:0 ODE R/W 0x00
184 November 30, 2007
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General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 186).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x510
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PUE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
7:0 PUE R/W -
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Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 185).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x514
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
7:0 PDE R/W 0x00
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Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 183).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x518
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SRL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0 Slew rate control disabled.
1 Slew rate control enabled.
7:0 SRL R/W 0x00
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Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x51C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Digital Enable
The DEN values are defined as follows:
Value Description
0 Digital functions disabled.
1 Digital functions enabled.
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 DEN R/W -
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Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 190). Writing
0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x520
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
GPIO Lock
A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR)
register for write access. A write of any other value reapplies the lock,
preventing any register updates. A read of this register returns the
following values:
Value Description
0x0000.0001 locked
0x0000.0000 unlocked
31:0 LOCK R/W 0x0000.0001
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Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is
performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit
in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the
GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register
will be committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers
that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of
the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only
be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR,
and GPIOAFSEL registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSEL register bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x524
Type -, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CR
Type RO RO RO RO RO RO RO RO - - - - - - - -
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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Bit/Field Name Type Reset Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins, with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-commitable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
7:0 CR - -
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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]
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Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]
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Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x61
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Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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10 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1,
and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and
TimerB) that can be configured to operate independently as timers or event counters, or configured
to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to
trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers
are ORed together before reaching the ADC module, so only one timer should be used to trigger
ADC events.
Note: Timer2 is an internal timer and can only be used to generate internal interrupts or trigger
ADC events.
The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers.
Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 40)
and the PWM timer in the PWM module (see “PWM Timer” on page 466).
The following modes are supported:
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock using 32.768-KHz input clock
– Software-controlled event stalling (excluding RTC mode)
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– Software-controlled event stalling
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
10.1 Block Diagram
Note: In Figure 10-1 on page 205, the specific CCP pins available depend on the Stellaris® device.
See Table 10-1 on page 205 for the available CCPs.
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Figure 10-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 10-1. Available CCP Pins
Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA CCP0 -
TimerB - CCP1
Timer 1 TimerA CCP2 -
TimerB - CCP3
Timer 2 TimerA - -
TimerB - -
10.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 216),
the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 219). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
10.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
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(GPTMTAILR) register (see page 230) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 231). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 234) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 235).
10.2.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 230
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 231
■ GPTM TimerA (GPTMTAR) register [15:0], see page 238
■ GPTM TimerB (GPTMTBR) register [15:0], see page 239
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
10.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 217), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 221), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and output triggers when
it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 226), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 228). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 224), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 227).
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000
state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL,
and can trigger SoC-level events such as ADC conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
10.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 232) by the controller.
The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The
clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
10.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 216). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
10.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and output triggers when it
reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it
until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR,
the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state,
and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL
register, and can trigger SoC-level events such as ADC conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 10-2. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (T c)a Max Time Units
00000000 1 1.3107 mS
00000001 2 2.6214 mS
00000010 3 3.9321 mS
------------ -- -- --
11111100 254 332.9229 mS
11111110 255 334.2336 mS
11111111 256 335.5443 mS
a. Tc is the clock period.
10.2.3.2 16-Bit Input Edge Count Mode
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 10-2 on page 209 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 10-2. 16-Bit Input Edge Count Mode Example
0x000A
0x0006
0x0007
0x0008
0x0009
Input Signal
Timer stops,
flags
asserted
Timer reload
Count on next cycle Ignored Ignored
10.2.3.3 16-Bit Input Edge Time Mode
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both
rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the
GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT
fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 10-3 on page 210 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 10-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
10.2.3.4 16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR
field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software
clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM
mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 10-4 on page 211 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 10-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
10.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, and TIMER2 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
10.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 212. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
10.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
10.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 212. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
10.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 213
through step 9 on page 213.
10.3.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
10.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register
and the GPTM Timern Prescale Match (GPTMTnPMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
10.4 Register Map
Table 10-3 on page 214 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
Table 10-3. Timers Register Map
See
Offset Name Type Reset Description page
0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 216
0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 217
0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 219
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See
Offset Name Type Reset Description page
0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 221
0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 224
0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 226
0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 227
0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 228
GPTM TimerA Interval Load 230
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x028 GPTMTAILR R/W
0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 231
GPTM TimerA Match 232
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x030 GPTMTAMATCHR R/W
0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 233
0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 234
0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 235
0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 236
0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 237
GPTM TimerA 238
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x048 GPTMTAR RO
0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 239
10.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPTMCFG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved.
0x3 Reserved.
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
2:0 GPTMCFG R/W 0x0
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAAMS TACMR TAMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
3 TAAMS R/W 0
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0 Edge-Count mode.
1 Edge-Time mode.
2 TACMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved.
0x1 One-Shot Timer mode.
0x2 Periodic Timer mode.
0x3 Capture mode.
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
1:0 TAMR R/W 0x0
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBAMS TBCMR TBMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
3 TBAMS R/W 0
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0 Edge-Count mode.
1 Edge-Time mode.
2 TBCMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved.
0x1 One-Shot Timer mode.
0x2 Periodic Timer mode.
0x3 Capture mode.
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
1:0 TBMR R/W 0x0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x00
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
14 TBPWML R/W 0
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output TimerB trigger is disabled.
1 The output TimerB trigger is enabled.
13 TBOTE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge.
0x1 Negative edge.
0x2 Reserved
0x3 Both edges.
11:10 TBEVENT R/W 0x0
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 TimerB stalling is disabled.
1 TimerB stalling is enabled.
9 TBSTALL R/W 0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0 TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
8 TBEN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
6 TAPWML R/W 0
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0 The output TimerA trigger is disabled.
1 The output TimerA trigger is enabled.
5 TAOTE R/W 0
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Bit/Field Name Type Reset Description
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
0 RTC counting is disabled.
1 RTC counting is enabled.
4 RTCEN R/W 0
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge.
0x1 Negative edge.
0x2 Reserved
0x3 Both edges.
3:2 TAEVENT R/W 0x0
GPTM TimerA Stall Enable
The TASTALL values are defined as follows:
Value Description
0 TimerA stalling is disabled.
1 TimerA stalling is enabled.
1 TASTALL R/W 0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0 TimerA is disabled.
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 TAEN R/W 0
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
10 CBEIM R/W 0
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9 CBMIM R/W 0
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
8 TBTOIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
3 RTCIM R/W 0
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
2 CAEIM R/W 0
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
1 CAMIM R/W 0
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
0 TATOIM R/W 0
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
10 CBERIS RO 0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
9 CBMRIS RO 0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
8 TBTORIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
3 RTCRIS RO 0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
2 CAERIS RO 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
1 CAMRIS RO 0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0 TATORIS RO 0
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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
10 CBEMIS RO 0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
9 CBMMIS RO 0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
8 TBTOMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
3 RTCMIS RO 0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
2 CAEMIS RO 0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMMIS RO 0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0 TATOMIS RO 0
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x024
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT
Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
10 CBECINT W1C 0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
9 CBMCINT W1C 0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
8 TBTOCINT W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
3 RTCCINT W1C 0
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
2 CAECINT W1C 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMCINT W1C 0
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
0 TATOCINT W1C 0
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x028
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAILRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAILRH R/W
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
15:0 TAILRL R/W 0xFFFF
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Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
15:0 TBILRL R/W 0xFFFF
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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAMRH R/W
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
15:0 TAMRL R/W 0xFFFF
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Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
15:0 TBMRL R/W 0xFFFF
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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 10-2 on page 208 for more details and an example.
7:0 TAPSR R/W 0x00
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Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 10-2 on page 208 for more details and an example.
7:0 TBPSR R/W 0x00
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
7:0 TAPSMR R/W 0x00
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Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
7:0 TBPSMR R/W 0x00
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Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x048
Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARH
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TARH RO
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TARL RO 0xFFFF
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General-Purpose Timers
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBRL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TBRL RO 0xFFFF
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LM3S6952 Microcontroller
11 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
11.1 Block Diagram
Figure 11-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
11.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
240 November 30, 2007
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Watchdog Timer
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
11.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
11.4 Register Map
Table 11-1 on page 241 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 11-1. Watchdog Timer Register Map
See
Offset Name Type Reset Description page
0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 243
0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 244
0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 245
0x00C WDTICR WO - Watchdog Interrupt Clear 246
0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 247
0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 248
0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 249
0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 250
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See
Offset Name Type Reset Description page
0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 251
0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 252
0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 253
0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 254
0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 255
0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 256
0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 257
0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 258
0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 259
0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 260
0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 261
0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 262
11.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
242 November 30, 2007
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Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value
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LM3S6952 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Watchdog Value
Current value of the 32-bit down counter.
31:0 WDTValue RO 0xFFFF.FFFF
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Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RESEN INTEN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0 Disabled.
1 Enable the Watchdog module reset output.
1 RESEN R/W 0
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
1 Interrupt event enabled. Once enabled, all writes are ignored.
0 INTEN R/W 0
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Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
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Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0 WDTRIS RO 0
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LM3S6952 Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0 WDTMIS RO 0
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Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALL reserved
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:9 reserved RO 0x00
Watchdog Stall Enable
When set to 1, if the Stellaris® microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
8 STALL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 0x00
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LM3S6952 Microcontroller
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked
31:0 WDTLock R/W 0x0000
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Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]
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LM3S6952 Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]
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Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]
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LM3S6952 Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]
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Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]
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LM3S6952 Microcontroller
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]
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Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]
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LM3S6952 Microcontroller
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]
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Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]
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Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]
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Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]
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Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]
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Watchdog Timer
12 Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The Stellaris® ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. The ADC module contains a programmable sequencer which
allows for the sampling of multiple analog input sources without controller intervention. Each sample
sequence provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequence priority.
The Stellaris® ADC provides the following features:
■ Three analog input channels
■ Single-ended and differential-input configurations
■ Internal temperature sensor
■ Sample rate of 500 thousand samples/second
■ Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
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12.1 Block Diagram
Figure 12-1. ADC Module Block Diagram
Analog-to-Digital
Converter
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
FIFO Block
ADCSSFSTAT0
ADCSSCTL0
ADCSSMUX0
Sample
Sequencer 0
ADCSSFSTAT1
ADCSSCTL1
ADCSSMUX1
Sample
Sequencer 1
ADCSSFSTAT2
ADCSSCTL2
ADCSSMUX2
Sample
Sequencer 2
ADCSSFSTAT3
ADCSSCTL3
ADCSSMUX3
Sample
Sequencer 3
ADCUSTAT
ADCOSTAT
ADCACTSS
Control/Status
ADCSSPRI
ADCISC
ADCRIS
ADCIM
Interrupt Control
SS0 Interrupt
Analog Inputs
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
ADCEMUX
ADCPSSI
Trigger Events
SS0
SS1
SS2
SS3
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Hardware Averager
ADCSAC
12.2 Functional Description
The Stellaris® ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the controller. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.
12.2.1 Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 12-1 on page 264 shows the maximum number of samples that each Sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 12-1. Samples and FIFO Depth of Sequencers
Sequencer Number of Samples Depth of FIFO
SS3 1 1
SS2 4 4
SS1 4 4
SS0 8 8
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For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample Sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any
combination of samples, allowing interrupts to be generated after every sample in the sequence if
necessary. Also, the END bit can be set at any point within a sample sequence. For example, if
Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing
Sequencer 0 to complete execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.
12.2.2 Module Control
Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such
as interrupt generation, sequence prioritization, and trigger configuration.
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris® devices.
12.2.2.1 Interrupts
The Sample Sequencers dictate the events that cause interrupts, but they don't have control over
whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal
is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt
status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which
shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and
Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the
ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
12.2.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample
Sequencer units with the same priority do not provide consistent results, so software must ensure
that all active Sample Sequencer units have a unique priority value.
12.2.2.3 Sampling Events
Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris® family member,
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but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.
12.2.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 281). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.
12.2.4 Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input.
12.2.5 Test Modes
There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual analog
stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see
page 294).
12.2.6 Internal Temperature Sensor
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:
SENSO = 2.7 - ((T + 55) / 75)
This relation is shown in Figure 12-2 on page 267.
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Figure 12-2. Internal Temperature Sensor Characteristic
12.3 Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
12.3.1 Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 100).
2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
12.3.2 Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
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4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
12.4 Register Map
Table 12-2 on page 268 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Table 12-2. ADC Register Map
See
Offset Name Type Reset Description page
0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 270
0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 271
0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 272
0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 273
0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 274
0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 275
0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 278
0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 279
0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 280
0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 281
0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 282
0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 284
0x048 ADCSSFIFO0 RO 0x0000.0000 ADC Sample Sequence Result FIFO 0 287
0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 288
0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 289
0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 290
0x068 ADCSSFIFO1 RO 0x0000.0000 ADC Sample Sequence Result FIFO 1 287
0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 288
0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 289
0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 290
0x088 ADCSSFIFO2 RO 0x0000.0000 ADC Sample Sequence Result FIFO 2 287
0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 288
0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 292
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See
Offset Name Type Reset Description page
0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 293
0x0A8 ADCSSFIFO3 RO 0x0000.0000 ADC Sample Sequence Result FIFO 3 287
0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 288
0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 294
12.5 Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ASEN3 ASEN2 ASEN1 ASEN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
ADC SS3 Enable
Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is
inactive.
3 ASEN3 R/W 0
ADC SS2 Enable
Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is
inactive.
2 ASEN2 R/W 0
ADC SS1 Enable
Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is
inactive.
1 ASEN1 R/W 0
ADC SS0 Enable
Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is
inactive.
0 ASEN0 R/W 0
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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INR3 INR2 INR1 INR0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL3 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN3 bit.
3 INR3 RO 0
SS2 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL2 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN2 bit.
2 INR2 RO 0
SS1 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL1 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN1 bit.
1 INR1 RO 0
SS0 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL0 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN0 bit.
0 INR0 RO 0
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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller
interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently.
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MASK3 MASK2 MASK1 MASK0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 3
(ADCRIS register INR3 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
3 MASK3 R/W 0
SS2 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 2
(ADCRIS register INR2 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
2 MASK2 R/W 0
SS1 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 1
(ADCRIS register INR1 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
1 MASK1 R/W 0
SS0 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 0
(ADCRIS register INR0 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0 MASK0 R/W 0
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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding
bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still
cleared via the ADCISC register, even if the IN bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN3 IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Interrupt Status and Clear
This bit is set by hardware when the MASK3 and INR3 bits are both 1,
providing a level-based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR3 bit.
3 IN3 R/W1C 0
SS2 Interrupt Status and Clear
This bit is set by hardware when the MASK2 and INR2 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR2 bit.
2 IN2 R/W1C 0
SS1 Interrupt Status and Clear
This bit is set by hardware when the MASK1 and INR1 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR1 bit.
1 IN1 R/W1C 0
SS0 Interrupt Status and Clear
This bit is set by hardware when the MASK0 and INR0 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR0 bit.
0 IN0 R/W1C 0
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Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OV3 OV2 OV1 OV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
3 OV3 R/W1C 0
SS2 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
2 OV2 R/W1C 0
SS1 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
1 OV1 R/W1C 0
SS0 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0 OV0 R/W1C 0
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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each
Sample Sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM3 EM2 EM1 EM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
15:12 EM3 R/W 0x00
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Bit/Field Name Type Reset Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
11:8 EM2 R/W 0x00
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
7:4 EM1 R/W 0x00
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Bit/Field Name Type Reset Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
3:0 EM0 R/W 0x00
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Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding
underflow condition can be cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved UV3 UV2 UV1 UV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
3 UV3 R/W1C 0
SS2 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
2 UV2 R/W1C 0
SS1 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
1 UV1 R/W1C 0
SS0 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0 UV0 R/W1C 0
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Analog-to-Digital Converter (ADC)
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has
the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence
priorities, each sequence must have a unique priority or the ADC behavior is inconsistent.
ADC Sample Sequencer Priority (ADCSSPRI)
Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 reserved SS2 reserved SS1 reserved SS0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
SS3 Priority
The SS3 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the Sequencers must be
uniquely mapped. ADC behavior is not consistent if two or more fields
are equal.
13:12 SS3 R/W 0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0x0
SS2 Priority
The SS2 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2.
9:8 SS2 R/W 0x2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
SS1 Priority
The SS1 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1.
5:4 SS1 R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
SS0 Priority
The SS0 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0.
1:0 SS0 R/W 0x0
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Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 SS2 SS1 SS0
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO -
SS3 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS
register.
3 SS3 WO -
SS2 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS
register.
2 SS2 WO -
SS1 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS
register.
1 SS1 WO -
SS0 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS
register.
0 SS0 WO -
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Analog-to-Digital Converter (ADC)
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AVG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0 No hardware oversampling
0x1 2x hardware oversampling
0x2 4x hardware oversampling
0x3 8x hardware oversampling
0x4 16x hardware oversampling
0x5 32x hardware oversampling
0x6 64x hardware oversampling
0x7 Reserved
2:0 AVG R/W 0x0
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Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:30 reserved RO 0
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the Sample Sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.
29:28 MUX7 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:26 reserved RO 0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
25:24 MUX6 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22 reserved RO 0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
21:20 MUX5 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:18 reserved RO 0
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Bit/Field Name Type Reset Description
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
17:16 MUX4 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14 reserved RO 0
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
13:12 MUX3 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
9:8 MUX2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
5:4 MUX1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
1:0 MUX0 R/W 0
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Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
8th Sample Temp Sensor Select
The TS7 bit is used during the eighth sample of the sample sequence
and specifies the input source of the sample. If set, the temperature
sensor is read. Otherwise, the input pin specified by the ADCSSMUX
register is read.
31 TS7 R/W 0
8th Sample Interrupt Enable
The IE7 bit is used during the eighth sample of the sample sequence
and specifies whether the raw interrupt signal (INR0 bit) is asserted at
the end of the sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted, otherwise it is not. It
is legal to have multiple samples within a sequence generate interrupts.
30 IE7 R/W 0
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
29 END7 R/W 0
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". The temperature sensor
does not have a differential option. When set, the analog inputs are
differentially sampled.
28 D7 R/W 0
7th Sample Temp Sensor Select
Same definition as TS7 but used during the seventh sample.
27 TS6 R/W 0
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Bit/Field Name Type Reset Description
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
26 IE6 R/W 0
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
25 END6 R/W 0
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
24 D6 R/W 0
6th Sample Temp Sensor Select
Same definition as TS7 but used during the sixth sample.
23 TS5 R/W 0
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
22 IE5 R/W 0
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
21 END5 R/W 0
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
20 D5 R/W 0
5th Sample Temp Sensor Select
Same definition as TS7 but used during the fifth sample.
19 TS4 R/W 0
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
18 IE4 R/W 0
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
17 END4 R/W 0
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
16 D4 R/W 0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
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Bit/Field Name Type Reset Description
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Analog-to-Digital Converter (ADC)
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
9:0 DATA RO 0x00 Conversion Result Data
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Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the Sample Sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FULL reserved EMPTY HPTR TPTR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x00
FIFO Full
When set, indicates that the FIFO is currently full.
12 FULL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0x00
FIFO Empty
When set, indicates that the FIFO is currently empty.
8 EMPTY RO 1
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
7:4 HPTR RO 0x00
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
3:0 TPTR RO 0x00
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Analog-to-Digital Converter (ADC)
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 282 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
13:12 MUX3 R/W 0 4th Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
9:8 MUX2 R/W 0 3rd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
5:4 MUX1 R/W 0 2nd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. This register is
16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on
page 284 for detailed bit descriptions.
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
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Bit/Field Name Type Reset Description
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample.
See the ADCSSMUX0 register on page 282 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 284 for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TS0 IE0 END0 D0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 1
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100
This register provides loopback operation within the digital logic of the ADC, which can be useful in
debugging software without having to provide actual analog stimulus. This test mode is entered by
writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode,
the read-only portion of this register is returned.
Read-Only Register
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CNT CONT DIFF TS MUX
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Continuous Sample Counter
Continuous sample counter that is initialized to 0 and counts each
sample as it processed. This helps provide a unique value for the data
received.
9:6 CNT RO 0x0
Continuation Sample Indicator
When set, indicates that this is a continuation sample. For example, if
two sequencers were to run back-to-back, this indicates that the
controller kept continuously sampling at full rate.
5 CONT RO 0
Differential Sample Indicator
When set, indicates that this is a differential sample.
4 DIFF RO 0
Temp Sensor Sample Indicator
When set, indicates that this is a temperature sensor sample.
3 TS RO 0
Analog Input Indicator
Indicates which analog input is to be sampled.
2:0 MUX RO 0x0
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Write-Only Register
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LB
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Loopback Mode Enable
When set, forces a loopback within the digital block to provide information
on input and unique numbering.
The 10-bit loopback data is defined as shown in the read for bits 9:0
above.
0 LB WO 0
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13 Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S6952 controller is equipped with three UART
modules.
Each UART has the following features:
■ Separate transmit and receive FIFOs
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Programmable baud-rate generator allowing rates up to 3.125 Mbps
■ Standard asynchronous communication bits for start, stop, and parity
■ False start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing:
– Programmable use of IrDA Serial InfraRed (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
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13.1 Block Diagram
Figure 13-1. UART Module Block Diagram
Receiver
Transmitter
System Clock
Control / Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Baud Rate
Generator
UARTIBRD
UARTFBRD
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UART PeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTDR
TXFIFO
16x8
...
RXFIFO
16x8
...
Interrupt
UnTx
UnRx
13.2 Functional Description
Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 315). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
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bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 298 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 13-2. UART Character Frame
1
0 5-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
13.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 311) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 312). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 313), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
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13.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 308) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 297).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 306). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
13.2.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output, and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register.
Figure 13-3 on page 300 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 13-3. IrDA Data Modulation
0 1 0 1 0 0 1 1 0 1
Data bits
0 1 0 1 0 0 1 1 0 1
Start Data bits
bit
Start Stop
Bit period Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
13.2.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 304). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 313).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 308) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 317). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
13.2.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
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■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 322).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 319) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 321).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 323).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
13.2.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 315). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
13.2.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
13.3 Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2
bits in the RCGC1 register.
This section discusses the steps that are required for using a UART module. For this example, the
system clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
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■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 298, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 311) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 312) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
13.4 Register Map
Table 13-1 on page 302 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 315)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 13-1. UART Register Map
See
Offset Name Type Reset Description page
0x000 UARTDR R/W 0x0000.0000 UART Data 304
0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 306
0x018 UARTFR RO 0x0000.0090 UART Flag 308
0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 310
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See
Offset Name Type Reset Description page
0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 311
0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 312
0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 313
0x030 UARTCTL R/W 0x0000.0300 UART Control 315
0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 317
0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 319
0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 321
0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 322
0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 323
0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 325
0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 326
0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 327
0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 328
0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 329
0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 330
0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 331
0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 332
0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 333
0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 334
0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 335
0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 336
13.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0
UART Overrun Error
The OE values are defined as follows:
Value Description
0 There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
1
11 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
10 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
9 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
8 FE RO 0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
7:0 DATA R/W 0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Read-Only Receive Status (UARTRSR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
3 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
2 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
1 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0 FE RO 0
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved WO 0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
7:0 DATA WO 0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXFE RXFF TXFF RXFE BUSY reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
7 TXFE RO 1
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
6 RXFF RO 0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
5 TXFF RO 0
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Bit/Field Name Type Reset Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
4 RXFE RO 1
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
3 BUSY RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the
bits are cleared to 0 when reset.
The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to
the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as
follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ILPDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
7:0 ILPDVSR R/W 0x00
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVINT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0
15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x028
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIVFRAC
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor
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Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SPS WLEN FEN STP2 EPS PEN BRK
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
7 SPS R/W 0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
6:5 WLEN R/W 0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
4 FEN R/W 0
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Bit/Field Name Type Reset Description
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
3 STP2 R/W 0
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
2 EPS R/W 0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
1 PEN R/W 0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0 BRK R/W 0
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Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXE TXE LBE reserved SIRLP SIREN UARTEN
Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
9 RXE R/W 1
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
8 TXE R/W 1
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
7 LBE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:3 reserved RO 0
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Bit/Field Name Type Reset Description
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 310 for more
information.
2 SIRLP R/W 0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
1 SIREN R/W 0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0 UARTEN R/W 0
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Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x034
Type R/W, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXIFLSEL TXIFLSEL
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value Description
0x0 RX FIFO ≥ 1/8 full
0x1 RX FIFO ≥ ¼ full
0x2 RX FIFO ≥ ½ full (default)
0x3 RX FIFO ≥ ¾ full
0x4 RX FIFO ≥ 7/8 full
0x5-0x7 Reserved
5:3 RXIFLSEL R/W 0x2
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Bit/Field Name Type Reset Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value Description
0x0 TX FIFO ≤ 1/8 full
0x1 TX FIFO ≤ ¼ full
0x2 TX FIFO ≤ ½ full (default)
0x3 TX FIFO ≤ ¾ full
0x4 TX FIFO ≤ 7/8 full
0x5-0x7 Reserved
2:0 TXIFLSEL R/W 0x2
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Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved
Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
10 OEIM R/W 0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
9 BEIM R/W 0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
8 PEIM R/W 0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
7 FEIM R/W 0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
6 RTIM R/W 0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
5 TXIM R/W 0
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Bit/Field Name Type Reset Description
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
4 RXIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
10 OERIS RO 0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9 BERIS RO 0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8 PERIS RO 0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7 FERIS RO 0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6 RTRIS RO 0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5 TXRIS RO 0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4 RXRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0xF
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Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
10 OEMIS RO 0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9 BEMIS RO 0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8 PEMIS RO 0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7 FEMIS RO 0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6 RTMIS RO 0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5 TXMIS RO 0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4 RXMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved
Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
10 OEIC W1C 0
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
9 BEIC W1C 0
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8 PEIC W1C 0
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Bit/Field Name Type Reset Description
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
7 FEIC W1C 0
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
6 RTIC W1C 0
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
5 TXIC W1C 0
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
4 RXIC W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x0000
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Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x0000
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Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x0000
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Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x0000
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Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE0
Type RO, reset 0x0000.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x11
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Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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14 Synchronous Serial Interface (SSI)
The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The Stellaris® SSI module has the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
14.1 Block Diagram
Figure 14-1. SSI Module Block Diagram
Transmit/
Receive
Logic
Clock
Prescaler
SSICPSR
Control / Status
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x 16
...
RxFIFO
8 x 16
...
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification Registers
SSIPCellID0 SSIPeriphID0 SSIPeriphID4
SSIPCellID1 SSIPeriphID1 SSIPeriphID5
SSIPCellID2 SSIPeriphID2 SSIPeriphID6
SSIPCellID3 SSIPeriphID3 SSIPeriphID7
14.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
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internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
14.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 356). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 349).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For master mode, the system clock must be at least two times faster
than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 543 to view SSI timing parameters.
14.2.2 FIFO Operation
14.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 353), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
14.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
14.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
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of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 357). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 359 and page 360, respectively).
14.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
14.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 14-2 on page 339 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
4 to 16 bits
SSIFss
SSITx/SSIRx MSB LSB
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In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 14-3 on page 340 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB LSB
4 to 16 bits
SSIClk
SSIFss
SSITx/SSIRx
14.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
14.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 14-4 on page 341 and Figure 14-5 on page 341.
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Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx Q
SSITx
MSB
MSB
LSB
LSB
Note: Q is undefined.
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
4 to 16 bits
LSB MSB
MSB
MSB
LSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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14.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
14-6 on page 342, which covers both single and continuous transfers.
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 14-7 on page 343 and Figure 14-8 on page 343.
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Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
MSB Q
MSB LSB
LSB
Note: Q is undefined.
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
LSB MSB
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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14.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
14-9 on page 344, which covers both single and continuous transfers.
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q Q
MSB
MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.2.4.7 MICROWIRE Frame Format
Figure 14-10 on page 345 shows the MICROWIRE frame format, again for a single frame. Figure
14-11 on page 346 shows the same format when back-to-back frames are transmitted.
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Figure 14-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx MSB LSB
8-bit control
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 14-11. MICROWIRE Frame Format (Continuous Transfer)
8-bit control
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx LSB MSB LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 14-12 on page 346 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk)
tHold=tSSIClk
14.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
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4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
14.4 Register Map
Table 14-1 on page 347 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 14-1. SSI Register Map
See
Offset Name Type Reset Description page
0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 349
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See
Offset Name Type Reset Description page
0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 351
0x008 SSIDR R/W 0x0000.0000 SSI Data 353
0x00C SSISR RO 0x0000.0003 SSI Status 354
0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 356
0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 357
0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 359
0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 360
0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 361
0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 362
0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 363
0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 364
0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 365
0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 366
0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 367
0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 368
0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 369
0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 370
0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 371
0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 372
0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 373
14.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCR SPH SPO FRF DSS
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
15:8 SCR R/W 0x0000
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
7 SPH R/W 0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
6 SPO R/W 0
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Bit/Field Name Type Reset Description
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Intruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
5:4 FRF R/W 0x0
SSI Data Size Select
The DSS values are defined as follows:
Value Data Size
0x0-0x2 Reserved
0x3 4-bit data
0x4 5-bit data
0x5 6-bit data
0x6 7-bit data
0x7 8-bit data
0x8 9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data
3:0 DSS R/W 0x00
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SOD MS SSE LBM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
0 SSI can drive SSITx output in Slave Output mode.
1 SSI must not drive the SSITx output in Slave mode.
3 SOD R/W 0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0 Device configured as a master.
1 Device configured as a slave.
2 MS R/W 0
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Bit/Field Name Type Reset Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0 SSI operation disabled.
1 SSI operation enabled.
Note: This bit must be set to 0 before any control registers
are reprogrammed.
1 SSE R/W 0
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0 Normal serial port operation enabled.
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0 LBM R/W 0
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Register 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
15:0 DATA R/W 0x0000
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Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BSY RFF RNE TNF TFE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x00
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0 SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
4 BSY RO 0
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.
3 RFF RO 0
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.
2 RNE RO 0
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.
1 TNF RO 1
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Bit/Field Name Type Reset Description
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0 Transmit FIFO is not empty.
1 Transmit FIFO is empty.
0 TFE R0 1
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CPSDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
7:0 CPSDVSR R/W 0x00
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXIM RXIM RTIM RORIM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0 TX FIFO half-full or less condition interrupt is masked.
1 TX FIFO half-full or less condition interrupt is not masked.
3 TXIM R/W 0
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.
2 RXIM R/W 0
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.
1 RTIM R/W 0
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Bit/Field Name Type Reset Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0 RX FIFO overrun interrupt is masked.
1 RX FIFO overrun interrupt is not masked.
0 RORIM R/W 0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXRIS RXRIS RTRIS RORRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXRIS RO 1
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXRIS RO 0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTRIS RO 0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORRIS RO 0
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXMIS RXMIS RTMIS RORMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXMIS RO 0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXMIS RO 0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTMIS RO 0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORMIS RO 0
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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RTIC RORIC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
1 RTIC W1C 0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
0 RORIC W1C 0
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x00
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x00
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x00
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Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x00
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Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
Offset 0xFE0
Type RO, reset 0x0000.0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x22
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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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15 Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S6952 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
Devices on the I2C bus can be designated as either a master or a slave. The Stellaris® I2C module
supports both sending and receiving data as either a master or a slave, and also supports the
simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master
Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris® I2C module can
operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates
interrupts when data has been sent or requested by a master.
15.1 Block Diagram
Figure 15-1. I2C Block Diagram
I2C I/O Select
I2C Master Core
Interrupt
I2C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CMMIS I2CSICR
I2C Control
15.2 Functional Description
The I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 375.
See “I2C” on page 539 for I2C timing diagrams.
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Figure 15-2. I2C Bus Configuration
RPUP
StellarisTM
I2CSCL I2CSDA
RPUP
3rd Party Device
with I2C Interface
SCL SDA
I2C Bus
SCL
SDA
3rd Party Device
with I2C Interface
SCL SDA
15.2.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 375) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
15.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
15-3 on page 375.
Figure 15-3. START and STOP Conditions
START
condition
SDA
SCL
STOP
condition
SDA
SCL
15.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4 on page 376. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
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Figure 15-4. Complete Data Transfer with a 7-Bit Address
Slave address Data
SDA MSB LSB R/S ACK MSB LSB ACK
SCL 1 2 7 8 9 1 2 7 8 9
The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 376). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 15-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
15.2.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is low (see Figure 15-6 on page 376).
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus
Change
of data
allowed
Dataline
stable
SDA
SCL
15.2.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 376.
When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
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15.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
15.2.2 Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 394).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 15-1 on page 377 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 Mhz 0x01 100 Kbps - -
6 Mhz 0x02 100 Kbps - -
12.5 Mhz 0x06 89 Kbps 0x01 312 Kbps
16.7 Mhz 0x08 93 Kbps 0x02 278 Kbps
20 Mhz 0x09 100 Kbps 0x02 333 Kbps
25 Mhz 0x0C 96.2 Kbps 0x03 312 Kbps
33Mhz 0x10 97.1 Kbps 0x04 330 Kbps
40Mhz 0x13 100 Kbps 0x04 400 Kbps
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System Clock Timer Period Standard Mode Timer Period Fast Mode
50Mhz 0x18 100 Kbps 0x06 357 Kbps
15.2.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C modules. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
15.2.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
15.2.3.2 I2C Slave Interrupts
The slave module generates interrupts as it receives requests from an I2C master. To enable the
I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave
Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
15.2.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
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15.2.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
15.2.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
Figure 15-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0? NO
Write ---0-111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
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Figure 15-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0? NO
Write ---00111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
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Figure 15-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011 to
I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
Write data to ARBLST bit=1?
I2CMDR
Write ---0-100 to
Index=n? I2CMCS
NO
Error Service
Idle
YES
Write ---0-001 to
I2CMCS
Write ---0-101 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
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Figure 15-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0? NO
Write ---01011 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0? NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100 to
I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101 to
I2CMCS
YES
Idle
Read data from
Error Service I2CMDR
ERROR bit=0?
YES
Write ---01001 to
I2CMCS
Read I2CMCS
BUSY bit=0? NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
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Figure 15-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
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Figure 15-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
15.2.5.2 I2C Slave Command Sequences
Figure 15-13 on page 385 presents the command sequence available for the I2C slave.
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Figure 15-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1? NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
15.3 Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
15.4 I2C Register Map
Table 15-2 on page 386 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C Master 0: 0x4002.0000
■ I2C Slave 0: 0x4002.0800
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map
See
Offset Name Type Reset Description page
I2C Master
0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 388
0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 389
0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 393
0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 394
0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 395
0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 396
0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 397
0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 398
0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 399
I2C Slave
0x000 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 401
0x004 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 402
0x008 I2CSDR R/W 0x0000.0000 I2C Slave Data 404
0x00C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 405
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See
Offset Name Type Reset Description page
0x010 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 406
0x014 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 407
0x018 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 408
15.5 Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 400.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SA R/S
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
7:1 SA R/W 0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0 Send.
1 Receive.
0 R/S R/W 0
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
6 BUSBSY RO 0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
5 IDLE RO 0
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
4 ARBLST RO 0
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Bit/Field Name Type Reset Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
3 DATACK RO 0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
2 ADRACK RO 0
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
1 ERROR RO 0
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0 BUSY RO 0
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ACK STOP START RUN
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO 0x00
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 15-3 on page 391.
3 ACK WO 0
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 15-3 on page 391.
2 STOP WO 0
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Bit/Field Name Type Reset Description
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 15-3 on page 391.
1 START WO 0
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 15-3 on page 391.
0 RUN WO 0
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Current I2CMSA[0] I2CMCS[3:0] Description
State R/S ACK STOP START RUN
START condition followed by SEND (master goes to the
Master Transmit state).
Idle 0 Xa 0 1 1
START condition followed by a SEND and STOP
condition (master remains in Idle state).
0 X 1 1 1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1 0 0 1 1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1 0 1 1 1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
SEND operation (master remains in Master Transmit
state).
Master X X 0 0 1
Transmit
X X 1 0 0 STOP condition (master goes to Idle state).
SEND followed by STOP condition (master goes to Idle
state).
X X 1 0 1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 0 0 1 1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE (master
goes to Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
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Current I2CMSA[0] I2CMCS[3:0] Description
State R/S ACK STOP START RUN
RECEIVE operation with negative ACK (master remains
in Master Receive state).
Master X 0 0 0 1
Receive
X X 1 0 0 STOP condition (master goes to Idle state).b
RECEIVE followed by STOP condition (master goes to
Idle state).
X 0 1 0 1
RECEIVE operation (master remains in Master Receive
state).
X 1 0 0 1
X 1 1 0 1 Illegal.
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1 0 0 1 1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE (master
remains in Master Receive state).
1 1 0 1 1
Repeated START condition followed by SEND (master
goes to Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Register 3: I2C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data Transferred
Data transferred during transaction.
7:0 DATA R/W 0x00
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TPR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
7:0 TPR R/W 0x1
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Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
0 RIS RO 0
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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SFE MFE reserved LPBK
Type RO RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
5 SFE R/W 0
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
4 MFE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0x00
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
0 LPBK R/W 0
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15.6 Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 387.
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Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
This register consists of seven address bits that identify the Stellaris® I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OAR
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
6:0 OAR R/W 0x00
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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris® device detects its own slave address
and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates
that the Stellaris® I2C device has received a data byte from an I2C master. Read one data byte from
the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris® I2C device is addressed as a Slave Transmitter. Write one data byte
into the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris® I2C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FBR TREQ RREQ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
2 FBR RO 0
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
1 TREQ RO 0
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0 RREQ RO 0
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Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Device Active
Value Description
0 Disables the I2C slave operation.
1 Enables the I2C slave operation.
0 DA WO 0
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Register 12: I2C Slave Data (I2CSDR), offset 0x008
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
7:0 DATA R/W 0x0
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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
slave block. If set, an interrupt is pending; otherwise, an interrupt is not
pending.
0 RIS RO 0
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C slave
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
Offset 0x018
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Clear Interrupt
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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16 Ethernet Controller
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards.
The Ethernet Controller module has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– Automatic MDI/MDI-X cross-over correction
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
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16.1 Block Diagram
Figure 16-1. Ethernet Controller Block Diagram
MACISR
MACIACK
MACIMR
Interrupt
Control
MACRCR
MACNPR
Receive
Control
MACTCR
MACITHR
MACTRR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIAR0
MACIAR1
Individual
Address
MACMDTX
MACMCR
MACMDVR
MACMAR
MACMDRX
MII
Control
MACDR
Data
Access
TXOP
TXON
RXIP
RXIN
XTLP
XTLN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect System Clock
Interrupt
16.2 Functional Description
As shown in Figure 16-2 on page 410, the Ethernet Controller is functionally divided into two layers
or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 16-2. Ethernet Controller
Cortex M3
Media Access
Controller
MAC
(Layer 2)
Physical
Layer Entity
PHY
(Layer 1)
Magnetics RJ45
Ethernet Controller
16.2.1 Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer will auto-negotiate the link parameters by default.
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For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider
used for scaling down the system clock. See page 430 for more details about the use of this register.
16.2.2 PHY Configuration/Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
16.2.2.1 Clock Selection
The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this
mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY
pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this
mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
16.2.2.2 Auto-Negotiation
The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset.
Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the
MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual
speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the
ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing
a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart.
16.2.2.3 Polarity Correction
The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation
functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is
automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted
the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the
signal polarity.
16.2.2.4 MDI/MDI-X Configuration
The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. This eliminates the need for cross-over cables when connecting to another device,
such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 452 for
additional details about these settings.
16.2.2.5 LED Indicators
The PHY supports two LED signals that can be used to indicate various states of operation of the
Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins
are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must
be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page
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163 for additional details. The function of these pins is programmable via the PHY layer MR23 register.
Refer to page 451 for additonal details on how to program these LED functions.
16.2.3 MAC Configuration/Operation
16.2.3.1 Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
16-3 on page 412.
Figure 16-3. Ethernet Frame
Preamble SFD Destination Address Source Address Length/
Type Data FCS
7
Bytes
6
Bytes
6
Bytes
2
Bytes
1
Byte
4
Bytes
46 - 1500
Bytes
The seven fields of the frame are transmitted from left to right. The bits within the frame are
transmitted from least to most significant bit.
■ Preamble
The Preamble field is used by the physical layer signaling circuitry to synchronize with the received
frame’s timing. The preamble is 7 octets long.
■ Start Frame Delimiter (SFD)
The SFD field follows the preamble pattern and indicates the start of the frame. Its value is
1010.1011.
■ Destination Address (DA)
This field specifies destination addresses for which the frame is intended. The LSB of the DA
determines whether the address is an individual (0), or group/multicast (1) address.
■ Source Address (SA)
The source address field identifies the station from which the frame was initiated.
■ Length/Type Field
The meaning of this field depends on its numeric value. The first of two octets is most significant.
This field can be interpreted as length or type code. The maximum length of the data field is
1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates
the number of MAC client data octets. If the value of this field is greater than or equal to 1536
decimal, then it is type interpretation. The meaning of the Length/Type field when the value is
between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes
type interpretation if the value of the Length/Type field is greater than 1500 decimal.
■ Data
The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values
can appear in this field. A minimum frame size is required to properly meet the IEEE standard.
If necessary, the data field is extended by appending extra bits (a pad). The pad field can have
a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets.
The MAC module automatically inserts pads if required, though it can be disabled by a register
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write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame
Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received
is too large to fit into the Ethernet Controller’s RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this
field is computed over destination address, source address, length/type, data, and pad fields
using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time.
For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by
the CRC bit in the MACTCTL register. For received frames, this field is automatically checked.
If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is
disabled by the BADCRC bit in the MACRCTL register.
16.2.3.2 MAC Layer FIFOs
For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes.
For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames,
up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO,
an overflow error will be indicated.
For details regarding the TX and RX FIFO layout, refer to Table 16-1 on page 413. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in
the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been
written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap
words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a
word boundary.
Table 16-1. TX & RX FIFO Organization
FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
1st 7:0 Data Length LSB Frame Length LSB
15:8 Data Length MSB Frame Length MSB
23:16 DA oct 1
31:24 DA oct 2
2nd 7:0 DA oct 3
15:8 DA oct 4
23:16 DA oct 5
31:24 DA oct 6
3rd 7:0 SA oct 1
15:8 SA oct 2
23:16 SA oct 3
31:24 SA oct 4
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FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
4th 7:0 SA oct 5
15:8 SA oct 6
23:16 Len/Type MSB
31:24 Len/Type LSB
5th to nth 7:0 data oct n
15:8 data oct n+1
23:16 data oct n+2
31:24 data oct n+3
FCS 1 (if the CRC bit in FCS 1
MACCTL is 0)
last 7:0
FCS 2 (if the CRC bit in FCS 2
MACCTL is 0)
15:8
FCS 3 (if the CRC bit in FCS 3
MACCTL is 0)
23:16
FCS 4 (if the CRC bit in FCS 4
MACCTL is 0)
31:24
16.2.3.3 Ethernet Transmission Options
The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS)
at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test
purposes, in order to generate a frame with an invalid CRC, this feature can be disabled.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload
data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by
the PADEN bit in the MACTCTL register.
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
16.2.3.4 Ethernet Reception Options
Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject
incoming Ethernet frames with an invalid FCS field.
The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS
and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames
with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and
MACIA1 register will be placed into the RX FIFO.
16.2.4 Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with no room in the RX FIFO (overrun)
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■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
16.3 Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0
bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller
for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value would be 4.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set
the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has
been cleared, the TX FIFO will be available for the next transmit frame.
7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin
reading the frame from the RX FIFO by using the MACDATA register. When the frame (including
the FCS field) has been read, the NPR field should decrement by one. When there are no more
frames in the RX FIFO, the NPR field will read 0.
16.4 Ethernet Register Map
Table 16-2 on page 416 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
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The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers and are detailed in Section
22.2.4 of the IEEE 802.3 specification. Table 16-2 on page 416 also lists these MII Management
registers. All addresses given are absolute and are written directly to the REGADR field of the
MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are
common to all PHY implementations. The only variance allowed is for features that may or may not
be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support
features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are
reserved.
Table 16-2. Ethernet Register Map
See
Offset Name Type Reset Description page
Ethernet MAC
0x000 MACRIS RO 0x0000.0000 Ethernet MAC Raw Interrupt Status 418
0x000 MACIACK W1C 0x0000.0000 Ethernet MAC Interrupt Acknowledge 420
0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 421
0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 422
0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 423
0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 424
0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 426
0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 427
0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 428
0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 429
0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 430
0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 431
0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 432
0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 433
0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 434
MII Management
- MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 435
- MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 437
Ethernet PHY Management Register 2 – PHY Identifier 439
- MR2 RO 0x000E 1
Ethernet PHY Management Register 3 – PHY Identifier 440
- MR3 RO 0x7237 2
Ethernet PHYManagement Register 4 – Auto-Negotiation 441
- MR4 R/W 0x01E1 Advertisement
Ethernet PHYManagement Register 5 – Auto-Negotiation 443
- MR5 RO 0x0000 Link Partner Base Page Ability
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See
Offset Name Type Reset Description page
Ethernet PHYManagement Register 6 – Auto-Negotiation 444
- MR6 RO 0x0000 Expansion
Ethernet PHY Management Register 16 – 445
- MR16 R/W 0x0140 Vendor-Specific
Ethernet PHY Management Register 17 – Interrupt 447
- MR17 R/W 0x0000 Control/Status
- MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 449
Ethernet PHY Management Register 19 – Transceiver 450
- MR19 R/W 0x4000 Control
Ethernet PHY Management Register 23 – LED 451
- MR23 R/W 0x0010 Configuration
Ethernet PHY Management Register 24 –MDI/MDIX 452
- MR24 R/W 0x00C0 Control
16.5 Ethernet MAC Register Descriptions
The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by
address offset. Also see “MII Management Register Descriptions” on page 434.
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Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000
The MACRIS register is the interrupt status register. On a read, this register gives the current status
value of the corresponding interrupt prior to masking.
Ethernet MAC Raw Interrupt Status (MACRIS)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occured. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
6 PHYINT RO 0x0
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
5 MDINT RO 0x0
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
4 RXER RO 0x0
FIFO Overrrun
When set, indicates that an overrun was encountered on the receive
FIFO.
3 FOV RO 0x0
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
2 TXEMP RO 0x0
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Bit/Field Name Type Reset Description
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
■ The data length field stored in the TX FIFO exceeds 2032. The
frame is not sent when this error occurs.
■ The retransmission attempts during the backoff process have
exceeded the maximum limit of 16.
1 TXER RO 0x0
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
0 RXINT RO 0x0
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Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000
A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet
MAC Raw Interrupt Status (MACRIS) register.
Ethernet MAC Interrupt Acknowledge (MACIACK)
Base 0x4004.8000
Offset 0x000
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Clear PHY Interrupt
A write of a 1 clears the PHYINT interrupt read from the MACRIS
register.
6 PHYINT W1C 0x0
Clear MII Transaction Complete
A write of a 1 clears the MDINT interrupt read from the MACRIS register.
5 MDINT W1C 0x0
Clear Receive Error
A write of a 1 clears the RXER interrupt read from the MACRIS register.
4 RXER W1C 0x0
Clear FIFO Overrun
A write of a 1 clears the FOV interrupt read from the MACRIS register.
3 FOV W1C 0x0
Clear Transmit FIFO Empty
A write of a 1 clears the TXEMP interrupt read from the MACRIS register.
2 TXEMP W1C 0x0
Clear Transmit Error
A write of a 1 clears the TXER interrupt read from the MACRIS register
and resets the TX FIFO write pointer.
1 TXER W1C 0x0
Clear Packet Received
A write of a 1 clears the RXINT interrupt read from the MACRIS register.
0 RXINT W1C 0x0
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Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the
interrupt, while writing a 1 enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Mask PHY Interrupt
This bit masks the PHYINT bit in the MACRIS register from being
asserted.
6 PHYINTM R/W 1
Mask MII Transaction Complete
This bit masks the MDINT bit in the MACRIS register from being
asserted.
5 MDINTM R/W 1
Mask Receive Error
This bit masks the RXER bit in the MACRIS register from being asserted.
4 RXERM R/W 1
Mask FIFO Overrrun
This bit masks the FOV bit in the MACRIS register from being asserted.
3 FOVM R/W 1
Mask Transmit FIFO Empty
This bit masks the TXEMP bit in the MACRIS register from being
asserted.
2 TXEMPM R/W 1
Mask Transmit Error
This bit masks the TXER bit in the MACRIS register from being asserted.
1 TXERM R/W 1
Mask Packet Received
This bit masks the RXINT bit in the MACRIS register from being
asserted.
0 RXINTM R/W 1
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Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register enables software to configure the receive module and control the types of frames that
are received from the physical medium. It is important to note that when the receive module is
enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address
field will be received and stored in the RX FIFO, even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RSTFIFO BADCRC PRMS AMUL RXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Clear Receive FIFO
When set, clears the receive FIFO. This should be done when software
initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), and then
the reset initiated (RSTFIFO = 1). This sequence will flush and reset the
RX FIFO.
4 RSTFIFO R/W 0x0
Enable Reject Bad CRC
The BADCRC bit enables the rejection of frames with an incorrectly
calculated CRC.
3 BADCRC R/W 0x1
Enable Promiscuous Mode
The PRMS bit enables Promiscuous mode, which accepts all valid frames,
regardless of the Destination Address.
2 PRMS R/W 0x0
Enable Multicast Frames
The AMUL bit enables the reception of multicast frames from the physical
medium.
1 AMUL R/W 0x0
Enable Receiver
The RXEN bit enables the Ethernet receiver. When this bit is Low, the
receiver is disabled and all frames on the physical medium are ignored.
0 RXEN R/W 0x0
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Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register enables software to configure the transmit module, and control frames are placed onto
the physical medium.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DUPLEX reserved CRC PADEN TXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Enable Duplex Mode
When set, enables Duplex mode, allowing simultaneous transmission
and reception.
4 DUPLEX R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0x0
Enable CRC Generation
When set, enables the automatic generation of the CRC and the
placement at the end of the packet. If this bit is not set, the frames placed
in the TX FIFO will be sent exactly as they are written into the FIFO.
2 CRC R/W 0x0
Enable Packet Padding
When set, enables the automatic padding of packets that do not meet
the minimum frame size.
1 PADEN R/W 0x0
Enable Transmitter
When set, enables the transmitter. When this bit is 0, the transmitter is
disabled.
0 TXEN R/W 0x0
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Register 6: Ethernet MAC Data (MACDATA), offset 0x010
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is then auto-incremented to the next TX FIFO location.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
Read-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Receive FIFO Data
The RXDATA bits represent the next four bytes of data stored in the RX
FIFO.
31:0 RXDATA RO 0x0
Write-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
Transmit FIFO Data
The TXDATA bits represent the next four bytes of data to place in the
TX FIFO for transmission.
31:0 TXDATA WO 0x0
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Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014
This register enables software to program the first four bytes of the hardware MAC address of the
Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 0 (MACIA0)
Base 0x4004.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACOCT4 MACOCT3
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT2 MACOCT1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
MAC Address Octet 4
The MACOCT4 bits represent the fourth octet of the MAC address used
to uniquely identify each Ethernet Controller.
31:24 MACOCT4 R/W 0x0
MAC Address Octet 3
The MACOCT3 bits represent the third octet of the MAC address used
to uniquely identify each Ethernet Controller.
23:16 MACOCT3 R/W 0x0
MAC Address Octet 2
The MACOCT2 bits represent the second octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT2 R/W 0x0
MAC Address Octet 1
The MACOCT1 bits represent the first octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT1 R/W 0x0
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Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT6 MACOCT5
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT6 R/W 0x0
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT5 R/W 0x0
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Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until
the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature.
Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When
THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in
the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight
writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to
be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission
starts when:
Number of Bytes >= 4 (THRESH x 8 + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is sent out on the physical medium. Because under-run checking is not performed, it is possible
that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate
values to be written to the physical medium rather than the end of the frame. Therefore, sufficient
bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register
must be set with an explicit write. This initiates the transmission of the frame even though the
threshold limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs.
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved THRESH
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds this value, transmission of the packet
begins.
5:0 THRESH R/W 0x3F
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Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description
of each of these registers can be found in Table 16-2 on page 416 and in “MII Management Register
Descriptions” on page 434.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
written with a 0 during the same cycle that the START bit is written with a 1.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written
with a 1 during the same cycle that the START bit is written with a 1.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved REGADR reserved WRITE START
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction.
7:3 REGADR R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x0
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation will be a write;
otherwise, it will be a read.
1 WRITE R/W 0x0
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When a 1 is written to this bit, the MII register
located at REGADR will be read (WRITE=0) or written (WRITE=1).
0 START R/W 0x0
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Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
Fmdc = Fipclk / (2 * (MACMDVR + 1 ))
The clock divider must be written with a value that ensures that the MDC clock will not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
Clock Divider
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY over the serial MII interface.
7:0 DIV R/W 0x80
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Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset
0x02C
This register holds the next value to be written to the MII Management registers.
Ethernet MAC Management Transmit Data (MACMTXD)
Base 0x4004.8000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDTX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Transmit Data
The MDTX bits represent the data that will be written in the next MII
management transaction.
15:0 MDTX R/W 0x0
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Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDRX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
15:0 MDRX R/W 0x0
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Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034
This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there
are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is
at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set.
Ethernet MAC Number of Packets (MACNP)
Base 0x4004.8000
Offset 0x034
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NPR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Number of Packets in Receive FIFO
The NPR bits represent the number of packets stored in the RX FIFO.
While the NPR field is greater than 0, the RXINT interrupt in the MACRIS
register will be asserted.
5:0 NPR RO 0x0
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Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX
FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NEWTX
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
0 NEWTX R/W 0x0
16.6 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 417.
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Register 16: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY. The default settings of these
registers are designed to initialize the PHY to a normal operational mode without configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Reset Registers
When set, resets the registers to their default state and reinitializes
internal state machines. Once the reset operation has completed, this
bit is cleared by hardware.
15 RESET R/W 0
Loopback Mode
When set, enables the Loopback mode of operation. The receive circuitry
is isolated from the physical medium and transmissions are sent back
through the receive circuitry instead of the medium.
14 LOOPBK R/W 0
Speed Select
1: Enables the 100 Mb/s mode of operation (100BASE-TX).
0: Enables the 10 Mb/s mode of operation (10BASE-T).
13 SPEEDSL R/W 1
Auto-Negotiation Enable
When set, enables the Auto-Negotiation process.
12 ANEGEN R/W 1
Power Down
When set, places the PHY into a low-power consuming state.
11 PWRDN R/W 0
Isolate
When set, isolates transmit and receive data paths and ignores all
signaling on these buses.
10 ISO R/W 0
Restart Auto-Negotiation
When set, restarts the Auto-Negotiation process. Once the restart has
initiated, this bit is cleared by hardware.
9 RANEG R/W 0
Set Duplex Mode
1: Enables the Full-Duplex mode of operation. This bit can be set by
software in a manual configuration process or by the Auto-Negotiation
process.
0: Enables the Half-Duplex mode of operation.
8 DUPLEX R/W 1
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Bit/Field Name Type Reset Description
Collision Test
When set, enables the Collision Test mode of operation. The COLT bit
asserts after the initiation of a transmission and de-asserts once the
transmission is halted.
7 COLT R/W 0
6:0 reserved R/W 0x00 Write as 0, ignore on read.
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Register 17: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY and perform its initialization
and operation appropriately.
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved 100X_F 100X_H 10T_F 10T_H reserved MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
100BASE-TX Full-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Full-Duplex mode.
14 100X_F RO 1
100BASE-TX Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Half-Duplex mode.
13 100X_H RO 1
10BASE-T Full-Duplex Mode
When set, indicates that the PHY is capable of 10BASE-T Full-Duplex
mode.
12 10T_F RO 1
10BASE-T Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 10BASE-T
Half-Duplex mode.
11 10T_H RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0
Management Frames with Preamble Suppressed
When set, indicates that the Management Interface is capable of
receiving management frames with the preamble suppressed.
6 MFPS RO 1
Auto-Negotiation Complete
When set, indicates that the Auto-Negotiation process has been
completed and that the extended registers defined by the
Auto-Negotiation protocol are valid.
5 ANEGC RO 0
Remote Fault
When set, indicates that a remote fault condition has been detected.
This bit remains set until it is read, even if the condition no longer exists.
4 RFAULT RC 0
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Bit/Field Name Type Reset Description
Auto-Negotiation
When set, indicates that the PHY has the ability to perform
Auto-Negotiation.
3 ANEGA RO 1
Link Made
When set, indicates that a valid link has been established by the PHY.
2 LINK RO 0
Jabber Condition
When set, indicates that a jabber condition has been detected by the
PHY. This bit remains set until it is read, even if the jabber condition no
longer exists.
1 JAB RC 0
Extended Capabilities
When set, indicates that the PHY provides an extended set of capabilities
that can be accessed through the extended register set.
0 EXTD RO 1
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Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2),
address 0x02
This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)
Base 0x4004.8000
Address 0x02
Type RO, reset 0x000E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[21:6]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[21:6]
This field, along with the OUI[5:0] field in MR3, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:0 OUI[21:6] RO 0x000E
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Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3),
address 0x03
This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)
Base 0x4004.8000
Address 0x03
Type RO, reset 0x7237
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[5:0] MN RN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[5:0]
This field, along with the OUI[21:6] field in MR2, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:10 OUI[5:0] RO 0x1C
Model Number
The MN field represents the Model Number of the PHY.
9:4 MN RO 0x23
Revision Number
The RN field represents the Revision Number of the PHY.
3:0 RN RO 0x7
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Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement (MR4), address 0x04
This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5
represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate
to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is
re-initiated.
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)
Base 0x4004.8000
Address 0x04
Type R/W, reset 0x01E1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP reserved RF reserved A3 A2 A1 A0 S[4:0]
Type RO RO R/W RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Next Page
When set, indicates the PHY is capable of Next Page exchanges to
provide more detailed information on the PHY’s capabilities.
15 NP RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
Remote Fault
When set, indicates to the link partner that a Remote Fault condition
has been encountered.
13 RF R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:9 reserved RO 0
Technology Ability Field[3]
When set, indicates that the PHY supports the 100Base-TX full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated with the
RANEG bit in the MR0 register.
8 A3 R/W 1
Technology Ability Field[2]
When set, indicates that the PHY supports the 100Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
7 A2 R/W 1
Technology Ability Field[1]
When set, indicates that the PHY supports the 10Base-T full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
6 A1 R/W 1
Technology Ability Field[0]
When set, indicates that the PHY supports the 10Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
5 A0 R/W 1
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Bit/Field Name Type Reset Description
Selector Field
The S[4:0] field encodes 32 possible messages for communicating
between PHYs. This field is hard-coded to 0x01, indicating that the
Stellaris® PHY is IEEE 802.3 compliant.
4:0 S[4:0] RO 0x01
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Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link
Partner Base Page Ability (MR5), address 0x05
This register provides the advertised abilities of the link partner’s PHY that are received and stored
during Auto-Negotiation.
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Base 0x4004.8000
Address 0x05
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP ACK RF A[7:0] S[4:0]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Next Page
When set, indicates that the link partner’s PHY is capable of Next page
exchanges to provide more detailed information on the PHY’s
capabilities.
15 NP RO 0
Acknowledge
When set, indicates that the device has successfully received the link
partner’s advertised abilities during Auto-Negotiation.
14 ACK RO 0
Remote Fault
Used as a standard transport mechanism for transmitting simple fault
information.
13 RF RO 0
Technology Ability Field
The A[7:0] field encodes individual technologies that are supported
by the PHY. See the MR4 register.
12:5 A[7:0] RO 0x00
Selector Field
The S[4:0] field encodes possible messages for communicating
between PHYs.
Value Description
0x00 Reserved
0x01 IEEE Std 802.3
0x02 IEEE Std 802.9 ISLAN-16T
0x03 IEEE Std 802.5
0x04 IEEE Std 1394
0x05–0x1F Reserved
4:0 S[4:0] RO 0x00
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Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion (MR6), address 0x06
This register enables software to determine the Auto-Negotiation and Next Page capabilities of the
PHY and the link partner after Auto-Negotiation.
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)
Base 0x4004.8000
Address 0x06
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDF LPNPA reserved PRX LPANEGA
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0x000
Parallel Detection Fault
When set, indicates that more than one technology has been detected
at link up. This bit is cleared when read.
4 PDF RC 0
Link Partner is Next Page Able
When set, indicates that the link partner is Next Page Able.
3 LPNPA RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x000
New Page Received
When set, indicates that a New Page has been received from the link
partner and stored in the appropriate location. This bit remains set until
the register is read.
1 PRX RC 0
Link Partner is Auto-Negotiation Able
When set, indicates that the Link partner is Auto-Negotiation Able.
0 LPANEGA RO 0
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Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the PHY.
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPTR INPOL reserved TXHIM SQEI NL10 reserved APOL RVSPOL reserved PCSBP RXCC
Type R/W R/W RO R/W R/W R/W RO RO RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Repeater Mode
When set, enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity. If the PHY is configured to 10Base-T mode, the SQE
test function is disabled.
15 RPTR R/W 0
Interrupt Polarity
1: Sets the polarity of the PHY interrupt to be active High.
0: Sets the polarity of the PHY interrupt to active Low.
Important: Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
14 INPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
Transmit High Impedance Mode
When set, enables the transmitter High Impedance mode. In this mode,
the TXOP and TXON transmitter pins are put into a high impedance state.
The RXIP and RXIN pins remain fully functional.
12 TXHIM R/W 0
SQE Inhibit Testing
When set, prohibits 10Base-T SQE testing.
When 0, the SQE testing is performed by generating a Collision pulse
following the completion of the transmission of a frame.
11 SQEI R/W 0
Natural Loopback Mode
When set, enables the 10Base-T Natural Loopback mode. This causes
the transmission data received by the PHY to be looped back onto the
receive data path when 10Base-T mode is enabled.
10 NL10 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:6 reserved RO 0x05
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Bit/Field Name Type Reset Description
Auto-Polarity Disable
When set, disables the PHY’s auto-polarity function.
If this bit is 0, the PHY automatically inverts the received signal due to
a wrong polarity connection during Auto-Negotiation if the PHY is in
10Base-T mode.
5 APOL R/W 0
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
a 1 in the RVSPOL bit indicates that the receive data is inverted while a
0 indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted while a 0 does not invert the receive data.
4 RVSPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
PCS Bypass
When set, enables the bypass of the PCS and scrambling/descrambling
functions in 100Base-TX mode. This mode is only valid when
Auto-Negotiation is disabled and 100Base-T mode is enabled.
1 PCSBP R/W 0
Receive Clock Control
When set, enables the Receive Clock Control power saving mode if the
PHY is configured in 100Base-TX mode. This mode shuts down the
receive clock when no data is being received from the physical medium
to save power. This mode should not be used when PCSBP is enabled
and is automatically disabled when the LOOPBK bit in the MR0 register
is set.
0 RXCC R/W 0
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Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events, which trigger a PHY
interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through
7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the
register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding
bit in the lower byte to signal a PHY interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INTRXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
Type R/W R/W R/W R/W R/W R/W R/W R/W RC RC RC RC RC RC RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Jabber Interrupt Enable
When set, enables system interrupts when a Jabber condition is detected
by the PHY.
15 JABBER_IE R/W 0
Receive Error Interrupt Enable
When set, enables system interrupts when a receive error is detected
by the PHY.
14 RXER_IE R/W 0
Page Received Interrupt Enable
When set, enables system interrupts when a new page is received by
the PHY.
13 PRX_IE R/W 0
Parallel Detection Fault Interrupt Enable
When set, enables system interrupts when a Parallel Detection Fault is
detected by the PHY.
12 PDF_IE R/W 0
LP Acknowledge Interrupt Enable
When set, enables system interrupts when FLP bursts are received with
the Acknowledge bit during Auto-Negotiation.
11 LPACK_IE R/W 0
Link Status Change Interrupt Enable
When set, enables system interrupts when the Link Status changes
from OK to FAIL.
10 LSCHG_IE R/W 0
Remote Fault Interrupt Enable
When set, enables system interrupts when a Remote Fault condition is
signaled by the link partner.
9 RFAULT_IE R/W 0
Auto-Negotiation Complete Interrupt Enable
When set, enables system interrupts when the Auto-Negotiation
sequence has completed successfully.
8 ANEGCOMP_IE R/W 0
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Bit/Field Name Type Reset Description
Jabber Event Interrupt
When set, indicates that a Jabber event has been detected by the
10Base-T circuitry.
7 JABBER_INT RC 0
Receive Error Interrupt
When set, indicates that a receive error has been detected by the PHY.
6 RXER_INT RC 0
Page Receive Interrupt
When set, indicates that a new page has been received from the link
partner during Auto-Negotiation.
5 PRX_INT RC 0
Parallel Detection Fault Interrupt
When set, indicates that a Parallel Detection Fault has been detected
by the PHY during the Auto-Negotiation process.
4 PDF_INT RC 0
LP Acknowledge Interrupt
When set, indicates that an FLP burst has been received with the
Acknowledge bit set during Auto-Negotiation.
3 LPACK_INT RC 0
Link Status Change Interrupt
When set, indicates that the link status has changed from OK to FAIL.
2 LSCHG_INT RC 0
Remote Fault Interrupt
When set, indicates that a Remote Fault condition has been signaled
by the link partner.
1 RFAULT_INT RC 0
Auto-Negotiation Complete Interrupt
When set, indicates that the Auto-Negotiation sequence has completed
successfully.
0 ANEGCOMP_INT RC 0
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Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous Auto-Negotiation.
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ANEGF DPLX RATE RXSD RX_LOCK reserved
Type RO RO RO RC RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
Auto-Negotiation Failure
When set, indicates that no common technology was found during
Auto-Negotiation and has failed. This bit remains set until read.
12 ANEGF RC 0
Duplex Mode
When set, indicates that Full-Duplex was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
11 DPLX RO 0
Rate
When set, indicates that 100Base-TX was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
10Base-TX was the highest common denominator found.
10 RATE RO 0
Receive Detection
When set, indicates that receive signal detection has occurred (in
100Base-TX mode) or that Manchester-encoded data has been detected
(in 10Base-T mode).
9 RXSD RO 0
Receive PLL Lock
When set, indicates that the Receive PLL has locked onto the receive
signal for the selected speed of operation (10Base-T or 100Base-TX).
8 RX_LOCK RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 00
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Register 26: Ethernet PHY Management Register 19 – Transceiver Control
(MR19), address 0x13
This register enables software to set the gain of the transmit output to compensate for transformer
loss.
Ethernet PHY Management Register 19 – Transceiver Control (MR19)
Base 0x4004.8000
Address 0x13
Type R/W, reset 0x4000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXO[1:0] reserved
Type R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Transmit Amplitude Selection
The TXO[1:0] field sets the transmit output amplitude to account for
transmit transformer insertion loss.
Value Description
0x0 Gain set for 0.0dB of insertion loss
0x1 Gain set for 0.4dB of insertion loss
0x2 Gain set for 0.8dB of insertion loss
0x3 Gain set for 1.2dB of insertion loss
15:14 TXO[1:0] R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13:0 reserved RO 0x0
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Register 27: Ethernet PHY Management Register 23 – LED Configuration
(MR23), address 0x17
This register enables software to select the source that will cause the LEDs to toggle.
Ethernet PHY Management Register 23 – LED Configuration (MR23)
Base 0x4004.8000
Address 0x17
Type R/W, reset 0x0010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LED1[3:0] LED0[3:0]
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
LED1 Source
The LED1 field selects the source that will toggle the LED1 signal.
Value Description
0x0 Link OK
0x1 RX or TX Activity (Default LED1)
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
7:4 LED1[3:0] R/W 1
LED0 Source
The LED0 field selects the source that will toggle the LED0 signal.
Value Description
0x0 Link OK (Default LED0)
0x1 RX or TX Activity
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
3:0 LED0[3:0] R/W 0
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Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PD_MODEAUTO_SW MDIX MDIX_CM MDIX_SD
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when Auto-Negotiation is not enabled.
7 PD_MODE R/W 0
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
6 AUTO_SW R/W 0
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
5 MDIX R/W 0
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
4 MDIX_CM RO 0
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
3:0 MDIX_SD R/W 0
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17 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6952 controller provides three independent integrated analog comparators that can be
configured to drive an output or generate an interrupt or ADC event.
Note: Not all comparators have the option to drive an output pin. See the Comparator Operating
Mode tables for more information.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
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17.1 Block Diagram
Figure 17-1. Analog Comparator Module Block Diagram
interrupt
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
interrupt
C1-
C1+ output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
C1o
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
interrupt
C0-
C0o
trigger trigger
trigger trigger
trigger trigger
17.2 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 17-2 on page 455, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
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Figure 17-2. Structure of Comparator Unit
ACCTL ACSTAT
IntGen
2 TrigGen
1
0
CINV
output
-ve input
+ve input
interrupt
internal
bus
trigger
+ve input (alternate)
reference input
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the
comparators are shown in the Comparator Operating Mode tables.
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin or generate an analog-to-digital converter (ADC) trigger.
Important: Certain register bit values must be set before using the analog comparators. The proper
pad configuration for the comparator input and output pins are described in the
Comparator Operating Mode tables.
Table 17-1. Comparator 0 Operating Modes
ACCNTL0 Comparator 0
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C0- C0+ C0o yes yes
01 C0- C0+ C0o yes yes
10 C0- Vref C0o yes yes
11 C0- reserved C0o yes yes
Table 17-2. Comparator 1 Operating Modes
ACCNTL1 Comparator 1
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C1- C1o/C1+ C1o/C1+ yes yes
01 C1- C0+ C1o/C1+ yes yes
10 C1- Vref C1o/C1+ yes yes
11 C1- reserved C1o/C1+ yes yes
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Table 17-3. Comparator 2 Operating Modes
ACCNTL2 Comparator 2
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C2- C2+ n/a yes yes
01 C2- C0+ n/a yes yes
10 C2- Vref n/a yes yes
11 C2- reserved n/a yes yes
17.2.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 17-3 on page 456. This is controlled by a
single configuration register (ACREFCTL). Table 17-4 on page 456 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 17-3. Comparator Internal Reference Structure
8R R R
8R
R R
•••
•••
0
Decoder
15 14 1
AVDD
EN
internal
reference
VREF
RNG
Table 17-4. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0
for the least noisy ground reference.
EN=0 RNG=X
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ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
Total resistance in ladder is 32 R.
VREF AVDD
R V REF
RT
= × ----------------
VREF AVDD
(VREF + 8)
32
= × ------------------------------
VR EF = 0.825 + 0.103 VREF
The range of internal reference in this mode is 0.825-2.37 V.
EN=1 RNG=0
Total resistance in ladder is 24 R.
VREF AVDD
R V REF
RT
= × ----------------
VREF AVDD
(VREF)
24
= × --------------------
VREF = 0.1375 x VREF
The range of internal reference for this mode is 0.0-2.0625 V.
RNG=1
17.3 Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output on the
C0o pin by writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
17.4 Register Map
Table 17-5 on page 458 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
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Table 17-5. Analog Comparators Register Map
See
Offset Name Type Reset Description page
0x00 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 459
0x04 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 460
0x08 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 461
0x10 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 462
0x20 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 463
0x24 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 464
0x40 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 463
0x44 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 464
0x60 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 463
0x64 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 464
17.5 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x00
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
2 IN2 R/W1C 0
Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
1 IN1 R/W1C 0
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0 IN0 R/W1C 0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x04
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
2.
2 IN2 RO 0
Comparator 1 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
1.
1 IN1 RO 0
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
0 IN0 RO 0
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x08
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Enable
When set, enables the controller interrupt from the comparator 2 output
2 IN2 R/W 0
Comparator 1 Interrupt Enable
When set, enables the controller interrupt from the comparator 1 output.
1 IN1 R/W 0
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
0 IN0 R/W 0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x10
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EN RNG reserved VREF
Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
9 EN R/W 0
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 32 R. If 1, the resistor ladder has a total
resistance of 24 R.
8 RNG R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x00
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
17-4 on page 456 for some output reference voltage examples.
3:0 VREF R/W 0x00
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x20
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OVAL reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
1 OVAL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TOEN ASRCP reserved TSLVAL TSEN ISLVAL ISEN CINV reserved
Type RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Trigger Output Enable
The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.
11 TOEN R/W 0
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved
10:9 ASRCP R/W 0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8 reserved RO 0
Trigger Sense Level Value
The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.
7 TSLVAL R/W 0
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Bit/Field Name Type Reset Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Function
0x0 Level sense, see TSLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
6:5 TSEN R/W 0x0
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
4 ISLVAL R/W 0
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
3:2 ISEN R/W 0x0
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
1 CINV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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18 Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The Stellaris® PWM module consists of two PWM generator blocks and a control block. Each PWM
generator block contains one timer (16-bit down or up/down counter), two PWM comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals
(other than being based on the same timer and therefore having the same frequency) or a single
pair of complementary signals with dead-band delays inserted. The output of the PWM generation
blocks are managed by the output control block before being passed to the device pins.
The Stellaris® PWM module provides a great deal of flexibility. It can generate simple PWM signals,
such as those required by a simple charge pump. It can also generate paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver.
18.1 Block Diagram
Figure 18-1 on page 466 provides a block diagram of a Stellaris® PWM module. The LM3S6952
controller contains two generator blocks (PWM0 and PWM1) and generates four independent PWM
signals or two paired PWM signals with dead-band delays inserted.
Figure 18-1. PWM Module Block Diagram
Interrupt and
Trigger Generate
PWMnINTEN
PWMnRIS
PWMnISC
PWM Clock
Interrupt
Dead-Band
Generator
PWMnDBCTL
PWMnDBRISE
PWMnDBFALL
PWM Output
Control
PWMENABLE
PWMINVERT
PWMFAULT
PWM
Generator
PWMnGENA
PWMnGENB
pwma
pwmb
Timer
PWMnLOAD
PWMnCOUNT
Comparator A
PWMnCMPA
Comparator B
PWMnCMPB
zero
load
dir
16
cmpA
cmpB
Fault
PWM Generator Block
18.2 Functional Description
18.2.1 PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
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is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse.
18.2.2 PWM Comparators
There are two comparators in each PWM generator that monitor the value of the counter; when
either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down
mode, these comparators match both when counting up and when counting down; they are therefore
qualified by the counter direction signal. These qualified pulses are used in the PWM generation
process. If either comparator match value is greater than the counter load value, then that comparator
never outputs a High pulse.
Figure 18-2 on page 467 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 18-3 on page 468 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode.
Figure 18-2. PWM Count-Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
ADown
BDown
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Figure 18-3. PWM Count-Up/Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
BUp
AUp ADown
BDown
18.2.3 PWM Signal Generator
The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM
signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load,
match A down, and match B down. In Count-Up/Down mode, there are six events that can affect
the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match
A or match B events are ignored when they coincide with the zero or load events. If the match A
and match B events coincide, the first signal, PWMA, is generated based only on the match A event,
and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 18-4 on page 468 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.
Figure 18-4. PWM Generation Example In Count-Up/Down Mode
Load
Zero
CompB
CompA
PWMB
PWMA
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
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changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.
18.2.4 Dead-Band Generator
The two PWM signals produced by the PWM generator are passed to the dead-band generator. If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal
is the input signal with the rising edge delayed by a programmable amount. The second output
PWM signal is the inversion of the input signal with a programmable delay added between the falling
edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a programmable
amount of time at transitions where both are Low. These signals are therefore suitable for driving
a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the
power electronics. Figure 18-5 on page 469 shows the effect of the dead-band generator on an input
PWM signal.
Figure 18-5. PWM Dead-Band Generator
Input
PWMA
PWMB
Rising Edge
Delay
Falling Edge
Delay
18.2.5 Interrupt/ADC-Trigger Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
within the PWM signal. Note that interrupts and ADC triggers are based on the raw events; delays
in the PWM signal edges caused by the dead-band generator are not taken into account.
18.2.6 Synchronization Methods
There is a global reset capability that can synchronously reset any or all of the counters in the PWM
generators. If multiple PWM generators are configured with the same counter load value, this can
be used to guarantee that they also have the same count value (this does imply that the PWM
generators must be configured before they are synchronized). With this, more than two PWM signals
can be produced with a known relationship between the edges of those signals since the counters
always have the same values.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly
short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global synchronized
update signal is asserted, at which point the new value is used as soon as the counter reaches
zero. This second mode allows multiple items in multiple PWM generators to be updated
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simultaneously without odd effects during the update; everything runs from the old values until a
point at which they all run from the new values. The Update mode of the load and comparator match
values can be individually configured in each PWM generator block. It typically makes sense to use
the synchronous update mechanism across PWM generator blocks when the timers in those blocks
are synchronized, though this is not required in order for this mechanism to function properly.
18.2.7 Fault Conditions
There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interrupt.
Each PWM generator can also be configured to stop counting during a stall condition. The user can
select for the counters to run until they reach zero then stop, or to continue counting and reloading.
A stall condition does not generate a controller interrupt.
18.2.8 Output Control Block
With each PWM generator block producing two raw PWM signals, the output control block takes
care of the final conditioning of the PWM signals before they go to the pins. Via a single register,
the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for
example, to perform commutation of a brushless DC motor with a single register write (and without
modifying the individual PWM generators, which are modified by the feedback control loop). Similarly,
fault control can disable any of the PWM signals as well. A final inversion can be applied to any of
the PWM signals, making them active Low instead of the default active High.
18.3 Initialization and Configuration
The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes
the system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
5. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
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■ Write the PWM0GENB register with a value of 0x0000.080C.
6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field
in the PWM0LOAD register to the requested period minus one.
■ Write the PWM0LOAD register with a value of 0x0000.018F.
7. Set the pulse width of the PWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
8. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
9. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
10. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
18.4 Register Map
Table 18-1 on page 471 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000.
Table 18-1. PWM Register Map
See
Offset Name Type Reset Description page
0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 473
0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 474
0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 475
0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 476
0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 477
0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 478
0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 479
0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 480
0x020 PWMSTATUS RO 0x0000.0000 PWM Status 481
0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 482
0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt and Trigger Enable 484
0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 486
0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 487
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See
Offset Name Type Reset Description page
0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 488
0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 489
0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 490
0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 491
0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 492
0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 495
0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 498
0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 499
0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 500
0x080 PWM1CTL R/W 0x0000.0000 PWM1 Control 482
0x084 PWM1INTEN R/W 0x0000.0000 PWM1 Interrupt and Trigger Enable 484
0x088 PWM1RIS RO 0x0000.0000 PWM1 Raw Interrupt Status 486
0x08C PWM1ISC R/W1C 0x0000.0000 PWM1 Interrupt Status and Clear 487
0x090 PWM1LOAD R/W 0x0000.0000 PWM1 Load 488
0x094 PWM1COUNT RO 0x0000.0000 PWM1 Counter 489
0x098 PWM1CMPA R/W 0x0000.0000 PWM1 Compare A 490
0x09C PWM1CMPB R/W 0x0000.0000 PWM1 Compare B 491
0x0A0 PWM1GENA R/W 0x0000.0000 PWM1 Generator A Control 492
0x0A4 PWM1GENB R/W 0x0000.0000 PWM1 Generator B Control 495
0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 498
0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 499
0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 500
18.5 Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
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Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GlobalSync1 GlobalSync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Update PWM Generator 1
Same as GlobalSync0 but for PWM generator 1.
1 GlobalSync1 R/W 0
Update PWM Generator 0
Setting this bit causes any queued update to a load or comparator
register in PWM generator 0 to be applied the next time the
corresponding counter becomes zero. This bit automatically clears when
the updates have completed; it cannot be cleared by software.
0 GlobalSync0 R/W 0
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Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing
multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred;
reading them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Sync1 Sync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Reset Generator 1 Counter
Performs a reset of the PWM generator 1 counter.
1 Sync1 R/W 0
Reset Generator 0 Counter
Performs a reset of the PWM generator 0 counter.
0 Sync0 R/W 0
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Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example, when the time bases
are synchronized) without driving PWM signals to the pins. When bits in this register are set, the
corresponding PWM signal is passed through to the output stage, which is controlled by the
PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is
also passed to the output stage.
PWM Output Enable (PWMENABLE)
Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM3En PWM2En PWM1En PWM0En
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
PWM3 Output Enable
When set, allows the generated PWM3 signal to be passed to the device
pin.
3 PWM3En R/W 0
PWM2 Output Enable
When set, allows the generated PWM2 signal to be passed to the device
pin.
2 PWM2En R/W 0
PWM1 Output Enable
When set, allows the generated PWM1 signal to be passed to the device
pin.
1 PWM1En R/W 0
PWM0 Output Enable
When set, allows the generated PWM0 signal to be passed to the device
pin.
0 PWM0En R/W 0
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Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM3Inv PWM2Inv PWM1Inv PWM0Inv
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Invert PWM3 Signal
When set, the generated PWM3 signal is inverted.
3 PWM3Inv R/W 0
Invert PWM2 Signal
When set, the generated PWM2 signal is inverted.
2 PWM2Inv R/W 0
Invert PWM1 Signal
When set, the generated PWM1 signal is inverted.
1 PWM1Inv R/W 0
Invert PWM0 Signal
When set, the generated PWM0 signal is inverted.
0 PWM0Inv R/W 0
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Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault input and debug events are considered fault conditions. On a fault condition, each PWM signal
can either be passed through unmodified or driven Low. For outputs that are configured for
pass-through, the debug event handling on the corresponding PWM generator also determines if
the PWM signal continues to be generated.
Fault condition control happens before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault3 Fault2 Fault1 Fault0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
PWM3 Driven Low on Fault
When set, the PWM3 output signal is driven Low on a fault condition.
3 Fault3 R/W 0
PWM2 Driven Low on Fault
When set, the PWM2 output signal is driven Low on a fault condition.
2 Fault2 R/W 0
PWM1 Driven Low on Fault
When set, the PWM1 output signal is driven Low on a fault condition.
1 Fault1 R/W 0
PWM0 Driven Low on Fault
When set, the PWM0 output signal is driven Low on a fault condition.
0 Fault0 R/W 0
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Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Enable
When 1, an interrupt occurs when the fault input is asserted.
16 IntFault R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2 reserved RO 0x00
PWM1 Interrupt Enable
When 1, an interrupt occurs when the PWM generator 1 block asserts
an interrupt.
1 IntPWM1 R/W 0
PWM0 Interrupt Enable
When 1, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.
0 IntPWM0 R/W 0
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Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 480).
The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared
via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that
are active; a zero bit indicates that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates that the fault input has been asserted.
16 IntFault RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2 reserved RO 0x00
PWM1 Interrupt Asserted
Indicates that the PWM generator 1 block is asserting its interrupt.
1 IntPWM1 RO 0
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
0 IntPWM0 RO 0
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Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. A
bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual
interrupt status registers in each block must be consulted to determine the reason for the interrupt,
and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched
interrupt status.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates if the fault input is asserting an interrupt.
16 IntFault R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2 reserved RO 0x00
PWM1 Interrupt Status
Indicates if the PWM generator 1 block is asserting an interrupt.
1 IntPWM1 RO 0
PWM0 Interrupt Status
Indicates if the PWM generator 0 block is asserting an interrupt.
0 IntPWM0 RO 0
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Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the status of the Fault input signal.
PWM Status (PWMSTATUS)
Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Fault Interrupt Status
When set to 1, indicates the fault input is asserted.
0 Fault RO 0
November 30, 2007 481
Preliminary
LM3S6952 Microcontroller
Register 10: PWM0 Control (PWM0CTL), offset 0x040
Register 11: PWM1 Control (PWM1CTL), offset 0x080
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, and the PWM1 block produces the
PWM2 and PWM3 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CmpBUpdCmpAUpd LoadUpd Debug Mode Enable
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
5 CmpBUpd R/W 0
Comparator A Update Mode
The Update mode for the comparator A register. If 0, updates to the
register are reflected to the comparator the next time the counter is 0.
If 1, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register (see page 473).
4 CmpAUpd R/W 0
Load Register Update Mode
The Update mode for the load register. If 0, updates to the register are
reflected to the counter the next time the counter is 0. If 1, updates to
the register are delayed until the next time the counter is 0 after a
synchronous update has been requested through the PWM Master
Control (PWMCTL) register.
3 LoadUpd R/W 0
Debug Mode
The behavior of the counter in Debug mode. If 0, the counter stops
running when it next reaches 0, and continues running again when no
longer in Debug mode. If 1, the counter always runs.
2 Debug R/W 0
482 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Counter Mode
The mode for the counter. If 0, the counter counts down from the load
value to 0 and then wraps back to the load value (Count-Down mode).
If 1, the counter counts up from 0 to the load value, back down to 0, and
then repeats (Count-Up/Down mode).
1 Mode R/W 0
PWM Block Enable
Master enable for the PWM generation block. If 0, the entire block is
disabled and not clocked. If 1, the block is enabled and produces PWM
signals.
0 Enable R/W 0
November 30, 2007 483
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LM3S6952 Microcontroller
Register 12: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 13: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interruptor an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified.
PWM0 Interrupt and Trigger Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
Trigger for Counter=Comparator B Down
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting down.
13 TrCmpBD R/W 0
Trigger for Counter=Comparator B Up
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting up.
12 TrCmpBU R/W 0
Trigger for Counter=Comparator A Down
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting down.
11 TrCmpAD R/W 0
484 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Trigger for Counter=Comparator A Up
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting up.
10 TrCmpAU R/W 0
Trigger for Counter=Load
When 1, a trigger pulse is output when the counter matches the
PWMnLOAD register.
9 TrCntLoad R/W 0
Trigger for Counter=0
When 1, a trigger pulse is output when the counter is 0.
8 TrCntZero R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
Interrupt for Counter=Comparator B Down
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting down.
5 IntCmpBD R/W 0
Interrupt for Counter=Comparator B Up
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting up.
4 IntCmpBU R/W 0
Interrupt for Counter=Comparator A Down
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting down.
3 IntCmpAD R/W 0
Interrupt for Counter=Comparator A Up
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting up.
2 IntCmpAU R/W 0
Interrupt for Counter=Load
When 1, an interrupt occurs when the counter matches the PWMnLOAD
register.
1 IntCntLoad R/W 0
Interrupt for Counter=0
When 1, an interrupt occurs when the counter is 0.
0 IntCntZero R/W 0
November 30, 2007 485
Preliminary
LM3S6952 Microcontroller
Register 14: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 15: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). Bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that
the event in question has not occurred.
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt Status
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD RO 0
Comparator B Up Interrupt Status
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU RO 0
Comparator A Down Interrupt Status
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD RO 0
Comparator A Up Interrupt Status
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU RO 0
Counter=Load Interrupt Status
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad RO 0
Counter=0 Interrupt Status
Indicates that the counter has matched 0.
0 IntCntZero RO 0
486 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 16: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 17: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; a 0 bit indicates that the event in question has not occurred. These are R/W1C
registers; writing a 1 to a bit position clears the corresponding interrupt reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD R/W1C 0
Comparator B Up Interrupt
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU R/W1C 0
Comparator A Down Interrupt
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD R/W1C 0
Comparator A Up Interrupt
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU R/W1C 0
Counter=Load Interrupt
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad R/W1C 0
Counter=0 Interrupt
Indicates that the counter has matched 0.
0 IntCntZero R/W1C 0
November 30, 2007 487
Preliminary
LM3S6952 Microcontroller
Register 18: PWM0 Load (PWM0LOAD), offset 0x050
Register 19: PWM1 Load (PWM1LOAD), offset 0x090
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter
after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero.
If the Load Value Update mode is immediate, this value is used the next time the counter reaches
zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 473).
If this register is re-written before the actual update occurs, the previous value is never used and is
lost.
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Load Value
The counter load value.
15:0 Load R/W 0
488 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 20: PWM0 Counter (PWM0COUNT), offset 0x054
Register 21: PWM1 Counter (PWM1COUNT), offset 0x094
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches the load register, a pulse is output;
this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see
page 492 and page 495) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see
page 484). A pulse with the same capabilities is generated when this value is zero.
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Value
The current value of the counter.
15:0 Count RO 0x00
November 30, 2007 489
Preliminary
LM3S6952 Microcontroller
Register 22: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 23: PWM1 Compare A (PWM1CMPA), offset 0x098
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register (see page 488), then no pulse is ever output.
If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),
then this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 473). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare A (PWM0CMPA)
Base 0x4002.8000
Offset 0x058
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator A Value
The value to be compared against the counter.
15:0 CompA R/W 0x00
490 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 24: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 25: PWM1 Compare B (PWM1CMPB), offset 0x09C
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register, then no pulse is ever output.
IF the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL
register), then this 16-bit CompB value is used the next time the counter reaches zero. If the update
mode is synchronous, it is used the next time the counter reaches zero after a synchronous update
has been requested through the PWM Master Control (PWMCTL) register (see page 473). If this
register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompB
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator B Value
The value to be compared against the counter.
15:0 CompB R/W 0x00
November 30, 2007 491
Preliminary
LM3S6952 Microcontroller
Register 26: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 27: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
These registers control the generation of the PWMnA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that
is produced.
The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
PWM0 Generator A Control (PWM0GENA)
Base 0x4002.8000
Offset 0x060
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
492 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 482) is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
November 30, 2007 493
Preliminary
LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is zero.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
494 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 28: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 29: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
These registers control the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These
events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
November 30, 2007 495
Preliminary
LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
496 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is 0.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
November 30, 2007 497
Preliminary
LM3S6952 Microcontroller
Register 30: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 31: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1
signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through
to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and
inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by
delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see
page 499), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by
the value in the PWM0DBFALL register (see page 500). In a similar manner, PWM2 and PWM3 are
produced from the PWM1A and PWM1B signals.
PWM0 Dead-Band Control (PWM0DBCTL)
Base 0x4002.8000
Offset 0x068
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Enable
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Dead-Band Generator Enable
When set, the dead-band generator inserts dead bands into the output
signals; when clear, it simply passes the PWM signals through.
0 Enable R/W 0
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Pulse Width Modulator (PWM)
Register 32: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 33: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RiseDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
11:0 RiseDelay R/W 0
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Register 34: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 35: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FallDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Fall Delay
The number of clock ticks to delay the falling edge.
11:0 FallDelay R/W 0x00
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Pulse Width Modulator (PWM)
19 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris® quadrature encoder interface (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
The Stellaris® quadrature encoder has the following features:
■ Position integrator that tracks the encoder position
■ Velocity capture using built-in timer
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
19.1 Block Diagram
Figure 19-1 on page 501 provides a block diagram of a Stellaris® QEI module.
Figure 19-1. QEI Block Diagram
Quadrature
Encoder
Velocity
Predivider
Interrupt Control
QEIINTEN
QEIRIS
QEIISC
Position Integrator
QEIMAXPOS
QEIPOS
Velocity Accumulator
QEICOUNT
QEISPEED
Velocity Timer
QEILOAD
QEITIME
PhA
PhB
IDX
clk
dir
Interrupt
Control & Status
QEICTL
QEISTAT
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19.2 Functional Description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA
and PhB, can be swapped before being interpreted by the QEI module to change the meaning of
forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see
page 506).
When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the
capture mode for the position integrator can be set to update the position counter on every edge of
the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on
every PhA and PhB provides more positional resolution at the cost of less range in the positional
counter.
When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB
lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is
seen on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI
Control (QEICTL) register.
When ResMode is 0, the positional counter is reset when the index pulse is sensed. This limits the
positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution
of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse
direction from position 0 can move the position counter to N-1. In this mode, the position register
contains the absolute position of the encoder relative to the index (or home) position once an index
pulse has been seen.
When ResMode is 1, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
The velocity capture has a configurable timer and a count register. It counts the number of phase
edges (using the same configuration as for the position integrator) in a given time period. The edge
count from the previous time period is available to the controller via the QEISPEED register, while
the edge count for the current time period is being accumulated in the QEICOUNT register. As soon
as the current time period is complete, the total number of edges counted in that time period is made
available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and
counting commences on a new time period. The number of edges counted in a given time period
is directly proportional to the velocity of the encoder.
Figure 19-2 on page 503 shows how the Stellaris® quadrature encoder converts the phase input
signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide
by 4 mode).
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Figure 19-2. Quadrature Encoder and Velocity Predivider Operation
-1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1 +1 +1 +1 +1 +1 +1 +1
PhA
PhB
clk
clkdiv
dir
pos
rel
The period of the timer is configurable by specifying the load value for the timer in the QEILOAD
register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the
timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer
timer period is needed to be able to capture enough edges to have a meaningful result. At higher
encoder speeds, both a shorter timer period and/or the velocity predivider can be used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and
4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
÷1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation since intermediate values may exceed the capacity
of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could
be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if
they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled
by the ÷4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation, as well as reducing the processing requirement of computing
this equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a
load value must be selected such that the product is very close to a power of two. For example, a
100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor,
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which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the
divide in most cases. If absolute accuracy were required, the controller’s divide instruction could be
used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
19.3 Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there
are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the
count is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
5. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
6. Delay for some time.
7. Read the encoder position by reading the QEIPOS register value.
19.4 Register Map
Table 19-1 on page 504 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
Table 19-1. QEI Register Map
See
Offset Name Type Reset Description page
0x000 QEICTL R/W 0x0000.0000 QEI Control 506
0x004 QEISTAT RO 0x0000.0000 QEI Status 508
0x008 QEIPOS R/W 0x0000.0000 QEI Position 509
0x00C QEIMAXPOS R/W 0x0000.0000 QEI Maximum Position 510
0x010 QEILOAD R/W 0x0000.0000 QEI Timer Load 511
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See
Offset Name Type Reset Description page
0x014 QEITIME RO 0x0000.0000 QEI Timer 512
0x018 QEICOUNT RO 0x0000.0000 QEI Velocity Counter 513
0x01C QEISPEED RO 0x0000.0000 QEI Velocity 514
0x020 QEIINTEN R/W 0x0000.0000 QEI Interrupt Enable 515
0x024 QEIRIS RO 0x0000.0000 QEI Raw Interrupt Status 516
0x028 QEIISC R/W1C 0x0000.0000 QEI Interrupt Status and Clear 517
19.5 Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
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Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
Type RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x00
Stall QEI
When set, the QEI stalls when the microcontroller asserts Halt.
12 STALLEN R/W 0
Invert Index Pulse
When set , the input Index Pulse is inverted.
11 INVI R/W 0
Invert PhB
When set, the PhB input is inverted.
10 INVB R/W 0
Invert PhA
When set, the PhA input is inverted.
9 INVA R/W 0
Predivide Velocity
A predivider of the input quadrature pulses before being applied to the
QEICOUNT accumulator. This field can be set to the following values:
Value Predivider
0x0 ÷1
0x1 ÷2
0x2 ÷4
0x3 ÷8
0x4 ÷16
0x5 ÷32
0x6 ÷64
0x7 ÷128
8:6 VelDiv R/W 0x0
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Bit/Field Name Type Reset Description
Capture Velocity
When set, enables capture of the velocity of the quadrature encoder.
5 VelEn R/W 0
Reset Mode
The Reset mode for the position counter. When 0, the position counter
is reset when it reaches the maximum; when 1, the position counter is
reset when the index pulse is captured.
4 ResMode R/W 0
Capture Mode
The Capture mode defines the phase edges that are counted in the
position. When 0, only the PhA edges are counted; when 1, the PhA
and PhB edges are counted, providing twice the positional resolution
but half the range.
3 CapMode R/W 0
Signal Mode
When 1, the PhA and PhB signals are clock and direction; when 0, they
are quadrature phase signals.
2 SigMode R/W 0
Swap Signals
Swaps the PhA and PhB signals.
1 Swap R/W 0
Enable QEI
Enables the quadrature encoder module.
0 Enable R/W 0
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Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
QEI0 base: 0x4002.C000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Direction Error
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Direction of Rotation
Indicates the direction the encoder is rotating.
The Direction values are defined as follows:
Value Description
0 Forward rotation
1 Reverse rotation
1 Direction RO 0
Error Detected
Indicates that an error was detected in the gray code sequence (that is,
both signals changing at the same time).
0 Error RO 0
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Quadrature Encoder Interface (QEI)
Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. Its value is updated by inputs on
the QEI phase inputs, and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
QEI0 base: 0x4002.C000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Position
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Position
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Current Position Integrator Value
The current value of the position integrator.
31:0 Position R/W 0x00
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Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving backward, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
QEI0 base: 0x4002.C000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MaxPos
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MaxPos
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Maximum Position Integrator Value
The maximum value of the position integrator.
31:0 MaxPos R/W 0x00
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Quadrature Encoder Interface (QEI)
Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Since this value is loaded into the timer
the clock cycle after the timer is zero, this value should be one less than the number of clocks in
the desired period. So, for example, to have 2000 clocks per timer period, this register should contain
1999.
QEI Timer Load (QEILOAD)
QEI0 base: 0x4002.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Timer Load Value
The load value for the velocity timer.
31:0 Load R/W 0x00
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Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
VelEn in QEICTL is 0.
QEI Timer (QEITIME)
QEI0 base: 0x4002.C000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Time
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Time
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Timer Current Value
The current value of the velocity timer.
31:0 Time RO 0x00
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Quadrature Encoder Interface (QEI)
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Since this is
a running total, the time period to which it applies cannot be known with precision (that is, a read of
this register does not necessarily correspond to the time returned by the QEITIME register since
there is a small window of time between the two reads, during which time either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when VelEn in
QEICTL is 0.
QEI Velocity Counter (QEICOUNT)
QEI0 base: 0x4002.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
31:0 Count RO 0x00
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Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when VelEn in QEICTL is 0.
QEI Velocity (QEISPEED)
QEI0 base: 0x4002.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Speed
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Speed
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity
The measured speed of the quadrature encoder in pulses per period.
31:0 Speed RO 0x00
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Quadrature Encoder Interface (QEI)
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
3 IntError R/W 0
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
2 IntDir R/W 0
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
1 IntTimer R/W 0
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
0 IntIndex R/W 0
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Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
Offset 0x024
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Detected
Indicates that a phase error was detected.
3 IntError RO 0
Direction Change Detected
Indicates that the direction has changed.
2 IntDir RO 0
Velocity Timer Expired
Indicates that the velocity timer has expired.
1 IntTimer RO 0
Index Pulse Asserted
Indicates that the index pulse has occurred.
0 IntIndex RO 0
516 November 30, 2007
Preliminary
Quadrature Encoder Interface (QEI)
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
Offset 0x028
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Interrupt
Indicates that a phase error was detected.
3 IntError R/W1C 0
Direction Change Interrupt
Indicates that the direction has changed.
2 IntDir R/W1C 0
Velocity Timer Expired Interrupt
Indicates that the velocity timer has expired.
1 IntTimer R/W1C 0
Index Pulse Interrupt
Indicates that the index pulse has occurred.
0 IntIndex R/W1C 0
November 30, 2007 517
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20 Pin Diagram
Figure 20-1 on page 518 shows the pin diagram and pin-to-signal-name mapping.
Figure 20-1. Pin Connection Diagram
LM3S6952
38
39
40
41
42
43
44
45
46
47
48
49
50
1 75
26 100
2
27
5
6
3
4
7
8
11
9
10
99
28 98
29 97
30 96
31 95
32 94
33 93
34 92
35 91
36 90
73
72
74
71
69
68
70
67
65
66
12
13
14
17
18
15
16
19
20
23
21
22
24
25
64
37 89
88
87
86
85
84
83
82
81
80
79
78
77
76
63
61
60
62
59
57
56
58
55
53
54
52
51
ADC0
ADC1
VDDA
GNDA
ADC2
PE4
LDO
VDD
GND
PD0/PWM0
PD1/PWM1
PD2/U1Rx
PD3/U1Tx
VDD25
GND
XTALPPHY
XTALNPHY
PG1/U2Tx
PG0/U2Rx
VDD
GND
PC7/C2-
PC6/C2+
PC5/C1+/C1o
PC4/PhA0
PA0/U0Rx
PA1/U0Tx
PA2/SSI0Clk
PA3/SSI0Fss
PA4/SSI0Rx
PA5/SSI0Tx
VDD
GND
PA6/CCP1
PA7
VCCPHY
RXIN
VDD25
GND
RXIP
GNDPHY
GNDPHY
TXOP
VDD
GND
TXON
PF0/PhB0
OSC0
OSC1
WAKE
HIB
XOSC0
XOSC1
GND
VBAT
VDD
GND
MDIO
PF3/LED0
PF2/LED1
PF1
VDD25
GND
RST
CMOD0
PB0/PWM2
PB1/PWM3
VDD
GND
PB2/I2C0SCL
PB3/I2C0SDA
PE0/CCP3
PE1
PE2
PE3
CMOD1
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
VDD
GND
VCCPHY
VCCPHY
GNDPHY
GNDPHY
GND
VDD25
PB7/TRST
PB6/C0+/C0o
PB5/C1-
PB4/C0-
VDD
GND
PD4/CCP0
PD5/CCP2
GNDA
VDDA
PD6/Fault
PD7/IDX0
518 November 30, 2007
Preliminary
Pin Diagram
21 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 21-1 on page 519 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 21-2 on page 523 lists the signals in alphabetical order by signal name.
Table 21-3 on page 527 groups the signals by functionality, except for GPIOs. Table 21-4 on page
531 lists the GPIO pins and their alternate functionality.
Table 21-1. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Type Description
1 ADC0 I Analog Analog-to-digital converter input 0.
2 ADC1 I Analog Analog-to-digital converter input 1.
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
3 VDDA - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
4 GNDA - Power
5 ADC2 I Analog Analog-to-digital converter input 2.
6 PE4 I/O TTL GPIO port E bit 4
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
7 LDO - Power
8 VDD - Power Positive supply for I/O and some logic.
9 GND - Power Ground reference for logic and I/O pins.
10 PD0 I/O TTL GPIO port D bit 0
PWM0 O TTL PWM 0
11 PD1 I/O TTL GPIO port D bit 1
PWM1 O TTL PWM 1
12 PD2 I/O TTL GPIO port D bit 2
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx I TTL
13 PD3 I/O TTL GPIO port D bit 3
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx O TTL
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LM3S6952 Microcontroller
Pin Number Pin Name Pin Type Buffer Type Description
Positive supply for most of the logic function,
including the processor core and most
peripherals.
14 VDD25 - Power
15 GND - Power Ground reference for logic and I/O pins.
16 XTALPPHY O TTL XTALP of the Ethernet PHY
17 XTALNPHY I TTL XTALN of the Ethernet PHY
18 PG1 I/O TTL GPIO port G bit 1
UART 2 Transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Tx O TTL
19 PG0 I/O TTL GPIO port G bit 0
UART 2 Receive. When in IrDA mode, this
signal has IrDA modulation.
U2Rx I TTL
20 VDD - Power Positive supply for I/O and some logic.
21 GND - Power Ground reference for logic and I/O pins.
22 PC7 I/O TTL GPIO port C bit 7
C2- I Analog Analog comparator 2 negative input
23 PC6 I/O TTL GPIO port C bit 6
C2+ I Analog Analog comparator positive input
24 PC5 I/O TTL GPIO port C bit 5
C1+ I Analog Analog comparator positive input
C1o O TTL Analog comparator 1 output
25 PC4 I/O TTL GPIO port C bit 4
PhA0 I TTL QEI module 0 Phase A
26 PA0 I/O TTL GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx I TTL
27 PA1 I/O TTL GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx O TTL
28 PA2 I/O TTL GPIO port A bit 2
SSI0Clk I/O TTL SSI module 0 clock
29 PA3 I/O TTL GPIO port A bit 3
SSI0Fss I/O TTL SSI module 0 frame
30 PA4 I/O TTL GPIO port A bit 4
SSI0Rx I TTL SSI module 0 receive
31 PA5 I/O TTL GPIO port A bit 5
SSI0Tx O TTL SSI module 0 transmit
32 VDD - Power Positive supply for I/O and some logic.
33 GND - Power Ground reference for logic and I/O pins.
34 PA6 I/O TTL GPIO port A bit 6
CCP1 I/O TTL Capture/Compare/PWM 1
35 PA7 I/O TTL GPIO port A bit 7
36 VCCPHY I TTL VCC of the Ethernet PHY
37 RXIN I Analog RXIN of the Ethernet PHY
520 November 30, 2007
Preliminary
Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
Positive supply for most of the logic function,
including the processor core and most
peripherals.
38 VDD25 - Power
39 GND - Power Ground reference for logic and I/O pins.
40 RXIP I Analog RXIP of the Ethernet PHY
41 GNDPHY I TTL GND of the Ethernet PHY
42 GNDPHY I TTL GND of the Ethernet PHY
43 TXOP O Analog TXOP of the Ethernet PHY
44 VDD - Power Positive supply for I/O and some logic.
45 GND - Power Ground reference for logic and I/O pins.
46 TXON O Analog TXON of the Ethernet PHY
47 PF0 I/O TTL GPIO port F bit 0
PhB0 I TTL QEI module 1 Phase B
Main oscillator crystal input or an external
clock reference input.
48 OSC0 I Analog
49 OSC1 I Analog Main oscillator crystal output.
An external input that brings the processor out
of hibernate mode when asserted.
50 WAKE I OD
An output that indicates the processor is in
hibernate mode.
51 HIB O TTL
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
52 XOSC0 I Analog
53 XOSC1 I Analog Hibernation Module oscillator crystal output.
54 GND - Power Ground reference for logic and I/O pins.
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
55 VBAT - Power
56 VDD - Power Positive supply for I/O and some logic.
57 GND - Power Ground reference for logic and I/O pins.
58 MDIO I/O TTL MDIO of the Ethernet PHY
59 PF3 I/O TTL GPIO port F bit 3
LED0 O TTL MII LED 0
60 PF2 I/O TTL GPIO port F bit 2
LED1 O TTL MII LED 1
61 PF1 I/O TTL GPIO port F bit 1
Positive supply for most of the logic function,
including the processor core and most
peripherals.
62 VDD25 - Power
63 GND - Power Ground reference for logic and I/O pins.
64 RST I TTL System reset input.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
65 CMOD0 I/O TTL
November 30, 2007 521
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LM3S6952 Microcontroller
Pin Number Pin Name Pin Type Buffer Type Description
66 PB0 I/O TTL GPIO port B bit 0
PWM2 O TTL PWM 2
67 PB1 I/O TTL GPIO port B bit 1
PWM3 O TTL PWM 3
68 VDD - Power Positive supply for I/O and some logic.
69 GND - Power Ground reference for logic and I/O pins.
70 PB2 I/O TTL GPIO port B bit 2
I2C0SCL I/O OD I2C module 0 clock
71 PB3 I/O TTL GPIO port B bit 3
I2C0SDA I/O OD I2C module 0 data
72 PE0 I/O TTL GPIO port E bit 0
CCP3 I/O TTL Capture/Compare/PWM 3
73 PE1 I/O TTL GPIO port E bit 1
74 PE2 I/O TTL GPIO port E bit 2
75 PE3 I/O TTL GPIO port E bit 3
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
76 CMOD1 I/O TTL
77 PC3 I/O TTL GPIO port C bit 3
TDO O TTL JTAG TDO and SWO
SWO O TTL JTAG TDO and SWO
78 PC2 I/O TTL GPIO port C bit 2
TDI I TTL JTAG TDI
79 PC1 I/O TTL GPIO port C bit 1
TMS I/O TTL JTAG TMS and SWDIO
SWDIO I/O TTL JTAG TMS and SWDIO
80 PC0 I/O TTL GPIO port C bit 0
TCK I TTL JTAG/SWD CLK
SWCLK I TTL JTAG/SWD CLK
81 VDD - Power Positive supply for I/O and some logic.
82 GND - Power Ground reference for logic and I/O pins.
83 VCCPHY I TTL VCC of the Ethernet PHY
84 VCCPHY I TTL VCC of the Ethernet PHY
85 GNDPHY I TTL GND of the Ethernet PHY
86 GNDPHY I TTL GND of the Ethernet PHY
87 GND - Power Ground reference for logic and I/O pins.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
88 VDD25 - Power
89 PB7 I/O TTL GPIO port B bit 7
TRST I TTL JTAG TRSTn
90 PB6 I/O TTL GPIO port B bit 6
C0+ I Analog Analog comparator 0 positive input
C0o O TTL Analog comparator 0 output
522 November 30, 2007
Preliminary
Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
91 PB5 I/O TTL GPIO port B bit 5
C1- I Analog Analog comparator 1 negative input
92 PB4 I/O TTL GPIO port B bit 4
C0- I Analog Analog comparator 0 negative input
93 VDD - Power Positive supply for I/O and some logic.
94 GND - Power Ground reference for logic and I/O pins.
95 PD4 I/O TTL GPIO port D bit 4
CCP0 I/O TTL Capture/Compare/PWM 0
96 PD5 I/O TTL GPIO port D bit 5
CCP2 I/O TTL Capture/Compare/PWM 2
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
97 GNDA - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
98 VDDA - Power
99 PD6 I/O TTL GPIO port D bit 6
Fault I TTL PWM Fault
100 PD7 I/O TTL GPIO port D bit 7
IDX0 I TTL QEI module 0 index
Table 21-2. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
C0+ 90 I Analog Analog comparator 0 positive input
C0- 92 I Analog Analog comparator 0 negative input
C0o 90 O TTL Analog comparator 0 output
C1+ 24 I Analog Analog comparator positive input
C1- 91 I Analog Analog comparator 1 negative input
C1o 24 O TTL Analog comparator 1 output
C2+ 23 I Analog Analog comparator positive input
C2- 22 I Analog Analog comparator 2 negative input
CCP0 95 I/O TTL Capture/Compare/PWM 0
CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 96 I/O TTL Capture/Compare/PWM 2
CCP3 72 I/O TTL Capture/Compare/PWM 3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 65 I/O TTL
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LM3S6952 Microcontroller
Pin Name Pin Number Pin Type Buffer Type Description
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Fault 99 I TTL PWM Fault
GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 4 - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 97 - Power
GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
An output that indicates the processor is in
hibernate mode.
HIB 51 O TTL
I2C0SCL 70 I/O OD I2C module 0 clock
I2C0SDA 71 I/O OD I2C module 0 data
IDX0 100 I TTL QEI module 0 index
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
LDO 7 - Power
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
Main oscillator crystal input or an external
clock reference input.
OSC0 48 I Analog
OSC1 49 I Analog Main oscillator crystal output.
524 November 30, 2007
Preliminary
Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
PA0 26 I/O TTL GPIO port A bit 0
PA1 27 I/O TTL GPIO port A bit 1
PA2 28 I/O TTL GPIO port A bit 2
PA3 29 I/O TTL GPIO port A bit 3
PA4 30 I/O TTL GPIO port A bit 4
PA5 31 I/O TTL GPIO port A bit 5
PA6 34 I/O TTL GPIO port A bit 6
PA7 35 I/O TTL GPIO port A bit 7
PB0 66 I/O TTL GPIO port B bit 0
PB1 67 I/O TTL GPIO port B bit 1
PB2 70 I/O TTL GPIO port B bit 2
PB3 71 I/O TTL GPIO port B bit 3
PB4 92 I/O TTL GPIO port B bit 4
PB5 91 I/O TTL GPIO port B bit 5
PB6 90 I/O TTL GPIO port B bit 6
PB7 89 I/O TTL GPIO port B bit 7
PC0 80 I/O TTL GPIO port C bit 0
PC1 79 I/O TTL GPIO port C bit 1
PC2 78 I/O TTL GPIO port C bit 2
PC3 77 I/O TTL GPIO port C bit 3
PC4 25 I/O TTL GPIO port C bit 4
PC5 24 I/O TTL GPIO port C bit 5
PC6 23 I/O TTL GPIO port C bit 6
PC7 22 I/O TTL GPIO port C bit 7
PD0 10 I/O TTL GPIO port D bit 0
PD1 11 I/O TTL GPIO port D bit 1
PD2 12 I/O TTL GPIO port D bit 2
PD3 13 I/O TTL GPIO port D bit 3
PD4 95 I/O TTL GPIO port D bit 4
PD5 96 I/O TTL GPIO port D bit 5
PD6 99 I/O TTL GPIO port D bit 6
PD7 100 I/O TTL GPIO port D bit 7
PE0 72 I/O TTL GPIO port E bit 0
PE1 73 I/O TTL GPIO port E bit 1
PE2 74 I/O TTL GPIO port E bit 2
PE3 75 I/O TTL GPIO port E bit 3
PE4 6 I/O TTL GPIO port E bit 4
PF0 47 I/O TTL GPIO port F bit 0
PF1 61 I/O TTL GPIO port F bit 1
PF2 60 I/O TTL GPIO port F bit 2
PF3 59 I/O TTL GPIO port F bit 3
PG0 19 I/O TTL GPIO port G bit 0
November 30, 2007 525
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LM3S6952 Microcontroller
Pin Name Pin Number Pin Type Buffer Type Description
PG1 18 I/O TTL GPIO port G bit 1
PhA0 25 I TTL QEI module 0 Phase A
PhB0 47 I TTL QEI module 1 Phase B
PWM0 10 O TTL PWM 0
PWM1 11 O TTL PWM 1
PWM2 66 O TTL PWM 2
PWM3 67 O TTL PWM 3
RST 64 I TTL System reset input.
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
TRST 89 I TTL JTAG TRSTn
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx 13 O TTL
UART 2 Receive. When in IrDA mode, this
signal has IrDA modulation.
U2Rx 19 I TTL
UART 2 Transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Tx 18 O TTL
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
VBAT 55 - Power
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
526 November 30, 2007
Preliminary
Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 62 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 88 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 98 - Power
An external input that brings the processor out
of hibernate mode when asserted.
WAKE 50 I OD
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
XOSC0 52 I Analog
XOSC1 53 I Analog Hibernation Module oscillator crystal output.
XTALNPHY 17 I TTL XTALN of the Ethernet PHY
XTALPPHY 16 O TTL XTALP of the Ethernet PHY
Table 21-3. Signals by Function, Except for GPIO
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
ADC ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Analog C0+ 90 I Analog Analog comparator 0 positive input
Comparators C0- 92 I Analog Analog comparator 0 negative input
C0o 90 O TTL Analog comparator 0 output
C1+ 24 I Analog Analog comparator positive input
C1- 91 I Analog Analog comparator 1 negative input
C1o 24 O TTL Analog comparator 1 output
C2+ 23 I Analog Analog comparator positive input
C2- 22 I Analog Analog comparator 2 negative input
Ethernet PHY GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
XTALNPHY 17 I TTL XTALN of the Ethernet PHY
XTALPPHY 16 O TTL XTALP of the Ethernet PHY
General-Purpose CCP0 95 I/O TTL Capture/Compare/PWM 0
Timers CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 96 I/O TTL Capture/Compare/PWM 2
CCP3 72 I/O TTL Capture/Compare/PWM 3
I2C I2C0SCL 70 I/O OD I2C module 0 clock
I2C0SDA 71 I/O OD I2C module 0 data
JTAG/SWD/SWO SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
PWM Fault 99 I TTL PWM Fault
PWM0 10 O TTL PWM 0
PWM1 11 O TTL PWM 1
PWM2 66 O TTL PWM 2
PWM3 67 O TTL PWM 3
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Signal Tables
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Power GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 4 - Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 97 - Power
An output that indicates the processor is in
hibernate mode.
HIB 51 O TTL
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the
board level in addition to the decoupling
capacitor(s).
LDO 7 - Power
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
VBAT 55 - Power
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 62 - Power
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
VDD25 Positive supply for most of the logic function,
including the processor core and most peripherals.
88 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 98 - Power
An external input that brings the processor out of
hibernate mode when asserted.
WAKE 50 I OD
QEI IDX0 100 I TTL QEI module 0 index
PhA0 25 I TTL QEI module 0 Phase A
PhB0 47 I TTL QEI module 1 Phase B
SSI SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
System Control & CMOD0 65 I/O TTL
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 48 I Analog
OSC1 49 I Analog Main oscillator crystal output.
RST 64 I TTL System reset input.
TRST 89 I TTL JTAG TRSTn
Hibernation Module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.19-MHz crystal or a 32.768-kHz oscillator
for the Hibernation Module RTC. See the CLKSEL
bit in the HIBCTL register.
XOSC0 52 I Analog
XOSC1 53 I Analog Hibernation Module oscillator crystal output.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
UART U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Tx 13 O TTL
UART 2 Receive. When in IrDA mode, this signal
has IrDA modulation.
U2Rx 19 I TTL
UART 2 Transmit. When in IrDA mode, this signal
has IrDA modulation.
U2Tx 18 O TTL
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Table 21-4. GPIO Pins and Alternate Functions
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 CCP1
PA7 35
PB0 66 PWM2
PB1 67 PWM3
PB2 70 I2C0SCL
PB3 71 I2C0SDA
PB4 92 C0-
PB5 91 C1-
PB6 90 C0+ C0o
PB7 89 TRST
PC0 80 TCK SWCLK
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25 PhA0
PC5 24 C1+ C1o
PC6 23 C2+
PC7 22 C2-
PD0 10 PWM0
PD1 11 PWM1
PD2 12 U1Rx
PD3 13 U1Tx
PD4 95 CCP0
PD5 96 CCP2
PD6 99 Fault
PD7 100 IDX0
PE0 72 CCP3
PE1 73
PE2 74
PE3 75
PE4 6
PF0 47 PhB0
PF1 61
PF2 60 LED1
PF3 59 LED0
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GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PG0 19 U2Rx
PG1 18 U2Tx
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Signal Tables
22 Operating Characteristics
Table 22-1. Temperature Characteristics
Characteristic Symbol Value Unit
Operating temperature rangea TA -40 to +85 °C
a. Maximum storage temperature is 150°C.
Table 22-2. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance (junction to ambient)a ΘJA 55.3 °C/W
Average junction temperatureb TJ TA + (PAVG • ΘJA) °C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
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23 Electrical Characteristics
23.1 DC Characteristics
23.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 23-1. Maximum Ratings
Characteristic Symbol Value Unit
a
Min Max
I/O supply voltage (VDD) VDD 0 4 V
Core supply voltage (VDD25) VDD25 0 4 V
Analog supply voltage (VDDA) VDDA 0 4 V
Battery supply voltage (VBAT) VBAT 0 4 V
Ethernet PHY supply voltage (VCCPHY) VCCPHY 0 4 V
Input voltage VIN -0.3 5.5 V
Maximum current per output pins I - 25 mA
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
23.1.2 Recommended DC Operating Conditions
Table 23-2. Recommended DC Operating Conditions
Parameter Parameter Name Min Nom Max Unit
VDD I/O supply voltage 3.0 3.3 3.6 V
VDD25 Core supply voltage 2.25 2.5 2.75 V
VDDA Analog supply voltage 3.0 3.3 3.6 V
VBAT Battery supply voltage 2.3 3.0 3.6 V
VCCPHY Ethernet PHY supply voltage 3.0 3.3 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V
VSIH High-level input voltage for Schmitt trigger inputs 0.8 * VDD - VDD V
VSIL Low-level input voltage for Schmitt trigger inputs 0 - 0.2 * VDD V
VOH High-level output voltage 2.4 - - V
VOL Low-level output voltage - - 0.4 V
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Parameter Parameter Name Min Nom Max Unit
IOH High-level source current, VOH=2.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
IOL Low-level sink current, VOL=0.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 23-3. LDO Regulator Characteristics
Parameter Parameter Name Min Nom Max Unit
VLDOOUT Programmable internal (logic) power supply output value 2.25 2.5 2.75 V
Output voltage accuracy - 2% - %
tPON Power-on time - - 100 μs
tON Time on - - 200 μs
tOFF Time off - - 100 μs
VSTEP Step programming incremental voltage - 50 - mV
CLDO External filter capacitor size for internal power supply 1.0 - 3.0 μF
23.1.4 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ VDD25 = 2.50 V
■ VBAT = 3.0 V
■ VDDA = 3.3 V
■ VDDPHY = 3.3 V
■ Temperature = 25°C
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
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Table 23-4. Detailed Power Specifications
3.3 V VDD, VDDA, 2.5 V VDD25 3.0 V VBAT Unit
VDDPHY
Parameter Conditions
Name
Parameter
Nom Max Nom Max Nom Max
VDD25 = 2.50 V 48 pendinga 108 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(Flash loop)
IDD_RUN
VDD25 = 2.50 V 5 pendinga 52 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(Flash loop)
VDD25 = 2.50 V 48 pendinga 100 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(SRAM loop)
VDD25 = 2.50 V 5 pendinga 45 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(SRAM loop)
VDD25 = 2.50 V 5 pendinga 16 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_SLEEP Sleep mode
LDO = 2.25 V 4.6 pendinga 0.21 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Deep-Sleep
mode
IDD_DEEPSLEEP
VBAT = 3.0 V 0 pendinga 0 pendinga 16 pendinga μA
VDD = 0 V
VDD25 = 0 V
VDDA = 0 V
VDDPHY = 0 V
Peripherals = All OFF
System Clock = OFF
Hibernate Module = 32 kHz
Hibernate
mode
IDD_HIBERNATE
a. Pending characterization completion.
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23.1.5 Flash Memory Characteristics
Table 23-5. Flash Memory Characteristics
Parameter Parameter Name Min Nom Max Unit
PECYC Number of guaranteed program/erase cycles before failurea 10,000 100,000 - cycles
TRET Data retention at average operating temperature of 85˚C 10 - - years
TPROG Word program time 20 - - μs
TERASE Page erase time 20 - - ms
TME Mass erase time 200 - - ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
23.2 AC Characteristics
23.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 23-1. Load Conditions
CL = 50 pF
GND
pin
23.2.2 Clocks
Table 23-6. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name Min Nom Max Unit
fref_crystal Crystal referencea 3.579545 - 8.192 MHz
fref_ext External clock referencea 3.579545 - 8.192 MHz
fpll PLL frequencyb - 400 - MHz
TREADY PLL lock time - - 0.5 ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 23-7. Clock Characteristics
Parameter Parameter Name Min Nom Max Unit
fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz
fIOSC30KHZ Internal 30 KHz oscillator frequency 21 30 39 KHz
fXOSC Hibernation module oscillator frequency - 4.194304 - MHz
fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz
fXOSC_EXT External clock reference for hibernation module - 32.768 - KHz
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Parameter Parameter Name Min Nom Max Unit
fMOSC Main oscillator frequency 1 - 8 MHz
tMOSC_per Main oscillator period 125 - 1000 ns
Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8 MHz
a
fref_crystal_bypass
fref_ext_bypass External clock reference (PLL in BYPASS mode)a 0 - 50 MHz
fsystem_clock System clock 0 - 50 MHz
a. The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly.
Table 23-8. Crystal Characteristics
Parameter Name Value Units
Frequency 8 6 4 3.5 MHz
Frequency tolerance ±50 ±50 ±50 ±50 ppm
Aging ±5 ±5 ±5 ±5 ppm/yr
Oscillation mode Parallel Parallel Parallel Parallel
Temperature stability (0 - 85 °C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF
Motional inductance (typ) 14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max) 10 10 10 10 pF
Load capacitance (typ) 16 16 16 16 pF
Drive level (typ) 100 100 100 100 μW
23.2.3 Analog-to-Digital Converter
Table 23-9. ADC Characteristics
Parameter Parameter Name Min Nom Max Unit
VADCIN Maximum single-ended, full-scale analog input voltage - - 3.0 V
Minimum single-ended, full-scale analog input voltage - - 0 V
Maximum differential, full-scale analog input voltage - - 1.5 V
Minimum differential, full-scale analog input voltage - - -1.5 V
CADCIN Equivalent input capacitance - 1 - pF
N Resolution - 10 - bits
fADC ADC internal clock frequency 7 8 9 MHz
tADCCONV Conversion time - - 16 tADCcyclesa
f ADCCONV Conversion rate 438 500 563 k samples/s
INL Integral nonlinearity - - ±1 LSB
DNL Differential nonlinearity - - ±1 LSB
OFF Offset - - ±1 LSB
GAIN Gain - - ±1 LSB
a. tADC= 1/fADC clock
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23.2.4 Analog Comparator
Table 23-10. Analog Comparator Characteristics
Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ±10 ±25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Common mode rejection ratio 50 - - dB
TRT Response time - - 1 μs
TMC Comparator mode change to Output Valid - - 10 μs
Table 23-11. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
RHR Resolution high range - VDD/32 - LSB
RLR Resolution low range - VDD/24 - LSB
AHR Absolute accuracy high range - - ±1/2 LSB
ALR Absolute accuracy low range - - ±1/4 LSB
23.2.5 I2C
Table 23-12. I2C Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
I1a tSCH Start condition hold time 36 - - system clocks
I2a tLP Clock Low period 36 - - system clocks
I3b tSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns
I4a tDH Data hold time 2 - - system clocks
I5c tSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns
I6a tHT Clock High time 24 - - system clocks
I7a tDS Data setup time 18 - - system clocks
Start condition setup time (for repeated start condition 36 - - system clocks
only)
I8a tSCSR
I9a tSCS Stop condition setup time 24 - - system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
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Figure 23-2. I2C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
23.2.6 Ethernet Controller
Table 23-13. 100BASE-TX Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak output amplitude 950 - 1050 mVpk
Output amplitude symmetry 0.98 - 1.02 mVpk
Output overshoot - - 5 %
Rise/Fall time 3 - 5 ns
Rise/Fall time imbalance - - 500 ps
Duty cycle distortion - - - ps
Jitter - - 1.4 ns
a. Measured at the line side of the transformer.
Table 23-14. 100BASE-TX Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Return loss 16 - - dB
Open-circuit inductance 350 - - μs
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 23-15. 100BASE-TX Receiver Characteristics
Parameter Name Min Nom Max Unit
Signal detect assertion threshold 600 700 mVppd
Signal detect de-assertion threshold 350 425 - mVppd
Differential input resistance 20 - - kΩ
Jitter tolerance (pk-pk) 4 - - ns
Baseline wander tracking -75 - +75 %
Signal detect assertion time - - 1000 μs
Signal detect de-assertion time - - 4 μs
Table 23-16. 10BASE-T Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak differential output signal 2.2 - 2.8 V
Harmonic content 27 - - dB
Link pulse width - 100 - ns
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Parameter Name Min Nom Max Unit
300 - ns
350
Start-of-idle pulse width -
a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using
the procedures found in Clause 14 of IEEE 802.3.
Table 23-17. 10BASE-T Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Output return loss 15 - - dB
Output impedance balance 29-17log(f/10) - - dB
Peak common-mode output voltage - - 50 mV
Common-mode rejection - - 100 mV
Common-mode rejection jitter - - 1 ns
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 23-18. 10BASE-T Receiver Characteristics
Parameter Name Min Nom Max Unit
DLL phase acquisition time - 10 - BT
Jitter tolerance (pk-pk) 30 - - ns
Input squelched threshold 500 600 700 mVppd
Input unsquelched threshold 275 350 425 mVppd
Differential input resistance - 20 - kΩ
Bit error ratio - 10-10 - -
Common-mode rejection 25 - - V
Table 23-19. Isolation Transformersa
Name Value Condition
Turns ratio 1 CT : 1 CT +/- 5%
Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz
Leakage inductance 0.40 uH (max) @ 1 MHz (min)
Inter-winding capacitance 25 pF (max)
DC resistance 0.9 Ohm (max)
Insertion loss 0.4 dB (typ) 0-65 MHz
HIPOT 1500 Vrms
a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode
chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer
characteristics.
Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the
transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be
compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO)
bits in the MR19 register.
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Table 23-20. Ethernet Reference Crystala
Name Value Condition
Frequency 25.00000 MHz
Load capacitanceb 4c pF
Frequency tolerance ±50 PPM
Aging ±2 PPM/yr
Temperature stability (0° to 70°) ±5 PPM
Oscillation mode Parallel resonance, fundamental mode
Parameters at 25° C ±2° C; Drive level = 0.5 mW
Drive level (typ) 50-100 μW
Shunt capacitance (max) 10 pF
Motional capacitance (min) 10 fF
Serious resistance (max) 60 Ω
Spurious response (max) > 5 dB below main within 500 kHz
a. If the internal crystal oscillator is used, select a crystal with the following characteristics.
b. Equivalent differential capacitance across XTLP/XTLN.
c. If crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent
capacitance difference.
Figure 23-3. External XTLP Oscillator Characteristics
Tclkper
Tr
Tclkhi Tclklo
Tf
Table 23-21. External XTLP Oscillator Characteristics
Parameter Name Symbol Min Nom Max Unit
XTLN Input Low Voltage XTLNILV - - 0.8 -
XTLP Frequencya XTLPf - 25.0 - -
XTLP Periodb Tclkper - 40 - -
60 %
60
40 -
40
XTLPDC XTLP Duty Cycle
Rise/Fall Time Tr , Tf - - 4.0 ns
Absolute Jitter - - 0.1 ns
a. IEEE 802.3 frequency tolerance ±50 ppm.
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b. IEEE 802.3 frequency tolerance ±50 ppm.
23.2.7 Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 VDC or powered down with the same regulator controlled
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 23-22. Hibernation Module Characteristics
Parameter No Parameter Parameter Name Min Nom Max Unit
H1 tHIB_LOW Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2 tHIB_HIGH Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3 tWAKE_ASSERT /WAKE assertion time 62 - - μs
H4 tWAKETOHIB /WAKE assert to /HIB desassert 62 - 124 μs
H5 tXOSC_SETTLE XOSC settling timea 20 - - ms
H6 tHIB_REG_WRITE Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum operational level - - 250 μs
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 23-4. Hibernation Module Timing
32.768 KHz
(internal)
/HIB
H4
H1
/WAKE
H2
H3
23.2.8 Synchronous Serial Interface (SSI)
Table 23-23. SSI Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
S1 tclk_per SSIClk cycle time 2 - 65024 system clocks
S2 tclk_high SSIClk high time - 1/2 - t clk_per
S3 tclk_low SSIClk low time - 1/2 - t clk_per
S4 tclkrf SSIClk rise/fall time - 7.4 26 ns
S5 tDMd Data from master valid delay time 0 - 20 ns
S6 tDMs Data from master setup time 20 - - ns
S7 tDMh Data from master hold time 40 - - ns
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Parameter No. Parameter Parameter Name Min Nom Max Unit
S8 tDSs Data from slave setup time 20 - - ns
S9 tDSh Data from slave hold time 40 - - ns
Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
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Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S8 S9
MSB
23.2.9 JTAG and Boundary Scan
Table 23-24. JTAG Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK clock Low time - tTCK - ns
J4 tTCK_HIGH TCK clock High time - tTCK - ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
J11 TCK fall to Data Valid from High-Z 2-mA drive - 23 35 ns
t TDO_ZDV 4-mA drive 15 26 ns
8-mA drive 14 25 ns
8-mA drive with slew rate control 18 29 ns
J12 TCK fall to Data Valid from Data Valid 2-mA drive - 21 35 ns
t TDO_DV 4-mA drive 14 25 ns
8-mA drive 13 24 ns
8-mA drive with slew rate control 18 28 ns
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Parameter No. Parameter Parameter Name Min Nom Max Unit
J13 TCK fall to High-Z from Data Valid 2-mA drive - 9 11 ns
t TDO_DVZ 4-mA drive 7 9 ns
8-mA drive 6 8 ns
8-mA drive with slew rate control 7 9 ns
J14 tTRST TRST assertion time 100 - - ns
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns
Figure 23-8. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 23-9. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8 J7 J8
Figure 23-10. JTAG TRST Timing
TCK
J14 J15
TRST
23.2.10 General-Purpose I/O
Note: All GPIOs are 5 V-tolerant.
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Table 23-25. GPIO Characteristics
Parameter Parameter Name Condition Min Nom Max Unit
tGPIOR GPIO Rise Time (from 20% to 80% of VDD) 2-mA drive - 17 26 ns
4-mA drive 9 13 ns
8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
tGPIOF GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive - 17 25 ns
4-mA drive 8 12 ns
8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns
23.2.11 Reset
Table 23-26. Reset Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-On Reset timeout - 10 - ms
R4 TBOR Brown-Out timeout - 500 - μs
R5 TIRPOR Internal reset timeout after POR 6 - 11 ms
R6 TIRBOR Internal reset timeout after BORa 0 - 1 μs
R7 TIRHWR Internal reset timeout after hardware reset (RST pin) 0 - 1 ms
R8 TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 μs
R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 μs
R10 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) - - 100 ms
R11 TMIN Minimum RST pulse width 2 - - μs
a. 20 * t MOSC_per
Figure 23-11. External Reset Timing (RST)
RST
/Reset
(Internal)
R11 R7
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Figure 23-12. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 23-13. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
Figure 23-14. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 23-15. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
548 November 30, 2007
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24 Package Information
Figure 24-1. 100-Pin LQFP Package
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
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Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols Leads 100L
A Max. 1.60
A1 0.05 Min./0.15 Max.
A2 ±0.05 1.40
D ±0.20 16.00
D1 ±0.05 14.00
E ±0.20 16.00
E1 ±0.05 14.00
L ±0.15/-0.10 0.60
e BASIC 0.50
b ±0.05 0.22
θ === 0˚~7˚
ddd Max. 0.08
ccc Max. 0.08
JEDEC Reference Drawing MS-026
Variation Designator BED
550 November 30, 2007
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Package Information
A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris® device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 339 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
November 30, 2007 551
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the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 554).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
552 November 30, 2007
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Serial Flash Loader
flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
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Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
554 November 30, 2007
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Serial Flash Loader
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
November 30, 2007 555
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LM3S6952 Microcontroller
B Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset -
VER CLASS
MAJOR MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000
PLLLRIS BORRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
PLLLIM BORIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
PLLLMIS BORMIS
RESC, type R/W, offset 0x05C, reset -
LDO SW WDT BOR POR EXT
RCC, type R/W, offset 0x060, reset 0x07AE.3AD1
ACG SYSDIV USESYSDIV USEPWMDIV PWMDIV
PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset -
F R
RCC2, type R/W, offset 0x070, reset 0x0780.2800
USERCC2 SYSDIV2
PWRDN2 BYPASS2 OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset -
VER FAM PARTNO
PINCOUNT TEMP PKG ROHS QUAL
DC0, type RO, offset 0x008, reset 0x00FF.007F
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0011.32FF
PWM ADC
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
DC2, type RO, offset 0x014, reset 0x0707.1117
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
DC3, type RO, offset 0x018, reset 0x0F07.BFCF
CCP3 CCP2 CCP1 CCP0 ADC2 ADC1 ADC0
PWMFAULT C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM3 PWM2 PWM1 PWM0
556 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC4, type RO, offset 0x01C, reset 0x5000.007F
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RCGC0, type R/W, offset 0x100, reset 0x00000040
PWM ADC
MAXADCSPD HIB WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040
PWM ADC
MAXADCSPD HIB WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040
PWM ADC
MAXADCSPD HIB WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
SCGC1, type R/W, offset 0x114, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
DCGC2, type R/W, offset 0x128, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SRCR0, type R/W, offset 0x040, reset 0x00000000
PWM ADC
HIB WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Hibernation Module
Base 0x400F.C000
HIBRTCC, type RO, offset 0x000, reset 0x0000.0000
RTCC
RTCC
HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF
RTCM0
RTCM0
HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF
RTCM1
RTCM1
HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF
RTCLD
RTCLD
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HIBCTL, type R/W, offset 0x010, reset 0x0000.0000
VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
HIBIM, type R/W, offset 0x014, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBRIS, type RO, offset 0x018, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBMIS, type RO, offset 0x01C, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF
TRIM
HIBDATA, type R/W, offset 0x030-0x12C, reset 0x0000.0000
RTD
RTD
Internal Memory
Flash Control Offset
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT MERASE ERASE WRITE
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
PRIS ARIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
PMASK AMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMISC AMISC
Internal Memory
System Control Offset
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
558 November 30, 2007
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW DATA
DATA DBG1 DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
560 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TAAMS TACMR TAMR
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
TBAMS TBCMR TBMR
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS
November 30, 2007 561
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000
RESEN INTEN
WDTICR, type WO, offset 0x00C, reset -
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
562 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Analog-to-Digital Converter (ADC)
Base 0x4003.8000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000
ASEN3 ASEN2 ASEN1 ASEN0
ADCRIS, type RO, offset 0x004, reset 0x0000.0000
INR3 INR2 INR1 INR0
November 30, 2007 563
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCIM, type R/W, offset 0x008, reset 0x0000.0000
MASK3 MASK2 MASK1 MASK0
ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000
IN3 IN2 IN1 IN0
ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000
OV3 OV2 OV1 OV0
ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000
EM3 EM2 EM1 EM0
ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000
UV3 UV2 UV1 UV0
ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210
SS3 SS2 SS1 SS0
ADCPSSI, type WO, offset 0x028, reset -
SS3 SS2 SS1 SS0
ADCSAC, type R/W, offset 0x030, reset 0x0000.0000
AVG
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000
MUX7 MUX6 MUX5 MUX4
MUX3 MUX2 MUX1 MUX0
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSFIFO0, type RO, offset 0x048, reset 0x0000.0000
DATA
ADCSSFIFO1, type RO, offset 0x068, reset 0x0000.0000
DATA
ADCSSFIFO2, type RO, offset 0x088, reset 0x0000.0000
DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset 0x0000.0000
DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
564 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSMUX1, type RO, offset 0x060, reset 0x0000.0000
MUX3 MUX2 MUX1 MUX0
ADCSSMUX2, type RO, offset 0x080, reset 0x0000.0000
MUX3 MUX2 MUX1 MUX0
ADCSSCTL1, type RO, offset 0x064, reset 0x0000.0000
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSCTL2, type RO, offset 0x084, reset 0x0000.0000
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000
MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002
TS0 IE0 END0 D0
ADCTMLB, type RO, offset 0x100, reset 0x0000.0000
CNT CONT DIFF TS MUX
ADCTMLB, type WO, offset 0x100, reset 0x0000.0000
LB
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
OE BE PE FE DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000
OE BE PE FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
TXFE RXFF TXFF RXFE BUSY
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
November 30, 2007 565
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
SPS WLEN FEN STP2 EPS PEN BRK
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
RXE TXE LBE SIRLP SIREN UARTEN
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
RXIFLSEL TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
OEIM BEIM PEIM FEIM RTIM TXIM RXIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
566 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
SCR SPH SPO FRF DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
SOD MS SSE LBM
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003
BSY RFF RNE TNF TFE
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
TXIM RXIM RTIM RORIM
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
TXRIS RXRIS RTRIS RORRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
TXMIS RXMIS RTMIS RORMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
November 30, 2007 567
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C Master 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
SA R/S
I2CMCS, type RO, offset 0x004, reset 0x0000.0000
BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
I2CMCS, type WO, offset 0x004, reset 0x0000.0000
ACK STOP START RUN
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
SFE MFE LPBK
Inter-Integrated Circuit (I2C) Interface
568 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C Slave
I2C Slave 0 base: 0x4002.0800
I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x004, reset 0x0000.0000
FBR TREQ RREQ
I2CSCSR, type WO, offset 0x004, reset 0x0000.0000
DA
I2CSDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000
IM
I2CSRIS, type RO, offset 0x010, reset 0x0000.0000
RIS
I2CSMIS, type RO, offset 0x014, reset 0x0000.0000
MIS
I2CSICR, type WO, offset 0x018, reset 0x0000.0000
IC
Ethernet Controller
Ethernet MAC
Base 0x4004.8000
MACRIS, type RO, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIACK, type W1C, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIM, type R/W, offset 0x004, reset 0x0000.007F
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
MACRCTL, type R/W, offset 0x008, reset 0x0000.0008
RSTFIFO BADCRC PRMS AMUL RXEN
MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000
DUPLEX CRC PADEN TXEN
MACDATA, type RO, offset 0x010, reset 0x0000.0000
RXDATA
RXDATA
MACDATA, type WO, offset 0x010, reset 0x0000.0000
TXDATA
TXDATA
November 30, 2007 569
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACIA0, type R/W, offset 0x014, reset 0x0000.0000
MACOCT4 MACOCT3
MACOCT2 MACOCT1
MACIA1, type R/W, offset 0x018, reset 0x0000.0000
MACOCT6 MACOCT5
MACTHR, type R/W, offset 0x01C, reset 0x0000.003F
THRESH
MACMCTL, type R/W, offset 0x020, reset 0x0000.0000
REGADR WRITE START
MACMDV, type R/W, offset 0x024, reset 0x0000.0080
DIV
MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000
MDTX
MACMRXD, type R/W, offset 0x030, reset 0x0000.0000
MDRX
MACNP, type RO, offset 0x034, reset 0x0000.0000
NPR
MACTR, type R/W, offset 0x038, reset 0x0000.0000
NEWTX
Ethernet Controller
MII Management
Base 0x4004.8000
MR0, type R/W, address 0x00, reset 0x3100
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT
MR1, type RO, address 0x01, reset 0x7849
100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
MR2, type RO, address 0x02, reset 0x000E
OUI[21:6]
MR3, type RO, address 0x03, reset 0x7237
OUI[5:0] MN RN
MR4, type R/W, address 0x04, reset 0x01E1
NP RF A3 A2 A1 A0 S[4:0]
MR5, type RO, address 0x05, reset 0x0000
NP ACK RF A[7:0] S[4:0]
MR6, type RO, address 0x06, reset 0x0000
PDF LPNPA PRX LPANEGA
MR16, type R/W, address 0x10, reset 0x0140
RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL PCSBP RXCC
MR17, type R/W, address 0x11, reset 0x0000
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
MR18, type RO, address 0x12, reset 0x0000
ANEGF DPLX RATE RXSD RX_LOCK
MR19, type R/W, address 0x13, reset 0x4000
TXO[1:0]
570 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR23, type R/W, address 0x17, reset 0x0010
LED1[3:0] LED0[3:0]
MR24, type R/W, address 0x18, reset 0x00C0
PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x00, reset 0x0000.0000
IN2 IN1 IN0
ACRIS, type RO, offset 0x04, reset 0x0000.0000
IN2 IN1 IN0
ACINTEN, type R/W, offset 0x08, reset 0x0000.0000
IN2 IN1 IN0
ACREFCTL, type R/W, offset 0x10, reset 0x0000.0000
EN RNG VREF
ACSTAT0, type RO, offset 0x20, reset 0x0000.0000
OVAL
ACSTAT1, type RO, offset 0x40, reset 0x0000.0000
OVAL
ACSTAT2, type RO, offset 0x60, reset 0x0000.0000
OVAL
ACCTL0, type R/W, offset 0x24, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL1, type R/W, offset 0x44, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL2, type R/W, offset 0x64, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
Pulse Width Modulator (PWM)
Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000
GlobalSync1 GlobalSync0
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000
Sync1 Sync0
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000
PWM3En PWM2En PWM1En PWM0En
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000
PWM3Inv PWM2Inv PWM1Inv PWM0Inv
November 30, 2007 571
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000
Fault3 Fault2 Fault1 Fault0
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000
IntFault
IntPWM1 IntPWM0
PWMRIS, type RO, offset 0x018, reset 0x0000.0000
IntFault
IntPWM1 IntPWM0
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000
IntFault
IntPWM1 IntPWM0
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000
Fault
PWM0CTL, type RO, offset 0x040, reset 0x0000.0000
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM1CTL, type RO, offset 0x080, reset 0x0000.0000
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM0INTEN, type RO, offset 0x044, reset 0x0000.0000
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1INTEN, type RO, offset 0x084, reset 0x0000.0000
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1RIS, type RO, offset 0x088, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0ISC, type RO, offset 0x04C, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1ISC, type RO, offset 0x08C, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0LOAD, type RO, offset 0x050, reset 0x0000.0000
Load
PWM1LOAD, type RO, offset 0x090, reset 0x0000.0000
Load
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000
Count
PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000
Count
572 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM0CMPA, type RO, offset 0x058, reset 0x0000.0000
CompA
PWM1CMPA, type RO, offset 0x098, reset 0x0000.0000
CompA
PWM0CMPB, type RO, offset 0x05C, reset 0x0000.0000
CompB
PWM1CMPB, type RO, offset 0x09C, reset 0x0000.0000
CompB
PWM0GENA, type RO, offset 0x060, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM1GENA, type RO, offset 0x0A0, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0GENB, type RO, offset 0x064, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM1GENB, type RO, offset 0x0A4, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0DBCTL, type RO, offset 0x068, reset 0x0000.0000
Enable
PWM1DBCTL, type RO, offset 0x0A8, reset 0x0000.0000
Enable
PWM0DBRISE, type RO, offset 0x06C, reset 0x0000.0000
RiseDelay
PWM1DBRISE, type RO, offset 0x0AC, reset 0x0000.0000
RiseDelay
PWM0DBFALL, type RO, offset 0x070, reset 0x0000.0000
FallDelay
PWM1DBFALL, type RO, offset 0x0B0, reset 0x0000.0000
FallDelay
Quadrature Encoder Interface (QEI)
QEI0 base: 0x4002.C000
QEICTL, type R/W, offset 0x000, reset 0x0000.0000
STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
QEISTAT, type RO, offset 0x004, reset 0x0000.0000
Direction Error
QEIPOS, type R/W, offset 0x008, reset 0x0000.0000
Position
Position
November 30, 2007 573
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000
MaxPos
MaxPos
QEILOAD, type R/W, offset 0x010, reset 0x0000.0000
Load
Load
QEITIME, type RO, offset 0x014, reset 0x0000.0000
Time
Time
QEICOUNT, type RO, offset 0x018, reset 0x0000.0000
Count
Count
QEISPEED, type RO, offset 0x01C, reset 0x0000.0000
Speed
Speed
QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000
IntError IntDir IntTimer IntIndex
QEIRIS, type RO, offset 0x024, reset 0x0000.0000
IntError IntDir IntTimer IntIndex
QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000
IntError IntDir IntTimer IntIndex
574 November 30, 2007
Preliminary
Register Quick Reference
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
Temperature
Package
Speed
Revision
Shipping Medium
I = -40 C to 85 C
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Omitted = Default to current shipping
revision
A0 = First all-layer mask
A1 = Metal layers update to A0
A2 = Metal layers update to A1
B0 = Second all-layer mask revision
RN = 28-pin SOIC
QN = 48-pin LQFP
QC = 100-pin LQFP
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
Table C-1. Part Ordering Information
Orderable Part Number Description
Stellaris® LM3S6952-IQC50 LM3S6952 Microcontroller
Stellaris® LM3S6952-IQC50(T) LM3S6952 Microcontroller
C.2 Kits
The Luminary Micro Stellaris® Family provides the hardware and software tools that engineers need
to begin development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware, and
comprehensive documentation including hardware design files:
http://www.luminarymicro.com/products/reference_design_kits/
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris® microcontrollers
before purchase:
http://www.luminarymicro.com/products/evaluation_kits/
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box:
http://www.luminarymicro.com/products/boards.html
See the Luminary Micro website for the latest tools available or ask your Luminary Micro distributor.
C.3 Company Information
Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs).
Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the
world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the
November 30, 2007 575
Preliminary
LM3S6952 Microcontroller
Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit
microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU,
Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural
upgrades or software tool changes.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
sales@luminarymicro.com
C.4 Support Information
For support on Luminary Micro products, contact:
support@luminarymicro.com +1-512-279-8800, ext. 3
576 November 30, 2007
Preliminary
Ordering and Contact Information
Evaluation Board User Guide
UG-146
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADE7878 Energy Metering IC
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 36
FEATURES
Evaluation board designed to be used with accompanying software to implement a fully functional 3-phase energy meter Easy connection of external transducers via screw terminals Easy modification of signal conditioning components using PCB sockets LED indicators on the CF1, CF2, CF3, IRQ0, and IRQ1 logic outputs Optically isolated metering components and USB-based communication with a PC External voltage reference option available for on-chip reference evaluation PC COM port-based firmware updates
GENERAL DESCRIPTION
The ADE7878 is a high accuracy, 3-phase electrical energy measurement IC with serial interfaces and three flexible pulse outputs. The ADE7878 incorporates seven ADCs, reference circuitry, and all signal processing required to perform total (fundamental and harmonic) active, reactive, and apparent energy measurement, fundamental active and reactive energy measurement, and rms calculations.
This user guide describes the ADE7878 evaluation kit hardware, firmware, and software functionality. The evaluation board contains an ADE7878 and a LPC2368 microcontroller (from NXP Semiconductors). The ADE7878 and its associated metering components are optically isolated from the microcontroller. The microcontroller communicates with the PC using a USB interface. Firmware updates can be loaded using one PC com port and a regular serial cable.
The ADE7878 evaluation board and this user guide, together with the ADE7878 data sheet, provide a complete evaluation platform for the ADE7878.
The evaluation board has been designed so that the ADE7878 can be evaluated in an energy meter. Using appropriate current transducers, the evaluation board can be connected to a test bench or high voltage (240 V rms) test circuit. On-board resistor divider networks provide the attenuation for the line voltages. This user guide describes how the current transducers should be connected for the best performance. The evaluation board requires two external 3.3 V power supplies and the appropriate current transducers.
EVALUATION BOARD CONNECTION DIAGRAM
ADE78xxP1P2P3P4P5P6P7P8P9IAPIANIBPIBNICPICNINPINNGNDVNGNDVCPGNDVBPGNDVAPGNDVDDFILTERNETWORKFILTER NETWORKAND ATTENUATIONADR280OPTIONAL EXTERNAL1.2V REFERENCEOPTIONALEXTERNALCLOCK INDIGITALISOLATORSLPC2368P10GND2VDD2P12MCU_GNDMCU_VDDUSB PORTJ2J3J4CF3CF2CF1P13JTAGINTERFACEP15CONNECTOR TOPC COM PORT09078-001 Figure 1.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Evaluation Board Connection Diagram ........................................ 1
Revision History ............................................................................... 2
Evaluation Board Hardware ............................................................ 3
Power Supplies .............................................................................. 3
Analog Inputs (P1 to P4 and P5 to P8) ...................................... 3
Setting Up the Evaluation Board as an Energy Meter ............. 6
Evaluation Board Software .............................................................. 8
Installing and Uninstalling the ADE7878 Software ................. 8
Front Panel .................................................................................... 8
PSM0 Mode—Normal Power Mode .......................................... 9
PSM1 Mode ................................................................................. 17
PSM2 Mode ................................................................................. 17
PSM3 Mode ................................................................................. 18
Managing the Communication Protocol Between the Microcontroller and the ADE7878 .............................................. 19
Acquiring HSDC Data Continuously ...................................... 21
Starting the ADE7878 DSP ....................................................... 22
Stopping the ADE7878 DSP ..................................................... 22
Upgrading Microcontroller Firmware ......................................... 23
Control Registers Data File ....................................................... 23
Evaluation Board Schematics and Layout ................................... 25
Schematic..................................................................................... 25
Layout .......................................................................................... 32
Ordering Information .................................................................... 34
Bill of Materials ........................................................................... 34
REVISION HISTORY
8/10—Revision 0: Initial Version
Evaluation Board User Guide UG-146
Rev. 0 | Page 3 of 36
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The evaluation board has three power domains: one that supplies the microcontroller and one side of the isocouplers, one that supplies the other side of the optocouplers, and one that supplies the ADE7878. The ground of the microcontroller’s power domain is connected to the ground of the PC through the USB cable. The ground of the ADE7878 power domain is determined by the ground of the phase voltages, VAP, VBP, VCP, and VN, and must be different from the ground of the micro-controller’s power domain.
The microcontroller 3.3 V supply is provided at the P12 connector. The ADE7878 3.3 V supply is provided at the P9 connector. Close jumper JP2 to ensure that the same 3.3 V supply from ADE7878 is also provided at the isocouplers.
ANALOG INPUTS (P1 TO P4 AND P5 TO P8)
Current and voltage signals are connected at the screw terminal, P1 to P4 and P5 to P8, respectively. All analog input signals are filtered using the on-board antialiasing filters before the signals are connected to the ADE7878. The components used on the board are the recommended values to be used with the ADE7878.
Current Sense Inputs (P1, P2, P3, and P4)
The ADE7878 measures three phase currents and the neutral current. Current transformers or Rogowski coils can be used to sense the current but should not be mixed together. The ADE7878 contains different internal PGA gains on phase currents and on the neutral current; therefore, sensors with different ratios can be used. The only requirement is to have the same scale signals at the PGA outputs; otherwise, the mismatch functionality of the ADE7878 is compromised (see the ADE7878 data sheet for more details about neutral current mismatch). Figure 2 shows the structure used for the Phase A current; the sensor outputs are connected to the P1 connector. The R1 and R2 resistors are the burden resistors and, by default, they are not populated. They can also be disabled using the JP1A and JP2A jumpers. The R9/C9 and R10/C10 RC networks are used in conjunction with Rogowski coils. They can be disabled using the JP3A and JP4A jumpers. The R17/C17 and R18/C18 RC networks are the antialiasing filters. The default corner frequency of these low pass filters is 7.2 kHz (1 kΩ/22 nF). These filters can easily be adjusted by replacing the components on the evaluation board. All the other current channels (that is, Phase B, Phase C, and the neutral current) have a similar input structure.
Using a Current Transformer as the Current Sensor
Figure 3 shows how a current transformer can be used as a current sensor in one phase of a 3-phase, 4-wire distribution system (Phase A). The other two phases and the neutral current require similar connections. P1IAPIANJP1AJP2AR1R2R17R10R18100Ω1kΩ100Ω1kΩC922,000pFC1022,000pFC1722,000pFC1822,000pFR9JP4AJP5AJP3AJP6AIAPIANADE78xxTP1TP209078-002
Figure 2. Phase A Current Input Structure on the Evaluation Board IMAX = 6A rmsCT1:2000P1JP1AJP2AR150ΩR250ΩR17R10R18100Ω1kΩ100Ω1kΩC922,000pFC1022,000pFC1722,000pFC1822,000pFR9JP4AJP5AJP3AJP6AIAPIANADE78xxTP1TP209078-003
Figure 3. Example of a Current Transformer Connection The R1 and R2 burden resistors must be defined as functions of the current transformer ratio and maximum current of the system, using the following formula: R1 = R2 = 1/2 × 0.5/sqrt(2) × N/IFS where: 0.5/sqrt(2) is the rms value of the full-scale voltage accepted at the ADC input. N is the input-to-output ratio of the current transformer. IFS is the maximum rms current to be measured.
The JP1A and JP2A jumpers should be opened if R1 and R2 are used. The antialiasing filters should be enabled by opening the J5A and J6A jumpers (see Figure 3). The secondary current of the transformer is converted to a voltage by using a burden resistor across the secondary winding outputs. Care should be taken when using a current transformer as the current sensor. If the secondary is left open (that is, no burden is connected), a large voltage may be present at the secondary outputs. This can cause an electric shock hazard and potentially damage electronic components.
Most current transformers introduce a phase shift that the manufacturer indicates in the data sheet. This phase shift can lead to significant energy measurement errors, especially at low power factors. The ADE7878 can correct the phase error using the APHCAL[9:0], BPHCAL[9:0], and CPHCAL[9:0] phase calibration registers as long as the error stays between −6.732° and +1.107° at 50 Hz (see the ADE7878 data sheet for more
UG-146 Evaluation Board User Guide
Rev. 0 | Page 4 of 36
details). The software supplied with the ADE7878 evaluation board allows user adjustment of phase calibration registers.
For this particular example, burden resistors of 50 Ω signify an input current of 7.05 A rms at the ADE7878 ADC full-scale input (0.5 V). In addition, the PGA gains for the current channel must be set at 1. For more information about setting PGA gains, see the ADE7878 data sheet. The evaluation software allows the user to configure the current channel gain.
Using a Rogowski Coil as the Current Sensor
Figure 4 shows how a Rogowski coil can be used as a current sensor in one phase of a 3-phase, 4-wire distribution system (Phase A). The other two phases and the neutral current require similar connections. The Rogowski coil does not require any burden resistors; therefore, R1 and R2 should not be populated. The antialiasing filters should be enabled by opening the J5A and J6A jumpers. To account for the high frequency noise introduced by the coil, an additional antialiasing filter must be introduced by opening the JP3A and JP4A jumpers. Then, to compensate for the 20 dB/dec gain introduced by the di/dt sensor, the integrator of the ADE7878 must be enabled by setting Bit 0 (INTEN) of the CONFIG register. The integrator has a −20 dB/dec attenuation and an approximately −90° phase shift and, when combined with the di/dt sensor, results in a magnitude and phase response with a flat gain over the frequency band of interest. ROGOWSKICOILP1JP1AJP2AR1R2R17R10R18100Ω1kΩ100Ω1kΩC922,000pFC1022,000pFC1722,000pFC1822,000pFR9JP4AJP5AJP3AJP6AIAPIANADE78xxTP1TP209078-004
Figure 4. Example of a Rogowski Coil Connection
Voltage Sense Inputs (P5, P6, P7, and P8 Connectors)
The voltage input connections on the ADE7878 evaluation board can be directly connected to the line voltage sources. The line voltages are attenuated using a simple resistor divider network before they are supplied to the ADE7878. The attenuation network on the voltage channels is designed so that the corner frequency (3 dB frequency) of the network matches that of the antialiasing filters in the current channel inputs. This prevents the occurrence of large energy errors at low power factors.
Figure 5 shows a typical connection of the Phase A voltage inputs; the resistor divider is enabled by opening the JP7A jumper. The antialiasing filter on the VN data path is enabled by opening the JP7N jumper. JP8A and JP8N are also opened. The VN analog input is connected to AGND via the R25/C25 antialiasing filter using the JP8N connector. The attenuation networks can be easily modified by the user to accommodate any input level. However, the value of R32 (1 kΩ), should be modified only together with the corresponding resistors in the current channel (R17 and R18 on the Phase A current data path). P8JP8AVAPVNR291MΩ100kΩR321kΩC3222,000pFC2522,000pFR26JP7AVAPADE78xxTP12JP9AVNPHASE ANEUTRALP5JP8N1kΩR25JP7NVNTP9ACOMB12309078-005
Figure 5. Phase A Voltage Input Structure on the Evaluation Board
The maximum signal level permissible at the VAP, VBP, and VCP pins of the ADE7878 is 0.5 V peak. Although the ADE7878 analog inputs can withstand ±2 V without risk of permanent damage, the signal range should not exceed ±0.5 V with respect to AGND for a specified operation.
Evaluation Board User Guide UG-146
Rev. 0 | Page 5 of 36 Table 1. Recommended Settings for Evaluation Board Connectors Jumper Option Description
JP1 Soldered Connects AGND to ground. By default, it is soldered. JP1A, JP1B,
JP1C, JP1N,
Open Connect IAP, IBP, IC, and INP to AGND. By default, they are open.
JP2 Closed Connects the ADE7878 VDD power supply (VDD_F at the P9 connector) to the power supply of the
isocouplers (VDD2 at the P10 connector). By default, it is closed. JP2A, JP2B,
JP2C, JP2N
Open Connect IAN, IBN, ICN, and INN to AGND. By default, they are open.
JP3 Unsoldered Connects the pad metal below the ADE7878 to AGND. By default, it is unsoldered.
JP3A, JP3B,
JP3C, JP3N
Closed Disable the phase compensation network in the IAP, IBP, ICP, and INP data path. By default, they are
closed. JP4 Soldered Connects C3 to DVDD. By default, it is soldered.
JP4A, JP4B,
JP4C, JP4N
Closed Disable the phase compensation network in the IAN, IBN, ICN, and INN data path. By default, they are
closed. JP5 Soldered Connects C5 to AVDD. By default, it is soldered.
JP5A, JP5B,
JP5C, JP5N
Open Disable the phase antialiasing filter in the IAP, IBP, ICP, and INP data path. By default, they are open.
JP6 Soldered Connects C41 to the REF pin of the ADE7878. By default, it is soldered. JP6A, JP6B,
JP6C, JP6N
Open Disable the phase antialiasing filter in the IAN, IBN, ICN, and INN data path. By default, they are open.
JP7 Closed Enables the supply to the microcontroller. When open, takes out the supply to the microcontroller. By default, it is closed.
JP7A, JP7B,
JP7C
Open Disable the resistor divider in the VAP, VBP, and VCP data path. By default, they are open.
JP7N Open Disables the antialiasing filter in the VN data path. By default, it is open.
JP8 Open Sets the microcontroller in flash memory programming mode. By default, it is open.
JP8A, JP8B,
JP8C
Open Connect VAP, VBP, and VCP to AGND. By default, they are open.
JP8N Closed Connects VN to AGND. By default, it is closed.
JP9 Open When closed, signals the microcontroller to declare all I/O pins as outputs. It is used when another
microcontroller is used to manage the ADE7878 through the P38 socket. By default, it is open. JP9A, JP9B,
JP9C
Soldered to Pin
1 (AGND) Connect the ground of antialiasing filters in the VAP, VB, and VCP data path to AGND or VN. By default,
they are soldered to AGND. JP10 Open Connects the external voltage reference to ADE7878. By default, it is open. JP11 Soldered to Pin
1
Connects the CLKIN pin of the ADE7878 to a 16,384 MHz crystal (Pin 1 of JP11) or to an external clock
input provided at J1. By default, it is soldered to Pin 1.
JP12 Soldered to Pin
3 (AGND) Connects DGND (Pin 2 of JP12) of the ADE7878 to ground (Pin 1 of JP12) or to AGND (Pin 3 of JP12).
JP35, JP33 Open If I2C communication between the NXP LPC2368 and the ADE7878 is used, these connectors should be
closed with 0 Ω resistors, and the JP36 and JP34 connectors should be opened. By default, the SPI is the
communication used between the NXP LPC2368 and the ADE7878; therefore, these connectors are open. JP31, JP37 Open If HSDC communication is used, these connectors should be closed with 0 Ω resistors, and the JP35 and JP33 connectors should also be closed. By default, the SPI is the communication used between the NXP
LPC2368 and the ADE7878; therefore, these connectors are open.
JP36, JP34,
JP32, JP38
Closed with
0 Ω resistors If SPI communication is used between the NXP LPC2368 and the ADE7878, these connectors should be
closed and JP35, JP33, JP31, and JP37 should be opened. By default, the SPI is the communication used
between the NXP LPC2368 and the ADE7878; therefore, these connectors are closed.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 6 of 36
SETTING UP THE EVALUATION BOARD AS AN ENERGY METER
Figure 6 shows a typical setup for the ADE7878 evaluation board. In this example, an energy meter for a 4-wire, 3-phase distribution system is shown. Current transformers are used to sense the phase and neutral currents and are connected as shown in Figure 6. The line voltages are connected directly to the evaluation board as shown. Note that the state of all jumpers must match the states shown in Figure 6, keeping in mind that the board is supplied from two different 3.3 V power supplies, one for the ADE7878 domain, VDD, and one for the NXP LPC2368 domain, MCU_VDD. Because the two domains are isolated to ensure that there is no electrical connection between the high voltage test circuit and the control circuit, the power supplies should have floating voltage outputs. The evaluation board is connected to the PC using a regular USB cable supplied with the board. When the evaluation board is powered up and connected to the PC, the enumeration process begins and the PC recognizes new hardware and asks to install the appropriate driver. The drive can be found in the VirCOM_ Driver_XP folder of the CD. After the driver is installed, the supplied evaluation software can be launched. The next section describes the ADE7878 evaluation software in detail and how it can be installed and uninstalled.
Activating Serial Communication Between the ADE7878 and the NXP LPC2368
The ADE7878 evaluation board is supplied with communica-tion between the ADE7878 and the NXP LPC2368 that is set through the SPI ports. The JP32, JP34, JP36, and JP38 jumpers are closed using 0 Ω resistors, and the JP31, JP33, JP35, and JP37 jumpers are open. The SPI port should be chosen as the active port in the ADE7878 control panel.
Communication between the ADE7878 and the NXP LPC2368 is also possible using the I2C ports. To accomplish this, the JP31, JP33, JP35, and JP37 jumpers should be closed using 0 Ω resistors, and the JP32, JP34, JP36, and JP38 jumpers should be open. In this case, the I2C port should be chosen as the active port in the ADE7878 control panel (see Table 2).
Table 2. Jumper State to Activate SPI or I2C Communication
Active Communication
Jumpers Closed with 0 Ω Resistors
Jumpers Open
SPI (Default)
JP32, JP34, JP36, JP38
JP31, JP33, JP35, JP37
I2C
JP31, JP33, JP35, JP37
JP32, JP34, JP36, JP38
Using the Evaluation Board with Another Microcontroller
It is possible to manage the ADE7878 mounted on the evalua-tion board with a different microcontroller mounted on another board. The ADE7878 can be connected to this second board through one of two connectors: P11 or P38. P11 is placed on the same power domain as the ADE7878. P38 is placed on the power domain of the NXP LPC2368 and communicates with the ADE7878 through the isocouplers. If P11 is used, the power domain of the NXP LPC2368 should not be supplied at P12. If P38 is used, a conflict may arise with the NXP LPC2368 I/O ports. The following two options are provided to deal with this situation:
• One option is to keep the NXP LPC2368 running and close JP9. This tells the NXP LPC2368 to set all of its I/Os high to allow the other microcontroller to communicate with the ADE7878. After JP9 is closed, the S2 reset button should be pressed low to force the NXP LPC2368 to reset. This is necessary because the state of JP9 is checked inside the NXP LPC2368 program only once after reset.
• The other option is to cut the power supply of the NXP LPC2368 by disconnecting JP7.
Evaluation Board User Guide UG-146
Rev. 0 | Page 7 of 36
P1IAPIANIAPIANVAPVOLTAGE SOURCEGNDP9VDDJP1A, JP2A = OPENJP3A, JP4A = CLOSEDJP5A, JP6A = OPENNEUTRALPHASE BPHASE CLOADNEUTRALVOLTAGE SOURCEMCU_GNDP12MCU_VDDJP1, JP2 = CLOSEDR1R2P2IBPIBNIBPIBNJP1B, JP2B = OPENJP3B, JP4B = CLOSEDJP5B, JP6B = OPENR3R4P3ICPICNICPICNJP1C, JP2C = OPENJP3C, JP4C = CLOSEDJP5C, JP6C = OPENR5R6P4INPINNINPINNJP1N, JP2N = OPENJP3N, JP4N = CLOSEDJP5N, JP6N = OPENJP7A, JP8A = OPENR7R8P8VAPR26R29R32C32VBPJP7B, JP8B = OPENP7VBPR27R30R33C33VCPJP7C, JP8C = OPENJP7N = OPENJP8N = CLOSEDP6VCPR28R31R34C34C34VNP5VNR2509078-006
Figure 6. Typical Setup for the ADE7878 Evaluation Board
UG-146 Evaluation Board User Guide
Rev. 0 | Page 8 of 36 EVALUATION BOARD SOFTWARE
The ADE7878 evaluation board is supported by Windows®
based software that allows the user to access all the functionality
of the ADE7878. The software communicates with the NXP
LPC2368 microcontroller using the USB as a virtual COM port.
The NXP LPC2368 communicates with the ADE7878 to process the requests that are sent from the PC. INSTALLING AND UNINSTALLING THE ADE7878
SOFTWARE
The ADE7878 software is supplied on one CD-ROM. It contains two projects: one that represents the NXP LPC2368
project and one LabVIEW™ based program that runs on the PC.
The NXP LPC2368 project is already loaded into the processor, but the LabVIEW based program must be installed. 1. To install the ADE7878 software, place the CD-ROM in the CD-ROM reader and double-click
LabView_project\installation_files\setup.exe. This
launches the setup program that automatically installs all the software components, including the uninstall
program, and creates the required directories. 2. To launch the software, go to the Start/Programs/ ADE7878 Eval Software menu and click ADE7878
Eval Software.
Both the ADE7878 evaluation software program and the NI
run-time engine are easily uninstalled by using the Add/ Remove Programs option in the control panel. 1. Before installing a new version of the ADE7878 evaluation software, first uninstall the previous version. 2. Select the Add/Remove Programs option in the Windows control panel. 3. Select the program to uninstall and click the Add/Remove
button. FRONT PANEL When the software is launched, the Front Panel is opened. This panel contains three areas: the main menu at the left, the sub-
menu at the right, and a box that displays the name of the communication port used by the PC to connect to the
evaluation port, also at the right (see Figure 7). The COM port used to connect the PC with the evaluation board must be selected first. The program displays a list of the
active COM ports, allowing you to select the right one. To learn
what COM port is used by the evaluation board, launch the
Windows Device Manager (the devmgmt.msc file) in the Run
window on the Windows Start menu. By default, the program offers the option of searching for the COM port. Serial communication between the microcontroller and the
ADE7878 is introduced using a switch. By default, the SPI port is used. Note that the active serial port must first be set in the
hardware. See the Activating Serial Communication Between the ADE7878 and the NXP LPC2368 section for details on how
to set it up. The main menu has only one choice, other than Exit, enabled,
Find COM Port. Clicking it starts a process in which the PC
tries to connect to the evaluation board using the port indicated
in the Start menu. It uses the echo function of the communica-
tion protocol (see the Managing the Communication Protocol Between the Microcontroller and the ADE7878 section). It displays the port that matches the protocol and then sets it to 115,200 baud, eight data bits, no parity, no flow control, one
stop bit. 09078-007
Figure 7. Front Panel of ADE7878 Software If the evaluation board is not connected, the port is displayed as
XXXXX. In this case, the evaluation software is still accessible, but no communication can be executed. In both cases, whether
the search for the COM port is successful or not, the cursor is
positioned back at Please select from the following options in
the main menu, Find COM Port is grayed out, and the next main menu options are enabled (see Figure 8). These options allow
you to command the ADE7878 in either the PSM0 or PSM3
power mode. The other power modes, PSM1 and PSM2, are not
available because initializations have to be made in PSM0 before the ADE7878 can be used in one of these other modes.
Evaluation Board User Guide UG-146
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Figure 8. Front Panel After the COM Port Is Identified
PSM0 MODE—NORMAL POWER MODE
Enter PSM0 Mode
When the evaluation board is powered up, the ADE7878 is in PSM3 sleep mode. When Enter PSM0 mode is selected, the microcontroller manipulates the PM0 and PM1 pins of the ADE7878 to switch it into PSM0 mode. It waits 50 ms for the circuit to power up and, if SPI communication is activated on the board, it executes three SPI write operations to Address 0xEBFF of the ADE7878 to activate the SPI port. If the operation has been correctly executed or I2C communi-cation is used, the message Configuring LPC2368 – ADE7878 communication was successful is displayed, and you must click OK to continue. The only error that may occur during this operation is communication related; if this happens, the following message is displayed: Configuring LPC2368 – ADE7878 communication was not successful. Please check the communication between the PC and ADE7878 evaluation board and between LPC2368 and ADE78xx.
Bit 1 (I2C_LOCK) of the CONFIG2[7:0] register is now set to 1 to lock in the serial port choice. Then the DICOEFF register is initialized with 0xFF8000, and the DSP of the ADE7878 is started when the software program writes RUN = 0x1. At the end of this process, the entire main menu is grayed out, and the submenu is enabled. You can now manage all functionality of the ADE7878 in PSM0 mode. To switch the ADE7878 to another power mode, click the Exit button on the submenu. The state of the Front Panel is shown in Figure 9.
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Figure 9. Front Panel After the ADE7878 Enters PSM0 Mode
Reset ADE7878
When Reset ADE78xx is selected on the Front Panel, the RESET pin of the ADE7878 is kept low for 20 ms and then is set high. If the operation is correctly executed, the message ADE7878 was reset successfully is displayed, and you must click OK to continue. The only error that may occur during this operation is communication related; if this happens, the following message is displayed: The communication between PC and ADE7878 evaluation board or between LPC2368 and ADE78xx did not function correctly. There is no guarantee the reset of ADE7878 has been performed.
Configure Communication
When Configure Communication is selected on the Front Panel, the panel shown in Figure 10 is opened. This panel is useful if an ADE7878 reset has been performed and the SPI is no longer the active serial port. Select the SPI port by clicking the I2C/SPI Selector button and then click OK to update the selection and lock the port. If the port selection is successful, the message, Configuring LPC2368 – ADE7878 communica-tion was successful, is displayed, and you must click OK to continue. If a communication error occurs, the message, Configuring LPC2368 – ADE7878 communication was not successful. Please check the communication between the PC and ADE7878 evaluation board, is displayed.
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Figure 10. Configure Communication Panel The CONFIG2[7:0] register is written with Bit 1 (I2C_LOCK) set to 1 so that you do not need to remember to set it once the communication is set. The contents of CONFIG2[7:0] are then read back and displayed with Bit 1 (I2C_LOCK). To close the panel, click the Exit button; the cursor is positioned at Please select from the following options in the submenu of the Front Panel.
Total Active Power
When Total Active Power is selected on the Front Panel, the panel shown in Figure 11 is opened. The screen has an upper half and a lower half: the lower half shows the total active power data path of one phase, and the upper half shows bits, registers, and commands necessary to power management. 09078-011
Figure 11. Total Active Power Panel
The Active Data Path button manages which data path is shown in the bottom half. Some registers or bits, like the WTHR0[23:0] register or Bit 0 (INTEN) of the CONFIG[15:0] register, are common to all data paths, independent of the phase shown. When these registers are updated, all the values in all data paths are updated. The HPFDIS[23:0] register is included twice in the data path, but only the register value from the current data path is written into the ADE7878. All the other instances take this value directly.
1. Click the Read Configuration button to cause all registers that manage the total active power to be read and displayed. Registers from the inactive data paths are also read and updated.
2. Click the Write Configuration button to cause all registers that manage the total active power to be written into the ADE7878. Registers from the inactive data paths are also written. The ADE78xx status box shows the power mode that the ADE7878 is in (it should always be PSM0 in this window), the active serial port (it should always be SPI), and the CHECKSUM[31:0] register. After every read and write operation, the CHECKSUM[31:0] register is read and its contents displayed.
3. Click the CFx Configuration button to open a new panel (see Figure 12). This panel gives access to all bits and registers that configure the CF1, CF2, and CF3 outputs of the ADE7878. The Read Setup and Write Setup buttons update and display the CF1, CF2, and CF3 output values.
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Figure 12. CFx Configuration Panel Like the Total Active Power panel, the CHECKSUM[31:0] register is read back whenever a read or write operation is executed in the CFx Configuration panel. To select more than one option for a TERMSELx bit in the COMPMODE [15:0] register, press the CTRL key while clicking the options you want.
Clicking the Exit button closes the panel and redisplays the Total Active Power panel. When the Read Energy Registers button in the Total Active Power panel is clicked, a new panel is opened (see Figure 13). This panel gives access to bits and registers that configure the energy accumulation. The Read Setup and Write Setup buttons update and display the bit and register values.
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The CHECKSUM[31:0] register is read back whenever a read or write operation is executed in the Read Energy Registers panel. Clicking the Read all energy registers button causes all energy registers to be read immediately, without regard to the modes in which they function. 09078-013
Figure 13. Read Energy Registers Panel The panel also gives the choice of reading the energy registers synchronous to CFx interrupts (pulses) or using line cycle accumulation mode. When the Read energy registers synchronous with CF1 pulses button is clicked, the following happens:
1. The STATUS0[31:0] register is read and then written back to so that all nonzero interrupt flag bits are cancelled.
2. Bit 14 (CF1) in the MASK0[31:0] register is set to 1, and the interrupt protocol is started (see the Managing the Communication Protocol Between the Microcontroller and the ADE7878 section for protocol details).
3. The microcontroller then waits until the IRQ0 pin goes low. If the wait is longer than the timeout you indicate in 3 sec increments, the following error message is displayed: No CF1 pulse was generated. Verify all the settings before attempting to read energy registers in this mode!
4. When the IRQ0 pin goes low, the STATUS0[31:0] register is read and written back to cancel Bit 14 (CF1); then the energy registers involved in the CF1 signal are read and their contents are displayed. A timer in 10 ms increments can be used to measure the reaction time after the IRQ0 pin goes low.
5. The operation is repeated until the button is clicked again.
The process is similar when the other CF2, CF3, and line accum-ulation (Read Energy Registers panel) buttons are clicked. It is recommended to always use a timeout when dealing with interrupts. By default, the timeout is set to 10 (indicating a 30 sec timeout), and the timer is set to 0 (indicating that the STATUSx[31:0] and energy registers are read immediately after the IRQ0 pin goes low).
When clicked on the Front Panel, the Total Reactive Power, Fundamental Active Power, and Fundamental Reactive Power buttons open panels that are very similar to the Total Active Power panel. These panels are shown in Figure 14, Figure 15, and Figure 16.
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Figure 14. Total Reactive Power Panel 09078-015
Figure 15. Fundamental Active Power Panel 09078-016
Figure 16. Fundamental Reactive Power Panel
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Apparent Power
When Apparent Power is selected on the Front Panel, a new panel is opened (see Figure 17). Similar to the other panels that deal with power measurement, this panel is divided into two parts: the lower half shows the apparent power data path of one phase and the ADE7878 status; the upper half shows the bits, registers, and commands necessary to power management. 09078-017
Figure 17. Apparent Power Panel
Current RMS
When RMS Current is selected on the Front Panel, a new panel is opened (see Figure 18). All data paths of all phases are available. 09078-018
Figure 18. Current RMS panel Clicking the Read Setup button causes a read of all registers shown in the panel. Clicking the Write Setup button causes writes to the xIRMSOS[23:0] registers.
You can use the Start Digital Signal Processor and Stop Digital Signal Processor buttons to manage the Run[15:0] register and the Read xIRMS registers button, which uses the ZXIA, ZXIB, and ZXIC interrupts at the IRQ1 pin, to read the xIRMS[23:0]registers 500 consecutive times and then compute and display their average. If no interrupt occurs for the time indicated by the timeout (in 3 sec increments), the following message is displayed: No ZXIA, ZXIB or ZXIC interrupt was generated. Verify at least one sinusoidal signal is provided between IAP-IAN, IBP-IBN or ICP-ICN pins. A delay can be introduced (in 10 ms increments) between the time the IRQ1 pin goes low and the moment the xIRMS registers are read. The operation is repeated until the button is clicked again.
Mean Absolute Value Current
When Mean Absolute Value Current is selected on the Front Panel, a new panel is opened (see Figure 19). When the Read xIMAV registers button is clicked, the xIMAV[19:0] registers are read 10 consecutive times, and their average is computed and displayed. After this operation, the button is returned to high automatically. The ADE7878 status is also displayed. 09078-019
Figure 19. Mean Absolute Value Current Panel
Voltage RMS
When RMS Voltage is selected on the Front Panel, the Voltage RMS panel is opened (see Figure 20). This panel is very similar to the Current RMS panel. Clicking the Read Setup button executes a read of the xVRMSOS[23:0] and xVRMS[23:0] registers.
Clicking Write Setup writes the xVRMSOS[23:0] registers into the ADE7878. The Start Digital Signal Processor and Stop Digital Signal Processor buttons manage the Run[15:0] register. When the Read xVRMS registers button is clicked, the xVRMS[23:0] registers are read 500 consecutive times and the average is displayed. The operation is repeated until the button is clicked again. Note that the ZXVA, ZXVB, and ZXVC zero-crossing interrupts are not used in this case because they are disabled when the voltages go below 10% of full scale. This allows rms voltage registers to be read even when the phase voltages are very low.
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Figure 20. Voltage RMS Panel
Power Quality
The Power Quality panel is accessible from the Front Panel and is divided into two parts (see Figure 21). The lower part displays registers that manage the power quality measurement functions for the Active Measurement button in the upper part of the panel. The upper part also displays the ADE7878 status and the buttons that manage the measurements.
When the READ CONFIGURATION button is clicked, all power quality registers (MASK1[31:0], STATUS1[31:0], PERIOD[15:0], MMODE[7:0], ISUM[27:0], OVLVL[23:0], OILVL[23:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], SAGLVL[23:0], SAGCYC[7:0], ANGLE0[15:0], ANGLE1[15:0], ANGLE2[15:0], COMPMODE[15:0], CHECKSUM[31:0], and PEAKCYC[7:0]) are read, and the ones belonging to the active panel are displayed. Based on the PERIOD[15:0] register, the line frequency is computed and displayed in the lower part of the panel, in Zero Crossing Measurements. Based on the ANGLEx[15:0] registers, cos(ANGLEx) is computed and displayed in the Time Intervals Between Phases panel that is accessible from the Active Measurement Zero Crossing dropdown box (see Figure 21).
When the WRITE CONFIGURATION button is clicked, MMODE[7:0], OVLVL[23:0], OILVL[23:0], SAGLVL[23:0], SAGCYC[7:0], COMPMODE[15:0], and PEAKCYC[7:0] are written into the ADE7878, and CHECKSUM[31:0] is read back and displayed in the CHECKSUM[31:0] box at the top of the upper part of the panel. 09078-021
Figure 21. Power Quality Zero-Crossing Measurements Panel When the WAIT FOR INTERRUPTS button is clicked, the interrupts that you have enabled in the MASK1[31:0] register are monitored. When the IRQ1 pin goes low, the STATUS1[31:0] register is read and its bits are displayed. The ISUM[27:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], ANGLE0[15:0], ANGLE1[15:0], and ANGLE2[15:0] registers are also read and displayed. A timeout should be introduced in 3 sec increments to ensure that the program does not wait indefinitely for interrupts. A timer (in 10 ms increments) is provided to allow reading of the registers with a delay from the moment the interrupt is triggered.
The Active Measurement Zero Crossing button gives access to the Zero Crossing, Neutral Current Mismatch, Overvoltage and Overcurrent Measurement, Peak Detection, and Time Intervals Between Phases panels (see Figure 21 through Figure 25). The line frequency is computed using the PERIOD[15:0] register, based on the following formula: ][000,256HzPeriodf= The cosine of the ANGLE0[15:0], ANGLE1[15:0], and ANGLE2[15:0] measurements is computed using the following formula: =000,256×360×)(fANGLExcosANGLExcos
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Figure 22. Neutral Current Mismatch Panel 09078-023
Figure 23. Overvoltage and Overcurrent Measurements Panel 09078-024
Figure 24. Peak Detection Panel 09078-025
Figure 25. Time Intervals Between Phases Panel
Waveform Sampling
The Waveform Sampling panel (see Figure 26) is accessible from the Front Panel and uses the HSDC port to acquire data from the ADE7878 and display it. It can be accessed only if the communication between the ADE7878 and the NXP LPC2368 is through the I2C. See the Activating Serial Communication Between the ADE7878 and the NXP LPC2368 section for details on how to set I2C communication on the ADE7878 evaluation board. 09078-026
Figure 26. Waveform Sampling Panel
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The HSDC transmits data to the NXP LPC2368 at 4 MHz because this is the maximum speed at which the slave SPI of the NXP LPC2368 can receive data. The panel contains some switches that must be set before acquiring data.
• One switch chooses the quantities that are displayed: phase currents and voltages or phase powers. For every set of quantities, only one can be acquired at a time. This choice is made using the Select Waveform button.
• A second switch allows acquired data to be stored in files for further use. This switch is set with the ACQUIRE DATA button.
• The acquisition time should also be set before an acquis-ition is ordered. By default, this time is 150 ms. It is unlimited for phase currents and voltages and for phase powers. The NXP LPC2368 executes in real time three tasks using the ping pong buffer method: continuously receiving data from HSDC, storing the data into its USB memory, and sending the data to the PC. Transmitting seven phase currents and voltages at 4 MHz takes 103.25 μs (which is less than 125 μs); therefore, the HSDC update rate is 8 kHz (HSDC_CFG = 0x0F). Transmitting nine phase powers takes 72 μs (again, less than 125 μs); therefore, the HSDC update rate is also 8 kHz (HSDC_CGF = 0x11).
To start the acquisition, click the ACQUIRE DATA button. The data is displayed on one plot. If you click the Write waveforms to file?/No writing to files switch to enable the writing of waveforms to a file, the program asks for the name and location of the files before storing the waveform.
Checksum Register
The Checksum Register panel is accessible from the Front Panel and gives access to all ADE7878 registers that are used to compute the CHECKSUM[31:0] register (see Figure 27). You can read/write the values of these registers by clicking the Read and Write buttons. The LabView program estimates the value of the CHECKSUM[31:0] register and displays it whenever one of the registers is changed. When the Read button is pressed, the registers are read and the CHECKSUM[31:0] register is read and its values displayed. This allows you to compare the value of the CHECKSUM[31:0] register estimated by LabView with the value read from the ADE7878. The values should always be identical. 09078-027
Figure 27. Checksum Register Panel
All Registers Access
The All Registers Access panel is accessible from the Front Panel and gives read/write access to all ADE7878 registers. Because there are many, the panel can scroll up and down and has multiple read, write, and exit buttons (see Figure 28 and Figure 29). The registers are listed in columns in alphabetical order, starting at the upper left. The panel also allows you to save all control registers into a data file by clicking the Save All Regs into a file button. By clicking the Load All Regs from a file button, you can load all control registers from a data file. Then, by clicking the Write All Regs button, you can load these values into the ADE7878. The order in which the registers are stored into a file is shown in the Control Registers Data File section. 09078-028
Figure 28. Panel Giving Access to All ADE7878 Registers (1)
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Figure 29. Panel Giving Access to All ADE7878 Registers (2)
Quick Startup
The Quick Startup panel is accessible from the Front Panel and can be used to rapidly initialize a 3-phase meter (see Figure 30). 09078-030
Figure 30. Panel Used to Quickly Set Up the 3-Phase Meter The meter constant (MC, in impulses/kWh), the nominal voltage (Un, in V rms units), the nominal current (In, in A rms units), and the nominal line frequency (fn, in either 50 Hz or 60 Hz) must be introduced in the panel controls. Then phase voltages and phase currents must be provided through the relative sensors.
Clicking the Begin Computations button starts the program that reads rms voltages and currents and calculates the full-scale voltage and currents used to further initialize the meter. This process takes 7 sec as the program reads the rms voltages 100 times and the rms currents 100 times and then averages them (this is because the PC reads the rms values directly and cannot synchronize the readings with the zero crossings).
The program then computes the full-scale voltages and currents and the constants that are important for setting up the ADE7878: nominal values (n), CFDEN, WTHR1, VARTHR1, VATHR1 and WTHR0, VARTHR0, and VATHR0. At this point, you can overwrite these values. You can also click the Update Registers button to cause the program to do the following:
• Initialize the CFxDEN and xTHR registers
• Enable the CF1 pin to provide a signal proportional to the total active power, the CF2 pin to provide a signal proportional to the total reactive power, and the CF3 pin to provide a signal proportional to the apparent power.
Throughout the program, it is assumed that PGA gains are 1 (for simplicity) and that the Rogowski coil integrators are disabled. You can enter and modify the PGAs and enable the integrators before executing this quick startup if necessary.
At this point, the evaluation board is set up as a 3-phase meter, and calibration can be executed. To store the register initializa-tions, click the Save All Regs into a file button in the All Registers Access panel. After the board is powered down and then powered up again, the registers can be loaded into the ADE7878 by simply loading back the content of the data file. To do this, click the Load All Regs from a file button in the All Registers Access panel.
PSM2 Settings
The PSM2 Settings panel, which is accessible from the Front Panel, gives access to the LPOILVL[7:0] register that is used to access PSM2 low power mode (see Figure 31). You can manipulate its LPOIL[2:0] and LPLINE[4:0] bits. The value shown in the LPOILVL[7:0] register is composed from these bits and then displayed. Note that you cannot write a value into the register by writing a value in the LPOILVL[7:0] register box.
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Figure 31. PSM2 Settings Panel
PSM1 MODE
Enter PSM1 Mode
When Enter PSM1 mode is selected on the Front Panel, the microcontroller manipulates the PM0 and PM1 pins of the ADE7878 to switch the ADE7878 into PSM1 reduced power mode. Then, the submenu allows access only to the Mean Absolute Value Current function because this is the only ADE7878 functionality available in this reduced power mode (see Figure 32). 09078-032
Figure 32. Front Panel After the ADE7878 Enters PSM1 Mode
Mean Absolute Value Current in PSM1 Mode
The Mean Absolute Value Current panel, which is accessible from the Front Panel when Enter PSM1 mode is selected, is very similar to the panel accessible in PSM0 mode (see the Mean Absolute Value Current section for details). The only difference is that ADE7878 status does not show the CHECKSUM[31:0] register because it is not available in PSM1 mode (see Figure 33) 09078-033
Figure 33. Mean Absolute Value Currents Panel in PSM1 Mode
PSM2 MODE
Enter PSM2 Mode
When Enter PSM2 mode is selected on the Front Panel, the microcontroller manipulates the PM0 and PM1 pins of the ADE7878 to switch the ADE7878 into PSM2 low power mode. Then the submenu allows access only to the Phase Current Monitoring function because this is the only ADE7878 functionality available in this low power mode. 09078-034 Figure 34. Front Panel After the ADE7878 Enters PSM2 Mode
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Phase Current Monitoring
The Phase Current Monitoring panel is accessible from the Front Panel when Enter PSM2 mode is selected; it allows you to display the state of the IRQ0and IRQ1 pins because, in PSM2 low power mode, the ADE7878 compares the phase currents against a threshold determined by the LPOILVL[7:0] register (see Figure 35). Clicking the READ STATUS OF IRQ0 AND IRQ1 PINS button reads the status of these pins and displays and interprets the status.
This operation is managed by the LPOILVL[7:0] register and can be modified only in PSM0 mode. The panel offers this option by switching the ADE7878 into PSM0 mode and then back to PSM2 mode when one of the READ LPOILVL/WRITE LPOILVL buttons is clicked. To avoid toggling both the PM0 and PM1 pins at the same time during this switch, the ADE7878 is set to PSM3 when changing modes.
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Figure 35. Panel Managing Current Monitoring in PSM2 Mode
PSM3 MODE
Enter PSM3 Mode
In PSM3 sleep mode, most of the internal circuits of the ADE7878 are turned off. Therefore, no submenu is activated while in this mode. You can click the Enter PSM0 mode, Enter PSM1 mode, or Enter PSM2 mode button to set the ADE7878 to one of these power modes.
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MANAGING THE COMMUNICATION PROTOCOL BETWEEN THE MICROCONTROLLER AND
THE ADE7878
In this section, the protocol commands are listed that have been
implemented to manage the ADE7878 from the PC using the
microcontroller. The microcontroller is a pure slave during the communication
process. It receives a command from the PC, executes the
command, and sends an answer to the PC. The PC should wait for the answer before sending a new command to the micro-
controller.
Table 3. Echo Command—Message from the PC to the Micro-
controller
Byte Description
0 A = 0x41
1 N = number of bytes transmitted after this byte
2 Data Byte N − 1 (MSB)
3 Data Byte N − 2 4 Data Byte N − 3 … …
N Data Byte 1 N + 1 Data Byte 0 (LSB)
Table 4. Echo Command—Answer from the Microcontroller to
the PC
Byte Description
0 R = 0x52
1 A = 0x41
2 N = number of bytes transmitted after this byte
3 Data byte N − 1 (MSB)
4 Data byte N − 2
… …
N + 1 Data Byte 1 N + 2 Data Byte 0 (LB)
Table 5. Power Mode Select—Message from the PC to the
Microcontroller
Byte Description
0 B = 0x42, change PSM mode 1 N = 1
2 Data Byte 0: 0x00 = PSM0
0x01 = PSM1
0x02 = PSM2
0x03 = PSM3
Table 6. Power Mode Select—Answer from the Microcon-
troller to the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
Table 7. Reset—Message from the PC to the Microcontroller
Byte Description
0 C = 0x43, toggle the RESET pin and keep it low for at least 10 ms
1 N = 1
2 Data Byte 0: this byte can have any value
Table 8. Reset—Answer from the Microcontroller to the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
Table 9. I2C/SPI Select (Configure Communication)—
Message from the PC to the Microcontroller
Byte Description
0 D = 0x44, select I2C and SPI and initialize them; then set
CONFIG2[7:0] = 0x2 to lock in the port choice. When I2C
is selected, also enable SSP0 of the LPC2368 (used for
HSDC). 1 N = 1.
2 Data Byte 0: 0x00 = I2C, 0x01 = SPI.
Table 10. I2C/SPI Select (Configure Communication)—
Answer from the Microcontroller to the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
Table 11. Data Write—Message from the PC to the Micro-
controller
Byte Description
0 E = 0x45.
1 N = number of bytes transmitted after this byte. N can
be 1 + 2, 2 + 2, 4 + 2, or 6 + 2.
2 MSB of the address. 3 LSB of the address. 4 Data Byte N − 3 (MSN). 5 Data Byte N − 4. 6 Data Byte N − 5. … …
N + 2 Data Byte 1.
N + 3 Data Byte 0 (LSB).
Table 12. Data Write—Answer from the Microcontroller to
the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
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Table 13. Data Read—Message from the PC to the Micro-
controller
Byte Description
0 F = 0x46.
1 N = number of bytes transmitted after this byte; N = 3.
2 MSB of the address. 3 LSB of the address. 4 M = number of bytes to be read from the address above.
M can be 1, 2, 4, or 6.
Table 14. Data Read—Answer from the Microcontroller to
the PC
Byte Description
0 R = 0x52.
1 MSB of the address. 2 LSB of the address. 3 Byte 5, Byte 3, Byte 1, or Byte 0 (MSB) read at the location
indicated by the address. The location may contain 6, 4,
2, or 1 byte. The content is transmitted MSB first.
4 Byte 4, Byte 2, or Byte 0. 5 Byte 3, Byte 1. 6 Byte 2, Byte 0. 7 Byte 1. 8 Byte 0. Table 15. Interrupt Setup—Message from the PC to the
Microcontroller
Byte Description
0 J = 0x4A. 1 N = 8, number of bytes transmitted after this byte.
2 MSB of the MASK1[31:0] or MASK0[31:0] register.
3 LSB of the MASK1[31:0] or MASK0[31:0] register.
4 Byte 3 of the desired value of the MASK0[31:0] or MASK1[31:0] register.
5 Byte 2. 6 Byte 1. 7 Byte 0. 8 Time out byte: time the MCU must wait for the interrupt
to be triggered. It is measured in 3 sec increments. Time out byte (TOB) = 0 means that timeout is disabled. 9 IRQ timer: time the MCU leaves the IRQx pin low before writing back to clear the interrupt flag. It is measured in
10 ms increments.
Timer = 0 means that timeout is disabled. Table 16. Interrupt Setup—Message from the Microcon-
troller to the PC
Byte Description
0 R = 0x52.
1 Byte 3 of the STATUS0[31:0] or STATUS1[31:0] register.
If the program waited for TOB × 3 sec and the interrupt
was not triggered, then Byte 3 = Byte 2 = Byte 1 = Byte 0
= 0xFF. 2 Byte 2 of the STATUS0[31:0] or STATUS1[31:0] register.
3 Byte 1 of the STATUS0[31:0] or STATUS1[31:0] register.
4 Byte 0 of the STATUS0[31:0] or STATUS1[31:0] register.
The microcontroller executes the following operations once the
interrupt setup command is received: 1. Reads the STATUS0[31:0] or STATUS1[31:0] register
(depending on the address received from the PC) and, if it shows an interrupt already triggered (one of its bits is equal
to 1), it erases the interrupt by writing it back. 2. Writes to the MASK0[31:0] or MASK1[31:0] register with the value received from the PC. 3. Waits for the interrupt to be triggered. If the wait is more
than the timeout specified in the command, 0xFFFFFFFF
is sent back. 4. If the interrupt is triggered, the STATUS0[31:0] or STATUS1[31:0] register is read and then written back to clear it. The value read at this point is the value sent back
to the PC so that you can see the source of the interrupts. 5. Sends back the answer. Table 17. Interrupt Pins Status—Message from the PC to the
Microcontroller
Byte Description
0 H = 0x48.
1 N = 1, number of bytes transmitted after this byte.
2 Any byte. This value is not used by the program but it is
used in the communication because N must not be equal
to 0.
Table 18. Interrupt Pins Status—Answer from the Micro-
controller to the PC
Byte Description
0 R = 0x52.
1 A number representing the status of the IRQ0 and IRQ1
pins.
0: IRQ0 = low, IRQ1 = low 1: IRQ0 = low, IRQ1 = high.
2: IRQ0 = high, IRQ1 = low. 3: IRQ0 = high, IRQ1 = high.
The reason for the IRQ0 and IRQ1 order is that on the
microcontroller IO port, IRQ0= P0.1 and IRQ1 = P0.0.
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ACQUIRING HSDC DATA CONTINUOUSLY
This function acquires data from the HSDC continuously for a defined time period and for up to two variables. The microcon-troller sends data in packages of 4 kB.
Table 19 describes the protocol when two instantaneous phase currents or voltages are acquired.
Table 19. Acquire HSDC Data Continuously—Message from the PC to the Microcontroller If Phase Currents and Voltages Are Acquired
Byte
Description
0
G = 0x47.
1
N = number of bytes transmitted after this byte. N = 32.
2
0: corresponds to Byte 3 of IA. Because this byte is only a sign extension of Byte 2, it is not sent back by the microcontroller.
3
Increment_IA_Byte2. If IA is to be acquired, Byte 3, Byte 4, and Byte 5 are 1. Otherwise, they are 0.
4
Increment_IA_Byte1.
5
Increment_IA_Byte2.
6
0.
7
Increment_VA_Byte2. If VA is to be acquired, Byte 7, Byte 8, and Byte 9 are 1. Otherwise, they are 0.
8
Increment_VA_Byte1.
9
Increment_VA_Byte0.
10
0.
11
Increment_IB_Byte2. If IB is to be acquired, Byte 11, Byte 12, and Byte 13 are 1. Otherwise, they are 0.
12
Increment_IB_Byte1.
13
Increment_IB_Byte0.
14
0.
15
Increment_VB_Byte2. If VB is to be acquired, Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0.
16
Increment_VB_Byte1.
17
Increment_VB_Byte0.
18
0.
19
Increment_IC_Byte2. If IC is to be acquired, Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they are 0.
20
Increment_IC_Byte1.
21
Increment_IC_Byte0.
22
0.
23
Increment_VC_Byte2. If VC is to be acquired, Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0.
24
Increment_VC_Byte1.
25
Increment_VC_Byte0.
26
0.
27
Increment_IN_Byte2. If IN is to be acquired, Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0.
28
Increment_IN_Byte1.
29
Increment_IN_Byte0.
30
Byte 1 of M. M is a 16-bit number. The number of 32-bit samples acquired by the microcontroller is (2 × M + 1) × 67 per channel.
31
Byte 0 of M.
If two of the phase powers are to be acquired, the protocol changes (see Table 20).
Table 20. Acquire HSDC Data Continuously—Message from the PC to the Microcontroller If Phase Powers Are Acquired
Byte
Description
0
G = 0x47
1
N = number of bytes transmitted after this byte. N = 38.
2
0: corresponds to Byte 3 of AVA. Because this byte is only a sign extension of Byte 2, it is not sent back by the microcontroller.
3
Increment_AVA_Byte2. If AVA is to be acquired, Byte 3, Byte 4, and Byte 5 are 1. Otherwise, they are 0.
4
Increment_AVA_Byte1.
5
Increment_AVA_Byte2.
6
0.
7
Increment_BVA_Byte2. If BVA is to be acquired, Byte 7, Byte 8, and Byte 9 are 1. Otherwise, they are 0.
8
Increment_BVA_Byte1.
9
Increment_BVA_Byte0.
10
0.
11
Increment_CVA_Byte2. If CVA is to be acquired, Byte 11, Byte 12, and Byte 13 are 1. Otherwise, they are 0.
12
Increment_CVA_Byte1.
13
Increment_CVA_Byte0.
14
0.
15
Increment_AWATT_Byte2. If AWATT is to be acquired, Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0.
16
Increment_AWATT_Byte1.
17
Increment_AWATT_Byte0.
18
0.
19
Increment_BWATT_Byte2. If BWATT is to be acquired, then Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they are 0.
20
Increment_BWATT_Byte1.
21
Increment_BWATT_Byte0.
22
0.
23
Increment_CWATT_Byte2. If CWATT is to be acquired, Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0.
24
Increment_CWATT_Byte1.
25
Increment_CWATT_Byte0.
26
0.
27
Increment_AVAR_Byte2. If AVAR is to be acquired, Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0.
28
Increment_AVAR_Byte1.
29
Increment_AVAR_Byte0.
30
0.
31
Increment_BVAR_Byte2. If BVAR is to be acquired, then Byte 31, Byte 32, and Byte 33 are 1. Otherwise, they are 0.
32
Increment_BVAR_Byte1.
33
Increment_BVAR_Byte0.
34
0.
35
Increment_CVAR_Byte2. If CVAR is to be acquired, Byte 35, Byte 36, and Byte 37 are 1. Otherwise, they are 0.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 22 of 36
Byte
Description
36
Increment_CVAR_Byte1.
37
Increment_CVAR_Byte0.
38
Byte 1 of M. M is a 16-bit number. The number of 32-bit samples acquired by the microcontroller is (2 × M + 1) × 67 per channel.
39
Byte 0 of M.
After receiving the command, the microcontroller enables the HSDC port and acquires 67 × 7 × 4 = 1876 bytes into BUFFER0. As soon as BUFFER0 is filled, data is acquired in BUFFER1 (equal in size to BUFFER0), while 2 × 3 × 67 = 402 bytes (134 24-bit words) from BUFFER0 are transmitted to the PC. As soon as BUFFER1 is filled, data is acquired into BUFFER0 while 402 bytes from BUFFER1 are transmitted to the PC. Only the less significant 24 bits of every 32-bit instantaneous value are sent to the PC to decrease the size of the buffer sent to the PC. The most significant eight bits are only an extension of a 24-bit signed word; therefore, no information is lost. The protocol used by the microcontroller to send data to the PC is shown in Table 21.
Table 21. Acquire HSDC Data Continuously—Answer from the Microcontroller to the PC
Byte
Description
0
R = 0x52
1
Byte 2 (MSB) of Word 1
2
Byte 1 of Word 1
3
Byte 0 (LSB) of Word 1
4
Byte 2 (MSB) of Word 2
5
Byte 1 (MSB) of Word 2
…
…
402
Byte 0 (LSB) of Word 134
STARTING THE ADE7878 DSP
This function orders the microcontroller to start the DSP. The microcontroller writes to the run register with 0x1. Table 22. Start ADE7878 DSP—Message from the PC to the Microcontroller
Byte
Description
0
N = 0x4E
1
N = number of bytes transmitted after this byte; N = 1
2
Any byte
Table 23. Start ADE7878 DSP—Answer from the Micro-controller to the PC
Byte
Description
0
R = 0x52
1
~ = 0x7E, to acknowledge that the operation was successful
STOPPING THE ADE7878 DSP
This function orders the microcontroller to stop the DSP. The microcontroller writes to the run register with 0x0. Table 24. Stop ADE7878 DSP—Message from the PC to the Microcontroller
Byte
Description
0
O = 0x4F
1
N = number of bytes transmitted after this byte; N = 1
2
Any byte
Table 25. Stop ADE7878 DSP—Answer from the Micro-controller to the PC
Byte
Description
0
R = 0x52
1
~ = 0x7E to acknowledge that the operation was successful
Evaluation Board User Guide UG-146
Rev. 0 | Page 23 of 36
UPGRADING MICROCONTROLLER FIRMWARE
Although the evaluation board is supplied with the microcontroller firmware already installed, the ADE7878 evaluation software CD provides the NXP LPC2368 microcontroller project developed under the IAR embedded workbench environment for ARM. Users in possession of this tool can modify the project at will and can download it using an IAR J-link debugger. As an alternative, the executable can be downloaded using a program called Flash Magic, available on the evaluation software CD or at the following website: http://www.flashmagictool.com/. Flash Magic uses the PC COM port to download the micro-controller firmware. The procedure for using Flash Magic is as follows:
1. Plug a serial cable into connector P15 of the ADE7878 evaluation board and into a PC COM port. As an alternative, use the ADE8052Z-DWDL1 ADE downloader from Analog Devices, Inc., together with a USB cable.
2. Launch the Device Manager under Windows XP by writing devmgmt.msc into the Start/Run box. This helps to identify which COM port is used by the serial cable.
3. Plug the USB2UART board into the P15 connector of the ADE7878 evaluation board with the VDD pin of the USB2UART aligned at Pin 1 of P15.
4. Connect Jumper JP8. The P2.10/EINT0 pin of the microcontroller is now connected to ground.
5. Supply the board with two 3.3 V supplies at the P10 and P12 connectors.
6. Press and release the reset button, S2, on the ADE7878 evaluation board.
7. Launch Flash Magic and do the following:
a. Select a COM port (COMx as seen in the Device Manager).
b. Set the baud rate to 115,200.
c. Select the NXP LPC2368 device.
d. Set the interface to none (ISP).
e. Set the DOscillator frequency (MHz) to 12.0.
f. Select Erase all Flash + Code Rd Block.
g. Choose ADE7878_Eval_Board.hex from the \Debug\Exe project folder.
h. Select Verify after programming.
The Flash Magic settings are shown in Figure 36. 09078-036
Figure 36. Flash Magic Settings
8. Click Start to begin the download process.
9. After the process finishes, extract the JP8 jumper.
10. Reset the ADE7878 evaluation board by pressing and releasing the S2 reset button.
At this point, the program should be functional, and a USB cable can be connected to the board. When the PC recognizes the evaluation board and asks for a driver, point it to the project \VirCOM_Driver_XP folder. The ADE7878_eval_board_ vircomport.inf file is the driver.
CONTROL REGISTERS DATA FILE
Table 26 shows the order in which the control registers of the ADE7878 are stored into a data file when you click the Save All Regs into a file button in the All Registers Access panel.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 24 of 36
Table 26. Control Register Data File Content
Line Number
Register
1
AIGAIN
2
AVGAIN
3
BIGAIN
4
BVGAIN
5
CIGAIN
6
CVGAIN
7
NIGAIN
8
AIRMSOS
9
AVRMSOS
10
BIRMSOS
11
BVRMSOS
12
CIRMSOS
13
CVRMSOS
14
NIRMSOS
15
AVAGAIN
16
BVAGAIN
17
CVAGAIN
18
AWGAIN
19
AWATTOS
20
BWGAIN
21
BWATTOS
22
CWGAIN
23
CWATTOS
24
AVARGAIN
25
AVAROS
26
BVARGAIN
27
BVAROS
28
CVARGAIN
29
CVAROS
30
AFWGAIN
31
AFWATTOS
32
BFWGAIN
33
BFWATTOS
34
CFWGAIN
35
CFWATTOS
36
AFVARGAIN
37
AFVAROS
38
BFVARGAIN
39
BFVAROS
40
CFVARGAIN
41
CFVAROS
Line Number
Register
42
VATHR1
43
VATHR0
44
WTHR1
45
WTHR0
46
VARTHR1
47
VARTHR0
48
VANOLOAD
49
APNOLOAD
50
VARNOLOAD
51
VLEVEL
52
DICOEFF
53
HPFDIS
54
ISUMLVL
55
RUN
56
OILVL
57
OVLVL
58
SAGLVL
59
MASK0
60
MASK1
61
VNOM
62
LINECYC
63
ZXTOUT
64
COMPMODE
65
Gain
66
CFMODE
67
CF1DEN
68
CF2DEN
69
CF3DEN
70
APHCAL
71
BPHCAL
72
CPHCAL
73
CONFIG
74
MMODE
75
ACCMODE
76
LCYCMODE
77
PEAKCYC
78
SAGCYC
79
CFCYC
80
HSDC_CFG
81
LPOILVL
82
CONFIG2
Evaluation Board User Guide UG-146
Rev. 0 | Page 25 of 36
EVALUATION BOARD SCHEMATICS AND LAYOUT
SCHEMATIC
09078-037NOTE:MOUNT JP? DIRECTLY BELOWPAD METAL. CONNECT TO PADWITH MULTIPLE VIAS.REPEAT VIA GRID TO AGND PLANEEXTRA GROUND TP FOR PROBINGOUTPUT LED CIRCUITIRQ1BCF1CF2IRQ0BCF3DEVICE INTERFACE HEADERREFERENCE DECOUPLING AND EXTERNAL REFRESONANT CIRCUIT. THIS OPTION SHOULD BE PLACED ASXTAL CKTBY DEFAULT SELECT OPTION A
TO COMPLETE PARALLELCLOSE TO DEVICE AS POSSIBLE.C27C26C25C6C4NPC41NPC5NPC321C38C43C42C40C7C2NPC8NPC1NPC44ACCR5ACCR4ACCR3ACCR2ACCR1RSBR43R42R41R40R3921E8NR69R84R85R70R68231JP12R35R361TP293421S121JP321JP421JP521JP621JP101TP49231A11TP511TP501TP341TP361TP381TP371TP391TP351TP331TP321TP311TP301TP281TP271TP261TP251TP241TP231TP2221JP221P10R371TP151TP141TP139876543231303292827262524232221202191817161514131211101P111826192223393641732PAD3837322915161314912785628273534332425U1213Q5213Q2213Q4213Q3213Q121JP121P9R381TP921P521JP7NR2521JP8N54321CLKIN21Y1231JP11DGND_DCLKOUTIRQ0B20PF20PF3PIN_SOLDER_JUMPERBLKCLKINAMP227699-2BLK1.0UFIBP10KCF2CMD28-21VGCTR8T1BLKVDD_FBLKVDD_F10UFVDD0.1UF0.1UF0.1UFBLKBLKBLKVDD2VDD0BLKJPR04021500 OHMSVNBERG69157-1021KBERG69157-102BLKBLKREFEXT_CLKINBLKBLKBLKBLKCF1SSB/HSAMOSI/SDACF3/HSCLKIRQ0B16.384MHZIRQ1BPM0PM1RESETBCLKOUTEXT_CLKINSAMTSW-1-30-08-GDSCLK/SCLCF2MISO/HSDFDV302P10KCF3/HSCLKFDV302PFDV302P10KVDD2CF1JPR0402JPR0402BLKWEILAND25.161.0253VDD2DVDDAVDD3PIN_SOLDER_JUMPERBLKBLKB3S1000BLKBLKBLKBLKPAD_CNVDD_FICNPM0PM1VCPVBPVAPCLKININPINNVNCF2IRQ0BBERG69157-102BLKJPR0402ADR280ARTZ10K499499499ICPIANIAPRESETBFDV302P4994992VDD2FDV302PIRQ1B10KCMD28-21VGCTR8T1CMD28-21VGCTR8T1CMD28-21VGCTR8T1CMD28-21VGCTR8T1XREF10UFVDD_F10UFVDD_F10KJPR04024.7UFMOSI/SDAIBNADE7858CPZSCLK/SCLPAD_CNBLKSSB/HSAMISO/HSD0.1UF4.7UFCF3/HSCLKCF1IRQ1BDVDDCLKOUTREFAVDDBERG69157-102BLK0.22UF0.22UF10KVDD20.1UFVDDBLK4.7UFDGND_DWEILAND25.161.025310KWEILAND25.161.0253VN_IN22NFAGNDDGNDBCOMADGNDDGNDAGNDAGNDAGNDDGNDAGNDAGNDAGNDV-V+VODGNDSCLK_SCLSS_N_HSAMISO_HSDMOSI_SDAIRQ1_N_SBSDAIRQ0_N_SBSCLRESET_NCF3_HSCLKCF2VNINNINPCF1CLKOUTCLKINVDDVAPVBPVCPREFIN_OUTDVDDPM1PM0PADAVDDAGNDDGNDICNICPIBNIBPIANIAPDGNDGDSDGNDGDSDGNDGDSDGNDGDSDGNDGDSDGNDAGNDAGNDAGNDAGNDAGNDAGNDBCOMA Figure 37.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 26 of 36
INPUT ANTI-ALIAS AND DEVICE CONNECTIONC12C11C20C19C24C23C16C15C22C14C13C18C17C10C9C2121E2N21E1N21E2C21E1C21E1A21E2A21E1B21E2B21JP2N21JP1N21JP2C21JP1C21JP2B21JP1B21JP1A21JP2A21JP6N21JP4N21JP5N21JP3N21JP6C21JP5C21JP4C21JP3C21JP6B21JP4B21JP5B21JP3B21JP6A21JP4A21JP5A21JP3A21P421P321P121P21TP7R71TP8R23R24R15R16R81TP5R51TP6R21R22R13R14R6R4R3R12R11R20R191TP41TP31TP21TP1R17R18R2R1R10R9TBD12061500 OHMSBERG69157-102100TBD1206INN_INWEILAND25.161.0253TBD1206BERG69157-102BERG69157-102BERG69157-102WEILAND25.161.0253IBP_INIBN_INBERG69157-102BERG69157-102100TBD12061001K1KBERG69157-102BLKBERG69157-102BERG69157-102BERG69157-1021001KBLKBERG69157-102IBNIAPBERG69157-102BLK1KBLK100TBD12061KBLKBERG69157-102BERG69157-102TBD1206100INPINN1500 OHMS1500 OHMSTBD12061500 OHMSIAP_INICP100BERG69157-102IBPBERG69157-102TBD1206BERG69157-102ICN100BERG69157-102BLK1KBERG69157-1021500 OHMSIAN_IN1500 OHMSICP_INBLK1KBERG69157-1021500 OHMSICN_INWEILAND25.161.0253BERG69157-102BERG69157-102WEILAND25.161.02531500 OHMS1KBLKIAN22NF22NF22NF22NF22NF22NF22NF22NFBERG69157-102BERG69157-102INP_IN22NF22NF22NF22NF22NF22NF22NF22NFAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGND09078-043 Figure 38.
Evaluation Board User Guide UG-146
Rev. 0 | Page 27 of 36
PHASE A VOLTAGEPHASE C VOLTAGEPHASE B VOLTAGEC34C33C32R26R28R2721E8C21E8B21E8A1TP10231JP9C21P621JP8CR3121JP7CR3421P721JP8BR3021JP7BR331TP11231JP9B21JP8A1TP1221JP7A21P8231JP9AR32R2922NF3PIN_SOLDER_JUMPERBERG69157-1021K1500 OHMSWEILAND25.161.0253WEILAND25.161.0253BERG69157-1021KBLK3PIN_SOLDER_JUMPERVBP1500 OHMSVCP_INVBP_INVN100KBERG69157-1021500 OHMS1KBERG69157-102VNBLK100KBERG69157-1021M1MWEILAND25.161.02531M3PIN_SOLDER_JUMPER100KBERG69157-102VCPVNBLKVAPVAP_IN22NF22NFBCOMAAGNDAGNDAGNDAGNDAGNDAGNDBCOMAAGNDAGNDAGNDBCOMA09078-044 Figure 39.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 28 of 36
BYPASSING CONTROLLER(OPTIONAL; CUSTOMER SUPPLIED)TP FOR EVAL PROBE - DISTRIBUTE AROUND ISOLATED CIRCUITSNCD-D+GNDVBUS(5V)USB IFMRESETMCU CIRCUITUARTSHIELD D+, D-, VREF_MCU WITH GNDFROM CONN TO MCUISOLATED PSU CONNECTIONSP2_11P2_12PM0_CTRLP1_29P1_28P1_27P1_19CF3_HSCLK_ISOP2_9P2_8P2_7P2_6PM1_CTRLMCU_XT2P1_15SSB_ISOCF2_ISOP4_29IRQ1B_ISOP1_26P1_25P1_0P1_4P1_8MCU_XT1TMSP1_22P0_24P0_26MOSI_ISOGNDGNDGNDAMP227699-2CF1_ISOCF2_ISOAMP227699-2AMP227699-2CF3_HSCLK_ISOP0_20SML-LXT0805GW-TRBLK680CF3_HSCLK_ISOIRQ0B_ISOP2_1310KRTCK0.1UFWEILAND25.161.0253MCU_VDD_ISO10KBERG69157-102P2_2SAMTSW-1-30-08-GDRXDTXD10KBLKP1_31MCU_RSTSAMTECTSW10608GS4PINMCU_VDD10K27BLKMCU_VDD10UF0.1UF1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF1.5KP1_23MCU_VDDMCU_VDD10KLPC2368FBD100P0_22MCU_VDDD+D-D-_MCUD+_MCUVBUS274-1734376-8RSTOUT_NRTCX2P1_1USB_UPP4_28P3_26P3_25D+_MCUSDA_ISOIRQ_OUT_EN_ISOIRQ_IN_ENMISO_ISOSCLK_ISORESB_CTRLPM0_CTRLIRQ1B_ISOPM1_CTRLSBENB_ISOSSB_ISOTCLKTRST_NTDI10K10KP0_21P0_19P0_5D-_MCURXDTXDWPP0_4P0_9BLKBLKBLKBLKBLKBLKBLKBLKBLKBLKVBUSP2_1P2_0P2_3P2_5HSDATA_ISOMCU_XT120PFMCU_XT220PF12.000MHZMCU_RSTMCU_VDDB3S100010KP1_9P1_17P1_14P1_10P1_16MCU_VDDSAMTECTSW11008GDTMS10K10KTDITCLKRTCKTDOMCU_RST10KTDOSCL_ISOTRST_NHSA_ISOBLKBLKBLKP2_4IRQ0B_ISOMCU_RSTRESB_CTRLHSA_ISOMOSI_ISOSDA_ISOMISO_HSD_ISOSCLK_ISOSCL_ISOCF1_ISOR79R80R81TP461TP421TP431TP411P151234R82P1212C78PNC79TP161TP171TP181CF312345CF212345CF112345C72U8464849626361605947585756987625242998309981807978777695908988878632339434353637383940434445212093929175535251507473706968676665642726828517141001618521341928547196134284101215314155728397112223C75C73C76C77C83C84C80C81C82R78P131101112131415161718192203456789R44R45R75R73R72R71R83TP521TP441TP541TP451TP551TP531TP481TP471TP401S21243R74C74Y212C70C71CR6CAR77P14123456R76JP712P381101112131415161718192202122232425262728293303132456789P2_10TRST_NTCKP1_18_USB_UP_LED_PWM1_1VBATVREFVDDAVDD_DCDC_3V3_3VDD_DCDC_3V3_2VDD_DCDC_3V3_1VDD_3V3_4VDD_3V3_3VDD_3V3_2VDD_3V3_1VSSAVSSP1_0_ENET_TXD0P2_12_EINT2_MCIDAT2_I2STX_WSP2_11_EINT1_MCIDAT1_I2STX_CLKP2_10_EINT0P2_9_USB_CONNECT_RXD2_EXTIN0P2_8_TD2_TXD2_TRACEPKT3P2_7_RD2_RTS1_TRACEPKT2P2_6_PCAP1_0_RI1_TRACEPKT1P2_5_PWM1_6_DTR1_TRACEPKT0P2_4_PWM1_5_DSR1_TRACESYNCP2_3_PWM1_4_DCD1_PIPESTAT2P2_2_PWM1_3_CTS1_PIPESTAT1P2_1_PWM1_2_RXD1_PIPESTAT0P2_0_PWM1_1_TXD1_TRACECLKP1_31_SCK1_AD0_5P1_30_VBUS_AD0_4P1_29_PCAP1_1_MAT0_1P1_28_PCAP1_0_MAT0_0P1_27_CAP0_1P1_26_PWM1_6_CAP0_0P1_25_MAT1_1P1_24_PWM1_5_MOSI0P1_23_PWM1_4_MISO0P1_22_MAT1_0P1_21_PWM1_3_SSEL0P1_20_PWM1_2_SCK0P1_19_CAP1_1P1_17_ENET_MDIOP1_16_ENET_MDCP1_15_ENET_REF_CLKP1_14_ENET_RX_ERP1_10_ENET_RXD1P1_9_ENET_RXD0P1_8_ENET_CRSP1_4_ENET_TX_ENP1_1_ENET_TXD1RTCX2XTAL2RSTOUT_NTDORTCKP2_13_EINT3_MCIDAT3_I2STX_SDAP4_29_MAT2_1_RXD3P4_28_MAT2_0_TXD3P3_26_MAT0_1_PWM1_3P3_25_MAT0_0_PWM1_2P0_30_USB_DNP0_29_USB_DPP0_28_SCL0P0_27_SDA0P0_26_AD0_3_AOUT_RXD3P0_25_AD0_2_I2SRX_SDA_TXD3P0_24_AD0_1_I2SRX_WS_CAP3_1P0_23_AD0_0_I2SRX_CLK_CAP3_0P0_22_RTS1_MCIDAT0_TD1P0_21_RI1_MCIPWR_RD1P0_20_DTR1_MCICMD_SCL1P0_19_DSR1_MCICLK_SDA1P0_18_DCD1_MOSI0_MOSIP0_17_CTS1_MISO0_MISOP0_16_RXD1_SSEL0_SSELP0_15_TXD1_SCK0_SCKP0_11_RXD2_SCL2_MAT3_1P0_10_TXD2_SDA2_MAT3_0P0_9_I2STX_SDA_MOSI1_MAT2_3P0_8_I2STX_WS_MISO1_MAT2_2P0_7_I2STX_CLK_SCK1_MAT2_1P0_6_I2SRX_SDA_SSEL1_MAT2_0P0_5_I2SRX_WS_TD2_CAP2_1P0_4_I2SRX_CLK_RD2_CAP2_0P0_3_RXD0P0_2_TXD0P0_1_TD1_RXD3_SCL1P0_0_RD1_TXD3_SDA1RTCX1XTAL1RESET_NTMSTDI09078-038 Figure 40.
Evaluation Board User Guide UG-146
Rev. 0 | Page 29 of 36
<- DUTISOLATION CIRCUITI2C/HSDC CONFIGSPI CONFIGSPI CONFIGI2C/HSDC CONFIGMCU ->0SDA_ISOSDA_ISO0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UFSB_ENBSCL_ISOSCLSDASCLKSSBMOSISCLK_ISOMOSI_ISOSSB_ISOIRQ_OUT_ENMISO_HSD_ISOCF3_HSCLK_ISOHSA_ISOVE2_U6MISO/HSDCF3/HSCLKHSACTIVEIRQ_OUT_EN_ISOIRQ1BWP_UXIRQ0BIRQ1BCF2IRQ_IN_ENSBENB_ISOCF1_ISORESETBPM0PM1RESB_CTRLPM1_CTRLCF1ADUM1401BRWZ10KVE2_U310KADUM1401BRWZHSDATA_ISOSCLK/SCLSDAVDD2MCU_VDDSCLIRQ1B_ISOIRQ1B_ISOIRQ0B_ISO10KVE2_U610KADUM1401BRWZ10KHSACTIVESSB/HSASCLSSBSCLK00MISO_ISOMISO_HSD_ISO00SCL_ISO10K10KADUM1401BRWZ10K10K10KADUM1401BRWZIRQ_IN_ENCF2_ISOIRQ0B_ISO10K10KPM0_CTRLVE2_U3WPIRQ0B0.1UF10KIRQ_OUT_EN0.1UFADUM1250ARZMOSI/SDA0SDADNIDNIDNIDNIMOSI010K0A245362718U428915116710345111413126U328915116710345111413126U628915116710345111413126R48R49R51R55R54JP35JP33JP37JP3612JP3412JP3812JP3212JP31C58C59R58BR58AR59BR59AC56C57U728915116710345111413126R57R53U528915116710345111413126R50R46R47C55C54C53C52C51C50C49C48GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1DGNDGNDSCL2SCL1SDA2SDA1VDD1VDD2GND1GND2GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD109078-045 Figure 41.
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09078-039LEFT MOST PINS SHOULD BE FURTHEST FROM DUT26ALIGN PORTS AS DRAWN NEXT TO MCUSIDE WITH PINS76 -
100100755025DO NOT INSTALLSIDE WITH PINS1 -
25DO NOT INSTALLSIDE WITH PINS51 -
75DO NOT INSTALLDO NOT INSTALLALIGN PORTS AS DRAWN NEXT TO MCUALIGN PORTS AS DRAWN NEXT TO MCU1SIDE WITH PINS26 -
50ALIGN PORTS AS DRAWN NEXT TO MCU5176R5221JP9R5621JP8R8654321P1954321P2154321P2554321P2954321P3354321P3754321P2054321P2454321P2854321P3254321P3654321P2354321P2754321P3554321P3154321P2654321P3054321P3454321P2254321P18P1_29SAMTECTSW10608GS5PINBERG69157-102SAMTECTSW10608GS5PINP3_25D+_MCUP2_10SAMTECTSW10608GS5PINP0_20SAMTECTSW10608GS5PINDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNITDOSAMTECTSW10608GS5PINSAMTECTSW10608GS5PINMISO_ISOSAMTECTSW10608GS5PINP1_28P1_22SAMTECTSW10608GS5PINSAMTECTSW10608GS5PINSAMTECTSW10608GS5PINHSA_ISOP1_19USB_UPP0_19P0_21TDISAMTECTSW10608GS5PINSAMTECTSW10608GS5PINP0_5PM1_CTRLP3_26P2_12P0_9SAMTECTSW10608GS5PINMCU_XT2SCL_ISOVBUSMCU_XT1SAMTECTSW10608GS5PINP1_31WPIRQ0B_ISOIRQ1B_ISOP2_13P2_0P2_1P2_2SAMTECTSW10608GS5PINP1_27P2_6P2_4P2_5RXDTXDRTCKSAMTECTSW10608GS5PINP1_8P1_0RSTOUT_NP1_26P1_25P1_23P2_8P2_9SSB_ISOSCLK_ISOSAMTECTSW10608GS5PINP1_16P1_17P1_10P1_15P1_14P1_4P1_1P1_9CF3_HSCLK_ISOSDA_ISOMCU_RSTRTCX2PM0_CTRLSBENB_ISOD-_MCUP4_29MOSI_ISOP2_3TMSP0_26IRQ_OUT_EN_ISOSAMTECTSW10608GS5PINSAMTECTSW10608GS5PINDNITRST_NTCLKIRQ_IN_ENP2_11P0_22P0_4P4_28RESB_CTRL10KBERG69157-10210K10KP0_24MCU_VDDP2_7HSDATA_ISOP0_24SAMTECTSW10608GS5PINGNDGND Figure 42.
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DO NOT POPULATE U2SELF BOOT EEPROMFACTORY USE ONLYCURRENT MEASUREMENT - DO NOT INSTALLC61C62C63R66R651TP611TP6221P17482631A3R6221JP6021JP61R61R63R6074295310186A4321P16R6474856321U20.1UFVDD2VDD210KMICRO24LC128-I-SN0.1UFWP_UXSBSCLDNIDNIBLKBLKISNS_OUTWEILAND25.161.0253AD8553ARMZDNIDNI560PFVDD_F200KIRQ0BDNIDNI4.02KDNIDNIDO NOT INSTALLDNI100K100KVREF_ISNSVDDDNI10KVDD2SBSCLVDD200SBSDAIRQ1B10KSBCONSBCONSB_ENBMOLEX22-03-2031SBSDAADG820BRMZDNIDGNDDGNDDGNDDGNDVDDS2S1INGNDDVFBGNDVREFENVCCVORGBRGASCLA1A2A0WPSDAVSSVCC09078-046 Figure 43.
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LAYOUT
09078-040 Figure 44. 09078-041
Figure 45.
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09078-042 Figure 46. 09078-043 Figure 47.
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ORDERING INFORMATION
BILL OF MATERIALS
Table 27.
Qty Designator Description Manufacturer/Part Number
1 A1 IC-ADI, 1.2 V, ultralow power, high PSRR voltage
reference Analog Devices, Inc./ADR280ARTZ 1 A2 IC swappable dual isolator Analog Devices, Inc./ADUM1250ARZ 4 C1, C8, C44, C78 Capacitor, tantalum, 10 μF AVX
20 C9 to C25, C32 to C34 Capacitor, ceramic, 22 nF AVX
30 C2, C7, C40, C42, C43, C48 to C59,
C61, C62, C72, C73, C75 to C77, C79
to C84
Capacitor, chip, X7R 0805, 0.1 μF Murata
4 C26, C27, C70, C71 Capacitor, mono, ceramic, C0G, 0402, 20 pF Murata
3 C3, C5, C41 Capacitor, tantalum, 4.7 μF AVX
2 C38, C74 Capacitor, ceramic chip, 1206, X7R, 1.0 μF Taiyo Yuden
2 C4, C6 Capacitor, ceramic, X7R, 0.22 μF Phycomp (Yageo)
4 CF1 to CF3, CLKIN Connector, PCB coax, BNC, ST AMP (Tyco)/227699-2
5 CR1 to CR5 Diode, LED, green, SMD Chicago Mini Lamp (CML Innovative Technologies)/CMD28-21VGCTR8T1 1 CR6 LED, green, surface mount LUMEX/SML-LXT0805GW-TR
12 E1A, E1B, E1C, E1N, E2A, E2B, E2C,
E2N, E8A, E8B, E8C, E8N Inductor, chip, ferrite bead, 0805, 1500 Ω Murata
37 JP2, JP7 to JP10, JP1A to JP8A, JP1B
to JP8B, JP1C to JP8C, JP1N to JP8N Connector, PCB Berg jumper, ST, male 2-pin Berg/69157-102
5 JP11, JP12, JP9A, JP9B, JP9C 3-pin solder jumper N/A
6 JP32, JP34, JP36, JP38, JP60, JP61 Resistor jumper, SMD 0805 (open), 0 Ω Panasonic
11 P1 to P10, P12 Connector, PCB TERM, black, 2-pin, ST WeilandD/25.161.0253
2 P11, P38 Connector, PCB, header, SHRD, ST, male 32-pin Samtec/TSW-1-30-08-G-D
1 P13 Connector, PCB, Berg, header, ST, male 20-pin Samtec/TSW-110-08-G-D
1 P14 Connector, PCB, USB, Type B, R/A, through hole AMP (Tyco)/4-1734376-8
1 P15 Connector, PCB, Berg, header, ST, male 4-pin Samtec/TSW106-08-G-S
1 P16 Connector, PCB straight header 3-pin Molex/22-03-2031
5 Q1 to Q5 Trans digital FET P channel Fairchild/FDV302P
8 R1 to R8 Do not install (TBD_R1206) N/A
8 R9 to R16 Resistor, PREC, thick film chip, R1206, 100 Ω Panasonic
12 R17 to R25, R32 to R34 Resistor, PREC, thick film chip, R0805, 1 kΩ Panasonic
3 R26 to R28 Resistor, MF, RN55, 1 M Vishay-Dale 3 R29 to R31 Resistor, MF, RN5, 100 kΩ Vishay-Dale 39 R35, R36, R38, R44 to R57, R64 to R66, R68 to R76, R78, R82 to R86, R58A, R58B, R59A, R59B
Resistor PREC thick film chip, R0805, 10 kΩ Panasonic
1 R37 Resistor, film, SMD 0805, 2 Ω Panasonic
5 R39 to R43 Resistor, PREC, thick film chip, R1206, 499 Panasonic
1 R77 Resistor, film, SMD, 0805, 680 Ω Multicomp
2 R79, R80 Resistor, film, SMD, 1206, 27 Ω Yageo-Phycomp
1 R81 Resistor, PREC, thick film chip, R1206, 1.5 kΩ Panasonic
1 RSB Resistor, jumper, SMD, 1206 (open), 0 Panasonic
2 S1, S2 SW SM mechanical key switch Omron/B3S1000
52 TP1 to TP18, TP22 to TP55 Connector, PCB, test point, black Components Corporation
1 U1 IC-ADI, polyphase, multifunction, energy metering IC Analog Devices, Inc./ADE7878CPZ 5 U3 to U7 IC-ADI quad channel digital isolator Analog Devices, Inc./ADum1401BRWZ
1 U8 IC ARM7, MCU, flash, 512 kΩ, 100 LQFP NXP/LPC2368FBD100
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Qty Designator Description Manufacturer/Part Number
1 Y1 IC crystal, 16.384 MHz Valpey Fisher Corporation
1 Y2 IC crystal quartz, 12.000 MHz ECS
1 A3 IC-ADI 1.8 V to 5.5 V 2:1 MUX/SPDT switches Analog Devices, Inc./ADG820BRMZ
1 A4 IC-ADI 1.8 V to 5 V auto-zero in amp with shutdown Analog Devices, Inc./AD8553ARMZ
1 C63 Capacitor, ceramic, NP0, 560 pF Phycomp (Yageo)
4 JP31, JP33, JP35, JP37 Resistor, jumper, SMD, 0805 (SHRT), 0 Panasonic
1 P17 Connector, PCB, TERM, black, 2-pin, ST Weiland/25.161.0253
20 P18 to P37 Connector, PCB, Berg, header, ST, male 5-pin Samtec/TSW106-08-G-S
1 R60 Resistor, PREC, thick film chip, R0805, 4.02 kΩ Panasonic
2 R61, R62 Resistor, PREC, thick film chip, R0805, 100 kΩ Panasonic
1 R63 Resistor, PREC, thick film chip, R1206, 200 kΩ Panasonic
2 TP61, TP62 Connector, PCB test point, black Components Corporation 1 U2 IC, serial EEPROM, 128 kΩ, 2.5 V Microchip/24LC128-I-SN
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NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG09078-0-8/10(0)
UCD3138
Highly Integrated Digital Controller for Isolated Power
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLUSAP2B
March 2012–Revised July 2012
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Contents
1 Introduction ........................................................................................................................ 6
1.1 Features ...................................................................................................................... 6
1.2 Applications .................................................................................................................. 7
2 Overview ............................................................................................................................ 7
2.1 Description ................................................................................................................... 7
2.2 Ordering Information ........................................................................................................ 8
2.3 Product Selection Matrix ................................................................................................... 8
2.4 Functional Block Diagram .................................................................................................. 9
2.5 UCD3138 64 QFN – Pin Assignments ................................................................................. 10
2.6 Pin Functions .............................................................................................................. 11
2.7 UCD3138 40 QFN – Pin Assignments ................................................................................. 13
2.8 Pin Functions .............................................................................................................. 14
3 Electrical Specifications ..................................................................................................... 15
3.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 15
3.2 THERMAL INFORMATION .............................................................................................. 15
3.3 RECOMMENDED OPERATING CONDITIONS ....................................................................... 15
3.4 ELECTRICAL CHARACTERISTICS .................................................................................... 16
3.5 PMBus/SMBus/I2C Timing ............................................................................................... 19
3.6 Power On Reset (POR) / Brown Out Reset (BOR) ................................................................... 20
3.7 Typical Clock Gating Power Savings ................................................................................... 21
3.8 Typical Temperature Characteristics ................................................................................... 22
4 Functional Overview .......................................................................................................... 23
4.1 ARM Processor ............................................................................................................ 23
4.2 Memory ..................................................................................................................... 23
4.2.1 CPU Memory Map and Interrupts ............................................................................ 23
4.2.1.1 Memory Map (After Reset Operation) ........................................................... 23
4.2.1.2 Memory Map (Normal Operation) ................................................................ 24
4.2.1.3 Memory Map (System and Peripherals Blocks) ................................................ 24
4.2.2 Boot ROM ....................................................................................................... 24
4.2.3 Customer Boot Program ....................................................................................... 25
4.2.4 Flash Management ............................................................................................. 25
4.3 System Module ............................................................................................................ 25
4.3.1 Address Decoder (DEC) ....................................................................................... 25
4.3.2 Memory Management Controller (MMC) .................................................................... 25
4.3.3 System Management (SYS) ................................................................................... 25
4.3.4 Central Interrupt Module (CIM) ............................................................................... 26
4.4 Peripherals ................................................................................................................. 27
4.4.1 Digital Power Peripherals ...................................................................................... 27
4.4.1.1 Front End ............................................................................................ 27
4.4.1.2 DPWM Module ..................................................................................... 28
4.4.1.3 DPWM Events ...................................................................................... 29
4.4.1.4 High Resolution DPWM ........................................................................... 31
4.4.1.5 Over Sampling ...................................................................................... 31
4.4.1.6 DPWM Interrupt Generation ...................................................................... 31
4.4.1.7 DPWM Interrupt Scaling/Range .................................................................. 31
4.5 DPWM Modes of Operation .............................................................................................. 32
4.5.1 Normal Mode .................................................................................................... 32
4.6 Phase Shifting ............................................................................................................. 34
4.7 DPWM Multiple Output Mode ............................................................................................ 35
4.8 DPWM Resonant Mode .................................................................................................. 36
4.9 Triangular Mode ........................................................................................................... 38
2 Contents Copyright © 2012, Texas Instruments Incorporated
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.10 Leading Edge Mode ....................................................................................................... 39
4.11 Sync FET Ramp and IDE Calculation .................................................................................. 41
4.12 Automatic Mode Switching ............................................................................................... 41
4.12.1 Phase Shifted Full Bridge Example .......................................................................... 41
4.12.2 LLC Example .................................................................................................... 42
4.12.3 Mechanism for Automatic Mode Switching .................................................................. 44
4.13 DPWMC, Edge Generation, IntraMux .................................................................................. 45
4.14 Filter ......................................................................................................................... 46
4.14.1 Loop Multiplexer ................................................................................................ 48
4.14.2 Fault Multiplexer ................................................................................................ 49
4.15 Communication Ports ..................................................................................................... 51
4.15.1 SCI (UART) Serial Communication Interface ............................................................... 51
4.15.2 PMBUS .......................................................................................................... 51
4.15.3 General Purpose ADC12 ...................................................................................... 52
4.15.4 Timers ............................................................................................................ 53
4.15.4.1 24-bit PWM Timer .................................................................................. 53
4.15.4.2 16-Bit PWM Timers ................................................................................ 54
4.15.4.3 Watchdog Timer .................................................................................... 54
4.16 Miscellaneous Analog ..................................................................................................... 54
4.17 Package ID Information ................................................................................................... 54
4.18 Brownout ................................................................................................................... 54
4.19 Global I/O ................................................................................................................... 55
4.20 Temperature Sensor Control ............................................................................................. 56
4.21 I/O Mux Control ............................................................................................................ 56
4.21.1 JTAG Use for I/O and JTAG Security ........................................................................ 57
4.22 Current Sharing Control .................................................................................................. 57
4.23 Temperature Reference .................................................................................................. 58
5 IC Grounding and Layout Recommendations ........................................................................ 59
6 Tools and Documentation ................................................................................................... 60
7 References ....................................................................................................................... 62
Revision History ......................................................................................................................... 63
Copyright © 2012, Texas Instruments Incorporated Contents 3
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
List of Figures
3-1 I2C/SMBus/PMBus Timing Diagram ........................................................................................... 20
3-2 Bus Timing in Extended Mode.................................................................................................. 20
3-3 Power On Reset (POR) / Brown Out Reset (BOR) .......................................................................... 20
3-4 EADC LSB Size with 4X Gain (mV) vs. Temperature ....................................................................... 22
3-5 ADC12 Measurement Temperature Sensor Voltage vs. Temperature.................................................... 22
3-6 ADC12 2.5-V Reference vs. Temperature .................................................................................... 22
3-7 ADC12 Temperature Sensor Measurement Error vs. Temperature....................................................... 22
3-8 UCD3138 Oscillator Frequency (2MHz Reference, Divided Down from 250MHz) vs. Temperature.................. 22
4-1 Input Stage of EADC Module ................................................................................................... 28
4-2 Front End Module ................................................................................................................ 28
4-3 Secondary-Referenced Phase-Shifted Full Bridge Control
With Synchronous Rectification ................................................................................................ 42
4-4 Secondary-Referenced Half-Bridge Resonant LLC Control
With Synchronous Rectification ................................................................................................ 43
4-5 Fault Mux Block Diagram ....................................................................................................... 51
4-6 PMBus Address Detection Method ............................................................................................ 52
4-7 ADC12 Control Block Diagram ................................................................................................. 53
4-8 Internal Temp Sensor............................................................................................................ 56
4-9 Simplified Current Sharing Circuitry ........................................................................................... 57
4 List of Figures Copyright © 2012, Texas Instruments Incorporated
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
List of Tables
2-1 Pin Functions ..................................................................................................................... 11
2-2 Pin Functions ..................................................................................................................... 14
3-1 I2C/SMBus/PMBus Timing Characteristics.................................................................................... 19
4-1 Interrupt Priority Table ........................................................................................................... 26
4-2 DPWM Interrupt Divide Ratio ................................................................................................... 31
Copyright © 2012, Texas Instruments Incorporated List of Tables 5
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
Highly Integrated Digital Controller for Isolated Power
Check for Samples: UCD3138
1 Introduction
1.1 Features
1
• Digital Control of up to 3 Independent – Synchronous Rectifier Soft On/Off
Feedback Loops – Low IC Standby Power
– Dedicated PID based hardware • Soft Start / Stop with and without Pre-bias
– 2-pole/2-zero configurable • Fast Input Voltage Feed Forward Hardware
– Non-Linear Control • Primary Side Voltage Sensing
• Up to 16MHz Error Analog to Digital Converter • Copper Trace Current Sensing
(EADC) • Flux and Phase Current Balancing for Non-
– Configurable Resolution as Small as Peak Current Mode Control Applications
1mV/LSB • Current Share Bus Support
– Automatic Resolution Selection – Analog Average
– Up to 8x Oversampling – Master/Slave
– Hardware Based Averaging (up to 8x) • Feature Rich Fault Protection Options
– 14 bit Effective DAC – 7 High Speed Analog Comparators
– Adaptive Sample Trigger Positioning – Cycle-by-Cycle Current Limiting
• Up to 8 High Resolution Digital Pulse Width – Programmable Fault Counting
Modulated (DPWM) Outputs – External Fault Inputs
– 250ps Pulse Width Resolution – 10 Digital Comparators
– 4ns Frequency Resolution – Programmable blanking time
– 4ns Phase Resolution • Synchronization of DPWM waveforms between
– Adjustable Phase Shift Between Outputs multiple UCD3138 devices
– Adjustable Dead-band Between Pairs • 14 channel, 12 bit, 267 ksps General Purpose
– Cycle-by-Cycle Duty Cycle Matching ADC with integrated
– Up to 2MHz Switching Frequency – Programmable averaging filters
• Configurable PWM Edge Movement – Dual sample and hold
– Trailing Modulation • Internal Temperature Sensor
– Leading Modulation • Fully Programmable High-Performance
– Triangular Modulation 31.25MHz, 32-bit ARM7TDMI-S Processor
• Configurable Feedback Control – 32 kByte (kB) Program Flash
– Voltage Mode – 2 kB Data Flash with ECC
– Average Current Mode – 4 kB Data RAM
– Peak Current Mode Control – 4 kB Boot ROM Enables Firmware Boot-Load
– Constant Current in the Field via I2C or UART
– Constant Power • Communication Peripherals
• Configurable Modulation Methods – I2C/PMBus
– Frequency Modulation – 2 UARTs on UCD3138RGC (64-pin QFN)
– Phase Shift Modulation – 1 UART on UCD3138RHA (40-pin QFN)
– Pulse Width Modulation • JTAG Debug Port
• Fast, Automatic and Smooth Mode Switching • Timer capture with selectable input pins
– Frequency Modulation and PWM • Up to 5 Additional General Purpose Timers
– Phase Shift Modulation and PWM • Built In Watchdog: BOD and POR
• High Efficiency and Light Load Management • 64-pin QFN and 40-pin QFN packages
– Burst Mode • Operating Temperature: –40°C to 125°C
– Ideal Diode Emulation • Fusion_Digital_Power_Designer GUI Support 1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2012, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
1.2 Applications
• Power Supplies and Telecom Rectifiers
• Power Factor Correction
• Isolated dc-dc Modules
2 Overview
2.1 Description
The UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of
integration and performance in a single chip solution. The flexible nature of the UCD3138 makes it
suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the
device have been specifically optimized to enhance the performance of ac/dc and isolated dc/dc
applications and reduce the solution component count in the IT and network infrastructure space.
The UCD3138 is a fully programmable solution offering customers complete control of their application,
along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our
customer’s development effort through offering best in class development tools, including application
firmware, Code Composer Studio™ software development environment, and TI’s power development GUI
which enables customers to configure and monitor key system parameters.
At the core of the UCD3138 controller are the digital control loop peripherals, also known as Digital Power
Peripherals (DPP). Each DPP implements a high speed digital control loop consisting of a dedicated Error
Analog to Digital Converter (EADC), a PID based 2 pole–2 zero digital compensator and DPWM outputs
with 250 ps pulse width resolution. The device also contains a 12-bit, 267ksps general purpose ADC with
up to 14 channels, timers, interrupt control, JTAG debug and PMBus and UART communications ports.
The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring,
configures peripherals and manages communications. The ARM microcontroller executes its program out
of programmable flash memory as well as on-chip RAM and ROM.
In addition to the FDPP, specific power management peripherals have been added to enable high
efficiency across the entire operating range, high integration for increased power density, reliability, and
lowest overall system cost and high flexibility with support for the widest number of control schemes and
topologies. Such peripherals include: light load burst mode, synchronous rectification, LLC and phase
shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode
emulation, constant current constant power control, synchronous rectification soft on and off, peak current
mode control, flux balancing, secondary side input voltage sensing, high resolution current sharing,
hardware configurable soft start with pre bias, as well as several other features. Topology support has
been optimized for voltage mode and peak current mode controlled phase shifted full bridge, single and
dual phase PFC, bridgeless PFC, hard switched full bridge and half bridge, and LLC half bridge and full
bridge.
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2.2 Ordering Information
PART NUMBER PIN COUNT PACKAGE SUPPLY TOP SIDE MARKING OPERATING TEMPERATURE RANGE, TA
UCD3138RGCT 64 QFN 250 (Small Reel) UCD3138 –40°C to 125°C
UCD3138RGCR 64 QFN 2000 (Large Reel) UCD3138 –40°C to 125°C
UCD3138RHAT 40 QFN 250 (Small Reel) UCD3138 –40°C to 125°C
UCD3138RHAR 40 QFN 2500 (large Reel) UCD3138 –40°C to 125°C
2.3 Product Selection Matrix
FEATURE UCD3138 64 PIN UCD3138 40 PIN
ARM7TDMI-S Core Processor 31.25 MHz 31.25 MHz
High Resolution DPWM Outputs (250ps Resolution) 8 8
Number of High Speed Independent Feedback Loops (# Regulated Output 3 3 Voltages)
12-bit, 267ksps, General Purpose ADC Channels 14 7
Digital Comparators at ADC Outputs 4 4
Flash Memory (Program) 32 KB 32 KB
Flash Memory (Data) 2 KB 2 KB
Flash Security √ √
RAM 4 KB 4 KB
DPWM Switching Frequency up to 2 MHz up to 2 MHz
Programmable Fault Inputs 4 1 + 2(1)
High Speed Analog Comparators with Cycle-by-Cycle Current Limiting 7(2) 6(2)
UART (SCI) 2 1(1)
PMBus √ √
Timers 4 (16 bit) and 1 (24 bit) 4 (16 bit) and 1 (24 bit)
Timer PWM Outputs 2 1
Timer Capture Inputs 1 1(1)
Watchdog √ √
On Chip Oscillator √ √
Power-On Reset and Brown-Out Reset √ √
JTAG √ √
Package Offering 64 Pin QFN (9mm x 9mm) 40 Pin QFN (6mm x 6mm)
Sync IN and Sync OUT Functions √ √
Total GPIO (includes all pins with multiplexed functions such as, DPWM, Fault 30 18 Inputs, SCI, etc.)
External Interrupts 1 0
(1) This number represents an alternate pin out that is programmable via firmware. See the UCD3138 Digital Power Peripherals
Programmer’s Manual for details.
(2) To facilitate simple OVP and UVP connections both comparators B and C are connected to the AD03 pin.
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Front End 2
Analog
Comparators
Power and
1.8 V Voltage
Regulator
AD07
AD06
AD04
V33DIO /RESET
SCI_RX0
SCI_TX0
PMBUS_CLK
PMBUS_DATA
AGND
V33D
BP18
FAULT3
FAULT2
TCAP
TMS
TDI
TDO
TCK
EXT_INT
FAULT1
FAULT0
PWM1
PWM0
SCI_RX1
SCI_TX1
PMBUS_CTRL
PMBUS_ALERT
SYNC
DGND
DPWM3B
DPWM3A
DPWM2B
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
EAP0
EAN0
EAP1
EAN1
V33 A
AD00
AD01
AD0 2
AD1 3
PID Based
Filter 0
DPWM0
DPWM1
DPWM2
DPWM3
PID Based
Filter 1
PID Based
Filter 2
ADC_EXT_ TRIG
ADC12
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold AD[13:0 ]
A
B
C
D
E
F
G
Current Share
Analog, Average, Master/Slave
AD03
AD0 2
AD1 3
AGND
PMBus
Timers
4 – 16 bit (PWM)
1 – 24 bit
UART0
UART1
GPIO
Control
JTAG
Loop MUX
ARM7TDMI-S
32 bit, 31.25 MHz
Memory
PFLASH 32 kB
DFLASH 2 kB
RAM 4 kB
ROM 4 kB
Power On Reset
Brown Out Detection
Oscillator
Internal Temperature
Sensor
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
Front End 1
Constant Power Constant
Current
Input Voltage Feed Forward
Front End Averaging
Digital Comparators
Fault MUX &
Control
Cycle by Cycle
Current Limit
Digital
Comparators
DAC0
EADC
X
AFE
Value
Dither
!
CPCC
Filter x
Ramp
SAR/Prebias
Abs()
2 Avg() AFE
23-AFE
Peak Current Mode
Control Comparator
A0
EAP2
EAN2
Front End 0
UCD3138
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2.4 Functional Block Diagram
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AGND 1
AD13 2
AD12 3
AD10 4
AD07 5
AD06 6
AD04 7
AD03 8
V33DIO 9
10
/RESET 11
ADC_EXT_TRIG/TCAP/SYNC/PWM0 12
SCI_RX0 13
SCI_TX0 14
DGND
PMBUS_CLK/SCI_TX0 15
PMBUS_DATA/SCI_RX0 16
48 AGND
47 V33D
46 BP18
45 V33DIO
44 DGND
43 FAULT3
42 FAULT2
41 TCAP
40 TMS
39 TDI/SCI_RX0/PMBUS_CTRL/FAULT1
38 TDO/SCI_TX0/PMBUS_ALERT/FAULT0
37 TCK/TCAP/SYNC/PWM0
36 FAULT1
35 FAULT0
34 INT_EXT
33 DGND
32
PWM1
31
PWM0
30
SCI_RX1/PMBUS_CTRL
29
SCI_TX1/PMBUS_ALERT
28
PMBUS_CTRL
27
PMBUS_ALERT
26
SYNC/TCAP/ADC_EXT_TRIG/PWM0
25
DGND
24
DPWM3B
23
DPWM3A
22
DPWM2B
21
DPWM2A
20
DPWM1B
19
DPWM1A
18
DPWM0B
17
DPWM0A
64
AGND
63
EAP0
62
EAN0
61
EAP1
60
EAN1
59
EAP2
58
EAN2
57
AGND
56
V33A
55
AD00
54
AD01
53
AD02
52
AD05
51
AD08
50
AD09
49
AD11
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2.5 UCD3138 64 QFN – Pin Assignments
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2.6 Pin Functions
Additional pin functionality is specified in the following table.
Table 2-1. Pin Functions
ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO?
1 AGND Analog ground
2 AD13 12-bit ADC, Ch 13, comparator E, I-share DAC output
3 AD12 12-bit ADC, Ch 12
4 AD10 12-bit ADC, Ch 10
5 AD07 12-bit ADC, Ch 7, Connected to comparator F and reference DAC output to comparator G
6 AD06 12-bit ADC, Ch 6, Connected to comparator F DAC output
7 AD04 12-bit ADC, Ch 4, Connected to comparator D DAC output
8 AD03 12-bit ADC, Ch 3, Connected to comparator B and C
9 V33DIO Digital I/O 3.3V core supply
10 DGND Digital ground
11 RESET Device Reset Input, active low
12 ADC_EXT_TRIG ADC conversion external trigger input TCAP SYNC PWM0 Yes
13 SCI_RX0 SCI RX 0 Yes
14 SCI_TX0 SCI TX 0 Yes
15 PMBUS_CLK PMBUS Clock (Open Drain) SCI TX 0 Yes
16 PMBUS_DATA PMBus data (Open Drain) SCI RX 0 Yes
17 DPWM0A DPWM 0A output Yes
18 DPWM0B DPWM 0B output Yes
19 DPWM1A DPWM 1A output Yes
20 DPWM1B DPWM 1B output Yes
21 DPWM2A DPWM 2A output Yes
22 DPWM2B DPWM 2B output Yes
23 DPWM3A DPWM 3A output Yes
24 DPWM3B DPWM 3B output Yes
25 DGND Digital ground
26 SYNC DPWM Synchronize pin TCAP ADC_EXT_ PWM0 Yes TRIG
27 PMBUS_ALERT PMBus Alert (Open Drain) Yes
28 PMBUS_CTRL PMBus Control (Open Drain) Yes
29 SCI_TX1 SCI TX 1 PMBUS_AL Yes ERT
30 SCI_RX1 SCI RX 1 PMBUS_CT Yes RL
31 PWM0 General purpose PWM 0 Yes
32 PWM1 General purpose PWM 1 Yes
33 DGND Digital ground
34 INT_EXT External Interrupt Yes
35 FAULT0 External fault input 0 Yes
36 FAULT1 External fault input 1 Yes
37 TCK JTAG TCK TCAP SYNC PWM0 Yes
38 TDO JTAG TDO SCI_TX0 PMBUS_AL FAULT0 Yes ERT
39 TDI JTAG TDI SCI_RX0 PMBUS_CT FAULT1 Yes RL
40 TMS JTAG TMS Yes
41 TCAP Timer capture input Yes
42 FAULT2 External fault input 2 Yes
43 FAULT3 External fault input 3 Yes
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Table 2-1. Pin Functions (continued)
ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO?
44 DGND Digital ground
45 V33DIO Digital I/O 3.3V core supply
46 BP18 1.8V Bypass
47 V33D Digital 3.3V core supply
48 AGND Substrate analog ground
49 AGND Analog ground
50 EAP0 Channel #0, differential analog voltage, positive input
51 EAN0 Channel #0, differential analog voltage, negative input
52 EAP1 Channel #1, differential analog voltage, positive input
53 EAN1 Channel #1, differential analog voltage, negative input
54 EAP2 Channel #2, differential analog voltage, positive input
55 EAN2 Channel #2, differential analog voltage, negative input
56 AGND Analog ground
57 V33A Analog 3.3V supply
58 AD00 12-bit ADC, Ch 0, Connected to current source
59 AD01 12-bit ADC, Ch 1, Connected to current source
60 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share
61 AD05 12-bit ADC, Ch 5
62 AD08 12-bit ADC, Ch 8
63 AD09 12-bit ADC, Ch 9
64 AD11 12-bit ADC, Ch 11
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AGND 1
2
3
4
5
AD13
6
AD06
7
AD04
8
AD03
9
DGND
10
/RESET
11
ADC_EXT_TRIG/TCAP/SYNC/PWM0
12 13 14 15
PMBUS_CLK/SCI_TX0
16
PMBUS_DATA/SCI_RX0
AGND
BP18
DGND
V33D
40 39
TMS
38
TDI/SCI_RX0/PMBUS_CTRL/FAULT1
37
TDO/SCI_TX0/PMBUS_ALERT/FAULT0
36
TCK/TCAP/SYNC/PWM0
35 34 33
FAULT2
32 31
AGND
30
29
28
27
26
DPWM3B
25
DPWM3A
24
PMBUS_CTRL
23
PMBUS_ALERT
22
DPWM2B
21
DPWM2A
20
DPWM1B
19
DPWM1A
18
DPWM0B
17
DPWM0A
EAP0
EAN0
EAP1
EAN1
EAP2
AGND
V33A
AD00
AD01
AD02
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2.7 UCD3138 40 QFN – Pin Assignments
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2.8 Pin Functions
Additional pin functionality is specified in the following table.
Table 2-2. Pin Functions
ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO?
1 AGND Analog ground
2 AD13 12-bit ADC, Ch 13, Connected to comparator E, I-share
3 AD06 12-bit ADC, Ch 6, Connected to comparator F
4 AD04 12-bit ADC, Ch 4, Connected to comparator D
5 AD03 12-bit ADC, Ch 3, Connected to comparator B & C
6 DGND Digital ground
7 RESET Device Reset Input, active low
8 ADC_EXT_TRIG ADC conversion external trigger input TCAP SYNC PWM0 Yes
9 PMBUS_CLK PMBUS Clock (Open Drain) SCI_TX0 Yes
10 PMBUS_DATA PMBus data (Open Drain) SCI_RX0 Yes
11 DPWM0A DPWM 0A output Yes
12 DPWM0B DPWM 0B output Yes
13 DPWM1A DPWM 1A output Yes
14 DPWM1B DPWM 1B output Yes
15 DPWM2A DPWM 2A output Yes
16 DPWM2B DPWM 2B output Yes
17 DWPM3A DPWM 3A output Yes
18 DPWM3B DPWM 3B output Yes
19 PMBUS_ALERT PMBus Alert (Open Drain) Yes
20 PMBUS_CTRL PMBus Control (Open Drain) Yes
21 TCK JTAG TCK TCAP SYNC PWM0 Yes
22 TDO JTAG TDO SCI_TX0 PMBUS_A FAULT0 Yes
LERT
23 TDI JTAG TDI SCI_RX0 PMBUS_C FAULT1 Yes
TRL
24 TMS JTAG TMS Yes
25 FAULT2 External fault input 2 Yes
26 DGND Digital ground
27 V33D Digital 3.3V core supply
28 BP18 1.8V Bypass
29 AGND Substrate analog ground
30 AGND Analog ground
31 EAP0 Channel #0, differential analog voltage, positive input
32 EAN0 Channel #0, differential analog voltage, negative input
33 EAP1 Channel #1, differential analog voltage, positive input
34 EAN1 Channel #1, differential analog voltage, negative input
35 EAP2 Channel #2, differential analog voltage, positive input
36 AGND Analog ground
37 V33A Analog 3.3V supply
38 AD00 12-bit ADC, Ch 0, Connected to current source
39 AD01 12-bit ADC, Ch 1, Connected to current source
40 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share
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3 Electrical Specifications
3.1 ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
V33D V33D to DGND –0.3 3.8 V
V33DIO V33DIO to DGND –0.3 3.8 V
V33A V33A to AGND –0.3 3.8 V
|DGND – AGND| Ground difference 0.3 V
All Pins, excluding AGND(2) Voltage applied to any pin –0.3 3.8 V
TOPT Junction Temperature –40 125 °C
TSTG Storage temperature –55 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Referenced to DGND
3.2 THERMAL INFORMATION
UCD3138 UCD3138
THERMAL METRIC(1) 64 PIN QFN 40 PIN UNITS
QFN
θJA Junction-to-ambient thermal resistance (2) 25.1 31.8
θJCtop Junction-to-case (top) thermal resistance (3) 10.5 18.5
θJB Junction-to-board thermal resistance (4) 4.6 6.8
°C/W
ψJT Junction-to-top characterization parameter(5) 0.2 0.2
ψJB Junction-to-board characterization parameter (6) 4.6 6.7
θJCbot Junction-to-case (bottom) thermal resistance (7) 1.2 1.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
3.3 RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
V33D Digital power 3.0 3.3 3.6 V
V33DIO Digital I/O power 3.0 3.3 3.6
V33A Analog power 3.0 3.3 3.6 V
TJ Junction temperature -40 - 125 °C
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3.4 ELECTRICAL CHARACTERISTICS
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
Measured on V33A. The device is
I33A powered up but all ADC12 and EADC 6.3 mA
sampling is disabled
I33DIO All GPIO and communication pins are 0.35 mA open
I33D ROM program execution 60 mA
I33D Flash programming in ROM mode 70 mA
The device is in ROM mode with all
I33 DPWMs enabled and switching at 2 100 mA
MHz. The DPWMs are all unloaded.
ERROR ADC INPUTS EAP, EAN
EAP – AGND –0.15 1.998 V
EAP – EAN –0.256 1.848 V
Typical error range AFE = 0 –256 248 mV
AFE = 3 0.8 1 1.20 mV
AFE = 2 1.7 2 2.30 mV
EAP – EAN Error voltage digital resolution
AFE = 1 3.55 4 4.45 mV
AFE = 0 6.90 8 9.10 mV
REA Input impedance (See Figure 4-1) AGND reference 0.5 MΩ
IOFFSET Input offset current (See Figure 4-1) –5 5 μA
Input voltage = 0 V at AFE = 0 –2 2 LSB
Input voltage = 0 V at AFE = 1 –2.5 2.5 LSB
EADC Offset
Input voltage = 0 V at AFE = 2 –3 -3 LSB
Input voltage = 0 V at AFE = 3 –4 4 LSB
Sample Rate 16 MHz
Analog Front End Amplifier Bandwidth 100 MHz
Gain See Figure 4-2 1 V/V
A0 Minimum output voltage 100 mV
EADC DAC
DAC range 0 1.6 V
VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV
VREF DAC reference resolution With 4 bit dithering enabled 97.6 μV
INL –3.0 3.0 LSB
DNL Does not include MSB transition –2.1 1.6 LSB
DNL at MSB transition -1.4 LSB
DAC reference voltage 1.58 1.61 V
τ Settling Time From 10% to 90% 250 ns
ADC12
IBIAS Bias current for PMBus address pins 9.5 10.5 μA
Measurement range for voltage monitoring 0 2.5 V
Internal ADC reference voltage –40°C to 125°C 2.475 2.500 2.525 V
–40°C to 25°C –0.4
Change in Internal ADC reference from 25°C to 85°C –1.8 mV 25°C reference voltage(1)
25°C to 125°C –4.2
(1) As designed and characterized. Not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
ADC12 INL integral nonlinearity(1) +/-2.5 LSB
ADC12 DNL differential nonlinearity(1) ADC_SAMPLINGSEL = 6 for all ADC12 –0.7/+2.5 LSB
ADC Zero Scale Error data, 25 °C to 125 °C –7 7 mV
ADC Full Scale Error –35 35 mV
Input bias 2.5 V applied to pin 400 nA
Input leakage resistance(1) ADC_SAMPLINGSEL= 6 or 0 1 MΩ
Input Capacitance(1) 10 pF
ADC single sample conversion time(1) ADC_SAMPLINGSEL= 6 or 0 3.9 μs
DIGITAL INPUTS/OUTPUTS(2) (3)
V DGND OL Low-level output voltage(4) IOH = 4 mA, V33DIO = 3 V + 0.25 V
V V33DIO OH High-level output voltage (4) IOH = –4 mA, V33DIO = 3 V – 0.6 V
VIH High-level input voltage V33DIO = 3 V 2.1 V
VIL Low-level input voltage V33DIO = 3 V 1.1 V
IOH Output sinking current 4 mA
IOL Output sourcing current –4 mA
SYSTEM PERFORMANCE
TWD Watchdog time out range Total time is: TWD x 14.6 17 20.5 ms (WDCTRL.PERIOD+1)
Time to disable DPWM output based on High level on FAULT pin 70 ns active FAULT pin signal
Processor master clock (MCLK) 31.25 MHz
tDelay Digital compensator delay(5) (1 clock = 32ns) 6 clocks
VDD Slew minimum VDD slew rate(6) VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms
t(reset) Pulse width needed at reset(6) 10 μs
Retention period of flash content (data TJ = 25°C 100 years retention and program)
Program time to erase one page or block in 20 ms data flash or program flash
Program time to write one word in data 20 μs flash or program flash
f(PCLK) Internal oscillator frequency 240 250 260 MHz
Sync-in/sync-out pulse width Sync pin 256 ns
Flash Read 1 MCLKs
Flash Write 20 μs
I Current share current source (See SHARE Figure 4-9) 238 259 μA
RSHARE Current share resistor (See Figure 4-9) 9.75 10.3 kΩ
POWER ON RESET AND BROWN OUT (V33D pin, See Figure 3-3)
VGH Voltage good High 2.7 V
VGL Voltage good Low 2.5 V
Vres Voltage at which IReset signal is valid 0.8 V
(2) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
(3) On the 40 pin package V33DIO is connected to V33D internally.
(4) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
(5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which
has no variation associated with it, must be accounted for when calculating the system dynamic response.
(6) As designed and characterized. Not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
T Time delay after Power is good or POR RESET* relinquished 1 ms
Brownout Internal signal warning of brownout 2.9 V conditions
TEMPERATURE SENSOR(7)
VTEMP Voltage range of sensor 1.46 2.44 V
Voltage resolution Volts/°C 5.9 mV/ºC
Temperature resolution Degree C per bit 0.1034 ºC/LSB
Accuracy(7) (8) -40°C to 125°C –10 ±5 10 ºC
Temperature range -40°C to 125°C –40 125 ºC
ITEMP Current draw of sensor when active 30 μA
TON Turn on time / settling time of sensor 100 μs
VAMB Ambient temperature Trimmed 25°C reading 1.85 V
ANALOG COMPARATOR
DAC Reference DAC Range 0 2.5 V
Reference Voltage 2.478 2.5 2.513 V
Bits 7 bits
INL(7) –0.42 0.21 LSB
DNL(7) 0.06 0.12 LSB
Offset –5.5 19.5 mV
Time to disable DPWM output based on 0
V to 2.5 V step input on the analog 150 ns
comparator.(9)
Reference DAC buffered output load(10) 0.5 1 mA
Buffer offset (-0.5 mA) 4.6 8.3 mV
Buffer offset (1.0 mA) –0.05 17 mV
(7) Characterized by design and not production tested.
(8) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
(9) As designed and characterized. Not 100% tested in production.
(10) Available from reference DACs for comparators D, E, F and G.
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3.5 PMBus/SMBus/I2C Timing
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus,
and PMBus in Slave or Master mode are shown in Table 3-1, Figure 3-1, and Figure 3-2. The numbers in
Table 3-1 are for 400 kHz operating frequency. However, the device supports all three speeds, standard
(100 kHz), fast (400 kHz), and fast mode plus (1 MHz).
Table 3-1. I2C/SMBus/PMBus Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 1000 kHz
fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 1000 kHz
t(BUF) Bus free time between start and stop 1.3 ms
t(HD:STA) Hold time after (repeated) start 0.6 ms
t(SU:STA) Repeated start setup time 0.6 ms
t(SU:STO) Stop setup time 0.6 ms
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 100 ns
t(TIMEOUT) Error signal/detect(1) 35 ms
t(LOW) Clock low period 1.3 ms
t(HIGH) Clock high period(2) 0.6 ms
t Cumulative clock low slave extend (LOW:SEXT) time(3) 25 ms
t 20 + 0.1 f Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) Cb(4) 300 ns
t 20 + 0.1 r Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) Cb(4) 300 ns
Cb Total capacitance of one bus line 400 pF
(1) The device times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Cb (pF)
Figure 3-1. I2C/SMBus/PMBus Timing Diagram
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TPOR
undefined
V33D
IReset
3.3 V
TPOR
VGH
VGL
Vres
t
t
Brown Out
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
Figure 3-2. Bus Timing in Extended Mode
3.6 Power On Reset (POR) / Brown Out Reset (BOR)
Figure 3-3. Power On Reset (POR) / Brown Out Reset (BOR)
VGH – This is the V33D threshold where the internal power is declared good. The UCD3138 comes
out of reset when above this threshold.
VGL – This is the V33D threshold where the internal power is declared bad. The device goes into
reset when below this threshold.
Vres – This is the V33D threshold where the internal reset signal is no longer valid. Below this
threshold the device is in an indeterminate state.
IReset – This is the internal reset signal. When low, the device is held in reset. This is equivalent to
holding the reset pin on the IC high.
TPOR – The time delay from when VGH is exceeded to when the device comes out of reset.
Brown – This is the V33D voltage threshold at which the device sets the brown out status bit. In
Out addition an interrupt can be triggered if enabled.
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DPWM FE_CTRL PCM ADC12 PMBUS TIMER CPCC FILTER SCI SCI GIO
0
1
2
3
4
5
6
UCD3138 Function
Power Savings (mA)
G001
4.9
2.57
1.2
0.8
0.4 0.4
0.2 0.2
0.1 0.1
0
UCD3138
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3.7 Typical Clock Gating Power Savings
Power disable control register provides control bits that can enable or disable arrival of clock to several
peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
All these controls are enabled as default. If a specific peripheral is not used in a specific application the
clock gate can be disabled in order to block the propagation of clock signal to that peripheral and therefore
reduce the overall current consumption of the device.
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2.475
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
ADC12 Reference
G003b
ADC12 2.5-V Reference
1.92
1.96
2
2.04
2.08
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
2-MHZ Reference
G004b
UCD3138 Oscillator Frequency
−4
−2
0
2
4
6
8
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
ADC12 Error (LSB)
G002b
ADC12 Temperature Sensor Measurement Error
1.4
1.6
1.8
2.0
2.2
2.4
2.6
−60 −40 −20 0 20 40 60 80 100 120 140 160
Temperature (°C)
Sensor Voltage (V)
G006b
ADC12 Measurement Temperature Sensor Voltage
1.6
1.7
1.8
1.9
2
2.1
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
EADC LSB Size (mV)
G005a
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
3.8 Typical Temperature Characteristics
Figure 3-4. EADC LSB Size with 4X Gain (mV) vs. Temperature
Figure 3-5. ADC12 Measurement Temperature Figure 3-7. ADC12 Temperature Sensor
Sensor Voltage vs. Temperature Measurement Error vs. Temperature
Figure 3-6. ADC12 2.5-V Reference vs. Figure 3-8. UCD3138 Oscillator Frequency (2MHz
Temperature Reference, Divided Down from 250MHz) vs.
Temperature
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4 Functional Overview
4.1 ARM Processor
The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit
microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles
where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction
set. The Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the
performance of the 32-bit microprocessor.
The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major
blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter. A JTAG port is
also available for firmware debugging.
4.2 Memory
The UCD3138 (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all
of the memory modules. All of the memory module addresses are sequentially aligned along the same
address range. This applies to program flash, data flash, ROM and all other peripherals.
Within the UCD3138 architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware
startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM
is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is
present, the ROM code branches to the main FLASH-program execution.
UCD3138 also supports customization of the boot program by allowing an alternative boot routine to be
executed from program FLASH. This feature enables assignment of a unique address to each device;
therefore, enabling firmware reprogramming even when several devices are connected on the same
communication bus.
Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is
organized as an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is
configured with page erase capability for erasing blocks as small as 1kB per page, or with a mass erase
for erasing the entire program FLASH array. The FLASH endurance is specified at 1000 erase/write
cycles and the data retention is good for 100 years. The 2 kB data FLASH array is organized as a 512 x
32 bit memory (32 byte page size). The Data FLASH is intended for firmware data value storage and data
logging. Thus, the Data FLASH is specified as a high endurance memory of 20 k cycles with embedded
error correction code (ECC).
For run time data storage and scratchpad memory, a 4 kB RAM is available. The RAM is organized as a 1
k x 32 bit array.
4.2.1 CPU Memory Map and Interrupts
When the device comes out of power-on-reset, the data memories are mapped to the processor as
follows:
4.2.1.1 Memory Map (After Reset Operation)
Address Size Module
0x0000_0000 – 0x0000_FFFF In 16 repeated blocks of 4K each 16 X 4K Boot ROM
0x0001_0000 – 0x0001_7FFF 32K Program Flash
0x0001_8800 – 0x0001_8FFF 2K Data Flash
0x0001_9000 – 0x0001_9FFF 4K Data RAM
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4.2.1.2 Memory Map (Normal Operation)
Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as
follows:
Address Size Module
0x0000_0000 – 0x0000_7FFF 32K Program Flash
0x0001_0000 – 0x0001_AFFF 4K Boot ROM
0x0001_8800 – 0x0001_8FFF 2K Data Flash
0x0001_9000 – 0x0001_9FFF 4K Data RAM
4.2.1.3 Memory Map (System and Peripherals Blocks)
Address Size Module
0x0002_0000 - 0x0002_00FF 256 Loop Mux
0x0003_0000 - 0x0003_00FF 256 Fault Mux
0x0004_0000 - 0x0004_00FF 256 ADC
0x0005_0000 - 0x0005_00FF 256 DPWM 3
0x0006_0000 - 0x0006_00FF 256 Filter 2
0x0007_0000 - 0x0007_00FF 256 DPWM 2
0x0008_0000 - 0x0008_00FF 256 Front End/Ramp I/F 2
0x0009_0000 - 0x0009_00FF 256 Filter 1
0x000A_0000 - 0x000A_00FF 256 DPWM 1
0x000B_0000 – 0x000B_00FF 256 Front End/Ramp I/F 1
0x000C_0000 - 0x000C_00FF 256 Filter 0
0x000D_0000 - 0x000D_00FF 256 DPWM 0
0x000E_0000 - 0x000E_00FF 256 Front End/Ramp I/F 0
0xFFF7_EC00 - 0xFFF7_ECFF 256 UART 0
0xFFF7_ED00 - 0xFFF7_EDFF 256 UART 1
0xFFF7_F000 - 0xFFF7_F0FF 256 Miscellaneous Analog Control
0xFFF7_F600 - 0xFFF7_F6FF 256 PMBus Interface
0xFFF7_FA00 - 0xFFF7_FAFF 256 GIO
0xFFF7_FD00 - 0xFFF7_FDFF 256 Timer
0xFFFF_FD00 - 0xFFFF_FDFF 256 MMC
0xFFFF_FE00 - 0xFFFF_FEFF 256 DEC
0xFFFF_FF20 - 0xFFFF_FF37 23 CIM
0xFFFF_FF40 - 0xFFFF_FF50 16 PSA
0xFFFF_FFD0 - 0xFFFF_FFEC 28 SYS
The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s
guide for each peripheral.
4.2.2 Boot ROM
The UCD3138 incorporates a 4k boot ROM. This boot ROM includes support for:
• Program download through the PMBus
• Device initialization
• Examining and modifying registers and memory
• Verifying and executing program FLASH automatically
• Jumping to a customer defined boot program
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The Boot ROM is entered automatically on device reset. It initializes the device and then performs
checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the
program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If
the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it
also jumps to location 0 in the program flash. This permits full automated program memory checking,
when there is no need for a custom boot program.
If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus
interface
These functions can be used to read and write to all memory locations in the UCD3138. Typically they are
used to download a program to Program Flash, and to command its execution
4.2.3 Customer Boot Program
As described above, it is possible to generate a user boot program using 2 kB or more of the Program
Flash. This can support things which the Boot ROM does not support, including:
• Program download via UART – useful especially for applications where the UCD3138 is isolated from
the host (e.g., PFC)
• Encrypted download – useful for code security in field updates.
4.2.4 Flash Management
The UCD3138 offers a variety of features providing for easy prototyping and easy flash programming. At
the same time, high levels of security are possible for production code, even with field updates. Standard
firmware will be provided for storing multiple copies of system parameters in data flash. This is minimizes
the risk of losing information if programming is interrupted.
4.3 System Module
The System Module contains the interface logic and configuration registers to control and configure all the
memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address
decoder, memory management controller, system management unit, central interrupt unit, and clock
control unit.
4.3.1 Address Decoder (DEC)
The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory
map addresses are selectable through configurable register settings. These memory selects can be
configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM
execution, which is then configured by the ROM code to the application setup. During access to the DEC
registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode
for user mode protection.
4.3.2 Memory Management Controller (MMC)
The MMC manages the interface to the peripherals by controlling the interface bus for extending the read
and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of
address space decoding.
4.3.3 System Management (SYS)
The SYS unit contains the software access protection by configuring user privilege levels to memory or
peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal
address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also
available.
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4.3.4 Central Interrupt Module (CIM)
The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor
supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides
hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a
vector table. This numerical index value indicates the highest precedence channel with a pending interrupt
and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has
the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt
request, the firmware should clear the request as the first action in the interrupt service routine. The
request channels are maskable, allowing individual channels to be selectively disabled or enabled.
Table 4-1. Interrupt Priority Table
NAME MODULE COMPONENT OR DESCRIPTION PRIORITY REGISTER
BRN_OUT_INT Brownout Brownout interrupt 0 (Lowest)
EXT_INT External Interrupts Interrupt on external input pin 1
WDRST_INT Watchdog Control Interrupt from watchdog exceeded (reset) 2
WDWAKE_INT Watchdog Control Wakeup interrupt when watchdog equals half of set 3 watch time
SCI_ERR_INT UART or SCI Control UART or SCI error Interrupt. Frame, parity or overrun 4
SCI_RX_0_INT UART or SCI Control UART0 RX buffer has a byte 5
SCI_TX_0_INT UART or SCI Control UART0 TX buffer empty 6
SCI_RX_1_INT UART or SCI Control UART1 RX buffer has a byte 7
SCI_TX_1_INT UART or SCI Control UART1 TX buffer empty 8
PMBUS_INT PMBus related interrupt 9
DIG_COMP_INT 12-bit ADC Control Digital comparator interrupt 10
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE0_INT Front End 0 Complete”, “Load Step Detected”, 11
“Over-Voltage Detected”, “EADC saturated”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE1_INT Front End 1 Complete”, “Load Step Detected”, 12
“Over-Voltage Detected”, “EADC saturated”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE2_INT Front End 2 Complete”, “Load Step Detected”, 13
“Over-Voltage Detected”, “EADC saturated”
PWM3_INT 16-bit Timer PWM 3 16-bit Timer PWM3 counter overflow or compare interrupt 14
PWM2_INT 16-bit Timer PWM 2 16-bit Timer PWM2 counter Overflow or compare 15 interrupt
PWM1_INT 16-bit Timer PWM 1 16-bit Timer PWM1 counter overflow or compare interrupt 16
PWM0_INT 16-bit timer PWM 0 16-bit Timer PWM1 counter overflow or compare interrupt 17
OVF24_INT 24-bit Timer Control 24-bit Timer counter overflow interrupt 18
CAPTURE_1_INT 24-bit Timer Control 24-bit Timer capture 1 interrupt 19
COMP_1_INT 24-bit Timer Control 24-bit Timer compare 1 interrupt 20
CAPTURE_0_INT 24-bit Timer Control 24-bit Timer capture 0 interrupt 21
COMP_0_INT 24-bit Timer Control 24-bit Timer compare 0 interrupt 22
CPCC_INT Constant Power Constant Current Mode switched in CPCC module Flag needs to be read 23 for details
ADC_CONV_INT 12-bit ADC Control ADC end of conversion interrupt 24
Analog comparator interrupts, Over-Voltage detection,
FAULT_INT Fault Mux Interrupt Under-Voltage detection, 25
LLM load step detection
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Error ADC
(Front End)
Filter
Digital
PWM
EAP
EAN
DPWMA
DPWMB
UCD3138
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Table 4-1. Interrupt Priority Table (continued)
NAME MODULE COMPONENT OR DESCRIPTION PRIORITY REGISTER
DPWM3 DPWM3 Same as DPWM1 26
DPWM2 DPWM2 Same as DPWM1 27
1) Every (1-256) switching cycles
DPWM1 DPWM1 2) Fault Detection 28
3) Mode switching
DPWM0 DPWM0 Same as DPWM1 29
EXT_FAULT_INT External Faults Fault pin interrupt 30
SYS_SSI_INT System Software System software interrupt 31 (highest)
4.4 Peripherals
4.4.1 Digital Power Peripherals
At the core of the UCD3138 controller are 3 Digital Power Peripherals (DPP). Each DPP can be
configured to drive from one to eight DPWM outputs. Each DPP consists of:
• Differential input error ADC (EADC) with sophisticated controls
• Hardware accelerated digital 2-pole/2-zero PID based compensator
• Digital PWM module with support for a variety of topologies
These can be connected in many different combinations, with multiple filters and DPWMs. They are
capable of supporting functions like input voltage feed forward, current mode control, and constant
current/constant power, etc.. The simplest configuration is shown in the following figure:
4.4.1.1 Front End
Figure 4-1 shows the block diagram of the front end module. It consists of a differential amplifier, an
adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging
filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert
with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range
with 6 bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended
result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output
could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE
value such that the minimum resolution is maintained that still allows the voltage to fit within the range of
the measurement. The EADC control logic receives the sample request from the DPWM module for
initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the
digital compensator for processing of the representative error. The set point DAC has 10 bits with an
additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a
variety of sources to facilitate things like soft start, nested loops, etc. Some additional features include the
ability to change the polarity of the error measurement and an absolute value mode which automatically
adds the DAC value to the error.
It is possible to operate the controller in a peak current mode control configuration. In this mode topologies
like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The
internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope
compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward
performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this
buffer is specified in the Electrical Characteristics table.
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EAP0
EAN0
DAC0
EADC
4 bit dithering gives 14 bits of effective resolution
97.65625 μV/LSB effective resolution
X
6 bit ADC
8 mV/LSB
Signed 9 bit result
(error) 1 mV /LSB
AFE_GAIN
10 bit DAC
1.5625 mV/LSB Value
Dither
S
CPCC
Filter x
Ramp
SAR/Prebias
Absolute Value
Calculation
Averaging
10 bit result
1.5625 mV/LSB
2
3-AFE_GAIN
Peak Current Mode
Comparator
Peak Current
Detected
A0
2
AFE_GAIN
IOFFSET
REA
EAP
EAN
AGND
AGND
IOFFSET
REA
Front End Differential
Amplifier
UCD3138
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Figure 4-1. Input Stage of EADC Module
Figure 4-2. Front End Module
4.4.1.2 DPWM Module
The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B.
Multiple DPWM modules within the UCD3138 system can be configured to support all key power
topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power
supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift
between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM
configurations.
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The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse
width modulated outputs for the power stage switches. The compensator calculates the necessary duty
ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value
within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON
time. The resolution of the DPWM ON time is 250 psec.
Each DPWM module can be synchronized to another module or to an external sync signal. An input
SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four
DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of
the DPWM outputs for multiple power stages can be tightly controlled.
The DPWM logic is probably the most complex of the Digital Peripherals. It takes the output of the
compensator and converts it into the correct DPWM output for several power supply topologies. It
provides for programmable dead times and cycle adjustments for current balancing between phases. It
controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can
provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to
several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM
registers. Fault handling is covered in the Fault Mux section.
Each DPWM module supports the following features:
• Dedicated 14 bit time-base with period and frequency control
• Shadow period register for end of period updates.
• Quad-event control registers (A and B, rising and falling) (Events 1-4)
– Used for on/off DPWM duty ratio updates.
• Phase control relative to other DPWM modules
• Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
• Support for 2 independent edge placement DPWM outputs (same frequency or period setting)
• Dead-time between DPWM A and B outputs
• High Resolution capabilities – 250 ps
• Pulse cycle adjustment of up to ±8.192 μs ( 32768 × 250 ps)
• Active high/ active low output polarity selection
• Provides events to trigger both CPU interrupts and start of ADC12 conversions.
4.4.1.3 DPWM Events
Each DPWM can control the following timing events:
1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in
relationship to the DPWM period. The programmed value set in the register should be one fourth of the
value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the
circuitry runs at one fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count
is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a
CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.
2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period–low resolution switching period count. (count of PCLK cycles)
4. Event 1–count offset for rising DPWM A event. (PCLK cycles)
5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are
for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.
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Start of Period
Period Counter
Start of Period
Period
Sample Trigger 1
DPWM Output A
Cycle Adjust A (High Resolution)
Event 2 (High Resolution)
Event 1
Event 3 (High Resolution)
Cycle Adjust B (High Resolution)
Event 4 (High Resolution)
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Multi Mode Open Loop
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 2 + Cycle Adjust A
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 4 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
UCD3138
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Basic comparisons between the programmed registers and the DPWM counter can create the desired
edge placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.
The drawing above is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely
by its own registers, not by the filter output. In other words, the power supply control loop is not closed.
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The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking
signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.
Additional DPWM modes are described below.
4.4.1.4 High Resolution DPWM
Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of
PWM edges, the UCD3138 DPWM can generate waveforms with resolutions as small as 250 ps. This is
16 times the resolution of the clock driving the DPWM module.
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz
each. The high resolution section of DPWM can be enabled or disabled, also the resolution can be defined
in several steps between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN ,
HIRES_SCALE and ALL_PHASE_CLK_ENA inside the DPWM Control Register 1. See the Power
Peripherals programmer’s manual for details.
4.4.1.5 Over Sampling
The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample
the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the
sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8
times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the
sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling,
and the “11” triggers over sampling at 8X.
4.4.1.6 DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in
the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower
interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12
trigger for sequence synchronization. Table 4-2 outlines the divide ratios that can be programmed.
4.4.1.7 DPWM Interrupt Scaling/Range
Table 4-2. DPWM Interrupt Divide Ratio
Interrupt Divide Interrupt Divide Interrupt Divide Switching Period Number of 32 MHz Setting Count Count (hex) Frames (assume 1MHz Processor Cycles loop)
1 0 00 1 32
2 1 01 2 64
3 3 03 4 128
4 7 07 8 256
5 15 0F 16 512
6 31 1F 32 1024
7 47 2F 48 1536
8 63 3F 64 2048
9 79 4F 80 2560
10 95 5F 96 3072
11 127 7F 128 4096
12 159 9F 160 5120
13 191 BF 192 6144
14 223 DF 224 7168
15 255 FF 256 8192
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4.5 DPWM Modes of Operation
The DPWM is a complex logic system which is highly configurable to support several different power
supply topologies. The discussion below will focus primarily on waveforms, timing and register settings,
rather than on logic design.
The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts
over again.
The DPWM logic causes transitions in many digital signals when the period counter hits the target value
for that signal.
4.5.1 Normal Mode
In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of
the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck
topologies, among others. Here is a drawing of the Normal Mode waveforms:
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Start of Period
Period Counter
Start of Period
Period
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
Event 3 – Event 2 (High Res)
Event 4 (High Res)
DPWM Output B
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
Normal Mode Closed Loop
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)
DPWM B Falling Edge = Event 4
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Filter controlled edge
Sample Trigger 1
Blanking A Begin
Blanking A End
To Other
Modules
Adaptive Sample Trigger A
Adaptive Sample Trigger B
UCD3138
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Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can
be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the
middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The
Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for
external delays, such as MOSFET and gate driver turn on times.
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Phase Shift
Phase Trigger = Phase Trigger Register value or Filter Duty
DPWM0 Start of Period
Period Counter
DPWM0 Start of Period
DPWM1 Start of Period
Period Counter
DPWM1 Start of Period
UCD3138
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Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the
beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB.
The other edges are dynamic, so blanking is more difficult.
Cycle Adjust B has no effect in Normal Mode.
4.6 Phase Shifting
In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The
phase shift signal has two possible sources. It can come from the Phase Shift Register. This provides a
fixed value, which is useful for an interleaved PFC, for example.
The phase shift value can also come from the filter output. In this case, the changes in the filter output
causes changes in the phase relationship of two DPWM modules. This is useful for phase shifted full
bridge topologies.
The following figure shows the mechanism of phase shift:
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Adaptive Sample Trigger B
Start of Period
Period Counter
Start of Period
Period
Adaptive Sample Trigger A
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
To Other
Modules
Multi Mode Closed Loop
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Filter controlled edge
Event 3 (High Resolution)
Cycle Adjust B (High Resolution)
Filter Duty (High Resolution)
DPWM Output B
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
Sample Trigger 1
Blanking A Begin
Blanking A End
UCD3138
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4.7 DPWM Multiple Output Mode
Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM
peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and
with different cycle adjusts for each phase.
Here is a diagram for Multi-Mode:
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Event 2 and Event 4 are not relevant in Multi mode.
DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100%
pulse width operation is possible. DPWMA cannot cross over the period boundary.
Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for
blanking this rising edge.
And, of course, Cycle Adjust B is usable on DPWM B.
4.8 DPWM Resonant Mode
This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As
the switching frequency changes, the dead times between the pulses remain the same.
The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as
described in the LLC Example section. Here is a diagram of this mode:
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Start of Period
Period Counter
Start of Period
Filter Period
Adaptive Sample Trigger A
Sample Trigger 1
DPWM Output A
Filter Duty – Average Dead Time
Event 1
Event 3 - Event 2
Period Register – Event 4
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Resonant Symmetrical Closed Loop
Events which change with DPWM mode:
Dead Time 1 = Event 3 – Event 2
Dead Time 2 = Event 1 + Period Register – Event 4)
Average Dead Time = (Dead Time 1 + Dead Time 2)/2
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead Time
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead Time + (Event 3 – Event 2)
DPWM B Falling Edge = Filter Period – (Period Register – Event 4)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
Filter controlled edge
Adaptive Sample Trigger B
UCD3138
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The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the
Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half
of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty
for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed
regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of
DPWM A. This is the only edge for which the blanking signals can be used easily.
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Start of Period
Period Counter
Start of Period
Period
Sample Trigger 1
DPWM Output A
Filter Duty/2 (High Resolution)
Period/2
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Triangular Mode Closed Loop
Events which change with DPWM mode:
DPWM A Rising Edge = None
DPWM A Falling Edge = None
Adaptive Sample Trigger = None
DPWM B Rising Edge = Period/2 - Filter Duty/2 + Cycle Adjust A
DPWM B Falling Edge = Period/2 + Filter Duty/2 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Filter controlled edge
Cycle Adjust A (High Resolution)
Cycle Adjust B (High Resolution)
UCD3138
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4.9 Triangular Mode
Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the
PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In
Triangular Mode, only DPWM-B is available. Here is a diagram for Triangular Mode:
All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger
is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time,
because the center of the on-time does not move in this mode.
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4.10 Leading Edge Mode
Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed,
and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B
falling edge stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the
Leading Edge Mode:
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Start of Period
Period Counter
Start of Period
Period
Adaptive Sample Trigger B
Sample Trigger 1
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
Event 2 - Event 3 (High Resolution)
Event 4 (High Resolution)
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Leading Edge Closed Loop
Events which change with DPWM mode:
DPWM A Falling Edge = Event 1
DPWM A Rising Edge = Event 1 - Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 - Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 4
DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A -(Event 2 – Event 3)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Adaptive Sample Trigger A
UCD3138
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As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking
intervals are mainly useful for the edges at the beginning and end of the period.
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DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTrans
DPWM0B
(QSYN2,4)
DPWM1B
(QSYN1,3)
IPRI
DPWM3A
(QB1)
UCD3138
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4.11 Sync FET Ramp and IDE Calculation
The UCD3138 has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This
comes in two forms:
• Sync FET ramp
• Ideal Diode Emulation (IDE) calculation
When starting up a power supply, sometimes there is already a voltage on the output – this is called
prebias. It is very difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated
correctly, it may pull down the pre-bias voltage, causing the power supply to sink current.
To avoid this, Sync FETs are not turned on until after the power supply has ramped up to the nominal
voltage. The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET
Ramp logic can be used to turn them on at a rate below the bandwidth of the filter.
In discontinuous mode, the ideal on-time for the Sync FETs is a function of Vin, Vout, and the primary side
duty cycle (D). The IDE logic in the UCD3138 takes Vin and Vout data from the firmware and combines it
with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync
FETs.
4.12 Automatic Mode Switching
Automatic Mode switching enables the DPWM module to switch between modes automatically, with no
firmware intervention. This is useful to increase efficiency and power range. The following paragraphs
describe phase-shifted full bridge and LLC examples:
4.12.1 Phase Shifted Full Bridge Example
In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather
than phase shift, at light load. This is shown below:
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Q1B
Q1T
QSR1
QSR2
fs< fr
fr
fs= fr_max fs> fr
PWM
Mode LLC Mode
Tr= 1/fr
Tr= 1/fr
ISEC(t )
SynFET Primary
QT1
QB1
Lr
ISOLATED
GATE Transformer SYNCHRONOUS
GATE DRIVE
PRIM
CURRENT
VOUT
+12V
T1
T1
ORING
CTL
VA
VBUS
QT2
QB2
D1
D2
T2
L1
Q5
C1 RL
C2
R2
Q6
Q7
I_SHARE
Vout
Iout
I_pri
temp
Vin
VA
UCD 3138
ARM7
FAULT 0
AD01
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD00
AD06/CMP5
FAULT 1
FAULT 2
GPIO2
GPIO3
GPIO1
AD07/CMP6
AD08
AD09
DPWM0B
DPWM1B
DPWM2A
DPWM2B
ORING_CRTL
P_GOOD
DPWM3A
DPWM3B
Vout
ON/OFF
FAILURE
ACFAIL_OUT
ACFAIL_IN
I_pri
Iout
EADC0
EADC1
CLA0
CLA1
EADC2
DPWM0
DPWM1
DPWM2
DPWM3
Duty for mode
switching
Vref
Load Current
PCM
CBC
<
DPWM3A
DPWM3B
DPWM2A
DPWM2B
DPWM0B
DPWM1B
CPCC
PMBus
UART1
UART0
Primary
OSC
WD
RST
Memory
FAULT
Current
Sensing
I_pri
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
Figure 4-3. Secondary-Referenced Phase-Shifted Full Bridge Control
With Synchronous Rectification
4.12.2 LLC Example
In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is
used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the
synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the
LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator
monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the
programmable comparator reference the pulse is immediately terminated. Due to classic instability issues
associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse
width of DPWMA. Here are the waveforms for the LLC:
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Q1T
CRES
CRES
LM
LK
Q1B
VBUS
VBUS
Transformer
COUT1
QSR1
QSR2
LRES
DPWM0A
DPWM0B
DPWM1A
DPWM1B
Driver
Driver
Driver
Driver
RS
RS1
RS2
CS
RF2 CF
RF1
RLRES
ESR1
COUT2
ESR2
EAP0
EAN0
NP
NS
NS
AD04
ADC13
EAP1
AD03
Oring Circuitry
VOUT
ILR(t)
ILM(t)
ISEC(t)
VCR(t)
VOUT(t)
Rectifier and filter
UCD3138
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Figure 4-4. Secondary-Referenced Half-Bridge Resonant LLC Control
With Synchronous Rectification
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Filter Duty
Low – Lower Threshold
High – Lower Threshold
Control
Register 1
Auto Config High
Auto Config Mid
High – Upper Threshold
Low – Upper Threshold
0
Full Range
Automatic Mode Switching
With Hysteresis
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
4.12.3 Mechanism for Automatic Mode Switching
The UCD3138 allows the customer to enable up to two distinct levels of automatic mode switching. These
different modes are used to enhance light load operation, short circuit operation and soft start. Many of the
configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching,
some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.
If automatic mode switching is enabled, the filter duty signal is used to select which of these three
registers is used. There are 4 registers which are used to select the points at which the mode switching
takes place. They are used as shown below.
As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto
Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go
back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between
modes if the filter duty is close to a mode switching point.
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A ON SELECT
A OFF SELECT
B ON SELECT
B OFF SELECT
EGEN A
EGEN B
EDGE GEN
PWM A
PWM B
B SELECT
A SELECT
INTRAMUX
A/B/C (N)
A/B/C (N+1)
C (N+2)
C (N+3)
A(N)
B(N)
A(N+1)
B(N+1)
UCD3138
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4.13 DPWMC, Edge Generation, IntraMux
The UCD3138 has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB
waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.
DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the
Blanking A end time.
The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and
uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next
DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.
The options are:
0 = DPWM(n) A Rising edge
1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge
Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.
The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.
The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The
IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to
generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge,
especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and
DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high
resolution must be disabled, and DPWM edge resolution goes down to 4 ns.
Here is a drawing of the Edge Gen/Intra Mux:
Here is a list of the IntraMux modes for DPWMA:
0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
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5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
and for DPWMB:
0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
3 = DPWMA(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:
DPWM(n) DPWM3
DPWM(n+1) DPWM0
DPWM(n+2) DPWM1
DPWM(n+3) DPWM2
4.14 Filter
The UCD3138 filter is a PID filter with many enhancements for power supply control. Some of its features
include:
• Traditional PID Architecture
• Programmable non-linear limits for automated modification of filter coefficients based on received
EADC error
• Multiple coefficient sets fully configurable by firmware
• Full 24-bit precision throughout filter calculations
• Programmable clamps on integrator branch and filter output
• Ability to load values into internal filter registers while system is running
• Ability to stall calculations on any of the individual filter branches
• Ability to turn off calculations on any of the individual filter branches
• Duty cycle, resonant period, or phase shift generation based on filter output.
• Flux balancing
• Voltage feed forward
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P
I 26
D
24
All are S0.23
24 +
24
Saturate Yn
S2.23 S0.23
24
Shifter
S0.23
24
Yn Scale
Clamp
S0.23
24
Filter Yn
Clamp High
Filter Yn
Clamp Low
Filter Yn
X
24
24
24
Ki_yn reg
Kp Coef
Xn-1 Reg
Xn 16
24
<>
9
9
16
24 24
24
24
24
24
Clamp
Kd yn_reg
Kd alpha
9
16
9 24
24
24
24
P
I
D
Limit Comparator
PID Filter Branch Stages
Ki High
EADC_DATA
9
9 9
9
24
32
Ki Coef
Kd coef
Limit 5
9
9
Limit 6
…..
Limit 0
Coefficient
select
Ki Low
Optional
Selected
by
KI_ADDER_
MODE
Clamp
X
X
X
+
-
+
+
Round
X X +1 n n –
UCD3138
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Here is the first section of the Filter :
The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note
that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D
alpha pole.
The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected
depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher
errors to improve transient response.
Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional
bits).:
This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.
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18
24
14
38 18
KCompx
DPWMx Period
Loop_VFF
Filter YN (Duty %) Filter Duty
S0.23
14.0
14.0
14.0
14.0
S14.23
Resonant Duty 14.0
Round to
18 bits,
Clamp to
Positive
Clamp
Filter Output
Clamp High
Filter Output
Clamp Low
X 14.4 14.4
OUTPUT_MULT_SEL
14
Bits [17:4]
Filter Period
24
14
38 18
KCompx
DPWMx Period
Filter YN
S0.23
14.0 14.0
14.0
S14.23
Round to
18 bits,
Clamp to
Positive
Truncate
X low 4 bits
14.0
PERIOD_MULT_SEL
14.4
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
There is a final section for the filter, which permits its output to be matched to the DPWM:
This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period,
to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant
mode, the filter can be used to generate both period and duty cycle.
4.14.1 Loop Multiplexer
The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end,
and DPWM can be combined with each other in many configurations.
It also controls the following connections:
• DPWM to Front End
• Front End DAC control from Filters or Constant Current/Constant Power Module
• Filter Special Coefficients and Feed Forward
• DPWM synchronization
• Filter to DPWM
The following control modules are configured in the Loop Mux:
• Constant Power/Constant Current
• Cycle Adjustment (Current and flux balancing)
• Global Period
• Light Load (Burst Mode)
• Analog Peak Current Mode
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FAULT - CBC
FAULT - AB
FAULT -A
DCOMP– 4X
EXT GPIO– 4X
ACOMP– 7X
FAULT -B
FAULT MODULE
FAULT MODULE
FAULT MODULE
CYCLE BY CYCLE
AB FLAG
AB FLAG
A FLAG
B FLAG
FAULT MUX
ALL_FAULT_EN DPWM_EN
DPWM
CBC_FAULT_EN
CBC_PWM_AB_EN
FAULT MODULE
ANALOG PCM
Bit20 in DPWMCTRL0
Bit30 in DPWMFLTCTRL
Bit 31 in DPWMFLTCTRL Bit0 in DPWMCTRL0
DISABLE PWM A AND B
DISABLE PWM A AND B
DISABLE PWM A ONLY
DISABLE PWM B ONLY
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.14.2 Fault Multiplexer
In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the
UCD3138 provides an extensive array of multiplexers that are united under the name Fault Mux module.
The Fault Mux Module supports the following types of mapping between all the sources of fault and all
different fault response mechanism inside each DPWM module.
• Many fault sources mapped to a single fault response mechanism. For instance an analog comparator
in charge of over voltage protection, a digital comparator in charge of over current protection and an
external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE
and shut down DPWM1-A.
• A single fault source can be mapped to many fault response mechanisms inside many DPWM
modules. For instance an analog comparator in charge of over current protection can be mapped to
DPWM-0 through DPWM-3 by way of several fault modules.
• Many fault sources can be mapped to many fault modules inside many DPWM modules.
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CYCLE BY CYCLE
FAULT - CBC CLIM
FAULT MODULE
FAULT IN FAULT FLAG
MAX COUNT
FAULT EN
DPWM EN
UCD3138
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The Fault Mux Module provides a multitude of fault protection functions within the UCD3138 high-speed
loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly
configurable fault generation based on digital comparators, high-speed analog comparators and external
fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of
the fault events provided in the Fault Mux Module.
Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB
fault module, A fault module and B fault module.
The internal circuitry in all the four fault modules is identical, and the difference between the modules is
limited to the way the modules are attached to the DPWMs.
All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of
the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle
faults count exceeds max_count.
Once the fault flag is set DPWMs need to be disabled by DPWM_EN going low in order to clear the fault
flags. Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault
Modules) will be cleared simultaneously.
All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module
cannot be enabled/ disabled separately.
Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.
The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to
signals arriving from Analog Peak current mode (PCM) module.
The Fault Mux Module supports the following basic functions:
• 4 digital comparators with programmable thresholds and fault generation
• Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
• External GPIO detection control with programmable fault generation
• Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection
Fault, DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
• Clock Failure Detection for High and Low Frequency Oscillator blocks
• Discontinuous Conduction Mode Detection
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Digital Comparator 0
Control
Digital Comparator 1
Control
Digital Comparator 2
Control
Digital Comparator 3
Control
Front End
Control 0
Front End
Control 1
Front End
Control 2
Analog
Comparator 0
Analog Comparator 0
Control
Analog
Comparator 1
Analog Comparator 1
Control
Analog
Comparator 2
Analog Comparator 2
Control
Analog
Comparator 3
Analog Comparator 3
Control
Analog
Comparator 4
Analog Comparator 4
Control
Analog
Comparator 5
Analog Comparator 5
Control
Analog
Comparator 6
Analog Comparator 6
Control
External GPIO
Detection
fault[2:0]
DPWM 0 DPWM 1 DPWM 2 DPWM 3
DPWM 0
Fault Control
DPWM 1
Fault Control
DPWM 2
Fault Control
DPWM 3
Fault Control
Analog Comparator
Automated Ramp
DCM Detection
HFO/LFO
Fail Detect
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Figure 4-5. Fault Mux Block Diagram
4.15 Communication Ports
4.15.1 SCI (UART) Serial Communication Interface
A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous
Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous startstop
serial data communication (see the pin out sections for details) Each interface has a 24 bit for
supporting programmable baud rates and has programmable data word and stop bit options. Half or full
duplex operation is configurable through register bits. A loop back feature can also be setup for firmware
verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being
used.
4.15.2 PMBUS
The PMBus Interface supports independent master and slave modes controlled directly by firmware
through a processor bus interface. Individual control and status registers enable firmware to send or
receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I2C
Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol
Specification.
The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit
address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write
enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading
and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface
connects directly to the I2C/SMBus/PMBus Clock, Data, Alert, and Control signals.
Example: PMBus Address Decode via ADC12 Reading
The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address
decoding. At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is
captured by the internal 12-bit ADC.
Where bin(VAD0x) is the address bin for one of 12 address as shown in Figure 4-6.
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Vdd
IBIAS
To ADC Mux
On/Off Control
AD00,
AD01
pin
Resistor to
set PMBus
Address
UCD3138
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Figure 4-6. PMBus Address Detection Method
4.15.3 General Purpose ADC12
The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:
• Typical conversion speed of 267 ksps
• Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
• Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
• Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,
ADC_EXT_TRIG pin or Analog Comparator results
• Interrupt capability to embedded processor at completion of ADC conversion
• Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data
or averaged ADC data
• Two 10 μA current sources for excitation of PMBus addressing resistors
• Dual sample and hold for accurate power measurement
• Internal temperature sensor for temperature protection and monitoring
The control module ( ADC12 Contol Block Diagram) contains the control and conversion logic for autosequencing
a series of conversions. The sequencing is fully configurable for any combination of 16
possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted,
the selected channel value is stored in the result register associated with the sequence number. Input
channels can be sampled in any desired order or programmed to repeat conversions on the same channel
multiple times during a conversion sequence. Selected channel conversions are also stored in the result
registers in order of conversion, where the result 0 register is the first conversion of a 16-channel
sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels
converted in a sequence can vary from 1 to 16.
Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops,
the ADC12 is not usually used for loop compensation purposes. The EADC converters have a
substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12
features make it best suited for monitoring and detection of currents, voltages, temperatures and faults.
Please see the Typical Characteristics plots for the temperature variation associated with this function.
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ADC
Channels
S/H
12-bit SAR
ADC
ADC12 Block
ADC12
Control
ADC Channel
ADC
Averaging
Digital
Comparators
DPWM
Modules
ADC12 Registers
Analog
Comparators
ADC External Trigger (from pin)
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Figure 4-7. ADC12 Control Block Diagram
4.15.4 Timers
External to the Digital Power Peripherals there are 3 different types of timers in UCD3138. They are the
24-bit timer, 16-bit timer and the Watchdog timer
4.15.4.1 24-bit PWM Timer
There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down
by an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data
Registers) for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data
Buffer register) which can be used to store CPU updates of the compare events while still using the timer.
The selected shadow register update mode happens after the compare event matches.
The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can
be set either to rising, falling, or both edges of the capture pin. Upon this event, the counter value is stored
in the corresponding capture data register.
The counter reset can be configured to happen on a counter roll over, a compare equal event, or by
software controlled register. Five Interrupts from the PWM timer can be set, which are the counter rollover
event (overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt can be
disabled or enabled.
Upon an event comparison on only the second event, the TCMP pin can be configured to set, clear, toggle
or have no action at the output. The value of PWM pin output can be read for status or simply configured
as general purpose I/O for reading the value of the input at the pin. The first compare event can only be
used as an interrupt.
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4.15.4.2 16-Bit PWM Timers
There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided
down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers
(Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register
(Data Buffer register) which can be used to store CPU updates of compare events while still using the
timer. The selected shadow register update mode happens after the compare event matches.
The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a
software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event
(overflow) or by the two comparison match events. Each comparison match and the overflow interrupts
can be disabled or enabled.
Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the
output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O
for reading the value of the input at the pin.
4.15.4.3 Watchdog Timer
A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is
clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is
issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key
register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the
watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled
state. A half timer flag is also provided for status monitoring of the watchdog.
4.16 Miscellaneous Analog
The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a
wide variety of functions. These functions include device supervisory features such as Brown-Out and
power saving configuration, general purpose input/output configuration and interfacing, internal
temperature sensor control and current sharing control.
The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually
used at the time of trimming at manufacturing; therefore this document will not cover these trim controls.
The MAC registers and peripherals are all available in the UCD3138 (64 pin version). Other UCD3138
devices may have reduced resources. See the device pin out description for details.
4.17 Package ID Information
Package ID register includes information regarding the package type of the device and can be read by
firmware for reporting through PMBus or for other package sensitive decisions.
BIT NUMBER 1:0
Bit Name PKG_ID
Access R/W
Default 0 – UCD3138RGC, 1 – UCD3138RHA
4.18 Brownout
Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a
condition that may be considered unsafe for proper operation of the device.
The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is
lower than brownout threshold, it still does not necessarily trigger a device reset.
The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by
an interrupt service routine. Please see the Power On Reset (POR) / Brown Out Reset (BOR) section.
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4.19 Global I/O
Up to 30 pins in UCD3138 can be configured to serve as a general purpose input or output pin (GPIO).
This includes all digital input or output pins except for the RESET pin.
The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input
pins, EADC analog input pins and the RESET pin.
There are two ways to configure and use the digital pins as GPIO pins:
1. Through the centralized Global I/O control registers.
2. Through the distributed control registers in the specific peripheral that shares it pins with the standard
GPIO functionality.
The Global I/O registers offer full control of:
1. Configuring each pin as a GPIO.
2. Setting each pin as input or output.
3. Reading the pin’s logic state, if it is configured as an input pin.
4. Setting the logic state of the pin, if it is configured as an output pin.
5. Connecting pin/pins to high rail through internal pull up resistors.
The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain
Control Register, Global I/O Value Register and Global I/O Read Register.
The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:
BIT NUMBER 29:0
Bit Name GLOBAL_IO_EN
Access R/W
Default 00_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.
PIN NUMBER
BIT PIN_NAME
UCD3138-64 PIN UCD3138-40 PIN
29 FAULT[3] 43 NA
28 ADC_EXT_TRIG 12, 26 8
27 TCK 37 21
26 TDO 38 20
25 TMS 40 24
24 TDI 39 23
23 SCI_TX[1] 29 NA
22 SCI_TX[0] 14 22
21 SCI_RX[1] 30 NA
20 SCI_RX[0] 13 23
19 TMR_CAP 12, 26, 41 8, 21
18 TMR_PWM[1] 32 NA
17 TMR_PWM[0] 12, 26, 31, 37 21
16 PMBUS-CLK 15 9
15 PMBUS-DATA 16 10
14 CONTROL 30 20
13 ALERT 29 19
12 EXT_INT 26, 34 NA
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Temperature
Sensor
Ch14
ADC 12
Temp Cal
UCD3138
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PIN NUMBER
BIT PIN_NAME
UCD3138-64 PIN UCD3138-40 PIN
11 FAULT[2] 42 25
10 FAULT[1] 36 23
9 FAULT[0] 35, 39 22
8 SYNC 12, 26,37 8, 21
7 DPWM3B 24 18
6 DPWM3A 23 17
5 DPWM2B 22 16
4 DPWM2A 21 15
3 DPWM1B 20 14
2 DPWM1A 19 13
1 DPWM0B 18 12
0 DPWM0A 17 11
4.20 Temperature Sensor Control
Temperature sensor control register provides internal temperature sensor enabling and trimming
capabilities. The internal temperature sensor is disabled as default.
Figure 4-8. Internal Temp Sensor
Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.
The temperature sensor is measured using ADC12 (via Ch14). The temperature is then calculated using a
mathematical formula involving the calibration register (this effectively adds a delta to the ADC
measurement).
The temperature sensor can be enabled or disabled.
4.21 I/O Mux Control
In different packages of UCD3138 several I/O functions are multiplexed and routed toward a single
physical pin. I/O Mux Control register may be used in order to choose a single specific functionality that is
desired to be assigned to a physical device pin for your application.
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EXT CAP
AD02
400 Ω
Digital
RSHARE
250 Ω
3.3 V
ISHARE
ADC12 and
CMP
ESD
ESD
3.2 kΩ 250 Ω
ESD
AD13
3.3V
SW2
SW1
SW3
3.3 V
ADC12 and
CMP
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.21.1 JTAG Use for I/O and JTAG Security
The UCD3138 provides a JTAG interface for debugging and for uploading data and programs. The pins
are multiplexed with other pins, and will not be available in certain topologies. For power supplies, other
debugging techniques (PMBus, UART, code instrumentation) are often superior to JTAG. Code
downloading is much faster via PMBus, or with a user boot program via UART. PMBus support is
available from TI. JTAG for debugging has limited support from TI’s Code Composer Studio. JTAG
parameter download may be supported by third parties.
4.22 Current Sharing Control
UCD3138 provides three separate modes of current sharing operation.
• Analog bus current sharing
• PWM bus current sharing
• Master/Slave current sharing
• AD02 has a special ESD protection mechanism that prevents the pin from pulling down the currentshare
bus if power is missing from the UCD3138
The simplified current sharing circuitry is shown in the drawing below:
Figure 4-9. Simplified Current Sharing Circuitry
CURRENT SHARING MODE FOR TEST ONLY, CS_MODE EN_SW1 EN_SW2 DPWM ALWAYS KEEP 00
Off or Slave Mode (3-state) 00 00 (default) 0 0 0
PWM Bus 00 01 1 0 ACTIVE
Off or Slave Mode (3-state) 00 10 0 0 0
Analog Bus or Master 00 11 0 1 0
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The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be
controlled through the current sharing control register (CSCTRL).
4.23 Temperature Reference
The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the
internal temperature sensor (channel 14) during the factory trim and calibration.
This information can be used by different periodic temperature compensation routines implemented in the
firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost.
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2 .2 μF
1 .0 μF
BPCAP
DGND
V33D
UCD3138
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5 IC Grounding and Layout Recommendations
• Two grounds are recommended: AGND (analog) and DGND (digital).
– AGND plane should be on a different layer than DGND, and right under the UCD3138 device.
– UCD3138 power pad should be tied to AGND plane by at least 4 vias
– AGND plane should be just large enough to connect to all required components.
– Power ground (PGND) can be independent or combined with DGND
– The power pad of the driver IC should be tied to DGND
• Both 3.3VD and 3.3VA should have a local 4.7μF capacitor placed as close as possible to the device
pins
• BPCAP decoupling (2.2 μF typically) MUST be connected to DGND
• All analog signal filter capacitors should be tied to AGND
– If the gate driver device, such as UCD27524 or UCD27511/7 driver is used, the filter capacitor for
the current sensing pin can be tied to DGND for easy layout
• All digital signals, such as GPIO, PMBus and PWM are referenced to DGND.
• The RESET pin capacitor (0.1μF) should be connected to either DGND or AGND locally. A 10kΩ pullup
resistor to 3.3V is recommended.
• All filter and decoupling capacitors should be placed close to UCD3138 as possible
– Resistor placement is less critical and can be moved a little further away
• The DGND and AGND net-short resistor MUST be placed right between one UCD3138’s DGND pin
and one AGND pin. Ground connections to the net short element should be made by a large via (or
multiple paralleled vias) for each terminal of the net-short element.
• If a gate driver device such as UCC27524 or UCC27511/7 is on the control card and there is a PGND
connection, a net-short resistor should be tied to the DGND plane and PGND plane by multiple vias. In
addition the net-short element should be close to the driver IC.
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6 Tools and Documentation
The application firmware for UCD3138 is developed on Texas Instruments Code Composer Studio (CCS)
integrated development environment (v3.3 recommended).
Monitoring and Configuration of key device parameters and real time debug capabilities are offered
through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER Graphical User Interface (GUI),
http://www.ti.com/tool/fusion_digital_power_designer.
The FUSION_DIGITAL_POWER_DESIGNER software application uses PMBus protocol to communicate
with the device over serial bus by way of a interface adaptor known as USB-TO-GPIO, available as an
EVM from Texas Instruments (http://www.ti.com/tool/usb-to-gpio).
The software application can also be used to program the devices, with a version of the tool known as
FUSION_MFR_GUI optimized for manufacturing environments (http://www.ti.com/tool/fusion_mfr_gui).
The FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and
reporting capabilities.
In terms of reference documentation, the following 3 programmer’s manuals are available offering detailed
information regarding the application and usage of UCD3138 digital controller:
1. UCD3138 Digital Power Peripheral Programmer's Manual Key topics covered in this manual include:
– Digital Pulse Width Modulator (DPWM)
– Modes of Operation (Normal/Multi/Phase-shift/Resonant etc)
– Automatic Mode Switching
– DPWMC, Edge Generation & Intra-Mux
– Front End
– Analog Front End
– Error ADC or EADC
– Front End DAC
– Ramp Module
– Successive Approximation Register Module
– Filter
– Filter Math
– Loop Mux
– Analog Peak Current Mode
– Constant Current/Constant Power (CCCP)
– Automatic Cycle Adjustment
– Fault Mux
– Analog Comparators
– Digital Comparators
– Fault Pin functions
– DPWM Fault Action
– Ideal Diode Emulation (IDE), DCM Detection
– Oscillator Failure Detection
– Register Map for all of the above peripherals in UCD3138
2. UCD3138 Monitoring and Communications Programmer’s Manual
Key topics covered in this manual include:
– ADC12
– Control, Conversion, Sequencing & Averaging
– Digital Comparators
– Temperature Sensor
– PMBUS Addressing
– Dual Sample & Hold
– Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating)
– PMBUS Interface
– General Purpose Input Output (GPIO)
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– Timer Modules
– PMBus
– Register Map for all of the above peripherals in UCD3138
3. UCD3138 ARM and Digital System Programmer’s Manual
Key topics covered in this manual include:
– Boot ROM & Boot Flash
– BootROM Function
– Memory Read/Write Functions
– Checksum Functions
– Flash Functions
– Avoiding Program Flash Lock-Up
– ARM7 Architecture
– Modes of Operation
– Hardware/Software Interrupts
– Instruction Set
– Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode)
– Memory & System Module
– Address Decoder, DEC (Memory Mapping)
– Memory Controller (MMC)
– Central Interrupt Module
– Register Map for all of the above peripherals in UCD3138
In addition to the tools and documentation described above, for the most up to date information regarding
evaluation modules, reference application firmware and application notes/design tips, please visit
http://www.ti.com/product/ucd3138.
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7 References
1. UCD3138 Digital Power Peripherals Programmer’s Manual (Literature Number:SLUU995)
2. UCD3138 Monitoring & Communications Programmer’s Manual (Literature Number:SLUU996)
3. UCD3138 ARM and Digital System Programmer’s Manual (Literature Number:SLUU994)
4. Code Composer Studio Development Tools v3.3 – Getting Started Guide, (Literature Number:
SPRU509H)
5. ARM7TDMI-S Technical Reference Manual
6. System Management Bus (SMBus) Specification
7. PMBusTM Power System Management Prototcol Specification (1)
(1) PMBus is a trademark of SMIF, Inc.
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2012) to Revision A Page
• Added Production Data statement to footnote and removed "Product Preview" banner ........................... 6
Changes from Revision A (March 2012) to Revision B Page
• Added Feature bullets ............................................................................................................. 6
• Changed "Dual Edge Modulation" to "Triangular Modulation" in Features section ................................. 6
• Changed "265 ksps" to "267 ksps" in Features section ................................................................... 6
• Clarified number of UARTs in Feature section ............................................................................... 6
• Changed "FDPP" to "DDP" throughout. ....................................................................................... 7
• Changed Total GPIO pin count for the UCD3138 40-pin device from "17" to "18" in the Product Selection
Matrix table. .......................................................................................................................... 8
• Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 16
• Changed EAP – EAN Error voltage digital resolution MIN values for AFE=3, AFE=2, AFE=1, AFE=0 from
0.95, 1.90, 3.72, and 7.3 respectively; to, 0.8, 1.7, 3.55, and 6.90 respectively. ....................................... 16
• Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 17
• Changed conditions for VOL and VOH specs in the Electrical Characteristics table ................................. 17
• Added TWD spec to Electrical Characteristics table ...................................................................... 17
• Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 18
• Changed "PWM" to "DPWM" in DPWM Module. ............................................................................ 29
• Changed "PWMA" and "PWMB" to "DPWMA" and "DPWMB" in . ...................................................... 34
• Changed waveforms graphic for "Phase Shifted Full Bridge Example" for clarification .......................... 41
• Added text to section LLC Example .......................................................................................... 42
• Changed typical conversion speed from "268 ksps" to "267 ksps" in the General Purpose ADC12
section. .............................................................................................................................. 52
• Added package ID information for the UCD3138RGC and UCD3138RHA devices. ................................. 54
• Added bullet "AD02 has a special ESD protection mechanism that prevents the pin from pulling down
the current-share bus if power is missing from the UCD3138" to Current Sharing Control. ..................... 57
• Added sub-bullet "The power pad of the driver IC should be tied to DGND" and changed capacitor value
from "0.1 μF" to "4.7 μF" in IC Grounding and Layout Recommendations ........................................... 59
• Added "Tools and Documentation" section ................................................................................. 60
• Changed " Mechanical Data" section to "References" section ......................................................... 62
Copyright © 2012, Texas Instruments Incorporated References 63
Submit Documentation Feedback
Product Folder Link(s): UCD3138
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing
Pins Package Qty Eco Plan (2) Lead/
Ball Finish
MSL Peak Temp (3) Samples
(Requires Login)
UCD3138RGCR ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
UCD3138RGCT ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
UCD3138RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
UCD3138RHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
UCD3138RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
UCD3138RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
UCD3138RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
UCD3138RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCD3138RGCR VQFN RGC 64 2000 367.0 367.0 38.0
UCD3138RGCT VQFN RGC 64 250 210.0 185.0 35.0
UCD3138RHAR VQFN RHA 40 2500 367.0 367.0 38.0
UCD3138RHAT VQFN RHA 40 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 1 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
Power Electronics R&D Center
Wireless Connectivity
Panasonic Industrial Devices Europe GmbH
APPROVED
CHECKED
DESIGNED
Specification for Production
Panasonic Industrial Devices Europe GmbH
Zeppelinstrasse 19
21337 Lüneburg
Applicant / Manufacturer
Hardware
Germany
Not applikable
Applicant / Manufacturer
Software
Software Version
Not applikable
Contents
Approval for Mass Production
Customer
Bluetooth QDL ID
Qualified Design Listing (QDL) ID: B019784
As Controller Sub-System Listing for PAN13xx Series.
By purchase of any products described in this document the customer accepts the document's validity and declares their agreement and understanding of its contents and recommendations. Panasonic reserves the right to make changes as required without notification.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 2 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
TABLE OF CONTENTS
1 Scope of this Document..................................................................................................5
1.1 New PAN1315A, PAN1325A.................................................................................5
2 Key Features...................................................................................................................6
2.1 Software Block Diagram........................................................................................6
3 Applications for the Module.............................................................................................7
4 Description for the Module..............................................................................................7
5 Detailed Description........................................................................................................8
5.1 Terminal Layout.....................................................................................................8
5.1.1 5.1.1. Terminal Layout PAN131x without antenna...................................8
5.1.2 5.1.2. Terminal Layout PAN132x with antenna........................................9
5.2 Pin Description.....................................................................................................10
5.3 Device Power Supply...........................................................................................11
5.4 Clock Inputs.........................................................................................................12
6 Bluetooth Features........................................................................................................12
7 Block Diagram...............................................................................................................13
8 Test Conditions.............................................................................................................14
9 General Device Requirements and Operation..............................................................14
9.1 Absolute Maximum Ratings.................................................................................14
9.2 Recommended Operating Conditions..................................................................15
9.3 Current Consumption...........................................................................................15
9.4 General Electrical Characteristics........................................................................16
9.5 nSHUTD Requirements.......................................................................................16
9.6 External Digital Slow Clock Requirements (–20°C to +70°C)..............................16
10 Host Controller Interface...............................................................................................17
11 Audio/Voice Codec Interface.........................................................................................18
11.1 PCM Hardware Interface.....................................................................................18
11.2 Data Format.........................................................................................................18
11.3 Frame Idle Period................................................................................................19
11.4 Clock-Edge Operation.........................................................................................20
11.5 Two-Channel PCM Bus Example........................................................................20
11.6 Audio Encoding....................................................................................................20
11.7 Improved Algorithm For Lost Packets..................................................................21
11.8 Bluetooth/PCM Clock Mismatch Handling...........................................................21
11.9 Bluetooth Inter-IC Sound (I2S)............................................................................21
11.10Current Consumption for Different Bluetooth Scenarios......................................22
12 Bluetooth RF Performance............................................................................................22
13 Soldering Temperature-Time Profile (for reflow soldering)...........................................25
13.1 For lead solder.....................................................................................................25
13.2 For leadfree solder...............................................................................................26
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 3 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
14 Module Dimension........................................................................................................27
14.1 Module Dimensions PAN131X without Antenna..................................................27
14.2 Module Dimensions PAN132X with Antenna.......................................................28
15 Footprint of the Module.................................................................................................29
15.1 Footprint PAN131x without antenna....................................................................29
15.2 Footprint PAN132x with antenna.........................................................................30
16 Labeling Drawing..........................................................................................................31
17 Mechanical Requirements.............................................................................................31
18 Recommended Foot Pattern.........................................................................................32
18.1 recommended foot pattern PAN131x without antenna........................................32
18.2 recommended foot pattern PAN132x with antenna.............................................33
19 Layout Recommendations with Antenna (PAN132x)....................................................34
20 Bluetooth LE (LOW ENERGY) PAN1316/26................................................................34
20.1 Network Topology................................................................................................34
20.2 module features...................................................................................................35
20.3 Current consumption for different LE scenarios..................................................36
21 ANT PAN1317/27..........................................................................................................36
21.1 Network topology.................................................................................................36
21.2 module features..................................................................................................37
21.3 ANT Current consumption...................................................................................37
22 Triple mode (BR/EDR + Bluetooth low energy + ANT) PAN1323................................38
22.1 Triple Mode Current consumption.......................................................................38
23 Development of Applications.........................................................................................39
23.1 Tools to be needed..............................................................................................39
24 List of Profiles...............................................................................................................40
25 Reliability Tests.............................................................................................................40
26 Cautions........................................................................................................................41
26.1 Design Notes.......................................................................................................41
26.2 Installation Notes.................................................................................................41
26.3 Usage Conditions Notes......................................................................................42
26.4 Storage Notes......................................................................................................42
26.5 Safety Cautions...................................................................................................43
26.6 Other cautions.....................................................................................................43
27 Packaging.....................................................................................................................44
27.1 Packaging of PAN131x without antenna.............................................................44
27.2 Packaging for PAN132x with antenna.................................................................47
28 Ordering Information.....................................................................................................48
29 RoHS Declaration.........................................................................................................49
30 Data Sheet Status.........................................................................................................49
31 History for this Document..............................................................................................50
32 Related Documents.......................................................................................................50
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 4 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
33 General Information......................................................................................................52
34 Regulatory Information..................................................................................................52
34.1 FCC for US..........................................................................................................52
34.1.1 FCC Notice.............................................................................................52
34.1.2 Caution...................................................................................................53
34.1.3 Labeling Requirements..........................................................................53
34.1.4 Antenna Warning....................................................................................53
34.1.5 Approved Antenna List...........................................................................53
34.1.6 RF Exposure PAN13xx..........................................................................54
34.2 Industry Canada Certification..............................................................................54
34.3 European R&TTE Declaration of Conformity.......................................................54
34.4 NCC for Taiwan...................................................................................................56
34.4.1 Labeling Requirements..........................................................................56
34.4.2 NCC Statement......................................................................................56
34.5 Bluetooth SIG Statement.....................................................................................56
35 Life Support Policy........................................................................................................56
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 5 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
1
SCOPE OF THIS DOCUMENT
This product specification describes Panasonic’s HCI, Class 1.5 , TI based, Bluetooth®1 modules, series number 13xx.
For detailed family overview that includes part numbers see Chapter 28, Ordering Information.
Non-antenna versions will be refered to as PAN131x, versions with antenna will be refered to as PAN132x in this document.
Fore information and features on Bluetooth Low Energy 4.0 refer to Chapter 19, for information on ANT refer to Chapter 21.
1.1
NEW PAN1315A, PAN1325A
The PAN1315A/1325A Series is based on Texas Instruments’ NEW CC2560A controller. A ROM update from Texas Instruments to the CC2560 IC has allowed Panasonic to improve PAN1315/1325 Series. The NEW PAN1315A/1325A Series Modules has increased power and system efficiency resulting from reduced initialization script size, start-up time and decreased system memory requirements.
Compatibility:
PAN1315, PAN1315A, PAN1316 and PAN1317 are 100% footprint compatible
PAN1325, PAN1325A, PAN1326 and PAN1327 are 100% footprint compatible
As an updated initialization script resident on the application microcontroller is required for modules based on the CC2560A, compatibility between the PAN1315/PAN1325 and PAN1315A/PAN1325A is dependant on the Bluetooth stack. Stacks are available that will operate with all PAN1315/1325 variations.
BT-Stack solutions provided by software development partners are available for most processors, including linux based host systems..
For detailed family overview that includes part numbers see Chapter 28 Ordering Information.
Contact your stack provider or local Panasonic sales company for currently available Bluetooth Profiles.
1 Bluetooth is a registered trademark of the Bluetooth Special Interest Group.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 6 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
2
KEY FEATURES
•
Bluetooth specification v2.1 + EDR (Enhanced Data Rate)
•
Surface mount type 6.5(9.5 w. Ant.) x 9.0 x 1.8 mm³
•
Up to 10.5dBm Tx power (typical) with transmit power control
•
High sensitivity (-93 dBm typ.)
•
Texas Instrument’s CC256X BlueLink 7.0 inside
•
Fast Connection Setup
•
Extended SCO Link
•
Supports convenient direct connection to battery (2.2-4.8 V), or connect to DC/DC (1.7-1.98 V) for improved power efficiency
•
Internal crystal oscillator (26MHz)
•
Fully shielded for immunity
•
Full Bluetooth data rate up to 2,178kbps asymmetric
•
Support for Bluetooth power saving modes (Sniff, Hold)
•
Support for very low-power modes (deep sleep and power down)
•
Optional support for ultra-low-power mode. Standby with Battery-Backup
•
PCM Interface Master / Slave supporting 13 or 16 bit linear, 8 bit μ-law or A-law Codecs and CVSD transcoders on up to 3 SCO channels
•
Full 8- to 128-bit encryption
•
UART, I²C and PCM Interface
•
IO operating voltage = 1.8 V nominal
•
3 Channel ADC and 1 Channel DAC
•
Bluetooth profiles such as SPP, A2DP and others are available. Refer to Panasonic’s RF module website for a listing of the most current releases.
•
Manufactured in conformance with RoHS
2.1
SOFTWARE BLOCK DIAGRAM
PAN13xxHost ProcessorApplicationBD/EDRBLEANTHCIL2CAPHCIRF BlockPAN13xxHost Block
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
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SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 7 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
APPLICATIONS FOR THE MODULE
All Embedded Wireless Applications
•
Smart Phones
•
Cable Replacement
•
Industrial Control
•
Automotive
•
Medical
•
Access Points
•
Scanners
•
Consumer Electronics
•
Wireless Sensors
•
Monitoring and Control
•
Low Power
•
Access Points
4
DESCRIPTION FOR THE MODULE
The PAN1315 and PAN1315A are short-range, Class 1 or 2, HCI modules for implementing Bluetooth functionality into various electronic devices. A block diagram can be found in Chapter 7.
Communication between the module and the host controller is carried out via UART.
New designs can be completed quickly by mating the PAN13xx series modules with Texas Instruments’ MSP430BT5190 that contains Mindtree’s EtherMind Bluetooth Protocol Stack and serial port profile, additional computing power can be achieved by choosing TI’s Stellaris ARM7 controller that includes StoneStreet One's A2DP profile. Other BT profiles are available on custom development basis.
Additional controllers are also supported by the PAN13xx series by using a TI/Panasonic software development partner to port the Bluetooth stack and profiles. Mindtree's Software Development Kit (SDK) is available on TI's website -- www.ti.com/connectivity.com
Contact your local sales office for further details on additional options and services, by visiting www.panasonic.com/rfmodules or write an e-mail to wireless@eu.panasonic.com.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 8 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
5
DETAILED DESCRIPTION
5.1
TERMINAL LAYOUT
5.1.1
5.1.1. Terminal Layout PAN131x without antenna
No
Pin Name
Pull at Reset
Def. Dir. 2
I/O Type 3
Description of Options (Common)
1
GND
Connect to Ground
2
TX_DBG
PU
O
2 mA
Logger output
3
HCI_CTS
PU
I
8 mA
HCI UART clear-to-send.
4
HCI_RTS
PU
O
8 mA
HCI UART request-to-send.
5
HCI_RX
PU
I
8 mA
HCI UART data receive
6
HCI_TX
PU
O
8 mA
HCI UART data transmit
7
AUD_FSYNC
PD
IO
4 mA
PCM frame synch. (NC if not used) Fail safe4
8
SLOW_CLK_IN
I
32.768-kHz clock in Fail safe
9
NC
IO
Not connected
10
MLDO_OUT
O
Main LDO output (1.8 V nom.)
11
CL1.5_LDO_IN
I
PA LDO input
12
GND
Connect to Ground
13
RF
IO
Bluetooth RF IO
14
GND
Connect to Ground
15
MLDO_IN
I
Main LDO input
16
nSHUTD
PD
I
Shutdown input (active low).
17
AUD_OUT
PD
O
4 mA
PCM data output. (NC if not used) Fail safe
18
AUD_IN
PD
I
4 mA
PCM data input. (NC if not used) Fail safe
19
AUD_CLK
PD
IO
HY, 4 mA
PCM clock. (NC if not used) Fail safe
20
GND
Connect to Ground
21
NC
EEPROM I²C SDA (Internal)
22
VDD_IO
PI
I/O power supply 1.8 V Nom
23
NC
EEPROM I²C SCL (Internal)
24
NC
IO
Not connected
2 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down
3 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ. output current
4 No signals are allowed on the IO pins if no VDD_IO (Pin 22) power supplied, except pin 7, 8, 17-19.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
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CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
5.1.2
5.1.2. Terminal Layout PAN132x with antenna
No
Pin Name
Pull at Reset
Def. Dir. 5
I/O Type 6
Description of Options (Common)
A
GND
Connect to Ground
B
GND
Connect to Ground
C
GND
Connect to Ground
D
GND
Connect to Ground
No 1-24 see above in Chapter 5.1.1. Except PIN 13 is not connected. For RF conducted measurements, either use the PAN1323ETU or de-solder the antenna and solder an antenna connector to the hot pin.
5 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down
6 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ. output current
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5.2
PIN DESCRIPTION
Pin Name
No
ESD 7 (V)
Pull at Reset
Def. Dir. 8
I/O Type 9
Description of Options
Bluetooth IO SIGNALS
HCI_RX
5
750
PU
I
8 mA
HCI UART data receive
HCI_TX
6
750
PU
O
8 mA
HCI UART data transmit
HCI_RTS
4
750
PU
O
8 mA
HCI UART request-to-send.
HCI_CTS
3
750
PU
I
8 mA
HCI UART clear-to-send.
AUD_FYSNC
7
500
PD
IO
4 mA
PCM frame synch (NC if not used) Fail safe
AUD_CLK
19
500
PD
IO
HY, 4 mS
PCM clock (NC if not used) Fail safe
AUD_IN
18
500
PD
I
4 mA
PCM data input (NC if not used) Fail safe
AUD_OUT
17
500
PD
O
4 mA
PCM data output (NC if not used) Fail safe
Logger output
TX_DBG
2
1000
PU
O
2 mA
OPTION: nTX_DBG – logger out (low = 1)
CLOCK SIGNALS
SLOW_CLK_IN
8
1000
I
32.768-kHz clock in Fail safe
Bluetooth ANALOG SIGNALS
RF
13
1000
IO
Bluetooth RF IO (not connected with antenna)
nSHUTD
16
1000
PD
I
Shutdown input (active low).
Bluetooth POWER AND GND SIGNALS
VDD_IO
22
1000
PI
I/O power supply 1.8 V Nom
MLDO_IN
15
1000
I
Main LDO inputConnect directly to battery or to a pre-regulated 1.8-V supply
MLDO_OUT
10
1000
O
Main LDO output (1.8 V nom.) Can not be used as 1.8V supply due to internal connection to the RF part.
CL1.5_LDO_IN
11
1000
I
PA LDO input
Connect directly to battery or to a pre-regulated 1.8-V supply
GND
1
P
Connect to Ground
GND
12
P
Connect to Ground
GND
14
P
Connect to Ground
GND
20
P
Connect to Ground
EEPROM IO SIGNALS (EEPROM is optional in PAN13x product line)
NC
23
1000
PU/PD
I
HY, 4mA
EEPROM I²C SCL (Internal)
NC
21
1000
PU/PD
IO
HY, 4mA
EEPROM I²C IRQ (Internal)
Remark:
HCI_CTS is an input signal to the CC256X device:
- When HCI_CTS is low, then CC256X is allowed to send data to Host device.
- When HCI_CTS is high, then CC256X is not allowed to send data to Host device.
7 ESD: Human Body Model (HBM). JEDEC 22-A114
8 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down
9 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ output current
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5.3
DEVICE POWER SUPPLY
The PAN13XX Bluetooth radio solution is intended to work in devices with a limited power budget such as cellular phones, headsets, hand-held PC’s and other battery-operated devices. One of the main differentiators of the PAN13XX is its power management – its ability to draw as little current as possible.
The PAN13XX device requires two kinds of power sources:
• Main power supply for the Bluetooth - VDD_IN = VBAT
• Power source for the 1.8 V I/O ring - VDD_IO
The PAN13XX includes several on-chip voltage regulators for increased noise immunity. The PAN13XX can be connected either directly to the battery or to an external 1.8-V DC to DC converter.
There are three ways to supply power:
•
Full-VBAT system:
Maximum RF output power, but not optimum system power:
•
Full-DC2DC system:
Lower RF output power, but optimum system power:
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•
Mixed DC2DC-VBAT system:
Maximum RF output power and optimum system power, but requires routing of VBAT:
5.4
CLOCK INPUTS
The slow clock is always supplied from an external source. It is connected to the SLOW_CLK_IN pin number 8 and can be a digital signal with peak to peak of 0-1.8 V.
The slow clock's frequency accuracy must be 32.768 kHz ±250 ppm for Bluetooth usage (according to the Bluetooth specification).
The Slow Clock 32.768 kHz is mandatory to start the internal controller, otherwise the module does not start up.
6
BLUETOOTH FEATURES
•
Support of Bluetooth2.1+EDR (Lisbon Release) up to HCI level.
•
Very fast AFH algorithm for both ACL and eSCO.
•
Supports typically 4 dBm Class 2 TX power w/o external PA, improving Bluetooth link robustness. Adjusting the host settings, the TX power can be increased to 10 dBm. However it is important, that the national regulations and Bluetooth specification are met.
•
Digital Radio Processor (DRP) single-ended 50 ohm.
•
Internal temperature detection and compensation ensures minimal variation in the RF performance over temperature.
•
Flexible PCM and I2S digital audio/voice interfaces: Full flexibility of data-format (Linear, a-Law, μ-Law), data-width, data order, sampling and slot positioning, master/slave modes, high clock rates up to 15 MHz for slave mode (or 4.096 MHz for Master Mode). Lost packet concealment for improved audio.
•
Proprietary low-power scan method for page and inquiry scans, achieves page and inquiry scans at 1/3rd normal power.
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7
BLOCK DIAGRAM
Note: The Slow Clock 32.768 kHz is mandatory, otherwise the module does not start up, refer to Chapter 5.4 for additional information.
Note: The IO are 1.8V driven and might need external level shifter and LDO. The MLDO_OUT PIN can not be used as reference due to RF internal connection.
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8
TEST CONDITIONS
Measurements shall be made under room temperature and humidity unless otherwise specified.
9
GENERAL DEVICE REQUIREMENTS AND OPERATION
Temperature 25 ± 10°C Humidity 40 to 85%RH SW-Patch V2.30 Supply Voltage 3.3V
All specifications are over temperature and process, unless indicated otherwise.
9.1
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
Note
All parameters are measured as follows unless stated otherwise:
VDD_IN 10 = 3.3 V, VDD_IO = 1.8 V.
No
See 11
Value
Unit
Ratings Over Operating Free-Air Temperature Range
1
VDD_IN
Supply voltage range
–0.5 to 5.5
V 12
2
VDDIO_1.8V
–0.5 to 2.145
V
3
Input voltage to RF (Pin 13)
–0.5 to 2.1
V
4
Operating ambient temperature range
–20 to 70
°C
5
Storage temperature range
–40 to 125
°C
6
Bluetooth RF inputs (Pin 13)
10
dBm
7
ESD: Human Body Model (HBM). JEDEC 22-A114
500
V
10 VDD_IN is supplied to MLDO_IN (Pin 15) and CL1.5_LDO_IN (Pin 11), other options are described in Chapter 5.3.
11 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
12 Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Reference schematics. When DC2DC supply is used, maximum voltage into MLDO_OUT and LDO_IN = 2.145 V.
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9.2
RECOMMENDED OPERATING CONDITIONS
No
Rating
Condition
Symbol
Min
Max
Unit
1
Power supply voltage 13
VDD_IN
1.7
4.8
V
2
IO power supply voltage
VDD_IO
1.62
1.92
V
3
High-level input voltage
Default
VIH
0.65 x VDD_IO
VDD_IO
V
4
Low-level input voltage
Default
VIL
0
0.35 x VDD_IO
V
5
IO Input rise/fall times, 10% to 90% 14
Tr/Tf
1
10
ns
0 to 0.1 MHz
60
0.1 to 0.5 MHz
50
0.5 to 2.5 MHz
30
2.5 to 3.0 MHz
15
6
Maximum ripple on VDD_IN (Sine wave) for 1.8 V (DC2DC) mode
> 3.0 MHz
5
mVp-p
7
Voltage dips on VDD_IN (VBAT) (duration = 577 μs to2.31 ms, period = 4.6 ms)
400
mV
8
Maximum ambient operating temperature 15
70
°C
9
Minimum ambient operating temperature 16
-20
C
9.3
CURRENT CONSUMPTION
No
Characteristics
Min
25°C
Typ
25°C
Max
25°C
Min
-20°C
Typ
-20°C
Max
-20°C
Min
+70°C
Typ
+70°C
Max
+70°C
Unit
1
Current consumption in shutdown mode 17
1
3
7
μA
2
Current consumption in deep sleep mode 18
40
105
700
μA
3
Total IO current consumption for active mode
1
1
1
mA
4
Current consumption during transmit DH5 full throughput
40
mA
13 Excluding 1.98 < VDD_IN < 2.2 V range – not allowed.
14 Asynchronous mode.
15 The device can be reliably operated for 7 years at Tambient of 70°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).
16 The device can be reliably operated for 7 years at Tambient of 70°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).
17 Vbat + Vio
18 Vbat + Vio + Vsd (shutdown)
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9.4
GENERAL ELECTRICAL CHARACTERISTICS
No
Rating
Condition
Min
Max
Value
at 2/4/8 mA
0.8 x VDD_IO
VDD_IO
V
1
High-level output voltage, VOH
at 0.1 mA
VDD_IO – 0.2
VDD_IO
V
at 2/4/8 mA
0
0.2 x VDD_IO
V
2
Low-level output voltage, VOL
at 0.1 mA
0
0.2
V
Resistance
1
MΩ
3
IO input impedance
Capacitance
5
pF
4
Output rise/fall times,10% to 90% (Digital pins)
CL = 20 pF
10
Ns
PU
typ = 6.5
3.5
9.7
TX_DBG, us
PCM b
PD
typ = 27
9.5
55
μA
PU
typ = 100
100
300
5 IO pull currents
All others
PD
typ = 100
100
360
μA
9.5
NSHUTD REQUIREMENTS
No
Parameter
Symbol
Min
Max
Unit
1
Operation mode level 19 V
IH
1.42
1.98
V
2
Shutdown mode level
VIL
0
0.4
V
3
Minimum time for nSHUT_DOWN low to reset the device
5
ms
4
Rise/fall times
Tr/Tf
20
μs
9.6
EXTERNAL DIGITAL SLOW CLOCK REQUIREMENTS (–20°C TO +70°C)
No
Characteristics
Condition
Symbol
Min
Typ
Max
Unit
1
Input slow clock frequency
32768
Hz
2
Input slow clock accuracy (Initial + temp + aging)
Bluetooth
±250
Ppm
3
Input transition time Tr/Tf – 10% to 90%
Tr/Tf
100
Ns
4
Frequency input duty cycle
15%
50%
85%
5
Phase noise
at 1 kHz
-125
dBc/Hz
6
Jitter
Integrated over 300 to 15000 Hz
1
Hz
VIH
0.65 x
VDD_IO
VDD_IO
7
Slow clock input voltage limits
Square wave, DC coupled
VIL
0
0.35 x
VDD_IO
V peak
8
Input impedance
1
MΩ
9
Input capacitance
5
pF
19 Internal pull down retains shut down mode when no external signal is applied to this pin.
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10
HOST CONTROLLER INTERFACE
The CC256X incorporates one UART module dedicated to the host controller interface (HCI) transport layer. The HCI interface transports commands, events, ACL, and synchronous data between the Bluetooth device and its host using HCI data packets.
The UART module supports H4 (4-wires) protocol with maximum baud rate of 4 Mbps for all fast clock frequencies.
After power up the baud rate is set for 115.2 kbps, irrespective of fast clock frequency. The baud rate can thereafter be changed with a vendor specific command. The CC256X responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change takes place. HCI hardware includes the following features:
• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
• Transmitter underflow detection
• CTS/RTS hardware flow control
The interface includes four signals: TXD, RXD, CTS, and RTS. Flow control between the host and the CC256X is byte-wise by hardware.
Flow control is obtained by the following:
When the UART RX buffer of the CC256X passes the “flow control” threshold, it will set the UART_RTS signal high to stop transmission from the host.
When the UART_CTS signal is set high, the CC256X will stop its transmission on the interface. In case HCI_CTS is set high in the middle of transmitting a byte, the CC256X will finish transmitting the byte and stop the transmission.
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11
AUDIO/VOICE CODEC INTERFACE
The codec interface is a fully-dedicated programmable serial port that provides the logic to interface to several kinds of PCM or I2S codec’s. PAN13XX supports all voice coding schemes required by Bluetooth specification – Log PCM (A-Law or μ-Law) and Linear (CVSD). In addition, module also supports transparent scheme:
• Two voice channels
• Master / slave modes
• μ-Law, A-Law, Linear, Transparent coding schemes
• Long and short frames
• Different data sizes, order, and positions.
• High rate PCM interface for EDR
• Enlarged interface options to support a wider variety of codecs
• PCM bus sharing
11.1
PCM HARDWARE INTERFACE
The PCM interface is one implementation of the codec interface. It contains the following four lines:
• Clock—configurable direction (input or output)
• Frame Sync—configurable direction (input or output)
• Data In—Input
• Data Out—Output/3-state
The Bluetooth device can be either the master of the interface where it generates the clock and the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured by a vendor specific command.
For slave mode, clock input frequencies of up to 16 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the CC256X can generate any clock frequency between 64 kHz and 6 MHz.
Please contact your sales representative if using the I2S bus over PCM. We strongly recommend adding a low pass filter (series resistor and capacitor to GND) to the bus for better noise suppression. It is not recommended to directly contact the host μController/DSP with the PCM interface.
11.2
DATA FORMAT
The data format is fully configurable:
• The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to 640 bits when using 1 channel. The Data length can be set independently for each channel.
• The data position within a frame is also configurable in with 1 clock (bit) resolution and can be set independently (relative to the edge of the Frame Sync signal) for each channel.
• The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with the MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up to 24 bits.
• It is not necessary for the data in and data out size to be the same length.
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• The Data_Out line is configured to ‘high-Z’ output between data words. Data_Out can also be set for permanent high-Z, irrespective of data out. This allows the CC256X to be a bus slave in a multi-slave PCM environment. At powerup, Data Out is configured as high-Z.
11.3
FRAME IDLE PERIOD
The codec interface has the capability for frame idle periods, where the PCM clock can “take a break” and become ‘0’ at the end of the PCM frame, after all data has been transferred.
The CC256X supports frame idle periods both as master and slave of the PCM bus.
When CC256X is the master of the interface, the frame idle period is configurable. There are two configurable parameters:
• Clk_Idle_Start – Indicates the number of PCM clock cycles from the beginning of the frame until the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock will become ‘0’.
• Clk_Idle_End – Indicates the time from the beginning of the frame till the end of the idle period. This time is given in multiples of PCM clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.
Between each two frame syncs there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame, and lasts 90 – 60 = 30 clock cycles. This means that the idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end prior to the beginning of the idle period.
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11.4
CLOCK-EDGE OPERATION
The codec interface of the CC256X can work on the rising or the falling edge of the clock. It also has the ability to sample the frame sync and the data at inversed polarity.
This is the operation of a falling-edge-clock type of codec. The codec is the master of the PCM bus. The frame sync signal is updated (by the codec) on the falling clock edge and therefore shall be sampled (by the CC256X) on the next rising clock. The data from the codec is sampled (by the CC256X) on the clock falling edge.
11.5
TWO-CHANNEL PCM BUS EXAMPLE
In below figure, a 2-channel PCM bus is shown where the two channels have different word sizes and arbitrary positions in the bus frame. (FT stands for Frame Timer)
11.6
AUDIO ENCODING
The CC256X codec interface can use one of four audio-coding patterns:
• A-Law (8-bit)
• μ-Law (8-bit)
• Linear (8- or 16-bit)
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11.7
IMPROVED ALGORITHM FOR LOST PACKETS
The CC256X features an improved algorithm for improving voice quality when received voice data packets are lost. There are two options:
• Repeat the last sample – possible only for sample sizes up to 24 bits. For sample sizes >24 bits, the last byte is repeated.
• Repeat a configurable sample of 8 to 24 bits (depends on the real sample size), in order to simulate silence (or anything else) in the PCM bus. The configured sample will be written in a specific register for each channel.
The choice between those two options is configurable separately for each channel.
11.8
BLUETOOTH/PCM CLOCK MISMATCH HANDLING
In Bluetooth RX, the CC256X receives RF voice packets and writes these to the codec I/F. If the CC256X receives data faster than the codec I/F output allows, an overflow will occur. In this case, the Bluetooth has two possible behaviour modes: ‘allow overflow’ and ‘don’t allow overflow’.
• If overflow is allowed, the Bluetooth will continue receiving data and will overwrite any data not yet sent to the codec.
• If overflow is not allowed, RF voice packets received when buffer is full will be discarded.
11.9
BLUETOOTH INTER-IC SOUND (I2S)
The CC256X can be configured as an Inter-IC Sound (I2S) serial interface to an I2S codec device. In this mode, the CC256X audio codec interface is configured as a bi-directional, full-duplex interface, with two time slots per frame: Time slot 0 is used for the left channel audio data and time slot 1 for the right channel audio data. Each time slot is configurable up to 40 serial clock cycles in length and the frame is configurable up to 80 serial clock cycles in length.
Do not connect the the microcontroller/DSP directly to the module's PCM interface, a simple RC low pass filter is recommended to improve noise suppression.
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11.10
CURRENT CONSUMPTION FOR DIFFERENT BLUETOOTH SCENARIOS
The following table gives average current consumption for different Bluetooth scenarios.
Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 4 dBm output power.
12
BLUETOOTH RF PERFORMANCE
No
Characteristics
Typ
BT Spec Max
BT Spec Min
Class1
Class1
1
Average Power Hopping DH5 [dBm] 21, 22
7.2
20
4
2
Average Power: Ch0 [dBm] 21, 22
7.5
20
4
3
Peak Power: Ch0 [dBm] 21, 22
7.7
23
4
Average Power: Ch39 [dBm] 21, 22
7.0
20
4
5
Peak Power: Ch39 [dBm] 21, 22
7.2
23
6
Average Power: Ch78 [dBm] 21, 22
6.7
20
4
7
Peak Power: Ch78 [dBm] 21, 22
7.0
23
8
Max. Frequency Tolerance: Ch0 [kHz]
-2.6
75
-75
9
Max. Frequency Tolerance: Ch39 [kHz]
-2.2
75
-75
10
Max. Frequency Tolerance: Ch78 [kHz]
-2.1
75
-75
11
Max. Drift: Ch0_DH1 [kHz]
3.6
25
-25
12
Max. Drift: Ch0_DH3 [kHz]
3.7
40
-40
13
Max. Drift: Ch0_DH5 [kHz]
4.0
40
-40
14
Max. Drift Rate: Ch0_DH1 [kHz]
-2.6
20
-20
15
Max. Drift Rate: Ch0_DH3 [kHz]
-3.2
20
-20
16
Max. Drift Rate: Ch0_DH5 [kHz]
-3.3
20
-20
17
Max. Drift: Ch39_DH1 [kHz]
4.0
25
-25
18
Max. Drift: Ch39_DH3 [kHz]
4.3
40
-40
19
Max. Drift: Ch39_DH5 [kHz]
4.3
40
-40
20
Max. Drift Rate: Ch39_DH1 [kHz]
-3.1
20
-20
21
Max. Drift Rate: Ch39_DH3 [kHz]
-3.6
20
-20
22
Max. Drift Rate: Ch39_DH5 [kHz]
-3.7
20
-20
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No Characteristics Typ
BT Spec
Max
BT Spec
Min
Class1 Class1
23
Max. Drift: Ch78_DH1 [kHz]
4.1
25
-25
24
Max. Drift: Ch78_DH3 [kHz]
4.5
40
-40
25
Max. Drift: Ch78_DH5 [kHz]
4.4
40
-40
26
Max. Drift Rate: Ch78_DH1 [kHz]
-3.4
20
-20
27
Max. Drift Rate: Ch78_DH3 [kHz]
-3.9
20
-20
28
Max. Drift Rate: Ch78_DH5 [kHz]
-4.1
20
-20
29
Delta F1 Avg: Ch0 [kHz]
159.5
175
140
30
Delta F2 Max.: Ch0 [%]
100.0
99.9
31
Delta F2 Avg/Delta F1 Avg: Ch0
0.9
0.8
32
Delta F1 Avg: Ch39 [kHz]
159.8
175
140
33
Delta F2 Max.: Ch39 [%]
100.0
99.9
34
Delta F2 Avg/Delta F1 Avg: Ch39
0.9
0.8
35
Delta F1 Avg: Ch78 [kHz]
159.1
175
140
36
Delta F2 Max.: Ch78 [%]
100.0
99.9
37
Delta F2 Avg/Delta F1 Avg: Ch78
0.9
0.8
45
Sensitivity
-93.0
-81
46
f(H)-f(L): Ch0 [kHz]
918.4
1000
47
f(H)-f(L): Ch39 [kHz]
918.3
1000
48
f(H)-f(L): Ch78 [kHz]
918.2
1000
49
ACPower -3: Ch3 [dBm]
-51.5
-40
50
ACPower -2: Ch3 [dBm]
-50.4
-40
51
ACPower -1: Ch3 [dBm]
-18.5
52
ACPower Center: Ch3 [dBm]
8.1
20
4
53
ACPower +1: Ch3 [dBm]
-19.2
54
ACPower +2: Ch3 [dBm]
-50.7
-40
55
ACPower +3: Ch3 [dBm]
-53.3
-40
56
ACPower -3: Ch39 [dBm]
-51.6
-40
57
ACPower -2: Ch39 [dBm]
-50.7
-40
58
ACPower -1: Ch39 [dBm]
-19.0
59
ACPower Center: Ch39 [dBm]
7.7
20
4
60
ACPower +1: Ch39 [dBm]
-19.7
61
ACPower +2: Ch39 [dBm]
-50.9
-40
62
ACPower +3: Ch39 [dBm]
-53.2
-40
63
ACPower -3: Ch75 [dBm]
-51.7
-40
64
ACPower -2: Ch75 [dBm]
-50.7
-40
65
ACPower -1: Ch75 [dBm]
-19.2
66
ACPower Center: Ch75 [dBm]
7.5
20
4
67
ACPower +1: Ch75 [dBm]
-20.0
68
ACPower +2: Ch75 [dBm]
-51.0
-40
69
ACPower +3: Ch75 [dBm]
-53.4
-40
70
omega i 2-DH5: Ch0 [kHz]
-4.7
75
-75
71
omega o + omega i 2-DH5: Ch0 [kHz]
-6.0
75
-75
72
omega o 2-DH5: Ch0 [kHz]
-1.5
10
-10
73
DEVM RMS 2-DH5: Ch0 [%]
0.0
0.2
74
DEVM Peak 2-DH5: Ch0 [%]
0.1
0.35
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No Characteristics Typ
BT Spec
Max
BT Spec
Min
Class1 Class1
75
DEVM 99% 2-DH5: Ch0 [%]
100.0
99
76
omega i 3-DH5: Ch0 [kHz]
-3.7
75
-75
77
omega o + omega i 3-DH5: Ch0 [kHz]
-5.8
75
-75
78
omega o 3-DH5: Ch0 [kHz]
-2.6
10
-10
79
DEVM RMS 3-DH5: Ch0 [%]
0.0
0.13
80
DEVM Peak 3-DH5: Ch0 [%]
0.1
0.25
81
DEVM 99% 3-DH5: Ch0 [%]
100.0
99
82
omega i 2-DH5: Ch39 [kHz]
-4.8
75
-75
83
omega o + omega i 2-DH5: Ch39 [kHz]
-6.1
75
-75
84
omega o 2-DH5: Ch39 [kHz]
-1.4
10
-10
85
DEVM RMS 2-DH5: Ch39 [%]
0.0
0.2
86
DEVM Peak 2-DH5: Ch39 [%]
0.1
0.35
87
DEVM 99% 2-DH5: Ch39 [%]
100.0
99
88
omega i 3-DH5: Ch39 [kHz]
-3.8
75
-75
89
omega o + omega i 3-DH5: Ch39 [kHz]
-5.9
75
-75
90
omega o 3-DH5: Ch39 [kHz]
-2.6
10
-10
91
DEVM RMS 3-DH5: Ch39 [%]
0.0
0.13
92
DEVM Peak 3-DH5: Ch39 [%]
0.1
0.25
93
DEVM 99% 3-DH5: Ch39 [%]
100.0
99
94
omega i 2-DH5: Ch78 [kHz]
-4.9
75
-75
95
omega o + omega i 2-DH5: Ch78 [kHz]
-6.2
75
-75
96
omega o 2-DH5: Ch78 [kHz]
-1.4
10
-10
97
DEVM RMS 2-DH5: Ch78 [%]
0.0
0.2
98
DEVM Peak 2-DH5: Ch78 [%]
0.1
0.35
99
DEVM 99% 2-DH5: Ch78 [%]
100.0
99
100
omega i 3-DH5: Ch78 [kHz]
-3.8
75
-75
101
omega o + omega i 3-DH5: Ch78 [kHz]
-6.0
75
-75
102
omega o 3-DH5: Ch78 [kHz]
-2.7
10
-10
103
DEVM RMS 3-DH5: Ch78 [%]
0.0
0.13
104
DEVM Peak 3-DH5: Ch78 [%]
0.1
0.25
105
DEVM 99% 3-DH5: Ch78 [%]
100.0
99
No
Characteristics
Condition
Min
Typ
Max
BT Spec
Unit
1
Operation frequency range
2402
2480
MHz
2
Channel spacing
1
MHz
3
Input impedance
50
Ω
GFSK, BER = 0.1%
-93.0
-70
Pi/4-DQPSK, BER = 0.01%
-92.5
-70
4
Sensitivity, Dirty Tx on
8DPSK, BER = 0.01%
-85.5
-70
dBm
CLASSIFICATION PRODUCT SPECIFICATION No.
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No
Characteristics
Condition
Typ
Max
Unit
30 kHz to 1 GHz 20, 21, 22
-30
1
Tx and Rx out-of-band emissions
Output signal = 7dBm
1 to 12.75 GHz 20, 21, 22
-30
dBm
2
2nd harmonic
at 7dBm output power 20, 21, 22
-30
dBm
3
3rd harmonic
at 7dBm output power 20, 21, 22
-30
dBm
The values are measured conducted. Better suppression of the spurious emissions with an antenna can be expected as, antenna frequently have band pass filter characteristics.
13
SOLDERING TEMPERATURE-TIME PROFILE (FOR REFLOW SOLDERING)
13.1
FOR LEAD SOLDER
Recommended temp. profile for reflow soldering Temp.[°C] Time [s] 235°C max. 220 ±5°C 200°C150 ±10°C 90 ±30s 10 ±1s 30 +20/-10s
20 Includes effects of frequency hopping
21 Average according FCC, IC and ETSI requirements. Above +7dBm output power (refer also to 22) the customer has to verify the final product against national regulations.
22 +7dBm related to power register value 18, according to TI service pack 2.30
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13.2
FOR LEADFREE SOLDER
Our used temp. profile for reflow soldering Temp.[°C] Time [s] 230°C -250°C max. 220°C150°C – 190°C 90 ±30s 30 +20/-10s
Reflow permissible cycle: 2 Opposite side reflow is prohibited due to module weight.
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14
MODULE DIMENSION
14.1
MODULE DIMENSIONS PAN131X WITHOUT ANTENNA
No.
Item
Dimension
Tolerance
Remark
1
Width
6.50
± 0.20
2
Lenght
9.00
± 0.20
3
Height
1.80
± 0.20
With case
PAN131X Module Drawing
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14.2
MODULE DIMENSIONS PAN132X WITH ANTENNA
No.
Item
Dimension
Tolerance
Remark
1
Width
9.50
± 0.20
2
Lenght
9.00
± 0.20
3
Height
1.80
± 0.20
With case
PAN132X Module Drawing
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15
FOOTPRINT OF THE MODULE
15.1
FOOTPRINT PAN131X WITHOUT ANTENNA
All dimensions are in millimeters. The outer dimensions have a tolerance of ± 0.2mm.
The layout is symetric to center. The inner pins (2,4,6,9,11,14,16,18,21,23) are shifted to the center by 1mm.
0.901.706,500.901.809,00171513141211987653212324211819202210416Pad =
24 x
0.60mm x
0.60mmTop View1.802.702.953.95
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15.2
FOOTPRINT PAN132X WITH ANTENNA
All dimensions are in millimeters. The outer dimensions have a tolerance of ± 0.2mm.
The layout is symetric to center. The inner pins (2,4,6,9,11,14,16,18,21,23) are shifted to the center by 1mm. 2.700.901.709.50171513141211987653212324211819202210416Pad =
28 x
0.60mm x 0.60mm1.80ACBD1.800.551.001.80
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16
LABELING DRAWING
The above pictures show the laser marking on the top case, this is only an example from PAN1315.
17
MECHANICAL REQUIREMENTS
No.
Item
Limit
Condition
1
Solderability
More than 75% of the soldering area shall be coated by solder
Reflow soldering with recommendable temperature profile
2
Resistance to soldering heat
It shall be satisfied electrical requirements and not be mechanical damage
See Chapter 13.2
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18
RECOMMENDED FOOT PATTERN
18.1
RECOMMENDED FOOT PATTERN PAN131X WITHOUT ANTENNA
Dimensions in mm.
171513141211987653212324211819202210416Pad = 24 x 0.60mm x 0.60mmTop View9,00 6,008,50
The land pattern dimensions above are meant to serve only as a guide. This information is provided without any legal liability.
For the solder paste screen, use as a first guideline the same foot print as shown in the figure above. Solder paste screen cutouts (with slightly different dimensions) might be optimum depending on your soldering process. For example, the solder paste screen thickness chosen might have an effect. The solder screen thickness depends on your production standard 120μm to 150μm is recommended.
IMPORTANT: Although the bottom side of PAN131X is fully coated, no copper such as through hole vias, planes or tracks on the board component layer should be located below the PAN131X to avoid creating a short. In cases where a track or through hole via has to be located under the module, it must be kept away from PAN131X bottom pads. The PAN131X multilayer pcb contains an inner RF shielding plane, therefore no pcb shielding plane below the module is needed.
When using an onboard ceramic antenna, place the antenna on the edge of your carrier board (if allowable).
If you have any questions on these points, contact your local Panasonic representative.
Schematics and layouts may be sent to wireless@eu.panasonic.com for final review.
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18.2
RECOMMENDED FOOT PATTERN PAN132X WITH ANTENNA
Dimensions in mm.
The land pattern dimensions above are meant to serve only as a guide.
For the solder paste screen, use as a first guideline the same foot print as shown in the Figure above. Solder paste screen cutouts (with slightly different dimensions) might be optimum depending on your soldering process. For example, the solder paste screen thickness chosen might have an effect. The solder screen thickness depends on your production standard 120μm to 150μm is recommended.
IMPORTANT: In cases where a track or through hole via has to be located under the module, it must be kept away from PAN132X bottom pads. The PAN132X multilayer pcb contains an inner RF shielding plane, therefore no pcb shielding plane below the module is needed.
If you have any questions on these points, contact your local Panasonic representative.
Schematics and layouts may be sent to wireless@eu.panasonic.com for final review.
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19
LAYOUT RECOMMENDATIONS WITH ANTENNA (PAN132X)
20
BLUETOOTH LE (LOW ENERGY) PAN1316/26
20.1
NETWORK TOPOLOGY
Bluetooth Low Energy is designed to reduce power consumption. It can be put into a sleep mode and is only activated for event activities such as sending files to a gateway, PC or mobile phone. Furthermore the maximum power consumption is set to less than 15 mA and the average power consumption is about 1 uA. The benefit of low energy consumption are short messages and establishing very fast connections (few ms). Using these techniques, energy consumption is reduced to a tenth of a Classic Bluetooth unit. Thus, a small coin cell – such as a CR2032 – is capable of powering a device for up to 10 years of operation.
T
o be backwards compatible with Classic Bluetooth and to be able to offer an affordable solution for very inexpensive devices, Panasonic Low Energy Bluetooth modules are offered in two versions:
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Dual-mode: Bluetooth Low Energy technology combined with Classic Bluetooth functionality on a single module. Dual mode devices act as gateways between these two technologies.
Single Mode: Bluetooth Low Energy technology to optimize power consumption, which is particularly useful for products powered by small batteries. These modules have embedded controllers allowing the module to operate autonomously in low cost applications that lack intelligence.
This data sheet describes dual-mode Bluetooth Low Energy technology combined with Classic Bluetooth functionality on a single module. Additional information on Panasonic’s single mode products can be found by visiting www.panasonic.com/rfmodules or write an e-mail to wireless@eu.panasonic.com.
20.2
MODULE FEATURES
Fully compliant with Bluetooth 4.0:
•
Optimized for proximity and sports use
•
Supports up to 10 simultaneous connections
•
Multiple sniff instances are tightly coupled to minimize power consumption
•
Independent buffering allows a large number of multiple connections without affecting BR/EDR performance
•
Includes built-in coexistence and prioritization handling for BR/EDR and LE
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20.3
CURRENT CONSUMPTION FOR DIFFERENT LE SCENARIOS
Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10 dBm output power
Mode
Description
Average Current
Unit
Advertising, non-connectable
Advertising in all 3 channels
1.28msec advertising interval
15Bytes advertise Data
104
μA
Advertising, discoverable
Advertising in all 3 channels
1.28msec advertising interval
15Bytes advertise Data
121
μA
Scanning
Listening to a single frequency per window
1.28msec scan interval
11.25msec scan window
302
μA
Connected
(master role)
500msec connection interval
0msec Slave connection latency
Empty Tx/Rx LL packets
169
μA
21
ANT PAN1317/27
ANT+ (sometimes ANT + or ANT Plus) is an interoperability function that can be added to the base ANT protocol (a proprietary wireless sensor network technology).[
21.1
NETWORK TOPOLOGY
ANT™ is a wireless sensor network protocol operating in the 2.4 GHz spectrum. Designed for ultra-low power, ease of use, efficiency and scalability, ANT supports peer-to-peer, star, tree and fixed mesh topologies. It provides reliable data communications, flexible and adaptive network operation and cross-talk immunity. The ANT protocol stack is compact, requiring minimal microcontroller resources to reduce system costs, lighten the computational burden and improve efficiency. Low-level security is implemented to allow user-defined network security.
PAN1317/1327 provides the first wireless, single-chip solution with dual-mode ANT and Bluetooth connectivity with inclusion of TI’s CC2567 device. This solution wirelessly connects 13 million ANT-based devices to the more than 3 billion Bluetooth endpoint devices used by people every day, creating new market opportunities for companies building ANT products and Bluetooth products alike. CC2567 requires 80% less board area than a design with two single-mode solutions (one ANT+, one Bluetooth) and increases the wireless transmission range up to two times the distance of a single-mode ANT+ solution.
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21.2
MODULE FEATURES
Fully compliant with ANT protocol:
• ANT solution optimized for fitness, health and consumers use cases
• Supports up to eight simultaneous connections, various network topologies and high-resolution proximity pairing
• Includes built-in coexistence and prioritization handling for BR/EDR and ANT
Features
Benefits
Dual-mode ANT+ and Bluetooth (Bluetooth v2.1 + EDR) on a single chip
- Requires 80% less board area than any dual module or device design
- Reduces costs associated with incorporating two wireless technologies
Fully validated optimized single antenna solution
- Enables simultaneous operation of ANT+ and Bluetooth without the need for two devices or modules
- Includes built-in coexistence
Best-in-class Bluetooth and ANT RF performance:
- +10 dBm Tx power with transmit power control
- -93 dBm sensitivity
- Delivers twice the distance between the aggregator and ANT sensor device than competitive single-mode ANT solutions
- Enables a robust and high-throughput connection with extended range
Support for:
- ANT+ ultra low power (master and slave devices)
- Bluetooth power saving modes (park, sniff, hold)
- Bluetooth ultra low power modes (deep sleep, power down)
- Improves battery life and power efficiency of the finished product
Turnkey solution:
- Fully integrated module
- Complete development kit with software and documentation
- TI MSP430 hardware and software platform integration (optional)
- Ease of integration into system allows quick time to market
- Reduces costs and time associated with certification
21.3
ANT CURRENT CONSUMPTION
Mode
Description
Average Current
Unit
Rx message mode
250msec interval
380
μA
Rx message mode
500msec interval
205
μA
Rx message mode
1000msec interval
118
μA
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22
TRIPLE MODE (BR/EDR + BLUETOOTH LOW ENERGY + ANT) PAN1323
The PAN1323 has been engineered to give designers the flexibility to implement Bluetooth Classic (BR/EDR), Bluetooth Low Energy and ANT into an application using a single module, reducing cost and footprint area. Refer to the paragraphs above for complete descriptions on each of the three protocols. The module is fully hardware compatible with the PAN1315, 15A, 16, 17, 25, 25A, 26 and 27. A highly efficent single RF block serves all three protocols. Protocols access the RF block using time division multiplexing. The application layer determines the priority and timing of the RF block.Customers interested in this unique module are encouraged to contact StoneStreetOne for a Bluetooth SIG certified stack.
22.1
TRIPLE MODE CURRENT CONSUMPTION
The current consumption of the PAN1326 is a function of the protocol that the module is running at any point in time. Refer to the paragraphs above for details on current consumption for each of the three protocols or software vendor.
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23
DEVELOPMENT OF APPLICATIONS
Mindtree Ltd. has developed a Bluetooth SPP freeware for TIs MSP430 and Panasonics PAN1315(A) and PAN1325(A). For other software refer to Chapter 24 or visit the following link www.panasonic.com/rfmodules.
23.1
TOOLS TO BE NEEDED
PAN1323ETU
Tool
Source
TI - MSP-EXP430F5438 - Experimenter Board
MSP-EXP430F5438
TI - MSP-FET430UIF430 - Debugging Interface
MSP-FET430UIF430
TI PAN1323EMK
PAN1323EMK - Bluetooth Evaluation Module Kit for MSP430
Panasonic PAN1323ETU
CC2567-PAN1327ANT-BTKIT
For information on Bluetooth + ANT kit for PAN1327
CC2567 + PAN1327 wiki
In addition you need the software development environment, e.g. IAR Embedded Workbench, refer to:
http://wiki.msp430.com/index.php/MSP430_Bluetooth_Platform
Evaluation kits and modules are available through Panasonic’s network of authorized distributors. For any additional information, please visit www.panasonic.com/rfmodules.
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SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 40 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
24
LIST OF PROFILES
Profile
Software Developer
Controller
Availability
Bluetooth
SPP and others
MindTree
TI, MSP430
Now
SPP
Seeran
STM32, MSP430
Now
HDP, SPP
Stollmann
TI, MSP430
Now
A2DP, AVRCP, SPP
StoneStreetOne
TI, Stellaris
Now
SPP and others
ARS
Multiple
Now
Bluetooth LE
All
ARS, MindTree, StoneStreetOne, Stollmann
TI, MSP430 and others
Upon request
ANT Protocoll
ANT
Dynastream
MSP430 and others
Now
Triple Mode Stack
SPP
StoneStreetOne
MSP430 and others
Now
For all other profiles contact your local sales representative.
25
RELIABILITY TESTS
The measurement should be done after being exposed to room temperature and humidity for 1 hour.
No.
Item
Limit
Condition
1
Vibration test
Electrical parameter should be in specification
a) Freq.:10~50Hz,Amplitude:1.5mm
a) 20min. / cycle,1hrs. each of XYZ axis
b) Freq.:30~100Hz, 6G
b) 20min. / cycle,1hrs. each of XYZ axis
2
Shock test
the same as above
Dropped onto hard wood from height of 50cm for 3 times
3
Heat cycle test
the same as above
-40°C for 30min. and +85°C for 30min.;
each temperature 300 cycles
4
Moisture test
the same as above
+60°C, 90% RH, 300h
5
Low temp. test
the same as above
-40°C, 300h
6
High temp. test
the same as above
+85°C, 300h
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 41 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
26
CAUTIONS
Failure to follow the guidelines set forth in this document may result in degrading of the product’s functions and damage to the product.
26.1
DESIGN NOTES
(1)
Follow the conditions written in this specification, especially the control signals of this module.
(2)
The supply voltage has to be free of AC ripple voltage (for example from a battery or a low noise regulator output). For noisy supply voltages, provide a decoupling circuit (for example a ferrite in series connection and a bypass capacitor to ground of at least 47uF directly at the module).
(3)
This product should not be mechanically stressed when installed.
(4)
Keep this product away from heat. Heat is the major cause of decreasing the life of these products.
(5)
Avoid assembly and use of the target equipment in conditions where the products' temperature may exceed the maximum tolerance.
(6)
The supply voltage should not be exceedingly high or reversed. It should not carry noise and/or spikes.
(7)
Keep this product away from other high frequency circuits.
26.2
INSTALLATION NOTES
(1) Reflow soldering is possible twice based on the conditions in Chapter 15. Set up the temperature at the soldering portion of this product according to this reflow profile.
(2)
Carefully position the products so that their heat will not burn into printed circuit boards or affect the other components that are susceptible to heat.
(3)
Carefully locate these products so that their temperatures will not increase due to the effects of heat generated by neighboring components.
(4)
If a vinyl-covered wire comes into contact with the products, then the cover will melt and generate toxic gas, damaging the insulation. Never allow contact between the cover and these products to occur.
(5)
This product should not be mechanically stressed or vibrated when reflowed.
(6)
To repair a board by hand soldering, keep the conditions of this chapter.
(7)
Do not wash this product.
(8)
Refer to the recommended pattern when designing a board.
(9)
Pressing on parts of the metal cover or fastening objects to the metal will cause damage to the unit.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 42 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
26.
3 USAGE CONDITIONS NOTES
(1) T
ake measures to protect the unit against static electricity. If pulses or other transient loads (a large load applied in a short time) are applied to the products, check and evaluate their operation befor assembly on the final products.
(2)
Do not use dropped products.
(3)
Do not touch, damage or soil the pins.
(4)
Follow the recommended condition ratings about the power supply applied to this product.
(5)
Electrode peeling strength: Do not add pressure of more than 4.9N when soldered on PCB.
(6)
Pressing on parts of the metal cover or fastening objects to the metal cover will cause damage.
(7)
These products are intended for general purpose and standard use in general electronic equipment, such as home appliances, office equipment, information and communication equipment.
26.
4 STORAGE NOTES
(1) T
he module should not be stressed mechanically during storage.
(2)
Do not store these products in the following conditions or the performance characteristics of the product, such as RF performance will be adversely affected:
• St
orage in salty air or in an environment with a high concentration of corrosive gas, such as Cl2, H2S, NH3, SO2, or NOX
•
Storage in direct sunlight
•
Storage in an environment where the temperature may be outside the range of 5°C to 35°C range, or where the humidity may be outside the 45 to 85% range.
•
Storage of the products for more than one year after the date of delivery Storage period: check the adhesive strength of the embossed tape and soldering after 6 months of storage.
(
3) Keep this product away from water, poisonous gas and corrosive gas.
(4)
This product should not be stressed or shocked when transported.
(5)
Follow the specification when stacking packed crates (max. 10).
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 43 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
26.
5 SAFETY CAUTIONS
These specifications are intended to preserve the quality assurance of products and individual components.
Before use, check and evaluate the operation when mounted on your products. Abide by these specifications, without deviation when using the products. These products may short-circuit. If electrical shocks, smoke, fire, and/or accidents involving human life are anticipated when a short circuit occurs, then provide the following failsafe functions, as a minimum.
(1)
Ensure the safety of the whole system by installing a protection circuit and a protection device.
(2)
Ensure the safety of the whole system by installing a redundant circuit or another system to prevent a single fault causing an unsafe status.
26.
6 OTHER CAUTIONS
(1) T
his specification sheet is copyrighted.
(2)
Do not use the products for other purposes than those listed.
(3)
Be sure to provide an appropriate fail-safe function on your product to prevent an additional damage that may be caused by the abnormal function or the failure of the product.
(4)
This product has been manufactured without any ozone chemical controlled under the Montreal Protocol.
(5)
These products are not intended for other uses, other than under the special conditions shown below. Before using these products under such special conditions, check their performance and reliability under the said special conditions carefully to determine whether or not they can be used in such a manner.
• In
liquid, such as water, salt water, oil, alkali, or organic solvent, or in places where liquid may splash.
•
In direct sunlight, outdoors, or in a dusty environment
•
In an environment where condensation occurs.
•
In an environment with a high concentration of harmful gas (e.g. salty air, HCl, Cl2, SO2, H2S, NH3, and NOX)
(
6) If an abnormal voltage is applied due to a problem occurring in other components or circuits, replace these products with new products because they may not be able to provide normal performance even if their electronic characteristics and appearances appear satisfactory.
(7)
When you have any question or uncertainty, contact Panasonic.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 44 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
27
PACKAGING
27
.1 PACKAGING OF PAN131X WITHOUT ANTENNA
Tape Dimension
Packing in Tape
trailer (empty)1 x circumference /hub(min 160mm)component packed areastandard 1500pcsleader (empty)minimum 10 pitchTop cover tape more than 1 x circumference plus 100mm to avoid fixing of tape end on sealed modules.Direction of unreeling (for customer)PAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-BarcodePAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-Barcode
Empty spaces in component packed area shall be less than two per reel and those spaces shall not be consecutive.
Top cover tape shall not be found on reel holes and shall not stick out from reel.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 45 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
Component direction
PAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-Barcode
Reel dimension
A BD NW2MAXMINMIN±1.0MAX13 +0.525.0 +2.024.4 +3.0 -0.2 -0.0 -0.5*Latch (2PC)All dimensions in millimeters unless otherwise stated Assembly Method24mm330.01.520.2100.030.4*LatchTAPE SIZECW1W3
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 46 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
Label for Package PAN1315Customer CodeENW89818C2JF105 mm
(1T) Lotcode [YYWWDLL] Example from above: YY year printed 08 WW normal calendar week printed 01 D day printed 5 (Friday) L line identifier, if more as one printed 1 L lot identifier per day printed 1 (1P) Customer Order Code, if any, otherwise company name will be printed
(2P) Panasonic Order Code fix as ENW89818C2JF
(9D) Datecode as [YYWW]
(Q) Quantity [XXXX], variable max. 1500
(HW/SW) Hardware /Software Release
Total Package
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 47 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
27.2
PACKAGING FOR PAN132X WITH ANTENNA
Tape Dimension
Measured from centreline of sprocket holeMeasured holeCumulative tolerance of 10 sprocketMeasured from centreline of sprocketto centreline of pocket.holes is ± 0.20 .hole to centreline of pocket.(I)(II)(III)(IV)Other material available.ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED.WFP1+/-0.10+/-0.10+/-0.307.5012.0016.00K12.00+/-0.102.80+/-0.10+/-0.109.40BoKo9.90Ao+/-0.10 Tooling code: Flatbed -9 Estimated Max Length: 72m per 22B3 YYXXSECTION Y-Y SCALE 3.5 : 1SECTION X-X SCALE 3.5 : 1
Packing in Tape
All other packaging information is similar to Chapter 27.1
Pin1 Marking
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 48 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
28 O
RDERING INFORMATION
Version
Function
Controller
Part number
Antenna on board
Notes
MOQ (1)
PAN1315(2)
CC2560
ENW89818C2JF
NO
PAN1315A
Bluetooth v2.1 + EDR
CC2560A
ENW89829C2JF
NO
CC2560A offers reductions in init script size over CC2560 and is recommended for all new designs
1500
PAN1325(2)
CC2560
ENW89818A2JF
YES
PAN1325A
Bluetooth v2.1 + EDR
CC2560A
ENW89829A2JF
YES
CC2560A offers reductions in init script size over CC2560 and is recommended for all new designs.
1500
PAN1316
Bluetooth v2.1 + EDR
BLE 4.0
CC2564
ENW89823C2JF
NO
1500
PAN1326
Bluetooth v2.1 + EDR BLE 4.0
CC2564
ENW89823C2JF
YES
1500
PAN1317
Bluetooth v2.1 + EDR ANT
CC2567
ENW89827C2JF
NO
1500
PAN1327
Bluetooth v2.1 + EDR ANT
CC2567
ENW89827A2JF
YES
1500
PAN1323
Bluetooth v2.1 + EDR BLE 4.0 ANT
CC2569
ENW89842A2JF
YES
Check with your software developer for details on triple mode functionality.
1500
PAN1323ETU
Bluetooth v2.1 + EDR BLE 4.0 ANT
CC25xx
ENW89825A2JF
YES
Evaluation kit for the whole series. PAN1315-PAN1327.
1
Notes:
(1
) Abbreviation for Minimum Order Quantity (MOQ). The standard MOQ for mass production are 1500 pieces, fewer only on customer demand. Samples for evaluation can be delivered at any quantity.
(2) Not recommended for new designs, please refer to Chapter 1.1
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 49 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
29
ROHS DECLARATION
Declaration of environmental compatibility for supplied products:
Hereby we declare to our best present knowledge based on declaration of our suppliers that this product do not contain by now the following substances which are banned by Directive 2002/95/EC (RoHS) or if contain a maximum concentration of 0,1% by weight in homogeneous materials for
• Le
ad and lead compounds
• M
ercury and mercury compounds
•
Chromium (VI)
•
PBB (polybrominated biphenyl) category
•
PBDE (polybrominated biphenyl ether) category
And a maximum concentration of 0,01% by weight in homogeneous materials for
•
Cadmium and cadmium compounds
3
0 DATA SHEET STATUS
This data sheet contains the final specification (RELEASE).
Panasonic reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Supplementary data will be published at a later date.
Consult the most recently issued data sheet before initiating or completing a design.
Use this URL to search for the most recent version of this data sheet: PAN13xx Latest Data Sheet!
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 50 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
1 HISTORY FOR THIS DOCUMENT
Revision
Date
Modification / Remarks
0.90
18.12.2009
1st preliminary version
0.95
01.03.2010
Updated Chapter 14.2 and 28.
0.96
Not released
Change ESD Information on foot note 7 in chapter
Pin Description
0.97
25.03.2010
Various updates. Deleted links to TI Datasheet.
0.98
21.04.2010
Updated Links Some minor changes in Chapter 8 and 9.1 and change the base for the values in Chapter 9.
0.99
22.10.2010
Adopted changes according to CC2560 Datasheet. Included Interface Description, performance values. Not released.
1.00
04.11.2010
1st internal Release.
1.01
03.12.2010
Included reference to PAN1325 Application Note. AN-1325-2420-111.pdf
1.02
10.01.2011
Changed wording in Chapter 34.2 ”
Industry Canada Certification
”.
1.03
23.05.2011
Included DOC for PAN1315 series. Included PAN13xx ANT and BLE Addendum Rev1.x.pdf reference. Included Note for IO voltage and MLD_OUT pin.
1.04
02.07.2011
Corrected wording in Chapter 34.3
Europ
ean R&TTE Declaration of Conformity
.
1.05
28.10.2011
Including CC2560A silicon PAN1315A HW40 at Chapter 1.1, Chapter and Chapter 0. Deleted ES label in Chapter
1.06
15.11.2011
Added overview for the core specification and their addendums. Updated front page. Updated Related Documents.
3.00
11.01.2012
Merging PAN13xx documents into this specification and correct some format
3.10
16.01.2012
Minor mistakes fixed
3.20
29.05.2012
DoC replaced with revised version
3.30
11.06.2012
Added triple mode stack Module PAN1323, add PAN1323 to ordering and software information overview, Software Block Diagram added, Bluetooth Inter IC-Sound chapter information added
Layout Recommandations with Antenna added, Application Note LGA added
3.31
27.06.2012
Added design information to use low pass filter (chapter 11.1 / 11.9) for better noise surpression when using PCM interface
3.40
18.07.2012
Re-organize chapter
Re
gulatory Information
and added 2 chapters
1.
NCC St
atement
(only valid for PAN1325)
2.
Blu
etooth SIG Statement
3. Chapter 11.9, Second Paragraph was updated
4. Link in Chapter 34.1.1. was fixed
32
RELATED DOCUMENTS
For an update, search in the suitable homepage.
[1
] PAN1323ETU Design-Guide: http://www.panasonic.com/industrial/includes/pdf/PAN1323ETUDesignGuide.pdf
[2
] CC2560 Product Bulletin: http://focus.ti.com/pdfs/wtbu/cc2560_slyt377.pdf
[3] Bluetooth SW for MSP430 is supported by IAR IDE service pack 5.10.6 and later. Use full IAR version edition (not the kick-start version). You can find info on IAR at http://www.iar.com/website1/1.0.1.0/3/1/ and www.MSP430.com . Note, that there is an option for a 30-day free version of IAR evaluation edition.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 51 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
[4] PAN13xx CAD data: http://www.pedeu.panasonic.de/pdf/174ext.zip
[5] Application Note Land Grid Array: http://www.pedeu.panasonic.de/pdf/184ext.pdf
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 52 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
33
GENERAL INFORMATION
© Panasonic Industrial Devices Europe GmbH.
All rights reserved.
This document may contain errors. Panasonic reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its literature at any time. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to Panasonic’s terms and conditions of sale supplied at the time of order acknowledgment.
If we deliver ES samples to the customer, these samples have the status Engineering Samples. This means, the design of this product is not yet concluded. Engineering Samples may be partially or fully functional, and there may be differences to be published Data Sheet.
Engineering Samples are not qualified and are not to be used for reliability testing or series production.
Disclaimer:
Customer acknowledges that samples may deviate from the Data Sheet and may bear defects due to their status of development and the lack of qualification mentioned above.
Panasonic rejects any liability or product warranty for Engineering Samples. In particular, Panasonic disclaims liability for damages caused by
• th
e use of the Engineering Sample other than for Evaluation Purposes, particularly the installation or integration in an other product to be sold by Customer,
• de
viation or lapse in function of Engineering Sample,
• im
proper use of Engineering Samples.
Panasonic disclaimes any liability for consequential and incidental damages. Panasonic assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Panasonic components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. In case of any questions, contact your local sales representative.
34 REGULATORY INFORMATION
34
.1 FCC FOR US
3
4.1.1 FCC Notice
The devices PAN13xx, for details refer to Chapter 28 in this document, including the antennas, which are listed in Chapter 34.5 of this data sheet, complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may
cause undesired operation.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 53 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
4.1.2 Caution
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Panasonic Industrial Devices Europe GmbH may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
•
Reorient or relocate the receiving antenna.
• I
ncrease the separation between the equipment and receiver.
• Con
nect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consu
lt the dealer or an experienced radio/TV technician for help
34.1.3
Labeling Requirements
The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Panasonic FCC identifier for this product as well as the FCC Notice above. The FCC identifier are FCC ID: T7V1315. This FCC identifier is valid for all PAN13xx modules, for details, see the Chapter 28. Ordering Information.
In any case the end product must be labelled exterior with "Contains FCC ID: T7V1315"
3
4.1.4 Antenna Warning
For the related part number of PAN13xx refer to Chapter 28. Ordering Information.
This devices are tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. The FCC identifier for this device with the antenna listed in item 1 are the same (FCC ID: T7V1315).
3
4.1.5 Approved Antenna List
Note: We are able to qualify your antenna and will add to this list as that process is completed.
Item
Part Number
Manufacturer
Frequency Band
Type
Gain (dBi)
1
2450AT43B100
Johanson Technologies
2.4GHz
Chip-Antenna
+1.3
2
LDA212G3110K
Murata
2.4GHz
Chip-Antenna
+0.9
3
4788930245
Würth Elektronik
2.4GHz
Chip-Antenna
+0.5
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 54 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
4.1.6 RF Exposure PAN13xx
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure that the approved antenna in the previous table must be installed.
The preceding statement must be included as a CAUTION statement in manuals for products operating with the approved antennas in the previous table to alert users on FCC RF Exposure compliance.
Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of PAN13xx with mounted ceramic antenna (FCC ID: T7V1315) is far below the FCC radio frequency exposure limits. Nevertheless, the PAN13xx shall be used in such a manner that the potential for human contact during normal operation is minimized.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
34.2 INDUSTRY CANADA CERTIFICATION
PAN1315 is licensed to meet the regulatory requirements of Industry Canada (IC), license: IC: 216Q-1315
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 20 above, having a maximum gain of 1.3 dBi. Antennas not included in this list or having a gain greater than 1.3 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. due to the model size the IC identifier is displayed in the installation instruction.
34.3 EUROPEAN R&TTE DECLARATION OF CONFORMITY
Hereby, Panasonic Industrial Devices Europe GmbH, declares that the Bluetooth module PAN1315 and their versions is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labelled as follows:
PAN13xx and their versions in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 55 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 56 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
34.4 N
CC FOR TAIWAN
34.4.1
Labeling Requirements
Due to the limited size on the module, the NCC ID is not visible on the module.
When the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following:
“Contains Transmitter Module NCC ID:” or “Contains NCC ID:” CCAJ11LPxxxxTx
Any similar wording that expresses the same meaning may be used.
Panasonic is able to provide the above content from the label as a vector graphic, please ask at wireless@eu.panasonic.com.
34.4.2 NCC Statement
Due to the national rule from Taiwan we have to print the below statement in Chinese language.
34.5 BLUETOOTH SIG STATEMENT
35 L
IFE SUPPORT POLICY
This Panasonic product is not designed for use in life support appliances, devices, or systems where malfunction can reasonably be expected to result in a significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably expected to cause the failure of the
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 57 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
life support device or system, or to affect its safety or effectiveness. Panasonic customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Panasonic for any damages resulting.
LM3S8933 Microcontroller
DATA SHEET
DS-LM3S8933-2550 Copyright © 2007-2008 Luminary Micro, Inc.
PRELIMINARY
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office
or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these
for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Copyright © 2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark
of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
®
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2 March 17, 2008
Preliminary
Table of Contents
About This Document .................................................................................................................... 20
Audience .............................................................................................................................................. 20
About This Manual ................................................................................................................................ 20
Related Documents ............................................................................................................................... 20
Documentation Conventions .................................................................................................................. 20
1 Architectural Overview ...................................................................................................... 22
1.1 Product Features ...................................................................................................................... 22
1.2 Target Applications .................................................................................................................... 27
1.3 High-Level Block Diagram ......................................................................................................... 28
1.4 Functional Overview .................................................................................................................. 28
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 29
1.4.2 Motor Control Peripherals .......................................................................................................... 29
1.4.3 Analog Peripherals .................................................................................................................... 30
1.4.4 Serial Communications Peripherals ............................................................................................ 30
1.4.5 System Peripherals ................................................................................................................... 32
1.4.6 Memory Peripherals .................................................................................................................. 33
1.4.7 Additional Features ................................................................................................................... 33
1.4.8 Hardware Details ...................................................................................................................... 34
2 ARM Cortex-M3 Processor Core ...................................................................................... 35
2.1 Block Diagram .......................................................................................................................... 36
2.2 Functional Description ............................................................................................................... 36
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 36
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 37
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 37
2.2.4 ROM Table ............................................................................................................................... 37
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 37
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 37
3 Memory Map ....................................................................................................................... 41
4 Interrupts ............................................................................................................................ 43
5 JTAG Interface .................................................................................................................... 46
5.1 Block Diagram .......................................................................................................................... 47
5.2 Functional Description ............................................................................................................... 47
5.2.1 JTAG Interface Pins .................................................................................................................. 48
5.2.2 JTAG TAP Controller ................................................................................................................. 49
5.2.3 Shift Registers .......................................................................................................................... 50
5.2.4 Operational Considerations ........................................................................................................ 50
5.3 Initialization and Configuration ................................................................................................... 53
5.4 Register Descriptions ................................................................................................................ 53
5.4.1 Instruction Register (IR) ............................................................................................................. 53
5.4.2 Data Registers .......................................................................................................................... 55
6 System Control ................................................................................................................... 57
6.1 Functional Description ............................................................................................................... 57
6.1.1 Device Identification .................................................................................................................. 57
6.1.2 Reset Control ............................................................................................................................ 57
March 17, 2008 3
Preliminary
LM3S8933 Microcontroller
6.1.3 Power Control ........................................................................................................................... 60
6.1.4 Clock Control ............................................................................................................................ 60
6.1.5 System Control ......................................................................................................................... 62
6.2 Initialization and Configuration ................................................................................................... 63
6.3 Register Map ............................................................................................................................ 64
6.4 Register Descriptions ................................................................................................................ 65
7 Hibernation Module .......................................................................................................... 119
7.1 Block Diagram ........................................................................................................................ 120
7.2 Functional Description ............................................................................................................. 120
7.2.1 Register Access Timing ........................................................................................................... 120
7.2.2 Clock Source .......................................................................................................................... 121
7.2.3 Battery Management ............................................................................................................... 121
7.2.4 Real-Time Clock ...................................................................................................................... 121
7.2.5 Non-Volatile Memory ............................................................................................................... 122
7.2.6 Power Control ......................................................................................................................... 122
7.2.7 Interrupts and Status ............................................................................................................... 122
7.3 Initialization and Configuration ................................................................................................. 123
7.3.1 Initialization ............................................................................................................................. 123
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 123
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 123
7.3.4 External Wake-Up from Hibernation .......................................................................................... 124
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 124
7.4 Register Map .......................................................................................................................... 124
7.5 Register Descriptions .............................................................................................................. 125
8 Internal Memory ............................................................................................................... 138
8.1 Block Diagram ........................................................................................................................ 138
8.2 Functional Description ............................................................................................................. 138
8.2.1 SRAM Memory ........................................................................................................................ 138
8.2.2 Flash Memory ......................................................................................................................... 139
8.3 Flash Memory Initialization and Configuration ........................................................................... 140
8.3.1 Flash Programming ................................................................................................................. 140
8.3.2 Nonvolatile Register Programming ........................................................................................... 141
8.4 Register Map .......................................................................................................................... 141
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 142
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 149
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 162
9.1 Functional Description ............................................................................................................. 162
9.1.1 Data Control ........................................................................................................................... 163
9.1.2 Interrupt Control ...................................................................................................................... 164
9.1.3 Mode Control .......................................................................................................................... 165
9.1.4 Commit Control ....................................................................................................................... 165
9.1.5 Pad Control ............................................................................................................................. 165
9.1.6 Identification ........................................................................................................................... 165
9.2 Initialization and Configuration ................................................................................................. 165
9.3 Register Map .......................................................................................................................... 167
9.4 Register Descriptions .............................................................................................................. 169
4 March 17, 2008
Preliminary
Table of Contents
10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 206
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Differential Sampling ............................................................................................................... 266
12.2.6 Test Modes ............................................................................................................................. 268
12.2.7 Internal Temperature Sensor .................................................................................................... 268
12.3 Initialization and Configuration ................................................................................................. 269
12.3.1 Module Initialization ................................................................................................................. 269
12.3.2 Sample Sequencer Configuration ............................................................................................. 269
12.4 Register Map .......................................................................................................................... 269
12.5 Register Descriptions .............................................................................................................. 270
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
March 17, 2008 5
Preliminary
LM3S8933 Microcontroller
13.4 Register Map .......................................................................................................................... 302
13.5 Register Descriptions .............................................................................................................. 303
14 Synchronous Serial Interface (SSI) ................................................................................ 337
14.1 Block Diagram ........................................................................................................................ 337
14.2 Functional Description ............................................................................................................. 337
14.2.1 Bit Rate Generation ................................................................................................................. 338
14.2.2 FIFO Operation ....................................................................................................................... 338
14.2.3 Interrupts ................................................................................................................................ 338
14.2.4 Frame Formats ....................................................................................................................... 339
14.3 Initialization and Configuration ................................................................................................. 346
14.4 Register Map .......................................................................................................................... 347
14.5 Register Descriptions .............................................................................................................. 348
15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374
15.1 Block Diagram ........................................................................................................................ 374
15.2 Functional Description ............................................................................................................. 374
15.2.1 I2C Bus Functional Overview .................................................................................................... 375
15.2.2 Available Speed Modes ........................................................................................................... 377
15.2.3 Interrupts ................................................................................................................................ 378
15.2.4 Loopback Operation ................................................................................................................ 378
15.2.5 Command Sequence Flow Charts ............................................................................................ 379
15.3 Initialization and Configuration ................................................................................................. 385
15.4 I2C Register Map ..................................................................................................................... 386
15.5 Register Descriptions (I2C Master) ........................................................................................... 387
15.6 Register Descriptions (I2C Slave) ............................................................................................. 400
16 Controller Area Network (CAN) Module ......................................................................... 409
16.1 Controller Area Network Overview ............................................................................................ 409
16.2 Controller Area Network Features ............................................................................................ 409
16.3 Controller Area Network Block Diagram .................................................................................... 410
16.4 Controller Area Network Functional Description ......................................................................... 410
16.4.1 Initialization ............................................................................................................................. 411
16.4.2 Operation ............................................................................................................................... 411
16.4.3 Transmitting Message Objects ................................................................................................. 412
16.4.4 Configuring a Transmit Message Object .................................................................................... 412
16.4.5 Updating a Transmit Message Object ....................................................................................... 413
16.4.6 Accepting Received Message Objects ...................................................................................... 413
16.4.7 Receiving a Data Frame .......................................................................................................... 413
16.4.8 Receiving a Remote Frame ...................................................................................................... 413
16.4.9 Receive/Transmit Priority ......................................................................................................... 414
16.4.10 Configuring a Receive Message Object .................................................................................... 414
16.4.11 Handling of Received Message Objects .................................................................................... 415
16.4.12 Handling of Interrupts .............................................................................................................. 415
16.4.13 Bit Timing Configuration Error Considerations ........................................................................... 416
16.4.14 Bit Time and Bit Rate ............................................................................................................... 416
16.4.15 Calculating the Bit Timing Parameters ...................................................................................... 418
16.5 Controller Area Network Register Map ...................................................................................... 420
16.6 Register Descriptions .............................................................................................................. 421
6 March 17, 2008
Preliminary
Table of Contents
17 Ethernet Controller .......................................................................................................... 449
17.1 Block Diagram ........................................................................................................................ 450
17.2 Functional Description ............................................................................................................. 450
17.2.1 Internal MII Operation .............................................................................................................. 450
17.2.2 PHY Configuration/Operation ................................................................................................... 451
17.2.3 MAC Configuration/Operation .................................................................................................. 452
17.2.4 Interrupts ................................................................................................................................ 455
17.3 Initialization and Configuration ................................................................................................. 455
17.4 Ethernet Register Map ............................................................................................................. 456
17.5 Ethernet MAC Register Descriptions ......................................................................................... 457
17.6 MII Management Register Descriptions ..................................................................................... 475
18 Analog Comparators ....................................................................................................... 494
18.1 Block Diagram ........................................................................................................................ 495
18.2 Functional Description ............................................................................................................. 495
18.2.1 Internal Reference Programming .............................................................................................. 497
18.3 Initialization and Configuration ................................................................................................. 498
18.4 Register Map .......................................................................................................................... 498
18.5 Register Descriptions .............................................................................................................. 499
19 Pin Diagram ...................................................................................................................... 507
20 Signal Tables .................................................................................................................... 509
20.1 100-Pin LQFP Package Pin Tables ........................................................................................... 509
20.2 108-Pin BGA Package Pin Tables ............................................................................................ 520
21 Operating Characteristics ............................................................................................... 534
22 Electrical Characteristics ................................................................................................ 535
22.1 DC Characteristics .................................................................................................................. 535
22.1.1 Maximum Ratings ................................................................................................................... 535
22.1.2 Recommended DC Operating Conditions .................................................................................. 535
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 536
22.1.4 Power Specifications ............................................................................................................... 536
22.1.5 Flash Memory Characteristics .................................................................................................. 538
22.2 AC Characteristics ................................................................................................................... 538
22.2.1 Load Conditions ...................................................................................................................... 538
22.2.2 Clocks .................................................................................................................................... 538
22.2.3 Analog-to-Digital Converter ...................................................................................................... 539
22.2.4 Analog Comparator ................................................................................................................. 540
22.2.5 I2C ......................................................................................................................................... 540
22.2.6 Ethernet Controller .................................................................................................................. 541
22.2.7 Hibernation Module ................................................................................................................. 544
22.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 544
22.2.9 JTAG and Boundary Scan ........................................................................................................ 546
22.2.10 General-Purpose I/O ............................................................................................................... 547
22.2.11 Reset ..................................................................................................................................... 548
23 Package Information ........................................................................................................ 550
A Serial Flash Loader .......................................................................................................... 554
A.1 Serial Flash Loader ................................................................................................................. 554
A.2 Interfaces ............................................................................................................................... 554
March 17, 2008 7
Preliminary
LM3S8933 Microcontroller
A.2.1 UART ..................................................................................................................................... 554
A.2.2 SSI ......................................................................................................................................... 554
A.3 Packet Handling ...................................................................................................................... 555
A.3.1 Packet Format ........................................................................................................................ 555
A.3.2 Sending Packets ..................................................................................................................... 555
A.3.3 Receiving Packets ................................................................................................................... 555
A.4 Commands ............................................................................................................................. 556
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 556
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 556
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 556
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 557
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 557
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 557
B Register Quick Reference ............................................................................................... 559
C Ordering and Contact Information ................................................................................. 578
C.1 Ordering Information ................................................................................................................ 578
C.2 Kits ......................................................................................................................................... 578
C.3 Company Information .............................................................................................................. 579
C.4 Support Information ................................................................................................................. 579
8 March 17, 2008
Preliminary
Table of Contents
List of Figures
Figure 1-1. Stellaris® 8000 Series High-Level Block Diagram ............................................................... 28
Figure 2-1. CPU Block Diagram ......................................................................................................... 36
Figure 2-2. TPIU Block Diagram ........................................................................................................ 37
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 47
Figure 5-2. Test Access Port State Machine ....................................................................................... 50
Figure 5-3. IDCODE Register Format ................................................................................................. 55
Figure 5-4. BYPASS Register Format ................................................................................................ 56
Figure 5-5. Boundary Scan Register Format ....................................................................................... 56
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 58
Figure 6-2. Main Clock Tree .............................................................................................................. 61
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 120
Figure 8-1. Flash Block Diagram ...................................................................................................... 138
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 163
Figure 9-2. GPIODATA Write Example ............................................................................................. 164
Figure 9-3. GPIODATA Read Example ............................................................................................. 164
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211
Figure 11-1. WDT Module Block Diagram .......................................................................................... 240
Figure 12-1. ADC Module Block Diagram ........................................................................................... 264
Figure 12-2. Differential Sampling Range, Vin(-) = 1.5 V ...................................................................... 267
Figure 12-3. Differential Sampling Range, Vin(-) = 0.75 V .................................................................... 267
Figure 12-4. Differential Sampling Range, Vin(-) = 2.25 V .................................................................... 268
Figure 12-5. Internal Temperature Sensor Characteristic ..................................................................... 268
Figure 13-1. UART Module Block Diagram ......................................................................................... 297
Figure 13-2. UART Character Frame ................................................................................................. 298
Figure 13-3. IrDA Data Modulation ..................................................................................................... 300
Figure 14-1. SSI Module Block Diagram ............................................................................................. 337
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 340
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346
Figure 15-1. I2C Block Diagram ......................................................................................................... 374
Figure 15-2. I2C Bus Configuration .................................................................................................... 375
Figure 15-3. START and STOP Conditions ......................................................................................... 375
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376
March 17, 2008 9
Preliminary
LM3S8933 Microcontroller
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376
Figure 15-7. Master Single SEND ...................................................................................................... 379
Figure 15-8. Master Single RECEIVE ................................................................................................. 380
Figure 15-9. Master Burst SEND ....................................................................................................... 381
Figure 15-10. Master Burst RECEIVE .................................................................................................. 382
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384
Figure 15-13. Slave Command Sequence ............................................................................................ 385
Figure 16-1. CAN Module Block Diagram ........................................................................................... 410
Figure 16-2. CAN Bit Time ................................................................................................................ 417
Figure 17-1. Ethernet Controller Block Diagram .................................................................................. 450
Figure 17-2. Ethernet Controller ......................................................................................................... 450
Figure 17-3. Ethernet Frame ............................................................................................................. 452
Figure 18-1. Analog Comparator Module Block Diagram ..................................................................... 495
Figure 18-2. Structure of Comparator Unit .......................................................................................... 496
Figure 18-3. Comparator Internal Reference Structure ........................................................................ 497
Figure 19-1. 100-Pin LQFP Package Pin Diagram .............................................................................. 507
Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ............................................................... 508
Figure 22-1. Load Conditions ............................................................................................................ 538
Figure 22-2. I2C Timing ..................................................................................................................... 541
Figure 22-3. External XTLP Oscillator Characteristics ......................................................................... 543
Figure 22-4. Hibernation Module Timing ............................................................................................. 544
Figure 22-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545
Figure 22-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545
Figure 22-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546
Figure 22-8. JTAG Test Clock Input Timing ......................................................................................... 547
Figure 22-9. JTAG Test Access Port (TAP) Timing .............................................................................. 547
Figure 22-10. JTAG TRST Timing ........................................................................................................ 547
Figure 22-11. External Reset Timing (RST) .......................................................................................... 548
Figure 22-12. Power-On Reset Timing ................................................................................................. 549
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 549
Figure 22-14. Software Reset Timing ................................................................................................... 549
Figure 22-15. Watchdog Reset Timing ................................................................................................. 549
Figure 23-1. 100-Pin LQFP Package .................................................................................................. 550
Figure 23-2. 100-Ball BGA Package .................................................................................................. 552
10 March 17, 2008
Preliminary
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 20
Table 3-1. Memory Map ................................................................................................................... 41
Table 4-1. Exception Types .............................................................................................................. 43
Table 4-2. Interrupts ........................................................................................................................ 44
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 48
Table 5-2. JTAG Instruction Register Commands ............................................................................... 53
Table 6-1. System Control Register Map ........................................................................................... 64
Table 7-1. Hibernation Module Register Map ................................................................................... 124
Table 8-1. Flash Protection Policy Combinations ............................................................................. 140
Table 8-2. Flash Resident Registers ............................................................................................... 141
Table 8-3. Flash Register Map ........................................................................................................ 141
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 166
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 166
Table 9-3. GPIO Register Map ....................................................................................................... 168
Table 10-1. Available CCP Pins ........................................................................................................ 205
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208
Table 10-3. Timers Register Map ...................................................................................................... 214
Table 11-1. Watchdog Timer Register Map ........................................................................................ 241
Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264
Table 12-2. Differential Sampling Pairs ............................................................................................. 266
Table 12-3. ADC Register Map ......................................................................................................... 269
Table 13-1. UART Register Map ....................................................................................................... 302
Table 14-1. SSI Register Map .......................................................................................................... 347
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
Table 16-1. Transmit Message Object Bit Settings ............................................................................. 412
Table 16-2. Receive Message Object Bit Settings .............................................................................. 414
Table 16-3. CAN Protocol Ranges .................................................................................................... 417
Table 16-4. CAN Register Map ......................................................................................................... 420
Table 17-1. TX & RX FIFO Organization ........................................................................................... 453
Table 17-2. Ethernet Register Map ................................................................................................... 456
Table 18-1. Comparator 0 Operating Modes ..................................................................................... 496
Table 18-2. Comparator 1 Operating Modes ..................................................................................... 496
Table 18-3. Comparator 2 Operating Modes ...................................................................................... 497
Table 18-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 497
Table 18-5. Analog Comparators Register Map ................................................................................. 499
Table 20-1. Signals by Pin Number ................................................................................................... 509
Table 20-2. Signals by Signal Name ................................................................................................. 513
Table 20-3. Signals by Function, Except for GPIO ............................................................................. 517
Table 20-4. GPIO Pins and Alternate Functions ................................................................................. 519
Table 20-5. Signals by Pin Number ................................................................................................... 520
Table 20-6. Signals by Signal Name ................................................................................................. 525
Table 20-7. Signals by Function, Except for GPIO ............................................................................. 529
Table 20-8. GPIO Pins and Alternate Functions ................................................................................. 532
Table 21-1. Temperature Characteristics ........................................................................................... 534
March 17, 2008 11
Preliminary
LM3S8933 Microcontroller
Table 21-2. Thermal Characteristics ................................................................................................. 534
Table 22-1. Maximum Ratings .......................................................................................................... 535
Table 22-2. Recommended DC Operating Conditions ........................................................................ 535
Table 22-3. LDO Regulator Characteristics ....................................................................................... 536
Table 22-4. Detailed Power Specifications ........................................................................................ 537
Table 22-5. Flash Memory Characteristics ........................................................................................ 538
Table 22-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 538
Table 22-7. Clock Characteristics ..................................................................................................... 538
Table 22-8. Crystal Characteristics ................................................................................................... 539
Table 22-9. ADC Characteristics ....................................................................................................... 539
Table 22-10. Analog Comparator Characteristics ................................................................................. 540
Table 22-11. Analog Comparator Voltage Reference Characteristics .................................................... 540
Table 22-12. I2C Characteristics ......................................................................................................... 540
Table 22-13. 100BASE-TX Transmitter Characteristics ........................................................................ 541
Table 22-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 541
Table 22-15. 100BASE-TX Receiver Characteristics ............................................................................ 541
Table 22-16. 10BASE-T Transmitter Characteristics ............................................................................ 541
Table 22-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 542
Table 22-18. 10BASE-T Receiver Characteristics ................................................................................ 542
Table 22-19. Isolation Transformers ................................................................................................... 542
Table 22-20. Ethernet Reference Crystal ............................................................................................ 543
Table 22-21. External XTLP Oscillator Characteristics ......................................................................... 543
Table 22-22. Hibernation Module Characteristics ................................................................................. 544
Table 22-23. SSI Characteristics ........................................................................................................ 544
Table 22-24. JTAG Characteristics ..................................................................................................... 546
Table 22-25. GPIO Characteristics ..................................................................................................... 548
Table 22-26. Reset Characteristics ..................................................................................................... 548
Table C-1. Part Ordering Information ............................................................................................... 578
12 March 17, 2008
Preliminary
Table of Contents
List of Registers
System Control .............................................................................................................................. 57
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 66
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 68
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 69
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 70
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 71
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 72
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 73
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 74
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 78
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 79
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 81
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 82
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 84
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 85
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 87
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 89
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 91
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 93
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 95
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 97
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 99
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 102
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 105
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 108
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 110
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 112
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 114
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 115
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 117
Hibernation Module ..................................................................................................................... 119
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 126
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 127
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 128
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 129
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 130
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 132
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 133
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 134
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 135
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 136
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 137
Internal Memory ........................................................................................................................... 138
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 143
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 144
March 17, 2008 13
Preliminary
LM3S8933 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 145
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 147
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 148
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 149
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 150
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 151
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 152
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 153
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 154
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 155
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 156
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 157
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 158
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 159
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 160
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 161
General-Purpose Input/Outputs (GPIOs) ................................................................................... 162
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202
14 March 17, 2008
Preliminary
Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203
General-Purpose Timers ............................................................................................................. 204
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239
Watchdog Timer ........................................................................................................................... 240
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262
Analog-to-Digital Converter (ADC) ............................................................................................. 263
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 271
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 272
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 273
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 274
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 275
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 276
March 17, 2008 15
Preliminary
LM3S8933 Microcontroller
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 279
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 280
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 281
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 282
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 283
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 285
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 288
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 288
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 288
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 288
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 289
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 289
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 289
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 289
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 290
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 290
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 291
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 291
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 293
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 294
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 295
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336
16 March 17, 2008
Preliminary
Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 337
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408
Controller Area Network (CAN) Module ..................................................................................... 409
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 422
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 424
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 427
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 428
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 430
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 431
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 433
March 17, 2008 17
Preliminary
LM3S8933 Microcontroller
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 434
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 434
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 435
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 435
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 438
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 438
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 439
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 439
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 440
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 440
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 441
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 441
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 442
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 442
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 444
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 444
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 444
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 444
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 444
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 444
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 444
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 444
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 445
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 445
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 446
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 446
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 447
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 447
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 448
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 448
Ethernet Controller ...................................................................................................................... 449
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 458
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 460
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 461
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 462
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 463
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 464
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 466
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 467
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 468
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 469
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 470
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 471
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 472
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 473
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 474
Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 475
Register 17: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 476
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Table of Contents
Register 18: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 478
Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 480
Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 481
Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 482
Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 484
Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 485
Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 486
Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 488
Register 26: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 490
Register 27: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 491
Register 28: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 492
Register 29: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 493
Analog Comparators ................................................................................................................... 494
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 500
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 501
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 502
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 503
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 504
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 504
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 504
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 505
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 505
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 505
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About This Document
This data sheet provides reference information for the LM3S8933 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 20.
Table 1. Documentation Conventions
Notation Meaning
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
bit A single bit in a register.
bit field Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 41.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
20 March 17, 2008
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About This Document
Notation Meaning
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
R/W1S
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
deassert a signal Change the value of the signal from the logically True state to the logically False state.
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
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1 Architectural Overview
The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris® family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris® LM3S8000 series combines Bosch Controller Area Network technology
with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer.
The LM3S8933 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S8933 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S8933 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S8933 microcontroller perfectly for
battery applications.
In addition, the LM3S8933 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S8933 microcontroller is code-compatible
to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network. See “Ordering and Contact Information” on page 578 for
ordering information for Stellaris® family devices.
1.1 Product Features
The LM3S8933 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
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– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 32 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
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• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Hardware assistance for IEEE 1588-2002 Precision Time Protocol (PTP)
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
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– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Four 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Three independent integrated analog comparators
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– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ GPIOs
– 6-36 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
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– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
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1.3 High-Level Block Diagram
Figure 1-1 on page 28 represents the full set of features in the Stellaris® 8000 series of devices;
not all features may be available on the LM3S8933 microcontroller.
Figure 1-1. Stellaris® 8000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S8933 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 578.
28 March 17, 2008
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Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 35)
All members of the Stellaris® product family, including the LM3S8933 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 35 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S8933 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 32 interrupts.
“Interrupts” on page 43 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S8933 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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LM3S8933 Microcontroller
On the LM3S8933, PWM motion control functionality can be achieved through:
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 210)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S8933 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S8933 microcontroller offers three analog comparators.
1.4.3.1 ADC (see page 263)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S8933 ADC module features 10-bit conversion resolution and supports four input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 494)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S8933 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S8933 controller supports both asynchronous and synchronous serial communications
with:
■ Two fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
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■ One CAN unit
■ Ethernet controller
1.4.4.1 UART (see page 296)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S8933 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 337)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S8933 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 374)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S8933 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
March 17, 2008 31
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LM3S8933 Microcontroller
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Controller Area Network (see page 409)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, now it is used in many embedded control
applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at
500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information. The LM3S8933 includes one CAN units.
1.4.4.5 Ethernet Controller (see page 449)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 162)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris® GPIO module is comprised of seven physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 6-36 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
509 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Four Programmable Timers (see page 204)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
32 March 17, 2008
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Architectural Overview
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 240)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S8933 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 138)
The LM3S8933 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 139)
The LM3S8933 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 Memory Map (see page 41)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S8933 controller can be found in “Memory Map” on page 41. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 46)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
March 17, 2008 33
Preliminary
LM3S8933 Microcontroller
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 57)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.4 Hibernation Module (see page 119)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 507
■ “Signal Tables” on page 509
■ “Operating Characteristics” on page 534
■ “Electrical Characteristics” on page 535
■ “Package Information” on page 550
34 March 17, 2008
Preliminary
Architectural Overview
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
March 17, 2008 35
Preliminary
LM3S8933 Microcontroller
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris® implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 36. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices.
36 March 17, 2008
Preliminary
ARM Cortex-M3 Processor Core
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 37.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S8933 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
March 17, 2008 37
Preliminary
LM3S8933 Microcontroller
■ Controls power management
■ Implements system control registers
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S8933 microcontroller supports 32 interrupts with eight priority
levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
38 March 17, 2008
Preliminary
ARM Cortex-M3 Processor Core
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:17 reserved RO 0
Count Flag
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
16 COUNTFLAG R/W 0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
15:3 reserved RO 0
Clock Source
Value Description
0 External reference clock. (Not implemented for Stellaris microcontrollers.)
1 Core clock
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
2 CLKSOURCE R/W 0
Tick Int
Value Description
Counting down to 0 does not pend the SysTick handler. Software can use
the COUNTFLAG to determine if ever counted to 0.
0
1 Counting down to 0 pends the SysTick handler.
1 TICKINT R/W 0
Enable
Value Description
0 Counter disabled.
Counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the
COUNTFLAG to 1 and optionally pends the SysTick handler, based on
TICKINT. It then loads the Reload value again, and begins counting.
1
0 ENABLE R/W 0
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
March 17, 2008 39
Preliminary
LM3S8933 Microcontroller
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
31:24 reserved RO 0
Reload
Value to load into the SysTick Current Value Register when the counter reaches 0.
23:0 RELOAD W1C -
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:24 reserved RO 0
Current Value
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
23:0 CURRENT W1C -
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
40 March 17, 2008
Preliminary
ARM Cortex-M3 Processor Core
3 Memory Map
The memory map for the LM3S8933 controller is provided in Table 3-1 on page 41.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 41, addresses not listed are reserved.
Table 3-1. Memory Mapa
For details on
registers, see
page ...
Start End Description
Memory
0x0000.0000 0x0003.FFFF On-chip flash b 142
0x0004.0000 0x00FF.FFFF Reserved -
0x0100.0000 0x1FFF.FFFF Reserved -
0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAMc 142
0x2001.0000 0x200F.FFFF Reserved -
0x2010.0000 0x21FF.FFFF Reserved -
0x2200.0000 0x221F.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 138
0x2220.0000 0x3FFF.FFFF Reserved -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 242
0x4000.1000 0x4000.3FFF Reserved -
0x4000.4000 0x4000.4FFF GPIO Port A 169
0x4000.5000 0x4000.5FFF GPIO Port B 169
0x4000.6000 0x4000.6FFF GPIO Port C 169
0x4000.7000 0x4000.7FFF GPIO Port D 169
0x4000.8000 0x4000.8FFF SSI0 348
0x4000.A000 0x4000.BFFF Reserved -
0x4000.C000 0x4000.CFFF UART0 303
0x4000.D000 0x4000.DFFF UART1 303
0x4000.F000 0x4000.FFFF Reserved -
0x4001.0000 0x4001.FFFF Reserved -
Peripherals
0x4002.0000 0x4002.07FF I2C Master 0 387
0x4002.0800 0x4002.0FFF I2C Slave 0 400
0x4002.2000 0x4002.3FFF Reserved -
0x4002.4000 0x4002.4FFF GPIO Port E 169
0x4002.5000 0x4002.5FFF GPIO Port F 169
0x4002.6000 0x4002.6FFF GPIO Port G 169
0x4002.9000 0x4002.BFFF Reserved -
0x4002.E000 0x4002.FFFF Reserved -
March 17, 2008 41
Preliminary
LM3S8933 Microcontroller
For details on
registers, see
page ...
Start End Description
0x4003.0000 0x4003.0FFF Timer0 215
0x4003.1000 0x4003.1FFF Timer1 215
0x4003.2000 0x4003.2FFF Timer2 215
0x4003.3000 0x4003.3FFF Timer3 215
0x4003.4000 0x4003.7FFF Reserved -
0x4003.8000 0x4003.8FFF ADC 270
0x4003.9000 0x4003.BFFF Reserved -
0x4003.C000 0x4003.CFFF Analog Comparators 494
0x4003.D000 0x4003.FFFF Reserved -
0x4004.0000 0x4004.0FFF CAN0 Controller 421
0x4004.3000 0x4004.7FFF Reserved -
0x4004.8000 0x4004.8FFF Ethernet Controller 457
0x4004.9000 0x4004.BFFF Reserved -
0x4004.C000 0x4004.FFFF Reserved -
0x4005.1000 0x4005.3FFF Reserved -
0x4005.4000 0x4005.7FFF Reserved -
0x4006.0000 0x400F.BFFF Reserved -
0x400F.C000 0x400F.CFFF Hibernation Module 125
0x400F.D000 0x400F.DFFF Flash control 142
0x400F.E000 0x400F.EFFF System control 65
0x4010.0000 0x41FF.FFFF Reserved -
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
0x4400.0000 0x5FFF.FFFF Reserved -
0x6000.0000 0xDFFF.FFFF Reserved -
Private Peripheral Bus
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM)
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT)
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB)
0xE000.3000 0xE000.DFFF Reserved
0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC)
0xE000.F000 0xE003.FFFF Reserved
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU)
0xE004.1000 0xFFFF.FFFF Reserved -
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
42 March 17, 2008
Preliminary
Memory Map
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 43 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 32 interrupts (listed in Table 4-2 on page 44).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Note: In Table 4-2 on page 44 interrupts not listed are reserved.
Table 4-1. Exception Types
Exception Type Position Prioritya Description
- 0 - Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
Reset 1 -3 (highest)
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
Non-Maskable 2 -2
Interrupt (NMI)
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
Hard Fault 3 -1
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
Memory Management 4 settable
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Bus Fault 5 settable
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Usage Fault 6 settable
- 7-10 - Reserved.
SVCall 11 settable System service call with SVC instruction. This is synchronous.
March 17, 2008 43
Preliminary
LM3S8933 Microcontroller
Exception Type Position Prioritya Description
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Debug Monitor 12 settable
- 13 - Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
PendSV 14 settable
SysTick 15 settable System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the NVIC
(prioritized). These are all asynchronous. Table 4-2 on page 44 lists the
interrupts on the LM3S8933 controller.
16 and settable
above
Interrupts
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt (Bit in Interrupt Registers) Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3 GPIO Port D
4 GPIO Port E
5 UART0
6 UART1
7 SSI0
8 I2C0
14 ADC Sequence 0
15 ADC Sequence 1
16 ADC Sequence 2
17 ADC Sequence 3
18 Watchdog timer
19 Timer0 A
20 Timer0 B
21 Timer1 A
22 Timer1 B
23 Timer2 A
24 Timer2 B
25 Analog Comparator 0
26 Analog Comparator 1
27 Analog Comparator 2
28 System Control
29 Flash Control
30 GPIO Port F
31 GPIO Port G
35 Timer3 A
36 Timer3 B
39 CAN0
44 March 17, 2008
Preliminary
Interrupts
Interrupt (Bit in Interrupt Registers) Description
42 Ethernet Controller
43 Hibernation Module
March 17, 2008 45
Preliminary
LM3S8933 Microcontroller
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions:
– BYPASS instruction
– IDCODE instruction
– SAMPLE/PRELOAD instruction
– EXTEST instruction
– INTEST instruction
■ ARM additional instructions:
– APACC instruction
– DPACC instruction
– ABORT instruction
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
46 March 17, 2008
Preliminary
JTAG Interface
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
TRST
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 47. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 53 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 546 for JTAG timing diagrams.
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5.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 48. Detailed information on each pin
follows.
Table 5-1. JTAG Port Pins Reset State
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
5.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 50.
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By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 50. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
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Figure 5-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 0 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 53.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Recovering a "Locked" Device
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
11. Perform the SWD-to-JTAG switch sequence.
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12. Release the RST signal.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 52. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
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2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 53. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
0000 EXTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
0001 INTEST
Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
0010 SAMPLE / PRELOAD
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
1110 IDCODE
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
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tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 56 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 56 for more
information.
5.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 56 for more information.
5.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 56 for more information.
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5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 55 for more
information.
5.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 55 for
more information.
5.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 55. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
Version Part Number Manufacturer ID 1
31 28 27 12 11 1 0
TDI TDO
5.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 56. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
March 17, 2008 55
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LM3S8933 Microcontroller
Figure 5-4. BYPASS Register Format
TDI 0 TDO
0
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 56. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
O TDO TDI O IN
E UT
O O IN
U E
T
O O IN
E UT
O O IN
U E
T
I
N ... ...
GPIO PB6 GPIO m RST GPIO m+1 GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 57
■ Local control, such as reset (see “Reset Control” on page 57), power (see “Power
Control” on page 60) and clock control (see “Clock Control” on page 60)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 62
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 57.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 58.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 58.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 59.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 59.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 46). The external reset sequence is as
follows:
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1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 22-11 on page 548.
6.1.2.4 Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 58.
Figure 6-1. External Circuitry to Extend Reset
R1
C1
R2
RST
Stellaris
D1
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 22-12 on page 549.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
6.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
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Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 22-13 on page 549.
6.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 62). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 22-14 on page 549.
6.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 22-15 on page 549.
6.1.3 Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator (MOSC): The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value
allowed depends on whether the main oscillator is used as the clock reference source to the
PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 74).
■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 119) and may
also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (SysClk), is derived from any of the four sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
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The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
Figure 6-2 on page 61 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be programmatically enabled/disabled. The ADC clock signal is
automatically divided down to 16 MHz for proper ADC operation.
Figure 6-2. Main Clock Tree
PLL
(240 MHz) ÷ 4
PLL
Main OSC (400 MHz)
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
÷ 4
Hibernation
Module
(32.768 kHz)
÷ 25
PWRDN
ADC Clock
System Clock
USB Clock
XTALa
USBPWRDNc
XTALa
PWRDN b
MOSCDIS a
IOSCDISa
OSCSRCb,d
BYPASS b,d
SYSDIVb,d
USESYSDIV a,d
PWMDW a
USEPWMDIVa
PWM Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 74) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
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6.1.4.3 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software configures the main PLL input reference clock source, specifies the output divisor
to set the system clock frequency, and enables the main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 78). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) on page 74 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.4.4 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 74 and page 79).
6.1.4.5 PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
22-6 on page 538). During the relock time, the affected PLL is not usable as a clock reference.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the source to the PLL until the main PLL is
stable (TREADY time met), after which it changes to the PLL. Software can use many methods to
ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit
in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt.
6.1.5 System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
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In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
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1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 64 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
Offset Name Type Reset Description page
0x000 DID0 RO - Device Identification 0 66
0x004 DID1 RO - Device Identification 1 82
0x008 DC0 RO 0x00FF.007F Device Capabilities 0 84
0x010 DC1 RO 0x0101.33FF Device Capabilities 1 85
0x014 DC2 RO 0x070F.1013 Device Capabilities 2 87
0x018 DC3 RO 0x0F0F.3FC0 Device Capabilities 3 89
0x01C DC4 RO 0x5100.007F Device Capabilities 4 91
0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 68
0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 69
0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 114
0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 115
0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 117
0x050 RIS RO 0x0000.0000 Raw Interrupt Status 70
0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 71
0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 72
0x05C RESC R/W - Reset Cause 73
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See
Offset Name Type Reset Description page
0x060 RCC R/W 0x0780.3AD1 Run-Mode Clock Configuration 74
0x064 PLLCFG RO - XTAL to PLL Translation 78
0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 79
0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 93
0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 99
0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 108
0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 95
0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 102
0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 110
0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 97
0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 105
0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 112
0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 81
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved VER reserved CLASS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
0x1 Second version of the DID0 register format.
30:28 VER RO 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:24 reserved RO 0x0
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x1 Stellaris® Fury-class devices.
23:16 CLASS RO 0x1
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Bit/Field Name Type Reset Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
15:8 MAJOR RO -
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
7:0 MINOR RO -
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Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BORIOR reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1 BORIOR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VADJ
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value VOUT (V)
0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55
5:0 VADJ R/W 0x0
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Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLRIS reserved BORRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
6 PLLLRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
1 BORRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLIM reserved BORIM reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
6 PLLLIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
1 BORIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 70).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLMIS reserved BORMIS reserved
Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
6 PLLLMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
1 BORMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LDO SW WDT BOR POR EXT
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
5 LDO R/W -
Software Reset
When set, indicates a software reset is the cause of the reset event.
4 SW R/W -
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
3 WDT R/W -
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
2 BOR R/W -
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
1 POR R/W -
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
0 EXT R/W -
March 17, 2008 73
Preliminary
LM3S8933 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x0780.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved ACG SYSDIV USESYSDIV reserved
Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS
Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0x0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
27 ACG R/W 0
74 March 17, 2008
