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Farnell PDF

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7491181012: Off-line Transformer WE-UNIT - Farnell - Farnell Element 14

7491181012: Off-line Transformer WE-UNIT - Farnell - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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Your Electronic Engineering Resource Legal Disclaimer: The content of the pages of this website is for your general information and use only. It is subject to change without notice. From time to time, this website may also include links to other websites. These links are provided for your convenience to provide further information. They do not signify that we endorse the website(s). We have no responsibility for the content of the linked website(s). Your use of any information or materials on this website is entirely at your own risk, for which we shall not be liable. It shall be your own responsibility to ensure that any products, services or information available through this website meet your specific requirements. 7491181012: Off-line Transformer WE-UNIT Product Description: Würth Electronics, Inc. has a broad selection of power transformers for the latest reference designs from some of the leading IC manufacturers in the industry. The overall product offering contains more than 50 transformers built for chipsets from NXP Semiconductors, Linear Technology, ON Semiconductor, Power Integrations, STMicroelectronics, and National Semiconductor. Examples of these devices are a series of offline power transformers designed for NXP's dimmable LED drivers and a full series of flyback transformers for Linear Technology's isolated flyback converters. They are Designed for Tiny Switch ICs from Power Integration and NCP101x or 105x of ON Semiconductor Key Features: Nominal input voltage: 125V DC to 375V DC Output power 3W and 9W Operating temperature: -40°C to +125°C Clearance and creepage distance 6mm min. Switching frequency: 132kHz Isolation voltage 4kVAC Applications: Designed for Tiny Switch ICs from Power Integration and NCP101x or 105x of ON Semiconductor For SMPS with universal input from 85 VAC up to 265 VAC Ordering Information: Mfr Part # Farnell# Newark# Description 7491181012 Click Here Click Here Off-line transformer WE-UNIT 1. Introduction This data sheet describes the functionality of the CLRC632 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. Remark: The CLRC632 supports all variants of the MIFARE Mini, MIFARE 1K, MIFARE 4K and MIFARE Ultralight RF identification protocols. To aid readability throughout this data sheet, the MIFARE Mini, MIFARE 1K, MIFARE 4K and MIFARE Ultralight products and protocols have the generic name MIFARE. 2. General description The CLRC632 is a highly integrated reader IC for contactless communication at 13.56 MHz. The CLRC632 reader IC provides: • outstanding modulation and demodulation for passive contactless communication • a wide range of methods and protocols • a small, fully integrated package • pin compatibility with the MFRC500, MFRC530, MFRC531 and SLRC400 All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication standards are supported provided: • additional components, such as the oscillator, power supply, coil etc. are correctly applied. • standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented The CLRC632 supports contactless communication using MIFARE higher baud rates (see Section 9.12 on page 40). The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for compatible transponder signals (see Section 9.10 on page 34). The digital module, manages the complete ISO/IEC 14443 standard framing and error detection (parity and CRC). In addition, it supports the fast MIFARE security algorithm for authenticating the MIFARE products (see Section 9.14 on page 42). All layers of the I-CODE1 and ISO/IEC 15693 protocols are supported by the CLRC632. The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for I-CODE1 and ISO/IEC 15693 compatible transponder signals. The digital module handles I-CODE1 and ISO/IEC 15693 framing and error detection (CRC). CLRC632 Standard multi-protocol reader solution Rev. 3.7 — 27 February 2014 073937 Product data sheet COMPANY PUBLICCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 2 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The internal transmitter module (Section 9.9 on page 31) can directly drive an antenna designed for a proximity operating distance up to 100 mm without any additional active circuitry. A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility is supported (see Section 9.1.4 on page 9). 3. Features and benefits 3.1 General  Highly integrated analog circuitry for demodulating and decoding card/label response  Buffered output drivers enable antenna connection using the minimum of external components  Proximity operating distance up to 100 mm  Supports both ISO/IEC 14443 A and ISO/IEC 14443 B standards  Supports MIFARE dual-interface card ICs and the MIFARE Mini, MIFARE 1K, MIFARE 4K protocols  Contactless communication at MIFARE higher baud rates (up to 424 kBd)  Supports both I-CODE1 and ISO/IEC 15693 protocols  Crypto1 and secure non-volatile internal key memory  Pin-compatible with the MFRC500, MFRC530, MFRC531 and the SLRC400  Parallel microprocessor interface with internal address latch and IRQ line  SPI compatibility  Flexible interrupt handling  Automatic detection of parallel microprocessor interface type  64-byte send and receive FIFO buffer  Hard reset with low power function  Software controlled Power-down mode  Programmable timer  Unique serial number  User programmable start-up configuration  Bit-oriented and byte oriented framing  Independent power supply pins for analog, digital and transmitter modules  Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz connection  Clock frequency filtering  3.3 V to 5 V operation for transmitter in short range and proximity applications  3.3 V or 5 V operation for the digital module 4. Applications  Electronic payment systems  Identification systems  Access control systemsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 3 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution  Subscriber services  Banking systems  Digital content systems 5. Quick reference data 6. Ordering information Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature 40 - +150 C Tstg storage temperature 40 - +150 C VDDD digital supply voltage 0.5 5 6 V VDDA analog supply voltage 0.5 5 6 V VDD(TVDD) TVDD supply voltage 0.5 5 6 V Vi  input voltage (absolute value) on any digital pin to DVSS 0.5 - VDDD + 0.5 V on pin RX to AVSS 0.5 - VDDA + 0.5 V ILI input leakage current 1.0 - 1.0 mA IDD(TVDD) TVDD supply current continuous wave - - 150 mA Table 2. Ordering information Type number Package Name Description Version CLRC63201T/0FE SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 4 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 7. Block diagram Fig 1. CLRC632 block diagram 001aaj629 FIFO CONTROL 64-BYTE FIFO MASTER KEY BUFFER CRYPTO1 UNIT CONTROL REGISTER BANK NWR NRD NCS ALE A0 A1 A2 10 11 9 21 22 23 24 13 14 15 16 17 18 19 20 AD0 to AD7/D0 to D7 STATE MACHINE COMMAND REGISTER PROGRAMMABLE TIMER INTERRUPT CONTROL CRC16/CRC8 GENERATION AND CHECK PARALLEL/SERIAL CONVERTER BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK SERIAL DATA SWITCH BIT DECODING BIT ENCODING 32 × 16-BYTE EEPROM EEPROM ACCESS CONTROL 32-BIT PSEUDO RANDOM GENERATOR AMPLITUDE RATING CLOCK GENERATION, FILTERING AND DISTRIBUTION OSCILLATOR LEVEL SHIFTERS CORRELATION AND REFERENCE BIT DECODING VOLTAGE Q-CHANNEL AMPLIFIER Q-CHANNEL DEMODULATOR I-CHANNEL ANALOG AMPLIFIER TEST MULTIPLEXER I-CHANNEL DEMODULATOR PARALLEL INTERFACE CONTROL (INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION) VOLTAGE MONITOR AND POWER ON DETECT DVDD RSTPD Q-CLOCK GENERATION TRANSMITTER CONTROL GND GND VMID AUX RX TVSS TX1 TX2 TVDD 30 27 29 8 5 7 6 V V POWER ON DETECT OSCIN AVDD AVSS OSCOUT IRQ MFIN MFOUT DVSS 25 31 1 26 28 32 2 3 4 12 RESET CONTROL POWER DOWN CONTROLCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 5 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 8. Pinning information 8.1 Pin description Fig 2. CLRC632 pin configuration CLRC632 OSCIN OSCOUT IRQ RSTPD MFIN VMID MFOUT RX TX1 AVSS TVDD AUX TX2 AVDD TVSS DVDD NCS A2/SCK NWR/R/NW/nWrite A1 NRD/NDS/nDStrb A0/nWait/MOSI DVSS ALE/AS/nAStrb/NSS AD0/D0 D7/AD7 AD1/D1 D6/AD6 AD2/D2 D5/AD5 AD3/D3 D4/AD4 001aaj630 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 Table 3. Pin description Pin Symbol Type[1] Description 1 OSCIN I oscillator/clock inputs: crystal oscillator input to the oscillator’s inverting amplifier externally generated clock input; fosc = 13.56 MHz 2 IRQ O interrupt request generates an output signaling an interrupt event 3 MFIN I ISO/IEC 14443 A MIFARE serial data interface input 4[2] MFOUT O interface outputs used as follows: MIFARE: generates serial data ISO/IEC 14443 A I-CODE: generates serial data based on I-CODE1 and ISO/IEC 15693 5 TX1 O transmitter 1 modulated carrier output; 13.56 MHz 6 TVDD P transmitter power supply for the TX1 and TX2 output stages 7 TX2 O transmitter 2 modulated carrier output; 13.56 MHz 8 TVSS G transmitter ground for the TX1 and TX2 output stages 9 NCS I not chip select input is used to select and activate the CLRC632’s microprocessor interface 10[3] NWR I not write input generates the strobe signal for writing data to the CLRC632 registers when applied to pins D0 to D7 R/NW I read not write input is used to switch between read or write cycles nWrite I not write input selects the read or write cycle to be performedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 6 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground. [2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The CLRC632 functionality includes test functions for the SLRC400 using pin MFOUT. [3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for detailed information). 11[3] NRD I not read input generates the strobe signal for reading data from the CLRC632 registers when applied to pins D0 to D7 NDS I not data strobe input generates the strobe signal for the read and write cycles nDStrb I not data strobe input generates the strobe signal for the read and write cycles 12 DVSS G digital ground 13 D0 O SPI master in, slave out output 13 to 20[3] D0 to D7 I/O 8-bit bidirectional data bus input/output on pins D0 to D7 AD0 to AD7 I/O 8-bit bidirectional address and data bus input/output on pins AD0 to AD7 21[3] ALE I address latch enable input for pins AD0 to AD5; HIGH latches the internal address AS I address strobe input for pins AD0 to AD5; HIGH latches the internal address nAStrb I not address strobe input for pins AD0 to AD5; LOW latches the internal address NSS I not slave select strobe input for SPI communication 22[3] A0 I address line 0 is the address register bit 0 input nWait O not wait output: LOW starts an access cycle HIGH ends an access cycle MOSI I SPI master out, slave in 23 A1 I address line 1 is the address register bit 1 input 24[3] A2 I address line 2 is the address register bit 2 input SCK I SPI serial clock input 25 DVDD P digital power supply 26 AVDD P analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX 27 AUX O auxiliary output is used to generate analog test signals. The output signal is selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits 28 AVSS G analog ground 29 RX I receiver input is used as the card response input. The carrier is load modulated at 13.56 MHz, drawn from the antenna circuit 30 VMID P internal reference voltage pin provides the internal reference voltage as a supply Remark: It must be connected to a 100 nF block capacitor connected between pin VMID and ground 31 RSTPD I reset and power-down input: HIGH: the internal current sinks are switched off, the oscillator is inhibited and the input pads are disconnected LOW (negative edge): start internal reset phase 32 OSCOUT O crystal oscillator output for the oscillator’s inverting amplifier Table 3. Pin description …continued Pin Symbol Type[1] DescriptionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 7 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The CLRC632 supports direct interfacing to various 8-bit microprocessors. Alternatively, the CLRC632 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows the parallel interface signals supported by the CLRC632. 9.1.2 Automatic microprocessor interface detection After a Power-On or Hard reset, the CLRC632 resets parallel microprocessor interface mode and detects the microprocessor interface type. The CLRC632 identifies the microprocessor interface using the logic levels on the control pins. This is performed using a combination of fixed pin connections and the dedicated Initialization routine (see Section 9.7.4 on page 30). Table 4. Supported microprocessor and EPP interface signals Bus control signals Bus Separated address and data bus Multiplexed address and data bus Separated read and write strobes control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5 data D0 to D7 AD0 to AD7 Common read and write strobe control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5 data D0 to D7 AD0 to AD7 Common read and write strobe with handshake (EPP) control - nWrite, nDStrb, nAStrb, nWait address - AD0, AD1, AD2, AD3, AD4, AD5 data - AD0 to AD7CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 8 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. 9.1.3.1 Separate read and write strobe Refer to Section 13.4.1 on page 102 for timing specification. Table 5. Connection scheme for detecting the parallel interface type CLRC632 pins Parallel interface type and signals Separated read/write strobe Common read/write strobe Dedicated address bus Multiplexed address bus Dedicated address bus Multiplexed address bus Multiplexed address bus with handshake ALE HIGH ALE HIGH AS nAStrb A2 A2 LOW A2 LOW HIGH A1 A1 HIGH A1 HIGH HIGH A0 A0 HIGH A0 LOW nWait NRD NRD NRD NDS NDS nDStrb NWR NWR NWR R/NW R/NW nWrite NCS NCS NCS NCS NCS LOW D7 to D0 D7 to D0 AD7 to AD0 D7 to D0 AD7 to AD0 AD7 to AD0 Fig 3. Connection to microprocessor: separate read and write strobes 001aak607 address bus (A3 to An) NCS A0 to A2 address bus (A0 to A2) D0 to D7 ALE data bus (D0 to D7) HIGH NRD Read strobe (NRD) NWR Write strobe (NWR) DEVICE ADDRESS DECODER non-multiplexed address NCS AD0 to AD7 ALE multiplexed address/data (AD0 to AD7) address latch enable (ALE) NRD Read strobe (NRD) NWR Write strobe (NWR) A2 LOW A1 HIGH A0 HIGH DEVICE ADDRESS DECODERCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 9 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.1.3.2 Common read and write strobe Refer to Section 13.4.2 on page 103 for timing specification. 9.1.3.3 Common read and write strobe: EPP with handshake Refer to Section 13.4.3 on page 104 for timing specification. Remark: In the EPP standard a chip select signal is not defined. To cover this situation, the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not used, it is mandatory that pin NCS is connected to pin DVSS. Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after the reset phase. The CLRC632 does not support Read Address Cycle. 9.1.4 Serial Peripheral Interface The CLRC632 provides compatibility with the 5-wire Serial Peripheral Interface (SPI) standard and acts as a slave during the SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line sends data from the CLRC632 to the master. Fig 4. Connection to microprocessor: common read and write strobes 001aak608 address bus (A3 to An) NCS A0 to A2 address bus (A0 to A2) D0 to D7 ALE data bus (D0 to D7) HIGH NRD Data strobe (NDS) NWR Read/Write (R/NW) DEVICE ADDRESS DECODER non-multiplexed address NCS AD0 to AD7 ALE multiplexed address/data (AD0 to AD7) Address strobe (AS) NRD Data strobe (NDS) NWR Read/Write (R/NW) A2 LOW A1 HIGH A0 LOW DEVICE ADDRESS DECODER Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake 001aak609 LOW NCS AD0 to AD7 ALE multiplexed address/data (AD0 to AD7) Address strobe (nAStrb) NRD Data strobe (nDStrb) NWR Read/Write (nWrite) A2 HIGH A1 HIGH A0 nWait DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 10 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Figure 6 shows the microprocessor connection to the CLRC632 using SPI. Remark: The SPI implementation for CLRC632 conforms to the SPI standard and ensures that the CLRC632 can only be addressed as a slave. 9.1.4.1 SPI read data The structure shown in Table 7 must be used to read data using SPI. It is possible to read up to n-data bytes. The first byte sent defines both, the mode and the address. The address byte must meet the following criteria: • the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the CLRC632 the MSB is set to logic 1 • bits [6:1] define the address • the Least Significant Bit (LSB) should be set to logic 0. As shown in Table 8, all the bits of the last byte sent are set to logic 0. Table 6. SPI compatibility CLRC632 pins SPI pins ALE NSS A2 SCK A1 LOW A0 MOSI NRD HIGH NWR HIGH NCS LOW D7 to D1 do not connect D0 MISO Fig 6. Connection to microprocessor: SPI 001aak610 LOW NCS D0 ALE A2 SCK A1 LOW MOSI NSS A0 MISO DEVICE Table 7. SPI read data Pin Byte 0 Byte 1 Byte 2 ... Byte n Byte n + 1 MOSI address 0 address 1 address 2 ... address n 00 MISO XX data 0 data 1 ... data n  1 data nCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 11 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] All reserved bits must be set to logic 0. 9.1.4.2 SPI write data The structure shown in Table 9 must be used to write data using SPI. It is possible to write up to n-data bytes. The first byte sent defines both the mode and the address. The address byte must meet the following criteria: • the MSB of the first byte sets the mode. To write data to the CLRC632, the MSB is set to logic 0 • bits [6:1] define the address • the LSB should be set to logic 0. SPI write mode writes all data to the address defined in byte 0 enabling effective write cycles to the FIFO buffer. [1] All reserved bits must be set to logic 0. Remark: The data bus pins D7 to D0 must be disconnected. Refer to Section 13.4.4 on page 106 for the timing specification. Table 8. SPI read address Address (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) byte 0 1 address address address address address address reserved byte 1 to byte n reserved address address address address address address reserved byte n + 1 0 0 0 0 0 0 0 0 Table 9. SPI write data Byte 0 Byte 1 Byte 2 ... Byte n Byte n + 1 MOSI address data 0 data 1 ... data n  1 data n MISO XX XX XX ... XX XX Table 10. SPI write address Address line (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) byte 0 0 address address address address address address reserved byte 1 to byte n+1 data data data data data data data dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 12 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2 Memory organization of the EEPROM Table 11. EEPROM memory organization diagram Block Byte address Access Memory content Refer to Position Address 0 0 00h to 0Fh R product information field Section 9.2.1 on page 13 1 1 10h to 1Fh R/W StartUp register initialization file Section 9.2.2.1 on page 14 2 2 20h to 2Fh R/W 3 3 30h to 3Fh R/W register initialization file user data or second initialization Section 9.2.2.3 “Register initialization file (read/write)” on page 16 4 4 40h to 4Fh R/W 5 5 50h to 5Fh R/W 6 6 60h to 6Fh R/W 7 7 70h to 7Fh R/W 8 8 80h to 8Fh W keys for Crypto1 Section 9.2.3 on page 18 9 9 90h to 9Fh W 10 A A0h to AFh W 11 B B0h to BFh W 12 C C0h to CFh W 13 D D0h to DFh W 14 E E0h to EFh W 15 F F0h to FFh W 16 10 100h to 10Fh W 17 11 110h to 11Fh W 18 12 120h to 12Fh W 19 13 130h to 13Fh W 20 14 140h to 14Fh W 21 15 150h to 15Fh W 22 16 160h to 16Fh W 23 17 170h to 17Fh W 24 18 180h to 18Fh W 25 19 190h to 19Fh W 26 1A 1A0h to 1AFh W 27 1B 1B0h to 1BFh W 28 1C 1C0h to 1CFh W 29 1D 1D0h to 1DFh W 30 1E 1E0h to 1EFh W 31 1F 1F0h to 1FFh WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 13 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2.1 Product information field (read only) [1] Byte 4 contains the current version number. 9.2.2 Register initialization files (read/write) Register initialization from address 10h to address 2Fh is performed automatically during the initializing phase (see Section 9.7.3 on page 30) using the StartUp register initialization file. In addition, the CLRC632 registers can be initialized using values from the register initialization file when the LoadConfig command is executed (see Section 11.5.1 on page 95). Table 12. Product information field Byte Symbol Access Value Description 15 CRC R - the content of the product information field is secured using a CRC byte which is checked during start-up 14 RsMaxP R - maximum source resistance for the p-channel driver transistor on pins TX1 and TX2 The source resistance of the p-channel driver transistors of pin TX1 and TX2 can be adjusted using the value GsCfgCW[5:0] in the CwConductance register (see Section 9.9.3 on page 32). The mean value of the maximum adjustable source resistance for pins TX1 and TX2 is stored as an integer value in  in this byte. Typical values for RsMaxP are between 60  to 140 . This value is denoted as maximum adjustable source resistance RS(ref)maxP and is measured by setting the CwConductance register’s GsCfgCW[5:0] bits to 01h. 13 to 12 Internal R - two bytes for internal trimming parameters 11 to 8 Product Serial Number R - a unique four byte serial number for the device 7 to 5 reserved R - 4 to 0 Product Type Identification R - the CLRC632 is a member of a new family of highly integrated reader ICs. Each member of the product family has a unique product type identification. The value of the product type identification is shown in Table 13. Table 13. Product type identification definition Definition Product type identification bytes Byte 0 1 2 3 4[1] Value 30h FFh FFh 0Fh XXhCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 14 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: The following points apply to initialization: • the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. • make sure that all PreSetxx registers are not changed. • make sure that all register bits that are reserved are set to logic 0. 9.2.2.1 StartUp register initialization file (read/write) The EEPROM memory block address 1 and 2 contents are used to automatically set the register subaddresses 10h to 2Fh during the initialization phase. The default values stored in the EEPROM during production are shown in Section 9.2.2.2 “Factory default StartUp register initialization file”. The byte assignment is shown in Table 14. 9.2.2.2 Factory default StartUp register initialization file During the production tests, the StartUp register initialization file is initialized using the default values shown in Table 15. During each power-up and initialization phase, these values are written to the CLRC632’s registers. Table 14. Byte assignment for register initialization at start-up EEPROM byte address Register address Remark 10h (block 1, byte 0) 10h skipped 11h 11h copied … …… 2Fh (block 2, byte 15) 2Fh copiedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 15 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: The CLRC632 default configuration supports the MIFARE and ISO/IEC 14443 A communication scheme. Memory addresses 3 to 7 may be used for user-specific initialization files such as I-CODE1, ISO/IEC 15693 or ISO/IEC 14443 B. Table 15. Shipment content of StartUp configuration file EEPROM byte address Register address Value Symbol Description 10h 10h 00h Page free for user 11h 11h 58h TxControl transmitter pins TX1 and TX2 are switched off, bridge driver configuration, modulator driven from internal digital circuitry 12h 12h 3Fh CwConductance source resistance of TX1 and TX2 is set to minimum 13h 13h 3Fh ModConductance defines the output conductance 14h 14h 19h CoderControl ISO/IEC 14443 A coding is set 15h 15h 13h ModWidth pulse width for Miller pulse coding is set to standard configuration 16h 16h 3Fh ModWidthSOF pulse width of Start Of Frame (SOF) 17h 17h 3Bh TypeFraming ISO/IEC 14443 A framing is set 18h 18h 00h Page free for user 19h 19h 73h RxControl1 ISO/IEC 14443 A is set and internal amplifier gain is maximum 1Ah 1Ah 08h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream 1Bh 1Bh ADh BitPhase BitPhase[7:0] is set to standard configuration 1Ch 1Ch FFh RxThreshold MinLevel[3:0] and CollLevel[3:0] are set to maximum 1Dh 1Dh 1Eh BPSKDemControl ISO/IEC 14443 A is set 1Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on, decoder is driven from internal analog circuitry 1Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on 20h 20h 00h Page free for user 21h 21h 06h RxWait frame guard time is set to six bit-clocks 22h 22h 03h ChannelRedundancy channel redundancy is set using ISO/IEC 14443 A 23h 23h 63h CRCPresetLSB CRC preset value is set using ISO/IEC 14443 A 24h 24h 63h CRCPresetMSB CRC preset value is set using ISO/IEC 14443 A 25h 25h 00h TimeSlotPeriod defines the time for the I-CODE1 time slots 26h 26h 00h MFOUTSelect pin MFOUT is set LOW 27h 27h 00h PreSet27 - 28h 28h 00h Page free for user 29h 29h 08h FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard configuration 2Ah 2Ah 07h TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart function is switched off 2Bh 2Bh 06h TimerControl Timer is started at the end of transmission, stopped at the beginning of reception 2Ch 2Ch 0Ah TimerReload TReloadValue[7:0]: the timer unit preset value is set to standard configuration 2Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance 2Eh 2Eh 00h PreSet2E - 2Fh 2Fh 00h PreSet2F -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 16 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address 3 to 7 can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.5.1 on page 95). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. The byte assignment is shown in Table 16. The register initialization file is large enough to hold values for two initialization sets and up to one block (16-byte) of user data. The startup configuration could be adapted to the I-CODE1 StartUp configuration and stored in register block address 3 and 4, providing additional flexibility. Remark: The register initialization file can be read/written by users and these bytes can be used to store other user data. After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A protocol. 9.2.2.4 Content of I-CODE1 and ISO/IEC 15693 StartUp register values Table 17 gives an overview of the StartUp values for I-CODE1 and ISO/IEC 15693 communication. Table 16. Byte assignment for register initialization at startup EEPROM byte address Register address Remark EEPROM starting byte address 10h skipped EEPROM + 1 starting byte address 11h copied … … EEPROM + 31 starting byte address 2Fh copiedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 17 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Table 17. Content of I-CODE1 startup configuration EEPROM byte address Register address Value Symbol Description 30h 10h 00h Page free for user 31h 11h 58h TxControl transmitter pins TX1 and TX2 switched off, bridge driver configuration, modulator driven from internal digital circuitry 32h 12h 3Fh CwConductance source resistance (RS) of TX1 and TX2 to minimum 33h 13h 05h ModGsCfgh source resistance (RS) of TX1 and TX2 at the time of modulation, to determine the modulation index 34h 14h 2Ch CoderControl selects the bit coding mode and the framing during transmission 35h 15h 3Fh ModWidth pulse width for code used (1 out of 256, NRZ or 1 out of 4) pulse coding is set to standard configuration 36h 16h 3Fh ModWidthSOF pulse width of SOF 37h 17h 00h TypeBFraming - 38h 18h 00h Page free for user 39h 19h 8Bh RxControl1 amplifier gain is maximum 3Ah 1Ah 00h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream 3Bh 1Bh 54h BitPhase BitPhase[7:0] is set to standard configuration 3Ch 1Ch 68h RxThreshold: MinLevel[3:0] and CollLevel[3:0] are set to maximum 3Dh 1Dh 00h BPSKDemControl - 3Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on, decoder is driven from internal analog circuitry 3Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on 40h 20h 00h Page free for user 41h 21h 08h RxWait frame guard time is set to eight bit-clocks 42h 22h 0Ch ChannelRedundancy channel redundancy is set using I-CODE1 43h 23h FEh CRCPresetLSB CRC preset value is set using I-CODE1 44h 24h FFh CRCPresetMSB CRC preset value is set using I-CODE1 45h 25h 00h TimeSlot Period defines the time for the I-CODE1 time slots 46h 26h 00h MFOUTSelect pin MFOUT is set LOW 47h 27h 00h PreSet27 - 48h 28h 00h Page free for user 49h 29h 3Eh FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard configuration 4Ah 2Ah 0Bh TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart function is switched off 4Bh 2Bh 02h TimerControl Timer is started at the end of transmission, stopped at the beginning of reception 4Ch 2Ch 00h TimerReload the timer unit preset value is set to standard configuration 4Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance 4Eh 2Eh 00h PreSet2E - 4Fh 2Fh 00h PreSet2F -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 18 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2.3 Crypto1 keys (write only) MIFARE security requires specific cryptographic keys to encrypt data stream communication on the contactless interface. These keys are called Crypto1 keys. 9.2.3.1 Key format Keys stored in the EEPROM are written in a specific format. Each key byte must be split into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble). Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This format is a precondition for successful execution of the LoadKeyE2 (see Section 11.7.1 on page 97) and LoadKey commands (see Section 11.7.2 on page 97). Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is shown in Figure 7. Example: The value for the key must be written to the EEPROM. • If the key was: A0h A1h A2h A3h A4h A5h then • 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written. Remark: It is possible to load data for other key formats into the EEPROM key storage location. However, it is not possible to validate card authentication with data which will cause the LoadKeyE2 command (see Section 11.7.1 on page 97) to fail. 9.2.3.2 Storage of keys in the EEPROM The CLRC632 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every byte of the dedicated memory area can be the start of a key. Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah. Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32 different keys can be stored in the EEPROM. Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh. Fig 7. Key storage format 001aak640 Master key byte 0 (LSB) Master key bits EEPROM byte address Example k7 k6 k5 k4 k7 k6 k5 k4 n 5Ah k3 k2 k1 k0 k3 k2 k1 k0 n + 1 F0h 1 k7 k6 k5 k4 k7 k6 k5 k4 n + 2 5Ah k3 k2 k1 k0 k3 k2 k1 k0 n + 3 E1h 5 (MSB) k7 k6 k5 k4 k7 k6 k5 k4 n + 10 5Ah k3 k2 k1 k0 k3 k2 k1 k0 n + 11 A5hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 19 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.3 FIFO buffer An 8  64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter. It buffers both the input and output data streams between the microprocessor and the internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64 bytes long without needing to take timing constraints into account. 9.3.1 Accessing the FIFO buffer 9.3.1.1 Access rules The FIFO buffer input and output data bus is connected to the FIFOData register. Writing to this register stores one byte in the FIFO buffer and increments the FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO buffer read pointer and increments the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLength register. When the microprocessor starts a command, the CLRC632 can still access the FIFO buffer while the command is running. Only one FIFO buffer has been implemented which is used for input and output. Therefore, the microprocessor must ensure that there are no inadvertent FIFO buffer accesses. Table 18 gives an overview of FIFO buffer access during command processing. 9.3.2 Controlling the FIFO buffer In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO buffer to be written with another 64 bytes of data. Table 18. FIFO buffer access Active command FIFO buffer Remark p Write p Read StartUp - - Idle - - Transmit yes - Receive - yes Transceive yes yes the microprocessor has to know the state of the command (transmitting or receiving) WriteE2 yes - ReadE2 yes yes the microprocessor has to prepare the arguments, afterwards only reading is allowed LoadKeyE2 yes - LoadKey yes - Authent1 yes - Authent2 - - LoadConfig yes - CalcCRC yes -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 20 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.3.3 FIFO buffer status information The microprocessor can get the following FIFO buffer status data: • the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0] • the FIFO buffer full warning: bit HiAlert • the FIFO buffer empty warning: bit LoAlert • the FIFO buffer overflow warning: bit FIFOOvfl. Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit. The CLRC632 can generate an interrupt signal when: • bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated. • bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated. The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be stored in the FIFO buffer. The trigger is generated by Equation 1: (1) The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or less are stored in the FIFO buffer. The trigger is generated by Equation 2: (2) 9.3.4 FIFO buffer registers and flags Table 18 shows the related FIFO buffer flags in alphabetic order. 9.4 Interrupt request system The CLRC632 indicates interrupt events by setting the PrimaryStatus register bit IRq (see Section 10.5.1.4 “PrimaryStatus register” on page 51) and activating pin IRQ. The signal on pin IRQ can be used to interrupt the microprocessor using its interrupt handling capabilities ensuring efficient microprocessor software. HiAlert 64 FIFOLength =   –  WaterLevel LoAlert FIFOLength WaterLevel =  Table 19. Associated FIFO buffer registers and flags Flags Register name Bit Register address FIFOLength[6:0] FIFOLength 6 to 0 04h FIFOOvfl ErrorFlag 4 0Ah FlushFIFO Control 0 09h HiAlert PrimaryStatus 1 03h HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h LoAlert PrimaryStatus 0 03h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h WaterLevel[5:0] FIFOLevel 5 to 0 29hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 21 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.4.1 Interrupt sources overview Table 20 shows the integrated interrupt flags, related source and setting condition. The interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one to the TReLoadValue[7:0] with bit TAutoRestart enabled. Bit TxIRq indicates interrupts from different sources and is set as follows: • the transmitter automatically sets the bit TxIRq interrupt when it is active and its state changes from sending data to transmitting the end of frame pattern • the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been processed indicated by bit CRCReady = logic 1 • when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit E2Ready = logic 1 The RxIRq flag bit indicates an interrupt when the end of the received data is detected. The IdleIRq flag bit is set when a command finishes and the content of the Command register changes to Idle. When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 on page 20) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to logic 1. When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 on page 20) and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to logic 1. 9.4.2 Interrupt request handling 9.4.2.1 Controlling interrupts and getting their status The CLRC632 informs the microprocessor about the interrupt request source by setting the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as source for an interrupt can be masked by the InterruptEn register interrupt enable bits. Table 20. Interrupt sources Interrupt flag Interrupt source Trigger action TimerIRq timer unit timer counts from 1 to 0 TxIRq transmitter a data stream, transmitted to the card, ends CRC coprocessor all data from the FIFO buffer has been processed EEPROM all data from the FIFO buffer has been programmed RxIRq receiver a data stream, received from the card, ends IdleIRq Command register command execution finishes HiAlertIRq FIFO buffer FIFO buffer is full LoAlertIRq FIFO buffer FIFO buffer is empty Table 21. Interrupt control registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 InterruptEn SetIEn reserved TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn InterruptRq SetIRq reserved TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRqCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 22 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is set to logic 1. Different interrupt sources can activate simultaneously because all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ. 9.4.2.2 Accessing the interrupt registers The interrupt request bits are automatically set by the CLRC632’s internal state machines. In addition, the microprocessor can also set or clear the interrupt request bits as required. A special implementation of the InterruptRq and InterruptEn registers enables changing an individual bit status without influencing any other bits. If an interrupt register is set to logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the interrupt register address must be set to logic 1 at the same time. If a content bit is not changed during the setting or clearing phase, zero must be written to the specific bit location. Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0 while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq to logic 1 and leaves all other bits unchanged. 9.4.3 Configuration of pin IRQ The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be controlled using the following IRQPinConfig register bits. • bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq. • bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When it is set to logic 0, it is an open-drain output which requires an external resistor to achieve a HIGH-level at pin IRQ. Remark: During the reset phase (see Section 9.7.2 on page 29) bit IRQInv is set to logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 23 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.4.4 Register overview interrupt request system Table 22 shows the related interrupt request system flags in alphabetic order. 9.5 Timer unit The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor can use this timer to manage timing-relevant tasks. The timer unit may be used in one of the following configurations: • Timeout counter • WatchDog counter • Stopwatch • Programmable one shot • Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific timed event occurred. The timer is triggered by events but does not influence any event (e.g. a time-out during data receiving does not automatically influence the receiving process). Several timer related flags can be set and these flags can be used to generate an interrupt. Table 22. Associated Interrupt request system registers and flags Flags Register name Bit Register address HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h IdleIEn InterruptEn 2 06h IdleIRq InterruptRq 2 07h IRq PrimaryStatus 3 03h IRQInv IRQPinConfig 1 07h IRQPushPull IRQPinConfig 0 07h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h RxIEn InterruptEn 3 06h RxIRq InterruptRq 3 07h SetIEn InterruptEn 7 06h SetIRq InterruptRq 7 07h TimerIEn InterruptEn 5 06h TimerIRq InterruptRq 5 07h TxIEn InterruptEn 4 06h TxIRq InterruptRq 4 07hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 24 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.5.1 Timer unit implementation 9.5.1.1 Timer unit block diagram Figure 8 shows the block diagram of the timer module. The timer unit is designed, so that events when combined with enabling flags start or stop the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received data with the timer unit. In addition, the first received bit is indicated by the TxBegin event. This combination starts the counter at the defined TReloadValue[7:0]. The timer stops automatically when the counter value is equal to zero or if a defined stop event happens. 9.5.1.2 Controlling the timer unit The main part of the timer unit is a down-counter. As long as the down-counter value is not zero, it decrements its value with each timer clock cycle. If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0]. Fig 8. Timer module block diagram 001aak611 TxEnd Event TAutoRestart TRunning TStartTxEnd TStartNow S RQ START COUNTER/ PARALLEL LOAD STOP COUNTER TPreScaler[4:0] TimerValue[7:0] Counter = 0 ? to interrupt logic: TimerIRq PARALLEL OUT PARALLEL IN TReloadValue[7:0] CLOCK DIVIDER COUNTER MODULE (x ≤ x − 1) TStopNow TxBegin Event TStartTxBegin TStopRxEnd RxEnd Event TStopRxBegin 13.56 MHz to parallel interface RxBegin Event QCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 25 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The timer is started immediately by loading a value from the TimerReload register into the counter module. This is activated by one of the following events: • transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1 • transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1 • bit TStartNow is set to logic 1 by the microprocessor Remark: Every start event reloads the timer from the TimerReload register. Thus, the timer unit is re-triggered. The timer can be configured to stop on one of the following events: • receipt of the first valid bit from the card (RxBegin event) with bit TStopRxBegin = logic 1 • receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd = logic 1 • the counter module has decremented down to zero and bit TAutoRestart = logic 0 • bit TStopNow is set to logic 1 by the microprocessor. Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit while it is counting will not immediately influence the counter. In both cases, this is because this register only affects the counter content after a start event. If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged. 9.5.1.3 Timer unit clock and period The timer unit clock is derived from the 13.56 MHz on-board chip clock using the programmable divider. Clock selection is made using the TimerClock register TPreScaler[4:0] bits based on Equation 3: (3) The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum periodic time (TTimerClock) of between 74 ns and 150 ms. The time period elapsed since the last start event is calculated using Equation 4: (4) This results in a minimum time period (tTimer) of between 74 ns and 40 s. 9.5.1.4 Timer unit status The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to logic 1. Conversely, configured stop events stop the timer and sets the TRunning status flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register changes on the next timer unit clock cycle. The TimerValue[7:0] bits can be read directly from the TimerValue register. fTimerClock 1 TTimerClock --------------------------- 2 TPreScaler 13.56 = = -------------------------- MHz tTimer TReLoadValue TimerValue – fTimerClock = ----------------------------------------------------------------------------- sCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 26 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.5.1.5 TimeSlotPeriod When sending I-CODE1 Quit frames, it is necessary to generate the exact chronological relationship to the start of the command frame. If at the end of command execution TimeSlotPeriod > 0, the TimeSlotPeriod starts. If the FIFO buffer contains data when the end of TimeSlotPeriod is reached, the data is sent. If the FIFO buffer is empty nothing happens. As long as the TimeSlotPeriod is > 0, the TimeSlotPeriod counter automatically starts on reaching the end. This forms the exact time relationship between the start and finish of the command frame used to generate and send I-CODE1 Quit frames. When the TimeSlotPeriod > 0, the next Frame starts with exactly the same interval TimeSlotPeriod/CoderRate delayed after each previous send frame. CoderRate defines the clock frequency of the encoder. If TimeSlotPeriod[7:0] = 0, the send function is not automatically triggered. The content of the TimeSlotPeriod register can be changed while it is running but the change is only effective after the next TimeSlotPeriod restart. Example: • CoderRate = 0  0.5 (~52.97 kHz) • The interval should be 8.458 ms for I-CODE1 standard mode  Remark: The TimeSlotPeriodMSB bit is contained in the MFOUTSelect register. Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to calculate the Quit value. Fig 9. TimeSlotPeriod Table 23. TimeSlotPeriod I-CODE1 mode TimeSlotPeriod for TSP1 TimeSlotPeriod for TSP2 standard mode BFh 1BFh fast mode 5Fh 67h TimeSlotPeriod CoderRate Interval =  = 52.97 kHz  8.458 ms – 1 447 1BFh = = 001aak612 COMMAND RESPONSE1 RESPONSE2 TSP1 TSP2 QUIT1 QUIT2CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 27 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event. If a given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt. If a stop event does not occur, such as the card not answering within the expected time, the timer unit decrements down to zero and generates a timer interrupt request. This signals to the microprocessor the expected event has not occurred within the given time (tTimer). 9.5.2.2 Stopwatch The time (tTimer) between a start and stop event is measured by the microprocessor using the timer unit. Setting the TReloadValue register triggers the timer which in turn, starts to decrement. If the defined stop event occurs, the timer stops. The time between start and stop is calculated by the microprocessor using Equation 5, when the timer does not decrement down to zero. (5) 9.5.2.3 Programmable one shot timer and periodic trigger Programmable one shot timer: The microprocessor starts the timer unit and waits for the timer interrupt. The interrupt occurs after the time specified by tTimer. Periodic trigger: If the microprocessor sets the TAutoRestart bit, it generates an interrupt request after every tTimer cycle. 9.5.3 Timer unit registers Table 24 shows the related flags of the timer unit in alphabetical order. t TReLoadvalue   – TimerValue tTimer =  Table 24. Associated timer unit registers and flags Flags Register name Bit Register address TAutoRestart TimerClock 5 2Ah TimerValue[7:0] TimerValue 7 to 0 0Ch TReloadValue[7:0] TimerReload 7 to 0 2Ch TPreScaler[4:0] TimerClock 4 to 0 2Ah TRunning SecondaryStatus 7 05h TStartNow Control 1 09h TStartTxBegin TimerControl 0 2Bh TStartTxEnd TimerControl 1 2Bh TStopNow Control 2 09h TStopRxBegin TimerControl 2 2Bh TStopRxEnd TimerControl 3 2BhCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 28 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. The status of all pins during a hard power-down is shown in Table 25. 9.6.2 Soft power-down mode Soft power-down mode is entered immediately using the Control register bit PowerDown. All internal current sinks, including the oscillator buffer, are switched off. The digital input buffers are not separated from the input pads and keep their functionality. In addition, the digital output pins do not change their state. After resetting the Control register bit PowerDown, the bit indicating Soft power-down mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The PowerDown bit is automatically cleared when the Soft power-down mode is exited. Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by VDDA and any clock cycles will not be detected by the internal logic until VDDA is stable. Table 25. Signal on pins during Hard power-down Symbol Pin Type Description OSCIN 1 I not separated from input, pulled to AVSS IRQ 2 O high-impedance MFIN 3 I separated from input MFOUT 4 O LOW TX1 5 O HIGH, if bit TX1RFEn = logic 1 LOW, if bit TX1RFEn = logic 0 TX2 7 O HIGH, only if bit TX2RFEn = logic 1 and bit TX2Inv = logic 0 otherwise LOW NCS 9 I separated from input NWR 10 I separated from input NRD 11 I separated from input D0 to D7 13 to 20 I/O separated from input ALE 21 I separated from input A0 22 I/O separated from input A1 23 I separated from input A2 24 I separated from input AUX 27 O high-impedance RX 29 I not changed VMID 30 A pulled to VDDA RSTPD 31 I not changed OSCOUT 32 O HIGHCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 29 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state. In addition, the oscillator does not need time to wake-up. After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is automatically cleared when the Standby mode is exited. 9.6.4 Automatic receiver power-down It is a power saving feature to switch off the receiver circuit when it is not needed. Setting bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use. Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up. 9.7 StartUp phase The events executed during the StartUp phase are shown in Figure 10. 9.7.1 Hard power-down phase The hard power-down phase is active during the following cases: • a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated when VDDD or VDDA is below the digital reset threshold. • a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level period on pin RSTPD must be at least 100 s (tPD  100 s). Shorter phases will not necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin RSTPD is not critical because pin RSTPD is a Schmitt trigger input. 9.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the description of each register (see Section 10.5 on page 50). Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by VDDA and any clock cycles will not be detected by the internal logic until VDDA is stable. Fig 10. The StartUp procedure 001aak613 StartUp phase states tRSTPD treset tinit Hard powerdown phase Reset phase Initialising phase readyCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 30 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.7.3 Initialization phase The initialization phase automatically follows the reset phase and takes 128 clock cycles. During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the register subaddresses 10h to 2Fh (see Section 9.2.2 on page 13). Remark: During the production test, the CLRC632 is initialized with default configuration values. This reduces the microprocessor’s configuration time to a minimum. 9.7.4 Initializing the parallel interface type A different initialization sequence is used for each microprocessor. This enables detection of the correct microprocessor interface type and synchronization of the microprocessor’s and the CLRC632’s start-up. See Section 9.1.3 on page 8 for detailed information on the different connections for each microprocessor interface type. During StartUp phase, the command value is set to 3Fh once the oscillator attains clock frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At the end of the initialization phase, the CLRC632 automatically switches to idle and the command value changes to 00h. To ensure correct detection of the microprocessor interface, the following sequence is executed: • the Command register is read until the 6-bit register value is 00h. On reading the 00h value, the internal initialization phase is complete and the CLRC632 is ready to be controlled • write 80h to the Page register to initialize the microprocessor interface • read the Command register. If it returns a value of 00h, the microprocessor interface was successfully initialized • write 00h to the Page registers to activate linear addressing mode. 9.8 Oscillator circuit The clock applied to the CLRC632 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. Fig 11. Quartz clock connection 001aak614 13.56 MHz 15 pF 15 pF OSCOUT OSCIN DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 31 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. It must meet the specifications described in Section 13.4.5 on page 106. Remark: We do not recommend using an external clock source. 9.9 Transmitter pins TX1 and TX2 The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using minimal passive components for matching and filtering (see Section 15.1 on page 107). To enable this, the output circuitry is designed with a very low-impedance source resistance. The TxControl register is used to control the TX1 and TX2 signals. 9.9.1 Configuring pins TX1 and TX2 TX1 pin configurations are described in Table 26. TX2 pin configurations are described in Table 27. Table 26. Pin TX1 configurations TxControl register configuration Envelope TX1 signal TX1RFEn FORCE100ASK 0 X X LOW (GND) 1 0 0 13.56 MHz carrier frequency modulated 1 0 1 13.56 MHz carrier frequency 1 1 0 LOW 1 1 1 13.56 MHz energy carrierCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 32 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.9.2 Antenna operating distance versus power consumption Using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin TVDD), it is possible to find the trade-off between maximum effective operating distance and power consumption. Different antenna matching circuits are described in the Application note “MIFARE Design of MFRC500 Matching Circuit and Antennas”. 9.9.3 Antenna driver output source resistance The output source conductance of pins TX1 and TX2 can be adjusted between 1  and 100  using the CwConductance register GsCfgCW[5:0] bits. The output source conductance of pins TX1 and TX2 during the modulation phase can be adjusted between 1  and 100  using the ModConductance register GsCfgMod[5:0] bits. The values are relative to the reference resistance (RS(ref)) which is measured during the production test and stored in the CLRC632 EEPROM. It can be read from the product information field (see Section 9.2.1 on page 13). The electrical specification can be found in Section 13.3.3 on page 101. Table 27. Pin TX2 configurations TxControl register configuration Envelope TX2 signal TX2RFEn FORCE100ASK TX2CW TX2Inv 0 X X X X LOW 1 0 0 0 0 13.56 MHz carrier frequency modulated 1 0 0 0 1 13.56 MHz carrier frequency 1 0 0 1 0 13.56 MHz carrier frequency modulated, 180 phase-shift relative to TX1 1 0 0 1 1 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 0 1 0 X 13.56 MHz carrier frequency 1 0 1 1 X 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 1 0 0 0 LOW 1 1 0 0 1 13.56 MHz carrier frequency 1 1 0 1 0 HIGH 1 1 0 1 1 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 1 1 0 X 13.56 MHz carrier frequency 1 1 1 1 X 13.56 MHz carrier frequency, 180 phase-shift relative to TX1CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 33 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.9.3.1 Source resistance table Table 28. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod MANT = Mantissa; EXP= Exponent. GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () 0 0 0 - 24 1 8 0.0652 16 1 0 - 25 1 9 0.0580 32 2 0 - 37 2 5 0.0541 48 3 0 - 26 1 10 0.0522 1 0 1 1.0000 27 1 11 0.0474 17 1 1 0.5217 51 3 3 0.0467 2 0 2 0.5000 38 2 6 0.0450 3 0 3 0.3333 28 1 12 0.0435 33 2 1 0.2703 29 1 13 0.0401 18 1 2 0.2609 39 2 7 0.0386 4 0 4 0.2500 30 1 14 0.0373 5 0 5 0.2000 52 3 4 0.0350 19 1 3 0.1739 31 1 15 0.0348 6 0 6 0.1667 40 2 8 0.0338 7 0 7 0.1429 41 2 9 0.0300 49 3 1 0.1402 53 3 5 0.0280 34 2 2 0.1351 42 2 10 0.0270 20 1 4 0.1304 43 2 11 0.0246 8 0 8 0.1250 54 3 6 0.0234 9 0 9 0.1111 44 2 12 0.0225 21 1 5 0.1043 45 2 13 0.0208 10 0 10 0.1000 55 3 7 0.0200 11 0 11 0.0909 46 2 14 0.0193 35 2 3 0.0901 47 2 15 0.0180 22 1 6 0.0870 56 3 8 0.0175 12 0 12 0.0833 57 3 9 0.0156 13 0 13 0.0769 58 3 10 0.0140 23 1 7 0.0745 59 3 11 0.0127 14 0 14 0.0714 60 3 12 0.0117 50 3 2 0.0701 61 3 13 0.0108 36 2 4 0.0676 62 3 14 0.0100 15 0 15 0.0667 63 3 15 0.0093CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 34 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.9.3.2 Calculating the relative source resistance The reference source resistance RS(ref) can be calculated using Equation 6. (6) The reference source resistance (RS(ref)) during the modulation phase can be calculated using ModConductance register’s GsCfgMod[5:0]. 9.9.3.3 Calculating the effective source resistance Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in Equation 7. (7) Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP byte) read from the Product Information Field (see Section 9.2.1 on page 13) are measured during the production test with CwConductance register’s GsCfgCW[5:0] = 01h. To calculate the driver resistance for a specific value set in GsCfgMod[5:0], use Equation 8. (8) 9.9.4 Pulse width The envelope carries the data signal information that is transmitted to the card. It is an encoded data signal based on the Miller code. In addition, each pause of the Miller encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is adjusted using the ModWidth register. The pulse width (tw) is calculated using Equation 9 where the frequency constant (fclk) = 13.56 MHz. (9) 9.10 Receiver circuitry The CLRC632 uses an integrated quadrature demodulation circuit enabling it to detect an ISO/IEC 14443 A or ISO/IEC 14443 B compliant subcarrier signal on pin RX. • ISO/IEC 14443 A subcarrier signal: defined as a Manchester coded ASK modulated signal • ISO/IEC 14443 B subcarrier signal: defined as an NRZ-L coded BPSK modulated ISO/IEC 14443 B subcarrier signal RS ref   1 MANTGsCfgCW 77 40 -----     EXPGsCfgCW  = -------------------------------------------------------------------------------- RS wire  TX1 500 m RSx RS ref  maxP RS wire  TX1   – RS rel   RS wire  TX1 =  + tw 2ModWidth 1 + fc = -------------------------------------CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 35 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitized and then passed to the digital circuitry. Various adjustments can be made to obtain optimum performance for all processing units. 9.10.1 Receiver circuit block diagram Figure 12 shows the block diagram of the receiver circuit. The receiving process can be broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal is performed. To achieve the optimum performance, automatic Q-clock calibration is recommended (see Section 9.10.2.1 on page 35). The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The BitPhase register enables correlation interval position alignment with the received signal’s bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital results are sent to the FIFO buffer. Several tuning steps are possible for this circuit. The signal can be observed on its way through the receiver as shown in Figure 12. One signal at a time can be routed to pin AUX using the TestAnaSelect register as described in Section 15.2.2 on page 112. 9.10.2 Receiver operation In general, the default settings programmed in the StartUp initialization file are suitable for use with the CLRC632 to MIFARE card data communication. However, in some environments specific user settings will achieve better performance. 9.10.2.1 Automatic Q-clock calibration The quadrature demodulation concept of the receiver generates a phase signal (I-clock) and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90. After the reset phase, a calibration procedure is automatically performed. Fig 12. Receiver circuit block diagram 001aak615 ClkQDelay[4:0] ClkQCalib ClkQ180Deg BitPhase[7:0] CORRELATION CIRCUITRY EVALUATION AND DIGITIZER CIRCUITRY MinLevel[3:0] CollLevel[3:0] RxWait[7:0] RcvClkSell s_valid s_data s_coll s_clock Gain[1:0] to TestAnaOutSel clock I TO Q CONVERSION I-clock Q-clock 13.56 MHz DEMODULATOR RX VCorrDI VCorrNI VCorrDQ VCorrNQ VEvalR VEvalL VRxFollQ VRxFollI VRxAmpI VRxAmpQCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 36 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Automatic calibration can be set-up to execute at the end of each Transceive command if bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations except after the reset sequence. Automatic calibration can also be triggered by the software when bit ClkQCalib has a logic 0 to logic 1 transition. Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or approximately 4.8 s. The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the phase-shift between the Q-clock and the I-clock is greater than 180. Remark: • The StartUp configuration file enables automatic Q-clock calibration after a reset • If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to logic 1 can be used to permanently disable automatic calibration. • It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The aim could be to disable automatic calibration and set the delay using the software. Configuring the delay value using the software requires bit ClkQCalib to have been previously set to logic 1 and a time interval of at least 4.8 s has elapsed. Each delay value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the configured delay value is overwritten by the next automatic calibration interval. 9.10.2.2 Amplifier The demodulated signal must be amplified by the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted using the RxControl1 register Gain[1:0] bits; see Table 29. Fig 13. Automatic Q-clock calibration 001aak616 calibration impulse from reset sequence a rising edge initiates Q-clock calibration ClkQCalib bit calibration impulse from end of Transceive command Table 29. Gain factors for the internal amplifier See Table 86 “RxControl1 register bit descriptions” on page 64 for additional information. Register setting Gain factor [dB] (simulation results) 00 20 01 24 10 31 11 35CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 37 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.10.2.3 Correlation circuitry The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure of the amplitude of the expected signal in the received signal. This is done for both, the Q and I-channels. The correlator provides two outputs for each of the two input channels, resulting in a total of four output signals. The correlation circuitry needs the phase information for the incoming card signal for optimum performance. This information is defined for the microprocessor using the BitPhase register. This value defines the phase relationship between the transmitter and receiver clock in multiples of the BitPhase time (tBitPhase) = 1 / 13.56 MHz. 9.10.2.4 Evaluation and digitizer circuitry The correlation results are evaluated for each bit-half of the Manchester coded signal. The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the current bit is valid • If the bit is valid, its value is identified • If the bit is not valid, it is checked to identify if it contains a bit-collision Select the following levels for optimal using RxThreshold register bits: • MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal which is considered valid. • CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester coded signal to generate a bit-collision. If the signal’s strength is below this value, logic 1 and logic 0 can be determined unequivocally. After data transmission, the card is not allowed to send its response before a preset time period which is called the frame guard time in the ISO/IEC 14443 standard. The length of this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register defines when the receiver is switched on after data transmission to the card in multiples of one bit duration. If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used. Remark: It is recommended to use the Q-clock. 9.11 Serial signal switch The CLRC632 comprises two main blocks: • digital circuitry: comprising the state machines, encoder and decoder logic etc. • analog circuitry: comprising the modulator, antenna drivers, receiver and amplification circuitry The interface between these two blocks can be configured so that the interface signals are routed to pins MFIN and MFOUT. This makes it possible to connect the analog part of one CLRC632 to the digital part of another device. The serial signal switch can be used to measure MIFARE and ISO/IEC 14443 A as well as related I-CODE1 and ISO/IEC 15693 signals.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 38 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The Manchester signal and the Manchester signal with subcarrier can only be accessed on pin MFOUT at 106 kBd based on ISO/IEC 14443 A. 9.11.1 Serial signal switch block diagram Figure 14 shows the serial signal switches. Three different switches are implemented in the serial signal switch enabling the CLRC632 to be used in different configurations. The serial signal switch can also be used to check the transmitted and received data during the design-in phase or for test purposes. Section 15.2.1 on page 110 describes the analog test signals and measurements at the serial signal switch. Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The CLRC632 functionality includes the test modes for the SLRC400 using pin MFOUT. Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and settings used to configure and control the serial signal switch. 9.11.2 Serial signal switch registers The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal Manchester decoder and are described in Table 30. Fig 14. Serial signal switch block diagram 3 MFIN MFOUT 001aak617 MODULATOR DRIVER (part of) analog circuitry SUBCARRIER DEMODULATOR TX1 TX2 RX CARRIER DEMODULATOR 2 MILLER CODER 1 OUT OF 256 NRZ OR 1 OUT OF 4 MANCHESTER DECODER SERIAL SIGNAL SWITCH (part of) serial data processing Decoder Source[1:0] 2 Modulator Source[1:0] SUBCARRIER DEMODULATOR serial data out 0 0 1 internal 2 Manchester with subcarrier 3 0 1 2 3 4 5 6 0 1 envelope MFIN 0 1 2 3 Manchester Manchester out serial data in 7 0 0 1 1 envelope transmit NRZ Manchester with subcarrier Manchester reserved reserved MFOUTSelect[2:0] digital test signal signal to MFOUTCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 39 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2. The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be routed to pin MFOUT. To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT bit must be logic 0. 9.11.2.1 Active antenna concept The CLRC632 analog and digital circuitry is accessed using pins MFIN and MFOUT. Table 33 lists the required settings. Table 30. DecoderSource[1:0] values See Table 96 on page 67 for additional information. Number DecoderSource [1:0] Input signal to decoder 0 00 constant 0 1 01 output of the analog part. This is the default configuration 2 10 direct connection to pin MFIN; expects an 847.5 kHz subcarrier signal modulated by a Manchester encoded signal 3 11 direct connection to pin MFIN; expects a Manchester encoded signal Table 31. ModulatorSource[1:0] values See Table 96 on page 67 for additional information. Number ModulatorSource [1:0] Input signal to modulator 0 00 constant 0 (energy carrier off on pins TX1 and TX2) 1 01 constant 1 (continuous energy carrier on pins TX1 and TX2) 2 10 modulation signal (envelope) from the internal encoder. This is the default configuration. 3 11 direct connection to MFIN; expects a Miller pulse coded signal Table 32. MFOUTSelect[2:0] values See Table 110 on page 70 for additional information. Number MFOUTSelect [2:0] Signal routed to pin MFOUT 0 000 constant LOW 1 001 constant HIGH 2 010 modulation signal (envelope) from the internal encoder 3 011 serial data stream to be transmitted; the same as for MFOUTSelect[2:0] = 001 but not encoded by the selected pulse encoder 4 100 output signal of the receiver circuit; card modulation signal regenerated and delayed 5 101 output signal of the subcarrier demodulator; Manchester coded card signal 6 110 reserved 7 111 reservedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 40 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] The number column refers to the value in the number column of Table 30, Table 31 and Table 32. Two CLRC632 devices configured as described in Table 33 can be connected to each other using pins MFOUT and MFIN. Remark: The active antenna concept can only be used at 106 kBd based on ISO/IEC 14443 A. 9.11.2.2 Driving both RF parts It is possible to connect both passive and active antennas to a single IC. The passive antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching circuit. At the same time an active antenna is connected to pins MFOUT and MFIN. In this configuration, two RF parts can be driven, one after another, by one microprocessor. 9.12 MIFARE higher baud rates The MIFARE system is specified with a fixed baud rate of 106 kBd for communication on the RF interface. The current version of ISO/IEC 14443 A also defines 106 kBd for the initial phase of a communication between Proximity Integrated Circuit Cards (PICC) and Proximity Coupling Devices (PCD). To cover requirements of large data transmissions and to speed up terminal to card communication, the CLRC632 supports communication at MIFARE higher baud rates in combination with a microcontroller IC such as the MIFARE ProX. The MIFARE higher baud rates concept is described in the application note: MIFARE Implementation of Higher Baud rates Ref. 5. This application covers the integration of the MIFARE higher baud rates communication concept in current applications. Table 33. Register settings to enable use of the analog circuitry Register Number[1] Signal CLRC632 pin Analog circuitry settings ModulatorSource 3 Miller pulse encoded MFIN MFOUTSelect 4 Manchester encoded with subcarrier MFOUT DecoderSource X - - Digital circuitry settings ModulatorSource X - - MFOUTSelect 2 Miller pulse encoded MFOUT DecoderSource 2 Manchester encoded with subcarrier MFIN Table 34. MIFARE higher baud rates Communication direction Baud rates (kBd) CLRC632 based PCD  microcontroller PICC supporting higher baud rates 106, 212, 424 Microcontroller PICC supporting higher baud rates  CLRC632 based PCD 106, 212, 424CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 41 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.13 ISO/IEC 14443 B communication scheme The international standard ISO/IEC 14443 covers two communication schemes; ISO/IEC 14443 A and ISO/IEC 14443 B. The CLRC632 reader IC fully supports both ISO/IEC 14443 variants. Table 35 describes the registers and flags covered by the ISO/IEC 14443 B communication protocol. As reference documentation, the international standard ISO/IEC 14443 Identification cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4 (Ref. 4) can be used. Remark: NXP Semiconductors does not offer a basic function library to design-in the ISO/IEC 14443 B protocol. Table 35. ISO/IEC 14443 B registers and flags Flag Register Bit Register address CharSpacing[2:0] TypeBFraming 4 to 2 17h CoderRate[2:0] CoderControl 5 to 3 14h EOFWidth TypeBFraming 5 17h FilterAmpDet BPSKDemControl 4 1Dh Force100ASK TxControl 4 11h GsCfgCW[5:0] CwConductance 5 to 0 12h GsCfgMod[5:0] ModConductance 5 to 0 13h MinLevel[3:0] RxThreshold 7 to 4 1Ch NoTxEOF TypeBFraming 6 17h NoTxSOF TypeBFraming 7 17h NoRxEGT BPSKDemControl 6 1Dh NoRxEOF BPSKDemControl 5 1Dh NoRxSOF BPSKDemControl 7 1Dh RxCoding DecoderControl 0 1Ah RxFraming[1:0] DecoderControl 4 to 3 1Ah SOFWidth[1:0] TypeBFraming 1 to 0 17h SubCPulses[2:0] RxControl1 7 to 5 19h TauB[1:0] BPSKDemControl 1 to 0 1Dh TauD[1:0] BPSKDemControl 3 to 2 1Dh TxCoding[2:0] CoderControl 2 to 0 14hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 42 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.14 MIFARE authentication and Crypto1 The security algorithm used in the MIFARE products is called Crypto1. It is based on a proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards, knowledge of the key format is needed. The correct key must be available in the CLRC632 to enable successful card authentication and access to the card’s data stored in the EEPROM. After a card is selected as defined in ISO/IEC 14443 A standard, the user can continue with the MIFARE protocol. It is mandatory that card authentication is performed. Crypto1 authentication is a 3-pass authentication which is automatically performed when the Authent1 and Authent2 commands are executed (see Section 11.7.3 on page 98 and Section 11.7.4 on page 98). During the card authentication procedure, the security algorithm is initialized. After a successful authentication, communication with the MIFARE card is encrypted. 9.14.1 Crypto1 key handling On execution of the authentication command, the CLRC632 reads the key from the key buffer. The key is always read from the key buffer and ensures Crypto1 authentication commands do not require addressing of a key. The user must ensure the correct key is prepared in the key buffer before triggering card authentication. The key buffer can be loaded from: • the EEPROM using the LoadKeyE2 command (see Section 11.7.1 on page 97) • the microprocessor’s FIFO buffer using the LoadKey command (see Section 11.7.2 on page 97). This is shown in Figure 15. Fig 15. Crypto1 key handling block diagram 001aak624 FIFO BUFFER from the microcontroller WriteE2 LoadKey EEPROM KEYS KEY BUFFER LoadKeyE2 during Authent1 CRYPTO1 MODULE serial data stream in serial data stream out (plain) (encrypted)CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 43 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.14.2 Authentication procedure The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid authentication, the correct key has to be available in the key buffer of the CLRC632. This can be ensured as follows: 1. Load the internal key buffer by using the LoadKeyE2 (see Section 11.7.1 on page 97) or the LoadKey (see Section 11.7.2 on page 97) commands. 2. Start the Authent1 command (see Section 11.7.3 on page 98). When finished, check the error flags to obtain the command execution status. 3. Start the Authent2 command (see Section 11.7.4 on page 98). When finished, check the error flags and bit Crypto1On to obtain the command execution status. 10. CLRC632 registers 10.1 Register addressing modes Three methods can be used to operate the CLRC632: • initiating functions and controlling data by executing commands • configuring the functional operation using a set of configuration bits • monitoring the state of the CLRC632 by reading status flags The commands, configuration bits and flags are accessed using the microprocessor interface. The CLRC632 can internally address 64 registers using six address lines. 10.1.1 Page registers The CLRC632 register set is segmented into eight pages contain eight registers each. A Page register can always be addressed, irrespective of which page is currently selected. 10.1.2 Dedicated address bus When using the CLRC632 with the dedicated address bus, the microprocessor defines three address lines using address pins A0, A1 and A2. This enables addressing within a page. To switch between registers in different pages a paging mechanism needs to be used. Table 36 shows how the register address is assembled. 10.1.3 Multiplexed address bus The microprocessor may define all six address lines at once using the CLRC632 with a multiplexed address bus. In this case either the paging mechanism or linear addressing can be used. Table 37 shows how the register address is assembled. Table 36. Dedicated address bus: assembling the register address Register bit: UsePageSelect Register address 1 PageSelect2 PageSelect1 PageSelect0 A2 A1 A0CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 44 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers. Table 38 describes the function of the Access column in the register tables. Table 37. Multiplexed address bus: assembling the register address Multiplexed address bus type UsePage Select Register address Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0 Linear addressing 0 AD5 AD4 AD3 AD2 AD1 AD0 Table 38. Behavior and designation of register bits Abbreviation Behavior Description R/W read and write These bits can be read and written by the microprocessor. Since they are only used for control, their content is not influenced by internal state machines. Example: TimerReload register may be read and written by the microprocessor. It will also be read by internal state machines but never changed by them. D dynamic These bits can be read and written by the microprocessor. Nevertheless, they may also be written automatically by internal state machines. Example: the Command register changes its value automatically after the execution of the command. R read only These registers hold flags which have a value determined by internal states only. Example: the ErrorFlag register cannot be written externally but shows internal states. W write only These registers are used for control only. They may be written by the microprocessor but cannot be read. Reading these registers returns an undefined value. Example: The TestAnaSelect register is used to determine the signal on pin AUX however, it is not possible to read its content.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 45 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.3 Register overview Table 39. CLRC632 register overview Sub address (Hex) Register name Function Refer to Page 0: Command and status 00h Page selects the page register Table 41 on page 50 01h Command starts and stops command execution Table 43 on page 50 02h FIFOData input and output of 64-byte FIFO buffer Table 45 on page 51 03h PrimaryStatus receiver and transmitter and FIFO buffer status flags Table 47 on page 51 04h FIFOLength number of bytes buffered in the FIFO buffer Table 49 on page 52 05h SecondaryStatus secondary status flags Table 51 on page 53 06h InterruptEn enable and disable interrupt request control bits Table 53 on page 53 07h InterruptRq interrupt request flags Table 55 on page 54 Page 1: Control and status 08h Page selects the page register Table 41 on page 50 09h Control control flags for timer unit, power saving etc Table 57 on page 55 0Ah ErrorFlag show the error status of the last command executed Table 59 on page 55 0Bh CollPos bit position of the first bit-collision detected on the RF interface Table 61 on page 56 0Ch TimerValue value of the timer Table 63 on page 57 0Dh CRCResultLSB LSB of the CRC coprocessor register Table 65 on page 57 0Eh CRCResultMSB MSB of the CRC coprocessor register Table 67 on page 57 0Fh BitFraming adjustments for bit oriented frames Table 69 on page 58 Page 2: Transmitter and coder control 10h Page selects the page register Table 41 on page 50 11h TxControl controls the operation of the antenna driver pins TX1 and TX2 Table 71 on page 59 12h CwConductance selects the conductance of the antenna driver pins TX1 and TX2 Table 73 on page 60 13h ModConductance defines the driver output conductance Table 75 on page 60 14h CoderControl sets the clock frequency and the encoding Table 77 on page 61 15h ModWidth selects the modulation pulse width Table 79 on page 62 16h ModWidthSOF selects the SOF pulse-width modulation (I-CODE1 fast mode) Table 81 on page 62 17h TypeBFraming defines the framing for ISO/IEC 14443 B communication Table 83 on page 63 Page 3: Receiver and decoder control 18 Page selects the page register Table 41 on page 50 19 RxControl1 controls receiver behavior Table 85 on page 64 1A DecoderControl controls decoder behavior Table 87 on page 65 1B BitPhase selects the bit-phase between transmitter and receiver clock Table 89 on page 65 1C RxThreshold selects thresholds for the bit decoder Table 91 on page 66 1D BPSKDemControl controls BPSK receiver behavior Table 93 on page 66 1Eh RxControl2 controls decoder and defines the receiver input source Table 95 on page 67 1Fh ClockQControl clock control for the 90 phase-shifted Q-channel clock Table 97 on page 67CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 46 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Page 4: RF Timing and channel redundancy 20h Page selects the page register Table 41 on page 50 21h RxWait selects the interval after transmission before the receiver starts Table 99 on page 68 22h ChannelRedundancy selects the method and mode used to check data integrity on the RF channel Table 101 on page 68 23h CRCPresetLSB preset LSB value for the CRC register Table 103 on page 69 24h CRCPresetMSB preset MSB value for the CRC register Table 105 on page 69 25h TimeSlotPeriod selects the time between automatically transmitted frames Table 107 on page 69 26h MFOUTSelect selects internal signal applied to pin MFOUT, includes the MSB of value TimeSlotPeriod; see Table 107 on page 69 Table 109 on page 70 27h PreSet27 these values are not changed Table 111 on page 70 Page 5: FIFO, timer and IRQ pin configuration 28h Page selects the page register Table 41 on page 50 29h FIFOLevel defines the FIFO buffer overflow and underflow warning levels Table 49 on page 52 2Ah TimerClock selects the timer clock divider Table 114 on page 71 2Bh TimerControl selects the timer start and stop conditions Table 116 on page 72 2Ch TimerReload defines the timer preset value Table 118 on page 72 2Dh IRQPinConfig configures pin IRQ output stage Table 120 on page 73 2Eh PreSet2E these values are not changed Table 122 on page 73 2Fh PreSet2F these values are not changed Table 123 on page 73 Page 6: reserved registers 30h Page selects the page register Table 41 on page 50 31h reserved reserved Table 124 on page 73 32h reserved reserved 33h reserved reserved 34h reserved reserved 35h reserved reserved 36h reserved reserved 37h reserved reserved Page 7: Test control 38h Page selects the page register Table 41 on page 50 39h reserved reserved Table 125 on page 74 3Ah TestAnaSelect selects analog test mode Table 126 on page 74 3Bh reserved reserved Table 128 on page 75 3Ch reserved reserved Table 129 on page 75 3Dh TestDigiSelect selects digital test mode Table 130 on page 75 3Eh reserved reserved Table 132 on page 76 3Fh reserved reserved Table 39. CLRC632 register overview …continued Sub address (Hex) Register name Function Refer toCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 47 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.4 CLRC632 register flags overview Table 40. CLRC632 register flags overview Flag(s) Register Bit Address AccessErr ErrorFlag 5 0Ah BitPhase[7:0] BitPhase 7 to 0 1Bh CharSpacing[2:0] TypeBFraming 4 to 2 17h, ClkQ180Deg ClockQControl 7 1Fh ClkQCalib ClockQControl 6 1Fh ClkQDelay[4:0] ClockQControl 4 to 0 1Fh CoderRate[2:0] CoderControl 5 to 3 14h CollErr ErrorFlag 0 0Ah CollLevel[3:0] RxThreshold 3 to 0 1Ch CollPos[7:0] CollPos 7 to 0 0Bh Command[5:0] Command 5 to 0 01h CRC3309 ChannelRedundancy 5 22h CRC8 ChannelRedundancy 4 22h CRCErr ErrorFlag 3 0Ah CRCPresetLSB[7:0] CRCPresetLSB 7 to 0 23h CRCPresetMSB[7:0] CRCPresetMSB 7 to 0 24h CRCReady SecondaryStatus 5 05h CRCResultMSB[7:0] CRCResultMSB 7 to 0 0Eh CRCResultLSB[7:0] CRCResultLSB 7 to 0 0Dh Crypto1On Control 3 09h DecoderSource[1:0] RxControl2 1 to 0 1Eh E2Ready SecondaryStatus 6 05h EOFWidth TypeBFraming 5 17h Err PrimaryStatus 2 03h FIFOData[7:0] FIFOData 7 to 0 02h FIFOLength[6:0] FIFOLength 6 to 0 04h FIFOOvfl ErrorFlag 4 0Ah FilterAmpDet BPSKDemControl 4 1Dh FlushFIFO Control 0 09h Force100ASK TxControl 4 11h FramingErr ErrorFlag 2 0Ah Gain[1:0] RxControl1 1 to 0 19h GsCfgCW[5:0] CwConductance 5 to 0 12h GsCfgMod[5:0] ModConductance 5 to 0 13h HiAlert PrimaryStatus 1 03h HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h IdleIEn InterruptEn 2 06h IdleIRq InterruptRq 2 07hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 48 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution IFDetectBusy Command 7 01h IRq PrimaryStatus 3 03h IRQInv IRQPinConfig 1 2Dh IRQPushPull IRQPinConfig 0 2Dh ISO Selection[1:0] RxControl1 4 to 3 19h KeyErr ErrorFlag 6 0Ah LoAlert PrimaryStatus 0 03h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h LPOff RxControl1 2 19h MFOUTSelect[2:0] MFOUTSelect 2 to 0 26h MinLevel[3:0] RxThreshold 7 to 4 1Ch ModemState[2:0] PrimaryStatus 6 to 4 03h ModulatorSource[1:0] TxControl 6 to 5 11h ModWidth[7:0] ModWidth 7 to 0 15h NoRxEGT BPSKDemControl 6 1Dh NoRxEOF BPSKDemControl 5 1Dh NoRxSOF BPSKDemControl 7 1Dh NoTxEOF TypeBFraming 6 17h NoTxSOF TypeBFraming 7 17h PageSelect[2:0] Page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h ParityEn ChannelRedundancy 0 22h ParityErr ErrorFlag 1 0Ah ParityOdd ChannelRedundancy 1 22h PowerDown Control 4 09h RcvClkSelI RxControl2 7 1Eh RxAlign[2:0] BitFraming 6 to 4 0Fh RxAutoPD RxControl2 6 1Eh RxCRCEn ChannelRedundancy 3 22h RxCoding DecoderControl 0 1Ah RxFraming[1:0] DecoderControl 4 to 3 1Ah RxIEn InterruptEn 3 06h RxIRq InterruptRq 3 07h RxLastBits[2:0] SecondaryStatus 2 to 0 05h RxMultiple DecoderControl 6 1Ah RxWait[7:0] RxWait 7 to 0 21h SetIEn InterruptEn 7 06h SetIRq InterruptRq 7 07h SignalToMFOUT TestDigiSelect 7 3Dh SOFWidth[1:0] TypeBFraming 1 to 0 17h Table 40. CLRC632 register flags overview …continued Flag(s) Register Bit AddressCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 49 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution StandBy Control 5 09h SubCPulses[2:0] RxControl1 7 to 5 19h TauB[1:0] BPSKDemControl 1 to 0 1Dh TauD[1:0] BPSKDemControl 3 to 2 1Dh TAutoRestart TimerClock 5 2Ah TestAnaOutSel[4:0] TestAnaSelect 3 to 0 3Ah TestDigiSignalSel[6:0] TestDigiSelect 6 to 0 3Dh TimerIEn InterruptEn 5 06h TimerIRq InterruptRq 5 07h TimerValue[7:0] TimerValue 7 to 0 0Ch TimeSlotPeriod[7:0] TimeSlotPeriod 7 to 0 25h TimeSlotPeriodMSB MFOUTSelect 4 26h TPreScaler[4:0] TimerClock 4 to 0 2Ah TReloadValue[7:0] TimerReload 7 to 0 2Ch TRunning SecondaryStatus 7 05h TStartTxBegin TimerControl 0 2Bh TStartTxEnd TimerControl 1 2Bh TStartNow Control 1 09h TStopRxBegin TimerControl 2 2Bh TStopRxEnd TimerControl 3 2Bh TStopNow Control 2 09h TX1RFEn TxControl 0 11h TX2Cw TxControl 3 11h TX2Inv TxControl 3 11h TX2RFEn TxControl 1 11h TxCoding[2:0] CoderControl 2 to 0 14h TxCRCEn ChannelRedundancy 2 22h TxIEn InterruptEn 4 06h TxIRq InterruptRq 4 07h TxLastBits[2:0] BitFraming 2 to 0 0Fh UsePageSelect Page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h WaterLevel[5:0] FIFOLevel 5 to 0 29h ZeroAfterColl DecoderControl 7 1Ah, bit 5 Table 40. CLRC632 register flags overview …continued Flag(s) Register Bit AddressCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 50 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. 10.5.1.2 Command register Starts and stops the command execution. Table 41. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol UsePageSelect 0000 PageSelect[2:0] Access R/W R/W R/W R/W R/W Table 42. Page register bit descriptions Bit Symbol Value Description 7 UsePageSelect 1 the value of PageSelect[2:0] is used as the register address A5, A4, and A3. The LSBs of the register address are defined using the address pins or the internal address latch, respectively. 0 the complete content of the internal address latch defines the register address. The address pins are used as described in Table 5 on page 8. 6 to 3 0000 - reserved 2 to 0 PageSelect[2:0] - when UsePageSelect = logic 1, the value of PageSelect is used to specify the register page (A5, A4 and A3 of the register address) Table 43. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol IFDetectBusy 0 Command[5:0] Access R R D Table 44. Command register bit descriptions Bit Symbol Value Description 7 IFDetectBusy - shows the status of interface detection logic 0 interface detection finished successfully 1 interface detection ongoing 6 0 - reserved 5 to 0 Command[5:0] - activates a command based on the Command code. Reading this register shows which command is being executed.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 51 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. 10.5.1.4 PrimaryStatus register Bits relating to receiver, transmitter and FIFO buffer status flags. Table 45. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol FIFOData[7:0] Access D Table 46. FIFOData register bit descriptions Bit Symbol Description 7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO buffer acts as a parallel in to parallel out converter for all data streams. Table 47. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 ModemState[2:0] IRq Err HiAlert LoAlert Access R R R R R R Table 48. PrimaryStatus register bit descriptions Bit Symbol Value Status Description 7 0 - reserved 6 to 4 ModemState[2:0] shows the state of the transmitter and receiver state machines: 000 Idle neither the transmitter or receiver are operating; neither of them are started or have input data 001 TxSOF transmit start of frame pattern 010 TxData transmit data from the FIFO buffer (or redundancy CRC check bits) 011 TxEOF transmit End Of Frame (EOF) pattern 100 GoToRx1 intermediate state 1; receiver starts GoToRx2 intermediate state 2; receiver finishes 101 PrepareRx waiting until the RxWait register time period expires 110 AwaitingRx receiver activated; waiting for an input signal on pin RX 111 Receiving receiving data 3 IRq - shows any interrupt source requesting attention based on the InterruptEn register flag settingsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 52 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.5 FIFOLength register Number of bytes in the FIFO buffer. 2 Err 1 any error flag in the ErrorFlag register is set 1 HiAlert 1 the alert level for the number of bytes in the FIFO buffer (FIFOLength[6:0]) is: otherwise value = logic 0 Example: FIFOLength = 60, WaterLevel = 4 then HiAlert = logic 1 FIFOLength = 59, WaterLevel = 4 then HiAlert = logic 0 0 LoAlert 1 the alert level for number of bytes in the FIFO buffer (FIFOLength[6:0]) is: otherwise value = logic 0 Example: FIFOLength = 4, WaterLevel = 4 then LoAlert = logic 1 FIFOLength = 5, WaterLevel = 4 then LoAlert = logic 0 Table 48. PrimaryStatus register bit descriptions …continued Bit Symbol Value Status Description HiAlert 64 FIFOLength =   –  WaterLevel LoAlert FIFOLe = ngth WaterLevel  Table 49. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 FIFOLength[6:0] Access R R Table 50. FIFOLength bit descriptions Bit Symbol Description 7 0 reserved 6 to 0 FIFOLength[6:0] gives the number of bytes stored in the FIFO buffer. Writing increments the FIFOLength register value while reading decrements the FIFOLength register valueCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 53 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.6 SecondaryStatus register Various secondary status flags. 10.5.1.7 InterruptEn register Control bits to enable and disable passing of interrupt requests. [1] This bit can only be set or cleared using bit SetIEn. Table 51. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TRunning E2Ready CRCReady 00 RxLastBits[2:0] Access R R R R R Table 52. SecondaryStatus register bit descriptions Bit Symbol Value Description 7 TRunning 1 the timer unit is running and the counter decrements the TimerValue register on the next timer clock cycle 0 the timer unit is not running 6 E2Ready 1 EEPROM programming is finished 0 EEPROM programming is ongoing 5 CRCReady 1 CRC calculation is finished 0 CRC calculation is ongoing 4 to 3 00 - reserved 2 to 0 RxLastBits [2:0] - shows the number of valid bits in the last received byte. If zero, the whole byte is valid Table 53. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SetIEn 0 TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn Access W R/W R/W R/W R/W R/W R/W R/W Table 54. InterruptEn register bit descriptions Bit Symbol Value Description 7 SetIEn 1 indicates that the marked bits in the InterruptEn register are set 0 clears the marked bits 6 0 - reserved 5 TimerIEn - sends the TimerIRq timer interrupt request to pin IRQ[1] 4 TxIEn - sends the TxIRq transmitter interrupt request to pin IRQ[1] 3 RxIEn - sends the RxIRq receiver interrupt request to pin IRQ[1] 2 IdleIEn - sends the IdleIRq idle interrupt request to pin IRQ[1] 1 HiAlertIEn - sends the HiAlertIRq high alert interrupt request to pin IRQ[1] 0 LoAlertIEn - sends the LoAlertIRq low alert interrupt request to pin IRQ[1]CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 54 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.8 InterruptRq register Interrupt request flags. [1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq. Table 55. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SetIRq 0 TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq Access W R/W D D D D D D Table 56. InterruptRq register bit descriptions Bit Symbol Value Description 7 SetIRq 1 sets the marked bits in the InterruptRq register 0 clears the marked bits in the InterruptRq register 6 0 - reserved 5 TimerIRq 1 timer decrements the TimerValue register to zero 0 timer decrements are still greater than zero 4 TxIRq 1 TxIRq is set to logic 1 if one of the following events occurs: Transceive command; all data transmitted Authent1 and Authent2 commands; all data transmitted WriteE2 command; all data is programmed CalcCRC command; all data is processed 0 when not acted on by Transceive, Authent1, Authent2, WriteE2 or CalcCRC commands 3 RxIRq 1 the receiver terminates 0 reception still ongoing 2 IdleIRq 1 command terminates correctly. For example; when the Command register changes its value from any command to the Idle command. If an unknown command is started the IdleIRq bit is set. Microprocessor start-up of the Idle command does not set the IdleIRq bit. 0 IdleIRq = logic 0 in all other instances 1 HiAlertIRq 1 PrimaryStatus register HiAlert bit is set[1] 0 PrimaryStatus register HiAlert bit is not set 0 LoAlertIRq 1 PrimaryStatus register LoAlert bit is set[1] 0 PrimaryStatus register LoAlert bit is not setCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 55 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.2.2 Control register Various control flags, for timer, power saving, etc. 10.5.2.3 ErrorFlag register Error flags show the error status of the last executed command. Table 57. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 StandBy PowerDown Crypto1On TStopNow TStartNow FlushFIFO Access R/W D D D D D D Table 58. Control register bit descriptions Bit Symbol Value Description 7 to 6 00 - reserved 5 StandBy 1 activates Standby mode. The current consuming blocks are switched off but the clock keeps running 4 PowerDown 1 activates Power-down mode. The current consuming blocks are switched off including the clock 3 Crypto1On 1 Crypto1 unit is switched on and all data communication with the card is encrypted. This bit can only be set to logic 1 by successful execution of the Authent2 command 0 Crypto1 unit is switched off. All data communication with the card is unencrypted (plain) 2 TStopNow 1 immediately stops the timer. Reading this bit always returns logic 0 1 TStartNow 1 immediately starts the timer. Reading this bit will always returns logic 0 0 FlushFIFO 1 immediately clears the internal FIFO buffer’s read and write pointer, the FIFOLength[6:0] bits are set to logic 0 and the FIFOOvfl flag. Reading this bit always returns logic 0 Table 59. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 KeyErr AccessErr FIFOOvfl CRCErr FramingErr ParityErr CollErr Access R R R R R R R R Table 60. ErrorFlag register bit descriptions Bit Symbol Value Description 7 0 - reserved 6 KeyErr 1 set when the LoadKeyE2 or LoadKey command recognize that the input data is not encoded based on the Key format definition 0 set when the LoadKeyE2 or the LoadKey command startsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 56 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] Only valid for communication using ISO/IEC 14443 A. 10.5.2.4 CollPos register Bit position of the first bit-collision detected on the RF interface. Remark: A bit collision is not indicated in the CollPos register when using the ISO/IEC 14443 B protocol standard. 5 AccessErr 1 set when the access rights to the EEPROM are violated 0 set when an EEPROM related command starts 4 FIFOOvfl 1 set when the microprocessor or CLRC632 internal state machine (e.g. receiver) tries to write data to the FIFO buffer when it is full 3 CRCErr 1 set when RxCRCEn is set and the CRC fails 0 automatically set during the PrepareRx state in the receiver start phase 2 FramingErr 1 set when the SOF is incorrect 0 automatically set during the PrepareRx state in the receiver start phase 1 ParityErr 1 set when the parity check fails 0 automatically set during the PrepareRx state in the receiver start phase 0 CollErr 1 set when a bit-collision is detected[1] 0 automatically set during the PrepareRx state in the receiver start phase[1] Table 60. ErrorFlag register bit descriptions …continued Bit Symbol Value Description Table 61. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CollPos[7:0] Access R Table 62. CollPos register bit descriptions Bit Symbol Description 7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a received frame. Example: 00h indicates a bit collision in the start bit 01h indicates a bit collision in the 1st bit ... 08h indicates a bit collision in the 8th bitCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 57 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.2.5 TimerValue register Value of the timer. 10.5.2.6 CRCResultLSB register LSB of the CRC coprocessor register. 10.5.2.7 CRCResultMSB register MSB of the CRC coprocessor register. Table 63. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TimerValue[7:0] Access R Table 64. TimerValue register bit descriptions Bit Symbol Description 7 to 0 TimerValue[7:0] this register shows the timer counter value Table 65. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCResultLSB[7:0] Access R Table 66. CRCResultLSB register bit descriptions Bit Symbol Description 7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if CRCReady = logic 1 Table 67. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCResultMSB[7:0] Access R Table 68. CRCResultMSB register bit descriptions Bit Symbol Description 7 to 0 CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if CRCReady = logic 1. The register’s value is undefined for 8-bit CRC calculation.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 58 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 69. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 RxAlign[2:0] 0 TxLastBits[2:0] Access R/W D R/W D Table 70. BitFraming register bit descriptions Bit Symbol Value Description 7 0 - reserved 6 to 4 RxAlign[2:0] defines the bit position for the first bit received to be stored in the FIFO buffer. Additional received bits are stored in the next subsequent bit positions. After reception, RxAlign[2:0] is automatically cleared. For example: 000 the LSB of the received bit is stored in bit position 0 and the second received bit is stored in bit position 1 001 the LSB of the received bit is stored in bit position 1, the second received bit is stored in bit position 2 ... 111 the LSB of the received bit is stored in bit position 7, the second received bit is stored in the next byte in bit position 0 3 0 - reserved 2 to 0 TxLastBits[2:0] - defines the number of bits of the last byte that shall be transmitted. 000 indicates that all bits of the last byte will be transmitted. TxLastBits[2:0] is automatically cleared after transmission.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 59 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.3.2 TxControl register Controls the logical behavior of the antenna pin TX1 and TX2. Table 71. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 ModulatorSource [1:0] Force 100ASK TX2Inv TX2Cw TX2RFEn TX1RFEn Access R/W R/W R/W R/W R/W R/W R/W Table 72. TxControl register bit descriptions Bit Symbol Value Description 7 0 - this value must not be changed 6 to 5 ModulatorSource[1:0] selects the source for the modulator input: 00 modulator input is LOW 01 modulator input is HIGH 10 modulator input is the internal encoder 11 modulator input is pin MFIN 4 Force100ASK - forces a 100 % ASK modulation independent ModConductance register setting 3 TX2Inv 0 delivers an inverted 13.56 MHz energy carrier output signal on pin TX2 2 TX2Cw 1 delivers a continuously unmodulated 13.56 MHz energy carrier output signal on pin TX2 0 enables modulation of the 13.56 MHz energy carrier 1 TX2RFEn 1 the output signal on pin TX2 is the 13.56 MHz energy carrier modulated by the transmission data 0 TX2 is driven at a constant output level 0 TX1RFEn 1 the output signal on pin TX1 is the 13.56 MHz energy carrier modulated by the transmission data 0 TX1 is driven at a constant output levelCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 60 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. See Section 9.9.3 on page 32 for detailed information about GsCfgCW[5:0]. 10.5.3.4 ModConductance register Defines the driver output conductance. Remark: When Force100ASK = logic 1, the GsCfgMod[5:0] value has no effect. See Section 9.9.3 on page 32 for detailed information about GsCfgMod[5:0]. Table 73. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 GsCfgCW[5:0] Access R/W R/W R/W Table 74. CwConductance register bit descriptions Bit Symbol Description 7 to 6 00 these values must not be changed 5 to 0 GsCfgCW[5:0] defines the conductance register value for the output driver. This can be used to regulate the output power/current consumption and operating distance. Table 75. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 GsCfgMod[5:0] Access R/W R/W R/W Table 76. ModConductance register bit descriptions Bit Symbol Description 7 to 6 00 these values must not be changed 5 to 0 GsCfgMod[5:0] defines the ModConductance register value for the output driver during modulation. This is used to regulate the modulation index.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 61 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 77. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SendOnePulse 0 CoderRate[2:0] TxCoding[2:0] Access R/W R/W R/W R/W Table 78. CoderControl register bit descriptions Bit Symbol Value Description 7 SendOnePulse 1 forced ISO/IEC 15693 modulation. This is used to switch to the next TimeSlot if the Inventory command is used. 0 this bit is not cleared automatically, it must be reset by the user to logic 0 6 0 - this value must not be changed 5 to 3 CoderRate[2:0] this register defines the clock rate for the encoder circuit 000 MIFARE 848 kBd 001 MIFARE 424 kBd 010 MIFARE 212 kBd 011 MIFARE 106 kBd; ISO/IEC 14443 A 100 ISO/IEC 14443 B 101 I-CODE1 standard mode and ISO/IEC 15693 (~52.97 kHz) 110 I-CODE1 fast mode (~26.48 kHz) 111 reserved 2 to 0 TxCoding[2:0] this register defines the bit coding mode and framing during transmission 000 NRZ according to ISO/IEC 14443 B 001 MIFARE, ISO/IEC 14443 A, (Miller coded) 010 reserved 011 reserved 100 I-CODE1 standard mode (1 out of 256 coding) 101 I-CODE1 fast mode (NRZ coding) 110 ISO/IEC 15693 standard mode (1 out of 256 coding) 111 ISO/IEC 15693 fast mode (1 out of 4 coding)CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 62 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.6 ModWidth register Selects the pulse-modulation width. 10.5.3.7 ModWidthSOF register Table 79. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ModWidth[7:0] Access R/W Table 80. ModWidth register bit descriptions Bit Symbol Description 7 to 0 ModWidth[7:0] defines the width of the modulation pulse based on tmod = 2(ModWidth + 1) / fclk Table 81. ModWidthSOF register (address: 16h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ModWidthSOF[7:0] Access R/W Table 82. ModWidthSOF register bit descriptions Bit Symbol Value Description 7 to 0 ModWidthSOF defines the width of the modulation pulse for SOF as tmod = 2(ModWidth + 1) / fclk the register settings are: 3Fh MIFARE and ISO/IEC 14443; modulation width SOF = 9.44 s 3Fh I-CODE1 standard mode; modulation width SOF = 9.44 s 73h I-CODE1 fast mode; modulation width SOF = 18.88 s 3Fh ISO/IEC 15693; modulation width SOF = 9.44 sCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 63 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.8 TypeBFraming Defines the framing for ISO/IEC 14443 B communication. Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol NoTxSOF NoTxEOF EOFWidth CharSpacing[2:0] SOFWidth[1:0] Access R/W R/W R/W R/W R/W Table 84. TypeBFraming register bit descriptions Bit Symbol Value Description 7 NoTxSOF 1 TxCoder suppresses the SOF 0 TxCoder does not suppress SOF 6 NoTxEOF 1 TxCoder suppresses the EOF 0 TxCoder does not suppress the EOF 5 EOFWidth 1 set the EOF to a length to 11 ETU 0 set the EOF to a length of 10 ETU 4 to 2 CharSpacing[2:0] set the EGT length between 0 and 7 ETU 1 to 0 SOFWidth[1:0] 00 sets the SOF to a length to 10 ETU LOW and 2 ETU HIGH 01 sets the SOF to a length of 10 ETU LOW and 3 ETU HIGH 10 sets the SOF to a length of 11 ETU LOW and 2 ETU HIGH 11 sets the SOF to a length of 11 ETU LOW and 3 ETU HIGHCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 64 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.4.2 RxControl1 register Controls receiver operation. Table 85. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SubCPulses[2:0] ISOSelection[1:0] LPOff Gain[1:0] Access R/W R/W R/W R/W Table 86. RxControl1 register bit descriptions Bit Symbol Value Description 7 to 5 SubCPulses[2:0] defines the number of subcarrier pulses for each bit 000 1 pulse for each bit 001 2 pulses for each bit 010 4 pulses for each bit 011 8 pulses for each bit ISO/IEC 14443 A and ISO/IEC 14443 B 100 16 pulses for each bit I-CODE1, ISO/IEC 15693 101 reserved 110 reserved 111 reserved 4 to 3 ISOSelection[1:0] used to select the communication protocol 00 reserved 10 ISO/IEC 14443 A and ISO/IEC 14443 B 01 I-CODE1, ISO/IEC 15693 11 reserved 2 LPOff switches off a low-pass filter at the internal amplifier 1 to 0 Gain[1:0] defines the receiver’s signal voltage gain factor 00 20 dB gain factor 01 24 dB gain factor 10 31 dB gain factor 11 35 dB gain factorCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 65 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4.3 DecoderControl register Controls decoder operation. 10.5.4.4 BitPhase register Selects the bit-phase between transmitter and receiver clock. Table 87. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 RxMultiple ZeroAfterColl RxFraming[1:0] RxInvert 0 RxCoding Access R/W R/W R/W R/W R/W R/W R/W Table 88. DecoderControl register bit descriptions Bit Symbol Value Description 7 0 - this value must not be changed 6 RxMultiple 0 after receiving one frame, the receiver is deactivated 1 enables reception of more than one frame 5 ZeroAfterColl 1 any bits received after a bit-collision are masked to zero. This helps to resolve the anti-collision procedure as defined in ISO/IEC 14443 A 4 to 3 RxFraming[1:0] 00 I-CODE1 01 MIFARE or ISO/IEC 14443 A 10 ISO/IEC 15693 11 ISO/IEC 14443 B 2 RxInvert 0 modulation at the first half-bit results in logic 1 (I-CODE1) 1 modulation at the first half-bit results in logic 0 (ISO/IEC 15693) 1 0 - this value must not be changed 0 RxCoding 0 Manchester encoding 1 BPSK encoding Table 89. BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BitPhase[7:0] Access R/W Table 90. BitPhase register bit descriptions Bit Symbol Description 7 to 0 BitPhase defines the phase relationship between transmitter and receiver clock Remark: The correct value of this register is essential for proper operation.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 66 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. 10.5.4.6 BPSKDemControl Controls BPSK demodulation. Table 91. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MinLevel[3:0] CollLevel[3:0] Access R/W R/W Table 92. RxThreshold register bit descriptions Bit Symbol Description 7 to 4 MinLevel[3:0] the minimum signal strength the decoder will accept. If the signal strength is below this level, it is not evaluated. 3 to 0 CollLevel[3:0] the minimum signal strength the decoder input that must be reached by the weaker half-bit of the Manchester encoded signal to generate a bit-collision (relative to the amplitude of the stronger half-bit) Table 93. BPSKDemControl register (address: 1Dh) reset value: 0001 1110b, 1Eh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol NoRxSOF NoRxEGT NoRxEOF FilterAmpDet TauD[1:0] TauB[1:0] Access R/W R/W R/W R/W R/W R/W Table 94. BPSKDemControl register bit descriptions Bit Symbol Value Description 7 NoRxSOF 1 a missing SOF in the received data stream is ignored and no framing errors are indicated 0 a missing SOF in the received data stream generates framing errors 6 NoRxEGT 1 an EGT which is too short or too long in the received data stream is ignored and no framing errors are indicated 0 an EGT which is too short or too long in the received data stream will cause framing errors 5 NoRxEOF 1 a missing EOF in the received data stream is ignored and no framing errors indicated 0 a missing EOF in the receiving data stream produces framing errors 4 FilterAmpDet - switches on a high-pass filter for amplitude detection 3 to 2 TauD[1:0] - changes the time constant of the internal PLL whilst receiving data 1 to 0 TauB[1:0] - changes the time constant of the internal PLL during data burstsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 67 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. [1] I-clock and Q-clock are 90 phase-shifted from each other. 10.5.4.8 ClockQControl register Controls clock generation for the 90 phase-shifted Q-clock. Table 95. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RcvClkSelI RxAutoPD 0000 DecoderSource[1:0] Access R/W R/W R/W R/W Table 96. RxControl2 register bit descriptions Bit Symbol Value Description 7 RcvClkSelI 1 I-clock is used as the receiver clock[1] 0 Q-clock is used as the receiver clock[1] 6 RxAutoPD 1 receiver circuit is automatically switched on before receiving and switched off afterwards. This can be used to reduce current consumption. 0 receiver is always activated 5 to 2 0000 - these values must not be changed 1 to 0 DecoderSource[1:0] selects the source for the decoder input 00 LOW 01 internal demodulator 10 a subcarrier modulated Manchester encoded signal on pin MFIN 11 a baseband Manchester encoded signal on pin MFIN Table 97. ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ClkQ180Deg ClkQCalib 0 ClkQDelay[4:0] Access R R/W R/W D Table 98. ClockQControl register bit descriptions Bit Symbol Value Description 7 ClkQ180Deg 1 Q-clock is phase-shifted more than 180 compared to the I-clock 0 Q-clock is phase-shifted less than 180 compared to the I-clock 6 ClkQCalib 0 Q-clock is automatically calibrated after the reset phase and after data reception from the card 1 no calibration is performed automatically 5 0 - this value must not be changed 4 to 0 ClkQDelay[4:0] - this register shows the number of delay elements used to generate a 90 phase-shift of the I-clock to obtain the Q-clock. It can be written directly by the microprocessor or by the automatic calibration cycle.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 68 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. 10.5.5.3 ChannelRedundancy register Selects kind and mode of checking the data integrity on the RF channel. Table 99. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RxWait[7:0] Access R/W Table 100. RxWait register bit descriptions Bit Symbol Function 7 to 0 RxWait[7:0] after data transmission, the activation of the receiver is delayed for RxWait bit-clock cycles. During this frame guard time any signal on pin RX is ignored. Table 101. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 CRC3309 CRC8 RxCRCEn TxCRCEn ParityOdd ParityEn Access R/W R/W R/W R/W R/W R/W R/W R/W Table 102. ChannelRedundancy bit descriptions Bit Symbol Value Function 7 to 6 00 - this value must not be changed 5 CRC3309 1 CRC calculation is performed using ISO/IEC 3309 (ISO/IEC 14443 B) and ISO/IEC 15693 0 CRC calculation is performed using ISO/IEC 14443 A and I-CODE1 4 CRC8 1 an 8-bit CRC is calculated 0 a 16-bit CRC is calculated 3 RxCRCEn 1 the last byte(s) of a received frame are interpreted as CRC bytes. If the CRC is correct, the CRC bytes are not passed to the FIFO. If the CRC bytes are incorrect, the CRCErr flag is set. 0 no CRC is expected 2 TxCRCEn 1 a CRC is calculated over the transmitted data and the CRC bytes are appended to the data stream 0 no CRC is transmittedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 69 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] When used with ISO/IEC 14443 A, this bit must be set to logic 1. 10.5.5.4 CRCPresetLSB register LSB of the preset value for the CRC register. [1] To use the ISO/IEC 15693 functionality, the CRCPresetLSB register has to be set to FFh. 10.5.5.5 CRCPresetMSB register MSB of the preset value for the CRC register. 10.5.5.6 TimeSlotPeriod register Defines the time-slot period for I-CODE1 protocol. 1 ParityOdd 1 odd parity is generated or expected[1] 0 even parity is generated or expected 0 ParityEn 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (MIFARE, ISO/IEC 14443 A) 0 no parity bit is inserted or expected (ISO/IEC 14443 B) Table 102. ChannelRedundancy bit descriptions …continued Bit Symbol Value Function Table 103. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCPresetLSB[7:0] Access R/W Table 104. CRCPresetLSB register bit descriptions Bit Symbol Description 7 to 0 CRCPresetLSB[7:0] defines the start value for CRC calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC command (if CRC calculation is enabled)[1]. Table 105. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCPresetMSB[7:0] Access R/W Table 106. CRCPresetMSB bit descriptions Bit Symbol Description 7 to 0 CRCPresetMSB[7:0] defines the starting value for CRC calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC command (if the CRC calculation is enabled) Remark: This register is not relevant if CRC8 is set to logic 1. Table 107. TimeSlotPeriod register (address: 25h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TimeSlotPeriod[7:0] Access R/WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 70 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.5.7 MFOUTSelect register Selects the internal signal applied to pin MFOUT. [1] Only valid for MIFARE and ISO/IEC 14443 A communication at 106 kBd. 10.5.5.8 PreSet27 register Table 108. TimeSlotPeriod register bit descriptions Bit Symbol Description 7 to 0 TimeSlotPeriod[7:0] defines the time between automatically transmitted frames. To send a Quit frame using the I-CODE1 protocol it is necessary to relate to the beginning of the command frame. The TimeSlotPeriod starts at the end of the command transmission. See Section 9.5.1.5 on page 26 for additional information. Table 109. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000 TimeSlotPeriodMSB 0 MFOUTSelect[2:0] Access R/W R/W R/W R/W R/W R/W Table 110. MFOUTSelect register bit descriptions Bit Symbol Value Description 7 to 5 000 - these values must not be changed 4 TimeSlotPeriodMSB - MSB of value TimeSlotPeriod; see Table 107 on page 69 for more detailed information 3 0 - this value must not be changed 2 to 0 MFOUTSelect[2:0] defines which signal is routed to pin MFOUT: 000 constant LOW 001 constant HIGH 010 modulation signal (envelope) from the internal encoder, (Miller coded) 011 serial data stream, not Miller encoded 100 output signal of the energy carrier demodulator (card modulation signal)[1] 101 output signal of the subcarrier demodulator (Manchester encoded card signal)[1] 110 reserved 111 reserved Table 111. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 71 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. 10.5.6.3 TimerClock register Selects the divider for the timer clock. Table 112. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 WaterLevel[5:0] Access R/W R/W R/W Table 113. FIFOLevel register bit descriptions Bit Symbol Description 7 to 6 00 these values must not be changed 5 to 0 WaterLevel[5:0] defines, the warning level of a FIFO buffer overflow or underflow: HiAlert is set to logic 1 if the remaining FIFO buffer space is equal to, or less than, WaterLevel[5:0] bits in the FIFO buffer. LoAlert is set to logic 1 if equal to, or less than, WaterLevel[5:0] bits in the FIFO buffer. Table 114. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 TAutoRestart TPreScaler[4:0] Access RW RW RW RW Table 115. TimerClock register bit descriptions Bit Symbol Value Function 7 to 6 00 - these values must not be changed 5 TAutoRestart 1 the timer automatically restarts its countdown from the TReloadValue[7:0] instead of counting down to zero 0 the timer decrements to zero and register InterruptIrq TimerIRq bit is set to logic 1 4 to 0 TPreScaler[4:0] - defines the timer clock frequency (fTimerClock). The TPreScaler[4:0] can be adjusted from 0 to 21. The following formula is used to calculate the TimerClock frequency (fTimerClock): fTimerClock = 13.56 MHz / 2TPreScaler [MHz]CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 72 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. 10.5.6.5 TimerReload register Defines the preset value for the timer. Table 116. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin Access R/W R/W R/W R/W R/W Table 117. TimerControl register bit descriptions Bit Symbol Value Description 7 to 4 0000 - these values must not be changed 3 TStopRxEnd 1 the timer automatically stops when data reception ends 0 the timer is not influenced by this condition 2 TStopRxBegin 1 the timer automatically stops when the first valid bit is received 0 the timer is not influenced by this condition 1 TStartTxEnd 1 the timer automatically starts when data transmission ends. If the timer is already running, the timer restarts by loading TReloadValue[7:0] into the timer. 0 the timer is not influenced by this condition 0 TStartTxBegin 1 the timer automatically starts when the first bit is transmitted. If the timer is already running, the timer restarts by loading TReloadValue[7:0] into the timer. 0 the timer is not influenced by this condition Table 118. TimerReload register (address: 2Ch) reset value: 0000 1010b, 0Ah bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TReloadValue[7:0] Access R/W Table 119. TimerReload register bit descriptions Bit Symbol Description 7 to 0 TReloadValue[7:0] on a start event, the timer loads the TReloadValue[7:0] value. Changing this register only affects the timer on the next start event. If TReloadValue[7:0] is set to logic 0 the timer cannot start.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 73 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. 10.5.6.7 PreSet2E register 10.5.6.8 PreSet2F register 10.5.7 Page 6: reserved 10.5.7.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h Remark: These registers are reserved for future use. Table 120. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000000 IRQInv IRQPushPull Access R/W R/W R/W Table 121. IRQPinConfig register bit descriptions Bit Symbol Value Description 7 to 2 000000 - these values must not be changed 1 IRQInv 1 inverts the signal on pin IRQ with respect to bit IRq 0 the signal on pin IRQ is not inverted and is the same as bit IRq 0 IRQPushPull 1 pin IRQ functions as a standard CMOS output pad 0 pin IRQ functions as an open-drain output pad Table 122. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 123. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 124. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access R/W R/W R/W R/W R/W R/W R/W R/WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 74 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.8.2 Reserved register 39h Remark: This register is reserved for future use. 10.5.8.3 TestAnaSelect register Selects analog test signals. Table 125. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 126. TestAnaSelect register (address: 3Ah) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TestAnaOutSel[4:0] Access W W Table 127. TestAnaSelect bit descriptions Bit Symbol Value Description 7 to 4 0000 - these values must not be changed 3 to 0 TestAnaOutSel[4:0] selects the internal analog signal to be routed to pin AUX. See Section 15.2.2 on page 112 for detailed information. The settings are as follows: 0 VMID 1 Vbandgap 2 VRxFollI 3 VRxFollQ 4 VRxAmpI 5 VRxAmpQ 6 VCorrNI 7 VCorrNQ 8 VCorrDI 9 VCorrDQ A VEvalL B VEvalR C VTemp D reserved E reserved F reservedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 75 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.8.4 Reserved register 3Bh Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Remark: This register is reserved for future use. 10.5.8.6 TestDigiSelect register Selects digital test mode. Table 128. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 129. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 130. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SignalToMFOUT TestDigiSignalSel[6:0] Access W W Table 131. TestDigiSelect register bit descriptions Bit Symbol Value Description 7 SignalToMFOUT 1 overrules the MFOUTSelect[2:0] setting and routes the digital test signal defined with the TestDigiSignalSel[6:0] bits to pin MFOUT 0 MFOUTSelect[2:0] defines the signal on pin MFOUT 6 to 0 TestDigiSignalSel[6:0] - selects the digital test signal to be routed to pin MFOUT. Refer to Section 15.2.3 on page 113 for detailed information. The following lists the signal names for the TestDigiSignalSel[6:0] addresses: F4h s_data E4h s_valid D4h s_coll C4h s_clock B5h rd_sync A5h wr_sync 96h int_clock 83h BPSK_out E2h BPSK_sigCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 76 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.8.7 Reserved registers 3Eh, 3Fh Remark: This register is reserved for future use. 11. CLRC632 command set CLRC632 operation is determined by an internal state machine capable of performing a command set. The commands can be started by writing the command code to the Command register. Arguments and/or data necessary to process a command are mainly exchanged using the FIFO buffer. • Each command needing a data stream (or data byte stream) as an input immediately processes the data in the FIFO buffer • Each command that requires arguments only starts processing when it has received the correct number of arguments from the FIFO buffer • The FIFO buffer is not automatically cleared at the start of a command. It is, therefore, possible to write command arguments and/or the data bytes into the FIFO buffer before starting a command. • Each command (except the StartUp command) can be interrupted by the microprocessor writing a new command code to the Command register e.g. the Idle command. 11.1 CLRC632 command overview Table 132. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 133. CLRC632 commands overview Command Value Action FIFO communication Arguments and data sent Data received StartUp 3Fh runs the reset and initialization phase. See Section 11.1.2 on page 78. Remark: This command can only be activated by Power-On or Hard resets. - - Idle 00h no action; cancels execution of the current command. See Section 11.1.3 on page 78 - - Transmit 1Ah transmits data from the FIFO buffer to the card. See Section 11.2.1 on page 79 data stream - Receive 16h activates receiver circuitry. Before the receiver starts, the state machine waits until the time defined in the RxWait register has elapsed. See Section 11.2.2 on page 82. Remark: This command may be used for test purposes only, since there is no timing relationship to the Transmit command. - data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 77 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] This command is the combination of the Transmit and Receive commands. [2] Relates to MIFARE Mini/MIFARE 1K/MIFARE 4K security. Transceive[1] 1Eh transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11.2.3 on page 85. data stream data stream WriteE2 01h reads data from the FIFO buffer and writes it to the EEPROM. See Section 11.4.1 on page 93. start address LSB - start address MSB data byte stream ReadE2 03h reads data from the EEPROM and sends it to the FIFO buffer. See Section 11.4.2 on page 95. Remark: Keys cannot be read back start address LSB data bytes start address MSB number of data bytes LoadKeyE2 0Bh copies a key from the EEPROM into the key buffer[2] See Section 11.7.1 on page 97. start address LSB - start address MSB LoadKey 19h reads a key from the FIFO buffer and loads it into the key buffer[2]. See Section 11.7.2 on page 97. Remark: The key has to be prepared in a specific format (refer to Section 9.2.3.1 “Key format” on page 18) byte 0 LSB - byte 1 … byte 10 byte 11 MSB Authent1 0Ch performs the first part of card authentication using the Crypto1 algorithm[2]. See Section 11.7.3 on page 98. card Authent1 command - card block address card serial number LSB card serial number byte 1 card serial number byte 2 card serial number MSB Authent2 14h performs the second part of card authentication using the Crypto1 algorithm[2]. See Section 11.7.4 on page 98. - - LoadConfig 07h reads data from EEPROM and initializes the CLRC632 registers. See Section 11.5.1 on page 95. start address LSB - start address MSB CalcCRC 12h activates the CRC coprocessor Remark: The result of the CRC calculation is read from the CRCResultLSB and CRCResultMSB registers. See Section 11.5.2 on page 96. data byte stream - Table 133. CLRC632 commands overview …continued Command Value Action FIFO communication Arguments and data sent Data receivedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 78 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.1.1 Basic states 11.1.2 StartUp command 3Fh Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data. It cannot be activated by the microprocessor but is automatically started after one of the following events: • Power-On Reset (POR) caused by power-up on pin DVDD • POR caused by power-up on pin AVDD • Negative edge on pin RSTPD The reset phase comprises an asynchronous reset and configuration of certain register bits. The initialization phase configures several registers with values stored in the EEPROM. When the StartUp command finishes, the Idle command is automatically executed. Remark: • The microprocessor must not write to the CLRC632 while it is still executing the StartUp command. To avoid this, the microprocessor polls for the Idle command to determine when the initialization phase has finished; see Section 9.7.4 on page 30. • When the StartUp command is active, it is only possible to read from the Page 0 register. • The StartUp command cannot be interrupted by the microprocessor. 11.1.3 Idle command 00h The Idle command switches the CLRC632 to its inactive state where it waits for the next command. It does not need or return, any data. The device automatically enters the idle state when a command finishes. When this happens, the CLRC632 sends an interrupt request by setting bit IdleIRq. When triggered by the microprocessor, the Idle command can be used to stop execution of all other commands (except the StartUp command) but this does not generate an interrupt request (IdleIRq). Remark: Stopping command execution with the Idle command does not clear the FIFO buffer. Table 134. StartUp command 3Fh Command Value Action Arguments and data Returned data StartUp 3Fh runs the reset and initialization phase - - Table 135. Idle command 00h Command Value Action Arguments and data Returned data Idle 00h no action; cancels current command execution - -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 79 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2 Commands for ISO/IEC 14443 A card communication The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and I-CODE1 compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.2.1 to Section 11.2.5 describe the command set for ISO/IEC 14443 A card communication and related communication protocols. 11.2.1 Transmit command 1Ah The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It does not return any data. The Transmit command can only be started by the microprocessor. 11.2.1.1 Using the Transmit command To transmit data, one of the following sequences can be used: 1. All data to be transmitted to the card is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. Remark: This is possible for transmission of a data stream up to 64 bytes. 2. The command code for the Transmit command is stored in the Command register. Since there is not any data available in the FIFO buffer, the command is only enabled but transmission is not activated. Data transmission starts when the first data byte is written to the FIFO buffer. To generate a continuous data stream on the RF interface, the microprocessor must write the subsequent data bytes into the FIFO buffer in time. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. 3. Part of the data transmitted to the card is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. While the Transmit command is active, the microprocessor can send further data to the FIFO buffer. This is then appended by the transmitter to the transmitted data stream. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. When the transmitter requests the next data byte to ensure the data stream on the RF interface is continuous and the FIFO buffer is empty, the Transmit command automatically terminates. This causes the internal state machine to change its state from transmit to idle. When the data transmission to the card is finished, the TxIRq flag is set by the CLRC632 to indicate to the microprocessor transmission is complete. Remark: If the microprocessor overwrites the transmit code in the Command register with another command, transmission stops immediately on the next clock cycle. This can produce output signals that are not in accordance with ISO/IEC 14443 A. Table 136. Transmit command 1Ah Command Value Action Arguments and data Returned data Transmit 1Ah transmits data from FIFO buffer to card data stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 80 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bit; see Section 11.2.4 on page 85. Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is calculated and appended to the data stream. The CRC is calculated according to the settings in the ChannelRedundancy register. Parity generation is handled according to the ChannelRedundancy register ParityEn and ParityOdd bits settings. 11.2.1.3 Transmission of bit oriented frames The transmitter can be configured to send an incomplete last byte. To achieve this the BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This is shown in Figure 16. Figure 16 shows the data stream if bit ParityEn is set in the ChannelRedundancy register. All fully transmitted bytes are followed by a parity check bit but the incomplete byte is not followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are automatically cleared. Remark: If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit. 11.2.1.4 Transmission of frames with more than 64 bytes To generate frames of more than 64 bytes, the microprocessor must write data to the FIFO buffer while the Transmit command is active. The state machine checks the FIFO buffer status when it starts transmitting the last bit of the data stream; the check time is marked in Figure 17 with arrows. Fig 16. Transmitting bit oriented frames 001aak618 TxLastBits = 0 TxLastBits = 7 TxLastBits = 1 SOF 0 7 P 0 7 P SOF SOF EOF EOF EOF 0 7 P 0 6 0 7 P 0CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 81 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the RF interface. If the internal accept further data signal is logic 0, the transmission terminates. All data written to the FIFO buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the FIFO buffer. Remark: If parity generation is enabled (ParityEn = logic 1), the parity bit is the last bit transmitted. This delays the accept further data signal by a duration of one bit. If the TxLastBits[2:0] bits are not zero, the last byte is not transmitted completely. Only the number of bits set by TxLastBits[2:0], starting with the least significant bit are transmitted. This means that the internal state machine has to check the FIFO buffer status at an earlier point in time; see Figure 18. Since in this example TxLastBits[2:0] = 4, transmission stops after bit 3 is transmitted and the frame is completed with an EOF, if configured. Fig 17. Timing for transmitting byte oriented frames Fig 18. Timing for transmitting bit oriented frames 001aak619 accept further data check FIFO empty TxData FIFO empty FIFOLength[6:0] 01h 00h TxLastBits[2:0] TxLastBits = 0 7 0 7 0 7 001aak620 accept further data check FIFO empty TxData FIFO empty FIFOLength[6:0] 01h 00h 01h 00h TxLastBits[2:0] TxLastBits = 4 NWR (FIFO data) 4 7 0 3 4 7 0 3CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 82 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Figure 18 also shows write access to the FIFOData register just before the FIFO buffer’s status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function. This function verifies FIFO empty for one bit duration before the last expected bit transmission. 11.2.2 Receive command 16h The Receive command activates the receiver circuitry. All data received from the RF interface is written to the FIFO buffer. The Receive command can be started either using the microprocessor or automatically during execution of the Transceive command. Remark: This command can only be used for test purposes since there is no timing relationship to the Transmit command. 11.2.2.1 Using the Receive command After starting the Receive command, the internal state machine decrements to the RxWait register value on every bit-clock. The analog receiver circuitry is prepared and activated from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming signal at the RF interface. When the signal strength reaches a level higher than the RxThreshold register MinLevel[3:0] bits value, it starts decoding. The decoder stops when the signal can longer be detected on the receiver input pin RX. The decoder sets bit RxIRq indicating receive termination. The different phases of the receive sequence are monitored using the PrimaryStatus register ModemState[2:0] bits; see Section 11.2.4 on page 85. Remark: Since the counter values from 3 to 0 are needed to initialize the analog receiver circuitry, the minimum value for RxWait[7:0] is 3. 11.2.2.2 RF channel redundancy and framing The decoder expects the SOF pattern at the beginning of each data stream. When the SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. Every completed byte is forwarded to the FIFO buffer. Table 137. Transmission of frames of more than 64 bytes Frame definition Verification at: 8-bit with parity 8th bit 8-bit without parity 7th bit x-bit without parity (x  1)th bit Table 138. Receive command 16h Command Value Action Arguments and data Returned data Receive 16h activates receiver circuitry - data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 83 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution If an EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected. The CRC block can be one byte or two bytes depending on the ChannelRedundancy register CRC8 bit setting. Remark: If the CRC block received is correct, it is not sent to the FIFO buffer. This is realized by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the CRC fails, all received bytes are sent to the FIFO buffer including the faulty CRC. If ParityEn is set in the ChannelRedundancy register, a parity bit is expected after each byte. If ParityOdd = logic 1, the expected parity is odd, otherwise even parity is expected. 11.2.2.3 Collision detection If more than one card is within the RF field during the card selection phase, they both respond simultaneously. The CLRC632 supports the algorithm defined in ISO/IEC 14443 A to resolve card serial number data collisions by performing the anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions. Bit-collision detection is supported by the Manchester coding bit encoding scheme used in the CLRC632. If in the first and second half-bit of a subcarrier, modulation is detected, instead of forwarding a 1-bit or 0-bit, a bit-collision is indicated. The CLRC632 uses the RxThreshold register CollLevel[3:0] bits setting to distinguish between a 1-bit or 0-bit and a bit-collision. If the amplitude of the half-bit with smaller amplitude is larger than that defined by the CollLevel[3:0] bits, the CLRC632 flags a bit-collision using the error flag CollErr. If a bit-collision is detected in a parity bit, the ParityErr flag is set. On a detected collision, the receiver continues receiving the incoming data stream. In the case of a bit-collision, the decoder sends logic 1 at the collision position. Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state has been detected. This feature makes it easier for the control software to perform the anti-collision procedure as defined in ISO/IEC 14443 A. When the first bit collision in a frame is detected, the bit-collision position is stored in the CollPos register. Table 139 shows the collision positions.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 84 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur after bit-collisions in the data bits. If a collision is detected in the SOF, a frame error is flagged and no data is sent to the FIFO buffer. In this case, the receiver continues to monitor the incoming signal. It generates the correct notifications to the microprocessor when the end of the faulty input stream is detected. This helps the microprocessor to determine when it is next allowed to send data to the card. 11.2.2.4 Receiving bit oriented frames The receiver can manage byte streams with incomplete bytes which result in bit-oriented frames. To support this, the following values may be used: • BitFraming register’s RxAlign[2:0] bits select a bit offset for the first incoming byte. For example, if RxAlign[2:0] = 3, the first 5 bits received are forwarded to the FIFO buffer. Further bits are packed into bytes and forwarded. After reception, RxAlign[2:0] is automatically cleared. If RxAlign[2:0] = logic 0, all incoming bits are packed into one byte. • RxLastBits[2:0] returns the number of bits valid in the last received byte. For example, if RxLastBits[2:0] evaluates to 5 bits at the end of the received command, the 5 least significant bits are valid. If the last byte is complete, RxLastBits[2:0] evaluates to zero. RxLastBits[2:0] is only valid if a frame error is not indicated by the FramingErr flag. If RxAlign[2:0] is not zero and ParityEn is active, the first parity bit is ignored and not checked. 11.2.2.5 Communication errors The events which can set error flags are shown in Table 140. Table 139. Return values for bit-collision positions Collision in bit CollPos register value (Decimal) SOF 0 Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1 … … Most Significant Bit (MSB) of the LSByte 8 LSB of second byte 9 … … MSB of second byte 16 LSB of third byte 17 … … Table 140. Communication error table Cause Flag bit Received data did not start with the SOF pattern FramingErr CRC block is not equal to the expected value CRCErr Received data is shorter than the CRC block CRCErr The parity bit is not equal to the expected value (i.e. a bit-collision, not parity) ParityErr A bit-collision is detected CollErrCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 85 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2.3 Transceive command 1Eh The Transceive command first executes the Transmit command (see Section 11.2.1 on page 79) and then starts the Receive command (see Section 11.2.2 on page 82). All data transmitted is sent using the FIFO buffer and all data received is written to the FIFO buffer. The Transceive command can only be started by the microprocessor. Remark: To adjust the timing relationship between transmitting and receiving, use the RxWait register. This register is used to define the time delay between the last bit transmitted and activation of the receiver. In addition, the BitPhase register determines the phase-shift between the transmitter and receiver clock. 11.2.4 States of the card communication The status of the transmitter and receiver state machine can be read from bits ModemState[2:0] in the PrimaryStatus register. The assignment of ModemState[2:0] to the internal action is shown in Table 142. Table 141. Transceive command 1Eh Command Value Action Arguments and data Returned data Transceive 1Eh transmits data from FIFO buffer to the card and then automatically activates the receiver data stream data stream Table 142. Meaning of ModemState ModemState [2:0] State Description 000 Idle transmitter and/or receiver are not operating 001 TxSOF transmitting the SOF pattern 010 TxData transmitting data from the FIFO buffer (or redundancy CRC check bits) 011 TxEOF transmitting the EOF pattern 100 GoToRx1 intermediate state passed, when receiver starts GoToRx2 intermediate state passed, when receiver finishes 101 PrepareRx waiting until the RxWait register time period expires 110 AwaitingRx receiver activated; waiting for an input signal on pin RXCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 86 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2.5 Card communication state diagram Fig 19. Card communication state diagram 001aak621 end of receive frame and RxMultiple = 0 RxMultiple = 1 EOF transmitted and command = Transceive FIFO not empty and command = Transmit or Transceive command = Receive COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE SET COMMAND REGISTER = IDLE (000) Awaiting Rx (110) RECEIVING (111) GoToRx2 (100) Prepare Rx (101) GoToRx1 (100) TxEOF (011) TxData (010) TxSOF (001) IDLE (000) SOF transmitted next bit clock data transmitted RxWaitC[7:0] = 0 EOF transmitted and command = Transmit signal strength > MinLevel[3:0] frame receivedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 87 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3 I-CODE1 and ISO/IEC 15693 label communication commands The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and I-CODE1 compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.3.1 to Section 11.3.5 give an overview of the command set for I-CODE1 and ISO/IEC 15693 card communication and related communication protocols. 11.3.1 Transmit command 1Ah The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It does not return any data. The Transmit command can only be started by the microprocessor. 11.3.1.1 Using the Transmit command To transmit data, one of the following sequences can be used: 1. All data to be transmitted to the label is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. Remark: This is possible for transmission of a data stream up to 64 bytes long. 2. The command code for the Transmit command is stored in the Command register. Since there is not any data available in the FIFO buffer, the command is only enabled but transmission is not triggered. Data transmission starts when the first data byte is written to the FIFO buffer. To generate a continuous data stream on the RF interface, the microprocessor must write the subsequent data bytes into the FIFO buffer in time. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. 3. Part of the data transmitted to the label is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. While the Transmit command is active, the microprocessor can send further data to the FIFO buffer. This is then appended by the transmitter to the transmitted data stream. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. When the transmitter requests the next data byte, to ensure that the data stream on the RF interface is continuous and the FIFO buffer is empty, the Transmit command automatically terminates. This causes the internal state machine to change its state from transmit to idle. When the data transmission to the label is finished, the TxIRq flag is set by the CLRC632 to indicate transmission is complete to the microprocessor. Remark: If the microprocessor overwrites the transmit code in the Command register with another command, transmission stops immediately on the next clock cycle. This can produce output signals that do not comply with the ISO/IEC 15693 standard or the I-CODE1 protocol. Table 143. Transmit command 1Ah Command Value Action Arguments and data Returned data Transmit 1Ah transmits data from FIFO buffer to the label data stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 88 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3.1.2 RF channel redundancy and framing Each transmitted ISO/IEC 15693 frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. All I-CODE1 command frames consists of a start pulse followed by the data stream. The I-CODE1 commands have a fixed length and do not need an EOF. The phases of the transmission sequence are monitored using the PrimaryStatus register’s ModemState[2:0] bits; see Section 11.2.4 on page 85. Depending on the ChannelRedundancy register TxCRCEn bit setting, the CRC is calculated and appended to the data stream. The CRC is calculated using the ChannelRedundancy register settings. 11.3.1.3 Transmission of frames of more than 64 bytes To generate frames of more than 64 bytes of data, the microprocessor has to write data to the FIFO buffer while the Transmit command is active. The state machine checks the FIFO buffer status when it starts transmitting the last bit of the data stream (the check time is shown in Figure 20 with arrows). As long as the internal accept further data signal is logic 1 further data can be written to the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the RF interface. If the internal accept further data signal is logic 0 the transmission terminates. All data written to the FIFO buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the FIFO buffer. 11.3.2 Receive command 16h The Receive command activates the receiver circuitry. All data received from the RF interface is written to the FIFO buffer. The Receive command can be started either by the microprocessor or automatically during execution of the Transceive command. Fig 20. Timing for transmitting byte oriented frames 001aak619 accept further data check FIFO empty TxData FIFO empty FIFOLength[6:0] 01h 00h TxLastBits[2:0] TxLastBits = 0 7 0 7 0 7 Table 144. Receive command 16h Command Value Action Arguments and data Returned data Receive 16h activates receiver circuitry - data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 89 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: This command may be used for test purposes only, since there is no timing relation to the Transmit command. 11.3.2.1 Using the Receive command After starting the Receive command the internal state machine decrements the RxWait register value on every bit-clock. The analog receiver circuitry is prepared and activated from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming signal using the RF interface. If the signal strength reaches a level above the value set in the RxThreshold register’s MinLevel[3:0] bits, the receiver starts decoding. The decoder stops when the signal cannot be detected on the receiver input pin RX. The decoder sets the RxIRq flag bit to indicate that the operation has finished. The receive sequence phases can be monitored using bits ModemStatus[2:0] in the PrimaryStatus register; see Section 11.2.4 on page 85. Remark: The minimum value for RxWait[7:0] is 3 because counter values from 3 to 0 are needed to initialize the analog receiver circuitry. 11.3.2.2 RF channel redundancy and framing In ISO/IEC 15693 mode, the decoder expects a SOF pattern at the beginning of each data stream. When a SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. If an EOF pattern (ISO/IEC 15693) is detected or the signal strength falls below the MinLevel value, the receiver and the decoder stop, the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). In I-CODE1 mode, the decoder does not expect a SOF pattern at the beginning of each data stream. It activates the serial-to-parallel converter on the first received bit of the data. Every full byte is then sent to the FIFO buffer. If ChannelRedundancy register bit RxCRCEn is set a CRC block is expected. The CRC block may be one byte or two bytes based on the ChannelRedundancy register’s CRC8 bit. Remark: If it is correct, the CRC block is not forwarded to the FIFO buffer. The CRC is realized by shifting the incoming data bytes through an internal buffer of one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the CRC fails, all bytes received are forwarded to the FIFO buffer (including the faulty CRC). 11.3.2.3 Collision detection If more than one label is within the RF field during the label selection phase, they will respond simultaneously. The CLRC632 supports the algorithm defined in ISO/IEC 15693 as well as the I-CODE1 anti-collision algorithm to resolve label serial number data collisions using the anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions. Bit-collision detection is supported by the Manchester coding bit encoding scheme used. If in the first and second half-bit of a bit a subcarrier modulation is detected, instead of forwarding a 1-bit or a 0-bit, a bit-collision is flagged.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 90 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution To distinguish between a 1-bit or 0-bit from a bit-collision, the RxThreshold register’s CollLevel[3:0] value is used. If the amplitude of the half-bit with smaller amplitude is larger than defined by CollLevel[3:0], a bit-collision is flagged by setting the CollErr error flag. The receiver continues receiving the incoming data stream independently from the detected collision. In case of a bit-collision, the decoder forwards logic 1 at the collision position. Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless of whether a bit-collision or an unequivocal state has been detected. This feature makes it easier for the software to carry out the anti-collision procedure as defined in ISO/IEC 15693. When the first bit-collision in a frame is detected, the bit position of the collision is stored in the CollPos register. The collision positions are shown in Table 145. If a collision is detected in the SOF, a frame error is reported and no data is sent to the FIFO buffer. In this case the receiver continues to monitor the incoming signal and generates the correct notifications to the microprocessor when the end of the faulty input stream is detected. This helps the microprocessor to determine the time when it is next allowed to send data to the label. 11.3.2.4 Communication errors Table 146 shows the events that set error flags. Table 145. Return values for bit-collision positions Collision in bit CollPos register value (Decimal) SOF 0 Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1 … … Most Significant Bit (MSB) of the LSByte 8 LSB of second byte 9 … … MSB of second byte 16 LSB of third byte 17 … … Table 146. Communication error table Cause Bit set Received data did not start with a SOF pattern FramingErr CRC block is not equal to the expected value CRCErr Received data is shorter than the CRC block CRCErr A collision is detected CollErrCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 91 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3.3 Transceive command 1Eh The Transceive command first executes the Transmit command (see Section 11.2.1 on page 79) and then starts the Receive command (see Section 11.2.2 on page 82). All data to be transmitted is sent using the FIFO buffer and all received data is written to the FIFO buffer. The Transceive command can be started only by the microprocessor. Remark: To adjust the timing relationship between transmitting and receiving, use the RxWait register. This enables the time delay from the last bit transmitted until the receiver is activated to be defined. The BitPhase register is used to set-up the phase-shift between the transmitter and the receiver clock. 11.3.4 Label communication states The status of the transmitter and receiver state machine can be read from the PrimaryStatus register ModemState[2:0] bits. The assignment of ModemState[2:0] to the internal action is shown in Table 148. Table 147. Transceive command 1Eh Command Value Action Arguments and data Returned data Transceive 1Eh transmits data from FIFO buffer to the label and then activates the receiver data stream data stream Table 148. ModemState values ModemState [2:0] Name Description 000 Idle transmitter and/or receiver are not operating 001 TxSOF transmitting the start of frame pattern 010 TxData transmitting data from the FIFO buffer (or CRC check bits) 011 TxEOF transmitting the end of frame pattern 100 GoToRx1 intermediate state passed, when receiver starts GoToRx2 intermediate state passed, when receiver finishes 101 PrepareRx waiting until the RxWait register wait time has elapsed 110 AwaitingRx receiver activated; awaiting an input signal on pin RX 111 Receiving receiving dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 92 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3.5 Label communication state diagram (1) I-CODE1 does not have a SOF and an EOF. Fig 21. Label communication state diagram 001aak622 end of receive frame and RxMultiple = 0 time slot period = 0 RxMultiple = 1 time slot period > 0 time slot trigger and data FIFO preparing to send the quit value EOF transmitted and command = Transceive FIFO not empty and command = Transmit or Transceive command = Receive COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE SET COMMAND REGISTER = IDLE (000) Awaiting Rx (110) RECEIVING (111) GoToRx2 (100) Prepare Rx (101) GoToRx1 (100) TxEOF (011) TxData (010) TxSOF (001) IDLE (000) IDLE (000) SOF transmitted next bit clock data transmitted RxWaitC[7:0] = 0 EOF transmitted and command = Transmit signal strength > MinLevel[3:0] frame received RxMultiple = 0 time slot period > 0 time slot trigger and FIFO dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 93 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.4 EEPROM commands 11.4.1 WriteE2 command 01h The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address. Any further bytes are interpreted as data bytes and are programmed into the EEPROM, starting from the given EEPROM start byte address. This command does not return any data. The WriteE2 command can only be started by the microprocessor. It will not stop automatically but has to be stopped explicitly by the microprocessor by issuing the Idle command. 11.4.1.1 Programming process One byte up to 16-byte can be programmed into the EEPROM during a single programming cycle. The time needed is approximately 5.8 ms. The state machine copies all the prepared data bytes to the FIFO buffer and then to the EEPROM input buffer. The internal EEPROM input buffer is 16 bytes long which is equal to the block size of the EEPROM. A programming cycle is started if the last position of the EEPROM input buffer is written or if the last byte of the FIFO buffer has been read. The E2Ready flag remains logic 0 when there are unprocessed bytes in the FIFO buffer or the EEPROM programming cycle is still in progress. When all the data from the FIFO buffer are programmed into the EEPROM, the E2Ready flag is set to logic 1. Together with the rising edge of E2Ready the TxIRq interrupt request flag shows logic 1. This can be used to generate an interrupt when programming of all data is finished. Remark: During the E2PROM programming indicated by E2Ready = logic 0, the WriteE2 command cannot be stopped using any other command. Once E2Ready = logic 1, the WriteE2 command can be stopped by the microprocessor by sending the Idle command. Table 149. WriteE2 command 01h Command Value Action FIFO Arguments and data Returned data WriteE2 01h get data from FIFO buffer and write it to the EEPROM start address LSB - start address MSB - data byte stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 94 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.4.1.2 Timing diagram Figure 22 shows programming five bytes into the EEPROM. Assuming that the CLRC632 finds and reads byte 0 before the microprocessor is able to write byte 1 (tprog,del = 300 ns). This causes the CLRC632 to start the programming cycle (tprog), which takes approximately 5.8 ms to complete. In the meantime, the microprocessor stores byte 1 to byte 4 in the FIFO buffer. If the EEPROM start byte address is 16Ch then byte 0 is stored at that address. The CLRC632 copies the subsequent data bytes into the EEPROM input buffer. Whilst copying byte 3, it detects that this data byte has to be programmed at the EEPROM byte address 16Fh. As this is the end of the memory block, the CLRC632 automatically starts a programming cycle. Next, byte 4 is programmed at the EEPROM byte address 170h. As this is the last data byte, the E2Ready and TxIRq flags are set indicating the end of the EEPROM programming activity. Although all data has been programmed into the E2PROM, the CLRC632 stays in the WriteE2 command. Writing more data to the FIFO buffer would lead to another EEPROM programming cycle continuing from EEPROM byte address 171h. The command is stopped using the Idle command. 11.4.1.3 WriteE2 command error flags Programming is restricted for EEPROM block 0 (EEPROM byte address 00h to 0Fh). If you program these addresses, the AccessErr flag is set and a programming cycle is not started. Addresses above 1FFh are taken modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. Fig 22. EEPROM programming timing diagram 001aak623 NWR data WriteE2 command active EEPROM programming E2Ready TxIRq write E2 addr LSB addr MSB byte 0 byte 1 tprog,del byte 2 byte 3 byte 4 programming byte 0 tprog programming byte 1, byte 2 and byte 3 tprog programming byte 4 tprog Idle commandCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 95 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.4.2 ReadE2 command 03h The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned. When all three argument bytes are available in the FIFO buffer, the specified number of data bytes is copied from the EEPROM into the FIFO buffer, starting from the given EEPROM starting byte address. The ReadE2 command can only be triggered by the microprocessor and it automatically stops when all data has been copied. 11.4.2.1 ReadE2 command error flags Reading is restricted to EEPROM blocks 8h to 1Fh (key memory area). Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.5 Diverse commands 11.5.1 LoadConfig command 07h The LoadConfig command interprets the first two bytes found in the FIFO buffer as the EEPROM starting byte address. When the two argument bytes are available in the FIFO buffer, 32 bytes from the EEPROM are copied into the Control and other relevant registers, starting at the EEPROM starting byte address. The LoadConfig command can only be started by the microprocessor and it automatically stops when all relevant registers have been copied. 11.5.1.1 Register assignment The 32 bytes of EEPROM content are written to the CLRC632 registers 10h to register 2Fh; see Section 9.2 on page 12 for the EEPROM memory organization. Remark: The procedure for the register assignment is the same as it is for the startup initialization (see Section 9.7.3 on page 30). The difference is, the EEPROM starting byte address for the startup initialization is fixed to 10h (block 1, byte 0). However, it can be chosen with the LoadConfig command. Table 150. ReadE2 command 03h Command Value Action Arguments Returned data ReadE2 03h reads EEPROM data and stores it in the FIFO buffer start address LSB data bytes start address MSB number of data bytes Table 151. LoadConfig command 07h Command Value Action Arguments and data Returned data LoadConfig 07h reads data from EEPROM and initializes the registers start address LSB - start address MSB -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 96 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.5.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.5.2 CalcCRC command 12h The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the CRC coprocessor. All data stored in the FIFO buffer before the command is started is processed. This command does not return any data to the FIFO buffer but the content of the CRC can be read using the CRCResultLSB and CRCResultMSB registers. The CalcCRC command can only be started by the microprocessor and it does not automatically stop. It must be stopped by the microprocessor sending the Idle command. If the FIFO buffer is empty, the CalcCRC command waits for further input before proceeding. 11.5.2.1 CRC coprocessor settings Table 153 shows the parameters that can be configured for the CRC coprocessor. The CRC polynomial for the 8-bit CRC is fixed to x8 + x4 + x3 + x2 + 1. The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1. 11.5.2.2 CRC coprocessor status flags The CRCReady status flag indicates that the CRC coprocessor has finished processing all the data bytes in the FIFO buffer. When the CRCReady flag is set to logic 1, an interrupt is requested which sets the TxIRq flag. This supports interrupt driven use of the CRC coprocessor. When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC validity for the processed data. Table 152. CalcCRC command 12h Command Value Action Arguments and data Returned data CalcCRC 12h activates the CRC coprocessor data byte stream - Table 153. CRC coprocessor parameters Parameter Value Bit Register CRC register length 8-bit or 16-bit CRC CRC8 ChannelRedundancy CRC algorithm ISO/IEC 14443 A or ISO/IEC 3309 CRC3309 ChannelRedundancy CRC preset value any CRCPresetLSB CRCPresetLSB CRCPresetMSB CRCPresetMSBCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 97 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.6 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. 11.7 MIFARE security commands 11.7.1 LoadKeyE2 command 0Bh The LoadKeyE2 command interprets the first two bytes found in the FIFO buffer as the EEPROM starting byte address. The EEPROM bytes starting from the given starting byte address are interpreted as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 18. When both argument bytes are available in the FIFO buffer, the command executes. The LoadKeyE2 command can only be started by the microprocessor and it automatically stops after copying the key from the EEPROM to the key buffer. 11.7.1.1 Relevant LoadKeyE2 command error flags If the key format is incorrect (see Section 9.2.3.1 “Key format” on page 18) an undefined value is copied into the key buffer and the KeyErr flag is set. 11.7.2 LoadKey command 19h Table 154. ErrorFlag register error flags overview Error flag Related commands KeyErr LoadKeyE2, LoadKey AccessErr WriteE2, ReadE2, LoadConfig FIFOOvlf no specific commands CRCErr Receive, Transceive, CalcCRC FramingErr Receive, Transceive ParityErr Receive, Transceive CollErr Receive, Transceive Table 155. LoadKeyE2 command 0Bh Command Value Action Arguments and data Returned data LoadKeyE2 0Bh reads a key from the EEPROM and puts it into the internal key buffer start address LSB - start address MSB - Table 156. LoadKey command 19h Command Value Action Arguments and data Returned data LoadKey 19h reads a key from the FIFO buffer and puts it into the key buffer byte 0 (LSB) - byte 1 - … - byte 10 - byte 11 (MSB) -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 98 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 18. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer. The LoadKey command can only be started by the microprocessor and it automatically stops after copying the key from the FIFO buffer to the key buffer. 11.7.2.1 Relevant LoadKey command error flags All bytes requested are copied from the FIFO buffer to the key buffer. If the key format is not correct (see Section 9.2.3.1 “Key format” on page 18) an undefined value is copied into the key buffer and the KeyErr flag is set. 11.7.3 Authent1 command 0Ch The Authent1 command is a special Transceive command; it sends six argument bytes to the card. The card’s response is not sent to the microprocessor, it is used instead to authenticate the card to the CLRC632 and vice versa. The Authent1 command can be triggered only by the microprocessor. The sequence of states for this command are the same as those for the Transceive command; see Section 11.2.3 on page 85. 11.7.4 Authent2 command 14h The Authent2 command is a special Transceive command. It does not need any argument byte, however all the data needed to be sent to the card is assembled by the CLRC632. The card response is not sent to the microprocessor but is used to authenticate the card to the CLRC632 and vice versa. The Authent2 command can only be started by the microprocessor. The sequence of states for this command are the same as those for the Transceive command; see Section 11.2.3 on page 85. Table 157. Authent1 command 0Ch Command Value Action Arguments and data Returned data Authent1 0Ch performs the first part of the Crypto1 card authentication card Authent1 command - card block address - card serial number LSB - card serial number byte1 - card serial number byte2 - card serial number MSB - Table 158. Authent2 command 14h Command Value Action Arguments and data Returned data Authent2 14h performs the second part of the card authentication using the Crypto1 algorithm - -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 99 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.7.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the CLRC632 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0). Remark: The Crypto1On flag can only be set by a successfully executed Authent2 command and not by the microprocessor. The microprocessor can clear bit Crypto1On to continue with unencrypted (plain) card communication. Remark: The Authent2 command must be executed immediately after a successful Authent1 command; see Section 11.7.3 “Authent1 command 0Ch”. In addition, the keys stored in the key buffer and those on the card must match. 12. Limiting values 13. Characteristics 13.1 Operating condition range Table 159. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb ambient temperature 40 +150 C Tstg storage temperature 40 +150 C VDDD digital supply voltage 0.5 +6 V VDDA analog supply voltage 0.5 +6 V VDD(TVDD) TVDD supply voltage 0.5 +6 V Vi  input voltage (absolute value) on any digital pin to DVSS 0.5 VDDD + 0.5 V on pin RX to AVSS 0.5 VDDA + 0.5 V Table 160. Operating condition range Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature - 25 +25 +85 C VDDD digital supply voltage DVSS = AVSS = TVSS = 0 V 3.0 3.3 3.6 V 4.5 5.0 5.5 V VDDA analog supply voltage DVSS = AVSS = TVSS = 0 V 4.5 5.0 5.5 V VDD(TVDD) TVDD supply voltage DVSS = AVSS = TVSS = 0 V 3.0 5.0 5.5 V VESD electrostatic discharge voltage Human Body Model (HBM); 1.5 k, 100 pF - - 1000 V Machine Model (MM); 0.75 H, 200 pF - - 100 VCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 100 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.2 Current consumption 13.3 Pin characteristics 13.3.1 Input pin characteristics Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in Table 162. The digital input pins NCS, NWR, NRD, ALE, A2, and MFIN have Schmitt trigger characteristics, and behave as defined in Table 163. Table 161. Current consumption Symbol Parameter Conditions Min Typ Max Unit IDDD digital supply current Idle command - 8 11 mA Standby mode - 3 5 mA Soft power-down mode - 800 1000 A Hard power-down mode - 1 10 A IDDA analog supply current Idle command; receiver on - 25 40 mA Idle command; receiver off - 12 15 mA Standby mode - 10 13 mA Soft power-down mode - 1 10 A Hard power-down mode - 1 10 A IDD(TVDD) TVDD supply current continuous wave - - 150 mA pins TX1 and TX2 unconnected; TX1RFEn and TX2RFEn = logic 1 - 5.5 7 mA pins TX1 and TX2 unconnected; TX1RFEn and TX2RFEn = logic 0 - 65 130 A Table 162. Standard input pin characteristics Symbol Parameter Conditions Min Typ Max Unit ILI input leakage current 1.0 - +1.0 A Vth threshold voltage CMOS: VDDD < 3.6 V 0.35VDDD - 0.65VDDD V TTL: 4.5 < VDDD 0.8 - 2.0 V Table 163. Schmitt trigger input pin characteristics Symbol Parameter Conditions Min Typ Max Unit ILI input leakage current 1.0 - +1.0 A Vth threshold voltage positive-going threshold; TTL = 4.5 < VDDD 1.4 - 2.0 V CMOS = VDDD < 3.6 V 0.65VDDD - 0.75VDDD V negative-going threshold; TTL = 4.5 < VDDD 0.8 - 1.3 V CMOS = VDDD < 3.6 V 0.25VDDD - 0.4VDDD VCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 101 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by a RC low-pass filter which causes a propagation delay on the reset signal. The analog input pin RX has the input capacitance and input voltage range shown in Table 165. 13.3.2 Digital output pin characteristics Pins D0 to D7, MFOUT and IRQ have CMOS output characteristics and behave as defined in Table 166. Remark: Pin IRQ can be configured as open collector which causes the VOH values to be no longer applicable. 13.3.3 Antenna driver output pin characteristics The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH-level can be configured using the CwConductance register’s GsCfgCW[5:0] bits, while their source conductance for driving the LOW-level is constant. The antenna driver default configuration output characteristics are specified in Table 167. Table 164. RSTPD input pin characteristics Symbol Parameter Conditions Min Typ Max Unit ILI input leakage current 1.0 - +1.0 A Vth threshold voltage positive-going threshold; CMOS = VDDD < 3.6 V 0.65VDDD - 0.75VDDD V negative-going threshold; CMOS = VDDD < 3.6 V 0.25VDDD - 0.4VDDD V tPD propagation delay - - 20 s Table 165. RX input capacitance and input voltage range Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance - - 15 pF Vi(dyn) dynamic input voltage VDDA = 5 V; Tamb = 25 C 1.1 - 4.4 V Table 166. Digital output pin characteristics Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage VDDD = 5 V; IOH = 1 mA 2.4 4.9 - V VDDD = 5 V; IOH = 10 mA 2.4 4.2 - V VOL LOW-level output voltage VDDD = 5 V; IOL = 1 mA - 25 400 mV VDDD = 5 V; IOL = 10 mA - 250 400 mV IO output current source or sink; VDDD = 5 V - - 10 mACLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 102 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.4 AC electrical characteristics 13.4.1 Separate read/write strobe bus timing Table 167. Antenna driver output pin characteristics Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 4.97 - V VDD(TVDD) = 5.0 V; IOL = 100 mA - 4.85 - V VOL LOW-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 30 - mV VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV IO output current transmitter; continuous wave; peak-to-peak - - 200 mA Table 168. Timing specification for separate read/write strobe Symbol Parameter Conditions Min Typ Max Unit tLHLL ALE HIGH time 20 - - ns tAVLL address valid to ALE LOW time 15 - - ns tLLAX address hold after ALE LOW time 8 - - ns tLLRWL ALE LOW to read/write LOW time ALE LOW to NRD or NWR LOW 15 - - ns tSLRWL chip select LOW to read/write LOW time NCS LOW to NRD or NWR LOW 0 - - ns tRWHSH read/write HIGH to chip select HIGH time NRD or NWR HIGH to NCS HIGH 0 - - ns tRLDV read LOW to data input valid time NRD LOW to data valid - - 65 ns tRHDZ read HIGH to data input high impedance time NRD HIGH to data high-impedance - - 20 ns tWLQV write LOW to data output valid time NWR LOW to data valid - - 35 ns tWHDX data output hold after write HIGH time data hold time after NWR HIGH 8 - - ns tRWLRWH read/write LOW time NRD or NWR 65 - - ns tAVRWL address valid to read/write LOW time NRD or NWR LOW (set-up time) 30 - - ns tWHAX address hold after write HIGH time NWR HIGH (hold time) 8 - - ns tRWHRWL read/write HIGH time 150 - - nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 103 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. The multiplexed address and data bus address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8. 13.4.2 Common read/write strobe bus timing Fig 23. Separate read/write strobe timing diagram 001aaj638 tSLRWL tRWHSH tRWHRWL tWHDX tRHDZ tWLQV tRLDV tAVRWL tWHAX tAVLL tLLAX tRWLRWH tLLRWL tRWHRWL tLHLL A0 to A2 A0 to A2 D0 to D7 D0 to D7 NWR NRD NCS ALE A0 to A2 Multiplexed address bus Separated address bus Table 169. Common read/write strobe timing specification Symbol Parameter Conditions Min Typ Max Unit tLHLL ALE HIGH time 20 - - ns tAVLL address valid to ALE LOW time 15 - - ns tLLAX address hold after ALE LOW time 8 - - ns tLLDSL ALE LOW to data strobe LOW time NWR or NRD LOW 15 - - ns tSLDSL chip select LOW to data strobe LOW time NCS LOW to NDS LOW 0 - - ns tDSHSH data strobe HIGH to chip select HIGH time 0 - - ns tDSLDV data strobe LOW to data input valid time - - 65 ns tDSHDZ data strobe HIGH to data input high impedance time - - 20 ns tDSLQV data strobe LOW to data output valid time NDS/NCS LOW - - 35 ns tDSHQX data output hold after data strobe HIGH time NDS HIGH (write cycle hold time) 8 - - ns tDSHRWX RW hold after data strobe HIGH time after NDS HIGH 8 - - ns tDSLDSH data strobe LOW time NDS/NCS 65 - - nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 104 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.4.3 EPP bus timing tAVDSL address valid to data strobe LOW time 30 - - ns tRHAX address hold after read HIGH time 8 - - ns tDSHDSL data strobe HIGH time period between write sequences 150 - - ns tWLDSL write LOW to data strobe LOW time R/NW valid to NDS LOW 8 - - ns Fig 24. Common read/write strobe timing diagram Table 169. Common read/write strobe timing specification …continued Symbol Parameter Conditions Min Typ Max Unit 001aaj639 tSLDSL tDSHSH tDSHDSL tDSHQX tDSHDZ tDSLDV tDSLQV tAVDSL tRHAX tAVLL tLLAX tDSLDSH tLLDSL tDSHDSL tLHLL tWLDSL tDSHRWX A0 to A2 A0 to A2 D0 to D7 D0 to D7 NRD R/NW NCS/NDS ALE A0 to A2 Multiplexed address bus Separated address bus Table 170. Common read/write strobe timing specification for EPP Symbol Parameter Conditions Min Typ Max Unit tASLASH address strobe LOW time nAStrb 20 - - ns tAVASH address valid to address strobe HIGH time multiplexed address bus set-up time 15 - - ns tASHAV address valid after address strobe HIGH time multiplexed address bus hold time 8 - - ns tSLDSL chip select LOW to data strobe LOW time NCS LOW to nDStrb LOW 0 - - ns tDSHSH data strobe HIGH to chip select HIGH time nDStrb HIGH to NCS HIGH 0 - - ns tDSLDV data strobe LOW to data input valid time read cycle - - 65 nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 105 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: Figure 25 does not distinguish between the address write cycle and a data write cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8. tDSHDZ data strobe HIGH to data input high impedance time read cycle - - 20 ns tDSLQV data strobe LOW to data output valid time nDStrb LOW - - 35 ns tDSHQX data output hold after data strobe HIGH time NCS HIGH 8 - - ns tDSHWX write hold after data strobe HIGH time nWrite 8 - - ns tDSLDSH data strobe LOW time nDStrb 65 - - ns tWLDSL write LOW to data strobe LOW time nWrite valid to nDStrb LOW 8 - - ns tDSL-WAITH data strobe LOW to WAIT HIGH time nDStrb LOW to nWrite HIGH - - 75 ns tDSH-WAITL data strobe HIGH to WAIT LOW time nDStrb HIGH to nWrite LOW - - 75 ns Fig 25. Timing diagram for common read/write strobe; EPP Table 170. Common read/write strobe timing specification for EPP …continued Symbol Parameter Conditions Min Typ Max Unit 001aaj640 nWait tDSL-WAITH tDSLDV tDSLQV tWLDSL tSLDSL tDSHSH tDSLDSH D0 to D7 A0 to A7 tDSHQX tDSHDZ tDSH-WAITL tDSHWX D0 to D7 nDStrb nAStrb nWrite NCSCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 106 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.4.4 SPI timing Remark: To send more bytes in one data stream the NSS signal must be LOW during the send process. To send more than one data stream the NSS signal must be HIGH between each data stream. 13.4.5 Clock frequency The clock input is pin OSCIN. The clock applied to the CLRC632 acts as a time constant for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for ensuring proper performance. To obtain highest performance, clock jitter must be as small as possible. This is best achieved using the internal oscillator buffer and the recommended circuitry; see Section 9.8 on page 30. Table 171. SPI timing specification Symbol Parameter Conditions Min Typ Max Unit tSCKL SCK LOW time 100 - - ns tSCKH SCK HIGH time 100 - - ns tDSHQX data output hold after data strobe HIGH time 20 - - ns tDQXCH data input/output changing to clock HIGH time 20 - - ns th(SCKL-Q) SCK LOW to data output hold time - - 15 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 20 - - ns Fig 26. Timing diagram for SPI 001aaj64 tNSSH tSCKL tSCKH tSCKL th(SCKL-Q) tsu(D-SCKH) th(SCKH-D) th(SCKL-Q) t(SCKL-NSSH) SCK OSI ISO MSB MSB LSB LSB NSS Table 172. Clock frequency Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency checked by the clock filter - 13.56 - MHz clk clock duty cycle 40 50 60 % tjit jitter time of clock edges - - 10 psCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 107 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 14. EEPROM characteristics The EEPROM size is 32  16  8 = 4096 bit. 15. Application information 15.1 Typical application 15.1.1 Circuit diagram Figure 27 shows a typical application where the antenna is directly matched to the CLRC632: Table 173. EEPROM characteristics Symbol Parameter Conditions Min Typ Max Unit Nendu(W_ER) write or erase endurance erase/write cycles 100.000 - - Hz tret retention time Tamb  55 C 10 - - year ter erase time - - 2.9 ms ta(W) write access time - - 2.9 ms Fig 27. Application example circuit diagram: directly matched antenna 001aak625 DVDD RSTPD AVDD TVDD DVDD Reset AVDD TVDD DVSS control lines data bus IRQ OSCIN OSCOUT 13.56 MHz AVSS VMID RX TX2 TVSS TX1 IRQ 15 pF 15 pF C0 C0 C2a C2b C3 R2 R1 L0 L0 C1 C1 C4 100 nF MICROPROCESSOR BUS MICROPROCESSOR DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 108 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. Refer to the following application notes for more detailed information about designing and tuning an antenna. • MICORE reader IC family; Directly Matched Antenna Design Ref. 1 • MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. 15.1.2.1 EMC low-pass filter The MIFARE system operates at a frequency of 13.56 MHz. This frequency is generated by a quartz oscillator to clock the CLRC632. It is also the basis for driving the antenna using the 13.56 MHz energy carrier. This not only causes power emissions at 13.56 MHz, it also emits power at higher harmonics. International EMC regulations define the amplitude of the emitted power over a broad frequency range. To meet these regulations, appropriate filtering of the output signal is required. A multilayer board is recommended to implement a low-pass filter as shown in Figure 27. The low-pass filter consists of the components L0 and C0. The recommended values are given in Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. Remark: To achieve best performance, all components must be at least equal in quality to those recommended. Remark: The layout has a major influence on the overall performance of the filter. 15.1.2.2 Antenna matching Due to the impedance transformation of the low-pass filter, the antenna coil has to be matched to a given impedance. The matching elements C1 and C2 can be estimated and have to be fine tuned depending on the design of the antenna coil. The correct impedance matching is important to ensure optimum performance. The overall quality factor has to be considered to guarantee a proper ISO/IEC 14443 A and ISO/IEC 14443 B communication schemes. Environmental influences have to considered and common EMC design rules. Refer to Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2 for details. Remark: Do not exceed the current limits (IDD(TVDD)), otherwise the chip might be destroyed. Remark: The overall 13.56 MHz RFID proximity antenna design in combination with the CLRC632 IC does not require any specialist RF knowledge. However, all relevant parameters have to be considered to guarantee optimum performance and international EMC compliance. 15.1.2.3 Receiver circuit The internal receiver of the CLRC632 makes use of both subcarrier load modulation side-bands. No external filtering is required.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 109 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution It is recommended to use the internally generated VMID potential as the input potential for pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To provide a stable DC reference voltage, a capacitor (C4) must be connected between VMID and ground. The AC voltage divider of R1 + C3 and R2 has to be designed taking in to account the AC voltage limits on pin RX. Depending on the antenna coil design and the impedance, matching the voltage at the antenna coil will differ. Therefore the recommended way to design the receiver circuit is to use the given values for R1, R2, and C3; refer to Application note; MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. The voltage on pin RX can be altered by varying R1 within the given limits. Remark: R2 is AC connected to ground using C4. 15.1.2.4 Antenna coil The precise calculation of the antenna coil’s inductance is not practicable but the inductance can be estimated using Equation 10. We recommend designing an antenna that is either circular or rectangular. (10) • l1 = length of one turn of the conductor loop • D1 = diameter of the wire or width of the PCB conductor, respectively • K = antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for square antennas) • N1 = number of turns • ln = natural logarithm function The values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend on various parameters such as: • antenna construction (type of PCB) • thickness of conductor • distance between the windings • shielding layer • metal or ferrite in the near environment Therefore a measurement of these parameters under real life conditions or at least a rough measurement and a tuning procedure is highly recommended to guarantee a reasonable performance. Refer to Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2 for details. L1  nH = 2 I1  cm I1 D1 ln K   ------ –    N1 1.8  CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 110 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2 Test signals The CLRC632 allows different kinds of signal measurements. These measurements can be used to check the internally generated and received signals using the serial signal switch as described in Section 9.11 on page 37. In addition, the CLRC632 enables users to select between: • internal analog signals for measurement on pin AUX • internal digital signals for observation on pin MFOUT (based on register selections) These measurements can be helpful during the design-in phase to optimize the receiver’s behavior, or for test purposes. 15.2.1 Measurements using the serial signal switch Using the serial signal switch on pin MFOUT, data is observed that is sent to the card or received from the card. Table 174 gives an overview of the different signals available. Remark: The routing of the Manchester or the Manchester with subcarrier signal to pin MFOUT is only possible at 106 kBd based on ISO/IEC 14443 A. 15.2.1.1 TX control Figure 28 shows as an example of an ISO/IEC 14443 A communication. The signal is measured on pin MFOUT using the serial signal switch to control the data sent to the card. Setting the flag MFOUTSelect[2:0] = 3 sends the data to the card coded as NRZ. Setting MFOUTSelect[2:0] = 2 shows the data as a Miller coded signal. The RFOut signal is measured directly on the antenna and gives the RF signal pulse shape. Refer to Application note Directly matched Antenna - Excel calculation (Ref. 3) for detail information on the RF signal pulse. Table 174. Signal routed to pin MFOUT SignalToMFOUT MFOUTSelect Signal routed to pin MFOUT 0 0 LOW 0 1 HIGH 0 2 envelope 0 3 transmit NRZ 0 4 Manchester with subcarrier 0 5 Manchester 0 6 reserved 0 7 reserved 1 X digital test signalCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 111 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2.1.2 RX control Figure 29 shows an example of ISO/IEC 14443 A communication which represents the beginning of a card’s answer to a request signal. The RF signal shows the RF voltage measured directly on the antenna so that the card’s load modulation is visible. Setting MFOUTSelect[2:0] = 4 shows the Manchester decoded signal with subcarrier. Setting MFOUTSelect[2:0] = 5 shows the Manchester decoded signal. (1) MFOUTSelect[2:0] = 3; serial data stream; 2 V per division. (2) MFOUTSelect[2:0] = 2; serial data stream; 2 V per division. (3) RFOut; 1 V per division. Fig 28. TX control signals 001aak626 (1) (2) (3) 10 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 112 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. (1) RFOut; 1 V per division. (2) MFOUTSelect[2:0] = 4; Manchester with subcarrier; 2 V per division. (3) MFOUTSelect[2:0] = 5; Manchester; 2 V per division. Fig 29. RX control signals 001aak627 10 μs per division (1) (2) (3) Table 175. Analog test signal selection Value Signal Name Description 0 VMID voltage at internal node VMID 1 Vbandgap internal reference voltage generated by the bandgap 2 VRxFollI output signal from the demodulator using the I-clock 3 VRxFollQ output signal from the demodulator using the Q-clock 4 VRxAmpI I-channel subcarrier signal amplified and filtered 5 VRxAmpQ Q-channel subcarrier signal amplified and filtered 6 VCorrNI output signal of N-channel correlator fed by the I-channel subcarrier signal 7 VCorrNQ output signal of N-channel correlator fed by the Q-channel subcarrier signal 8 VCorrDI output signal of D-channel correlator fed by the I-channel subcarrier signal 9 VCorrDQ output signal of D-channel correlator fed by the Q-channel subcarrier signal A VEvalL evaluation signal from the left half-bitCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 113 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits. The signals selected by the TestDigiSignalSel[6:0] bits are shown in Table 176. If test signals are not used, the TestDigiSelect register address value must be 00h. Remark: All other values for TestDigiSignalSel[6:0] are for production test purposes only. 15.2.4 Examples of ISO/IEC 14443 A analog and digital test signals Figure 30 shows a MIFARE card’s answer to a request command using the Q-clock receiving path. RX reference is given to show the Manchester modulated signal on pin RX. The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and VCorrNQ were generated in the correlation circuitry. They are processed further in the evaluation and digitizer circuitry. B VEvalR evaluation signal from the right half-bit C VTemp temperature voltage derived from band gap D reserved reserved for future use E reserved reserved for future use F reserved reserved for future use Table 175. Analog test signal selection …continued Value Signal Name Description Table 176. Digital test signal selection TestDigiSignalSel [6:0] Signal name Description F4h s_data data received from the card E4h s_valid when logic 1 is returned the s_data and s_coll signals are valid D4h s_coll when logic 1 is returned a collision has been detected in the current bit C4h s_clock internal serial clock: during transmission, this is the encoder clock during reception this is the receiver clock B5h rd_sync internal synchronized read signal which is derived from the parallel microprocessor interface A5h wr_sync internal synchronized write signal which is derived from the parallel microprocessor interface 96h int_clock internal 13.56 MHz clock 83h BPSK_out BPSK output signal E2h BPSK_sig BPSK signal’s amplitude detected 00h no test signal output as defined by the MFOUTSelect register MFOUTSelect[2:0] bits routed to pin MFOUTCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 114 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit. Finally, the digital test signal s_data shows the received data. This is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. 15.2.5 Examples of I-CODE1 analog and digital test signals Figure 31 shows the answer of an I-CODE1 label IC to an unselected read command using the Q-clock receiving path. RX reference is given to show the Manchester modulated signal on pin RX. The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and VCorrNQ generated in the correlation circuitry are processed further in the evaluation and digitizer circuitry. Signals VEvalR and VEvalL are the evaluation signal of the right and left half-bit. Finally, the digital test-signal s_data shows the received data. This is then routed to the internal digital circuit and s_valid indicates that the received data stream is valid. Fig 30. ISO/IEC 14443 A receiving path Q-clock 001aak628 RX reference VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid 50 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 115 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Fig 31. I-CODE1 receiving path Q-clock VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid receiving path Q-Clock 50 μs per division 001aak629 500 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 116 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 16. Package outline Fig 32. Package outline SOT287-1 UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q Z ywv θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.1 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT287-1 MO-119 (1) 0.012 0.004 0.096 0.089 0.02 0.01 0.05 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w M bp D HE Z e c v M A X A y 32 17 1 16 θ A A1 A2 Lp Q detail X L (A ) 3 E pin 1 index 0 5 10 mm scale SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 00-08-17 03-02-19CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 117 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 17. Abbreviations 18. References [1] Application note — MICORE reader IC family; Directly Matched Antenna Design. [2] Application note — MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas. [3] Application note — Directly matched Antenna - Excel calculation. [4] ISO standard — ISO/IEC 14443 Identification cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4. [5] Application note — MIFARE Implementation of Higher Baud rates. Table 177. Abbreviations and acronyms Acronym Description ASK Amplitude-Shift Keying BPSK Binary Phase-Shift Keying CMOS Complementary Metal-Oxide Semiconductor CRC Cyclic Redundancy Check EOF End Of Frame EPP Enhanced Parallel Port ETU Elementary Time Unit FIFO First In, First Out HBM Human Body Model LSB Least Significant Bit MM Machine Model MSB Most Significant Bit NRZ None Return to Zero POR Power-On Reset PCD Proximity Coupling Device PICC Proximity Integrated Circuit Card SOF Start Of Frame SPI Serial Peripheral InterfaceCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 118 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 19. Revision history Table 178. Revision history Document ID Release date Data sheet status Change notice Supersedes CLRC632 v. 3.7 20140227 Product data sheet - CLRC632 v. 3.6 Modifications: • Section 2 “General description”: 1st paragraph updated CLRC632 v. 3.6 20140130 Product data sheet - CLRC632_35 Modifications: • Section 2 “General description”: updated • Change of descriptive title CLRC632_35 20091110 Product data sheet - CLRC632_34 Modifications: • Data sheet security status changed from COMPANY CONFIDENTIAL to COMPANY PUBLIC • RATP/Innovatron Technologies license statement added to the legal page CLRC632_34 20091014 Product data sheet - 073933 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors • Legal texts have been adapted to the new company name where appropriate • The symbols for electrical characteristics and their parameters have been updated to meet the NXP Semiconductors’ guidelines • A number of inconsistencies in pin, register and bit names have been eliminated from the data sheet • All drawings have been updated • Several symbol changes made to drawings in Figure 23 on page 103 to Figure 26 on page 106 • Section 5 “Quick reference data” on page 3: section added • Section 6 “Ordering information” on page 3: updated • Section 15.1.2.4 “Antenna coil” on page 109: added missing formula and updated the last clause • Section 16 “Package outline” on page 116: updated • Section 18 “References” on page 117: added section and updated the references in the document 073933 December 2005 Product data sheet 073932 073932 April 2005 Product data sheet 073931 073931 May 2004 Product data sheet 073930 073930 November 2002 Product data sheet 073920 073920 June 2002 Preliminary data sheet 073910 073910 January 2002 internal version -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 119 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 120 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 20.4 Licenses 20.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP Semiconductors N.V. ICODE and I-CODE — are trademarks of NXP Semiconductors N.V. MIFARE Ultralight — is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron TechnologyCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 121 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 22. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Supported microprocessor and EPP interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 6. SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10 Table 7. SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 8. SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11 Table 9. SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 10. SPI write address . . . . . . . . . . . . . . . . . . . . . . 11 Table 11. EEPROM memory organization diagram . . . . .12 Table 12. Product information field . . . . . . . . . . . . . . . . .13 Table 13. Product type identification definition . . . . . . . .13 Table 14. Byte assignment for register initialization at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 15. Shipment content of StartUp configuration file .15 Table 16. Byte assignment for register initialization at startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 17. Content of I-CODE1 startup configuration . . . .17 Table 18. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .19 Table 19. Associated FIFO buffer registers and flags . . .20 Table 20. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .21 Table 21. Interrupt control registers . . . . . . . . . . . . . . . .21 Table 22. Associated Interrupt request system registers and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 23. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . .26 Table 24. Associated timer unit registers and flags . . . . .27 Table 25. Signal on pins during Hard power-down . . . . .28 Table 26. Pin TX1 configurations . . . . . . . . . . . . . . . . . .31 Table 27. Pin TX2 configurations . . . . . . . . . . . . . . . . . .32 Table 28. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 29. Gain factors for the internal amplifier . . . . . . . .36 Table 30. DecoderSource[1:0] values . . . . . . . . . . . . . . .39 Table 31. ModulatorSource[1:0] values . . . . . . . . . . . . . .39 Table 32. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .39 Table 33. Register settings to enable use of the analog circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 34. MIFARE higher baud rates . . . . . . . . . . . . . . .40 Table 35. ISO/IEC 14443 B registers and flags . . . . . . . .41 Table 36. Dedicated address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . .43 Table 37. Multiplexed address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . .44 Table 38. Behavior and designation of register bits . . . . .44 Table 39. CLRC632 register overview . . . . . . . . . . . . . . .45 Table 40. CLRC632 register flags overview . . . . . . . . . .47 Table 41. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .50 Table 42. Page register bit descriptions . . . . . . . . . . . . .50 Table 43. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation . . . . . . .50 Table 44. Command register bit descriptions . . . . . . . . . 50 Table 45. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation . . . . . . . . . . . . . 51 Table 46. FIFOData register bit descriptions . . . . . . . . . 51 Table 47. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation . . . . . . . 51 Table 48. PrimaryStatus register bit descriptions . . . . . . 51 Table 49. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation . . . . . . . 52 Table 50. FIFOLength bit descriptions . . . . . . . . . . . . . . 52 Table 51. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation . . . 53 Table 52. SecondaryStatus register bit descriptions . . . . 53 Table 53. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation . . . . . . . 53 Table 54. InterruptEn register bit descriptions . . . . . . . . 53 Table 55. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation . . . . . . . 54 Table 56. InterruptRq register bit descriptions . . . . . . . . 54 Table 57. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 55 Table 58. Control register bit descriptions . . . . . . . . . . . 55 Table 59. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation . . . . . . . . . . . . 55 Table 60. ErrorFlag register bit descriptions . . . . . . . . . . 55 Table 61. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 56 Table 62. CollPos register bit descriptions . . . . . . . . . . . 56 Table 63. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57 Table 64. TimerValue register bit descriptions . . . . . . . . 57 Table 65. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57 Table 66. CRCResultLSB register bit descriptions . . . . . 57 Table 67. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57 Table 68. CRCResultMSB register bit descriptions . . . . 57 Table 69. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 58 Table 70. BitFraming register bit descriptions . . . . . . . . . 58 Table 71. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation . . . . . . . . . . . . 59 Table 72. TxControl register bit descriptions . . . . . . . . . 59 Table 73. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . 60 Table 74. CwConductance register bit descriptions . . . . 60 Table 75. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . 60 Table 76. ModConductance register bit descriptions . . . 60 Table 77. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation . . . . . . . . . . . . 61 Table 78. CoderControl register bit descriptions . . . . . . . 61 Table 79. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation . . . . . . . . . . . . 62 Table 80. ModWidth register bit descriptions . . . . . . . . . 62 Table 81. ModWidthSOF register (address: 16h) reset CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 122 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution value: 0011 1111b, 3Fh bit allocation . . . . . . . .62 Table 82. ModWidthSOF register bit descriptions . . . . . .62 Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation . . . . . . .63 Table 84. TypeBFraming register bit descriptions . . . . . .63 Table 85. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation . . . . . . . . . . . . .64 Table 86. RxControl1 register bit descriptions . . . . . . . . .64 Table 87. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit allocation . . . . . . .65 Table 88. DecoderControl register bit descriptions . . . . .65 Table 89. BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation . . . . . . . . . . . .65 Table 90. BitPhase register bit descriptions . . . . . . . . . .65 Table 91. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation . . . . . . . . . . . . .66 Table 92. RxThreshold register bit descriptions . . . . . . .66 Table 93. BPSKDemControl register (address: 1Dh) reset value: 0001 1110b, 1Eh bit allocation . . . . . . .66 Table 94. BPSKDemControl register bit descriptions . . .66 Table 95. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation . . . . . . . . . . . . .67 Table 96. RxControl2 register bit descriptions . . . . . . . . .67 Table 97. ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation . . . . . . . .67 Table 98. ClockQControl register bit descriptions . . . . . .67 Table 99. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation . . . . . . . . . . . . .68 Table 100. RxWait register bit descriptions . . . . . . . . . . .68 Table 101. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation . . .68 Table 102. ChannelRedundancy bit descriptions . . . . . . .68 Table 103. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation . . . . . . .69 Table 104. CRCPresetLSB register bit descriptions . . . . .69 Table 105. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit allocation . . . . . . .69 Table 106. CRCPresetMSB bit descriptions . . . . . . . . . . .69 Table 107. TimeSlotPeriod register (address: 25h) reset value: 0000 0000b, 00h bit allocation . . . . . . .69 Table 108. TimeSlotPeriod register bit descriptions . . . . .70 Table 109. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation . . . . . . .70 Table 110. MFOUTSelect register bit descriptions . . . . . .70 Table 111. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . .70 Table 112. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation . . . . . . .71 Table 113. FIFOLevel register bit descriptions . . . . . . . . .71 Table 114. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation . . . . . . . .71 Table 115. TimerClock register bit descriptions . . . . . . . .71 Table 116. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation . . . . . . .72 Table 117. TimerControl register bit descriptions . . . . . . .72 Table 118. TimerReload register (address: 2Ch) reset value: 0000 1010b, 0Ah bit allocation . . . . . . .72 Table 119. TimerReload register bit descriptions . . . . . . .72 Table 120. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation . . . . . . . 73 Table 121. IRQPinConfig register bit descriptions . . . . . . 73 Table 122. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 73 Table 123. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 73 Table 124. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 73 Table 125. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 74 Table 126. TestAnaSelect register (address: 3Ah) reset value: 0000 0000b, 00h bit allocation . . . . . . . 74 Table 127. TestAnaSelect bit descriptions . . . . . . . . . . . . 74 Table 128. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 75 Table 129. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 75 Table 130. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 75 Table 131. TestDigiSelect register bit descriptions . . . . . 75 Table 132. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 76 Table 133. CLRC632 commands overview . . . . . . . . . . . 76 Table 134. StartUp command 3Fh . . . . . . . . . . . . . . . . . . 78 Table 135. Idle command 00h . . . . . . . . . . . . . . . . . . . . . 78 Table 136. Transmit command 1Ah . . . . . . . . . . . . . . . . . 79 Table 137. Transmission of frames of more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 138. Receive command 16h . . . . . . . . . . . . . . . . . 82 Table 139. Return values for bit-collision positions . . . . . 84 Table 140. Communication error table . . . . . . . . . . . . . . . 84 Table 141. Transceive command 1Eh . . . . . . . . . . . . . . . 85 Table 142. Meaning of ModemState . . . . . . . . . . . . . . . . 85 Table 143. Transmit command 1Ah . . . . . . . . . . . . . . . . . 87 Table 144. Receive command 16h . . . . . . . . . . . . . . . . . 88 Table 145. Return values for bit-collision positions . . . . . 90 Table 146. Communication error table . . . . . . . . . . . . . . . 90 Table 147. Transceive command 1Eh . . . . . . . . . . . . . . . 91 Table 148. ModemState values . . . . . . . . . . . . . . . . . . . . 91 Table 149. WriteE2 command 01h . . . . . . . . . . . . . . . . . . 93 Table 150. ReadE2 command 03h . . . . . . . . . . . . . . . . . 95 Table 151. LoadConfig command 07h . . . . . . . . . . . . . . . 95 Table 152. CalcCRC command 12h . . . . . . . . . . . . . . . . 96 Table 153. CRC coprocessor parameters . . . . . . . . . . . . 96 Table 154. ErrorFlag register error flags overview . . . . . . 97 Table 155. LoadKeyE2 command 0Bh . . . . . . . . . . . . . . 97 Table 156. LoadKey command 19h . . . . . . . . . . . . . . . . . 97 Table 157. Authent1 command 0Ch . . . . . . . . . . . . . . . . 98 Table 158. Authent2 command 14h . . . . . . . . . . . . . . . . . 98 Table 159. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 160. Operating condition range . . . . . . . . . . . . . . . 99 Table 161. Current consumption . . . . . . . . . . . . . . . . . . 100 Table 162. Standard input pin characteristics . . . . . . . . 100 Table 163. Schmitt trigger input pin characteristics . . . . 100 Table 164. RSTPD input pin characteristics . . . . . . . . . 101 Table 165. RX input capacitance and input voltage CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 123 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table 166. Digital output pin characteristics . . . . . . . . . .101 Table 167. Antenna driver output pin characteristics . . .102 Table 168. Timing specification for separate read/write strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Table 169. Common read/write strobe timing specification . . . . . . . . . . . . . . . . . . . . . . . . . .103 Table 170. Common read/write strobe timing specification for EPP . . . . . . . . . . . . . . . . . . .104 Table 171. SPI timing specification . . . . . . . . . . . . . . . . .106 Table 172. Clock frequency . . . . . . . . . . . . . . . . . . . . . .106 Table 173. EEPROM characteristics . . . . . . . . . . . . . . .107 Table 174. Signal routed to pin MFOUT . . . . . . . . . . . . . 110 Table 175. Analog test signal selection . . . . . . . . . . . . . 112 Table 176. Digital test signal selection . . . . . . . . . . . . . . 113 Table 177. Abbreviations and acronyms . . . . . . . . . . . . . 117 Table 178. Revision history . . . . . . . . . . . . . . . . . . . . . . . 118CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 124 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 23. Figures Fig 1. CLRC632 block diagram . . . . . . . . . . . . . . . . . . . .4 Fig 2. CLRC632 pin configuration . . . . . . . . . . . . . . . . . .5 Fig 3. Connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .8 Fig 4. Connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .9 Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake. . . . . . . . . . . . .9 Fig 6. Connection to microprocessor: SPI . . . . . . . . . . .10 Fig 7. Key storage format . . . . . . . . . . . . . . . . . . . . . . .18 Fig 8. Timer module block diagram . . . . . . . . . . . . . . . .24 Fig 9. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . . . .26 Fig 10. The StartUp procedure. . . . . . . . . . . . . . . . . . . . .29 Fig 11. Quartz clock connection . . . . . . . . . . . . . . . . . . .30 Fig 12. Receiver circuit block diagram. . . . . . . . . . . . . . .35 Fig 13. Automatic Q-clock calibration . . . . . . . . . . . . . . .36 Fig 14. Serial signal switch block diagram. . . . . . . . . . . .38 Fig 15. Crypto1 key handling block diagram . . . . . . . . . .42 Fig 16. Transmitting bit oriented frames . . . . . . . . . . . . .80 Fig 17. Timing for transmitting byte oriented frames . . . .81 Fig 18. Timing for transmitting bit oriented frames. . . . . .81 Fig 19. Card communication state diagram . . . . . . . . . . .86 Fig 20. Timing for transmitting byte oriented frames . . . .88 Fig 21. Label communication state diagram . . . . . . . . . .92 Fig 22. EEPROM programming timing diagram. . . . . . . .94 Fig 23. Separate read/write strobe timing diagram . . . .103 Fig 24. Common read/write strobe timing diagram . . . .104 Fig 25. Timing diagram for common read/write strobe; EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Fig 26. Timing diagram for SPI . . . . . . . . . . . . . . . . . . .106 Fig 27. Application example circuit diagram: directly matched antenna . . . . . . . . . . . . . . . . . . . . . . . .107 Fig 28. TX control signals . . . . . . . . . . . . . . . . . . . . . . . 111 Fig 29. RX control signals . . . . . . . . . . . . . . . . . . . . . . . 112 Fig 30. ISO/IEC 14443 A receiving path Q-clock. . . . . . 114 Fig 31. I-CODE1 receiving path Q-clock . . . . . . . . . . . . 115 Fig 32. Package outline SOT287-1 . . . . . . . . . . . . . . . . 116CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 125 of 127 continued >> NXP Semiconductors CLRC632 Standard multi-protocol reader solution 24. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 8.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Functional description . . . . . . . . . . . . . . . . . . . 7 9.1 Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 Automatic microprocessor interface detection . 7 9.1.3 Connection to different microprocessor types . 8 9.1.3.1 Separate read and write strobe . . . . . . . . . . . . 8 9.1.3.2 Common read and write strobe . . . . . . . . . . . . 9 9.1.3.3 Common read and write strobe: EPP with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9.1.4 Serial Peripheral Interface . . . . . . . . . . . . . . . . 9 9.1.4.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.1.4.2 SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.2 Memory organization of the EEPROM . . . . . . 12 9.2.1 Product information field (read only). . . . . . . . 13 9.2.2 Register initialization files (read/write) . . . . . . 13 9.2.2.1 StartUp register initialization file (read/write) . 14 9.2.2.2 Factory default StartUp register initialization file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.2.2.3 Register initialization file (read/write) . . . . . . . 16 9.2.2.4 Content of I-CODE1 and ISO/IEC 15693 StartUp register values . . . . . . . . . . . . . . . . . . 16 9.2.3 Crypto1 keys (write only) . . . . . . . . . . . . . . . . 18 9.2.3.1 Key format . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2.3.2 Storage of keys in the EEPROM . . . . . . . . . . 18 9.3 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 19 9.3.1.1 Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 19 9.3.3 FIFO buffer status information . . . . . . . . . . . . 20 9.3.4 FIFO buffer registers and flags. . . . . . . . . . . . 20 9.4 Interrupt request system. . . . . . . . . . . . . . . . . 20 9.4.1 Interrupt sources overview . . . . . . . . . . . . . . . 21 9.4.2 Interrupt request handling. . . . . . . . . . . . . . . . 21 9.4.2.1 Controlling interrupts and getting their status . 21 9.4.2.2 Accessing the interrupt registers . . . . . . . . . . 22 9.4.3 Configuration of pin IRQ . . . . . . . . . . . . . . . . 22 9.4.4 Register overview interrupt request system. . 23 9.5 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5.1 Timer unit implementation . . . . . . . . . . . . . . . 24 9.5.1.1 Timer unit block diagram . . . . . . . . . . . . . . . . 24 9.5.1.2 Controlling the timer unit . . . . . . . . . . . . . . . . 24 9.5.1.3 Timer unit clock and period . . . . . . . . . . . . . . 25 9.5.1.4 Timer unit status. . . . . . . . . . . . . . . . . . . . . . . 25 9.5.1.5 TimeSlotPeriod. . . . . . . . . . . . . . . . . . . . . . . . 26 9.5.2 Using the timer unit functions. . . . . . . . . . . . . 27 9.5.2.1 Time-out and WatchDog counters . . . . . . . . . 27 9.5.2.2 Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5.2.3 Programmable one shot timer and periodic trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5.3 Timer unit registers . . . . . . . . . . . . . . . . . . . . 27 9.6 Power reduction modes . . . . . . . . . . . . . . . . . 28 9.6.1 Hard power-down. . . . . . . . . . . . . . . . . . . . . . 28 9.6.2 Soft power-down mode . . . . . . . . . . . . . . . . . 28 9.6.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 29 9.6.4 Automatic receiver power-down. . . . . . . . . . . 29 9.7 StartUp phase . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7.1 Hard power-down phase . . . . . . . . . . . . . . . . 29 9.7.2 Reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7.3 Initialization phase . . . . . . . . . . . . . . . . . . . . . 30 9.7.4 Initializing the parallel interface type . . . . . . . 30 9.8 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 30 9.9 Transmitter pins TX1 and TX2 . . . . . . . . . . . . 31 9.9.1 Configuring pins TX1 and TX2. . . . . . . . . . . . 31 9.9.2 Antenna operating distance versus power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9.3 Antenna driver output source resistance . . . . 32 9.9.3.1 Source resistance table . . . . . . . . . . . . . . . . . 33 9.9.3.2 Calculating the relative source resistance . . . 34 9.9.3.3 Calculating the effective source resistance . . 34 9.9.4 Pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.10 Receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 34 9.10.1 Receiver circuit block diagram . . . . . . . . . . . . 35 9.10.2 Receiver operation. . . . . . . . . . . . . . . . . . . . . 35 9.10.2.1 Automatic Q-clock calibration . . . . . . . . . . . . 35 9.10.2.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.10.2.3 Correlation circuitry . . . . . . . . . . . . . . . . . . . . 37 9.10.2.4 Evaluation and digitizer circuitry . . . . . . . . . . 37 9.11 Serial signal switch . . . . . . . . . . . . . . . . . . . . 37 9.11.1 Serial signal switch block diagram . . . . . . . . . 38 9.11.2 Serial signal switch registers . . . . . . . . . . . . . 38 9.11.2.1 Active antenna concept . . . . . . . . . . . . . . . . . 39 9.11.2.2 Driving both RF parts . . . . . . . . . . . . . . . . . . . 40 9.12 MIFARE higher baud rates. . . . . . . . . . . . . . . 40CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 126 of 127 continued >> NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.13 ISO/IEC 14443 B communication scheme . . . 41 9.14 MIFARE authentication and Crypto1 . . . . . . . 42 9.14.1 Crypto1 key handling . . . . . . . . . . . . . . . . . . . 42 9.14.2 Authentication procedure . . . . . . . . . . . . . . . . 43 10 CLRC632 registers. . . . . . . . . . . . . . . . . . . . . . 43 10.1 Register addressing modes . . . . . . . . . . . . . . 43 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.2 Dedicated address bus. . . . . . . . . . . . . . . . . . 43 10.1.3 Multiplexed address bus. . . . . . . . . . . . . . . . . 43 10.2 Register bit behavior. . . . . . . . . . . . . . . . . . . . 44 10.3 Register overview . . . . . . . . . . . . . . . . . . . . . . 45 10.4 CLRC632 register flags overview . . . . . . . . . . 47 10.5 Register descriptions . . . . . . . . . . . . . . . . . . . 50 10.5.1 Page 0: Command and status . . . . . . . . . . . . 50 10.5.1.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5.1.2 Command register . . . . . . . . . . . . . . . . . . . . . 50 10.5.1.3 FIFOData register. . . . . . . . . . . . . . . . . . . . . . 51 10.5.1.4 PrimaryStatus register . . . . . . . . . . . . . . . . . . 51 10.5.1.5 FIFOLength register . . . . . . . . . . . . . . . . . . . . 52 10.5.1.6 SecondaryStatus register . . . . . . . . . . . . . . . . 53 10.5.1.7 InterruptEn register. . . . . . . . . . . . . . . . . . . . . 53 10.5.1.8 InterruptRq register. . . . . . . . . . . . . . . . . . . . . 54 10.5.2 Page 1: Control and status . . . . . . . . . . . . . . . 55 10.5.2.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.3 ErrorFlag register . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.4 CollPos register . . . . . . . . . . . . . . . . . . . . . . . 56 10.5.2.5 TimerValue register. . . . . . . . . . . . . . . . . . . . . 57 10.5.2.6 CRCResultLSB register . . . . . . . . . . . . . . . . . 57 10.5.2.7 CRCResultMSB register. . . . . . . . . . . . . . . . . 57 10.5.2.8 BitFraming register . . . . . . . . . . . . . . . . . . . . . 58 10.5.3 Page 2: Transmitter and control . . . . . . . . . . . 59 10.5.3.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.5.3.2 TxControl register . . . . . . . . . . . . . . . . . . . . . . 59 10.5.3.3 CwConductance register . . . . . . . . . . . . . . . . 60 10.5.3.4 ModConductance register. . . . . . . . . . . . . . . . 60 10.5.3.5 CoderControl register . . . . . . . . . . . . . . . . . . . 61 10.5.3.6 ModWidth register. . . . . . . . . . . . . . . . . . . . . . 62 10.5.3.7 ModWidthSOF register . . . . . . . . . . . . . . . . . . 62 10.5.3.8 TypeBFraming . . . . . . . . . . . . . . . . . . . . . . . . 63 10.5.4 Page 3: Receiver and decoder control . . . . . . 64 10.5.4.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5.4.2 RxControl1 register. . . . . . . . . . . . . . . . . . . . . 64 10.5.4.3 DecoderControl register . . . . . . . . . . . . . . . . . 65 10.5.4.4 BitPhase register . . . . . . . . . . . . . . . . . . . . . . 65 10.5.4.5 RxThreshold register . . . . . . . . . . . . . . . . . . . 66 10.5.4.6 BPSKDemControl. . . . . . . . . . . . . . . . . . . . . . 66 10.5.4.7 RxControl2 register. . . . . . . . . . . . . . . . . . . . . 67 10.5.4.8 ClockQControl register . . . . . . . . . . . . . . . . . . 67 10.5.5 Page 4: RF Timing and channel redundancy . 68 10.5.5.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.5.2 RxWait register. . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.5.3 ChannelRedundancy register . . . . . . . . . . . . 68 10.5.5.4 CRCPresetLSB register . . . . . . . . . . . . . . . . . 69 10.5.5.5 CRCPresetMSB register . . . . . . . . . . . . . . . . 69 10.5.5.6 TimeSlotPeriod register . . . . . . . . . . . . . . . . . 69 10.5.5.7 MFOUTSelect register . . . . . . . . . . . . . . . . . . 70 10.5.5.8 PreSet27 register . . . . . . . . . . . . . . . . . . . . . . 70 10.5.6 Page 5: FIFO, timer and IRQ pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.2 FIFOLevel register . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.3 TimerClock register . . . . . . . . . . . . . . . . . . . . 71 10.5.6.4 TimerControl register . . . . . . . . . . . . . . . . . . . 72 10.5.6.5 TimerReload register . . . . . . . . . . . . . . . . . . . 72 10.5.6.6 IRQPinConfig register . . . . . . . . . . . . . . . . . . 73 10.5.6.7 PreSet2E register. . . . . . . . . . . . . . . . . . . . . . 73 10.5.6.8 PreSet2F register. . . . . . . . . . . . . . . . . . . . . . 73 10.5.7 Page 6: reserved . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h . . . . . . . . . . . . . . . . . . . . . . 73 10.5.8 Page 7: Test control . . . . . . . . . . . . . . . . . . . . 74 10.5.8.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.5.8.2 Reserved register 39h . . . . . . . . . . . . . . . . . . 74 10.5.8.3 TestAnaSelect register . . . . . . . . . . . . . . . . . . 74 10.5.8.4 Reserved register 3Bh . . . . . . . . . . . . . . . . . . 75 10.5.8.5 Reserved register 3Ch . . . . . . . . . . . . . . . . . . 75 10.5.8.6 TestDigiSelect register . . . . . . . . . . . . . . . . . . 75 10.5.8.7 Reserved registers 3Eh, 3Fh . . . . . . . . . . . . . 76 11 CLRC632 command set . . . . . . . . . . . . . . . . . 76 11.1 CLRC632 command overview . . . . . . . . . . . . 76 11.1.1 Basic states . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1.2 StartUp command 3Fh . . . . . . . . . . . . . . . . . . 78 11.1.3 Idle command 00h . . . . . . . . . . . . . . . . . . . . . 78 11.2 Commands for ISO/IEC 14443 A card communication. . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.1 Transmit command 1Ah. . . . . . . . . . . . . . . . . 79 11.2.1.1 Using the Transmit command . . . . . . . . . . . . 79 11.2.1.2 RF channel redundancy and framing. . . . . . . 80 11.2.1.3 Transmission of bit oriented frames. . . . . . . . 80 11.2.1.4 Transmission of frames with more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.2 Receive command 16h . . . . . . . . . . . . . . . . . 82 11.2.2.1 Using the Receive command . . . . . . . . . . . . . 82 11.2.2.2 RF channel redundancy and framing. . . . . . . 82 11.2.2.3 Collision detection . . . . . . . . . . . . . . . . . . . . . 83 11.2.2.4 Receiving bit oriented frames . . . . . . . . . . . . 84 11.2.2.5 Communication errors . . . . . . . . . . . . . . . . . . 84 11.2.3 Transceive command 1Eh . . . . . . . . . . . . . . . 85NXP Semiconductors CLRC632 Standard multi-protocol reader solution © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 February 2014 073937 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11.2.4 States of the card communication. . . . . . . . . . 85 11.2.5 Card communication state diagram . . . . . . . . 86 11.3 I-CODE1 and ISO/IEC 15693 label communication commands. . . . . . . . . . . . . . . 87 11.3.1 Transmit command 1Ah . . . . . . . . . . . . . . . . . 87 11.3.1.1 Using the Transmit command. . . . . . . . . . . . . 87 11.3.1.2 RF channel redundancy and framing . . . . . . . 88 11.3.1.3 Transmission of frames of more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.3.2 Receive command 16h. . . . . . . . . . . . . . . . . . 88 11.3.2.1 Using the Receive command . . . . . . . . . . . . . 89 11.3.2.2 RF channel redundancy and framing . . . . . . . 89 11.3.2.3 Collision detection . . . . . . . . . . . . . . . . . . . . . 89 11.3.2.4 Communication errors . . . . . . . . . . . . . . . . . . 90 11.3.3 Transceive command 1Eh . . . . . . . . . . . . . . . 91 11.3.4 Label communication states . . . . . . . . . . . . . . 91 11.3.5 Label communication state diagram. . . . . . . . 92 11.4 EEPROM commands . . . . . . . . . . . . . . . . . . . 93 11.4.1 WriteE2 command 01h . . . . . . . . . . . . . . . . . . 93 11.4.1.1 Programming process . . . . . . . . . . . . . . . . . . 93 11.4.1.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 94 11.4.1.3 WriteE2 command error flags. . . . . . . . . . . . . 94 11.4.2 ReadE2 command 03h. . . . . . . . . . . . . . . . . . 95 11.4.2.1 ReadE2 command error flags. . . . . . . . . . . . . 95 11.5 Diverse commands. . . . . . . . . . . . . . . . . . . . . 95 11.5.1 LoadConfig command 07h . . . . . . . . . . . . . . . 95 11.5.1.1 Register assignment. . . . . . . . . . . . . . . . . . . . 95 11.5.1.2 Relevant LoadConfig command error flags . . 96 11.5.2 CalcCRC command 12h. . . . . . . . . . . . . . . . . 96 11.5.2.1 CRC coprocessor settings . . . . . . . . . . . . . . . 96 11.5.2.2 CRC coprocessor status flags . . . . . . . . . . . . 96 11.6 Error handling during command execution. . . 97 11.7 MIFARE security commands . . . . . . . . . . . . . 97 11.7.1 LoadKeyE2 command 0Bh. . . . . . . . . . . . . . . 97 11.7.1.1 Relevant LoadKeyE2 command error flags . . 97 11.7.2 LoadKey command 19h . . . . . . . . . . . . . . . . . 97 11.7.2.1 Relevant LoadKey command error flags . . . . 98 11.7.3 Authent1 command 0Ch. . . . . . . . . . . . . . . . . 98 11.7.4 Authent2 command 14h . . . . . . . . . . . . . . . . . 98 11.7.4.1 Authent2 command effects . . . . . . . . . . . . . . . 99 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 99 13 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1 Operating condition range . . . . . . . . . . . . . . . 99 13.2 Current consumption . . . . . . . . . . . . . . . . . . 100 13.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . 100 13.3.1 Input pin characteristics . . . . . . . . . . . . . . . . 100 13.3.2 Digital output pin characteristics. . . . . . . . . . 101 13.3.3 Antenna driver output pin characteristics . . . 101 13.4 AC electrical characteristics . . . . . . . . . . . . . 102 13.4.1 Separate read/write strobe bus timing . . . . . 102 13.4.2 Common read/write strobe bus timing . . . . . 103 13.4.3 EPP bus timing . . . . . . . . . . . . . . . . . . . . . . 104 13.4.4 SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.4.5 Clock frequency . . . . . . . . . . . . . . . . . . . . . . 106 14 EEPROM characteristics . . . . . . . . . . . . . . . 107 15 Application information . . . . . . . . . . . . . . . . 107 15.1 Typical application . . . . . . . . . . . . . . . . . . . . 107 15.1.1 Circuit diagram. . . . . . . . . . . . . . . . . . . . . . . 107 15.1.2 Circuit description . . . . . . . . . . . . . . . . . . . . 108 15.1.2.1 EMC low-pass filter . . . . . . . . . . . . . . . . . . . 108 15.1.2.2 Antenna matching . . . . . . . . . . . . . . . . . . . . 108 15.1.2.3 Receiver circuit . . . . . . . . . . . . . . . . . . . . . . 108 15.1.2.4 Antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.2 Test signals . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1 Measurements using the serial signal switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1.1 TX control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1.2 RX control . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 15.2.2 Analog test signals. . . . . . . . . . . . . . . . . . . . . 112 15.2.3 Digital test signals . . . . . . . . . . . . . . . . . . . . . 113 15.2.4 Examples of ISO/IEC 14443 A analog and digital test signals . . . . . . . . . . . . . . . . . . 113 15.2.5 Examples of I-CODE1 analog and digital test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 116 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 117 18 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 118 20 Legal information . . . . . . . . . . . . . . . . . . . . . . 119 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 119 20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 20.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 120 21 Contact information . . . . . . . . . . . . . . . . . . . 120 22 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 23 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 1. General description The NTAG I2C is the first product of NXP’s NTAG family offering both contactless and contact interfaces (see Figure 1). In addition to the passive NFC Forum compliant contactless interface, the IC features an I2C contact interface, which can communicate with a microcontroller if the NTAG I2C is powered from an external power supply. An additional externally powered SRAM mapped into the memory allows a fast data transfer between the RF and I2C interfaces and vice versa, without the write cycle limitations of the EEPROM memory. The NTAG I2C product features a configurable Field Detection Pin, which provides a trigger to an external device depending on the activities at the RF interface. The NTAG I2C product can also supply power to external (low power) devices (e.g., a microcontroller) via the embedded energy harvesting circuitry. 2. Features and benefits 2.1 Key features  RF interface NFC forum Type 2 Tag compliant  I 2C interface NT3H1101/NT3H1201 NTAG I2C , NFC Forum type 2 Tag compliant IC with I2C interface Rev. 3.1 — 9 October 2014 265431 Product data sheet COMPANY PUBLIC Fig 1. Contactless and contact system aaa-010357 NFC enabled device Data Energy Data Energy I 2C EEPROM 1 1 1 0 0 0 1 Energy Harvesting Field detection Micro controllerNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 2 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface  Configurable field detection pin based on open drain implementation that can be triggered upon the following events:  A RF field presence  The first Start-of-Frame  The selection of the tag only  64 byte SRAM buffer for fast transfer of data (Pass-through mode) between the RF and the I2C interfaces located outside the User Memory  Wake up signal at the field detect pin when:  New data has arrived from one interface  Data has been read by the receiving interface  Clear arbitration between RF and I2C interfaces:  First come, first serve strategy  Status flag bits to signal if one interface is busy writing to or reading data from the EEPROM  Energy harvesting functionality to power external devices (e.g. microcontroller)  FAST READ command for faster data reading 2.2 RF interface  Contactless transmission of data  NFC Forum Type 2 tag compliant (see Ref. 1)  Operating frequency of 13.56 MHz  Data transfer of 106 kbit/s  4 bytes (one page) written including all overhead in 4,8 ms via EEPROM or 0,8 ms via SRAM (Pass-through mode)  Data integrity of 16-bit CRC, parity, bit coding, bit counting  Operating distance of up to 100 mm (depending on various parameters, such as field strength and antenna geometry)  True anticollision  Unique 7 byte serial number (cascade level 2 according to ISO/IEC 14443-3 (see Ref. 2) 2.3 Memory  1904 bytes freely available with User Read/Write area (476 pages with 4 bytes per pages) for the NTAG I2C 2k version  888 bytes freely available with User Read/Write area (222 pages with 4 bytes per pages) for the NTAG I2C 1k version  Field programmable RF read-only locking function with static and dynamic lock bits configurable from both I²C and NFC interfaces  64 bytes SRAM volatile memory without write endurance limitation  Data retention time of 20 years  Write endurance 200,000 cycles 2.4 I2C interface  I 2C slave interface supports Standard (100 kHz) and Fast (up to 400 kHz) mode (see Ref. 3)NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 3 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface  16 bytes (one block) written in 4,5ms (EEPROM) or 0,4 ms (SRAM - Pass-through mode) including all overhead  RFID chip can be used as standard I2C EEPROM 2.5 Security  Manufacturer-programmed 7-byte UID for each device  Capability container with one time programmable bits  Field programmable read-only locking function per page (per 32 pages for the extended memory section) 2.6 Key benefits  The Pass-through mode allows fast download and upload of data from RF to I²C and vice versa without the cycling limitation of EEPROM  NDEF message storage up to 1904 bytes (2k version) or up to 888 bytes (1k version)  The mapping of the SRAM inside the User Memory buffer allows dynamic update of NDEF message content 3. Applications With all its integrated features and functions the NTAG I2C is the ideal solution to enable a contactless communication via an NFC device (e.g., NFC enabled mobile phone) to an electronic device for:  Zero power configuration (late customization)  Smart customer interaction (e.g., easier after sales service, such as firmware update)  Advanced pairing (for e.g., WiFi or Blue tooth) for dynamic generation of sessions keys Easier product customization and customer experience for the following applications:  Home automation  Home appliances  Consumer electronics  Healthcare  Printers  Smart meters 4. Ordering information Table 1. Ordering information Type number Package Name Description Version NT3H1101W0FHK XQFN8 Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.6mm; 1k bytes memory, 50pF input capacitance SOT902-3 NT3H1201W0FHK XQFN8 Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.6mm; 2k bytes memory, 50pF input capacitance SOT902-3NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 4 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 5. Marking 6. Block diagram Table 2. Marking codes Type number Marking code NT3H1201FHK N12 NT3H1101FHK N11 Fig 2. Block diagram aaa-010358 I 2C SLAVE I 2C CONTROL RF INTERFACE LA LB POWER MANAGEMENT/ ENERGY HARVESTING DIGITAL CONTROL UNIT MEMORY EEPROM SRAM ARBITER/STATUS REGISTERS ANTICOLLISION COMMAND INTERPRETER MEMORY INTERFACE SDA SCL GND FD VCC VoutNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 5 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 7. Pinning information 7.1 Pinning 7.2 Pin description NXP recommends leaving the central pad of the package unconnected. (1) Dimension A: 1.6 mm (2) Dimension B: 0.5 mm Fig 3. Pin configuration aaa-010359 FD Transparent top view side view 4 8 6 5 7 3 1 2VSS LA SCL A B LB A VCC SDA VOUT Table 3. Pin description Pin Symbol Description 1 LA Antenna connection LA 2 VSS GND 3 SCL Serial Clock I2C 4 FD Field detection 5 SDA Serial data I2C 6 VCC VCC in connection (external power supply) 7 Vout Voltage out (energy harvesting) 8 LB Antenna connection LBNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 6 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8. Functional description 8.1 Block description NTAG I2C ICs consist of (see details below): 2016 bytes of EEPROM memory, 64 Bytes of SRAM, a RF interface, Digital Control Unit (DCU), Power Management Unit (PMU) and an I²C interface. Energy and data are transferred via an antenna consisting of a coil with a few turns, which is directly connected to NTAG I2C IC. No further external components are necessary. • RF interface: – modulator/demodulator – rectifier – clock regenerator – Power-On Reset (POR) – voltage regulator • Anticollision: multiple cards may be selected and managed in sequence • Command interpreter: processes memory access commands supported by the NTAG I 2C • EEPROM interface 8.2 RF interface The RF-interface is based on the ISO/IEC 14443 Type A standard. During operation, the NFC device generates an RF field. The RF field must always be present (with short pauses for data communication), as it is used for both communication and as power supply for the tag. For both directions of data communication, there is one start bit at the beginning of each frame. Each byte is transmitted with an odd parity bit at the end. The LSB of the byte with the lowest address of the selected block is transmitted first. The maximum length of an NFC device to tag frame is 163 bits (16 data bytes + 2 CRC bytes = 16×9 + 2×9 + 1 start bit). The maximum length of a fixed size tag to NFC device frame is 307 bits (32 data bytes + 2 CRC bytes = 32 9 + 2  9 + 1 start bit). The FAST_READ command has a variable frame length, which depends on the start and end address parameters. The maximum frame length supported by the NFC device must be taken into account when issuing this command. For a multi-byte parameter, the least significant byte is always transmitted first. For example, when reading from the memory using the READ command, byte 0 from the addressed block is transmitted first, followed by bytes 1 to byte 3 out of this block. The same sequence continues for the next block and all subsequent blocks. 8.2.1 Data integrity The following mechanisms are implemented in the contactless communication link between the NFC device and the NTAG I²C IC to ensure very reliable data transmission: • 16 bits CRC per blockNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 7 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface • Parity bits for each byte • Bit count checking • Bit coding to distinguish between “1”, “0” and “no information” • Channel monitoring (protocol sequence and bit stream analysis) The commands are initiated by the NFC device and controlled by the Digital Control Unit of the NTAG I2C IC. The command response depends on the state of the IC, and for memory operations, also on the access conditions valid for the corresponding page. 8.2.2 RF communication principle The overall RF communication principle is summarized in Figure 4. 8.2.2.1 IDLE state After a power-on reset (POR), the NTAG I2C switches to the IDLE state. It only exits this state when a REQA or a WUPA command is received from the NFC device. Any other data received while in this state is interpreted as an error, and the NTAG I2C remains in the IDLE state. Fig 4. RF communication principle of NTAG I2C SELECT cascade level 2 READY 1 READY 2 SELECT cascade level 1 ACTIVE HALT IDLE POR ANTICOLLISION ANTICOLLISION HLTA identification and selection procedure memory operations aaa-012797 REQA WUPA WUPA READ (16 Byte) FAST_READ WRITE SECTOR_SELECT GET_VERSION NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 8 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface After a correctly executed HLTA command e.g., out of the ACTIVE state, the default waiting state changes from the IDLE state to the HALT state. This state can then only be exited with a WUPA command. 8.2.2.2 READY 1 state In the READY 1 state, the NFC device resolves the first part of the UID (3 bytes) using the ANTICOLLISION or SELECT commands in cascade level 1. This state is correctly exited after execution of the following command: • SELECT command from cascade level 1: the NFC device switches the NTAG I2C into READY2 state where the second part of the UID is resolved. 8.2.2.3 READY 2 state In the READY 2 state, the NTAG I2C supports the NFC device in resolving the second part of its UID (4 bytes) with the cascade level 2 ANTICOLLISION command. This state is usually exited using the cascade level 2 SELECT command. Remark: The response of the NTAG I2C to the cascade level 2 SELECT command is the Select AcKnowledge (SAK) byte. In accordance with ISO/IEC 14443, this byte indicates if the anticollision cascade procedure has finished. NTAG I2C is now uniquely selected and only this device will communicate with the NFC device even when other contactless devices are present in the NFC device field. 8.2.2.4 ACTIVE state All memory operations are operated in the ACTIVE state. The ACTIVE state is exited with the HLTA command and upon reception, the NTAG I2C transits to the HALT state. Any other data received when the device is in this state is interpreted as an error. Depending on its previous state, the NTAG I2C returns to either the IDLE state or HALT state. 8.2.2.5 HALT state HALT and IDLE states constitute the two wait states implemented in the NTAG I2C. An already processed NTAG I2C can be set into the HALT state using the HLTA command. In the anticollision phase, this state helps the NFC device distinguish between processed tags and tags yet to be selected. The NTAG I2C can only exit this state upon execution of the WUPA command. Any other data received when the device is in this state is interpreted as an error, and NTAG I2C state remains unchanged. 8.3 Memory organization The memory map is detailed in Figure 5 (1k memory) and Figure 6 (2k memory) from the RF interface and in Figure 7 (1k memory) and Figure 8 (2k memory) from the I2C interface. The SRAM memory is not mapped from the RF interface, because in the default settings of the NTAG I2C the Pass-through mode is not enabled. Please refer to Section 11 for examples of memory map from the RF interface with SRAM mapping. The structure of manufacturing data, static lock bytes, capability container and user memory pages (except of the user memory length) are compatible with other NTAG products.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 9 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Any memory access which starts at a valid address and extends into an invalid access region will return 0x00 value in the invalid region. 8.3.1 Memory map from RF interface Memory access from the RF interface is organized in pages of 4 bytes each. Fig 5. NTAG I²C 1k memory organization from the RF interface aaa-012798 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 1h ...... 1 1h 2 2h 3 3h 4 4h 15 0Fh 225 E1h 226 E2h 227 E3h 228 E4h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ&WRITE READ READ/R&W n.a. Dynamic lock bytes R&W/R 2h ...... Invalid access - returns NAK n.a. 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. AccessNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 10 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.2 Memory map from I²C interface The memory access of NTAG I²C from the I²C interface is organized in blocks of 16 bytes each. Fig 6. NTAG I²C 2k memory organization from the RF interface aaa-012799 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 2h ...... 1 1h 1h 2 2h 3 3h 4 4h 15 0Fh 225 FFh 226 E2h 227 E3h 228 E4h 223 DFh 224 E0h 225 E1h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ&WRITE READ READ/R&W n.a. Dynamic lock bytes R&W/R 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. Access 0 0h 1 1h ...... ...... ... ... ... ...NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 11 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Remark: * The Byte 0 of Block 0 is always read as 04h. Writing to this byte modifies the I²C address. Fig 7. NTAG I²C 1k memory organization from the I²C interface aaa-012800 Dec. Hex. 12 13 14 15 I 2C block address 1 1h 0 0h ... ... 55 37h 56 38h Serial number Serial number Internal data Internal data Lock bytes I 2C addr.* Byte number within a block 00h 00h 00h 00h R&W/READ Capability Container (CC) READ&WRITE User memory READ&WRITE User memory READ&WRITE Invalid access - returns NAK n.a. READ Dynamic lock bytes 00h R&W READ 57 39h Invalid access - returns NAK n.a. READ/R&W User memory READ&WRITE Access conditions 8 910 11 4567 0123 58 3Ah fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Configuration See section 8.5.9 fixed 00h READ READ 254 FEh fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Session registers (requires READ-Register command) See section 8.5.9 fixed 00h READ READ 59 3Bh ... ... 247 F7h Invalid access - returns NAK n.a. 248 F8h ... ... ... ... ... ... Invalid access - returns NAK n.a. 251 FBh SRAM memory (64 bytes) READ&WRITENT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 12 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.3 EEPROM The EEPROM is a non volatile memory that stores the 7 byte UID, the memory lock conditions, IC configuration information and the 1904 bytes User Data (888 byte User Data in case of the NTAG I2C 1k version). 8.3.4 SRAM For frequently changing data, a volatile memory of 64 bytes with unlimited endurance is built in. The 64 bytes are mapped in a similar way as is done in the EEPROM, i.e., 64 bytes are seen as 16 pages of 4 bytes. Remark: *The Byte 0 of Block 0 is always read as 04h. Writing to this byte modifies the I²C address. Fig 8. NTAG I²C 2k memory organization from the I²C interface aaa-012801 Dec. Hex. 12 13 14 15 I 2C block address 1 1h 0 0h ... ... 119 77h 120 78h Serial number Serial number Internal data Internal data Lock bytes I 2C addr.* Byte number within a block R&W/READ Capability Container (CC) READ&WRITE Dynamic lock bytes R&W Invalid access - returns NAK n.a. READ 00h 00h 00h 00h 00h 00h 00h 00h 00h READ 00h 00h 00h 00h 121 79h Invalid access - returns NAK n.a. READ/R&W User memory READ&WRITE Access conditions 8 910 11 4567 0123 122 7Ah fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Configuration See section 8.5.9 fixed 00h READ READ 254 FEh fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Session registers (requires READ-Register command) See section 8.9 fixed 00h READ READ 123 7Bh ... ... 247 F7h Invalid access - returns NAK n.a. 248 F8h ... ... ... ... ... ... Invalid access - returns NAK n.a. 251 FBh SRAM memory (64 bytes) READ&WRITENT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 13 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The SRAM is only available if the tag is powered via the VCC pin. The SRAM is located at the end of the memory space and it is always directly accessible by the I2C host (addresses F8h to FBh). An RF reader cannot access the SRAM memory in normal mode (i.e., outside the Pass-through mode). The SRAM is only accessible by the RF reader if the SRAM is mirrored onto the EEPROM memory space. With Memory Mirror enabled (SRAM_MIRROR_ON_OFF=1 - see Section 11.2), the SRAM can be mirrored in the User Memory (page 1 to page 119 - see Section 11.2) for access from the RF side. The Memory mirror must be enabled once both interfaces are ON as this feature is disabled after each POR. The register SRAM_MIRROR_BLOCK (see Table 10) indicates the address of the first page of the SRAM buffer. In the case where the SRAM mirror is enabled and the READ command is addressing blocks where the SRAM mirror is located, the SRAM mirror byte values will be returned instead of the EEPROM byte values. Similarly, if the tag is not VCC powered, the SRAM mirror is disabled and reading out the bytes related to the SRAM mirror position would return the values from the EEPROM. In the Pass-through mode (PTHRU_ON_OFF=1 - see Section 8.3.11), the SRAM is mirrored to the fixed address 240 -255 for RF access (see Section 11) in the first memory sector for NTAG I2C 1k and in the second memory sector for NTAG I2C 2k. 8.3.5 UID/serial number The unique 7-byte serial number (UID) is programmed into the first 7 bytes of memory covering page addresses 00h and 01h - see Figure 9. These bytes are programmed and write protected in the production test. SN0 holds the Manufacturer ID for NXP Semiconductors (04h) in accordance with ISO/IEC 14443-3. 8.3.6 Static lock bytes The bits of byte 2 and byte 3 of page 02h (via RF) or byte 10 and 11 address 0h (via I2C) represent the field programmable, read-only locking mechanism (see Figure 10). Each page from 03h (CC) to 0Fh can be individually locked by setting the corresponding locking bit Lx to logic 1 to prevent further write access. After locking, the corresponding page becomes read-only memory. Fig 9. UID/serial number aaa-012802 MSB LSB page 0 byte 00000100 manufacturer ID for NXP Semiconductors (04h) UID0 UID1 UID2 UID3 UID4 UID5 UID6 SAK page 1 page 2 0123 ATQA1 7 bytes UID ATQA0 lock bytesNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 14 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The three least significant bits of lock byte 0 are the block-locking bits. Bit 2 controls pages 0Ah to 0Fh (via RF), bit 1 controls pages 04h to 09h (via RF) and bit 0 controls page 03h (CC). Once the block-locking bits are set, the locking configuration for the corresponding memory area is frozen. For example, if BL15-10 is set to logic 1, then bits L15 to L10 (lock byte 1, bit[7:2]) can no longer be changed. The static locking and block-locking bits are set by the bytes 2 and 3 of the WRITE command to page 02h. The contents of the lock bytes are bit-wise OR’ed and the result then becomes the new content of the lock bytes. This process is irreversible from RF perspective. If a bit is set to logic 1, it cannot be changed back to logic 0. From I²C perspective, the bits can be reset to “0”. The contents of bytes 0 and 1 of page 02h are unaffected by the corresponding data bytes of the WRITE. The default value of the static lock bytes is 00 00h. 8.3.7 Dynamic Lock Bytes To lock the pages of NTAG I2C starting at page address 0Fh and onwards, the dynamic lock bytes are used. The dynamic lock bytes are located at page E2h sector 0h (NTAG I2C 1k) or address E0h sector 1 (NTAG I2C 2k). The three lock bytes cover the memory area of 830 data bytes (NTAG I2C 1k) or 1846 data bytes (NTAG I2C 2k). The granularity is 16 pages for NTAG I2C 1k and 32 pages for NTAG I2C 2k compared to a single page for the first 48 bytes (NTAG I2C 1k) or the first 64 bytes (NTAG I2C 2k) as shown in Figure 11 and Figure 12. Remark: Set all bits marked with RFUI to 0 when writing to the dynamic lock bytes. Fig 10. Static lock bytes 0 and 1 L 7 L 6 L 5 L 4 L CC BL 15-10 BL 9-4 BL CC MSB 0 page 2 Lx locks page x to read-only BLx blocks further locking for the memory area x lock byte 0 lock byte 1 123 LSB L 15 L 14 L 13 L 12 L 11 L 10 L 9 L 8 MSB LSB aaa-006983NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 15 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 11. NTAG I2C 1k Dynamic lock bytes 0, 1 and 2 Fig 12. NTAG I2C 2k Dynamic lock bytes 0, 1 and 2 aaa-008092 page 226 (E2h) 0 1 2 3 LOCK PAGE 128-143 MSB LSB bit 7 6LOCK PAGE 112-127 LOCK PAGE 96-111 LOCK PAGE 80-95 LOCK PAGE 64-79 LOCK PAGE 48-63 LOCK PAGE 32-47 LOCK PAGE 16-31 LOCK PAGE 224-225 543210 RFUI MSB LSB bit 7 6RFUI LOCK PAGE 208-223 LOCK PAGE 192-207 LOCK PAGE 176-191 LOCK PAGE 160-175 LOCK PAGE 144-159 543210 RFUI MSB LSB bit 7 6BL 208-225 BL 176-207 BL 144-175 BL 112-143 BL 80-111 BL 48-79 BL 16-47 543210 page 224 (E0h) 0 1 2 3 Block Locking (BL) bits LOCK PAGE 240-271 MSB LSB bit 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 aaa-012803 LOCK PAGE 208-239 LOCK PAGE 176-207 LOCK PAGE 144-175 LOCK PAGE 112-143 LOCK PAGE 80-111 LOCK PAGE 48-79 LOCK PAGE 16-47 RFUI BL 464-479 LOCK PAGE 464-479 LOCK PAGE 432-463 LOCK PAGE 400-431 LOCK PAGE 368-399 LOCK PAGE 336-367 LOCK PAGE 304-335 LOCK PAGE 272-303 BL 400-463 BL 336-399 BL 272-335 BL 208-271 BL 144-207 BL 80-143 BL 16-79NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 16 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The default value of the dynamic lock bytes is 00 00 00h. The value of Byte 3 is always 00h when read. Reading the 3 bytes for the dynamic lock bytes and the Byte 3 (00h) from RF interface (address E2h sector 0 (NTAG I2C 1k) or E0h sector 1 (NTAG I2C 2k) or from I2C (address 38h (NTAG I2C 1k) or 78h (NTAG I2C 2k)) will also return a fixed value for the next 12 bytes of 00h. Like for the static lock bytes, this process of modifying the dynamic lock bytes is irreversible from RF perspective. If a bit is set to logic 1, it cannot be changed back to logic 0. From I²C perspective, the bits can be reset to “0”. 8.3.8 Capability Container (CC bytes) The Capability Container CC (page 3) is programmed during the IC production according to the NFC Forum Type 2 Tag specification (see Ref. 1). These bytes may be bit-wise modified by a WRITE command from the I²C or RF interface. See examples for NTAG I2C 1k version in Figure 13 and for NTAG I2C 2k version in Figure 14. The default values of the CC bytes at delivery are defined in Section 8.3.10. Fig 13. CC bytes of NTAG I2C 1k version Fig 14. CC bytes of NTAG I2C 2k version aaa-012804 byte E1h 10h 6Dh 00h Example NTAG I2C 1k version CC bytes CC bytes byte 0123 page 3 default value (initialized state) 11100001 00010000 01101101 00000000 write command to page 3 00000000 00000000 00000000 00001111 result in page 3 (read-only state) 11100001 00010000 01101101 00001111 aaa-012805 Example NTAG I2C 2k version default value (initialized state) CC bytes 11100001 00010000 11101010 00000000 write command to page 3 00000000 00000000 00000000 00001111 result in page 3 (read-only state) 11100001 00010000 11101010 00001111 data E1h 10h EAh 00h CC bytes byte 0 1 2 3 page 3NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 17 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.9 User Memory pages Pages 04h to E1h via the RF interface - Block 1h to 37h, plus the first 8 bytes of block 38h via the I2C interface are the user memory read/write areas for NTAG I2C 1k version. Pages 04h (sector 0) to DFh (sector 1) via the RF interface - Block 1h to 77h via the I2C interface are the user memory read/write areas for NTAG I2C 2k version. The default values of the data pages at delivery are defined in Section 8.3.10.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 18 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.10 Memory content at delivery The capability container in page 03h and the page 04h and 05h of NTAG I2C is pre-programmed to the initialized state according to the NFC Forum Type 2 Tag specification (see Ref. 1) as defined in Table 4 (NTAG I2C 1k version) and Table 5 (NTAG I 2C 2k version). This content is READ only from the RF side and READ&WRITE from the I²C side. The User memory contains an empty NDEF TLV. Remark: The default content of the data pages from page 05h onwards is not defined at delivery. 8.3.11 NTAG I2C configuration and session registers NTAG I2C functionalities can be configured and read in two separate locations depending if the configurations shall be effective within the communication session (session registers) or by default after Power On Reset (POR) (configuration bits). The configuration registers of pages E8h to E9h (sector 0 or 1 depending if it is for NTAG I²C 1k or 2k) via the RF interface or block 3Ah or 7Ah (depending if it is for NTAG I²C 1k or 2k) via the I2C interface, see Figure 5, Figure 6, Figure 7 and Figure 8, are used to configure the default functionalities of the NTAG I2C - see Table 6. Those bits values are stored in the EEPROM and represent the default settings to be effective after POR. Their values can be read & written by both interfaces when applicable and when not locked by the register lock bits (see REG_LOCK in Table 9). Table 4. Memory content at delivery NTAG I2C 1k version Page Address Byte number within page 0 1 2 3 03h E1h 10h 6Dh 00h 04h 03h 00h FEh 00h 05h 00h 00h 00h 00h Table 5. Memory content at delivery NTAG I2C 2k version Page Address Byte number within page 0 1 2 3 03h E1h 10h EAh 00h 04h 03h 00h FEh 00h 05h 00h 00h 00h 00h Table 6. Configuration memory NTAG I²C 1k RF address (sector 0) I 2C Address Byte number Dec Hex Dec Hex 0 1 2 3 232 E8h 58 3Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_ BLOCK WDT_LS 233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixedNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 19 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The session registers Pages F8h to F9h (sector 3) via the RF interface or block FEh via I 2C, see Table 8, are used to configure or monitor the values of the current communication session- see Figure 6 and Figure 8. Those bits can only be read via the RF interface but both read and written via the I2C interface. Both the session and the configuration bits have the same register except the REG_LOCK bits, which are only available in the configuration bits and the NS_REG bits which are only available in the session registers. After POR, the configuration bits are loaded into the session registers. During the communication session, the values can be changed, but the related effect will only be visible within the communication session for the session registers or after POR for the configuration bits. After POR, the registers values will be again brought back to the default configuration values. All registers and configuration default values, access and descriptions are described in Table 9 and Table 10. Reading and writing the session registers via I²C can only be done via the READ & WRITE registers operation - see Section 9.8. Table 7. Configuration memory NTAG I²C 2k RF address (sector 1) I 2C Address Byte number Dec Hex Dec Hex 0 1 2 3 232 E8h 122 7Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_ BLOCK WDT_LS 233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixed Table 8. Session registers NTAG I²C 1k and 2k RF address (sector 3h) I 2C Address Byte number Dec Hex Dec Hex 0 1 2 3 248 F8h 254 FEh NC_REG LAST_NDEF_BLOCK SRAM_MIRROR _BLOCK WDT_LS 249 F9h WDT_MS I2C_CLOCK_STR NS_REG 00h fixed Table 9. Configuration bytes Bit Field Access via RF Access via I²C Default values Description NC_REG 7 I2C_RST_ON_OFF R&W R&W 0b enables soft reset through I²C repeated start - see Section 9.3 6 - READ R&W 0b No function - keep at 0b 5 FD_OFF R&W R&W 00b defines the event upon which the signal output on the FD pin is brought up 00b… if the field is switched off 01b… if the field is switched off or the tag is set to the HALT state 10b… if the field is switched off or the last page of the NDEF message has been read (defined in LAST_NDEF_BLOCK)NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 20 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 4 11b... (if FD_ON = 11b) if the field is switched off or if last data is read by I²C (in pass-through mode RF ---> I²C) or last data is written by I²C (in passthrough mode I²C---> RF) 11b... (if FD_ON = 00b or 01b or 10b) if the field is switched off See Section 8.4 for more details 3 FD_ON R&W R&W 00b defines the event upon which the signal output on the FD pin is brought down 00b… if the field is switched on 01b... by first valid Start-of-Frame (SoF) 10b... by selection of the tag 2 11b (in passthrough mode RF-->I²C) if the data is ready to be read from the I²C interface 11b (in passthrough mode I²C--> RF) if the data is read by the RF interface See Section 8.4for more details 1 - READ R&W 0b No function - keep at 0b 0 TRANSFER_DIR R&W R&W 1b defines the data flow direction for the data transfer 0b… From I²C to RF interface 1b… From RF to I²C interface In case the passthrough mode is not enabled 0b… no WRITE access from the RF side Table 9. …continuedConfiguration bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 21 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface LAST_NDEF_BLOCK 7 Address of last BLOCK (16bytes) of NDEF message from I²C addressing. An RF read of the last page of the I2C block, specified by LAST_NDEF_BLOCK sets the register NDEF_DATA_READ to 1b and triggers FD_OFF if FD_OFF is set to 10b 1h is page 4h (first page of the User Memory) from RF addressing 2h is page 8h 3h is page Ch ……… 37h is page DEh - memory sector 0h (last possible page of User memory for NTAG I²C 1k) ...... 77h is page DCh - memory sector 1h (last page possible of the User Memory for NTAG I²C 2k) 6 5 4 LAST_NDEF_BLOCK R&W R&W 00h 3 2 1 0 SRAM_MIRROR_BLOCK 7 Address of first BLOCK (16bytes) of SRAM buffer when mirrored into the User memory from I²C addressing 1h is page 4h (first page of the User Memory) from RF addressing 2h is page 8h 3h is page Ch ……… 34h is page DEh - memory sector 0h (last possible page of User memory for NTAG I²C 1k) ...... 74h is page DCh - memory sector 1h (last page possible of the User Memory for NTAG I²C 2k) 6 5 4 SRAM_MIRROR_ R&W R&W F8h 3 BLOCK 2 1 0 WDT_LS 7 6 5 4 WDT_LS R&W R&W 48h Least Significant byte of watchdog time 3 control register 2 1 0 Table 9. …continuedConfiguration bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 22 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface WDT_MS 7 6 5 4 WDT_MS R&W R&W 08h Most Significant byte of watchdog time 3 control register 2 1 0 I2C_CLOCK_STR 7 0b 6 0b 5 0b 4 READ READ 0b locked to 0b 3 0b 2 0b 1 0b 0 I2C_CLOCK_STR R&W R&W 1b Enables (1b) or disable (0b) the I²C clock stretching REG_LOCK 7 0b 6 0b 5 READ READ 0b locked to 0b 4 0b 3 0b 2 0b 1 R&W R&W 0b… Enable writing of the configuration bytes via I²C 1b… Disable writing of the configuration bytes via I²C One time programmable 0 REG_LOCK R&W R&W 00b 0b… Enable writing of the configuration bytes via RF 1b… Disable writing of the configuration bytes via RF One time programmable Table 9. …continuedConfiguration bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 23 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Table 10. Session register bytes Bit Field Access via RF Access via I²C Default values Description NC_REG 7 I2C_RST_ON_OFF READ R&W - see configuration bytes description 6 PTHRU_ON_OFF READ R&W 0b 1b… enables data transfer via the SRAM buffer (Passthrough mode) 5 FD_OFF READ R&W 4 3 FD_ON READ R&W - see configuration bytes description 2 1 SRAM_MIRROR_ ON_OFF READ R&W 0b 1b enables SRAM mirroring 0 PTHRU_DIR READ R&W see configuration bytes description LAST_NDEF_BLOCK 7 6 5 4 LAST_NDEF_ BLOCK READ R&W - see configuration bytes description 3 2 1 0 SRAM_MIRROR_BLOCK 7 6 5 4 SRAM_MIRROR_ BLOCK READ R&W - see configuration bytes description 3 2 1 0 WDT_LS 7 6 5 4 WDT_LS READ R&W - see configuration bytes description 3 2 1 0NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 24 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.4 Configurable Field Detection Pin The field detection feature provides the capability to trigger an external device (e.g. Controller) or switch on the connected circuitry by an external power management unit depending on activities on the RF interface. WDT_MS 7 6 5 4 WDT_MS READ R&W - see configuration bytes description 3 2 1 0 I2C_CLOCK_STR 7 6 5 4 READ READ - Locked to 0b 3 2 1 0 I2C_CLOCK_STR READ READ See configuration bytes description NS_REG 7 NDEF_DATA_READ READ READ 0b 1b… all data bytes read from the address specified in LAST_NDEF_BLOCK. value is reset to 0b when read 6 I2C_LOCKED READ R&W 0b 1b… Memory access is locked to the I²C interface 5 RF_LOCKED READ READ 0b 1b… Memory access is locked to the RF interface 4 SRAM_I2C_READY READ READ 0b 1b… data is ready in SRAM buffer to be read by I2C 3 SRAM_RF_READY READ READ 0b 1b… data is ready in SRAM buffer to be read by RF 2 EEPROM_WR_ERR READ R&W 0b 1b… HV voltage error during EEPROM write or erase cycle via I²C needs to be written back to "0b" to be cleared 1 EEPROM_WR_BUSY READ READ 0b 1b… EEPROM write cycle in progress - access to EEPROM disabled 0b… EEPROM access possible 0 RF_FIELD_PRESENT READ READ 0b 1b… RF field is detected Table 10. …continuedSession register bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 25 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The conditions for the activation of the field detection signal (FD_ON) can be: • The presence of the RF field • The detection of a valid command (Start-of-Frame) • The selection of the IC. The conditions for the de-activation of the field detection signal (FD_OFF) can be: • The absence of the RF field • The detection of the HALT state • The RF interface has read the last part of the NDEF message defined with LAST_NDEF_MESSAGE All the various combinations of configurations are described in Table 9 and illustrated in Figure 15, Figure 16 and Figure 17 for all various combination of the filed detection signal configuration. The field detection pin can also be used as a handshake mechanism in the Pass-through mode to signal to the external microcontroller if • New data are written to SRAM on the RF interface • Data written to SRAM from the microcontroller are read via the RF interface. See Section 11 for more information on this handshake mechanism.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 26 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 15. Illustration of the field detection feature when configured for simple field detection aaa-012808 I 2C RF NDEF_DATA_READ I2C_LOCKED RF_LOCKED SRAM_I2C_READY SRAM_RF_READY EEPROM_WR_ERR EEPROM_WR_BUSY RF_FIELD_PRESENT 0b 1b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF SRAM_MIRROR_ON_OFF PTHRU_DIR RF field switches ON RF field switches OFF RF field FD pin EVENT ON OFF HIGH LOW REGISTERS NS_REG NC_REG FD_ON FD_OFF 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 27 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 16. Illustration of the field detection feature when configured for First valid state of Frame detection aaa-012809 I 2C RF NDEF_DATA_READ I2C_LOCKED RF_LOCKED SRAM_I2C_READY SRAM_RF_READY EEPROM_WR_ERR EEPROM_WR_BUSY RF_FIELD_PRESENT 0b 1b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF SRAM_MIRROR_ON_OFF PTHRU_DIR RF field ON OFF FD pin HIGH LOW EVENT First valid State-ofFrame RF field switches OFF or tag set to the HALT state REGISTERS NS_REG 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 0b 0b 0b 0b 0b 0b NC_REG 0b 0b 0b 0b FD_ON 0b 0b 1b 1b 1b FD_OFF 0b 0b 1b 1b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 28 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.5 Watchdog timer In order to allow the I²C interface to perform all necessary commands (READ, WRITE...), the memory access remains locked to the I²C interface til the register I2C_LOCKED is cleared by the host - see Table 10. In order however to avoid that the memory stays 'locked' to the I²C for a long period of time, it is possible to program a watchdog timer to unlock the I2C host from the tag, so that the RF reader can access the tag after a period of time of inactivity. The host itself will not be notified of this event directly, but the NS_REG register is updated accordingly (the register bit I2C_LOCKED will be cleared - see Table 10). The default value is set to 20 ms (848h), but the watch dog timer can be freely set from 0001h (9.43 s) up to FFFFh (617.995 s). The timer starts ticking when the communication between the NTAG I2C and the I2C interface starts. In case the Fig 17. Illustration of the field detection feature when configured for selection of the tag detection aaa-012810 I 2C RF NDEF_DATA_READ I2C_LOCKED RF_LOCKED SRAM_I2C_READY SRAM_RF_READY EEPROM_WR_ERR EEPROM_WR_BUSY RF_FIELD_PRESENT 0b 1b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF 1b 1b 1b 1b 1b 1b 1b 1b SRAM_MIRROR_ON_OFF PTHRU_DIR 1b 1b 1b 1b RF field ON OFF FD pin HIGH LOW EVENT Selection of the tag RF field switches OFF or RF read the last 4 bytes of the NDEF message defined in LAST_NDEF_MESSAGE REGISTERS NS_REG 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b NC_REG 0b 0b 0b 0b FD_ON 0b 0b 0b 0b FD_OFF 0b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 29 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface communication with the I2C is still going on after the watchdog timer expires, the communication will continue until the communication has completed. Then the status register I2C_LOCKED will be immediately cleared. In the case where the communication with the I2C interface has completed before the end of the timer and the status register I2C_LOCKED was not cleared by the host, it will be cleared at the end of the watchdog timer. The watchdog timer is only effective if the VCC pin is powered and will be reset and stopped if the NTAG I2C is not VCC powered or if the register status I2C_LOCKED is set to 0 and RF_LOCKED is set to 1. 8.6 Energy harvesting The NTAG I2C provides the capability to supply external low power devices with energy generated from the RF field of a NFC device. The voltage and current from the energy harvesting depend on various parameters, such as the strength of the RF field, the tag antenna size, or the distance from the NFC device. At room temperature, NTAG I2C could provide typically 5 mA at 2 V on the VOUT pin with an NFC Phone. Operating NTAG I2C in energy harvesting mode requires a number of precautions: • A significant buffer capacitor in the range of typically 10nF up to 100 nF maximum shall be connected between VOUT and GND close to the terminals. • If NTAG I2C also powers the I2C bus, then VCC must be connected to VOUT, and pull-up resistors on the SCL and SDA pins must be sized to control SCL and SDA sink current when those lines are pulled low by NTAG I2C or the I2C host • If NTAG I2C also powers the Field Detect bus, then the pull-up resistor on the Field Detect line must be sized to control the sink current into the Field Detect pin when NTAG I2C pulls it low • The NFC reader device communicating with NTAG I2C shall apply polling cycles including an RF Field Off condition of at least 5.1 ms as defined in NFC Forum Activity specification (see Ref. 4, chapter 6). Note that increasing the output current on the Vout decreases the RF communication range.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 30 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9. I²C commands For details about I2C interface refer to Ref. 3. The NTAG I2C supports the I2C protocol. This protocol is summarized in Figure 18. Any device that sends data onto the bus is defined as a transmitter, and any device that reads the data from the bus is defined as a receiver. The device that controls the data transfer is known as the “bus master”, and the other as the “slave” device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The NTAG I2C is always a slave in all communications. 9.1 Start condition Start is identified by a falling edge of Serial Data (SDA), while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The NTAG I 2C continuously monitors SDA (except during a Write cycle) and SCL for a Start condition, and will not respond unless one is given. 9.2 Stop condition Stop is identified by a rising edge of SDA while SCL is stable and driven high. A Stop condition terminates communication between the NTAG I2C and the bus master. A Stop condition at the end of a Write command triggers the internal Write cycle. Fig 18. I2C bus protocol SCL SDA SCL 1 2 3 7 8 9 1 2 3 7 8 9 MSB ACK MSB ACK Start Condition SDA Input SDA Change Stop Condition Stop Condition Start Condition SDA SCL SDA 001aao231NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 31 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9.3 Soft reset feature In the case where the I2C interface is constantly powered on, NTAG I2C can trigger a reset of the I2C interface via its soft reset feature- see Table 9. When this feature is enabled, if the microcontroller does not issue a stop condition between two start conditions, this situation will trigger a reset of the I2C interface and hence may hamper the communication via the I2C interface. 9.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it is the bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 9.5 Data input During data input, the NTAG I2C samples SDA on the rising edge of SCL. For correct device operation, SDA must be stable during the rising edge of SCL, and the SDA signal must change only when SCL is driven low. 9.6 Addressing To start communication between a bus master and the NTAG I2C slave device, the bus master must initiate a Start condition. Following this initiation, the bus master sends the device address. The NTAG I2C address from I2C consists of a 7-bit device identifier (see Table 11 for default value). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device address, the NTAG I2C gives an acknowledgment on SDA during the 9th bit time. If the NTAG I2C does not match the device select code, it deselects itself from the bus and clear the register I2C_LOCKED (see Table 8). [1] Initial values - can be changed. The I2C address of the NTAG I2C (byte 0 - block 0h) can only be modified by the I2C interface. Both interfaces have no READ access to this address and a READ command from the RF or I²C interface to this byte will only return 04h (manufacturer ID for NXP Semiconductors - see Figure 9). Table 11. Default NTAG I2C address from I2C Device address R/W b7 b6 b5 b4 b3 b2 b1 b0 Value 1[1] 0[1] 1[1] 0[1] 1 [1] 0 [1] 1 [1] 1/0xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 32 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9.7 READ and WRITE Operation Fig 19. I2C READ and WRITE operation aaa-012811 Host 7 bits SA and ‘0’ Tag Tag Start Stop Stop D0 D1 D0 D1 D15 MEMA D15 A A A A A A A A A Host Start 7 bits SA and ‘0’ Write: Read: MEMA Stop Start 7 bits SA and ‘1’ A ANT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 33 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The READ and WRITE operation handle always 16 bytes to be read or written (one block - see Figure 8) For the READ operation (see Figure 19), following a Start condition, the bus master/host sends the NTAG I2C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which should correspond to the address of the block of memory (SRAM or EEPROM) that is intended to be read. The NTAG I2C responds to a valid address byte with an acknowledge (A). A Stop condition can be then issued. Then the host again issues a start condition followed by the NTAG I2C slave address with the Read/Write bit set to “1”. The NTAG I2C acknowledges this (A) and sends the first byte of data read (D0).The bus master/host acknowledges it (A) and the NTAG I2C will subsequently transmit the following 15 bytes of memory read with an acknowledge from the host after every byte. After the last byte of memory data has been transmitted by the NTAG I2C, the bus master/host will acknowledge it and issue a Stop condition. For the WRITE operation (see Figure 19), following a Start condition, the bus master/host sends the NTAG I2C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which should correspond to the address of the block of memory (SRAM or EEPROM) that is intended to be written. The NTAG I2C responds to a valid address byte with an acknowledge (A) and, in the case of a WRITE operation, the bus master/host starts transmitting each 16 bytes (D0...D15) that shall be written at the specified address with an acknowledge of the NTAG I²C after each byte (A). After the last byte acknowledge from the NTAG I²C, the bus master/host issues a Stop condition. The memory address accessible via the READ and WRITE operations can only correspond to the EEPROM or SRAM (respectively 00h to 3Ah or F8h to FBh for NTAG I²C 1k and 00h to 7Ah or F8h to FBh for NTAG I²C 2k).xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 34 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9.8 WRITE and READ register operation In order to modify or read the session register bytes (see Table 10), NTAG I²C requires the WRITE and READ register operation (see Figure 20). Fig 20. WRITE and READ register operation aaa-012812 Host 7 bits SA and ‘0’ Tag Tag Start Stop MEMA REGA A A A Host Start 7 bits SA and ‘0’ A Write: Read: Stop Start 7 bits SA and ‘1’ Stop MEMA MASK REGDAT REGDAT A REGA A A A A ANT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 35 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface For the READ register operation, following a Start condition the bus master/host sends the NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA) which corresponds to the address of the block of memory with the session register bytes (FEh). The NTAG I2C responds to the address byte with an acknowledge (A). Then the bus master/host issues a register address (REGA), which corresponds to the address of the targeted byte inside the block FEh (00h, 01h...to 07h) and then waits for the Stop condition. Then the bus master/host again issues a start condition followed by the NTAG I²C slave address with the Read/Write bit set to “1”. The NTAG I²C acknowledges this (A), and sends the selected byte of session register data (REGDAT) within the block FEh. The bus master/host will acknowledge it and issue a Stop condition. For the WRITE register operation, following a Start condition, the bus master/host sends the NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which corresponds to the address of the block of memory within the session register bytes (FEh). After the NTAG I2C acknowledge (A), the bus master/host issues a MASK byte that defines exactly which bits shall be modified by a “1” bit value at the corresponding bit position. Following the NTAG I²C acknowledge (A), the new register data (one byte - REGDAT) to be written is transmitted by the bus master/host. The NTAG I²C acknowledges it (A), and the bus master/host issues a stop condition.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 36 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 10. RF Command NTAG activation follows the ISO/IEC 14443 Type A specification. After NTAG I2C has been selected, it can either be deactivated using the ISO/IEC 14443 HALT command, or NTAG commands (e.g., READ or WRITE) can be performed. For more details about the card activation refer to Ref. 2. 10.1 NTAG I2C command overview All available commands for NTAG I2C are shown in Table 12. [1] Unless otherwise specified, all commands use the coding and framing as described in Ref. 1. 10.2 Timing The command and response timing shown in this document are not to scale and values are rounded to 1 s. All given command and response times refer to the data frames, including start of communication and end of communication. They do not include the encoding (like the Miller pulses). An NFC device data frame contains the start of communication (1 “start bit”) and the end of communication (one logic 0 + 1 bit length of unmodulated carrier). An NFC tag data frame contains the start of communication (1 “start bit”) and the end of communication (1 bit length of no subcarrier). The minimum command response time is specified according to Ref. 1 as an integer n, which specifies the NFC device to NFC tag frame delay time. The frame delay time from NFC tag to NFC device is at least 87 s. The maximum command response time is specified as a time-out value. Depending on the command, the TACK value specified for command responses defines the NFC device to NFC tag frame delay time. It does it for either the 4-bit ACK value specified or for a data frame. All timing can be measured according to the ISO/IEC 14443-3 frame specification as shown for the Frame Delay Time in Figure 21. For more details refer to Ref. 2. Table 12. Command overview Command[1] ISO/IEC 14443 NFC FORUM Command code (hexadecimal) Request REQA SENS_REQ 26h (7 bit) Wake-up WUPA ALL_REQ 52h (7 bit) Anticollision CL1 Anticollision CL1 SDD_REQ CL1 93h 20h Select CL1 Select CL1 SEL_REQ CL1 93h 70h Anticollision CL2 Anticollision CL2 SDD_REQ CL2 95h 20h Select CL2 Select CL2 SEL_REQ CL2 95h 70h Halt HLTA SLP_REQ 50h 00h GET_VERSION - - 60h READ - READ 30h FAST_READ - - 3Ah WRITE - WRITE A2h SECTOR_SELECT SECTOR_SELECT C2hNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 37 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Remark: Due to the coding of commands, the measured timings usually excludes (a part of) the end of communication. Consider this factor when comparing the specified with the measured times. 10.3 NTAG ACK and NAK NTAG uses a 4 bit ACK / NAK as shown in Table 13. 10.4 ATQA and SAK responses NTAG I2C replies to a REQA or WUPA command with the ATQA value shown in Table 14. It replies to a Select CL2 command with the SAK value shown in Table 15. The 2-byte ATQA value is transmitted with the least significant byte first (44h). Fig 21. Frame Delay Time (from NFC device to NFC tag), TACK and TNAK last data bit transmitted by the NFC device FDT = (n* 128 + 84)/fc first modulation of the NFC TAG FDT = (n* 128 + 20)/fc aaa-006986 128/fc logic „1“ 128/fc logic „0“ 256/fc end of communication (E) 256/fc end of communication (E) 128/fc start of communication (S) communication (S) 128/fc start of Table 13. ACK and NAK values Code (4-bit) ACK/NAK Ah Acknowledge (ACK) 0h NAK for invalid argument (i.e. invalid page address) 1h NAK for parity or CRC error 3h NAK for Arbiter locked to I²C 7h NAK for EEPROM write error Table 14. ATQA response of the NTAG I2C Bit number Sales type Hex value 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NTAG I2C 00 44h 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Table 15. SAK response of the NTAG I2C Bit number Sales type Hex value 8 7 6 5 4 3 2 1 NTAG I2C 00h 00000000NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 38 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Remark: The ATQA coding in bits 7 and 8 indicate the UID size according to ISO/IEC 14443 independent from the settings of the UID usage. Remark: The bit numbering in the ISO/IEC 14443 specification starts with LSB = bit 1 and not with LSB = bit 0. So 1 byte counts bit 1 to bit 8 instead of bit 0 to 7. 10.5 GET_VERSION The GET_VERSION command is used to retrieve information about the NTAG family, the product version, storage size and other product data required to identify the specific NTAG I 2C. This command is also available on other NTAG products to have a common way of identifying products across platforms and evolution steps. The GET_VERSION command has no arguments and returns the version information for the specific NTAG I2C type. The command structure is shown in Figure 22 and Table 16. Table 17 shows the required timing. [1] Refer to Section 10.2 “Timing”. Fig 22. GET_VERSION command Table 16. GET_VERSION command Name Code Description Length Cmd 60h Get product version 1 byte CRC - CRC according to Ref. 1 2 bytes Data - Product version information 8 bytes NAK see Table 13 see Section 10.3 4-bit Table 17. GET_VERSION timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut GET_VERSION n=9[1] TTimeOut 5 ms CRC CRC NFC device Cmd NTAG ,,ACK'' Data 283 µs 868 µs NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs aaa-006987NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 39 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The most significant 7 bits of the storage size byte are interpreted as an unsigned integer value n. As a result, it codes the total available user memory size as 2n. If the least significant bit is 0b, the user memory size is exactly 2n. If the least significant bit is 1b, the user memory size is between 2n and 2n+1. The user memory for NTAG I²C 1k is 888 bytes. This memory size is between 512 bytes and 1024 bytes. Therefore, the most significant 7 bits of the value 13h, are interpreted as 9d, and the least significant bit is 1b. The user memory for NTAG I²C 2k is 1904 bytes. This memory size is between 1024 bytes and 2048 bytes. Therefore, the most significant 7 bits of the value 15h, are interpreted as 10d, and the least significant bit is 1b. 10.6 READ The READ command requires a start page address, and returns the 16 bytes of four NTAG I2C pages. For example, if address (Addr) is 03h then pages 03h, 04h, 05h, 06h are returned. Special conditions apply if the READ command address is near the end of the accessible memory area. For details on those cases and the command structure refer to Figure 23 and Table 19. Table 20 shows the required timing. Table 18. GET_VERSION response for NTAG I²C 1k and 2k Byte no. Description NTAG I²C 1k NTAG I²C 2k Interpretation 0 fixed Header 00h 00h 1 vendor ID 04h 04h NXP Semiconductors 2 product type 04h 04h NTAG 3 product subtype 05h 05h 50 pF I2C, Field detection 4 major product version 02h 02h 2 5 minor product version 01h 01h V1 6 storage size 13h 15h see following information 7 protocol type 03h 03h ISO/IEC 14443-3 compliant Fig 23. READ command CRC CRC NFC device Cmd Addr Data NTAG ,,ACK'' 368 µs 1548 µs NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs aaa-006988NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 40 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface [1] Refer to Section 10.2 “Timing”. In the initial state of NTAG I2C, all memory pages are allowed as Addr parameter to the READ command: • Page address from 00h to E2h and E8h for NTAG I²C 1k • Page address from 00h to FFh (sector 0h), from page 00h to E0h and E8h (sector 1h) for NTAG I²C 2k • SRAM buffer when Passthrough is ON Addressing a start memory page beyond the limits above results in a NAK response from NTAG I2C. In case a READ command addressing start with a valid memory area but extends over an invalid memory area, the content of the invalid memory area will be reported as 00h. 10.7 FAST_READ The FAST_READ command requires a start page address and an end page address and returns all n*4 bytes of the addressed pages. For example, if the start address is 03h and the end address is 07h, then pages 03h, 04h, 05h, 06h and 07h are returned. For details on those cases and the command structure, refer to Figure 24 and Table 21. Table 22 shows the required timing. Table 19. READ command Name Code Description Length Cmd 30h read four pages 1 byte Addr - start page address 1 byte CRC - CRC according to Ref. 1 2 bytes Data - Data content of the addressed pages 16 bytes NAK see Table 13 see Section 10.3 4-bit Table 20. READ timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut READ n=9[1] TTimeOut 5 msNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 41 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface [1] Refer to Section 10.2 “Timing”. In the initial state of NTAG I2C, all memory pages are allowed as StartAddr parameter to the FAST_READ command: • Page address from 00h to E2h and E8h for NTAG I²C 1k • Page address from 00h to FFh (sector 0h), from page 00h to E0h and E8h (sector 1h) for NTAG I²C 2k • SRAM buffer when Passthrough mode s ON If the start addressed memory page (StartAddr) is outside of accessible area, NTAG I2C replies a NAK. In case the FAST_READ command starts with a valid memory area but extends over an invalid memory area, the content of the invalid memory area will be reported as 00h. The EndAddr parameter must be equal to or higher than the StartAddr. Remark: The FAST_READ command is able to read out the entire memory of one sector with one command. Nevertheless, the receive buffer of the NFC device must be able to handle the requested amount of data as no chaining is possible. Fig 24. FAST_READ command Table 21. FAST_READ command Name Code Description Length Cmd 3Ah read multiple pages 1 byte StartAddr - start page address 1 byte EndAddr - end page address 1 byte CRC - CRC according to Ref. 1 2 bytes Data - data content of the addressed pages n*4 bytes NAK see Table 13 see Section 10.3 4-bit Table 22. FAST_READ timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut FAST_READ n=9[1] TTimeOut 5 ms CRC CRC NFC device Cmd StartAddr NTAG ,,ACK'' Data 453 µs depending on nr of read pages NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs EndAddr aaa-006989NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 42 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 10.8 WRITE The WRITE command requires a block address, and writes 4 bytes of data into the addressed NTAG I2C page. The WRITE command is shown in Figure 25 and Table 23. Table 24 shows the required timing. [1] Refer to Section 10.2 “Timing”. In the initial state of NTAG I2C, the following memory pages are valid Addr parameters to the WRITE command: • Page address from 02h to E2h, E8h and E9h (sector 0h) for NTAG I²C 1k • Page address from 02h to FFh (sector 0h), from 00h to E2h, E8h and E9h (sector 1h) for NTAG I²C 2k • SRAM buffer address in Passthrough mode Addressing a memory page beyond the limits above results in a NAK response from NTAG I2C. Pages that are locked against writing cannot be reprogrammed using any write command. The locking mechanisms include static and dynamic lock bits, as well as the locking of the configuration pages. Fig 25. WRITE command Table 23. WRITE command Name Code Description Length Cmd A2h write one page 1 byte Addr - page address 1 byte CRC - CRC according to Ref. 1 2 bytes Data - data 4 bytes NAK see Table 13 see Section 10.3 4-bit Table 24. WRITE timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut WRITE n=9[1] TTimeOut 10 ms NFC device Cmd Addr CRC NTAG ,,ACK'' 708 µs NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs ACK 57 µs Data aaa-006990NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 43 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 10.9 SECTOR SELECT The SECTOR SELECT command consists of two commands packet: the first one is the SECTOR SELECT command (C2h), FFh and CRC. Upon an ACK answer from the Tag, the second command packet needs to be issued with the related sector address to be accessed and 3 bytes RFU. To successfully access to the requested memory sector, the tag shall issue a passive ACK, which is sending NO REPLY for more than 1ms after the CRC of the second command set. The SECTOR SELECT command is shown in Figure 26 and Table 25. Table 26 shows the required timing. Fig 26. SECTOR_SELECT command Table 25. SECTOR_SELECT command Name Code Description Length Cmd C2h sector select 1 byte FFh - 1 byte CRC - CRC according to Ref. 1 2 bytes SecNo - Memory sector to be selected (00h-FEh) 1 byte NAK see Table 13 see Section 10.3 4-bit aaa-014051 NFC device Cmd FFh CRC SecNo 00h 00h 00h CRC 708 µs NTAG I2C ,,NAK'' NTAG I2C ,,ACK'' NTAG I2C ,,NAK'' NTAG I2C ,,ACK'' NAK Time out NFC device TTimeOut TNAK TACK 57 µs ACK 57 µs NAK <1ms >1ms 57 µs Passive ACK SECTOR SELECT packet 2 SECTOR SELECT packet 1 (any reply) (no reply)NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 44 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface [1] Refer to Section 10.2 “Timing”. Table 26. SECTOR_SELECT timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut SECTOR SELECT n=9[1] TTimeOut 10 msNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 45 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11. Communication and arbitration between RF and I²C interface If both interfaces are powered by their corresponding source, only one interface shall have access according to the "first-come, first-serve" principle. In NS_REG, the two status bits I2C_LOCKED and RF_LOCKED reflect the status of the NTAG I²C memory access and indicate which interface is locking the memory access. At power on, both bits are 0, setting the arbitration in idle mode. In the case arbiter locks to the I²C interface, an RF reader still can access the session registers. If the ISO state machine is in 'active' state, only the SECTOR SELECT command is allowed. But any other command requiring EEPROM access like READ or WRITE is handled as an illegal command and replied to with a special NAK value. In the case where the memory access is locked to the RF interface, the I²C host still can access the NFC register, by issuing a 'Register READ/WRITE' command. All other read or write commands will be replied to with a NACK to the I²C host. 11.1 Non Pass-through Mode PTHRU_ON_OFF = 0 (see Table 10) indicates non-Pass-through mode. 11.1.1 I²C interface access If the tag is in the IDLE or HALT state (RF state after POR or HALT-command) and the correct I²C slave address of NTAG I²C is specified following the START condition, bit I2C_LOCKED will be automatically set to “1b”. If I2C_LOCKED=,1 the I²C interface has access to the tag memory and the tag will respond with a NACK to any memory READ/WRITE command on the RF interface other than reading the register bytes command during this time. I2C_LOCKED must be either reset to 0 at the end of the I²C sequence or wait until the end of the watch dog timer. 11.1.2 RF interface access The arbitration will allow the RF interface to read and write accesses to EEPROM only when I2C_LOCKED is not set to “1b”. RF_LOCKED is automatically set to “1b” if the tag receives a valid command (EEPROM Access Commands) on the RF interface. If RF_LOCKED=1, the tag is locked to the RF interface and will not respond to any command from the I²C interface other than READ register command (see Table 10). RF_LOCKED is automatically set to 0 in one of the following conditions • At POR or if the RF field is switched off • If the tag is set to the HALT state with a HALT command on the RF interface • If the memory access command is finished on the RF interface When the RF interface has read the last page of the NDEF message specified in LAST_NDEF_BLOCK (see Table 9 and Table 10) the bit NDEF_DATA_READ - in the register NS_REG see Table 10 - is set to “1b” and indicates to the I²C interface that, for example, new NDEF data can be written. NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 46 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.2 SRAM buffer mapping with Memory Mirror enabled With SRAM_MIRROR_ON_OFF= 1, the SRAM buffer mirroring is enabled. This mode cannot be combined with the pass through mode (see Section 11.3). With the Memory Mirror enabled, the SRAM is now mapped into the User Memory from the RF interface perspective using the SRAM mirror lower page address specified in SRAM_MIRROR_BLOCK byte (Table 9 and Table 10). See Figure 27 (NTAG I²C 1k) and Figure 28(NTAG I²C 2k) for an illustration of this SRAM memory mapping when SRAM_MIRROR_BLOCK is set to 1h. The SRAM buffer will be then available in 2 locations: inside the User memory and at the end of the first or second memory sector (respectively NTAG I²C 1k or NTAG I²C 2k). The tag must be VCC powered to make this mode work, because without VCC, the SRAM will not be accessible via RF powered only. When mapping the SRAM buffer to the User Memory, the User shall be aware that all data written into the SRAM part of the User memory will be lost once the NTAG I²C is no longer powered from the I²C side (as SRAM is a volatile memory).NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 47 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 27. Illustration of the SRAM memory addressing via the RF interface (with Memory mirror enabled and SRAM_MIRROR_BLOCK set to 1h) for the NTAG I²C 1k aaa-012813 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 1h ...... 1 1h 2 2h 3 3h 4 4h 19 13h 225 E1h 226 E2h 227 E3h 228 E4h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 2h ...... Invalid access - returns NAK n.a. 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory SRAM memory (16 pages) with memory mirror mode enabled only with SRAM_MIRROR_BLOCK set to 1h READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. AccessNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 48 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.3 Pass-through mode PTHRU_ON_OFF = 1 (see Table 10) enables and indicates Pass-through mode. To handle large amount of data transfer from one interface to the other, NTAG I²C offers the Pass-through mode where data is transferred via a 64 byte SRAM buffer. This buffer offers fast write access and unlimited WRITE endurance as well as an easy handshake mechanism between the 2 interfaces. Fig 28. Illustration of the SRAM memory addressing via the RF interface (with Memory mirror enabled and SRAM_MIRROR_BLOCK set to 1h) for the NTAG I²C 2k aaa-012814 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 2h ...... 1 1h 1h 2 2h 3 3h 4 4h 19 13h 225 FFh 226 E2h 227 E3h 228 E4h 223 DFh 224 E0h 225 E1h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. Access 0 0h 1 1h ...... ...... SRAM memory (16 pages) with memory mirror mode enabled only with SRAM_MIRROR_BLOCK set to 1hNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 49 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface This buffer is mapped directly at the end of the sector 0h (NTAG I²C 1k) or sector 1h (NTAG I²C 2k) of the memory (from the RF interface perspective). In both cases, the principle of access to the SRAM buffer via the RF and I²C interface is exactly the same (see Section 11.3.2 and Section 11.3.3). The data flow direction must be set with the PTHRU_DIR bit (see Table 10) within the current communication session with the session registers (in this case, it can only be set via the I²C interfaces) or for the configuration bits after POR (in this case both RF and I²C interface can set it). This pass through direction settings avoids locking the memory access during the data transfer from one interface to the SRAM buffer. The pass-through mode can only be enabled when both interfaces are ON and only via the I²C interface via the bit PTHRU_ON_OFF located in the session registers NC_REG (see Section 8.3.11). In case one interface powers off, the pass-through mode is disabled automatically. 11.3.1 SRAM buffer mapping In Pass-through mode, the SRAM is mirrored to pages F0h to FFh sector 0h for the NTAG I²C 1k - see Figure 29 - or sector 1h for the NTAG I²C 2k - see Figure 30 - outside the User memory. The last page/block of the SRAM buffer (page 16) is used as the terminator page. Once the terminator page/block in the respective interfaces is read/written, the control would be transferred to other interface (RF/I²C) - see Section 11.3.2 and Section 11.3.3 for more details. Accordingly, the application can align on the Reader & Host side to transfer 16/32/48/64 bytes of data in one pass through step by only using the last blocks/page of the SRAM buffer. When using FAST_READ to read the SRAM buffer from RF, the EndAddress input of the FAST_READ command has to be always set to FFh.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 50 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 29. Illustration of the SRAM memory addressing via the RF interface in Pass-through mode for the NTAG I²C 1k aaa-012815 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 1h ...... 1 1h 2 2h 3 3h 4 4h 15 0Fh 225 E1h 226 E2h 227 E3h 228 E4h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh ... 240 F0h 255 FFh ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 2h ...... Invalid access - returns NAK n.a. 3h 0 0h Invalid access - returns NAK n.a. SRAM memory (16 pages) in Pass Through mode only READ&WRITE Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Invalid access - returns NAK n.a. Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. AccessNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 51 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.3.2 RF to I²C Data transfer If the RF interface is enabled (RF_LOCKED=1) and data is written to the terminator block/page of the SRAM via the RF interface, at the end of the WRITE command, bit SRAM_I2C_READY is set to 1 and bit RF_LOCKED is set to 0 automatically, and the NTAG I²C is locked to the I²C interface. Fig 30. Illustration of the SRAM memory addressing via the RF interface in Pass-through mode for the NTAG I²C 2k aaa-012816 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 2h ...... 1 1h 1h 2 2h 3 3h 4 4h 225 FFh 226 E2h 227 E3h 228 E4h 223 DFh 224 E0h 225 E1h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 235 EBh 236 ECh 237 EDh 238 EEh 239 EFh 240 F0h 255 FFh ...... ...... ...... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 3h 0 0h Invalid access - returns NAK n.a. SRAM memory (16 pages) in Pass Through mode only READ&WRITE. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. Access 0 0h 1 1h ...... ......NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 52 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface To signal to the host that data is ready to be read following mechanisms are in place: • The host polls/reads bit SRAM_I2C_READY from NS_REG (see Table 10) to know if data is ready in SRAM • A trigger on the "FD" pin indicates to the host that data is ready to be read from SRAM. This feature can be enabled by programming bits 5:2 (FD_OFF, FD_ON) of the NC_REG appropriately (see Table 9) This is illustrated in the Figure 31. If the tag is addressed with the correct I²C slave address, the I2C_LOCKED bit is automatically set to 1 (according to the interface arbitration). After a READ from the terminator page of the SRAM, bit SRAM_I2C_READY and bit I2C_LOCKED are automatically reset to 0, and the tag returns to the arbitration idle mode where, for example, further data from the RF interface can be transferred.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 53 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 31. Illustration of the Field detection feature in combination with the Pass Through mode for data transfer from RF to I²C aaa-012807 I 2C RF RF writing data to the SRAM buffer RF writing data to the SRAM buffer NDEF_DATA_READ 0b I2C_LOCKED 0b 0b RF_LOCKED 0b 1b SRAM_I2C_READY 0b 0b SRAM_RF_READY 0b EEPROM_WR_ERR 0b EEPROM_WR_BUSY 0b RF_FIELD_PRESENT 0b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF SRAM_MIRROR_ON_OFF PTHRU_DIR ON OFF HIGH LOW NC_REGFD_ON FD_OFF Last 4 bytes of SRAM written by RF Last 4 bytes of SRAM written by RF RF field switches ON RF field FD pin EVENT RF field switches OFF 1b 0b 0b 0b REGISTERS NS_REG 0b 1b 1b 0b 1b Last 16 bytes of SRAM read by I2C Last 16 bytes of SRAM read by I2C 0b 0b 1b 0b 1b 0b 1b 0b 0b 0b 0b 0b 1b 0b 1b 0b 0b 1b 1b 0b 0b 0b 0b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 1b Set data direction from RF to I2C + set FD for Switch ON Pass through modeNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 54 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.3.3 I²C to RF Data transfer If the I²C interface is enabled (I2C_LOCKED is 1) and data is written to the terminator page of the SRAM via the I²C interface, at the end of the WRITE command, bit SRAM_RF_READY is set to 1 and bit I2C_LOCKED is automatically reset to 0 to set the tag in the arbitration idle state. The RF_LOCKED bit is then automatically set to 1 (according to the interface arbitration). After a READ or FAST_READ command involving the terminator block/page of the SRAM, bit SRAM_RF_READY and bit RF_LOCKED are automatically reset to 0 allowing the I²C interface to further write data into the SRAM buffer. To signal to the host that further data is ready to be written, the following mechanisms are in place: • The RF interface polls/reads the bit SRAM_RF_READY from NS_REG (see Table 10) to know if new data has been written by the I²C interface in the SRAM • A trigger on the "FD" pin indicates to the host that data has been read from SRAM by the RF interface. This feature can be enabled by programming bits 5:2 (FD_OFF, FD_ON) of the NC_REG appropriately (see Table 9) The above mechanism is illustrated in the Figure 32.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 55 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 32. Illustration of the Field detection signal feature in combination with Pass-through mode for data transfer from I²C to RF aaa-012806 I 2C Switch ON Pass through mode I 2C writing data to the SRAM buffer I 2C writing data to the SRAM buffer RF NDEF_DATA_READ 0b 0b 0b I2C_LOCKED 0b 1b 0b 0b RF_LOCKED 0b 0b 0b 0b SRAM_I2C_READY 0b 0b 0b SRAM_RF_READY 0b 0b 0b 0b EEPROM_WR_ERR 0b 0b 0b EEPROM_WR_BUSY 0b 0b 0b RF_FIELD_PRESENT 0b 1b 0b I2C_RST_ON_OFF 0b 0b 0b PTHRU_ON_OFF 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b SRAM_MIRROR_ON_OFF 0b 0b 0b PTHRU_DIR 1b 0b 0b RF field switches OFF REGISTERS 16 bytes of SRAM read by RF 16 bytes of SRAM written by I2C 16 bytes of SRAM read by RF LOW HIGH ON OFF EVENT FD pin RF field NS_REG NC_REGFD_ON FD_OFF RF field switches ON 16 bytes of SRAM written by I2C 0b 0b 0b 0b 0b 0b 1b 1b 0b 0b 1b 1b 1b 1b 0b 0b 0b 1b 0b 1b 1b 1b 1b Set data direction from I 2C to RF + set FD for 1b 0b 1b 0b 0b 0b 0b 0b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 56 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 12. Limiting values Exceeding the limits of one or more values in reference may cause permanent damage to the device. Exposure to limiting values for extended periods may affect device reliability. [1] ANSI/ESDA/JEDEC JS-001; Human body model: C = 100 pF, R = 1.5 k. 13. Characteristics 13.1 Electrical characteristics [1] Stresses above one or more of the limiting values may cause permanent damage to the device. [2] These are stress ratings only. Operation of the device at these or any other conditions above those given in the Characteristics section of the specification is not implied. [3] Exposure to limiting values for extended periods may affect device reliability. Table 27. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage 2 - kV VFD Voltage on the FD pin - 3.6 V VSDA Voltage on the SDA line - 3.6 V VSCL Voltage on the SCL line - 3.6 V Table 28. Characteristics In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2][3] Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance LA - LB 44 50 56 pF fi input frequency - 13.56 - MHz Energy harvesting characteristics Vout voltage generated at the Vout pin - - 3.2 V I²C interface characteristics VCC supply voltage I²C on VCC input 1.8 3.6 V IDD supply current - 155 - A EEPROM characteristics tret retention time Tamb = 22 C 20 - - year Nendu(W) write endurance Tamb = 22 C 200000 - - cycleNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 57 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 14. Package outline Fig 33. Package outline SOT902-3 (XQFN8) Outline References version European projection Issue date IEC JEDEC JEITA SOT902-3 - - - - - - MO-255 sot902-3_po 11-08-16 11-08-18 Unit mm max nom min 0.5 0.05 0.00 1.65 1.60 1.55 1.65 1.60 1.55 0.6 0.5 0.1 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-3 A1 b 0.25 0.20 0.15 DE ee1 L 0.45 0.40 0.35 v w 0.05 y y1 0.05 0 1 2 mm scale terminal 1 index area D B A E X C y1 C y terminal 1 index area 3 L e1 e v AC B w C 2 1 5 6 7 metal area not for soldering 8 4 e1 e b A1 A detail XNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 58 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 15. Abbreviations 16. References [1] NFC Forum Tag 2 Type Operation, Technical Specification - NFC Forum, 31.05.2011, Version 1.1 [2] ISO/IEC 14443 - International Organization for Standardization [3] I2C-bus specification and user manual (NXP standard UM10204.pdf / Rev. 03 - 19 June 2007) [4] NFC Forum Activity, Technical Specification V1.1 Table 29. Pin description Pin no. Symbol Description 1 LA Antenna connection LA 2 VSS GND 3 SCL Serial Clock I2C 4 FD Field detection 5 SDA Serial data I2C 6 VCC VCC in connection (external power supply) 7 Vout Voltage out (energy harvesting) 8 LB Antenna connection LB Table 30. Abbreviations Acronym Description POR Power On ResetNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 59 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 17. Revision history Table 31. Revision history Document ID Release date Data sheet status Change notice Supersedes NT3H1101_1201 v. 3.1 20141009 Product data sheet - NT3H1101_1201 v. 3.0 Modifications: • Section 8.6 “Energy harvesting”: updated • Section 10.5 “GET_VERSION”: updated • Figure 31 and Figure 32: updated • Section 12 “Limiting values” and Section 13 “Characteristics”: remark removed NT3H1101_1201 v. 3.0 20140806 Product data sheet - NT3H1101_1201 v. 2.3 Modifications: • Section 8.6 “Energy harvesting” updated • Section 16 “References”: updated • Data sheet status changed to “Product data sheet” NT3H1101_1201 v. 2.3 20140708 Objective data sheet - NT3H1201_1101 v. 2.2 Modifications: • Figures updated • General update NT3H1101_1201 v. 2.2 20140306 Objective data sheet - NT3H1201_1101 v. 2.1 Modifications: • General updates NT3H1101_1201 v. 2.1 20131218 Objective data sheet - NT3H1201_1101 v. 2.0 Modifications: • Section 4 “Ordering information”: type number corrected NT3H1101_1201 v. 2.0 20131212 Objective data sheet NT3H1201 v. 1.4 Modifications: • Additional description for the Field detection functionality for Pass-through mode • General update NT3H1201 v. 1.4 20130802 Objective data sheet - NT3H1201 v. 1.3 Modifications: • Update for 1k memory version and RF commands NT3H1201 v. 1.3 20130613 Objective data sheet - Modifications: • Pinning package update NT3H1201 v. 1.0 NT3H1201 v. 1.0 20130425 Objective data sheet - -NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 60 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 61 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Licenses 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP Semiconductors N.V. I 2C-bus — logo is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards.NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 October 2014 265431 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.6 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Block description . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2.1 Data integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2.2 RF communication principle . . . . . . . . . . . . . . . 7 8.2.2.1 IDLE state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2.2.2 READY 1 state . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2.3 READY 2 state . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2.4 ACTIVE state . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2.5 HALT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.3 Memory organization . . . . . . . . . . . . . . . . . . . . 8 8.3.1 Memory map from RF interface . . . . . . . . . . . . 9 8.3.2 Memory map from I²C interface . . . . . . . . . . . 10 8.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3.4 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3.5 UID/serial number. . . . . . . . . . . . . . . . . . . . . . 13 8.3.6 Static lock bytes . . . . . . . . . . . . . . . . . . . . . . . 13 8.3.7 Dynamic Lock Bytes . . . . . . . . . . . . . . . . . . . . 14 8.3.8 Capability Container (CC bytes) . . . . . . . . . . . 16 8.3.9 User Memory pages . . . . . . . . . . . . . . . . . . . . 17 8.3.10 Memory content at delivery . . . . . . . . . . . . . . 18 8.3.11 NTAG I2C configuration and session registers 18 8.4 Configurable Field Detection Pin . . . . . . . . . . 24 8.5 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 28 8.6 Energy harvesting. . . . . . . . . . . . . . . . . . . . . . 29 9 I²C commands . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Start condition. . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 Soft reset feature . . . . . . . . . . . . . . . . . . . . . . 31 9.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . 31 9.5 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7 READ and WRITE Operation. . . . . . . . . . . . . 32 9.8 WRITE and READ register operation . . . . . . 34 10 RF Command . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 NTAG I2C command overview . . . . . . . . . . . . 36 10.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 NTAG ACK and NAK . . . . . . . . . . . . . . . . . . 37 10.4 ATQA and SAK responses. . . . . . . . . . . . . . . 37 10.5 GET_VERSION . . . . . . . . . . . . . . . . . . . . . . . 38 10.6 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.7 FAST_READ . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.8 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.9 SECTOR SELECT . . . . . . . . . . . . . . . . . . . . . 43 11 Communication and arbitration between RF and I²C interface . . . . . . . . . . . . . . . . . . . . 45 11.1 Non Pass-through Mode . . . . . . . . . . . . . . . . 45 11.1.1 I²C interface access . . . . . . . . . . . . . . . . . . . . 45 11.1.2 RF interface access . . . . . . . . . . . . . . . . . . . . 45 11.2 SRAM buffer mapping with Memory Mirror enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.3 Pass-through mode . . . . . . . . . . . . . . . . . . . . 48 11.3.1 SRAM buffer mapping . . . . . . . . . . . . . . . . . . 49 11.3.2 RF to I²C Data transfer . . . . . . . . . . . . . . . . . 51 11.3.3 I²C to RF Data transfer . . . . . . . . . . . . . . . . . 54 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 56 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56 13.1 Electrical characteristics . . . . . . . . . . . . . . . . 56 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 57 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 59 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 60 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 60 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 18.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19 Contact information . . . . . . . . . . . . . . . . . . . . 61 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series. For additional documentation, see Section 19 “References”. 2. Features and benefits  ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included.  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  On-chip SRAM includes:  32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.5 — 24 June 2014 Product data sheetLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 2 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller  Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.  Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays.  Split APB bus allows high throughput with few stalls between the CPU and DMA.  Serial interfaces:  Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.)  USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.)  Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.  CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)  SPI controller with synchronous, serial, full duplex communication and programmable data length.  Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.  Three enhanced I2C bus interfaces, one with an open-drain output supporting full I 2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I 2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.)  Other peripherals:  70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.  12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.  10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2)  Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.  One motor control PWM with support for three-phase motor control.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 3 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller  Quadrature encoder interface that can monitor one external quadrature encoder.  One standard PWM/timer block with external count input.  RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.  WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.  ARM Cortex-M3 system tick timer, including an external clock input option.  Repetitive interrupt timer provides programmable and repeating timed interrupts.  Each peripheral has its own clock divider for further power savings.  Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.  Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.  Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Single 3.3 V power supply (2.4 V to 3.6 V).  Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.  Non-maskable Interrupt (NMI) input.  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock.  The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).  Brownout detect with separate threshold for interrupt and forced reset.  Power-On Reset (POR).  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.  USB PLL for added flexibility.  Code Read Protection (CRP) with different security levels.  Unique device serial number for identification purposes.  Available as LQFP100 (14 mm  14 mm  1.4 mm), TFBGA1001 (9 mm  9 mm  0.7 mm), and WLCSP100 (5.074  5.074  0.6 mm) package. 1. LPC1768/65 only.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 4 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 3. Applications 4. Ordering information 4.1 Ordering options  eMetering  Alarm systems  Lighting  White goods  Industrial networking  Motor control Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074  5.074  0.6 mm - LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 Table 2. Ordering options Type number Flash SRAM in kB Ethernet USB CAN I 2S DAC Maximum CPU operating frequency CPU AHB SRAM0 AHB SRAM1 Total LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768UK 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHzLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 5 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Table 3. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘B’ Third device revisionLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 6 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 6. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 32/64 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128 kB DMA CONTROLLER ETHERNET CONTROLLER WITH DMA(1) USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS XTAL1 XTAL2 RESET clocks and controls JTAG interface debug port USB PHY SSP0 UART2/3 I2S(1) I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM QUADRATURE ENCODER SSP1 UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT PWM1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS 32 kHz OSCILLATOR APB slave group 1 APB slave group 0 DAC(1) RTC POWER DOMAIN LPC1769/68/67/ 66/65/64/63 master master master 002aad944 slave slave slave slave slave ROM slave MULTILAYER AHB MATRIX P0 to P4 SDA2 SCL2 SCK0 SSEL0 MISO0 MOSI0 SCK1 SSEL1 MISO1 MOSI1 RXD2/3 TXD2/3 PHA, PHB INDEX EINT[3:0] AOUT MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT 4 × MAT2 2 × MAT3 2 × CAP2 2 × CAP3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1 RTCX2 VBAT PWM1[7:0] 2 × MAT0/1 2 × CAP0/1 RD1/2 TD1/2 SDA0/1 SCL0/1 AD0[7:0] SCK/SSEL MOSI/MISO 8 × UART1 RXD0/TXD0 P0, P2 PCAP1[1:0] RMII pins USB pins CLKOUT MPU = connected to DMALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 7 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package LPC176xFBD100 50 1 25 75 51 26 76 100 002aad945 002aaf723 LPC1768/65FET100 Transparent top view J G K H F E D C B A 13579 2 4 6 8 10 ball A1 index areaLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 8 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 4. Pin configuration WLCSP100 package Transparent top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 LPC1768UK bump A1 index area aaa-009522 Table 4. Pin allocation table TFBGA100 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 11 - 12 - Row B 1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - Row D 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] 11 - 12 - Row E 1 VSSA 2 VDDA 3 VREFP 4 n.c. 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 7 P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/ RI1/TRACECLKLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 9 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ RXD2 8 P0[16]/RXD1/ SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin SymbolLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 10 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Row J 1 P0[28]/SCL0/ USB_SCL 2 P0[27]/SDA0/ USB_SDA 3 P0[29]/USB_D+ 4 P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 5 P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 6 VSS 7 P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 8 P0[1]/TD1/RXD3/SCL1 9 P2[13]/EINT3/ I2STX_SDA 10 P2[10]/EINT0/NMI 11 - 12 - Row K 1 P3[26]/STCLK/ MAT0[1]/PWM1[3] 2 VDD(3V3) 3 VSS 4 P1[20]/MCI0/ PWM1[2]/SCK0 5 P1[23]/MCI1/ PWM1[4]/MISO0 6 P1[26]/MCOB1/ PWM1[6]/CAP0[0] 7 P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 8 P0[0]/RD1/TXD3/SDA1 9 P0[11]/RXD2/ SCL2/MAT3[1] 10 P2[12]/EINT2/ I2STX_WS 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 5. Pin description Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ SDA1 46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). O TXD3 — Transmitter output for UART3. I/O SDA1 — I 2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ SCL1 47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). I RXD3 — Receiver input for UART3. I/O SCL1 — I 2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 11 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). I CAP2[1] — Capture input for Timer 2, channel 1. P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ I2STX_WS/ MISO1/MAT2[2] 77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ SDA2/MAT3[0] 48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I 2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 12 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[11]/RXD2/ SCL2/MAT3[1] 49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I 2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ SSEL0/SSEL 63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ MISO0/MISO 61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ MOSI0/MOSI 60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ SDA1 59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I/O SDA1 — I 2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I 2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 13 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] 8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ AOUT/RXD3 6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output (LPC1769/68/67/66/65/63 only). I RXD3 — Receiver input for UART3. P0[27]/SDA0/ USB_SDA 25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I 2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O USB_SDA — USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28]/SCL0/ USB_SCL 24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I 2C0 clock input/output. Open-drain output (for I2C-bus compliance). I/O USB_SCL — USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 14 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ ENET_TXD0 95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1]/ ENET_TXD1 94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4]/ ENET_TX_EN 93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8]/ ENET_CRS 92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only). P1[9]/ ENET_RXD0 91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[10]/ ENET_RXD1 90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[14]/ ENET_RX_ER 89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15]/ ENET_REF_CLK 88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16]/ ENET_MDC 87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17]/ ENET_MDIO 86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 15 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0] 32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. (LPC1769/68/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1769/68/66/65 only). I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/MCI0/ PWM1[2]/SCK0 34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/MCABORT/ PWM1[3]/ SSEL0 35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ PWM1[4]/MISO0 37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ PWM1[5]/MOSI0 38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 16 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[25]/MCOA1/ MAT1[1] 39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/MCOB1/ PWM1[6]/CAP0[0] 40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin. O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65 only). I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ PCAP1[1]/ MAT0[1] 45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ TXD1 75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ RXD1 74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 17 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3] 73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2] 70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1] 69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0] 68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ RI1/TRACECLK 67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). O TXD2 — Transmitter output for UART2. P2[9]/ USB_CONNECT/ RXD2 64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 18 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[11]/EINT1/ I2STX_CLK 52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12]/EINT2/ I2STX_WS 51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13]/EINT3/ I2STX_SDA 50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin. I EINT3 — External interrupt 3 input. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25]/MAT0[0]/ PWM1[2] 27 H3 D8 [1] I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/STCLK/ MAT0[1]/PWM1[3] 26 K1 A10 [1] I/O P3[26] — General purpose digital input/output pin. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28]/RX_MCLK/ MAT2[0]/TXD3 82 C7 G1 [1] I/O P4[28] — General purpose digital input/output pin. O RX_MCLK — I 2S receive master clock. (LPC1769/68/67/66/65 only). O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/TX_MCLK/ MAT2[1]/RXD3 85 E6 F1 [1] I/O P4[29] — General purpose digital input/output pin. O TX_MCLK — I 2S transmit master clock. (LPC1769/68/67/66/65 only). O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 19 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller TDO/SWO 1 A1 A1 [1][7] O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. TDI 2 C3 C4 [1][8] I TDI — Test Data in for JTAG interface. TMS/SWDIO 3 B1 B3 [1][8] I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 4 C2 A2 [1][8] I TRST — Test Reset for JTAG interface. TCK/SWDCLK 5 C1 D4 [1][7] I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RTCK 100 B2 B2 [1][7] O RTCK — JTAG interface control signal. RSTOUT 14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. RESET 17 F3 C6 [9] I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22 H2 D7 [10][11] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23 G3 A9 [10][11] O Output from the oscillator amplifier. RTCX1 16 F2 A7 [10][11] I Input to the RTC oscillator circuit. RTCX2 18 G1 B7 [10] O Output from the RTC oscillator circuit. VSS 31, 41, 55, 72, 83, 97 B3, B7, C9, G7, J6, K3 E5, F5, F6, G5, G6, G7 [10] I ground: 0 V reference. VSSA 11 E1 B5 [10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, 71, 96 K2, H9, C10 , A3 E4, E6, F7, G4 [10] I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(REG)(3V3) 42, 84 H6, A7 F4, F0 [10] I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. VDDA 10 E2 A4 [10] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFP 12 E3 A5 [10] I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 20 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. VREFN 15 F1 A6 I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19 G2 A8 [10][12] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. n.c. 13 D4, E4 B6, D6 - not connected. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 21 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 8.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 8.3 On-chip flash program memory The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 8.4 On-chip SRAM The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 8.5 Memory Protection Unit (MPU) The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 22 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 8.6 Memory map The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 23 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2. Fig 5. LPC17xx memory map 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 C000 0x5020 0000 0x5001 0000 AHB peripherals Ethernet controller(1) USB controller(1) reserved 127- 4 reserved GPDMA controller 0 1 2 3 APB0 peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 WDT 0x4000 0000 timer 0 timer 1 UART0 UART1 reserved reserved SPI RTC + backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM(1) CAN AF registers(1) CAN common(1) CAN1(1) CAN2(1) 22 - 19 reserved I2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 reserved reserved 32 kB local SRAM (LPC1769/8/7/6/5/3) 16 kB local SRAM (LPC1764) reserved reserved private peripheral bus 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x0004 0000 0x0002 0000 0x0008 0000 0x1000 4000 0x1000 0000 0x1000 8000 0x1FFF 0000 0x1FFF 2000 0x2008 0000 0x2007 C000 0x2008 4000 0x2200 0000 0x200A 0000 0x2009 C000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved GPIO reserved reserved reserved reserved APB0 peripherals AHB peripherals APB1 peripherals AHB SRAM bit-band alias addressing peripheral bit-band alias addressing 16 kB AHB SRAM1 (LPC1769/8/7/6/5) 16 kB AHB SRAM0 256 kB on-chip flash (LPC1766/65/63) 128 kB on-chip flash (LPC1764) 512 kB on-chip flash (LPC1769/8/7) PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aad946 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC(1) timer 2 timer 3 UART2 UART3 reserved I2S(1) I2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 reserved repetitive interrupt timer 11 12 reserved motor control PWM 30 - 16 reserved 13 14 15 31 system control QEI LPC1769/68/67/66/65/64/63LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 24 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC17xx, the NVIC supports 33 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • Non-Maskable Interrupt (NMI) • Software interrupt generation 8.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 8.8 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 8.9 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers. Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 25 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 8.10 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 26 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 8.11 Ethernet Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 8.11.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 27 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 8.12 USB interface Remark: The USB controller is available as device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 15.1. 8.12.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. 8.12.1.1 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 28 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 8.12.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification. 8.12.2.1 Features • OHCI compliant. • One downstream port. • Supports port power switching. 8.12.3 USB OTG controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I 2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver. 8.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 8.13 CAN controller and acceptance filters Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 29 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 8.14 12-bit ADC The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support. 8.14.1 Features • 12-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range VREFN to VREFP. • 12-bit conversion rate: 200 kHz. • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 8.15 10-bit DAC The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. 8.15.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA supportLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 30 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 8.16.1 Features • Maximum UART data bit rate of 6.25 Mbit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • Support for RS-485/9-bit/EIA-485 mode (UART1). • UART3 includes an IrDA mode to support infrared communication. • All UARTs have DMA support. 8.17 SPI serial I/O controller The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 8.17.1 Features • Maximum SPI data bit rate of 12.5 Mbit/s • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 8.18 SSP serial I/O controller The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 31 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.1 Features • Maximum SSP speed of 33 Mbit/s (master) or 8 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 8.19 I2C-bus serial I/O controllers The LPC17xx each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 8.19.1 Features • I 2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • I 2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 32 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.20 I2S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. The I2S-bus provides a standard communication interface for digital audio applications. The I 2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 8.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 8.21 General purpose 32-bit timers/external event counters The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.21.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 33 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 8.22.1 Features • One PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 34 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 8.23 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 8.24 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 8.24.1 Features • Tracks encoder position. • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 35 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.25.1 Features • 32-bit counter running from PCLK. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.26 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be clocked from the internal AHB clock or from a device pin. 8.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 8.27.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  232  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC) oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 36 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC17xx is powered off. The RTC includes an alarm function that can wake up the LPC17xx from all reduced power modes with a time resolution of 1 s. 8.28.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 8.29 Clocking and power control 8.29.1 Crystal oscillators The LPC17xx include three independent oscillators. These are the main oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 37 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller See Figure 6 for an overview of the LPC17xx clock generation. 8.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.29.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 8.29.2 for additional information. 8.29.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU. Fig 6. LPC17xx clocking generation block diagram MAIN OSCILLATOR INTERNAL RC OSCILLATOR RTC OSCILLATOR MAIN PLL WATCHDOG TIMER REAL-TIME CLOCK CPU CLOCK DIVIDER PERIPHERAL CLOCK GENERATOR USB BLOCK ARM CORTEX-M3 ETHERNET BLOCK DMA GPIO NVIC USB CLOCK DIVIDER system clock select (CLKSRCSEL) USB clock config (USBCLKCFG) CPU clock config (CCLKCFG) pllclk CCLK/8 CCLK/6 CCLK/4 CCLK/2 CCLK pclkWDT rtclk = 1Hz usbclk (48 MHz) cclk USB PLL USB PLL enable main PLL enable 32 kHz APB peripherals LPC17xx 002aad947LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 38 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 8.29.3 USB PLL (PLL1) The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle. 8.29.4 RTC clock output The LPC17xx feature a clock output function intended for synchronizing with external devices and for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results. 8.29.5 Wake-up timer The LPC17xx begin operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 39 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 8.29.6 Power control The LPC17xx support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC17xx also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 8.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 40 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 8.29.6.3 Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 8.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 8.29.6.5 Wake-up interrupt controller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 8.29.7 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 41 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC17xx application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 42 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30 System control 8.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 8.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 7. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aad978 RTCX1 VBAT VDD(REG)(3V3) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VREFN VSSA LPC17xx ULTRA LOW-POWER REGULATOR POWER SELECTORLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 43 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 8.30.3 Code security (Code Read Protection - CRP) This feature of the LPC17xx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. 8.30.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 44 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 8.30.6 External interrupt inputs The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 8.30.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC17xx is configured for 128 total interrupts. 8.31 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 45 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 8. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 19 for maximum operating voltage. [4] Including voltage on outputs in 3-state mode. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD  2.4 V [2][4] 0.5 +5.5 VI VDD = 0 V 0.5 +3.6 5 V tolerant open-drain pins PIO0_27 and PIO0_28 [2][5] 0.5 +5.5 IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature [6] 65 +150 C Tj(max) maximum junction temperature 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 VLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 46 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C) • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal resistance (15 %) Symbol Parameter Conditions Max/Min Unit LQFP100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 38.01 C/W Single-layer (4.5 in  3 in); still air 55.09 C/W Rth(j-c) thermal resistance from junction to case 9.065 C/W TFBGA100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 55.2 C/W Single-layer (4.5 in  3 in); still air 45.6 C/W Rth(j-c) thermal resistance from junction to case 9.5 C/W Tj Tamb PD Rth j a   – +=   LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 47 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3][4] 2.5 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled; PCLK = CCLK⁄ 8 CCLK = 12 MHz; PLL disabled [6][7] - 7- mA CCLK = 100 MHz; PLL enabled [6][7] - 42- mA CCLK = 100 MHz; PLL enabled (LPC1769) [6][8] - 50- mA CCLK = 120 MHz; PLL enabled (LPC1769) [6][8] - 67- mA sleep mode [6][9] - 2- mA deep sleep mode [6][10] - 240 - A power-down mode [6][10] - 31 - A deep power-down mode; RTC running [11] - 630- nA IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present [12] - 530- nA VDD(REG)(3V3) not present [13] - 1.1 - A IDD(IO) I/O supply current deep sleep mode [14][15] - 40- nA power-down mode [14][15] - 40- nA deep power-down mode [14] - 10- nALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 48 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller IDD(ADC) ADC supply current active mode; ADC powered [16][17] - 1.95- mA ADC in Power-down mode [16][18] - <0.2 - A deep sleep mode [16] - 38- nA power-down mode [16] - 38- nA deep power-down mode [16] - 24- nA II(ADC) ADC input current on pin VREFP deep sleep mode [19] - 100- nA power-down mode [19] - 100- nA deep power-down mode [19] - 100- nA Standard port pins, RESET, RTCK IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [20][21] [22] 0- 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3) --V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3)  0.4 --V VOL LOW-level output voltage IOL = 4 mA --0.4 V IOH HIGH-level output current VOH = VDD(3V3)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4- - mA IOHS HIGH-level short-circuit output current VOH =0V [23] - - 45 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [23] --50 mA Ipd pull-down current VI =5V 10 50 150 A Ipu pull-up current VI =0V 15 50 85 A VDD(3V3) < VI <5V 0 0 0 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max UnitLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 49 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  VDD((3V3)  3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] VDDA for DAC specs are from 2.7 V to 3.6 V. I 2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3) --V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05  VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA --0.4 V ILI input leakage current VI = VDD(3V3) [24] - 24 A VI =5V - 10 22 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V USB pins (LPC1769/68/66/65/64 only) IOZ OFF-state output current 0V> NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 21 8.1 Architectural overview . . . . . . . . . . . . . . . . . . 21 8.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 21 8.3 On-chip flash program memory . . . . . . . . . . . 21 8.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Memory Protection Unit (MPU). . . . . . . . . . . . 21 8.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 Nested Vectored Interrupt Controller (NVIC) . 24 8.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24 8.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24 8.9 General purpose DMA controller . . . . . . . . . . 24 8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10 Fast general purpose parallel I/O . . . . . . . . . . 25 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 27 8.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 28 8.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 28 8.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 CAN controller and acceptance filters . . . . . . 28 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 30 8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 30 8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . 31 8.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 32 8.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 33 8.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 34 8.24 Quadrature Encoder Interface (QEI) . . . . . . . 34 8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 35 8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.26 ARM Cortex-M3 system tick timer . . . . . . . . . 35 8.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 35 8.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.28 RTC and backup registers . . . . . . . . . . . . . . . 36 8.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.29 Clocking and power control . . . . . . . . . . . . . . 36 8.29.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36 8.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 37 8.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 38 8.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 38 8.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 40 8.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 40 8.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 40 8.29.7 Peripheral power control . . . . . . . . . . . . . . . . 40 8.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 41 8.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 43 8.30.3 Code security (Code Read Protection - CRP) 43 8.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 44 8.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 44 8.30.7 Memory mapping control . . . . . . . . . . . . . . . . 44 8.31 Emulation and debugging . . . . . . . . . . . . . . . 44 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Thermal characteristics . . . . . . . . . . . . . . . . . 46NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 June 2014 Document identifier: LPC1769_68_67_66_65_64_63 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 47 11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 50 11.2 Peripheral power consumption . . . . . . . . . . . . 53 11.3 Electrical pin characteristics . . . . . . . . . . . . . . 54 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 56 12.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 57 12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.6 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 59 12.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 63 12.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13 ADC electrical characteristics . . . . . . . . . . . . 66 14 DAC electrical characteristics . . . . . . . . . . . . 69 15 Application information. . . . . . . . . . . . . . . . . . 70 15.1 Suggested USB interface solutions . . . . . . . . 70 15.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 74 15.4 Standard I/O pin configuration . . . . . . . . . . . . 75 15.5 Reset pin configuration. . . . . . . . . . . . . . . . . . 76 15.6 ElectroMagnetic Compatibility (EMC). . . . . . . 77 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 83 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 20 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 84 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 86 21.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 86 21.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 87 22 Contact information. . . . . . . . . . . . . . . . . . . . . 87 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1. General description NXP’s UCODE G2iM series transponder ICs offers in addition to the leading-edge read range features such as a Tag Tamper Alarm, Data Transfer, Digital Switch, advanced privacy-protection modes and a 640 bit configurable User Memory. Very high chip sensitivity (17.5 dBm) enables longer read ranges with simple, single-port antenna designs. In fashion and retail the UCODE G2iM series improve read rates and provide for theft deterrence. In the electronic device market, they are ideally suited for device configuration, activation, production control and PCB tagging. In authentication applications, they protect brands and guard against counterfeiting. They can also be used to tag containers, electronic vehicles, airline baggage, and more. In addition to the EPC specifications the UCODE G2iM offers an integrated Product Status Flag (PSF) feature and read protection of the memory content. The UCODE G2iM+ offers on top of the UCODE G2iM features an integrated tag tamper alarm, digital switch, external supply mode, data transfer mode and real read range reduction. A special feature is the conditional, automatic real read range reduction, where the activation condition can be defined by the user, is newly introduced in the UCODE G2iM+. When connected to a power supply, the READ as well as the WRITE range can be boosted to a sensitivity of 27 dBm. The UCODE G2iM+ also allows the segmentation of the 640 bit User Memory in up to three segments (open, protected, private) with different access levels (Access- and User Password). For applications which require a longer EPC number the UCODE G2iM+ offers the possibility of up to 448 bit. 2. Features and benefits 2.1 Key features  UHF RFID Gen2 tag chip according EPCglobal v1.2.0  256 bit EPC for UCODE G2iM and up to 448 bit EPC for UCODE G2iM+  Up to 640 bit User Memory which can be segmented in the UCODE G2iM+  Private User Memory area protected by special User Password  Memory read protection  Integrated Product Status Flag (PSF)  Tag tamper alarm  Digital switch  Data transfer mode SL3S1003_1013 UCODE G2iM and G2iM+ Rev. 3.6 — 17 October 2014 201236 Product data sheet COMPANY PUBLICSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 2 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+  Real Read Range Reduction (Privacy Mode)  Conditional Real Read Range Reduction  External supply mode  Long read/write ranges due to extremely low power design  Reliable operation of multiple tags due to advanced anti-collision  Broad international operating frequency: from 840 MHz to 960 MHz  Data retention: 20 years  Wide specified temperature range: 40 C up to +85 C 2.1.1 Memory  256 bit of EPC memory / up to 448 bit in G2iM+  96 bit Tag IDentifier (TID) including 48-bit factory locked unique serial number  112 bit User TID memory  32 bit Kill Password to permanently disable the tag  32 bit Access Password to allow a transition into the secured state  32 bit User Password to allow access to the private user memory segment  Read protection  BlockWrite (32 bit)  Write Lock  BlockPermalock 2.2 Key benefits 2.2.1 End user benefit  Outstanding User Memory size of 640 bit  Prevention of unauthorized memory access through different levels of read protection  Indication of tag tampering attempt by use of the tag tamper alarm feature  Electronic device configuration and / or activation by the use of the digital switch / data transfer mode  Theft deterrence supported by the PSF feature (PSF alarm or EPC code)  Small label sizes, long read ranges due to high chip sensitivity  Product identification through unalterable TID range, including a 48 bit serial number  Reliable operation in dense reader and noisy environments through high interference suppression 2.2.2 Antenna design benefits  High sensitivity enables small and cost efficient antenna designs  Low Q-Value eases broad band antenna design for global usage 2.2.3 Label manufacturer benefit  Consistent performance on different materials due to low Q-factor  Ease of assembly and high assembly yields through large chip input capacitance and Polyimide spacer  Fast first WRITE or BLOCKWRITE of the EPC memory for fast label initializationSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 3 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 2.3 Custom commands  PSF Alarm Built-in PSF (Product Status Flag), enables the UHF RFID tag to be used as EAS tag (Electronic Article Surveillance) tag without the need for a back-end data base.  Read Protect Protects all memory content from unauthorized reading.  ChangeConfig Configures the additional features of the chip like external supply mode, tamper alarm, digital switch, read range reduction, privacy mode activation condition or data transfer. The UCODE G2iM+ is equipped with a number of additional features. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. No custom commands are needed to take advantage of all the features in case of unlocked EPC memory. 3. Applications 3.1 Markets  Fashion (apparel and footwear)  Retail  Electronics  Fast moving consumer goods  Asset management  Electronic vehicle identification 3.2 Applications  Supply chain management  Item level tagging  Pallet and case tracking  Container identification  Product authentication  PCB tagging  Cost efficient, low level seals  Wireless firmware download  Wireless product activationSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 4 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 4. Ordering information 5. Marking Table 1. Ordering information Type number Package Name IC type Description Version SL3S1003FUD/BG Wafer G2iM bumped G2iM die on sawn 8” 120 mm wafer, 7 mm Polyimide spacer not applicable SL3S1013FUD/BG Wafer G2iM+ bumped G2iM+ die on sawn 8” 120 mm wafer, 7 mm Polyimide spacer not applicable SL3S1013FTB0 XSON6 G2iM+ plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886F1 Table 2. Marking codes Type number Marking code Comment Version SL3S1013FTB0 US UCODE G2iM+ SOT886SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 5 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 6. Block diagram The SL3S10x3 IC consists of three major blocks: - Analog Interface - Digital Control - EEPROM The analog part provides stable supply voltage and demodulates data received from the reader for being processed by the digital part. Further, the modulation transistor of the analog part transmits data back to the reader. The digital section includes the state machines, processes the protocol and handles communication with the EEPROM, which contains the EPC and the user data. Fig 1. Block diagram of SL3S10x3 IC 001aam226 MOD DEMOD VREG VDD VDD data in data out R/W ANALOG RF INTERFACE PAD PAD RECT DIGITAL CONTROL ANTENNA ANTICOLLISION READ/WRITE CONTROL ACCESS CONTROL EEPROM INTERFACE CONTROL RF INTERFACE CONTROL I/O CONTROL I/O CONTROL EEPROM MEMORY SEQUENCER CHARGE PUMP PAD OUT PADSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 6 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 7. Pinning information 7.1 Pin description Fig 2. Pinning bare die Fig 3. Pin configuration for SOT886 001aan572 VDD OUT RFN RFP NXP trademark SL3S10x3FTB0 n.c. aaa-001689 RFP RFN n.c. VDD OUT Transparent top view 2 3 1 5 4 6 Table 3. Pin description bare die Symbol Description OUT output pin RFN grounded antenna connector VDD external supply RFP ungrounded antenna connector Table 4. Pin description SOT886 Pin Symbol Description 1 RFP ungrounded antenna connector 2 n.c. not connected 3 RFN grounded antenna connector 4 OUT output pin 5 n.c. not connected 6 VDD external supplySL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 7 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 8. Wafer layout 8.1 Wafer layout (1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m) (2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m) (3) Chip step, x-length: 615 m (4) Chip step, y-length: 475 m (5) Bump to bump distance X (OUT - RFN): 513 m (6) Bump to bump distance Y (RFN - RFP): 333 m (7) Distance bump to metal sealring X: 43,5 m (outer edge - top metal) (8) Distance bump to metal sealring (RFP, VDD) Y: 40,3 m (9) Distance bump to metal sealring (RFN, OUT) Y: 80,3 m Bump size X  Y: 60 m ´ 60 m Remark: OUT and VDD are used with G2iM+ only Fig 4. SL3S10x3 wafer layout not to scale! 001aan642 (1) (7) (2) (8) (5) (6) (4) (3) Y X VDD (9) OUT RFN RFPSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 8 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 9. Mechanical specification The SL3S10x3 wafers are offered with 120 mm thickness and 7mm Polyimide spacer. This robust structure with the enhanced Polyimide spacer supports easy assembly due to low assembly variations. 9.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**”. 9.1.1 Wafer Table 5. Specifications Wafer Designation each wafer is scribed with batch number and wafer number Diameter 200 mm (8”) Thickness 120 m 15 m Number of pads 4 Pad location non diagonal/ placed in chip corners Distance pad to pad RFN-RFP 333.0 µm Distance pad to pad OUT-RFN 513.0 µm Process CMOS 0.14 mm Batch size 25 wafers Potential good dies per wafer 100544 Wafer backside Material Si Treatment ground and stress release Roughness Ra max. 0.5 m, Rt max. 5 m Chip dimensions Die size including scribe 0.615 mm  0.475 mm = 0.292 mm2 Scribe line width: x-dimension = 15 m y-dimension = 15 m Passivation on front Type Sandwich structure Material PE-Nitride (on top) Thickness 1.75 m total thickness of passivation Polyimide spacer 7 m Au bump Bump material > 99.9% pure Au Bump hardness 35 – 80 HV 0.005 Bump shear strength > 70 MPa Bump height 25 m[1] Bump height uniformitySL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 9 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ [1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer. 9.1.2 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 9.1.3 Map file distribution See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” – within a die  2 m – within a wafer  3 m – wafer to wafer  4 m Bump flatness 1.5 m Bump size – RFP, RFN 60  60 m – OUT, VDD 60  60 m Bump size variation  5 m Table 5. Specifications …continuedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 10 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10. Functional description 10.1 Air interface standards The UCODE G2iM fully supports all parts of the "Specification for RFID Air Interface EPCglobal, EPCTM Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 10.2 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE G2iM. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the UCODE G2iM on the tag. The UCODE G2iM+ can also be supplied externally. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. The antenna attached to the chip may use a DC connection between the two antenna pads which also enables loop antenna design. 10.3 Data transfer 10.3.1 Reader to tag Link An interrogator transmits information to the UCODE G2iM by modulating an UHF RF signal. The UCODE G2iM receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. In order to further improve the read range the UCODE G2iM can be externally supplied as well so the energy to operate the chip does not need to be transmitted by the reader. An interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. It communicates to the UCODE G2iM by modulating an RF carrier using DSB-ASK with PIE encoding. For further details refer to Section 17, Ref. 1. Interrogator-to-tag (R=>T) communications. 10.3.2 Tag to reader Link An interrogator receives information from a UCODE G2iM by transmitting an unmodulated RF carrier and listening for a backscattered reply. The UCODE G2iM backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. The UCODE G2iM communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subcarrier.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 11 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.4 UCODE G2iM and UCODE G2iM+ differences The UCODE G2iM is tailored for application where EPC or TID number space, and User Memory is needed. The UCODE G2iM+ provides beside the segmented memory additional functionality such as tag tamper alarm, external supply operation to further boost read/write range (external supply mode), a privacy mode reducing the read range where the activation criteria (open or short) can be defined or I/O functionality (data transfer to externally connected devices) where required. The following table provides an overview of UCODE G2iM, UCODE G2iM+ special features. 10.5 Supported commands The UCODE G2iM supports all mandatory EPCglobal V1.2.0 commands. In addition the UCODE G2iM supports the following optional commands: • ACCESS • BlockWrite (32 bit) • BlockPermalock The UCODE G2iM features the following custom commands described more in detail later: • ResetReadProtect (backward compatible to UCODE G2X; UCODE G2iL) • ReadProtect(backward compatible to UCODE G2X; UCODE G2iL) • ChangeEAS (backward compatible to UCODE G2X; UCODE G2iL) • EAS_Alarm(backward compatible to UCODE G2X; UCODE G2iL) • ChangeConfig(backward compatible to UCODE G2iL) Table 6. Overview of UCODE G2iM and UCODE G2iM+ features Features UCODE G2iM UCODE G2iM+ Read protection (bankwise) yes yes PSF (Built-in Product Status Flag) yes yes Backscatter strength reduction yes yes BlockWrite (32 bit) yes yes BlockPermalock yes yes User TID (112 bit) yes yes Segmented user memory (open, protected, private) - yes Additional User Password for private memory - yes EPC size selectable (448bit max.) - yes Tag tamper alarm - yes Digital switch / Digital input - yes External supply mode - yes Data transfer - yes Real read range reduction - yes Conditional Real Read Range Reduction - yesSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 12 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.6 UCODE G2iM and UCODE G2iM+ memory The UCODE G2iM and UCODE G2iM+ memory is implemented according EPCglobal Class1Gen2 and organized in four banks: The logical address of all memory banks begin at zero (00h). In addition to the four memory banks two configuration words are available. The first to handle the UCODE G2iM memory configuration (Mem-Config-Word) is available at EPC bank 01 address 1F0h and the second to handle UCODE G2iM specific features Config-Word) is available at EPC bank 01 address 200h. The configuration words are described in detail in Section 10.7.1 “ChangeConfig” and Section 10.7.3 “UCODE G2iM+ memory configuration control mechanism”. Memory pages (16 bit words) pre-programmed to zero will not execute an erase cycle before writing data to it. This approach accelerates initialization of the chip and enables faster programming of the memory. Table 7. UCODE G2iM and UCODE G2iM+ memory sections Name Size Bank Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16 bit PC) (UCODE G2iM) EPC (excluding 16 bit CRC-16 and 16 bit PC) (UCODE G2iM+) 256 bit 128 bit up to 448 bit 01b G2iM Configuration Word (Config-Word) 16 bit 01b G2iM Memory Configuration Word (Mem-Config-Word) 16 bit 01b TID (including permalocked unique 48 bit serial number; 16bit unalterable XTID-header) 96 bit 10b User TID 112 bit 10b User memory (UCODE G2iM) User memory can be segmented and configured (UCODE G2iM+) 512 bit 320 bit up to 640 bit 11bSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 13 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.6.1 UCODE G2iM and UCODE G2iM+ overall memory map Table 8. UCODE G2iM and UCODE G2iM+ overall memory map Bank address Memory address Type Content Initial Remark Bank 00 00h to 1Fh reserved Kill Password all 00h unlocked memory 20h to 3Fh reserved Access Password all 00h unlocked memory Bank 01 EPC 00h to 0Fh EPC CRC-16: refer to Ref. 16 memory mapped calculated CRC 10h to 14h EPC backscatter length 00110b unlocked memory 15h EPC UMI 0b calculated according EPC 16h EPC reserved for future use 0b hardwired to 0 17h to 1Fh EPC numbering system indicator 00h unlocked memory 20h to 9Fh EPC EPC [1] unlocked memory Bank 01 Memory Config Word 1F0h to 1F3h EPC RFU 0000b hardwired to 0000b 1F4h to 1F7h EPC Number of EPC blocks 0h unlocked memory 1F8h to 1FBh EPC Number protected memory blocks 0h unlocked memory 1FCh to 1FFh EPC Number of private memory blocks 0h unlocked memory Bank 01 Config Word 200h EPC tamper alarm flag 0b[4] indicator bit 201h EPC external supply flag or input signal 0b[4] indicator bit 202h EPC RFU 0b[4] locked memory 203h EPC RFU 0b[4] locked memory 204h EPC invert digital output: 0b[4] temporary bit 205h EPC transparent mode on/off 0b[4] temporary bit 206h EPC transparent mode data/raw 0b[4] temporary bit 207h EPC conditional read range reduction 0b[4] unlocked memory 208h EPC conditional read range reduction open/short 0b[4] unlocked memory 209h EPC max. backscatter strength 1b[4] unlocked memory 20Ah EPC digital output 0b[4] unlocked memory 20Bh EPC read range reduction on/off 0b[4] unlocked memory 20Ch EPC read protect User Memory 0b[4] locked memory 20Dh EPC read protect EPC Bank 0b[4] unlocked memory 20Eh EPC read protect TID 0b[4] unlocked memory 20Fh EPC PSF alarm flag 0b[4] unlocked memorySL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 14 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ [1] UCODE G2iM: HEX E200 680A 0000 0000 0000 0000 (0000 0000) UCODE G2iM+: HEX E200 680B 0000 0000 0000 0000 (0000 0000) [2] Indicates the existence of a Configuration Word at the end of the EPC number [3] See Figure 5 [4] See also Table 13 for further details. Bank 10 TID 00h to 07h TID allocation class identifier 1110 0010b locked memory 08h to 13h TID tag mask designer identifier 0000 0000 0110b locked memory 14h TIG config word indicator 1b[2] locked memory 14h to 1Fh TID tag model number TMNR[3] locked memory 20h to 2Fh TID XTID Header 00h locked memory 30h to 5Fh TID serial number SNR locked memory 60h to CFh TID User TID memory all ’0’ unlocked memory Bank 11 USER 000h to 27Fh USER User Memory undefined unlocked memory Table 8. UCODE G2iM and UCODE G2iM+ overall memory map Bank address Memory address Type Content Initial Remarkxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.6 — 17 October 2014 201236 15 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.6.2 UCODE G2iM and UCODE G2iM+ TID memory details Table 9. G2iM TID description Model number Type First 32 bit of TID memory Class ID Mask designer ID Config Word indicator Sub version number Version (Silicon) number UCODE G2iM E200680A E2h 006h 1 0000b 0001010 UCODE G2iM+ E200680B E2h 006h 1 0000b 0001011 Fig 5. G2iM TID memory structure 001aan573 Class Identifier MS Byte MS Bit LS Bit TID Mask-Designer Identifier Model Number XTID Header Serial Number 7Bits 000 11 11 15 0 47 0 Addresses 00h 07h 13h 1Fh 5Fh Addresses 00h CFh 08h 14h 20h 2Fh 30h E2h (EAN.UCC) TID Example (UCODE G2iM) 006h (NXP) 80Ah (UCODE G2iM) 0000h Sub Version Number Version Number 000b 0001010b (UCODE G2iM) Bits 0 3 0 6 0 Addresses 14h 18h 19h 1Fh LS Byte User TID 112 0 60h CFhSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 16 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.7 Custom commands The UCODE G2iM and UCODE G2iM+ supports a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. The memory map stated in the previous section describes the Config-Word used to control the additional features located at address 200h as well as the Mem-Config-Word located at 1F0h of the EPC memory. For this reason the standard READ/WRITE commands of an UHF EPCglobal compliant reader can be used to select the flags, activate/deactivate features or define memory segments. The features can only be activated/deactivated (written) using standard EPC WRITE command as long the EPC is not locked. In case the EPC is locked either the bank needs to be unlocked to apply changes or the ChangeConfig custom command is used to change the settings. The UCODE G2iM products supports the complete UCODE G2iL command set for backward compatibility reasons. Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable selecting Config-Word enhanced transponders in mixed tag populations. 10.7.1 ChangeConfig Although UCODE G2iM is tailored for supply chain management, item level tagging and product authentication the UCODE G2iM+ version enables active interaction with products. Among the password protected features are the capability of download firmware to electronics, activate/deactivate electronics which can also be used as theft deterrence, a dedicated privacy mode by reducing the read range, integrated PSF (Product Status Flag) or Tag Tamper Alarm. In addition to the UCODE G2iL/G2iL+ the activation condition (open/short) for the Read Range Reduction can be defined by the user. The UCODE G2iM ChangeConfig custom command allows handling the special NXP Semiconductors features described in the following paragraph. Please also see the memory map in Section 10.6 “UCODE G2iM and UCODE G2iM+ memory” and “Section 10.7.2 “UCODE G2iM and UCODE G2iM+ special features control mechanism”. If the EPC memory is not write locked the standard EPC READ/WRITE command can be used to change the settings. UCODE G2iM and UCODE G2iM+ special features1 UCODE G2iM and UCODE G2iM+ common special features are: • Bank wise read protection (separate for EPC, TID and User Memory) EPC bank (except of configuration words), the serial number part of the TID as well as the User TID and the User Memory (open segment) can be read protected independently. When protected reading of the particular memory will return '0'. The flags of the Config-Word can be selected using the standard SELECT command. Only read protected parts will then participate an inventory round. 1. The features can only be manipulated (enabled/disabled) with unlocked EPC bank, otherwise the ChangeConfig command can be used.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 17 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ • Integrated PSF (Product Status Flag) The PSF is a general purpose flag that can be used as an EAS (Electronic Article Surveillance) flag, quality checked flag or similar. The UCODE G2iM offers two ways of detecting an activated PSF. In cases extremely fast detection is needed the EAS_Alarm command can be used. The UCODE G2iM will reply a 64 bit alarm code like described in section EAS_Alarm upon sending the command. As a second option the EPC SELECT command selecting the PSF flag of the Config-Word can be used. In the following inventory round only PSF enabled chips will reply their EPC number. • Backscatter strength reduction The UCODE G2iM features two levels of backscatter strengths. Per default maximum backscatter is enabled in order to enable maximum read rates. When clearing the flag the strength can be reduced if needed. UCODE G2iM+ specific special features are:1 • Real Read Range Reduction 4R (UCODE G2iM+ only) Some applications require the reduction of the read range to close proximity for privacy reasons. Setting the 4R flag will significantly reduce the chip sensitivity to +12 dBm. The +12 dBm have to be available at chip start up (slow increase of field strength is not applicable). For additional privacy, the read protection can be activated in the same configuration step. The related flag of the configuration word can be selected using the standard SELECT command so only chips with reduced read range will be part of an inventory. Remark: The attenuation will result in only a few centimeter of read range at 36 dBm EIRP! • Tag Tamper Alarm (UCODE G2iM+ only) The UCODE G2iM+ Tamper Alarm will flag the status of the VDD to OUT pad connection which can be designed as an predetermined breaking point (see Figure 6). The status of the pad connection (open/closed) can be read in the configuration register and/or selected using the EPC SELECT. This feature enables the design of a wireless RFID safety seal. When breaking the connection by peeling off the label or manipulating a lock an alarm can be triggered. Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal 001aan668 OUT VDD RFN RFPSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 18 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ • Conditional Real Read Range Reduction (UCODE G2iM+ only) In addition to the 4R and the Tag Tamper Alarm feature the UCODE G2iM+ offers a feature which combines both in one functionality. This feature allow the automatic activation of the 4R depending on the status of the VDD to OUT pad connection. To offer high flexibility for the applications the 4R activation can be done on short (bit 8 = ’1’) or open (bit 8 =’0’) of the VDD to OUT pad connection. For activation of this feature bit 7 and bit 11 of the Config-Word have to be set to ’1’. • Digital Switch (UCODE G2iM+ only) The UCODE G2iM+ OUT pin can be used as digital switch. The state of the output pad can be switched to VDD or GND depending on the Digital OUT bit of the Config-Word register. The state of the output is persistent in the memory even after KILL or switching off the supply. This feature will allow activating/deactivating externally connected peripherals or can be used as theft deterrence of electronics. The state of the OUT pin can also be changed temporary by toggling the 'Invert Digital Output' bit. • Data transfer Mode (UCODE G2iM+ only) In applications where not switching the output like described in "Digital Switch" but external device communication is needed the UCODE G2iM+ Data Transfer Mode can be used by setting the according bit of the Config-Word register. When activated the air interface communication will be directly transferred to the OUT pad of the chip. Two modes of data transfer are available and can be switched using the Transparent Mode DATA/RAW bit. The default Transparent Mode DATA will remove the Frame Sync of the communication and toggle the output with every raising edge in the RF field. This will allow implementing a Manchester type of data transmission. The Transparent Mode RAW will switch the demodulated air interface communication to the OUT pad. • External Supply Indicator - Digital Input (UCODE G2iM+ only) The VDD pad of the UCODE G2iM+ can be used as a digital input pin. The state of the pad is directly associated with the External Supply Indicator bit of the configuration register. A simple return signaling (chip to reader) can be implemented by polling this Configuration Word register flag. RF reset is necessary for proper polling. • External Supply Mode (G2iM+ only) The UCODE G2iM+ can be supplied externally by connecting 1.85 V (Iout = 0µA) supply. When externally supplied less energy from the RF field is needed to operate the chip. This will not just enable further improved sensitivity and read ranges (up to -27 dBm) but also enable a write range that is equal to the read range. The figure schematically shows the supply connected to the UCODE G2iM+. Remark: When permanently externally supplied there will not be a power-on-reset. This will result in the following limitations: • When externally supplied session flag S0 will keep it’s state during RF-OFF phase. • When externally supplied session flag S2, S3, SL will have infinite persistence time and will behave similar to S0. • Session flag S1 will behave regular like in pure passive operation.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 19 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ The bits to be toggled in the configuration register need to be set to '1'. E.g. sending 0000 0000 0001 0001 XOR RN16 will activate the 4R and PSF. Sending the very same command a second time will disable the features again. The reply of the ChangeConfig will return the current register setting. Fig 7. Schematic of external power supply Table 10. ChangeConfig custom command Command RFU Data RN CRC-16 No. of bits 16 8 16 16 16 Description 11100000 00000111 00000000 Toggle bits XOR RN 16 handle - Table 11. ChangeConfig custom command reply Header Status bits RN CRC-16 No. of bits 1 16 16 16 Description 0 Config-Word Handle - Table 12. ChangeConfig command-response table Starting state Condition Response Next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle Status word needs to change Backscatter unchanged Config-Word immediately open valid handle Status word does not need to change Backscatter Config-Word immediately open secured valid handle Status word needs to change Backscatter modified Config-Word, when done secured valid handle Status word does not need to change Backscatter Config-Word immediately secured killed all - killed 001aan669 OUT VDD Vsupply RFN RFPSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 20 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ The features can only be activated/deactivated using standard EPC WRITE if the EPC bank is unlocked. The permanent and temporary bits of the Configuration Word can be toggled without the need for an Access Password in case the Access Password is set to zero. In case the EPC bank is locked the lock needs to be removed before applying changes or the ChangeConfig command has to be used. 10.7.2 UCODE G2iM and UCODE G2iM+ special features control mechanism Special features of the UCODE G2iM are managed using a configuration word (Config-Word) located at address 200h in the EPC memory bank. The entire Config-Word is selectable (using the standard EPC SELECT command), as well as single bits, and can be read using standard EPC READ command and modified using the standard EPC WRITE or ChangeConfig custom command in case the EPC memory is locked for writing. ChangeConfig can be executed from the OPEN and SECURED state. The chip will take all “Toggle Bits” for ’0’ if the chip is in the OPEN state or the ACCESS password is zero; therefore it will not alter any status bits, but report the current status only. The command will be ignored with an invalid CRC-16 or an invalid handle. The chip will then remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A ChangeConfig command without frame-sync and proceeding Req_RN will be ignored. The command will also be ignored if any of the RFU bits are toggled. In order to change the configuration, to activate/deactivate a feature a ’1’ has to be written to the corresponding register flag to toggle the status. E.g. sending 0x0002 to the register will activate the read protection of the TID. Sending the same command a second time will again clear the read protection of the TID. Invalid toggling on indicator or RFU bits are ignored. Executing the command with zero as payload or in the OPEN state will return the current register settings. The chip will reply to a successful ChangeStatus with an extended preamble regardless of the TRext value of the Query command. After sending a ChangeConfig an interrogator shall transmit CW for less than TReply or 20ms, where TReply is the time between the interrogator's ChangeConfig command and the chip’s backscattered reply. An interrogator may observe three possible responses after sending a ChangeConfig, depending on the success or failure of the operation • ChangeConfig succeeded: The chip will backscatter the reply shown above comprising a header (a 0-bit), the current Config-Word setting, the handle, and a CRC-16 calculated over the 0-bit, the Config-Word and the handle. If the interrogator observes this reply within 20 ms then the ChangeConfig completed successfully. • The chip encounters an error: The chip will backscatter an error code during the CW period rather than the reply shown below (see EPCglobal Spec for error-code definitions and for the reply format). • ChangeConfig does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeConfig did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the chip is still in the interrogator's field, and may reissue the ChangeConfig command.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 21 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ The UCODE G2iM configuration word (Config-Word) is located at address 200h of the EPC memory and is structured as following: The configuration word contains three different type of bits: • Indicator bits cannot be changed by command: Tag Tamper Alarm Indicator External Supply Indicator (digital input) • Temporary bits are reset at power up: Invert Output Transparent Mode on/off Data Mode data/raw • Permanent bits: permanently stored bits in the memory Conditional Read Range Reduction on/off Conditional Read Range Reduction short/open Max. Backscatter Strength Digital Output Read Range Reduction Read Protect User Memory Read Protect EPC Read Protect TID PSF Alarm Table 13. Address 200h to 207h Indicator bits Temporary bits Permanent bits Tamper indicator External supply indicator RFU RFU Invert Output Transparent mode on/off Data mode data/raw Conditional Read Range Reduction on/off 0 1 2 34 5 6 7 Table 14. Address 208h to 20Fh Permanent bits Conditional Read Range Reduction open/short max. backscatter strength Digital output Read Range Reduction Protect UM Protect EPC Protect TID PSF Alarm bit 8 9 10 11 12 13 14 15SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 22 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.7.3 UCODE G2iM+ memory configuration control mechanism The segmented user memory available in the UCODE G2iM+ enables a flexible configuration of the device with respect to EPC size and access rights to the User Memory. The standard configuration offers 256 bit EPC memory and 512 bit open User Memory for UCODE G2iM and 128 bit EPC memory and 640 bit open User Memory for UCODE G2iM+. For applications where more EPC memory is required the UCODE G2iM+ offers the flexibility to extend the 128 bit EPC up to 448 bit (in steps of 64 bit) by reducing the User Memory size accordingly. See Table 15 and Table 17. Beside the possibility to extend the EPC memory the UCDOE G2iM+ offers the possibility to segment the User Memory in up to three areas with different access rights. • Open: no read/write protection • Protected: read/write protected by the Access Password • Private: read/write protected by the User Password (see Section 10.7.4) Table 15. EPC / User Memory Standard Configuration (UCODE G2iM) EPC Memory User Memory Open 256 bit 512 bit Table 16. EPC / User Memory Standard Configuration (UCODE G2iM+) EPC Memory User Memory Open 128 bit 640 bit Table 17. EPC / User Memory Max. EPC Configuration (UCODE G2iM+) EPC Memory User Memory Open 448 bit 320 bitSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 23 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ The memory configuration can be defined one time, by programming the memory configuration word, at the initialization of the UCODE G2iM+. The UCODE G2iM+ Memory Configuration Word (Mem-Config-Word) is located at address 1F0h of the EPC memory and is structured as following: • RFU-Bits: The four RFU bits are fixed to 0000b. These four bits are ignored for access commands (e.g. WRITE). • Number of EPC blocks: The 4 bit of this region specify the number of blocks (max. 5) which should be added on top of the standard EPC Memory of 128bit. • Number of Protected memory blocks: The 4 bit of this region specify the number of blocks which should be used for the Protected memory region. • Number of Private memory blocks: The 4 bit of this region specify the number of blocks which should be used for the Private memory region. The total amount of User Memory is defined by the number of blocks for EPC-, Open-, Protected- and Private- memory area. Based on the total User Memory size (640 bit) and the defined block size of 64 bit, the overall number of blocks results in ten blocks. As described in the examples (Table 19 to Table 21) below the blocks used for the EPC-, Open-, Protected- or Private segment can be exchanged according to the application requirements as long as the overall block number is below ten. The number of blocks allocated to the Open Memory Area are defined by the number of blocks specified in the Mem-Config-Word, therefore the size of the Open Memory area is derived by subtracting the number of defined blocks (Mem-Config-Word) from the total available number of blocks of the User Memory (10 blocks). Undefined blocks are always added to the Open Memory area. In case an invalid total amount of blocks (exceeds ten) is written to the Mem-Config-Word, the configuration fails and the error code (Locked Memory) will be returned. The entire Mem-Config-Word is selectable (using the standard EPC SELECT command), as well as single bits, and can be read using standard EPC READ command and modified using the standard EPC WRITE command. NOTE: THE MEM-CONFIG-WORD IS ONE TIME PROGRAMMABLE. Programming has be performed in the secured state. In case no programming of the memory configuration word is done at the initialization of the UCODE G2iM+ it will be automatically locked upon a lock of any part of the memory. The following tables will provide a few examples for different memory configurations. Table 18. Memory Configuration Word, Address 1F0h to 1FFh RFU Number of EPC blocks Number of Protected memory blocks Number of Private memory blocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 24 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ • Standard EPC size, 4 blocks Protected and 3 blocks Private memory which results in 3 blocks Open memory. (Mem-Config-Word value: 0043h) See Table 19 • Standard EPC size, 3 blocks Protected memory which results in 7 blocks Open memory. (Mem-Config-Word value: 0030h). See Table 20 • 192 bit EPC (1 block EPC added), 6 blocks Private memory which results in 4 blocks Open memory. (Mem-Config-Word value: 0106h) See Table 21 10.7.4 Private Memory Segment The Private memory is a part of the User Memory which can be accessed out of the secured state only. Private regions will appear as non existent to not authorized users. The address of the location of the User Password is not fixed and has therefore to be calculated based on the applied memory configuration. The 32 bit User Password is located at the end of the User Memory. Since the UCODE G2iM+ memory is configurable and can be segmented the address location of the User Password depends on the Memory configuration done at the initialization. User Password address calculation: HEX[(Total number of memory blocks - blocks appointed to EPC)*Blocksize)] Example: EPC length: 192 This means that 1 block from the User Memory is required (128 bit + 64 bit) HEX[(101)*64]=HEX[9*64]=HEX[384]=240h Therefore the User Password for this configuration is located at address 240h to 25Fh Table 19. User Memory Configuration with 3 segments EPC Memory User Memory Open Protected Private 128 bit 192 bit 256 bit 192 bit Table 20. User Memory Configuration with 2 segments (no Private segment) EPC Memory User Memory Open Protected 128 bit 448 bit 192 bit Table 21. User Memory Configuration with 2 areas (no Access password protected area) EPC Memory User Memory Open Private 192 bit 192 bit 384 bitSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 25 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.7.5 ReadProtect2 The UCODE G2iM ReadProtect custom command enables reliable read protection of the entire UCODE G2iM memory. Executing ReadProtect from the Secured state will set the ProtectEPC and ProtectTID bits of the Configuration Word to '1'. With the ReadProtect-Bit set the UCODE G2iM will continue to work unaffected but veil its protected content. The read protection can be removed by executing Reset ReadProtect. The ReadProtect-Bits will than be cleared. Devices whose access password is zero will ignore the command. A frame-sync must be pre-pended the command. After sending the ReadProtect command an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect command and the backscattered reply. An interrogator may observe three possible responses after sending a ReadProtect, depending on the success or failure of the operation: • ReadProtect succeeds: After completing the ReadProtect the UCODE G2iM shall backscatter the reply shown in Table 23 comprising a header (a 0-bit), the tag's handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this reply the UCODE G2iM will render itself to this ReadProtect mode. If the interrogator observes this reply within 20 ms then the ReadProtect completed successfully. • The UCODE G2iM encounters an error: The UCODE G2iM will backscatter an error code during the CW period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code definitions and for the reply format). • ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the UCODE G2iM is still in the interrogation zone, and may re-initiate the ReadProtect command. The UCODE G2iM reply to the ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. 2. Note: The ChangeConfig command can be used instead of “ReadProtect”, “ResetReadProtect”, “ChangeEAS”. Table 22. ReadProtect command Command RN CRC-16 # of bits 16 16 16 description 11100000 00000001 handle - Table 23. UCODE G2iM reply to a successful ReadProtect procedure Header RN CRC-16 # of bits 1 16 16 description 0 handle -SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 26 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.7.6 Reset ReadProtect2 Reset ReadProtect allows an interrogator to clear the ProtectEPC and ProtectTID bits of the Configuration Word. This will re-enable reading of the related UCODE G2iM memory content. For details on the command response please refer to Table 25 “Reset ReadProtect command”. After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect command and the UCODE G2iM backscattered reply. A Req_RN command prior to the Reset ReadProtect is necessary to successfully execute the command. A frame-sync must be pre-pended the command. An interrogator may observe three possible responses after sending a Reset ReadProtect, depending on the success or failure of the operation: • Reset ReadProtect succeeds: After completing the Reset ReadProtect a UCODE G2iM will backscatter the reply shown in Table 26 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the Reset ReadProtect completed successfully. • The UCODE G2iM encounters an error: The UCODE G2iM will backscatter an error code during the CW period rather than the reply shown in Table 26 (see EPCglobal Spec for error-code definitions and for the reply format). • Reset ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the Reset ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iM is still in the interrogation zone, and may reissue the Reset ReadProtect command. The UCODE G2iM reply to the Reset ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a UCODE G2iM will reply as if TRext=1 regardless of the TRext value in the Query that initiated the round. Table 24. ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all - open secured valid handle & invalid access password – arbitrate valid handle & valid non zero access password Backscatter handle, when done secured invalid handle – secured killed all – killedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 27 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ The Reset ReadProtect command is structured as following: • 16 bit command • Password: 32 bit Access-Password XOR with 2 times current RN16 Remark: To generate the 32 bit password the 16 bit RN16 is duplicated and used two times to generate the 32 bit (e.g. a RN16 of 1234 will result in 1234 1234). • 16 bit handle • CRC-16 calculate over the first command-code bit to the last handle bit Table 25. Reset ReadProtect command Command Password RN CRC-16 # of bits 16 32 16 16 description 11100000 00000010 (access password)  2*RN16 handle - Table 26. UCODE G2iM reply to a successful Reset ReadProtect command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 27. Reset ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open valid handle & valid access password Backscatter handle, when done open valid handle & invalid access password – arbitrate invalid handle – open secured valid handle & valid access password Backscatter handle, when done secured valid handle & invalid access password – arbitrate invalid handle – secured killed all – killedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 28 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.7.7 ChangeEAS2 UCODE G2iM equipped RFID tags will also feature a stand-alone operating EAS alarm mechanism for fast and offline electronic article surveillance. The PSF bit of the Config-Word directly relates to the EAS Alarm feature. With an PSF bit set to '1' the tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the need of a Select or Query. The EAS is a built-in solution so no connection to a backend database is required. In case the EAS_Alarm command is not implemented in the reader a standard EPC SELCET to the Config-Word and Query can be used. When using standard SELECT/QUERY the EPC will be returned during inventory. ChangeEAS can be executed from the Secured state only. The command will be ignored if the Access Password is zero, the command will also be ignored with an invalid CRC-16 or an invalid handle, the UCODE G2iM will than remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A frame-sync must be pre-pended the command. The UCODE G2iM reply to a successful ChangeEAS will use the extended preamble, as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeEAS command and the UCODE G2iM backscattered reply. An interrogator may observe three possible responses after sending a ChangeEAS, depending on the success or failure of the operation • ChangeEAS succeeds: After completing the ChangeEAS a UCODE G2iM will backscatter the reply shown in Table 29 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the ChangeEAS completed successfully. • The UCODE G2iM encounters an error: The UCODE G2iM will backscatter an error code during the CW period rather than the reply shown in Table 29 (see EPCglobal Spec for error-code definitions and for the reply format). • ChangeEAS does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeEAS did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iM is still in the interrogator's field, and may reissue the ChangeEAS command. Upon receiving a valid ChangeEAS command a G2iM will perform the commanded set/reset operation of the PSF bit of the Configuration Word. If PSF bit is set, the EAS_Alarm command will be available after the next power up and reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be ignored. Table 28. ChangeEAS command Command ChangeEas RN CRC-16 # of bits 16 1 16 16 description 11100000 00000011 1 ... set PSF bit 0 ... reset PSF bit handleSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 29 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 10.7.8 EAS_Alarm Upon receiving an EAS_Alarm custom command the UCODE G2iM will immediately backscatter an EAS-Alarmcode in case the PSF bit of the Config-Word is set. The alarm code is returned without any delay caused by Select, Query and without the need for a backend database. The EAS feature of the UCODE G2iM is available after enabling it by sending a ChangeEAS command described in Section 10.7.7 “ChangeEAS2” or after setting the PSF bit of the Config-Word to ’1’. With the EAS-Alarm enabled the UCODE G2iM will reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A UCODE G2iM will reply to an EAS_Alarm command from the ready state only. As an alternative to the fast EAS_Alarm command a standard SELECT (upon the Config-Word) and QUERY can be used. If the PSF bit is reset to '0' by sending a ChangeEAS command in the password protected Secure state or clearing the PSF bit the UCODE G2iM will not reply to an EAS_Alarm command. The EAS_Alarm command is structured as following: • 16 bit command • 16 bit inverted command • DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec. 6.3.1.2.8 and Table 6.9. • M (cycles per symbol) sets the T=>R data rate and modulation format as shown in EPCglobal Spec. Table 6.10. • TRext chooses whether the T=>R preamble is pre-pended with a pilot tone as described in EPCglobal Spec. 6.3.1.3. A preamble must be pre-pended the EAS_Alarm command according EPCglobal Spec, 6.3.1.2.8. Table 29. UCODE G2iM reply to a successful ChangeEAS command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 30. ChangeEAS command-response table Starting State Condition Response Next state ready all – ready arbitrate, reply, acknowledged all – arbitrate open all – open secured valid handle backscatter handle, when done secured invalid handle – secured killed all – killedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 30 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate the CRC5 over the backscattered 64 bits received to verify the received code. Table 31. EAS_Alarm command Command Inv_Command DR M TRext CRC-16 # of bits 16 16 1 2 1 16 description 11100000 00000100 00011111 11111011 0: DR=8 1: DR=64/3 00: M=1 01: M=2 10: M=4 11: M=8 0: no pilot tone 1: use pilot tone - Table 32. UCODE G2iM reply to a successful EAS_Alarm command Header EAS Code # of bits 1 64 description 0 CRC5 (MSB) Table 33. EAS_Alarm command-response table Starting State Condition Response Next state ready PSF bit is set PSF bit is cleard backscatter alarm code -- ready arbitrate, reply, acknowledged all – arbitrate open all – open secured all – secured killed all – killedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 31 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 11. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP20 package. Table 34. Limiting values[1][2] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to RFN Symbol Parameter Conditions Min Max Unit Bare die limitations Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage Human body model [3] - ±2 kV Pad limitations Vi input voltage absolute limits, VDD-OUT pad 0.5 +2.5 V Io output current absolute limits input/output current, VDD-OUT pad 0.5 +0.5 mA Pi input power maximum power dissipation, RFP pad - 100 mWSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 32 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 12. Characteristics 12.1 UCODE G2iM and UCODE G2iM+ bare die characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. [4] It has to be assured the reader (system) is capable of providing enough field strength to give +10 dBm at the chip otherwise communication with the chip will not be possible. [5] Enables tag designs to be within ETSI limits for return link data rates of e.g. 320 kHz/M4. [6] Will result in up to 10 dB higher tag backscatter power at high field strength. [7] Results in approx. 18 dBm tag sensitivity on a 2 dBi gain antenna. Table 35. UCODE G2iM and UCODE G2iM+ RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit fi input frequency 840 - 960 MHz Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2][7] - 17.5 - dBm Pi(min) minimum input power WRITE, BLOCKWRITE sensitivity, (write range/read range - ratio) - - 30 20 - % Ci input capacitance parallel [3] - 0.77 - pF Q quality factor 915 MHz [3] - 9.2 - - Z impedance 866 MHz [3] - 27 j234 -  915 MHz [3] - 24 j222 -  953MHz [3] - 23 j213 -  External supply mode - VDD pad supplied, read range reduction OFF Pi(min) minimum input power Ext. supplied READ [1][2] - 27 - dBm Ext. supplied WRITE [2] - 27 - dBm Z impedance externally supplied, 915 MHz [3] - 8 -j228 -  Read range reduction ON - no external supply Pi(min) minimum input power 4R on READ [1][2][4] - +10 - dBm 4R on WRITE [2][4] - +10 - dBm Z impedance 4R on, 915 MHz [3] - 16 j1 -  Modulation resistance R resistance modulation resistance, max. backscatter = off [5] - 170 -  modulation resistance, max. backscatter = on [6] - 55 - SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 33 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ [1] Activates Digital Output (OUT pin), increases read range (external supplied). [2] Activates Digital Output (OUT pin), increases read and write range (external supplied). [3] Operating the chip outside the specified voltage range may lead to undefined behaviour.1925. [4] Either the voltage or the current needs to be above given values to guarantee specified functionality. [5] No proper operation is guaranteed if both, voltage and current, limits are exceeded. [1] Is the sum of the allowed capacitance of the VDD and OUT pin referenced to RFN. [2] Is the maximum allowed RF input voltage coupling to the VDD/OUT pin to guarantee undisturbed chip functionality. [3] Resistance between VDD and OUT pin in checked during power up only. [4] Resistance range to achieve tamper alarm flag = 1. [5] Resistance range to achieve tamper alarm flag = 0: Table 36. VDD pin characteristics Symbol Parameter Conditions Min Typ Max Unit Minimum supply voltage/current - without assisted EEPROM WRITE [1][3][4] VDD supply voltage minimum voltage - - 1.8 V IDD supply current minimum current, Iout = 0 mA - - 14 mA Iout = 100 mA - - 120 mA Minimum supply voltage/current - assisted EEPROM READ and WRITE [2][3][4] VDD supply voltage minimum voltage, Iout = 0 mA - 1.8 1.85 V Iout = 100 mA - - 1.95 V IDD supply current minimum current, Iout = 0 mA - - 135 mA Iout = 100 mA - - 265 mA Maximum supply voltage/current [3][5] VDD supply voltage absolute maximum voltage 2.2 - - V Ii(max) maximum input current absolute maximum current 280 - - mA Table 37. G2iM, G2iM+ VDD and OUT pin characteristics Symbol Parameter Conditions Min Typ Max Unit OUT pin characteristics VOL Low-level output voltage Isink = 1mA - - 100 mV VOH HIGH-level output voltage VDD = 1.8 V; Isource = 100µA 1.5 - - V VDD/OUT pin characteristics CL load capacitance VDD - OUT pin max. [1] - - 5 pF Vo output voltage maximum RF peak voltage on VDD-OUT pins [2] - - 500 mV VDD/OUT pin tamper alarm characteristics [3] RL(max) maximum load resistance resistance range high [4] - - <2 M RL(min) minimum load resistance resistance range low [5] >20 - - MSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 34 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ [1] Tamb 25 C 12.2 UCODE G2iM+ SOT886 characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. Remark: For DC and memory characteristics refer to Table 36, Table 37 and Table 38. Table 38. UCODE G2iM and UCODE G2iM+ memory characteristics Symbol Parameter Conditions Min Typ Max Unit EEPROM characteristics tret retention time Tamb 55 C 20 - - year Nendu(W) write endurance 1000 10000[1] - cycle Table 39. G2iM+ RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 17.6 - dBm Z impedance 915 MHz [3] - 21.2 -j199.7 -  Normal mode - externally supply VDD = 1.8V, read range reduction OFF Z impedance 915 MHz [3] - 6.9 -j205.5 - SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 35 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 13. Package outline Fig 8. Package outline SOT886 terminal 1 index area OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT886 MO-252 SOT886 04-07-15 04-07-22 DIMENSIONS (mm are the original dimensions) XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm D E e1 e A1 b L L 1 e1 0 1 2 mm scale Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. UNIT mm 0.25 0.17 1.5 1.4 0.35 0.27 A1 max b E 1.05 0.95 D e e1 L 0.40 0.32 L1 0.50.6 A(1) max 0.5 0.04 1 6 2 5 3 4 6× (2) 4× (2) ASL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 36 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 14. Handling information 14.1 Assembly conditions 14.1.1 General assembly recommendations While pads OUT and VDD are not used for UCODE G2iM (SL3S1003), they are still electrically active and therefore must not be connected to the antenna and the RFN and RFP pads. In case of any doubts, the customer is constrained to contact NXP Semiconductors for further clarification. 14.1.2 Label converting Generally, an optimization of the entire lamination process by label manufacturer is recommended in order to minimize the stress onto the module and guarantee high assembly yield. Roller diameter must not be smaller than 45 mm. 15. Packing information 15.1 Wafer See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**”SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 37 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 16. Abbreviations Table 40. Abbreviations Acronym Description CRC Cyclic Redundancy Check CW Continuous Wave DC Direct Current EAS Electronic Article Surveillance EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) ESD ElectroStatic Discharge FCS Flip Chip Strap FM0 Bi phase space modulation G2 Generation 2 HBM Human Body Model IC Integrated Circuit PSF Product Status Flag PCB Printed Circuit Board RF Radio Frequency UHF Ultra High Frequency TID Tag IDentifier SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 38 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 17. References [1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0 (December 17, 2005) [2] EPCglobal: EPC Tag Data Standards [3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft) [4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference (draft) [5] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 1 – Technical characteristics and test methods [6] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive [7] [CEPT1]: CEPT REC 70-03 Annex 1 [8] [ETSI1]: ETSI EN 330 220-1, 2 [9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1: Technical characteristics and test methods. [10] [FCC1]: FCC 47 Part 15 Section 247 [11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International Standards [12] ISO/IEC 3309: Information technology – Telecommunications and information exchange between systems – High-level data link control (HDLC) procedures – Frame structure [13] ISO/IEC 15961: Information technology, Automatic identification and data capture – Radio frequency identification (RFID) for item management – Data protocol: application interface [14] ISO/IEC 15962: Information technology, Automatic identification and data capture techniques – Radio frequency identification (RFID) for item management – Data protocol: data encoding rules and logical memory functions [15] ISO/IEC 15963: Information technology — Radio frequency identification for item management — Unique identification for RF tags [16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item management — Part 1: Reference architecture and definition of parameters to be standardized [17] ISO/IEC 18000-6: Information technology automatic identification and data capture techniques — Radio frequency identification for item management air interface — Part 6: Parameters for air interface communications at 860–960 MHz [18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary – Part 3: radio-frequency identification (RFID) SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 39 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ [19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15: Radio-frequency devices, U.S. Federal Communications Commission. [20] Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**3 3. ** ... document version numberSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 40 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 18. Revision history Table 41. Revision history Document ID Release date Data sheet status Change notice Supersedes SL2S1003_1013 v. 3.6 20141017 Product data sheet - SL2S1003_1013 v. 3.5 Modifications: • Table 21 “User Memory Configuration with 2 areas (no Access password protected area)”: corrected • Table 39 “G2iM+ RF interface characteristics (RFN, RFP)”: corrected SL2S1003_1013 v. 3.5 20131107 Product data sheet - SL2S1003_1013 v. 3.4 Modifications: • Table 1 “Ordering information”: updated • Table 2 “Marking codes”: updated • Section 2.2 “Key benefits”: title updated • Table 39 “G2iM+ RF interface characteristics (RFN, RFP)”: title updated SL2S1003_1013 v. 3.4 20120227 Product data sheet - SL2S1003_1013 v. 3.3 Modifications: • Figure 4 “SL3S10x3 wafer layout”: Figure notes (1) and (2) updated SL2S1003_1013 v. 3.3 20120130 Product data sheet SL2S1003_1013 v. 3.2 Modifications: • Section 14 “Handling information”: added SL2S1003_1013 v. 3.2 20120111 Product data sheet - SL2S1003_1013 v. 3.1 Modifications: • Section 8.1 “Wafer layout”: figure notes (1), (2), (8) and (9) updated SL2S1003_1013 v. 3.1 20111117 Product data sheet - SL2S1003_1013 v. 3.0 Modifications: • Security status changed into COMPANY PUBLIC • Package delivery form SOT886 added • Section 5 “Marking”, Section 13 “Package outline”: added SL2S1003_1013 v. 3.0 20110503 Product data sheet - SL2S1003_1013 v. 2.0 Modifications: • Specification status changed into product • Some EPC bit values changed • Table 16 added SL2S1003_1013 v. 2.0 20110415 Preliminary data sheet - -SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 41 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ 19. Legal information 19.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.6 — 17 October 2014 201236 42 of 43 NXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP Semiconductors N.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors SL3S1003_1013 UCODE G2iM and G2iM+ © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 October 2014 201236 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1.1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.1 End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.2 Antenna design benefits . . . . . . . . . . . . . . . . . . 2 2.2.3 Label manufacturer benefit. . . . . . . . . . . . . . . . 2 2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 Mechanical specification . . . . . . . . . . . . . . . . . 8 9.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 8 9.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9.1.2 Fail die identification . . . . . . . . . . . . . . . . . . . . 9 9.1.3 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 9 10 Functional description . . . . . . . . . . . . . . . . . . 10 10.1 Air interface standards . . . . . . . . . . . . . . . . . . 10 10.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . 10 10.3 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 10 10.3.1 Reader to tag Link . . . . . . . . . . . . . . . . . . . . . 10 10.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . 10 10.4 UCODE G2iM and UCODE G2iM+ differences 11 10.5 Supported commands . . . . . . . . . . . . . . . . . . 11 10.6 UCODE G2iM and UCODE G2iM+ memory . 12 10.6.1 UCODE G2iM and UCODE G2iM+ overall memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13 10.6.2 UCODE G2iM and UCODE G2iM+ TID memory details . . . . . . . . . . . . . . . . . . . . . . . . 15 10.7 Custom commands. . . . . . . . . . . . . . . . . . . . . 16 10.7.1 ChangeConfig. . . . . . . . . . . . . . . . . . . . . . . . . 16 UCODE G2iM and UCODE G2iM+ special features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 10.7.2 UCODE G2iM and UCODE G2iM+ special features control mechanism . . . . . . . . . . . . . . 20 10.7.3 UCODE G2iM+ memory configuration control mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.7.4 Private Memory Segment . . . . . . . . . . . . . . . . 24 10.7.5 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.7.6 Reset ReadProtect2 . . . . . . . . . . . . . . . . . . . . 26 10.7.7 ChangeEAS2 . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.7.8 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 12.1 UCODE G2iM and UCODE G2iM+ bare die characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 12.2 UCODE G2iM+ SOT886 characteristics . . . . 34 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35 14 Handling information . . . . . . . . . . . . . . . . . . . 36 14.1 Assembly conditions . . . . . . . . . . . . . . . . . . . 36 14.1.1 General assembly recommendations . . . . . . 36 14.1.2 Label converting. . . . . . . . . . . . . . . . . . . . . . . 36 15 Packing information . . . . . . . . . . . . . . . . . . . . 36 15.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37 17 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40 19 Legal information . . . . . . . . . . . . . . . . . . . . . . 41 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20 Contact information . . . . . . . . . . . . . . . . . . . . 42 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1. General description NXP’s UCODE G2iL series transponder ICs offer leading-edge read range and support industry-first features such as a Tag Tamper Alarm, Data Transfer, Digital Switch, and advanced privacy-protection modes. Very high chip sensitivity (18 dBm) enables longer read ranges with simple, single-port antenna designs. When connected to a power supply, the READ as well as the WRITE range can be boosted to a sensitivity of 27 dBm. In fashion and retail the UCODE G2iL series improve read rates and provide for theft deterrence. For consumer electronics the UCODE G2iL series is suited for device configuration, activation, production control, and PCB tagging. In authentication applications the transponders can be used to protect brands and guard against counterfeiting. They can also be used to tag containers, electronic vehicles, airline baggage, and more. In addition to the EPC specifications the G2iL offers an integrated Product Status Flag (PSF) feature and read protection of the memory content. On top of the G2iL features the G2iL+ offers an integrated tag tamper alarm, RF field detection, digital switch, external supply mode, read range reduction and data transfer mode. 2. Features and benefits 2.1 Key features  UHF RFID Gen2 tag chip according EPCglobal v1.2.0 with 128 bit EPC memory  Memory read protection  Integrated Product Status Flag (PSF)  Tag tamper alarm  RF field detection  Digital switch  Data transfer mode  Real Read Range Reduction (Privacy Mode)  External supply mode where both the READ & WRITE range are boosted to -27dBm 2.1.1 Memory  128-bit of EPC memory  64-bit Tag IDentifier (TID) including 32-bit factory locked unique serial number  32-bit kill password to permanently disable the tag  32-bit access password to allow a transition into the secured state SL3S1203_1213 UCODE G2iL and G2iL+ Rev. 4.4 — 17 March 2014 178844 Product data sheet COMPANY PUBLICSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 2 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+  Data retention: 20 years  Broad international operating frequency: from 840 MHz to 960 MHz  Long read/write ranges due to extremely low power design  Reliable operation of multiple tags due to advanced anti-collision  READ protection  WRITE Lock  Wide specified temperature range: 40 C up to +85 C 2.2 Key benefits 2.2.1 End user benefit  Prevention of unauthorized memory access through read protection  Indication of tag tampering attempt by use of the tag tamper alarm feature  Electronic device configuration and / or activation by the use of the digital switch / data transfer mode  Theft deterrence supported by the PSF feature (PSF alarm or EPC code)  Small label sizes, long read ranges due to high chip sensitivity  Product identification through unalterable extended TID range, including a 32-bit serial number  Reliable operation in dense reader and noisy environments through high interference suppression 2.2.2 Antenna design benefits  High sensitivity enables small and cost efficient antenna designs  Low Q-Value eases broad band antenna design for global usage 2.2.3 Label manufacturer benefit  Consistent performance on different materials due to low Q-factor  Ease of assembly and high assembly yields through large chip input capacitance  Fast first WRITE of the EPC memory for fast label initialization 2.3 Custom commands  PSF Alarm Built-in PSF (Product Status Flag), enables the UHF RFID tag to be used as EAS tag (Electronic Article Surveillance) tag without the need for a back-end data base.  Read Protect Protects all memory content including CRC16 from unauthorized reading.  ChangeConfig Configures the additional features of the chip like external supply mode, tamper alarm, digital switch, read range reduction or data transfer. The UCODE G2iL is equipped with a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. No custom commands are needed to take advantage of all the features in case of unlocked EPC memory.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 3 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 3. Applications 3.1 Markets  Fashion (Apparel and footwear)  Retail  Electronics  Fast Moving Consumer Goods  Asset management  Electronic Vehicle Identification 3.2 Applications  Supply chain management  Item level tagging  Pallet and case tracking  Container identification  Product authentication  PCB tagging  Cost efficient, low level seals  Wireless firmware download  Wireless product activation Outside above mentioned applications, please contact NXP Semiconductors for support. 4. Ordering information 5. Marking Table 1. Ordering information Type number Package Name IC type Description Version SL3S1203FUF Wafer G2iL bumped die on sawn 8” 75 m wafer not applicable SL3S1213FUF Wafer G2iL+ bumped die on sawn 8” 75 m wafer not applicable SL3S1203FUD/BG Wafer G2iL bumped die on sawn 8” 120 m wafer, 7 m Polyimide spacer not applicable SL3S1213FUD/BG Wafer G2iL+ bumped die on sawn 8” 120 m wafer, 7 m Polyimide spacer not applicable SL3S1203FTB0 XSON6 G2iL plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886F1 Table 2. Marking codes Type number Marking code Comment Version SL3S1203FTB0 UN UCODE G2iL SOT886SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 4 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 6. Block diagram The SL3S12x3 IC consists of three major blocks: - Analog Interface - Digital Control - EEPROM The analog part provides stable supply voltage and demodulates data received from the reader for being processed by the digital part. Further, the modulation transistor of the analog part transmits data back to the reader. The digital section includes the state machines, processes the protocol and handles communication with the EEPROM, which contains the EPC and the user data. Fig 1. Block diagram of G2iL IC 001aam226 MOD DEMOD VREG VDD VDD data in data out R/W ANALOG RF INTERFACE PAD PAD RECT DIGITAL CONTROL ANTENNA ANTICOLLISION READ/WRITE CONTROL ACCESS CONTROL EEPROM INTERFACE CONTROL RF INTERFACE CONTROL I/O CONTROL I/O CONTROL EEPROM MEMORY SEQUENCER CHARGE PUMP PAD OUT PADSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 5 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 7. Pinning information 7.1 Pin description Fig 2. Pinning bare die Fig 3. Pin configuration for SOT886 001aam529 VDD OUT RFN NXP trademark RFP SL3S12x3FTB0 n.c. 001aan103 RFP RFN n.c. VDD OUT Transparent top view 2 3 1 5 4 6 Table 3. Pin description bare die Symbol Description OUT output pin RFN grounded antenna connector VDD external supply RFP ungrounded antenna connector Table 4. Pin description SOT886 Pin Symbol Description 1 RFP ungrounded antenna connector 2 n.c. not connected 3 RFN grounded antenna connector 4 OUT output pin 5 n.c. not connected 6 VDD external supplySL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 6 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 8. Wafer layout 8.1 Wafer layout (1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m) (2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m) (3) Chip step, x-length: 485 m (4) Chip step, y-length: 435 m (5) Bump to bump distance X (OUT - RFN): 383 m (6) Bump to bump distance Y (RFN - RFP): 333 m (7) Distance bump to metal sealring X: 40,3 m (outer edge - top metal) (8) Distance bump to metal sealring Y: 40,3 m Bump size X x Y: 60 m x 60 m Remark: OUT and VDD are used with G2iL+ only Fig 4. G2iL wafer layout not to scale! 001aak871 (1) (7) (2) (8) (5) (6) (4) (3) Y X VDD OUT RFN RFPSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 7 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 9. Mechanical specification The UCODE G2iL/G2iL+ wafers are available in 75 m and 120 m thickness. The 75m thick wafer allows ultra thin label design but require a proper tuning of the glue dispenser during production. Because of the more robust structure of the 120m wafer, the wafer is ideal for harsh applications. The 120 m thick wafer is also enhanced with 7m Polyimide spacer allowing additional protection of the active circuit. 9.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**”. 9.1.1 Wafer Table 5. Specifications Wafer Designation each wafer is scribed with batch number and wafer number Diameter 200 mm (8”) Thickness SL3S12x3FUF 75 m  15 m SL3S12x3FUD 120 m  15 m Number of pads 4 Pad location non diagonal/ placed in chip corners Distance pad to pad RFN-RFP 333.0 m Distance pad to pad OUT-RFN 383.0 m Process CMOS 0.14 m Batch size 25 wafers Potential good dies per wafer 139.351 Wafer backside Material Si Treatment ground and stress release Roughness Ra max. 0.5 m, Rt max. 5 m Chip dimensions Die size including scribe 0.485 mm  0.435 mm = 0.211 mm2 Scribe line width: x-dimension = 15 m y-dimension = 15 m Passivation on front Type Sandwich structure Material PE-Nitride (on top) Thickness 1.75 m total thickness of passivation Polyimide spacer 7 m  1 m (SL3S12x3FUD only) Au bump Bump material > 99.9 % pure AuSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 8 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer. 9.1.2 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 9.1.3 Map file distribution See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 10. Functional description 10.1 Air interface standards The UCODE G2iL fully supports all parts of the "Specification for RFID Air Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 10.2 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE G2iL. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the G2iL on the tag. The G2iL+ can also be supplied externally. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. Bump hardness 35 – 80 HV 0.005 Bump shear strength > 70 MPa Bump height SL3S12x3FUF 18 m SL3S12x3FUD 25 m[1] Bump height uniformity within a die  2 m – within a wafer  3 m – wafer to wafer  4 m Bump flatness  1.5 m Bump size – RFP, RFN 60  60 m – OUT, VDD 60  60 m Bump size variation  5 m Table 5. SpecificationsSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 9 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The antenna that is attached to the chip may use a DC connection between the two antenna pads. Therefore the G2iL also enables loop antenna design. Possible examples of supported antenna structures can be found in the reference antenna design guide. 10.3 Data transfer 10.3.1 Reader to tag Link An interrogator transmits information to the UCODE G2iL by modulating an UHF RF signal. The G2iL receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. In order to further improve the read range the UCODE G2iL+ can be externally supplied as well so the energy to operate the chip does not need to be transmitted by the reader. An interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. It communicates to the G2iL by modulating an RF carrier using DSB-ASK with PIE encoding. For further details refer to Section 16, Ref. 1. Interrogator-to-tag (R=>T) communications. 10.3.2 Tag to reader Link An interrogator receives information from a G2iL by transmitting an unmodulated RF carrier and listening for a backscattered reply. The G2iL backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. For further details refer to Section 16, Ref. 1, chapter 6.3.1.3. The UCODE G2iL communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subcarrier. 10.4 G2iL and G2iL+ differences The UCODE G2iL is tailored for application where mainly EPC or TID number space is needed. The G2iL+ in addition provides functionality such as tag tamper alarm, external supply operation to further boost read/write range (external supply mode), a Privacy mode reducing the read range or I/O functionality (data transfer to externally connected devices) required. The following table provides an overview of G2iL, G2iL+ special features. Table 6. Overview of G2iL and G2iL+ features Features G2iL G2iL+ Read protection (bankwise) yes yes PSF (Built-in Product Status Flag) yes yes Backscatter strength reduction yes yes Real read range reduction yes yes Digital switch / Digital input - yes External supply mode - yesSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 10 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.5 Supported commands The G2iL supports all mandatory EPCglobal V1.2.0 commands. In addition the G2iL supports the following optional commands: • ACCESS • Block Write (32 bit) The G2iL features the following custom commands described more in detail later: • ResetReadProtect (backward compatible to G2X) • ReadProtect (backward compatible to G2X) • ChangeEAS (backward compatible to G2X) • EAS_Alarm (backward compatible to G2X) • ChangeConfig (new with G2iL) 10.6 G2iL, G2iL+ memory The G2iL, G2iL+ memory is implemented according EPCglobal Class1Gen2 and organized in three sections: The logical address of all memory banks begin at zero (00h). In addition to the three memory banks one configuration word to handle the G2iL specific features is available at EPC bank 01 address 200h. The configuration word is described in detail in Section 10.7.1 “ChangeConfig”. Memory pages (16 bit words) pre-programmed to zero will not execute an erase cycle before writing data to it. This approach accelerates initialization of the chip and enables faster programming of the memory. RF field detection - yes Data transfer - yes Tag tamper alarm - yes Table 6. Overview of G2iL and G2iL+ features …continued Features G2iL G2iL+ Table 7. G2iL memory sections Name Size Bank Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16 bit PC) 128 bit 01b G2iL Configuration Word 16 bit 01b TID (including permalocked unique 32 bit serial number) 64 bit 10bSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 11 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.6.1 G2iL, G2iL+ overall memory map [1] See Figure 5 [2] Indicates the existence of a Configuration Word at the end of the EPC number [3] See also Table 12 for further details. Table 8. G2iL, G2iL+ overall memory map Bank address Memory address Type Content Initial Remark Bank 00 00h to 1Fh reserved kill password all 00h unlocked memory 20h to 3Fh reserved access password all 00h unlocked memory Bank 01 EPC 00h to 0Fh EPC CRC-16: refer to Ref. 16 memory mapped calculated CRC 10h to 14h EPC backscatter length 00110b unlocked memory 15h EPC UMI 0b unlocked memory 16h EPC XPC indicator 0b hardwired to 0 17h to 1Fh EPC numbering system indicator 00h unlocked memory 20h to 9Fh EPC EPC [1] unlocked memory Bank 01 Config Word 200h EPC tamper alarm flag 0b[3] indicator bit 201h EPC external supply flag or input signal 0b[3] indicator bit 202h EPC RFU 0b[3] locked memory 203h EPC RFU 0b[3] locked memory 204h EPC invert digital output: 0b[3] temporary bit 205h EPC transparent mode on/off 0b[3] temporary bit 206h EPC transparent mode data/raw 0b[3] temporary bit 207h EPC RFU 0b[3] locked memory 208h EPC RFU 0b[3] locked memory 209h EPC max. backscatter strength 1b[3] unlocked memory 20Ah EPC digital output 0b[3] unlocked memory 20Bh EPC read range reduction on/off 0b[3] unlocked memory 20Ch EPC RFU 0b[3] locked memory 20Dh EPC read protect EPC Bank 0b[3] unlocked memory 20Eh EPC read protect TID 0b[3] unlocked memory 20Fh EPC PSF alarm flag 0b[3] unlocked memory Bank 10 TID 00h to 07h TID allocation class identifier 1110 0010b locked memory 08h to 13h TID tag mask designer identifier 0000 0000 0110b locked memory 14h TID config word indicator 1b[2] locked memory 14h to 1Fh TID tag model number TMNR[1] locked memory 20h to 3Fh TID serial number SNR locked memoryxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 4.4 — 17 March 2014 178844 12 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.6.2 G2iL TID memory details Fig 5. G2iL TID memory structure aaa-010217 E2006906 E2h 006h 1 0010b 0000110b Ucode G2iL+ E2006807 E2h 006h 1 0000b 0000111b E2006907 E2h 006h 1 0010b 0000111b Ucode G2iL E2006806 E2h 006h 1 0000b 0000110b First 32 bit of TID memory Class ID Mask Designer ID Config Word Indicator Sub Version Nr. Model Number Version (Silicon) Nr. Class Identifier MS Byte MS Bit LS Bit LS Byte TID MS Bit LS Bit Mask-Designer Identifier Model Number Serial Number Bits 7 0 00 11 11 31 0 Addresses 00h 07h 13h 1Fh 3Fh Addresses 00h 3Fh 08h 14h 20h E2h (EAN.UCC) 006h (NXP) 806h or 906h or B06h (UCODE G2iL) 00000001h to FFFFFFFFh Sub Version Number Version Number 000b or 001b or 0110b 0000110b (UCODE G2iL) Bits 0 3 0 6 0 Addresses 14h 18h 19h 1Fh E2006B06 E2h 006h 1 0110b 0000110b E2006B07 E2h 006h 1 0110b 0000111bSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 13 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.7 Custom commands The UCODE G2iL, G2iL+ is equipped with a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. The memory map stated in the previous section describes the Configuration Word used to control the additional features located at address 200h of the EPC memory. For this reason the standard READ/WRITE commands of an UHF EPCglobal compliant reader can be used to select the flags or activate/deactivate features. The features can only be activated/deactivated (written) using standard EPC WRITE command as long the EPC is not locked. In case the EPC is locked either the bank needs to be unlocked to apply changes or the ChangeConfig custom command is used to change the settings. The UCODE G2iL is also equipped with the complete UCODE G2X command set for backward compatibility reasons. Nevertheless, the one ChangeConfig command of the G2iL can be used instead of the entire G2X command set. Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable selecting Config-Word enhanced transponders in mixed tag populations. 10.7.1 ChangeConfig Although G2iL is tailored for supply chain management, item level tagging and product authentication the G2iL+ version enables active interaction with products. Among the password protected features are the capability of download firmware to electronics, activate/deactivate electronics which can also be used as theft deterrence, a dedicated privacy mode by reducing the read range, integrated PSF (Product Status Flag) or Tag Tamper Alarm. The G2iL ChangeConfig custom command allows handling the special NXP Semiconductors features described in the following paragraph. Please also see the memory map in Section 10.6 “G2iL, G2iL+ memory” and “Section 10.7.2 “G2iL, G2iL+ special features control mechanism”. If the EPC memory is not write locked the standard EPC READ/WRITE command can be used to change the settings. G2iL, G2iL+ special features1 UCODE G2iL and G2iL+ common special features are: • Bank wise read protection (separate for EPC and TID) EPC bank and the serial number part of the TID can be read protected independently. When protected reading of the particular memory will return '0'. The flags of the configuration word can be selected using the standard SELECT2 command. Only read protected parts will then participate an inventory round. The G2X ReadProtect command will set both EPC and TID read protect flags. 1. The features can only be manipulated (enabled/disabled) with unlocked EPC bank, otherwise the ChangeConfig command can be used. 2. SELECT has to be applied onto the Configuration Word with pointer address 200h. Selecting bits within the Configuration Word using a pointer address not equal to 200h is not possible.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 14 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • Integrated PSF (Product Status Flag) The PSF is a general purpose flag that can be used as an EAS (Electronic Article Surveillance) flag, quality checked flag or similar. The G2iL offers two ways of detecting an activated PSF. In cases extremely fast detection is needed the EAS_Alarm command can be used. The UCODE G2iL will reply a 64-bit alarm code like described in section EAS_Alarm upon sending the command. As a second option the EPC SELECT2 command selecting the PSF flag of the configuration word can be used. In the following inventory round only PSF enabled chips will reply their EPC number. • Backscatter strength reduction The UCODE G2iL features two levels of backscatter strengths. Per default maximum backscatter is enabled in order to enable maximum read rates. When clearing the flag the strength can be reduced if needed. • Real Read Range Reduction 4R Some applications require the reduction of the read range to close proximity for privacy reasons. Setting the 4R flag will significantly reduce the chip sensitivity to +12 dBm. The +12 dBm have to be available at chip start up (slow increase of field strength is not applicable). For additional privacy, the read protection can be activated in the same configuration step. The related flag of the configuration word can be selected using the standard SELECT2 command so only chips with reduced read range will be part of an inventory. Remark: The attenuation will result in only a few centimeter of read range at 36 dBm EIRP! UCODE G2iL+ specific special features are:1 • Tag Tamper Alarm (G2iL+ only) The UCODE G2iL+ Tamper Alarm will flag the status of the VDD to OUT pad connection which can be designed as an predetermined breaking point (see Figure 6). The status of the pad connection (open/closed) can be read in the configuration register and/or selected using the EPC SELECT2. This feature will enable designing a wireless RFID safety seal. When breaking the connection by peeling off the label or manipulating a lock an alarm can be triggered. Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal 001aam228 OUT VDD GND RFPSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 15 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • RF field detection (G2iL+ only) The UCODE G2iL+ VDD pin can be also used as a RF field detector. Upon bringing the tag within an RF field, a pulse signal will be immediately sent from the VDD test pad. (for details see Ref. 21). • Digital Switch (G2iL+ only) The UCODE G2iL+ OUT pin can be used as digital switch. The state of the output pad can be switched to VDD or GND depending on the Digital OUT bit of the Configuration Word register. The state of the output is persistent in the memory even after KILL or switching off the supply. This feature will allow activating/deactivating externally connected peripherals or can be used as theft deterrence of electronics. The state of the OUT pin can also be changed temporary by toggling the 'Invert Digital Output' bit. • Data transfer Mode (G2iL+ only) In applications where not switching the output like described in "Digital Switch" but external device communication is needed the G2iL+ Data Transfer Mode can be used by setting the according bit of the Configuration Word register. When activated the air interface communication will be directly transferred to the OUT pad of the chip. Two modes of data transfer are available and can be switched using the Transparent Mode DATA/RAW bit. The default Transparent Mode DATA will remove the Frame Sync of the communication and toggle the output with every raising edge in the RF field. This will allow implementing a Manchester type of data transmission. The Transparent Mode RAW will switch the demodulated air interface communication to the OUT pad. • External Supply Indicator - Digital Input (G2iL+ only) The VDD pad of the UCODE G2iL+ can be used as a single bit digital input pin. The state of the pad is directly associated with the External Supply Indicator bit of the configuration register. Simple one bit return signaling (chip to reader) can be implemented by polling this Configuration Word register flag. RF reset is necessary for proper polling. • External Supply Mode (G2iL+ only) The UCODE G2iL+ can be supplied externally by connecting 1.85 V (Iout = 0µA) supply. When externally supplied less energy from the RF field is needed to operate the chip. This will not just enable further improved sensitivity and read ranges (up to 27 dBm) but also enable a write range that is equal to the read range. The figure schematically shows the supply connected to the UCODE G2iL+. Remark: When permanently externally supplied there will not be a power-on-reset. This will result in the following limitations: • When externally supplied session flag S0 will keep it’s state during RF-OFF phase. • When externally supplied session flag S2, S3, SL will have infinite persistence time and will behave similar to S0. • Session flag S1 will behave regular like in pure passive operation.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 16 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The bits to be toggled in the configuration register need to be set to '1'. E.g. sending 0000 0000 0001 0001 XOR RN16 will activate the 4R and PSF. Sending the very same command a second time will disable the features again. The reply of the ChangeConfig will return the current register setting. Fig 7. Schematic of external power supply Table 9. ChangeConfig custom command Command RFU Data RN CRC-16 No. of bits 16 8 16 16 16 Description 11100000 00000111 00000000 Toggle bits XOR RN 16 handle - Table 10. ChangeConfig custom command reply Header Status bits RN CRC-16 No. of bits 1 16 16 16 Description 0 Config-Word Handle - Table 11. ChangeConfig command-response table Starting state Condition Response Next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle Status word needs to change Backscatter unchanged Config-WordConfig-Word immediately open valid handle Status word does not need to change Backscatter Config-Word immediately open secured valid handle Status word needs to change Backscatter modified Config-Word, when done secured valid handle Status word does not need to change Backscatter Config-Word immediately secured killed all - killed 001aam229 OUT VDD Vsupply GND RFPSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 17 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The features can only be activated/deactivated using standard EPC WRITE if the EPC bank is unlocked. The permanent and temporary bits of the Configuration Word can be toggled without the need for an ACCESS password in case the ACCESS password is set to zero. In case the EPC bank is locked the lock needs to be removed before applying changes or the ChangeConfig command has to be used. 10.7.2 G2iL, G2iL+ special features control mechanism Special features of the G2iL are managed using a configuration word (Config-Word) located at address 200h in the EPC memory bank. The entire Config-Word is selectable (using the standard EPC SELECT2 command) and can be read using standard EPC READ command and modified using the standard EPC WRITE or ChangeConfig custom command in case the EPC memory is locked for writing. ChangeConfig can be executed from the OPEN and SECURED state. The chip will take all “Toggle Bits” for ’0’ if the chip is in the OPEN state or the ACCESS password is zero; therefore it will not alter any status bits, but report the current status only. The command will be ignored with an invalid CRC-16 or an invalid handle. The chip will then remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A ChangeConfig command without frame-sync and proceeding Req_RN will be ignored. The command will also be ignored if any of the RFU bits are toggled. In order to change the configuration, to activate/deactivate a feature a ’1’ has to be written to the corresponding register flag to toggle the status. E.g. sending 0x0002 to the register will activate the read protection of the TID. Sending the same command a second time will again clear the read protection of the TID. Invalid toggling on indicator or RFU bits are ignored. Executing the command with zero as payload or in the OPEN state will return the current register settings. The chip will reply to a successful ChangeConfig with an extended preamble regardless of the TRext value of the Query command. After sending a ChangeConfig an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeConfig command and the chip’s backscattered reply. An interrogator may observe three possible responses after sending a ChangeConfig, depending on the success or failure of the operation • ChangeConfigChangeConfig succeeded: The chip will backscatter the reply shown above comprising a header (a 0-bit), the current Status Word setting, the handle, and a CRC-16 calculated over the 0-bit, the status word and the handle. If the interrogator observes this reply within 20 ms then the ChangeConfig completed successfully. • The chip encounters an error: The chip will backscatter an error code during the CW period rather than the reply shown below (see EPCglobal Spec for error-code definitions and for the reply format). • ChangeConfig does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeStatus did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the chip is still in the interrogator's field, and may reissue the ChangeConfig command. The G2iL configuration word is located at address 200h of the EPC memory and is structured as following:SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 18 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The configuration word contains three different type of bits: • Indicator bits cannot be changed by command: Tag Tamper Alarm Indicator External Supply Indicator (digital input) • Temporary bits are reset at power up: Invert Output Transparent Mode on/off Data Mode data/raw • Permanent bits: permanently stored bits in the memory Max. Backscatter Strength Digital Output Read Range Reduction Read Protect EPC Read Protect TID PSF Alarm 10.7.3 ReadProtect3 The G2iL ReadProtect custom command enables reliable read protection of the entire G2iL memory. Executing ReadProtect from the Secured state will set the ProtectEPC and ProtectTID bits of the Configuration Word to '1'. With the ReadProtect-Bit set the G2iL will continue to work unaffected but veil its protected content. The read protection can be removed by executing Reset ReadProtect. The ReadProtect-Bits will than be cleared. Devices whose access password is zero will ignore the command. A frame-sync must be pre-pended the command. After sending the ReadProtect command an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect command and the backscattered reply. An interrogator may observe three possible responses after sending a ReadProtect, depending on the success or failure of the operation: Table 12. Address 200h to 207h Indicator bits Temporary bits Tamper indicator External supply indicator RFU RFU Invert Output Transparent mode on/off Data mode data/raw RFU 0 1 2 34 5 6 7 Table 13. Address 208h to 20Fh Permanent bits RFU max. backscatter strength Digital output Privacy mode RFU Protect EPC Protect TID PSF Alarm bit 8 9 10 11 12 13 14 15 3. Note: The ChangeConfig command can be used instead of “ReadProtect”, “ResetReadProtect”, “ChangeEAS”.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 19 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • ReadProtect succeeds: After completing the ReadProtect the G2iL shall backscatter the reply shown in Table 15 comprising a header (a 0-bit), the tag's handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this reply the G2iL will render itself to this ReadProtect mode. If the interrogator observes this reply within 20 ms then the ReadProtect completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code definitions and for the reply format). • ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogation zone, and may re-initiate the ReadProtect command. The G2iL reply to the ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. 10.7.4 Reset ReadProtect3 Reset ReadProtect allows an interrogator to clear the ProtectEPC and ProtectTID bits of the Configuration Word. This will re-enable reading of the related G2iL memory content. For details on the command response please refer to Table 17 “Reset ReadProtect command”. Table 14. ReadProtect command Command RN CRC-16 # of bits 16 16 16 description 11100000 00000001 handle - Table 15. G2iL reply to a successful ReadProtect procedure Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 16. ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all - open secured valid handle & invalid access password – arbitrate valid handle & valid non zero access password Backscatter handle, when done secured invalid handle – secured killed all – killedSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 20 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect command and the G2iL backscattered reply. A Req_RN command prior to the Reset ReadProtect is necessary to successfully execute the command. A frame-sync must be pre-pended the command. An interrogator may observe three possible responses after sending a Reset ReadProtect, depending on the success or failure of the operation: • Reset ReadProtect succeeds: After completing the Reset ReadProtect a G2iL will backscatter the reply shown in Table 18 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the Reset ReadProtect completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in Table 18 (see EPCglobal Spec for error-code definitions and for the reply format). • Reset ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the Reset ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogation zone, and may reissue the Reset ReadProtect command. The G2iL reply to the Reset ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a G2iL will reply as if TRext=1 regardless of the TRext value in the Query that initiated the round. The Reset ReadProtect command is structured as following: • 16 bit command • Password: 32 bit Access-Password XOR with 2 times current RN16 Remark: To generate the 32 bit password the 16 bit RN16 is duplicated and used two times to generate the 32 bit (e.g. a RN16 of 1234 will result in 1234 1234). • 16 bit handle • CRC-16 calculate over the first command-code bit to the last handle bit Table 17. Reset ReadProtect command Command Password RN CRC-16 # of bits 16 32 16 16 description 11100000 00000010 (access password)  2*RN16 handle - Table 18. G2iL reply to a successful Reset ReadProtect command Header RN CRC-16 # of bits 1 16 16 description 0 handle -SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 21 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.7.5 ChangeEAS3 UCODE G2iL equipped RFID tags will also feature a stand-alone operating EAS alarm mechanism for fast and offline electronic article surveillance. The PSF bit of the Configuration Word directly relates to the EAS Alarm feature. With an PSF bit set to '1' the tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the need of a Select or Query. The EAS is a built-in solution so no connection to a backend database is required. In case the EAS_Alarm command is not implemented in the reader a standard EPC SELCET to the Configuration Word and Query can be used. When using standard SELECT/QUERY the EPC will be returned during inventory. ChangeEAS can be executed from the Secured state only. The command will be ignored if the Access Password is zero, the command will also be ignored with an invalid CRC-16 or an invalid handle, the G2iL will than remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A frame-sync must be pre-pended the command. The G2iL reply to a successful ChangeEAS will use the extended preamble, as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeEAS command and the G2iL backscattered reply. An interrogator may observe three possible responses after sending a ChangeEAS, depending on the success or failure of the operation • ChangeEAS succeeds: After completing the ChangeEAS a G2iL will backscatter the reply shown in Table 21 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the ChangeEAS completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in Table 21 (see EPCglobal Spec for error-code definitions and for the reply format). Table 19. Reset ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open valid handle & valid access password Backscatter handle, when done open valid handle & invalid access password – arbitrate invalid handle – open secured valid handle & valid access password Backscatter handle, when done secured valid handle & invalid access password – arbitrate invalid handle – secured killed all – killedSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 22 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • ChangeEAS does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeEAS did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogator's field, and may reissue the ChangeEAS command. Upon receiving a valid ChangeEAS command a G2iL will perform the commanded set/reset operation of the PSF bit of the Configuration Word. If PSF bit is set, the EAS_Alarm command will be available after the next power up and reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be ignored. 10.7.6 EAS_Alarm Upon receiving an EAS_Alarm custom command the UCODE G2iL will immediately backscatter an EAS-Alarmcode in case the PSF bit of the Configuration Word is set. The alarm code is returned without any delay caused by Select, Query and without the need for a backend database. The EAS feature of the G2iL is available after enabling it by sending a ChangeEAS command described in Section 10.7.5 “ChangeEAS3” or after setting the PSF bit of the Configuration Word to ’1’. With the EAS-Alarm enabled the G2iL will reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A G2iL will reply to an EAS_Alarm command from the ready state only. As an alternative to the fast EAS_Alarm command a standard SELECT2 (upon the Configuration Word) and QUERY can be used. If the PSF bit is reset to '0' by sending a ChangeEAS command in the password protected Secure state or clearing the PSF bit the G2iL will not reply to an EAS_Alarm command. Table 20. ChangeEAS command Command ChangeEAS RN CRC-16 # of bits 16 1 16 16 description 11100000 00000011 1 ... set PSF bit 0 ... reset PSF bit handle Table 21. G2iL reply to a successful ChangeEAS command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 22. ChangeEAS command-response table Starting State Condition Response Next state ready all – ready arbitrate, reply, acknowledged all – arbitrate open all – open secured valid handle backscatter handle, when done secured invalid handle – secured killed all – killedSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 23 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The EAS_Alarm command is structured as following: • 16 bit command • 16 bit inverted command • DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec. 6.3.1.2.8 and Table 6.9. • M (cycles per symbol) sets the T=>R data rate and modulation format as shown in EPCglobal Spec. Table 6.10. • TRext chooses whether the T=>R preamble is pre-pended with a pilot tone as described in EPCglobal Spec. 6.3.1.3. A preamble must be pre-pended the EAS_Alarm command according EPCglobal Spec, 6.3.1.2.8. Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate the CRC5 over the backscattered 64 bits received to verify the received code. Table 23. EAS_Alarm command Command Inv_Command DR M TRext CRC-16 # of bits 16 16 1 2 1 16 description 11100000 00000100 00011111 11111011 0: DR = 8 1: DR = 64/3 00: M = 1 01: M = 2 10: M = 4 11: M = 8 0: no pilot tone 1: use pilot tone - Table 24. G2iL reply to a successful EAS_Alarm command Header EAS Code # of bits 1 64 description 0 CRC5 (MSB) Table 25. EAS_Alarm command-response table Starting State Condition Response Next state ready PSF bit is set PSF bit is cleard backscatter alarm code -- ready arbitrate, reply, acknowledged all – arbitrate open all – open secured all – secured killed all – killedSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 24 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 11. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP20 package. Table 26. Limiting values[1][2] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to RFN Symbol Parameter Conditions Min Max Unit Bare die and SOT886 limitations Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage Human body model [3] - 2 kV Pad limitations Vi input voltage absolute limits, VDD-OUT pad 0.5 +2.5 V Io output current absolute limits input/output current, VDD-OUT pad 0.5 +0.5 mA Pi input power maximum power dissipation, RFP pad - 100 mWSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 25 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 12. Characteristics 12.1 UCODE G2iL, G2iL+ bare die characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. [4] It has to be assured the reader (system) is capable of providing enough field strength to give +12 dBm at the chip otherwise communication with the chip will not be possible. [5] Enables tag designs to be within ETSI limits for return link data rates of e.g. 320 kHz/M4. [6] Will result in up to 10 dB higher tag backscatter power at high field strength. [7] Results in approx. 18.5 dBm tag sensitivity on a 2 dBi gain antenna. Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit fi input frequency 840 - 960 MHz Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2][7] - 18 - dBm Pi(min) minimum input power WRITE sensitivity, (write range/read range - ratio) - 30 - % Ci input capacitance parallel [3] - 0.77 - pF Q quality factor 915 MHz [3] - 9.7 - - Z impedance 866 MHz [3] - 25 -j237 -  915 MHz [3] - 23 -j224 -  953 MHz [3] - 21 -j216 -  External supply mode - VDD pad supplied, read range reduction OFF Pi(min) minimum input power Ext. supplied READ [1][2] - 27 - dBm Ext. supplied WRITE [2] - 27 - dBm Z impedance externally supplied, 915 MHz [3] - 7 -j230 -  Read range reduction ON - no external supply Pi(min) minimum input power 4R on READ [1][2][4] - +12 - dBm 4R on WRITE [2][4] - +12 - dBm Z impedance 4R on, 915 MHz [3] - 18 -j2 -  Modulation resistance R resistance modulation resistance, max. backscatter = off [5] - 170 -  modulation resistance, max. backscatter = on [6] - 55 - SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 26 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [1] Activates Digital Output (OUT pin), increases read range (external supplied). [2] Activates Digital Output (OUT pin), increases read and write range (external supplied). [3] Operating the chip outside the specified voltage range may lead to undefined behaviour. [4] Either the voltage or the current needs to be above given values to guarantee specified functionality. [5] No proper operation is guaranteed if both, voltage and current, limits are exceeded. [1] Is the sum of the allowed capacitance of the VDD and OUT pin referenced to RFN. [2] Is the maximum allowed RF input voltage coupling to the VDD/OUT pin to guarantee undisturbed chip functionality. [3] Resistance between VDD and OUT pin in checked during power up only. [4] Resistance range to achieve tamper alarm flag = 1. [5] Resistance range to achieve tamper alarm flag = 0: Table 28. VDD pin characteristics Symbol Parameter Conditions Min Typ Max Unit Minimum supply voltage/current - without assisted EEPROM WRITE [1][3][4] VDD supply voltage minimum voltage - - 1.8 V IDD supply current minimum current, Iout-^- = 0 A -- 7 A Iout = 100 A -- 110 A Minimum supply voltage/current - assisted EEPROM READ and WRITE [2][3][4] VDD supply voltage minimum voltage, Iout = 0 A - 1.8 1.85 V Iout = 100 A -- 1.95 V IDD supply current minimum current, Iout = 0 A - - 125 A Iout = 100 A -- 265 A Maximum supply voltage/current [3][5] VDD supply voltage absolute maximum voltage 2.2 - - V Ii(max) maximum input current absolute maximum current 280 - - A Table 29. G2iL, G2iL+ VDD and OUT pin characteristics Symbol Parameter Conditions Min Typ Max Unit OUT pin characteristics VOL Low-level output voltage Isink = 1 mA - - 100 mV VOH HIGH-level output voltage VDD = 1.8 V; Isource = 100 µA 1.5 - - V VDD/OUT pin characteristics CL load capacitance VDD - OUT pin max. [1] - - 5 pF Vo output voltage maximum RF peak voltage on VDD-OUT pins [2] - - 500 mV VDD/OUT pin tamper alarm characteristics [3] RL(max) maximum load resistance resistance range high [4] - - <2 M RL(min) minimum load resistance resistance range low [5] >20 - - MSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 27 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ For further reading we recommend application note “FAQ UCODE G2iL+“ (Ref. 21) describing the output characteristics more in detail. An example schematic is available in application note “UCODE G2iL+ Demo board Manual“ (Ref. 22). The documents are available at NXP Document Control or at the website www.nxp.com. [1] Tamb 25 C 12.2 UCODE G2iL SOT886 characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. Remark: For DC and memory characteristics refer to Table 28, Table 29 and Table 30. Table 30. G2iL, G2iL+ memory characteristics Symbol Parameter Conditions Min Typ Max Unit EEPROM characteristics tret retention time Tamb 55 C 20 - - year Nendu(W) write endurance 1000 10000[1] - cycle Table 31. G2iL RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 17.6 - dB m Z impedance 915 MHz [3] - 21 j199 -  Normal mode - externally supplied, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 27 - dB m Z impedance 915 MHz [3] - 5.6 j204 - SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 28 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 13. Package outline Fig 8. Package outline SOT886 Outline References version European projection Issue date IEC JEDEC JEITA SOT886 MO-252 sot886_po 04-07-22 12-01-05 Unit mm max nom min 0.5 0.04 1.50 1.45 1.40 1.05 1.00 0.95 0.35 0.30 0.27 0.40 0.35 0.32 0.6 A(1) Dimensions (mm are the original dimensions) Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 A1 b 0.25 0.20 0.17 D E ee1 0.5 L L1 terminal 1 index area D E e1 e A1 b L L 1 e1 0 1 2 mm scale 1 6 2 5 3 4 6x (2) 4x (2) ASL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 29 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 14. Packing information 14.1 Wafer See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 14.2 SOT886 Part orientation T1. For details please refer to http://www.standardics.nxp.com/packaging/packing/pdf/sot886.t1.t4.pdf 15. Abbreviations Table 32. Abbreviations Acronym Description CRC Cyclic Redundancy Check CW Continuous Wave DSB-ASK Double Side Band-Amplitude Shift Keying DC Direct Current EAS Electronic Article Surveillance EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bi phase space modulation G2 Generation 2 IC Integrated Circuit PIE Pulse Interval Encoding RRRR Real Read Range Reduction PSF Product Status Flag RF Radio Frequency UHF Ultra High Frequency SECS Semi Equipment Communication Standard TID Tag IDentifier SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 30 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 16. References [1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0 (December 17, 2005) [2] EPCglobal: EPC Tag Data Standards [3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft) [4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference (draft) [5] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 1 – Technical characteristics and test methods [6] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive [7] [CEPT1]: CEPT REC 70-03 Annex 1 [8] [ETSI1]: ETSI EN 330 220-1, 2 [9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1: Technical characteristics and test methods. [10] [FCC1]: FCC 47 Part 15 Section 247 [11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International Standards [12] ISO/IEC 3309: Information technology – Telecommunications and information exchange between systems – High-level data link control (HDLC) procedures – Frame structure [13] ISO/IEC 15961: Information technology, Automatic identification and data capture – Radio frequency identification (RFID) for item management – Data protocol: application interface [14] ISO/IEC 15962: Information technology, Automatic identification and data capture techniques – Radio frequency identification (RFID) for item management – Data protocol: data encoding rules and logical memory functions [15] ISO/IEC 15963: Information technology — Radio frequency identification for item management — Unique identification for RF tags [16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item management — Part 1: Reference architecture and definition of parameters to be standardized [17] ISO/IEC 18000-6: Information technology automatic identification and data capture techniques — Radio frequency identification for item management air interface — Part 6: Parameters for air interface communications at 860–960 MHz [18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary – Part 3: radio-frequency identification (RFID) SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 31 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15: Radio-frequency devices, U.S. Federal Communications Commission. [20] Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**4 [21] Application note - FAQ UCODE G2i, BU-ID document number: AN10940 [22] Application note - UCODE G2iM+ demo board documentation, BU-ID document number: AN11237 4. ** ... document version numberSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 32 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 17. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3S1203_1213 v.4.4 20140317 Product data sheet - SL3S1203_1213 v.4.3 Modifications: • Table 8 “G2iL, G2iL+ overall memory map”: Table notes updated • Figure 5 “G2iL TID memory structure”: TIDs updated SL3S1203_1213 v.4.3 20131127 Product data sheet - SL3S1203_1213 v.4.2 Modifications: • Figure 5 “G2iL TID memory structure”: updated SL3S1203_1213 v.4.2 20130701 Product data sheet - SL3S1203_1213 v.4.1 Modifications: • Update of delivery form • Update RF field detection SL3S1203_1213 v.4.1 20120917 Product data sheet - SL3S1203_1213 v.4.0 Modifications: • Update of delivery form SL3S1203_1213 v.4.0 20120227 Product data sheet - SL3S1203_1213 v.3.9 Modifications: • Figure 4 “G2iL wafer layout”: Figure notes (1) and (2) updated SL3S1203_1213 v.3.9 20120130 Product data sheet - SL3S1203_1213 v.3.8 Modifications: • Table 6 “Specifications”: “Passivation on front” updated • Section 15.2.1 “General assembly recommendations”: updated SL3S1203_1213 v.3.8 20120111 Product data sheet - SL3S1203_1213 v.3.7 Modifications: • Section 8.1 “Wafer layout”: Figure notes (1) and (2) updated SL3S1203_1213 v.3.7 20111124 Product data sheet - SL3S1203_1213 v.3.6 Modifications: • Table 11 “G2iL, G2iL+ overall memory map”: updated • Table 34 “G2iL, G2iL+ RF interface characteristics (RFN, RFP)”: updated SL3S1203_1213 v.3.6 20110803 Product data sheet - SL3S1203_1213 v.3.5 Modifications: • Real Read Range Reduction feature added to G2iL SL3S1203_1213 v.3.5 20110531 Product data sheet - SL3S1203_1213 v.3.4 Modifications: • Superfluous text removed from Table 6 SL3S1203_1213 v.3.4 20110511 Product data sheet - SL3S1203_1213 v.3.3 Modifications: • Security status changed into COMPANY PUBLIC • Delivery form of FCS2 strap added • Section 13 “Package information”, Section 15 “Handling information” and Section 16 “Packing information” added SL3S1203_1213 v.3.3 20110131 Product data sheet - SL3S1203_1213 v.3.2 Modifications: • Section 4 “Ordering information”: new types SL3S1203FUD and SL3S1213FUD added • Section 9 “Mechanical specification”: updated according to the new types • Replaced wording of “ChangeStatus” with “ChangeConfig” SL3S1203_1213 v.3.2 20101109 Product data sheet - SL3S1203_1213 v.3.1 Modifications: • Version SOT886F1 added • Section 5 “Marking”, Section 13 “Package outline” and Section 14 “Packing information” added SL3S1203_1213 v.3.1 20100922 Product data sheet - SL3S1203_1213 v.3.0 Modifications: • General Modifications SL3S1203_1213 v.3.0 20100621 Product data sheet - 178810SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 33 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ Modifications: • General update 178810 20100304 Objective data sheet - - Table 33. Revision history …continued Document ID Release date Data sheet status Change notice SupersedesSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 34 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 35 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 36 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 20. Tables Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description bare die . . . . . . . . . . . . . . . . . . .5 Table 4. Pin description SOT886 . . . . . . . . . . . . . . . . . . .5 Table 5. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 6. Overview of G2iL and G2iL+ features . . . . . . . .9 Table 7. G2iL memory sections . . . . . . . . . . . . . . . . . . .10 Table 8. G2iL, G2iL+ overall memory map. . . . . . . . . . . 11 Table 9. ChangeConfig custom command . . . . . . . . . . .16 Table 10. ChangeConfig custom command reply. . . . . . .16 Table 11. ChangeConfig command-response table . . . . .16 Table 12. Address 200h to 207h . . . . . . . . . . . . . . . . . . .18 Table 13. Address 208h to 20Fh . . . . . . . . . . . . . . . . . . .18 Table 14. ReadProtect command. . . . . . . . . . . . . . . . . . .19 Table 15. G2iL reply to a successful ReadProtect procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 16. ReadProtect command-response table . . . . . .19 Table 17. Reset ReadProtect command . . . . . . . . . . . . .20 Table 18. G2iL reply to a successful Reset ReadProtect command. . . . . . . . . . . . . . . . . . .20 Table 19. Reset ReadProtect command-response table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 20. ChangeEAS command . . . . . . . . . . . . . . . . . . 22 Table 21. G2iL reply to a successful ChangeEAS command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 22. ChangeEAS command-response table . . . . . . 22 Table 23. EAS_Alarm command . . . . . . . . . . . . . . . . . . . 23 Table 24. G2iL reply to a successful EAS_Alarm c ommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 25. EAS_Alarm command-response table . . . . . . 23 Table 26. Limiting values[1][2] . . . . . . . . . . . . . . . . . . . . . . 24 Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 28. VDD pin characteristics . . . . . . . . . . . . . . . . . . 26 Table 29. G2iL, G2iL+ VDD and OUT pin characteristics . . . . . . . . . . . . . . . . . . . . . . 26 Table 30. G2iL, G2iL+ memory characteristics . . . . . . . . 27 Table 31. G2iL RF interface characteristics (RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 33. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32 21. Figures Fig 1. Block diagram of G2iL IC . . . . . . . . . . . . . . . . . . .4 Fig 2. Pinning bare die. . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. Pin configuration for SOT886 . . . . . . . . . . . . . . . .5 Fig 4. G2iL wafer layout. . . . . . . . . . . . . . . . . . . . . . . . . .6 Fig 5. G2iL TID memory structure . . . . . . . . . . . . . . . . .12 Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal. .14 Fig 7. Schematic of external power supply . . . . . . . . . .16 Fig 8. Package outline SOT886. . . . . . . . . . . . . . . . . . .28NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 March 2014 178844 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1.1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.1 End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.2 Antenna design benefits . . . . . . . . . . . . . . . . . . 2 2.2.3 Label manufacturer benefit. . . . . . . . . . . . . . . . 2 2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Mechanical specification . . . . . . . . . . . . . . . . . 7 9.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 Fail die identification . . . . . . . . . . . . . . . . . . . . 8 9.1.3 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 8 10 Functional description . . . . . . . . . . . . . . . . . . . 8 10.1 Air interface standards . . . . . . . . . . . . . . . . . . . 8 10.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 8 10.3 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.3.1 Reader to tag Link . . . . . . . . . . . . . . . . . . . . . . 9 10.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . . 9 10.4 G2iL and G2iL+ differences . . . . . . . . . . . . . . . 9 10.5 Supported commands . . . . . . . . . . . . . . . . . . 10 10.6 G2iL, G2iL+ memory . . . . . . . . . . . . . . . . . . . 10 10.6.1 G2iL, G2iL+ overall memory map. . . . . . . . . . 11 10.6.2 G2iL TID memory details . . . . . . . . . . . . . . . . 12 10.7 Custom commands. . . . . . . . . . . . . . . . . . . . . 13 10.7.1 ChangeConfig. . . . . . . . . . . . . . . . . . . . . . . . . 13 G2iL, G2iL+ special features . . . . . . . . . . . . . .13 10.7.2 G2iL, G2iL+ special features control mechanism . . . . . . . . . . . . . . . . . . . . . 17 10.7.3 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.7.4 Reset ReadProtect3 . . . . . . . . . . . . . . . . . . . . 19 10.7.5 ChangeEAS3 . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.7.6 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1 UCODE G2iL, G2iL+ bare die characteristics 25 12.2 UCODE G2iL SOT886 characteristics . . . . . . 27 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 28 14 Packing information . . . . . . . . . . . . . . . . . . . . 29 14.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.2 SOT886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 34 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19 Contact information . . . . . . . . . . . . . . . . . . . . 35 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1. Introduction This document describes the functionality and electrical specifications of the transceiver IC PN512. The PN512 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. 1.1 Different available versions The PN512 is available in three versions: • PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2 (TFBGA64), hereafter named as version 2.0 • PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In), hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs). • PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named as version 1.0 The data sheet describes the functionality for the industrial version and version 2.0. The differences of the version 1.0 to the version 2.0 are summarized in Section 21. The industrial version has only differences within the outlined characteristics and limitations. 2. General description The PN512 transceiver ICs support 4 different operating modes • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Reader/Writer mode supporting ISO/IEC 14443B • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and PN512 Full NFC Forum compliant solution Rev. 4.5 — 17 December 2013 111345 Product data sheet COMPANY PUBLICPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 2 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC). The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both directions. Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented. In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card functionality is only possible in combination with a secure IC using the S2C interface. Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection. Various host controller interfaces are implemented: • 8-bit parallel interface1 • SPI interface • serial UART (similar to RS232 with voltage levels according pad voltage supply) • I 2C interface. A purchaser of this NXP IC has to take care for appropriate third party patent licenses. 1. 8-bit parallel Interface only available in HVQFN40 package.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 3 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 3. Features and benefits  Highly integrated analog circuitry to demodulate and decode responses  Buffered output drivers for connecting an antenna with the minimum number of external components  Integrated RF Level detector  Integrated data mode detector  Supports ISO/IEC 14443 A/MIFARE  Supports ISO/IEC 14443 B Read/Write modes  Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning  Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna size and tuning and power supply  Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation mode of about 100 mm depending on the antenna size and tuning and the external field strength  Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode  ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s  Contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s  Integrated RF interface for NFCIP-1 up to 424 kbit/s  S2C interface  Additional power supply to directly supply the smart card IC connected via S2C  Supported host interfaces  SPI up to 10 Mbit/s  I 2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode  RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply  8-bit parallel interface with and without Address Latch Enable  FIFO buffer handles 64 byte send and receive  Flexible interrupt modes  Hard reset with low power function  Power-down mode per software  Programmable timer  Internal oscillator for connection to 27.12 MHz quartz crystal  2.5 V to 3.6 V power supply  CRC coprocessor  Programmable I/O pins  Internal self-testPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 4 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 4. Quick reference data [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. [4] Ipd is the total current for all supplies. [5] IDD(PVDD) depends on the overall load at the digital pins. [6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz. Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V [1][2] 2.5 - 3.6 V VDDD digital supply voltage VDD(TVDD) TVDD supply voltage VDD(PVDD) PVDD supply voltage [3] 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V Ipd power-down current VDDA = VDDD = VDD(TVDD) =VDD(PVDD) =3V hard power-down; pin NRSTPD set LOW [4] --5 A soft power-down; RF level detector on [4] - - 10 A IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register’s RcvOff bit = 1 - 3 5 mA IDD(PVDD) PVDD supply current pin PVDD [5] - - 40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8] - 60 100 mA Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 +85 C lndustrial version: Ipd power-down current VDDA = VDDD = VDD(TVDD) =VDD(PVDD) =3V hard power-down; pin NRSTPD set LOW [4] - - 15 A soft power-down; RF level detector on [4] - - 30 A Tamb ambient temperature HVQFN32 40 - +90 CPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 5 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 5. Ordering information Table 2. Ordering information Type number Package Name Description Version PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-1 PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-1 PN5120A0ET/C2 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT1336-1PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 6 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN512. The communication (S2C) interface provides digital signals to support communication for transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC. The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa. Various host interfaces are implemented to meet different customer requirements. Fig 1. Simplified block diagram of the PN512 001aaj627 HOST ANTENNA FIFO BUFFER ANALOG INTERFACE CONTACTLESS UART SERIAL UART SPI I 2C-BUS REGISTER BANKPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 7 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 2. Detailed block diagram of the PN512 001aak602 DVDD NRSTPD IRQ MFIN MFOUT SVDD OSCIN OSCOUT VMID AUX1 AUX2 RX TVSS TX1 TX2 TVDD 16 19 20 17 10, 14 11 13 12 DVSS AVDD SDA/NSS/RX EA I2C PVDD PVSS 24 32 1 52 D1/ADR_5 25 D2/ADR_4 26 D3/ADR_3 27 D4/ADR_2 28 D5/ADR_1/ SCK/DTRQ 29 D6/ADR_0/ MOSI/MX 30 D7/SCL/ MISO/TX 31 AVSS 3 6 23 7 8 9 21 22 4 15 18 FIFO CONTROL MIFARE CLASSIC UNIT STATE MACHINE COMMAND REGISTER PROGRAMABLE TIMER INTERRUPT CONTROL CRC16 GENERATION AND CHECK PARALLEL/SERIAL CONVERTER SERIAL DATA SWITCH TRANSMITTER CONTROL BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK BIT DECODING BIT ENCODING RANDOM NUMBER GENERATOR ANALOG TO DIGITAL CONVERTER I-CHANNEL AMPLIFIER ANALOG TEST MULTIPLEXOR AND DIGITAL TO ANALOG CONVERTER I-CHANNEL DEMODULATOR Q-CHANNEL AMPLIFIER CLOCK GENERATION, FILTERING AND DISTRIBUTION Q-CLOCK GENERATION OSCILLATOR TEMPERATURE SENSOR Q-CHANNEL DEMODULATOR AMPLITUDE RATING REFERENCE VOLTAGE 64-BYTE FIFO BUFFER CONTROL REGISTER BANK SPI, UART, I2C-BUS INTERFACE CONTROL VOLTAGE MONITOR AND POWER ON DETECT RESET CONTROL POWER-DOWN CONTROLPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 8 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1) Fig 4. Pinning configuration HVQFN40 (SOT618-1) 001aan212 PN512 Transparent top view RX SIGIN SIGOUT AVSS NRSTPD AUX1 PVSS AUX2 DVSS OSCIN DVDD OSCOUT PVDD IRQ A1 ALE SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID A0D7 D6 D5 D4 D3 D2 D1 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 001aan213 PN512 AVSS NRSTPD SIGIN AUX1 PVSS AUX2 DVSS OSCIN DVDD OSCOUT PVDD IRQ A5 NWR A4 NRD A3 ALE A2 NCS SIGOUT SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMIDRX A1A0D7 D6 D5 D4 D3 D2 D1 D0 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 11121314151617181920 40393837363534333231 terminal 1 index area Transparent top viewPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 9 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 5. Pin configuration TFBGA64 (SOT1336-1) aaa-005873 TFBGA64 Transparent top view ball A1 index area H G F E D C B A 1 3 5 78 246PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 10 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 7.2 Pin description Table 3. Pin description HVQFN32 Pin Symbol Type Description 1 A1 I Address Line 2 PVDD PWR Pad power supply 3 DVDD PWR Digital Power Supply 4 DVSS PWR Digital Ground 5 PVSS PWR Pad power supply ground 6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. 7 SIGIN I Communication Interface Input: accepts a digital, serial data stream 8 SIGOUT O Communication Interface Output: delivers a serial data stream 9 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads 10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 15 AVDD PWR Analog Power Supply 16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 17 RX I Receiver Input 18 AVSS PWR Analog Ground 19 AUX1 O Auxiliary Outputs: These pins are used for testing. 20 AUX2 O 21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). 22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 23 IRQ O Interrupt Request: output to signal an interrupt event 24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus. Remark: An 8-bit parallel interface is not available. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. Remark: For serial interfaces this pins can be used for test signals or I/Os. 32 A0 I Address LinePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 11 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 4. Pin description HVQFN40 Pin Symbol Type Description 1 to 4 A2 to A5 I Address Line 5 PVDD PWR Pad power supply 6 DVDD PWR Digital Power Supply 7 DVSS PWR Digital Ground 8 PVSS PWR Pad power supply ground 9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. 10 SIGIN I Communication Interface Input: accepts a digital, serial data stream 11 SIGOUT O Communication Interface Output: delivers a serial data stream 12 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads 13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 18 AVDD PWR Analog Power Supply 19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 20 RX I Receiver Input 21 AVSS PWR Analog Ground 22 AUX1 O Auxiliary Outputs: These pins are used for testing. 23 AUX2 O 24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). 25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 26 IRQ O Interrupt Request: output to signal an interrupt event 27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register 28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7) 29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512 31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. 39 to 40 A0 to A1 I Address LinePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 12 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 5. Pin description TFBGA64 Pin Symbol Type Description A1 to A5, A8, B3, B4, B8, E1 PVSS PWR Pad power supply ground A6 D4 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. A7 D2 I/O B1 PVDD PWR Pad power supply B2 A0 I Address Line B5 D5 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. B6 D3 I/O B7 D1 I/O C1 DVDD PWR Digital Power Supply C2 A1 I Address Line C3 D7 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. C4 D6 I/O C5 IRQ O Interrupt Request: output to signal an interrupt event C6 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. C7, C8, D6, D8, E6, E8, F7, G8, H8 AVSS PWR Analog Ground D1 DVSS PWR Digital Ground D2 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. D3 to D5, E3 to E5, F3, F4, G1 to G6, H1, H2, H6 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 D7 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. E2 SIGIN I Communication Interface Input: accepts a digital, serial data stream E7 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). F1 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads F2 SIGOUT O Communication Interface Output: delivers a serial data stream F5 AUX1 O Auxiliary Outputs: These pins are used for testing. F6 AUX2 O F8 RX I Receiver Input G7 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. H3 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrierPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 13 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier H7 AVDD PWR Analog Power Supply Table 5. Pin description TFBGA64 Pin Symbol Type DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 14 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8. Functional description The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols. PN512 transceiver IC supports the following operating modes: • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail. Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance. 8.1 ISO/IEC 14443 A/MIFARE functionality The physical level communication is shown in Figure 7. The physical parameters are described in Table 4. Fig 6. PN512 Read/Write mode 001aan218 BATTERY reader/writer contactless card MICROCONTROLLER PN512 ISO/IEC 14443 A CARD Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer Communication direction Signal type Transfer speed 106 kBd 212 kBd 424 kBd Reader to card (send data from the PN512 to a card) reader side modulation 100 % ASK 100 % ASK 100 % ASK bit encoding modified Miller encoding modified Miller encoding modified Miller encoding bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s) (1) (2) 001aan219 PN512 ISO/IEC 14443 A CARD ISO/IEC 14443 A READERPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 15 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The PN512’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol. Figure 8 shows the data coding and framing according to ISO/IEC 14443 A/MIFARE. The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the ManualRCVReg register’s ParityDisable bit. 8.2 ISO/IEC 14443 B functionality The PN512 reader IC fully supports international standard ISO 14443 which includes communication schemes ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. Card to reader (PN512 receives data from a card) card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit encoding Manchester encoding BPSK BPSK Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued Communication direction Signal type Transfer speed 106 kBd 212 kBd 424 kBd Fig 8. Data coding and framing according to ISO/IEC 14443 A 001aak585 ISO/IEC 14443 A framing at 106 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start odd start bit is 1 parity ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start even parity start bit is 0 burst of 32 subcarrier clocks even parity at the end of the framePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 16 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.3 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. The contactless UART of PN512 and a dedicated external host controller are required to handle the complete FeliCa protocol. 8.3.1 FeliCa framing and coding To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver. The following Len byte indicates the length of the sent data bytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first. To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the PN512 automatically and must not be written to the FIFO by the host controller. The PN512 performs internally the CRC calculation and adds the result to the data frame. Example for FeliCa CRC Calculation: Fig 9. FeliCa reader/writer communication diagram Table 7. Communication overview for FeliCa reader/writer Communication direction FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s PN512  card Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s card  PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK bit coding Manchester coding Manchester coding 2. PICC to PCD, > 12 % ASK loadmodulation Manchester coded, baudrate 212 to 424 kbaud 1. PCD to PICC, 8-30 % ASK Manchester coded, baudrate 212 to 424 kbaud 001aan214 PN512 FeliCa CARD (PICC) Felica READER (PCD) Table 8. FeliCa framing and coding Preamble Sync Len n-Data CRC 00h 00h 00h 00h 00h 00h B2h 4Dh Table 9. Start value for the CRC Polynomial: (00h), (00h) Preamble Sync Len 2 Data Bytes CRC 00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35hPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 17 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4 NFCIP-1 mode The NFCIP-1 communication differentiates between an active and a Passive Communication mode. • Active Communication mode means both the initiator and the target are using their own RF field to transmit data. • Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active in terms of generating the RF field. • Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication • Target: responds to initiator command either in a load modulation scheme in Passive Communication mode or using a self generated and self modulated RF field for Active Communication mode. In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. Fig 10. NFCIP-1 mode 001aan215 BATTERY initiator: active target: passive or active MICROCONTROLLER PN512 BATTERY MICROCONTROLLER PN512PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 18 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated external circuits. Fig 11. Active communication mode Table 10. Communication overview for Active communication mode Communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s Initiator  Target According to ISO/IEC 14443A 100 % ASK, Modified Miller Coded According to FeliCa, 8-30 % ASK Manchester Coded digital capability to handle this communication Target  Initiator host NFC INITIATOR powered to generate RF field 1. initiator starts communication at selected transfer speed Initial command response 2. target answers at the same transfer speed host NFC INITIATOR powered for digital processing host host NFC TARGET NFC TARGET powered for digital processing powered to generate RF field 001aan216PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 19 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated external circuits. Fig 12. Passive communication mode Table 11. Communication overview for Passive communication mode Communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s Initiator  Target According to ISO/IEC 14443A 100 % ASK, Modified Miller Coded According to FeliCa, 8-30 % ASK Manchester Coded digital capability to handle this communication Target  Initiator According to ISO/IEC 14443A subcarrier load modulation, Manchester Coded According to FeliCa, > 12 % ASK Manchester Coded host NFC INITIATOR powered to generate RF field 1. initiator starts communication at selected transfer speed 2. targets answers using load modulated data at the same transfer speed host NFC TARGET powered for digital processing 001aan217PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 20 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. 8.4.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is according to the following policy: • Speed shall not be changed while continuum data exchange in a transaction. • Transaction includes initialization and anticollision methods and data exchange (in continuous way, meaning no interruption by another transaction). In order not to disturb current infrastructure based on 13.56 MHz general rules to start NFCIP-1 communication are defined in the following way. 1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off. 2. The RF level detector is active. 3. Only if application requires the NFCIP-1 device shall switch to Initiator mode. 4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level detector during a time of TIDT. 5. The initiator performs initialization according to the selected mode. 8.4.5 MIFARE Card operation mode Table 12. Framing and coding overview Transfer speed Framing and Coding 106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme Table 13. MIFARE Card operation mode Communication direction ISO/IEC 14443A/ MIFARE MIFARE Higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s reader/writer  PN512 Modulation on reader side 100 % ASK 100 % ASK 100 % ASK bit coding Modified Miller Modified Miller Modified Miller Bitlength (128/13.56) s (64/13.56) s (32/13.56) s PN512  reader/ writer Modulation on PN512 side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding Manchester coding BPSK BPSKPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 21 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.6 FeliCa Card operation mode 9. PN512 register SET 9.1 PN512 registers overview Table 14. FeliCa Card operation mode Communication direction FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s reader/writer  PN512 Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s PN512  reader/ writer Load modulation on PN512 side > 12 % ASK load modulation > 12 % ASK load modulation bit coding Manchester coding Manchester coding Table 15. PN512 registers overview Addr (hex) Register Name Function Page 0: Command and Status 0 PageReg Selects the register page 1 CommandReg Starts and stops command execution 2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests 3 DivlEnReg Controls bits to enable and disable the passing of Interrupt Requests 4 ComIrqReg Contains Interrupt Request bits 5 DivIrqReg Contains Interrupt Request bits 6 ErrorReg Error bits showing the error status of the last command executed 7 Status1Reg Contains status bits for communication 8 Status2Reg Contains status bits of the receiver and transmitter 9 FIFODataReg In- and output of 64 byte FIFO-buffer A FIFOLevelReg Indicates the number of bytes stored in the FIFO B WaterLevelReg Defines the level for FIFO under- and overflow warning C ControlReg Contains miscellaneous Control Registers D BitFramingReg Adjustments for bit oriented frames E CollReg Bit position of the first bit collision detected on the RF-interface F RFU Reserved for future use Page 1: Command 0 PageReg Selects the register page 1 ModeReg Defines general modes for transmitting and receiving 2 TxModeReg Defines the data rate and framing during transmission 3 RxModeReg Defines the data rate and framing during receiving 4 TxControlReg Controls the logical behavior of the antenna driver pins TX1 and TX2 5 TxAutoReg Controls the setting of the antenna driversPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 22 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6 TxSelReg Selects the internal sources for the antenna driver 7 RxSelReg Selects internal receiver settings 8 RxThresholdReg Selects thresholds for the bit decoder 9 DemodReg Defines demodulator settings A FelNFC1Reg Defines the length of the valid range for the receive package B FelNFC2Reg Defines the length of the valid range for the receive package C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit D ManualRCVReg Allows manual fine tuning of the internal receiver E TypeBReg Configure the ISO/IEC 14443 type B F SerialSpeedReg Selects the speed of the serial UART interface Page 2: CFG 0 PageReg Selects the register page 1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation 2 3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when the driver is switched off 4 ModWidthReg Controls the setting of the ModWidth 5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit 6 RFCfgReg Configures the receiver gain and RF level 7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation when the drivers are switched on 8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during times of no modulation 9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during modulation A TModeReg TPrescalerReg Defines settings for the internal timer B C TReloadReg Describes the 16-bit timer reload value D E TCounterValReg Shows the 16-bit actual timer value F Page 3: TestRegister 0 PageReg selects the register page 1 TestSel1Reg General test signal configuration 2 TestSel2Reg General test signal configuration and PRBS control 3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial interfaces only) 4 TestPin ValueReg Defines the values for the 8-bit parallel bus when it is used as I/O bus 5 TestBusReg Shows the status of the internal testbus 6 AutoTestReg Controls the digital selftest Table 15. PN512 registers overview …continued Addr (hex) Register Name FunctionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 23 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.1.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In Table 16 the access conditions are described. 7 VersionReg Shows the version 8 AnalogTestReg Controls the pins AUX1 and AUX2 9 TestDAC1Reg Defines the test value for the TestDAC1 A TestDAC2Reg Defines the test value for the TestDAC2 B TestADCReg Shows the actual value of ADC I and Q C-F RFT Reserved for production tests Table 15. PN512 registers overview …continued Addr (hex) Register Name Function Table 16. Behavior of register bits and its designation Abbreviation Behavior Description r/w read and write These bits can be written and read by the -Controller. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the PageSelect-Register may be written and read by the -Controller. It will also be read by internal state machines, but never changed by them. dy dynamic These bits can be written and read by the -Controller. Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command. r read only These registers hold bits, which value is determined by internal states only, e.g. the CRCReady bit can not be written from external but shows internal states. w write only Reading these registers returns always ZERO. RFU - These registers are reserved for future use. In case of a PN512 Version version 2.0 (VersionReg = 82h) a read access to these registers returns always the value “0”. Nevertheless this is not guaranteed for future chips versions where the value is undefined. In case of a write access, it is recommended to write always the value “0”. RFT - These registers are reserved for production tests and shall not be changed.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 24 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2 Register description 9.2.1 Page 0: Command and status 9.2.1.1 PageReg Selects the register page. 9.2.1.2 CommandReg Starts and stops command execution. Table 17. PageReg register (address 00h); reset value: 00h, 0000000b 7 6 5 4 3 2 1 0 UsePage Select 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 18. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case it specifies the register page (which is A5 and A4 of the register address). Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 RcvOff Power Down Command Access Rights RFU RFU r/w dy dy dy dy dy Table 20. Description of CommandReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 RcvOff Set to logic 1, the analog part of the receiver is switched off. 4 PowerDown Set to logic 1, Soft Power-down mode is entered. Set to logic 0, the PN512 starts the wake up procedure. During this procedure this bit still shows a 1. A 0 indicates that the PN512 is ready for operations; see Section 16.2 “Soft power-down mode”. Note: The bit Power Down cannot be set, when the command SoftReset has been activated. 3 to 0 Command Activates a command according to the Command Code. Reading this register shows, which command is actually executed (see Section 19.3 “PN512 command overview”).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 25 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 22. Description of CommIEnReg bits Bit Symbol Description 7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of 1 ensures, that the output level on pin IRQ is 3-state. 6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. 5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. 4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. 3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. 2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. 1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated to pin IRQ. 0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 26 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn Access Rights r/w RFU RFU r/w r/w r/w r/w r/w Table 24. Description of DivIEnReg bits Bit Symbol Description 7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad. Set to logic 0, the pin IRQ works as open drain output pad. 6 to 5 - Reserved for future use. 4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ. 3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be propagated to pin IRQ. 2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be propagated to pin IRQ. 1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to be propagated to pin IRQ. 0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to be propagated to pin IRQ.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 27 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b 7 6 5 4 3 2 1 0 Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq Access Rights w dy dy dy dy dy dy dy Table 26. Description of CommIRqReg bits All bits in the register CommIRqReg shall be cleared by software. Bit Symbol Description 7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg are cleared. 6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out. 5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream. If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set to logic 1 when data bytes are available in the FIFO. 4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq. 3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1. 2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1. 1 ErrIRq Set to logic 1 if any error bit in the Error Register is set. 0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 28 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb 7 6 5 4 3 2 1 0 Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq Access Rights w RFU RFU dy dy dy dy dy Table 28. Description of DivIRqReg bits All bits in the register DivIRqReg shall be cleared by software. Bit Symbol Description 7 Set2 Set to logic 1, Set2 defines that the marked bits in the register DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register DivIRqReg are cleared 6 to 5 - Reserved for future use. 4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “S2C interface support”. This interrupt is set when either a rising or falling signal edge is detected. 3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode detector. Note: The Data mode detector can only be activated by the AutoColl command and is terminated automatically having detected the Communication mode. Note: The Data mode detector is automatically restarted after each RF Reset. 2 CRCIRq Set to logic 1, when the CRC command is active and all data are processed. 1 RFOnIRq Set to logic 1, when an external RF field is detected. 0 RFOffIRq Set to logic 1, when a present external RF field is switched off.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 29 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. [1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr Access Rights r rr r r r r r Table 30. Description of ErrorReg bits Bit Symbol Description 7 WrErr Set to logic 1, when data is written into FIFO by the host controller during the AutoColl command or MFAuthent command or if data is written into FIFO by the host controller during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface. 6 TempErr[1] Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically. 5 RFErr Set to logic 1, if in Active Communication mode the counterpart does not switch on the RF field in time as defined in NFCIP-1 standard. Note: RFErr is only used in Active Communication mode. The bits RxFraming or the bits TxFraming has to be set to 01 to enable this functionality. 4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine (e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer although the FIFO-buffer is already full. 3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit. During communication schemes at 212 and 424 kbit this bit is always set to logic 1. 2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the CRC calculation fails. It is cleared to 0 automatically at receiver start-up phase. 1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or NFCIP-1 communication at 106 kbit. 0 ProtocolErr Set to logic 1, if one out of the following cases occur: • Set to logic 1 if the SOF is incorrect. It is cleared automatically at receiver start-up phase. The bit is only valid for 106 kbit in Active and Passive Communication mode. • If bit DetectSync in register ModeReg is set to logic 1 during FeliCa communication or active communication with transfer speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in case of a byte length violation. • During the AutoColl command, bit ProtocolErr is set to logic 1, if the bit Initiator in register ControlReg is set to logic 1. • During the MFAuthent Command, bit ProtocolErr is set to logic 1, if the number of bytes received in one data stream is incorrect. • Set to logic 1, if the Miller Decoder detects 2 pulses below the minimum time according to the ISO/IEC 14443A definitions.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 30 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb 7 6 5 4 3 2 1 0 RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert Access Rights r r r r r rr r Table 32. Description of Status1Reg bits Bit Symbol Description 7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of 13.56 MHz. Set to logic 1, if the frequency at the RX pin is in the range 12 MHz < RX pin frequency < 15 MHz. Note: The value of RFFreqOK is not defined if the external RF frequency is in the range from 9 to 12 MHz or in the range from 15 to 19 MHz. 6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC co-processor, during calculation the value changes to ZERO, when the calculation is done correctly, the value changes to ONE. 5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only valid for the CRC co-processor calculation using the command CalcCRC. 4 IRq This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg). 3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will decrement the TCounterValReg with the next timer clock. Note: In the gated mode the bit TRunning is set to logic 1, when the timer is enabled by the register bits. This bit is not influenced by the gated signal. 2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store the state of the RF field. 1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer fulfills the following equation: Example: FIFOLength = 60, WaterLevel = 4  HiAlert = 1 FIFOLength = 59, WaterLevel = 4  HiAlert = 0 0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer fulfills the following equation: Example: FIFOLength = 4, WaterLevel = 4  LoAlert = 1 FIFOLength = 5, WaterLevel = 4  LoAlert = 0 HiAlert 64 FIFOLength =  –   WaterLevel LoAlert FIFOLength WaterLevel = PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 31 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TempSensClear I2CForceHS 0 TargetActivated MFCrypto1On Modem State Access Rights r/w r/w RFU dy dy r r r Table 34. Description of Status2Reg bits Bit Symbol Description 7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature is below the alarm limit of 125 C. 6 I2CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the High-speed mode independent of the I2C protocol. Set to logic 0, the I 2C input filter is set to the used I2C protocol. 5 - Reserved for future use. 4 TargetActivated Set to logic 1 if the Select command or if the Polling command was answered. Note: This bit can only be set during the AutoColl command in Passive Communication mode. Note: This bit is cleared automatically by switching off the external RF field. 3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and therefore all data communication with the card is encrypted. This bit can only be set to logic 1 by a successful execution of the MFAuthent Command. This bit is only valid in Reader/Writer mode for MIFARE cards. This bit shall be cleared by software. 2 to 0 Modem State ModemState shows the state of the transmitter and receiver state machines. Value Description 000 IDLE 001 Wait for StartSend in register BitFramingReg 010 TxWait: Wait until RF field is present, if the bit TxWaitRF is set to logic 1. The minimum time for TxWait is defined by the TxWaitReg register. 011 Sending 100 RxWait: Wait until RF field is present, if the bit RxWaitRF is set to logic 1. The minimum time for RxWait is defined by the RxWaitReg register. 101 Wait for data 110 ReceivingPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 32 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. 9.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 FIFOData Access Rights dy dy dy dy dy dy dy dy Table 36. Description of FIFODataReg bits Bit Symbol Description 7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The FIFO-buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs. Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 FlushBuffer FIFOLevel Access Rights w rrrrrrr Table 38. Description of FIFOLevelReg bits Bit Symbol Description 7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0. 6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the FIFODataReg increments, reading decrements the FIFOLevel.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 33 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. 9.2.1.13 ControlReg Miscellaneous control bits. Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b 7 6 5 4 3 2 1 0 0 0 WaterLevel Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 40. Description of WaterLevelReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or underflow: The bit HiAlert in Status1Reg is set to logic 1, if the remaining number of bytes in the FIFO-buffer space is equal or less than the defined number of WaterLevel bytes. The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO. Note: For the calculation of HiAlert and LoAlert see Table 31 Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits Access Rights w w dy r/w RFU r r r Table 42. Description of ControlReg bits Bit Symbol Description 7 TStopNow Set to logic 1, the timer stops immediately. Reading this bit will always return 0. 6 TStartNow Set to logic 1 starts the timer immediately. Reading this bit will always return 0. 5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the FIFO. Afterwards the bit is cleared automatically 4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target 3 - Reserved for future use. 2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the whole byte is valid.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 34 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 StartSend RxAlign 0 TxLastBits Access Rights w r/w r/w r/w RFU r/w r/w r/w Table 44. Description of BitFramingReg bits Bit Symbol Description 7 StartSend Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command. 6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position for the first bit received to be stored in the FIFO. Further received bits are stored at the following bit positions. Example: RxAlign = 0: the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1. RxAlign = 1: the LSB of the received bit is stored at bit 1, the second received bit is stored at bit position 2. RxAlign = 7: the LSB of the received bit is stored at bit 7, the second received bit is stored in the following byte at bit position 0. This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive Communication mode. In all other modes it shall be set to logic 0. 3 - Reserved for future use. 2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 35 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb 7 6 5 4 3 2 1 0 Values AfterColl 0 CollPos NotValid CollPos Access Rights r/w RFU r r r r r r Table 46. Description of CollReg bits Bit Symbol Description 7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a collision. This bit shall only be used during bitwise anticollision at 106 kbit, otherwise it shall be set to logic 1. 6 - Reserved for future use. 5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the Collision is out of the range of bits CollPos. This bit shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode. 4 to 0 CollPos These bits show the bit position of the first detected collision in a received frame, only data bits are interpreted. Example: 00h indicates a bit collision in the 32th bit 01h indicates a bit collision in the 1st bit 08h indicates a bit collision in the 8th bit These bits shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit CollPosNotValid is set to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 36 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2 Page 1: Communication 9.2.2.1 PageReg Selects the register page. Table 47. PageReg register (address 10h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePage Select 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 48. Description of PageReg bits Bit Symbol Description 7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to logic 1. In this case it specifies the register page (which is A5 and A4 of the register address).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 37 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b 7 6 5 4 3 2 1 0 MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 50. Description of ModeReg bits Bit Symbol Description 7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB first and the CRCResultMSB and the CRCResultLSB in the CRCResultReg register are bit reversed. Note: During RF communication this bit is ignored. 6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before the receiver is activated and F0h is added as a Sync-byte for transmission. This bit is only valid for 106 kbit during NFCIP-1 data exchange protocol. In all other modes it shall be set to logic 0. 5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for NFCIP-1 can only be started, if an RF field is generated. 4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field is detected in Target mode for NFCIP-1 or in Card Communication mode. 3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN pin is active low. Note: The internal envelope signal is coded active low. Note: Changing this bit will generate a SiginActIRq event. 2 ModeDetOff Set to logic 1, the internal mode detector is switched off. Note: The mode detector is only active during the AutoColl command. 1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command CalCRC. Note: During any communication, the preset values is selected automatically according to the definition in the bits RxMode and TxMode. Value Description 00 0000 01 6363 10 A671 11 FFFFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 38 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TxCRCEn TxSpeed InvMod TxMix TxFraming Access Rights r/w dy dy dy r/w r/w dy dy Table 52. Description of TxModeReg bits Bit Symbol Description 7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data transmission. Note: This bit shall only be set to logic 0 at 106 kbit. 6 to 4 TxSpeed Defines the bit rate while data transmission. Value Description 000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to the bit coding of Active Communication mode 424 kbit (Ecma 340). 3 InvMod Set to logic 1, the modulation for transmitting data is inverted. 2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder (see Section 12.6 “S2C interface support”). 1 to 0 TxFraming Defines the framing used for data transmission. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive communication mode 212 and 424 kbit 11 ISO/IEC 14443BPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 39 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming Access Rights r/w dy dy dy r/w r/w dy dy Table 54. Description of RxModeReg bits Bit Symbol Description 7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception. Note: This bit shall only be set to logic 0 at 106 kbit. 6 to 4 RxSpeed Defines the bit rate while data transmission. The PN512’s analog part handles only transfer speeds up to 424 kbit internally, the digital UART handles the higher transfer speeds as well. Value Description 000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to the bit coding of Active Communication mode 424 kbit (Ecma 340). 3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits received) will be ignored. The receiver will remain active. For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non valid datastream. 2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame. Set to logic 1, it is possible to receive more than one data frame. Having set this bit, the receive and transceive commands will not terminate automatically. In this case the multiple receiving can only be deactivated by writing any command (except the Receive command) to the CommandReg register or by clearing the bit by the host controller. At the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the ErrorReg register. The behaviour for version 1.0 is described in Section 21 “Errata sheet” on page 109.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 40 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. 1 to 0 RxFraming Defines the expected framing for data reception. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive Communication mode 212 and 424 kbit 11 ISO/IEC 14443B Table 54. Description of RxModeReg bits Bit Symbol Description Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 InvTx2RF On InvTx1RF On InvTx2RF Off InvTx1RF Off Tx2CW CheckRF Tx2RF En Tx1RF En Access Rights r/w r/w r/w r/w r/w w r/w r/w Table 56. Description of TxControlReg bits Bit Symbol Description 7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is enabled. 6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is enabled. 5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is disabled. 4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is disabled. 3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz energy carrier. Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy carrier. 2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF field is detected. Only valid when using in combination with bit Tx2RFEn or Tx1RFEn 1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier modulated by the transmission data. 0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier modulated by the transmission data.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 41 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 AutoRF OFF Force100 ASK Auto WakeUp 0 CAOn InitialRF On Tx2RFAut oEn Tx1RFAuto En Access Rights r/w r/w r/w RFU r/w r/w r/w r/w Table 58. Description of TxAutoReg bits Bit Symbol Description 7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last data bit has been transmitted as defined in the NFCIP-1. 6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation independent of the setting in register ModGsPReg. 5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by the RF level detector. 4 - Reserved for future use. 3 CAOn Set to logic 1, the collision avoidance is activated and internally the value n is set in accordance to the NFCIP-1 Standard. 2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit InitialRFOn is cleared automatically, if the RF is switched on. Note: The driver, which should be switched on, has to be enabled by bit Tx2RFAutoEn or bit Tx1RFAutoEn. 1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field is switched off according to the time TADT. If the bits InitialRFOn and Tx2RFAutoEn are set to logic 1, Tx2 is switched on if no external RF field is detected during the time TIDT. Note: The times TADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092). 0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field is switched off according to the time TADT. If the bit InitialRFOn and Tx1RFAutoEn are set to logic 1, Tx1 is switched on if no external RF field is detected during the time TIDT. Note: The times TADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 42 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.7 TxSelReg Selects the sources for the analog part. Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b 7 6 5 4 3 2 1 0 0 0 DriverSel SigOutSel Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 60. Description of TxSelReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 DriverSel Selects the input of driver Tx1 and Tx2. Value Description 00 Tristate Note: In soft power down the drivers are only in Tristate mode if DriverSel is set to Tristate mode. 01 Modulation signal (envelope) from the internal coder 10 Modulation signal (envelope) from SIGIN 11 HIGH Note: The HIGH level depends on the setting of InvTx1RFOn/ InvTx1RFOff and InvTx2RFOn/InvTx2RFOff.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 43 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 3 to 0 SigOutSel Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. 0100 Modulation signal (envelope) from the internal coder 0101 Serial data stream to be transmitted 0110 Output signal of the receiver circuit (card modulation signal regenerated and delayed). This signal is used as data output signal for SAM interface connection using 3 lines. Note: To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. Note: Do not use this setting in MIFARE mode. Manchester coding as data collisions will not be transmitted on the SIGOUT line. 0111 Serial data stream received. Note: Do not use this setting in MIFARE mode. Miller coding parameters as the bit length can vary. 1000-1011 FeliCa Sam modulation 1000 RX* 1001 TX 1010 Demodulator comparator output 1011 RFU Note: * To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. 1100-1111 MIFARE Sam modulation 1100 RX* with RF carrier 1101 TX with RF carrier 1110 RX with RF carrier un-filtered 1111 RX envelope un-filtered Note: *To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. Table 60. Description of TxSelReg bits …continued Bit Symbol DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 44 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.8 RxSelReg Selects internal receiver settings. 9.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b 7 6 5 4 3 2 1 0 UartSel RxWait Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 62. Description of RxSelReg bits Bit Symbol Description 7 to 6 UartSel Selects the input of the contactless UART Value Description 00 Constant Low 01 Envelope signal at SIGIN 10 Modulation signal from the internal analog part 11 Modulation signal from SIGIN pin. Only valid for transfer speeds above 424 kbit 5 to 0 RxWait After data transmission, the activation of the receiver is delayed for RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX is ignored. This parameter is ignored by the Receive command. All other commands (e.g. Transceive, Autocoll, MFAuthent) use this parameter. Depending on the mode of the PN512, the counter starts different. In Passive Communication mode the counter starts with the last modulation pulse of the transmitted data stream. In Active Communication mode the counter starts immediately after the external RF field is switched on. Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b 7 6 5 4 3 2 1 0 MinLevel 0 CollLevel Access Rights r/w r/w r/w r/w RFU r/w r/w r/w Table 64. Description of RxThresholdReg bits Bit Symbol Description 7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. 3 - Reserved for future use. 2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 45 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.10 DemodReg Defines demodulator settings. Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b 7 6 5 4 3 2 1 0 AddIQ FixIQ TPrescal Even TauRcv TauSync Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 66. Description of DemodReg bits Bit Symbol Description 7 to 6 AddIQ Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings. Value Description 00 Select the stronger channel 01 Select the stronger and freeze the selected during communication 10 combines the I and Q channel 11 Reserved 5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to I channel. If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to Q channel. NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ set to X0 is rewired. 4 TPrescalE ven If set to logic 0 the following formula is used to calculate fTimer of the prescaler: fTimer = 13.56 MHz / (2 * TPreScaler + 1). If set to logic 1 the following formula is used to calculate fTimer of the prescaler: fTimer = 13.56 MHz / (2 * TPreScaler + 2). (Default TPrescalEven is logic 0) The behaviour for the version 1.0 is described in Section 21 “Errata sheet” on page 109. 3 to 2 TauRcv Changes the time constant of the internal during data reception. Note: If set to 00, the PLL is frozen during data reception. 1 to 0 TauSync Changes the time constant of the internal PLL during burst.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 46 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 FelSyncLen DataLenMin Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 68. Description of FelNFC1Reg bits Bit Symbol Description 7 to 6 FelSyncLen Defines the length of the Sync bytes. Value Sync- bytes in hex 00 B2 4D 01 00 B2 4D 10 00 00 B2 4D 11 00 00 00 B2 4D 5 to 0 DataLenMin These bits define the minimum length of the accepted packet length: DataLenMin * 4  data packet length This parameter is ignored at 106 kbit if the bit DetectSync in register ModeReg is set to logic 0. If a received data packet is shorter than the defined DataLenMin value, the data packet will be ignored.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 47 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WaitForSelected ShortTimeSlot DataLenMax Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 70. Description of FelNFC2Reg bits Bit Symbol Description 7 WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1. A valid command has been received after performing a valid Select procedure according ISO/IEC 14443A. 2. A valid command has been received after performing a valid Polling procedure according to the FeliCa specification. Note: If this bit is set, no active communication is possible. Note: Setting this bit reduces the host controller interaction in case of a communication to another device in the same RF field during Passive Communication mode. 6 ShortTimeSlot Defines the time slot length for Passive Communication mode at 424 kbit. Set to logic 1 a short time slot is used (half of the timeslot at 212 kbit). Set to logic 0 a long timeslot is used (equal to the timeslot for 212 kbit). 5 to 0 DataLenMax These bits define the maximum length of the accepted packet length: DataLenMax * 4  data packet length Note: If set to logic 0 the maximum data length is 256 bytes. This parameter is ignored at 106 kbit if the bit DetectSync in register ModeReg is set to logic 0. If a received packet is larger than the defined DataLenMax value, the packet will be ignored.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 48 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b 7 6 5 4 3 2 1 0 SensMiller TauMiller MFHalted TxWait Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 72. Description of MifNFCReg bits Bit Symbol Description 7 to 5 SensMiller These bits define the sensitivity of the Miller decoder. 4 to 3 TauMiller These bits define the time constant of the Miller decoder. 2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in Card Operation mode at 106 kbit. This bit is either set by the host controller or by the internal state machine and indicates that only the code 52h is accepted as a request command. This bit is cleared automatically by a RF reset. 1 to 0 TxWait These bits define the minimum response time between receive and transmit in number of data bits + 7 data bits. The shortest possible minimum response time is 7 data bits. (TxWait=0). The minimum response time can be increased by the number of bits defined in TxWait. The longest minimum response time is 10 data bits (TxWait = 3). If a transmission of a frame is started before the minimum response time is over, the PN512 waits before transmitting the data until the minimum response time is over. If a transmission of a frame is started after the minimum response time is over, the frame is started immediately if the data bit synchronization is correct. (adjustable with TxBitPhase).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 49 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 0 FastFilt MF_SO Delay MF_SO Parity Disable LargeBW PLL Manual HPCF HPFC Access Rights RFU r/w r/w r/w r/w r/w r/w r/w Table 74. Description of ManualRCVReg bits Bit Symbol Description 7 - Reserved for future use. 6 FastFilt MF_SO If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is set to Fast mode. Note: This bit should only set to logic 1, if Millerpulses of less than 400 ns Pulse length are expected. At 106 kBaud the typical value is 3 us. 5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that in SAM mode the Signal at SIGIN must be 128/fc faster compared to the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the RF-Field. Note: This delay shall only be activated for setting bits SigOutSel to (1110b) or (1111b) in register TxSelReg. 4 Parity Disable If this bit is set to logic 1, the generation of the Parity bit for transmission and the Parity-Check for receiving is switched off. The received Parity bit is handled like a data bit. 3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock recovery is extended. 2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are adapted automatically to the receiving mode. Set to logic 1, values of HPCF are valid. 1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the internal receiver chain 00 For signals with frequency spectrum down to 106 kHz. 01 For signals with frequency spectrum down to 212 kHz. 10 For signals with frequency spectrum down to 424 kHz. 11 For signals with frequency spectrum down to 848 kHzPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 50 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.15 TypeBReg 9.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 RxSOF Req RxEOF Req 0 EOFSO FWidth NoTxSOF NoTxEOF TxEGT Access Rights r/w r/w RFU r/w r/w r/w r/w r/w Table 76. Description of TypeBReg bits Bit Symbol Description 7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting without SOF is ignored. If this bit is cleared, a datastream with and without SOF is accepted. The SOF will be removed and not written into the FIFO. 6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending without EOF will generate a Protocol-Error. If this bit is cleared, a datastream with and without EOF is accepted. The EOF will be removed and not written into the FIFO. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 5 - Reserved for future use. 4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF and EOF will have the maximum length defined in ISO/IEC 14443B. If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and EOF will have the minimum length defined in ISO/IEC 14443B. If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in SOF low = (11etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in an incorrect system behavior in respect to ISO specification. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed. 2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed. 1 to 0 TxEGT These bits define the length of the EGT. Value Description 00 0 bit 01 1 bit 10 2 bits 11 3 bitsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 51 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b 7 6 5 4 3 2 1 0 BR_T0 BR_T1 Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 78. Description of SerialSpeedReg bits Bit Symbol Description 7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”. 3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 52 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3 Page 2: Configuration 9.2.3.1 PageReg Selects the register page. 9.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Note: The CRC is split into two 8-bit register. Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is not changed. Table 79. PageReg register (address 20h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePageSelect 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 80. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case, it specifies the register page (which is A5 and A4of the register address). Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 CRCResultMSB Access Rights r r r r r r r r Table 82. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of the CRCResultReg register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 CRCResultLSB Access Rights r r r r r r r r Table 84. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 53 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.3 GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b 7 6 5 4 3 2 1 0 CWGsNOff ModGsNOff Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 86. Description of GsNOffReg bits Bit Symbol Description 7 to 4 CWGsNOff The value of this register defines the conductance of the output N-driver during times of no modulation. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched off. Otherwise the bit value CWGsNOn of register GsNOnReg is used. Note: This value is used for LoadModulation. 3 to 0 ModGsNOff The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched off. Otherwise the bit value ModGsNOn of register GsNOnReg is used Note: This value is used for LoadModulation.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 54 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.4 ModWidthReg Controls the modulation width settings. 9.2.3.5 TxBitPhaseReg Adjust the bitphase at 106 kbit during transmission. Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b 7 6 5 4 3 2 1 0 ModWidth Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 88. Description of ModWidthReg bits Bit Symbol Description 7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active and Passive Communication mode as multiples of the carrier frequency (ModWidth + 1/fc). The maximum value is half the bit period. Acting as a target in Passive Communication mode at 106 kbit or in Card Operating mode for ISO/IEC 14443A/MIFARE these bits are used to change the duty cycle of the subcarrier frequency. The resulting number of carrier periods are calculated according to the following formulas: LOW value: #clocksLOW = (ModWidth modulo 8) + 1. HIGH value: #clocksHIGH = 16-#clocksLOW. Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b 7 6 5 4 3 2 1 0 RcvClkChange TxBitPhase Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 90. Description of TxBitPhaseReg bits Bit Symbol Description 7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF field. 6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock cycles, which are added to the waiting period before transmitting data in all communication modes. TXBitPhase is used to adjust the TX bit synchronization during passive NFCIP-1 communication mode at 106 kbit and in ISO/IEC 14443A/MIFARE card mode.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 55 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b 7 6 5 4 3 2 1 0 RFLevelAmp RxGain RFLevel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 92. Description of RFCfgReg bits Bit Symbol Description 7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier. 6 to 4 RxGain This register defines the receivers signal voltage gain factor: Value Description 000 18 dB 001 23 dB 010 18 dB 011 23 dB 100 33 dB 101 38 dB 110 43 dB 111 48 dB 3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see Section 12.3 “RF level detector”.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 56 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. 9.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b 7 6 5 4 3 2 1 0 CWGsNOn ModGsNOn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 94. Description of GsNOnReg bits Bit Symbol Description 7 to 4 CWGsNOn The value of this register defines the conductance of the output N-driver during times of no modulation. This may be used to regulate the output power and subsequently current consumption and operating distance. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or TX2 are switched on. Otherwise the value of the bits CWGsNOff of register GsNOffReg is used. 3 to 0 ModGsNOn The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or Tx2 are switched on. Otherwise the value of the bits ModsNOff of register GsNOffReg is used. Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 CWGsP Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 96. Description of CWGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 CWGsP The value of this register defines the conductance of the output P-driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 57 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. [1] If Force100ASK is set to logic 1, the value of ModGsP has no effect. 9.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Note: The Prescaler value is split into two 8-bit registers Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 ModGsP Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 98. Description of ModGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 ModGsP[1] The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TAuto TGated TAutoRestart TPrescaler_Hi Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 100. Description of TModeReg bits Bit Symbol Description 7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission in all communication modes at all speeds or when bit InitialRFOn is set to logic 1 and the RF field is switched on. In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is not set. In all other modes, the timer stops after the 4th bit if the bit RxMultiple the register RxModeReg is not set. If RxMultiple is set to logic 1, the timer never stops. In this case the timer can be stopped by setting the bit TStopNow in register ControlReg to 1. Set to logic 0 indicates, that the timer is not influenced by the protocol.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 58 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6 to 5 TGated The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits. This bit does not influence the gating signal. Value Description 00 Non gated mode 01 Gated by SIGIN 10 Gated by AUX1 11 Gated by A3 4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from TReloadValue, instead of counting down to zero. Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set to logic 1. 3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler. The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 0: fTimer = 13.56 MHz/(2*TPreScaler+1). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) (Default TPrescalEven is logic 0) The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1: fTimer = 13.56 MHz/(2*TPreScaler+2). For detailed description see Section 15 “Timer unit”. For the behaviour within version 1.0, see Section 21 “Errata sheet” on page 109. Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TPrescaler_Lo Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 102. Description of TPrescalerReg bits Bit Symbol Description 7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler. The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 0: fTimer = 13.56 MHz/(2*TPreScaler+1). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1: fTimer = 13.56 MHz/(2*TPreScaler+2). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) For detailed description see Section 15 “Timer unit”. Table 100. Description of TModeReg bits …continued Bit Symbol DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 59 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TReloadVal_Hi Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 104. Description of the higher TReloadReg bits Bit Symbol Description 7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TReloadVal_Lo Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 106. Description of lower TReloadReg bits Bit Symbol Description 7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 60 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. 9.2.4 Page 3: Test 9.2.4.1 PageReg Selects the register page. Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TCounterVal_Hi Access Rights rrrrrrrr Table 108. Description of the higher TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits. Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TCounterVal_Lo Access Rights rrrrrrrr Table 110. Description of lower TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits. Table 111. PageReg register (address 30h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePageSelect 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/wPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 61 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 112. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case, it specifies the register page (which is A5 and A4 of the register address).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 62 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.2 TestSel1Reg General test signal configuration. 9.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 - - SAMClockSel SAMClkD1 TstBusBitSel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 114. Description of TestSel1Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock Value Description 00 GND- Sam Clock switched off 01 clock derived by the internal oscillator 10 internal UART clock 11 clock derived by the RF field 3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1. Note: Only possible if the 8bit parallel interface is not used. 2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT. Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TstBusFlip PRBS9 PRBS15 TestBusSel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 116. Description of TestSel2Reg bits Bit Symbol Description 7 TstBusFlip If set to logic 1, the testbus is mapped to the parallel port by the following order: D4, D3, D2, D6, D5, D0, D1. See Section 20 “Testsignals”. 6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150. Note: All relevant registers to transmit data have to be configured before entering PRBS9 mode. Note: The data transmission of the defined sequence is started by the send command. 5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150. Note: All relevant registers to transmit data have to be configured before entering PRBS15 mode. Note: The data transmission of the defined sequence is started by the send command. 4 to 0 TestBusSel Selects the testbus. See Section 20 “Testsignals”PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 63 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. 9.2.4.5 TestPinValueReg Defines the values for the 7-bit parallel port when it is used as I/O. Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 RS232LineEn TestPinEn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 118. Description of TestPinEnReg bits Bit Symbol Description 7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are disabled. 6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface. Example: Setting bit 0 to 1 enables D0 Setting bit 5 to 1 enables D5 Note: Only valid if one of serial interfaces is used. If the SPI interface is used only D0 to D4 can be used. If the serial UART interface is used and RS232LineEn is set to logic 1 only D0 to D4 can be used. Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UseIO TestPinValue Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 120. Description of TestPinValueReg bits Bit Symbol Description 7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel port in case one of the serial interfaces is used. The input/output behavior is defined by TestPinEn in register TestPinEnReg. The value for the output behavior is defined in the bits TestPinVal. Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O. 6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each output has to be enabled by the TestPinEn bits in register TestPinEnReg. Note: Reading the register indicates the actual status of the pins D6 - D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the register TestPinValueReg is read back. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 64 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.6 TestBusReg Shows the status of the internal testbus. 9.2.4.7 AutoTestReg Controls the digital selftest. 9.2.4.8 VersionReg Shows the version. Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TestBus Access Rights r r r r r r r r Table 122. Description of TestBusReg bits Bit Symbol Description 7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the register TestSel2Reg. See Section 20 “Testsignals”. Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b 7 6 5 4 3 2 1 0 0 AmpRcv EOFSO FAdjust - SelfTest Access Rights RFT r/w RFU RFU r/w r/w r/w r/w Table 124. Description of bits Bit Symbol Description 7 - Reserved for production tests. 6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is performed non-linear. This increases the operating distance in communication modes at 106 kbit. Note: Due to the non linearity the effect of the bits MinLevel and CollLevel in the register RxThreshholdReg are as well non linear. 5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the Maximum length of SOF and EOF according to ISO/IEC14443B If set to logic 0 and the EOFSOFwidth is set to 0 will result in the Minimum length of SOF and EOF according to ISO/IEC14443B If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in SOF low = (11 etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 4 - Reserved for future use. 3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest command in the command register. The selftest is enabled by 1001. Note: For default operation the selftest has to be disabled by 0000.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 65 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 Version Access Rights r r r r r r r r Table 126. Description of VersionReg bits Bit Symbol Description 7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are described within Section 21 “Errata sheet” on page 109. 82h indicates PN512 version 2.0, which covers also the industrial version.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 66 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 AnalogSelAux1 AnalogSelAux2 Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 128. Description of AnalogTestReg bits Bit Symbol Description 7 to 4 3 to 0 AnalogSelAux1 AnalogSelAux2 Controls the AUX pin. Note: All test signals are described in Section 20 “Testsignals”. Value Description 0000 Tristate 0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2) Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0010 Testsignal Corr1 Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0011 Testsignal Corr2 Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0100 Testsignal MinLevel Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0101 Testsignal ADC channel I Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0110 Testsignal ADC channel Q Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0111 Testsignal ADC channel I combined with Q Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1000 Testsignal for production test Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1001 SAM clock (13.56 MHz) 1010 HIGH 1011 LOW 1100 TxActive At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High during Preamble, Sync, Data and CRC. 1101 RxActive At 106 kbit: High during databit, Parity and CRC. At 212 and 424 kbit: High during data and CRC. 1110 Subcarrier detected 106 kbit: not applicable 212 and 424 kbit: High during last part of Preamble, Sync data and CRC 1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 67 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. 9.2.4.11 TestDAC2Reg Defines the testvalue for TestDAC2. 9.2.4.12 TestADCReg Shows the actual value of ADC I and Q channel. Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb 7 6 5 4 3 2 1 0 0 0 TestDAC1 Access Rights RFT RFU r/w r/w r/w r/w r/w r/w Table 130. Description of TestDAC1Reg bits Bit Symbol Description 7 - Reserved for production tests. 6 - Reserved for future use. 5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be switched to AUX1 by setting AnalogSelAux1 to 0001 in register AnalogTestReg. Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb 7 6 5 4 3 2 1 0 0 0 TestDAC2 Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 132. Description ofTestDAC2Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be switched to AUX2 by setting AnalogSelAux2 to 0001 in register AnalogTestReg. Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 ADC_I ADC_Q Access Rights Table 134. Description of TestADCReg bits Bit Symbol Description 7 to 4 ADC_I Shows the actual value of ADC I channel. 3 to 0 ADC_Q Shows the actual value of ADC Q channel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 68 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.13 RFTReg 10. Digital interfaces 10.1 Automatic microcontroller interface detection The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART interfaces. The PN512 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The PN512 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections. Table 141 shows the different connection configurations. Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 11111111 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 136. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 00000000 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 138. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b 7 6 5 4 3 2 1 0 00000011 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 140. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 69 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] only available in HVQFN 40. Table 141. Connection protocol for detecting different interface types Pin Interface type UART (input) SPI (output) I 2C-bus (I/O) SDA RX NSS SDA I 2C0 0 1 EA 0 1 EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5 Table 142. Connection scheme for detecting the different interface types PN512 Parallel Interface Type Serial Interface Types Separated Read/Write Strobe Common Read/Write Strobe Pin Dedicated Address Bus Multiplexed Address Bus Dedicated Address Bus Multiplexed Address Bus UART SPI I 2C ALE 1 ALE 1 AS RX NSS SDA A5[1] A5 0 A5 0 0 0 0 A4[1] A4 0 A4 0 0 0 0 A3[1] A3 0 A3 0 0 0 0 A2[1] A2 1 A2 1 0 0 0 A1 A1 1 A1 1 0 0 1 A0 A0 1 A0 0 0 1 EA NRD[1] NRD NRD NDS NDS 1 1 1 NWR[1] NWR NWR RD/NWR RD/NWR 1 1 1 NCS[1] NCS NCS NCS NCS NCS NCS NCS D7 D7 D7 D7 D7 TX MISO SCL D6 D6 D6 D6 D6 MX MOSI ADR_0 D5 D5 AD5 D5 AD5 DTRQ SCK ADR_1 D4 D4 AD4 D4 AD4 - - ADR_2 D3 D3 AD3 D3 AD3 - - ADR_3 D2 D2 AD2 D2 AD2 - - ADR_4 D1 D1 AD1 D1 AD1 - - ADR_5 D0 D0 AD0 D0 AD0 - - ADR_6 Remark: Overview on the pin behavior Pin behavior Input Output In/OutPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 70 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds up to 10 Mbit/s. When communicating with a host, the PN512 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication. An interface compatible with SPI enables high-speed serial communication between the PN512 and a microcontroller. The implemented interface is in accordance with the SPI standard. The timing specification is given in Section 26.1 on page 117. The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line is used to send data from the PN512 to the master. Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is provided by the PN512 on the falling clock edge and is stable during the rising clock edge. 10.2.1 SPI read data Reading data using SPI requires the byte order shown in Table 143 to be used. It is possible to read out up to n-data bytes. The first byte sent defines both the mode and the address. [1] X = Do not care. Remark: The MSB must be sent first. 10.2.2 SPI write data To write data to the PN512 using SPI requires the byte order shown in Table 144. It is possible to write up to n data bytes by only sending one address byte. Fig 13. SPI connection to host 001aan220 PN512 SCK SCK MOSI MOSI MISO MISO NSS NSS Table 143. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 address 1 address 2 ... address n 00 MISO X[1] data 0 data 1 ... data n  1 data nPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 71 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The first send byte defines both the mode and the address byte. [1] X = Do not care. Remark: The MSB must be sent first. 10.2.3 SPI address byte The address byte has to meet the following format. The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is set to logic 1. To write data to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define the address and the LSB is set to logic 0. 10.3 UART interface 10.3.1 Connection to a host Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s RS232LineEn bit. 10.3.2 Selectable UART transfer speeds The internal UART interface is compatible with an RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new transfer speed to the SerialSpeedReg register. Bits BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the SerialSpeedReg register. The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different transfer speeds and the relevant register settings are given in Table 11. Table 144. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 data 0 data 1 ... data n  1 data n MISO X[1] X[1] X[1] ... X[1] X[1] Table 145. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write address 0 Fig 14. UART connection to microcontrollers 001aan221 PN512 RX RX TX TX DTRQ DTRQ MX MXPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 72 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds. The selectable transfer speeds shown in Table 11 are calculated according to the following equations: If BR_T0[2:0] = 0: (1) If BR_T0[2:0] > 0: (2) Remark: Transfer speeds above 1228.8 kBd are not supported. 10.3.3 UART framing Table 146. BR_T0 and BR_T1 settings BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 BR_T0 factor 1 1 2 4 8 16 32 64 BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 147. Selectable UART transfer speeds Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1] Decimal Hexadecimal 7.2 250 FAh 0.25 9.6 235 EBh 0.32 14.4 218 DAh 0.25 19.2 203 CBh 0.32 38.4 171 ABh 0.32 57.6 154 9Ah 0.25 115.2 122 7Ah 0.25 128 116 74h 0.06 230.4 90 5Ah 0.25 460.8 58 3Ah 0.25 921.6 28 1Ch 1.45 1228.8 21 15h 0.32 transfer speed 27.12 106    BR_T0 1 + = -------------------------------- transfer speed 27.12 106    BR_T1 33 + 2   BR_T0 1 – ----------------------------------- -----------------------------------           = Table 148. UART framing Bit Length Value Start 1-bit 0 Data 8 bits data Stop 1-bit 1PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 73 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the flow shown in Table 149 must be used. The first byte sent defines both the mode and the address. Write data: To write data to the PN512 using the UART interface, the structure shown in Table 150 must be used. The first byte sent defines both the mode and the address. Table 149. Read data byte order Pin Byte 0 Byte 1 RX (pin 24) address - TX (pin 31) - data 0 (1) Reserved. Fig 15. UART read data timing diagram 001aak588 SA ADDRESS RX TX MX DTRQ A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO DATA R/W Table 150. Write data byte order Pin Byte 0 Byte 1 RX (pin 24) address 0 data 0 TX (pin 31) - address 0xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 4.5 — 17 December 2013 111345 74 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The address byte has to meet the following format: (1) Reserved. Fig 16. UART write data timing diagram 001aak589 SA ADDRESS RX TX MX DTRQ A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO SA A0 A1 A2 A3 A4 A5 (1) SO DATA ADDRESS R/W R/WPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 75 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 151. 10.4 I2C Bus Interface An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I2C-bus interface is implemented according to NXP Semiconductors’ I 2C-bus interface specification, rev. 2.1, January 2000. The interface can only act in Slave mode. Therefore the PN512 does not implement clock generation or access arbitration. The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The PN512 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode. If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA as defined in the I2C-bus interface specification. See Table 171 on page 117 for timing requirements. Table 151. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write reserved address Fig 17. I2C-bus interface 001aan222 PN512 SDA SCL I2C EA ADR_[5:0] PULL-UP NETWORK CONFIGURATION WIRING PULL-UP NETWORK MICROCONTROLLERPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 76 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. 10.4.2 START and STOP conditions To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. • A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH. • A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH. The I2C-bus master always generates the START and STOP conditions. The bus is busy after the START condition. The bus is free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. The START (S) and repeated START (Sr) conditions are functionally identical. Therefore, S is used as a generic term to represent both the START (S) and repeated START (Sr) conditions. 10.4.3 Byte format Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first; see Figure 22. The number of transmitted bytes during one data transfer is unrestricted but must meet the read/write cycle format. Fig 18. Bit transfer on the I2C-bus mbc621 data line stable; data valid change of data allowed SDA SCL Fig 19. START and STOP conditions mbc622 SDA SCL P STOP condition SDA SCL S START conditionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 77 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer or a repeated START (Sr) condition to start a new transfer. A master-receiver indicates the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter releases the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. Fig 20. Acknowledge on the I2C-bus mbc602 S START condition 1 2 8 9 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master Fig 21. Data transfer on the I2C-bus msc608 Sr or P SDA Sr P SCL STOP or repeated START condition S or Sr START or repeated START condition 1 2 3 - 8 9 ACK 9 ACK 1 2 7 8 MSB acknowledgement signal from slave byte complete, interrupt within slave clock line held LOW while interrupts are serviced acknowledgement signal from receiverPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 78 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.5 7-Bit addressing During the I2C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I 2C-bus specification for a complete list of reserved addresses. The I2C-bus address specification is dependent on the definition of pin EA. Immediately after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus address according to pin EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I2C-bus devices. If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins according to Table 141 on page 69. ADR_6 is always set to logic 0. In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration. Depending on the external wiring, the I2C-bus address pins can be used for test signal outputs. 10.4.6 Register write access To write data from the host controller using the I2C-bus to a specific register in the PN512 the following frame format must be used. • The first byte of a frame indicates the device address according to the I2C-bus rules. • The second byte indicates the register address followed by up to n-data bytes. In one frame all data bytes are written to the same register address. This enables fast FIFO buffer access. The Read/Write (R/W) bit is set to logic 0. Fig 22. First byte following the START procedure slave address 001aak591 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W MSB LSBPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 79 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.7 Register read access To read out data from a specific register address in the PN512, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I2C-bus rules • The second byte indicates the register address. No data bytes are added • The Read/Write bit is 0 After the write access, read access can start. The host sends the device address of the PN512. In response, the PN512 sends the content of the read access register. In one frame all data bytes can be read from the same register address. This enables fast FIFO buffer access or register polling. The Read/Write (R/W) bit is set to logic 1. Fig 23. Register read and write access 001aak592 S A 0 0 I 2C-BUS SLAVE ADDRESS [A7:A0] JOINER REGISTER ADDRESS [A5:A0] write cycle 0 (W) A DATA [7:0] [0:n] [0:n] [0:n] A P S A 0 0 I 2C-BUS SLAVE ADDRESS [A7:A0] JOINER REGISTER ADDRESS [A5:A0] read cycle optional, if the previous access was on the same register address 0 (W) A P P S S start condition P stop condition A acknowledge A not acknowledge W write cycle R read cycle A I 2C-BUS SLAVE ADDRESS [A7:A0] sent by master sent by slave DATA [7:0] 1 (R) A DATA [7:0] APN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 80 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates of up to 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system. 10.4.9 High-speed transfer To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to I 2C-bus operation. • The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger on the SDA and SCL inputs and different timing constants when compared to F/S mode • The output buffers of the device in HS mode incorporate slope control of the falling edges of the SDA and SCL signals with different fall times compared to F/S mode 10.4.10 Serial data transfer format in HS mode The HS mode serial data transfer format meets the Standard mode I2C-bus specification. HS mode can only start after all of the following conditions (all of which are in F/S mode): 1. START condition (S) 2. 8-bit master code (00001XXXb) 3. Not-acknowledge bit (A) When HS mode starts, the active master sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from the selected PN512. Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions (Sr). Fig 24. I2C-bus HS mode protocol switch F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode 001aak749 A A/A A DATA (n-bytes + A) S MASTER CODE Sr SLAVE ADDRESS R/W HS mode continues Sr SLAVE ADDRESS PPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 81 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 25. I2C-bus HS mode protocol frame msc618 8-bit master code 0000 1xxx A tH t1 S F/S mode HS mode If P then F/S mode If Sr (dotted lines) then HS mode 1 6789 6789 1 1 2 to 5 2 to 5 2 to 5 67 89 SDA high SCL high SDA high SCL high tH tFS Sr Sr P 7-bit SLA R/W A n + (8-bit data + A/A) = Master current source pull-up = Resistor pull-upPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 82 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.11 Switching between F/S mode and HS mode After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting. The following actions are taken: 1. Adapt the SDA and SCL input filters according to the spike suppression requirement in HS mode. 2. Adapt the slope control of the SDA output stages. It is possible for system configurations that do not have other I2C-bus devices involved in the communication to switch to HS mode permanently. This is implemented by setting Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code is not required to be sent. This is not defined in the specification and must only be used when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines must be avoided because of the reduced spike suppression. 10.4.12 PN512 at lower speed modes PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus system. The device stays in F/S mode and communicates at F/S mode speeds because a master code is not transmitted in this configuration. 11. 8-bit parallel interface The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola compatible modes. 11.1 Overview of supported host controller interfaces The PN512 supports direct interfacing to various -Controllers. The following table shows the parallel interface types supported by the PN512. Table 152. Supported interface types Supported interface types Bus Separated Address and Data Bus Multiplexed Address and Data Bus Separated Read and Write Strobes (INTEL compatible) control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7 Multiplexed Read and Write Strobe (Motorola compatible) control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 83 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 11.2 Separated Read/Write strobe For timing requirements refer to Section 26.2 “8-bit parallel interface timing”. 11.3 Common Read/Write strobe For timing requirements refer to Section 26.2 “8-bit parallel interface timing” Fig 26. Connection to host controller with separated Read/Write strobes 001aan223 PN512 NCS A0...A3[A5*] D0...D7 A0 A1 A2 A3 A4* A5* address bus (A0...A3[A5*]) ALE NRD NWR ADDRESS DECODER data bus (D0...D7) high not data strobe (NRD) not write (NWR) address bus remark: *depending on the package type. multiplexed address/data AD0...AD7) PN512 NCS D0...D7 ALE NRD NWR ADDRESS DECODER low low high high high low address latch enable (ALE) not read strobe (NRD) not write (NWR) non multiplexed address Fig 27. Connection to host controller with common Read/Write strobes 001aan224 PN512 NCS A0...A3[A5*] D0...D7 A0 A1 A2 A3 A4* A5* address bus (A0...A3[A5*]) ALE NRD NWR ADDRESS DECODER Data bus (D0...D7) high not data strobe (NDS) read not write (RD/NWR) address bus remark: *depending on the package type. multiplexed address/data AD0...AD7) PN512 NCS D0...D7 ALE NRD NWR ADDRESS DECODER low low high high low low address strobe (AS) not data strobe (NDS) read not write (RD/NWR) non multiplexed addressPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 84 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12. Analog interface and contactless UART 12.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In addition, it handles error detection such as parity and CRC, based on the various supported contactless communication protocols. Remark: The size and tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance. 12.2 TX driver The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering; see Section 15 on page 96. The signal on pins TX1 and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on page 40. The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning. The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds. [1] X = Do not care. Table 153. Register and bit settings controlling the signal on pin TX1 Bit Tx1RFEn Bit Force 100ASK Bit InvTx1RFOn Bit InvTx1RFOff Envelope Pin TX1 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is switched off 1 00 X[1] 0 RF pMod nMod 100 % ASK: pin TX1 pulled to logic 0, independent of the InvTx1RFOff bit 1 RF pCW nCW 01 X[1] 0 RF pMod nMod 1 RF pCW nCW 11 X[1] 0 0 pMod nMod 1 RF_n pCW nCWPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 85 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] X = Do not care. The following abbreviations have been used in Table 153 and Table 154: • RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 • RF_n: inverted 13.56 MHz clock • GSPMos: conductance, configuration of the PMOS array • GSNMos: conductance, configuration of the NMOS array • pCW: PMOS conductance value for continuous wave defined by the CWGsPReg register • pMod: PMOS conductance value for modulation defined by the ModGsPReg register • nCW: NMOS conductance value for continuous wave defined by the GsNReg register’s CWGsN[3:0] bits • nMod: NMOS conductance value for modulation defined by the GsNReg register’s ModGsN[3:0] bits • X = do not care. Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and GsNReg registers are used for both drivers. 12.3 RF level detector The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF collision avoidance). Furthermore the RF level detector can be used to wake up the PN512 and to generate an interrupt. Table 154. Register and bit settings controlling the signal on pin TX2 Bit Tx1RFEn Bit Force 100ASK Bit Tx2CW Bit InvTx2RFOn Bit InvTx2RFOff Envelope Pin TX2 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is switched off 1 0 00 X[1] 0 RF pMod nMod - 1 RF pCW nCW 1 X[1] 0 RF_n pMod nMod 1 RF_n pCW nCW 10 X[1] X[1] RF pCW nCW conductance always CW for the Tx2CW bit 1 X[1] X[1] RF_n pCW nCW 1 00 X[1] 0 0 pMod nMod 100 % ASK: pin TX2 pulled to logic 0 (independent of the InvTx2RFOn/In vTx2RFOff bits) 1 RF pCW nCW 1 X[1] 0 0 pMod nMod 1 RF_n pCW nCW 10 X[1] X[1] RF pCW nCW 1 X[1] X[1] RF_n pCW nCWPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 86 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register RFCfgReg. The sensitivity itself depends on the antenna configuration and tuning. Possible sensitivity levels at the RX pin are listed in the Table 154. To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp in register RFCfgReg to 1. Remark: During soft Power-down mode the RF level detector amplifier is automatically switched off to ensure that the power consumption is less than 10 A at 3 V. Remark: With typical antennas lower sensitivity levels can provoke misleading results because of intrinsic noise in the environment. Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings. 12.4 Data mode detector The Data mode detector gives the possibility to detect received signals according to the ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and convenient way for further data processing. The Data mode detector can only be activated by the AutoColl command. The mode detector resets, when no external RF field is detected by the RF level detector. The Data mode detector could be switched off during the AutoColl command by setting bit ModeDetOff in register ModeReg to 1. Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) V~Rx [Vpp] RFLevel ~2 1111 ~1.4 1110 ~0.99 1101 ~0.69 1100 ~0.49 1011 ~0.35 1010 ~0.24 1001 ~0.17 1000 ~0.12 0111 ~0.083 0110 ~0.058 0101 ~0.041 0100 ~0.029 0011 ~0.020 0010 ~0.014 0001 ~0.010 0000PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 87 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 28. Data mode detector 001aan225 HOST INTERFACES RECEIVER I/Q DEMODULATOR REGISTERS REGISTERSETTING FOR THE DETECTED MODE DATA MODE DETECTOR PN512 RX NFC @ 106 kbit/s NFC @ 212 kbit/s NFC @ 424 kbit/sPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 88 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.5 Serial data switch Two main blocks are implemented in the PN512. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above 424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional external circuit to generate transfer speeds above 424 kbit (including 106, 212 and 424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S2C interface in the card SAM mode to emulate a card functionality with the PN512 and a secure IC. A secure IC can be the SmartMX smart card controller IC. This topology allows the analog block of the PN512 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. Figure 29 shows the serial data switch for TX1 and TX2. 12.6 S2C interface support The S2C provides the possibility to directly connect a secure IC to the PN512 in order act as a contactless smart card IC via the PN512. The interfacing signals can be routed to the pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC provided by NXP Semiconductors. The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and SIGOUT pads. Figure 31 outlines possible ways of communications via the PN512 to the secure IC. Fig 29. Serial data switch for TX1 and TX2 001aak593 INTERNAL CODER INVERT IF InvMod = 1 DriverSel[1:0] 00 01 10 11 3-state to driver TX1 and TX2 0 = impedance = modulated 1 = impedance = CW 1 INVERT IF PolMFin = 0 MFIN envelopePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 89 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and performs the communication on the SIGOUT line. To enable the Secure Access module mode the clock has to be derived by the internal oscillator of the PN512, see bits SAMClockSel in register TestSel1Reg. Configured in Contactless Card mode the secure IC can act as contactless smart card IC via the PN512. In this mode the signal on the SIGOUT line is provided by the external RF field of the external reader/writer. To enable the Contactless Card mode the clock derived by the external RF field has to be used. The configuration of the S2C interface differs for the FeliCa and MIFARE scheme as outlined in the following chapters. Fig 30. Communication flows using the S2C interface 001aan226 CONTACTLESS UART SERIAL SIGNAL SWITCH FIFO AND STATE MACHINE SPI, I2C, SERIAL UART HOST CONTROLLER PN512 SECURE CORE IC SIGOUT SIGIN 2. contactless card mode 1. secure access module (SAM) mode PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 90 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.6.1 Signal shape for Felica S2C interface support The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or. To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first. The time delay for that digital filtering is in the range of one bit length. The demodulated signal changes only at a positive edge of the clock. The register TxSelReg controls the setting at SIGOUT. The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver. The modulation is done according to the register settings of the antenna drivers. The clock is switched to AUX1 or AUX2 (see AnalogSelAux). Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock output if a serial interface is used. The HIGH level at D0 is the same as PVDD. Note: The signal on the antenna is shown in principle only. In reality the waveform is sinusoidal. Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode Fig 32. Signal shape for SIGIN in SAM mode 001aan227 clock signal on SIGIN signal on antenna 001aan228 clock demodulated signal signal on SIGOUTPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 91 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode. The register TxSelReg controls the setting at SIGOUT. Note: The clock settings for the Secure Access mode and the Contactless Card mode differ, refer to the description of the bits SAMClockSel in register TestSel1Reg. The signal at SIGIN is a digital Manchester coded signal according to the requirements of the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure IC. Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode 001aan229 1 0 bit value RF signal on antenna signal on SIGOUT 01001 001aan230 0 1 0 1 1 0 0 bit value signal on antenna signal on SIGINPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 92 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.7 Hardware support for FeliCa and NFC polling 12.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot, or if required an interrupt is generated at the end of the last timeslot. 2. The receiver can be configured in a way to receive continuously. In this mode it can receive any number of packets. The receiver is ready to receive the next packet directly after the last packet has been received. This mode is active by setting the bit RxMultiple in register RxModeReg to 1 and has to be stopped by software. 3. The internal UART adds one byte to the end of every received packet, before it is transferred into the FIFO-buffer. This byte indicates if the received byte packet is correct (see register ErrReg). The first byte of each packet contains the length byte of the packet. 4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a length of 64 bytes. This means three packets can be stored in the FIFO at the same time. If more than three packets are expected, the host controller has to empty the FIFO, before the FIFO is filled completely. In case of a FIFO-overflow data is lost (See bit BufferOvfl in register ErrorReg). 12.7.2 Polling sequence functionality for target 1. The host controller has to configure the PN512 with the correct polling response parameters for the polling command. 2. To activate the automatic polling in Target mode, the AutoColl Command has to be activated. 3. The PN512 receives the polling command send out by an initiator and answers with the polling response. The timeslot is selected automatically (The timeslot itself is randomly generated, but in the range 0 to TSN, which is defined by the Polling command). The PN512 compares the system code, stored in byte 17 and 18 of the Config Command with the system code received by the polling command of an initiator. If the system code is equal, the PN512 answers according to the configured polling response. The system code FF (hex) acts as a wildcard for the system code bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex). If the system code does not match no answer is sent back by the PN512. If a valid command is received by the PN512, which is not a Polling command, no answer is sent back and the command AutoColl is stopped. The received packet is stored in the FIFO.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 93 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length. This register is six bit long. Each bit represents a length of four bytes. DataLenMax in register FelNFC2Reg defines the maximum length of the accepted package. This register is six bit long. Each bit represents a length of four bytes. If set to logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not transferred to the FIFO and receiving is kept active. Example 1: • DataLenMin = 4 – The length shall be greater or equal 16. • DataLenMax = 5 – The length shall be smaller than 20. Valid area: 16, 17, 18, 19 Example 2: • DataLenMin = 9 – The length shall be greater or equal 36. • DataLenMax = 0 – The length shall be smaller than 256. Valid area: 36 to 255 12.7.4 CRC coprocessor The following CRC coprocessor parameters can be configured: • The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting • The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1 • The CRCResultReg register indicates the result of the CRC calculation. This register is split into two 8-bit registers representing the higher and lower bytes. • The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB first. Table 156. CRC coprocessor parameters Parameter Value CRC register length 16-bit CRC CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the ModeReg register’s CRCPreset[1:0] bitsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 94 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 13. FIFO buffer An 8  64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream between the host and the PN512’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account. 13.1 Accessing the FIFO buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register. Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register. When the microcontroller starts a command, the PN512 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses. 13.2 Controlling the FIFO buffer The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer accessible allowing the FIFO buffer to be filled with another 64 bytes. 13.3 FIFO buffer status information The host can get the following FIFO buffer status information: • Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0] • FIFO buffer almost full warning: Status1Reg register’s HiAlert bit • FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit • FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit. The PN512 can generate an interrupt signal when: • ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register’s LoAlert bit changes to logic 1. • ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register’s HiAlert bit changes to logic 1. If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to Equation 3: HiAlert 64 FIFOLength =   –  WaterLevel (3)PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 95 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4: (4) 14. Interrupt request system The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 14.1 Interrupt sources overview Table 157 shows the available interrupt bits, the corresponding source and the condition for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by the timer unit which is set when the timer decrements from 1 to 0. The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by CRCReady bit = 1. The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on page 101). The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. LoAlert FIFOLength WaterLevel =  Table 157. Interrupt sources Interrupt flag Interrupt source Trigger action TimerIRq timer unit the timer counts from 1 to 0 TxIRq transmitter a transmitted data stream ends CRCIRq CRC coprocessor all data from the FIFO buffer has been processed RxIRq receiver a received data stream ends IdleIRq ComIrqReg register command execution finishes HiAlertIRq FIFO buffer the FIFO buffer is almost full LoAlertIRq FIFO buffer the FIFO buffer is almost empty ErrIRq contactless UART an error is detectedPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 96 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 15. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • Time-out counter • Watch-dog counter • Stop watch • Programmable one-shot • Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A time-out during data reception does not influence the reception process automatically). Furthermore, several timer related bits are set and these bits can be used to generate an interrupt. Timer The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer consists of two stages: 1 prescaler and 1 counter. The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between 0 and 4095 in register TModeReg and TPrescalerReg. The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the register TReloadReg. The current value of the timer is indicated by the register TCounterValReg. If the counter reaches 0 an interrupt will be generated automatically indicated by setting the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on the configuration the timer will stop at 0 or restart with the value from register TReloadReg. The status of the timer is indicated by bit TRunning in register Status1Reg. The timer can be manually started by TStartNow in register ControlReg or manually stopped by TStopNow in register ControlReg. Furthermore the timer can be activated automatically by setting the bit TAuto in the register TModeReg to fulfill dedicated protocol requirements automatically. The time delay of a timer stage is the reload value +1. The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz Maximum time: TPrescaler = 4095,TReloadVal = 65535 => (2*4095 +2)*65536/13.56 MHz = 39.59 s Example:PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 97 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution To indicate 25 us it is required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us. The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 98 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 16. Power reduction modes 16.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level. 16.2 Soft power-down mode Soft Power-down mode is entered immediately after the CommandReg register’s PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input buffers are not separated from the input pins and keep their functionality. The digital output pins do not change their state. During soft power-down, all register values, the FIFO buffer content and the configuration keep their current contents. After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited. Remark: If the internal oscillator is used, you must take into account that it is supplied by pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock cycles can be detected by the internal logic. It is recommended for the serial UART, to first send the value 55h to the PN512. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the PN512 answers to the last read command with the register content of address 0. This indicates that the PN512 is ready. 16.3 Transmitter power-down mode The Transmitter Power-down mode switches off the internal antenna drivers thereby, turning off the RF field. Transmitter power-down mode is entered by setting either the TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 99 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 17. Oscillator circuitry The clock applied to the PN512 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, special care must be taken with the clock duty cycle and clock jitter and the clock quality must be verified. 18. Reset and oscillator start-up time 18.1 Reset timing requirements The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns. 18.2 Oscillator start-up time If the PN512 has been set to a Power-down mode or is powered by a VDDX supply, the start-up time for the PN512 depends on the oscillator used and is shown in Figure 36. The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator start-up time is defined by the crystal. The time (td) is the internal delay time of the PN512 when the clock signal is stable before the PN512 can be addressed. The delay time is calculated by: (5) The time (tosc) is the sum of td and tstartup. Fig 35. Quartz crystal connection 001aan231 PN512 27.12 MHz OSCOUT OSCIN td 1024 27 s = = -------------- 37.74 sPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 100 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19. PN512 command set The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.1 General description The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.2 General behavior • Each command that needs a data bit stream (or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the Transceive command. Using this command, transmission is started with the BitFramingReg register’s StartSend bit. • Each command that needs a certain number of arguments, starts processing only when it has received the correct number of arguments from the FIFO buffer. • The FIFO buffer is not automatically cleared when commands start. This makes it possible to write command arguments and/or the data bytes to the FIFO buffer and then start the command. • Each command can be interrupted by the host writing a new command code to the CommandReg register, for example, the Idle command. Fig 36. Oscillator start-up time 001aak596 tstartup td tosc t device activation oscillator clock stable clock readyPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 101 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3 PN512 command overview 19.3.1 PN512 command descriptions 19.3.1.1 Idle Places the PN512 in Idle mode. The Idle command also terminates itself. 19.3.1.2 Config command To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for these transactions has to be stored internally. All the following data have to be written to the FIFO in this order: SENS_RES (2 bytes); in order byte 0, byte 1 NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h and the check byte is calculated automatically. SEL_RES (1 Byte) polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes system code) NFCID3 (1 byte) In total 25 bytes are transferred into an internal buffer. The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2 bytes and the one NFCID3 byte which are listed above. To read out this configuration the command Config with an empty FIFO-buffer has to be started. In this case the 25 bytes are transferred from the internal buffer to the FIFO. Table 158. Command overview Command Command code Action Idle 0000 no action, cancels current command execution Configure 0001 Configures the PN512 for FeliCa, MIFARE and NFCIP-1 communication Generate RandomID 0010 generates a 10-byte random ID number CalcCRC 0011 activates the CRC coprocessor or performs a self test Transmit 0100 transmits data from the FIFO buffer NoCmdChange 0111 no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit Receive 1000 activates the receiver circuits Transceive 1100 transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and MIFARE anticollision (Card Operation mode only) MFAuthent 1110 performs the MIFARE standard authentication as a reader SoftReset 1111 resets the PN512PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 102 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The PN512 has to be configured after each power up, before using the automatic Anticollision/Polling function (AutoColl command). During a hard power down (reset pin) this configuration remains unchanged. This command terminates automatically when finished and the active command is idle. 19.3.1.3 Generate RandomID This command generates a 10-byte random number which is initially stored in the internal buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the PN512 returns to Idle mode. 19.3.1.4 CalcCRC The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped when the FIFO buffer is empty during the data stream. The next byte written to the FIFO buffer is added to the calculation. The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The value is loaded in to the CRC coprocessor when the command starts. This command must be terminated by writing a command to the CommandReg register, such as, the Idle command. If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self Test mode. Starting the CalcCRC command initiates a digital self test. The result of the self test is written to the FIFO buffer. 19.3.1.5 Transmit The FIFO buffer content is immediately transmitted after starting this command. Before transmitting the FIFO buffer content, all relevant registers must be set for data transmission. This command automatically terminates when the FIFO buffer is empty. It can be terminated by another command written to the CommandReg register. 19.3.1.6 NoCmdChange This command does not influence any running command in the CommandReg register. It can be used to manipulate any bit except the CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit. 19.3.1.7 Receive The PN512 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command. This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 103 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3.1.8 Transceive This command continuously repeats the transmission of data from the FIFO buffer and the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream. Each transmit process must be started by setting the BitFramingReg register’s StartSend bit to logic 1. This command must be cleared by writing any command to the CommandReg register. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive command never leaves the receive state because this state cannot be cancelled automatically. 19.3.1.9 AutoColl This command automatically handles the MIFARE activation and the FeliCa polling in the Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0 for correct operation. During this command also the mode detector is active if not deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode detector detects a mode, all the mode dependent registers are set according to the received data. In case of no external RF field the command resets the internal state machine and returns to the initial state but it will not be terminated. When the command terminates the transceive command gets active. During protocol processing the IRQ bits are not supported. Only the last received frame will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the protocol. During ISO/IEC 14443A activation the enable bits are defined by the command AutoColl. The changes cannot be observed at the register TXModeReg and RXModeReg. After the Transceive command is active, the value of the register bit is relevant. The FIFO will also receive the two CRC check bytes of the last command even if they already checked and correct, if the state machine (Anticollision and Select routine) has to not been executed and 106 kbit is detected. During Felica activation the register bit is always relevant and is not overruled by the command settings. This command can be cleared by software by writing any other command to the CommandReg register, e.g. the idle command. Writing the same content again to the CommandReg register resets the state machine.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 104 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution NFCIP-1 106 kbps Passive Communication mode: The MIFARE anticollision is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit TargetActivated in the Status2Reg register is set to logic 1. NFCIP-1 212/424 kbps Passive Communication mode: The FeliCa polling command is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ. The bit TargetActivated in the Status2Reg register is set to logic 1. NFCIP-1 106/212/424 kbps Active Communication mode: This command is changing the automatically to the command Transceive. The FIFO contains the ATR REQ The bit TargetActivated in the Status2Reg register is set to logic 0. For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC is added to the FIFO. Fig 37. Autocoll Command NFCIP-1 106 kB aud ISO14443-3 NPCIP-1 > 106 kB aud FELICA IDLE MODEO MODE detection RXF raming MFHalted = 1 HALT AC nAC SELECT nSELECT HLTA AC polling, polling response next frame received next frame received REQA, WUPA READY ACTIVE WUPA SELECT SELECT READY* ACTIVE* TRANSCEIVE wait for transmit next frame received J N HLTA REQA, WUPA, AC, nAC, SELECT, nSELECT, error REQA, AC, nAC, SELECT, nSELECT, HLTA REQA, WUPA, nAC, nSELECT, HLTA, error REQA, WUPA, nAC, nSELECT, HLTA, error REQA, WUPA, AC, SELECT, nSELECT, error 00 10 AC aaa-001826PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 105 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution MIFARE (Card Operation mode): The MIFARE anticollision is finished and the command has automatically changed to transceive. The FIFO contains the first command after the Select. The bit TargetActivated in the Status2Reg register is set to logic 1. Felica (Card Operation mode): The FeliCa polling command is finished and the command has automatically changed to transceive. The FIFO contains the first command followed after the Poling by the FeliCa protocol. The bit TargetActivated in the Status2Reg register is set to logic 1. 19.3.1.10 MFAuthent This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the FIFO buffer before the command can be activated: • Authentication command code (60h, 61h) • Block address • Sector key byte 0 • Sector key byte 1 • Sector key byte 2 • Sector key byte 3 • Sector key byte 4 • Sector key byte 5 • Card serial number byte 0 • Card serial number byte 1 • Card serial number byte 2 • Card serial number byte 3 In total 12 bytes are written to the FIFO. Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set. This command automatically terminates when the MIFARE card is authenticated and the Status2Reg register’s MFCrypto1On bit is set to logic 1. This command does not terminate automatically if the card does not answer, so the timer must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the TimerIRq bit can be used as the termination criteria. During authentication processing, the RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of the MFAuthent command, either after processing the protocol or writing Idle to the CommandReg register. If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 106 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3.1.11 SoftReset This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished. Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to 9.6 kBd.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 107 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 20. Testsignals 20.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. 4. Write 00h to the FIFO. 5. Start the Selftest with the CalcCRC Command. 6. The Selftest will be performed. 7. When the Selftest is finished, the FIFO contains the following bytes: Version 1.0 has a different Selftest answer, explained in Section 21. Correct answer for VersionReg equal to 82h: 00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh, 9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h, 49h, 7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h, 21h, A9h, 86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh, 95h, 3Bh, 2Fh 20.2 Testbus The testbus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the PN512. The testbus allows to route internal signals to the digital interface. The testbus signals are selected by accessing TestBusSel in register TestSel2Reg. Table 159. Testsignal routing (TestSel2Reg = 07h) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal sdata scoll svalid sover RCV_reset RFon, filtered Envelope Table 160. Description of Testsignals Pins Testsignal Description D6 sdata shows the actual received data stream. D5 scoll shows if in the actual bit a collision has been detected (106 kbit only) D4 svalid shows if sdata and scoll are valid D3 sover shows that the receiver has detected a stop condition (ISO/IEC 14443A/ MIFARE mode only). D2 RCV_reset shows if the receiver is reset D1 RFon, filtered shows the value of the internal RF level detector D0 Envelope shows the output of the internal coderPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 108 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 20.3 Testsignals at pin AUX Table 161. Testsignal routing (TestSel2Reg = 0Dh) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf Table 162. Description of Testsignals Pins Testsignal Description D6 clkstable shows if the oscillator delivers a stable signal. D5 clk27/8 shows the output signal of the oscillator divided by 8 D4 clk27rf/8 shows the clk27rf signal divided by 8 D3 clkrf13/4 shows the clk13rf divided by 4. D2 clk27 shows the output signal of the oscillator D1 clk27rf shows the RF clock multiplied by 2. D0 clk13rf shows the RF clock of 13.56 MHz Table 163. Testsignal routing (TestSel2Reg = 19h) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal - TRunning - - - - - Table 164. Description of Testsignals Pins Testsignal Description D6 - - D5 TRunning TRunning stops 1 clockcycle after TimerIRQ is raised D4 - - D3 - - D2 - - D1 - - D0 - - Table 165. Testsignals description SelAux Description for Aux1 / Aux2 0000 Tristate 0001 DAC: register TestDAC 1/2 0010 DAC: testsignal corr1 0011 DAC: testsignal corr2 0100 DAC: testsignal MinLevel 0101 DAC: ADC_I 0110 DAC: ADC_Q 0111 DAC: testsignal ADC_I combined with ADC_Q 1000 Testsignal for production test 1001 SAM clock 1010 High 1011 low 1100 TxActivePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 109 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Note: The DAC has a current output, it is recommended to use a 1 k pull-down resistance at pins AUX1/AUX2. 20.4 PRBS Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the transmission of the defined datastream the command send has to be activated. The preamble/Sync byte/start bit/parity bit are generated automatically depending on the selected mode. Note: All relevant register to transmit data have to be configured before entering PRBS mode according ITU-TO150. 21. Errata sheet This data sheet is describing the functionality for version 2.0 and the industrial version. This chapter lists all differences from version 1.0 to version 2.0: The value of the version in Section 9.2.4.8 is set to80h. The behaviour ‘RFU’ for the register is undefined. The answer to the Selftest (see Section 20.1) for version 1.0 (VersionReg equal to 80h): 00h, AAh, E3h, 29h, 0Ch, 10h, 29zhh, 6Bh, 76h, 8Dh, AFh, 4Bh, A2h, DAh, 76h, 99h C7h, 5Eh, 24h, 69h, D2h, BAh, FAh, BCh 3Eh, DAh, 96h, B5h, F5h, 94h, B0h, 3Ah 4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh 38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh 4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh 38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh FBh, F4h, 19h, 94h, 82h, 5Ah, 72h, 9Dh BAh, 0Dh, 1Fh, 17h, 56h, 22h, B9h, 08h Only the default setting for the prescaler (see Section 15 “Timer unit” on page 96): t = ((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula fTimer = 13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in Table 100 “Description of TModeReg bits” on page 57 and TPrescalerLo in Table 101 “TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b” on page 58. As there is no option for the prescaler available, also the TPrescalEven is not available Section 9.2.2.10 on page 45. This bit is set to ‘RFU’. 1101 RxActive 1110 Subcarrier detected 1111 TstBusBit Table 165. Testsignals description SelAux Description for Aux1 / Aux2PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 110 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Especially when using time slot protocols, it is needed that the error flag is copied into the status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4 on page 39) within version 1.0 the protocol error flag is not included in the status information for the frame. In addition the CRCOk is copied instead of the CRCErr. This can be a problem in frames without length information e.g. ISO/IEC 14443-B. The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits, as such the configuration within Section 9.2.2.15 “TypeBReg” on page 50 bit 4 for RxEOFReq does not exist. In addition the IC only has the possibility to select the minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section 9.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only setting minimum and maximum length according ISO/IEC 14443-B, see Section 9.2.2.15 “TypeBReg” on page 50, bit 4. 22. Application design-in information The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN512. The antenna tuning and RF part matching is described in the application note “NFC Transmission Module Antenna and RF Design Guide”. Fig 38. Typical circuit diagram AVDD TVDD RX VMID supply TX1 TVSS TX2 DVSS DVDD DVDD PVDD SVDD AVSS IRQ NRSTPD R1 R2 L0 C0 C0 C2 C1 CRX RQ C1 RQ C2 L0 Cvmid 001aan232 27.12 MHz OSCIN OSCOUT HOST CONTROLLER interface PN512 antenna LantPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 111 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 23. Limiting values 24. Recommended operating conditions Table 166. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDA analog supply voltage 0.5 +4.0 V VDDD digital supply voltage 0.5 +4.0 V VDD(PVDD) PVDD supply voltage 0.5 +4.0 V VDD(TVDD) TVDD supply voltage 0.5 +4.0 V VDD(SVDD) SVDD supply voltage 0.5 +4.0 V VI input voltage all input pins except pins SIGIN and RX VSS(PVSS)  0.5 VDD(PVDD) + 0.5 V pin MFIN VSS(PVSS)  0.5 VDD(SVDD) + 0.5 V Ptot total power dissipation per package; and VDDD in shortcut mode - 200 mW Tj junction temperature - 125 C VESD electrostatic discharge voltage HBM; 1500 , 100 pF; JESD22-A114-B - 2000 V MM; 0.75 H, 200 pF; JESD22-A114-A - 200 V Charged device model; JESD22-C101-A on all pins - 200 V on all pins except SVDD in TFBGA64 package - 500 V Industrial version: VESD electrostatic discharge voltage HBM; 1500 , 100 pF; JESD22-A114-B - 2000 V MM; 0.75 H, 200 pF; JESD22-A114-A - 200 V Charged device model; AEC-Q100-011 on all pins - 200 V on all pins except SVDD - 500 V Table 167. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V [1][2] 2.5 - 3.6 V VDDD digital supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V [1][2] 2.5 - 3.6 V VDD(TVDD) TVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V [1][2] 2.5 - 3.6 VPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 112 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] Supply voltages below 3 V reduce the performance (the achievable operating distance). [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. 25. Thermal characteristics 26. Characteristics VDD(PVDD) PVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V [3] 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V 1.6 - 3.6 V Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 - +85 C Industrial version: Tamb ambient temperature HVQFN32 40 - +90 C Table 167. Operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit Table 168. Thermal characteristics Symbol Parameter Conditions Package Typ Unit Rthj-a Thermal resistance from junction to ambient In still air with exposed pad soldered on a 4 layer Jedec PCB In still air HVQFN32 40 K/W HVQFN40 35 K/W TFBGA64 K/W Table 169. Characteristics Symbol Parameter Conditions Min Typ Max Unit Input characteristics Pins A0, A1 and NRSTPD ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD) -- V VIL LOW-level input voltage - - 0.3VDD(PVDD) V Pin SIGIN ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(SVDD) -- V VIL LOW-level input voltage - - 0.3VDD(SVDD) V Pin ALE ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD) -- V VIL LOW-level input voltage - - 0.3VDD(PVDD) V Pin RX[1] Vi input voltage 1 -VDDA +1 V Ci input capacitance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.5 V (DC) offset - 10- pFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 113 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Ri input resistance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.5 V (DC) offset - 350 -  Input voltage range; see Figure 39 Vi(p-p)(min) minimum peak-to-peak input voltage Manchester encoded; VDDA =3V - 100 - mV Vi(p-p)(max) maximum peak-to-peak input voltage Manchester encoded; VDDA =3V - 4- V Input sensitivity; see Figure 39 Vmod modulation voltage minimum Manchester encoded; VDDA = 3 V; RxGain[2:0] = 111b (48 dB) - 5 - mV Pin OSCIN ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDDA -- V VIL LOW-level input voltage - - 0.3VDDA V Ci input capacitance VDDA = 2.8 V; DC = 0.65 V; AC = 1 V (p-p) - 2 - pF Input/output characteristics pins D1, D2, D3, D4, D5, D6 and D7 ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD) -- V VIL LOW-level input voltage - - 0.3VDD(PVDD) V VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)  0.4 - VDD(PVDD) V VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOH HIGH-level output current VDD(PVDD) =3V - - 4 mA IOL LOW-level output current VDD(PVDD) =3V - - 4 mA Output characteristics Pin SIGOUT VOH HIGH-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VDD(SVDD)  0.4 - VDD(SVDD) V VOL LOW-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDD(SVDD) =3V - - 4 mA IOH HIGH-level output current VDD(SVDD) =3V - - 4 mA Pin IRQ VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)  0.4 - VDD(PVDD) V VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDD(PVDD) =3V - - 4 mA IOH HIGH-level output current VDD(PVDD) =3V - - 4 mA Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 114 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Pins AUX1 and AUX2 VOH HIGH-level output voltage VDDD = 3 V; IO = 4 mA VDDD  0.4 - VDDD V VOL LOW-level output voltage VDDD = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDDD =3V - - 4 mA IOH HIGH-level output current VDDD =3V - - 4 mA Pins TX1 and TX2 VOL LOW-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh - - 0.15 V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh - - 0.4 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh - - 0.24 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh - - 0.64 V VOH HIGH-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.15 -- V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.4 -- V VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.24 -- V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.64 -- V Industrial version: VOL LOW-level output voltage VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh - - 0.18 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh - -0.44 V VOH HIGH-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.18 -- V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.44 -- V Output resistance for TX1/TX2, Industrial Version: ROP,01H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 01h 123 180 261  Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 115 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution ROP,02H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 02h 61 90 131  ROP,04H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 04h 30 46 68  ROP,08H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 08h 15 23 35  ROP,10H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 10h 7.5 12 19  ROP,20H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 20h 4.2 6 9  ROP,3FH High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 3Fh 2 35  RON,10H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 10h 30 46 68  RON,20H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 20h 15 23 35  RON,40H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 40h 7.5 12 19  RON,80H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 80h 4.2 6 9  RON,F0H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = F0h 2 35  Current consumption Ipd power-down current VDDA = VDDD = VDD(TVDD) = VDD(PVDD) =3V hard power-down; pin NRSTPD set LOW [2] - -5 A soft power-down; RF level detector on [2] - -10 A IDD(PVDD) PVDD supply current pin PVDD [3] - -40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [4][5][6] - 60 100 mA IDD(SVDD) SVDD supply current pin SVDD [7] - -4 mA IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register’s RcvOff bit = 1 - 3 5 mA Industrial version: IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9,5 mA Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 116 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD. [2] Ipd is the total current for all supplies. [3] IDD(PVDD) depends on the overall load at the digital pins. [4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [5] During typical circuit operation, the overall current is below 100 mA. [6] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz. [7] IDD(SVDD) depends on the load at pin MFOUT. Ipd power-down current VDDA = VDDD = VDD(TVDD) = VDD(PVDD) =3V hard power-down; pin NRSTPD set LOW [2] - -15 A soft power-down; RF level detector on [2] - -30 A Clock frequency fclk clock frequency - 27.12 - MHz clk clock duty cycle 40 50 60 % tjit jitter time RMS - - 10 ps Crystal oscillator VOH HIGH-level output voltage pin OSCOUT - 1.1 - V VOL LOW-level output voltage pin OSCOUT - 0.2 - V Ci input capacitance pin OSCOUT - 2 - pF pin OSCIN - 2 - pF Typical input requirements fxtal crystal frequency - 27.12 - MHz ESR equivalent series resistance - - 100  CL load capacitance - 10 - pF Pxtal crystal power dissipation - 50 100 W Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 117 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 26.1 Timing characteristics Fig 39. Pin RX input voltage range 001aak012 VMID 0 V Vmod Vi(p-p)(max) Vi(p-p)(min) 13.56 MHz carrier Table 170. SPI timing characteristics Symbol Parameter Conditions Min Typ Max Unit tWL pulse width LOW line SCK 50 - - ns tWH pulse width HIGH line SCK 50 - - ns th(SCKH-D) SCK HIGH to data input hold time SCK to changing MOSI 25 - - ns tsu(D-SCKH) data input to SCK HIGH set-up time changing MOSI to SCK 25 - - ns th(SCKL-Q) SCK LOW to data output hold time SCK to changing MISO - - 25 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns Table 171. I2C-bus timing in Fast mode Symbol Parameter Conditions Fast mode High-speed mode Unit Min Max Min Max fSCL SCL clock frequency 0 400 0 3400 kHz tHD;STA hold time (repeated) START condition after this period, the first clock pulse is generated 600 - 160 - ns tSU;STA set-up time for a repeated START condition 600 - 160 - ns tSU;STO set-up time for STOP condition 600 - 160 - ns tLOW LOW period of the SCL clock 1300 - 160 - ns tHIGH HIGH period of the SCL clock 600 - 60 - ns tHD;DAT data hold time 0 900 0 70 nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 118 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution tSU;DAT data set-up time 100 - 10 - ns tr rise time SCL signal 20 300 10 40 ns tf fall time SCL signal 20 300 10 40 ns tr rise time SDA and SCL signals 20 300 10 80 ns tf fall time SDA and SCL signals 20 300 10 80 ns tBUF bus free time between a STOP and START condition 1.3 - 1.3 - s Remark: The signal NSS must be LOW to be able to send several bytes in one data stream. To send more than one data stream NSS must be set HIGH between the data streams. Fig 40. Timing diagram for SPI Fig 41. Timing for Fast and Standard mode devices on the I2C-bus Table 171. I2C-bus timing in Fast mode …continued Symbol Parameter Conditions Fast mode High-speed mode Unit Min Max Min Max 001aaj634 tSCKL tSCKH tSCKL tDXSH tSHDX tDXSH tSLDX tSLNH MOSI SCK MISO MSB MSB LSB LSB NSS 001aaj635 SDA tf SCL tLOW tf tSP tr tHD;STA tHD;DAT tHD;STA tr tHIGH tSU;DAT S Sr P S tSU;STA tSU;STO tBUFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 119 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 26.2 8-bit parallel interface timing 26.2.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Example: tAVLL = time for address valid to ALE low 26.2.2 AC operating specification 26.2.2.1 Bus timing for separated Read/Write strobe Table 172. AC symbols Designation Signal Designation Logic Level A address H HIGH D data L LOW W NWR or nWait Z high impedance R NRD or R/NW or nWrite X any level or data L ALE or AS V any valid signal or data C NCS N NSS S NDS or nDStrb and nAStrb, SCK Table 173. Timing specification for separated Read/Write strobe Symbol Parameter Min Max Unit tLHLL ALE pulse width 10 - ns tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 5 - ns tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 5 - ns tLLWL ALE low to NWR, NRD low 10 - ns tCLWL NCS low to NRD, NWR low 0 - ns tWHCH NRD, NWR high to NCS high 0 - ns tRLDV NRD low to DATA valid - 35 ns tRHDZ NRD high to DATA high impedance - 10 ns tDVWH DATA valid to NWR high 5 - ns tWHDX DATA hold after NWR high (Data Hold Time) 5 - ns tWLWH NRD, NWR pulse width 40 - ns tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 - ns tWHAX Separated Address Bus valid after NWR high (Hold Time) 5 - ns tWHWL period between sequenced read/write accesses 40 - nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 120 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A3 have to be connected as described in chapter Automatic host controller Interface Type Detection. 26.2.2.2 Bus timing for common Read/Write strobe Fig 42. Timing diagram for separated Read/Write strobe 001aan233 tLHLL tCLWL tLLWL tWHWL tWLWH tWHWL tWHDX tRHDZ tWLDV tRLDV tWHCH tWHAX tAVLL tLLAX tAVWL ALE NCS NWR NRD D0...D7 D0...D7 A0...A3 multiplexed addressbus A0...A3 SEPARATED ADDRESSBUS A0...A3 Table 174. Timing specification for common Read/Write strobe Symbol Parameter Min Max Unit tLHLL AS pulse width 10 - ns tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 5 - ns tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 5 - ns tLLSL AS low to NDS low 10 - ns tCLSL NCS low to NDS low 0 - ns tSHCH NDS high to NCS high 0 - ns tSLDV,R NDS low to DATA valid (for read cycle) - 35 ns tSHDZ NDS low to DATA high impedance (read cycle) - 10 ns tDVSH DATA valid to NDS high (for write cycle) 5 - ns tSHDX DATA hold after NDS high (write cycle, Hold Time) 5 - ns tSHRX R/NW hold after NDS high 5 - ns tSLSH NDS pulse width 40 - ns tAVSL Separated Address Bus valid to NDS low (Hold Time) 30 - ns tSHAX Separated Address Bus valid after NDS high (Set Up Time) 5 - nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 121 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A3 have to be connected as described in Automatic -Controller Interface Type Detection. Fig 43. Timing diagram for common Read/Write strobe SEPARATED ADDRESSBUS A0...A3 multiplexed addressbus A0...A3 ALE tLHLL tCLSL R/NW NDS D0...D7 D0...D7 A0...A3 NCS tSHCH tSHRX tRVSL tLLSL tSLSH tSHSL tAVLL tLLAX tSLDV, R tSLDV, W tSHDX tSHDZ tSHAX tAVSL tSHSL 001aan234PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 122 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 27. Package information The PN512 can be delivered in 3 different packages. Table 175. Package information Package Remarks HVQFN32 8-bit parallel interface not supported HVQFN40 Supports the 8-bit parallel interface TFBGA64 Ball grid array facilitating development of an PCI compliant devicePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 123 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 28. Package outline Fig 44. Package outline package version (HVQFN32) 1 0.5 UNIT A1 b Eh e y 0.2 c OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 5.1 4.9 Dh 3.25 2.95 y1 5.1 4.9 3.25 2.95 e1 3.5 e2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT617-1 MO-220 - - - - - - 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT617-1 HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A(1) max. A A1 c detail X y y e 1 C L Eh Dh e e1 b 9 16 32 25 24 17 8 1 X D E C B A e2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e AC C v M B w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1)PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 124 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 45. Package outline package version (HVQFN40) Outline References version European projection Issue date IEC JEDEC JEITA SOT618-1 MO-220 sot618-1_po 02-10-22 13-11-05 Unit mm max nom min 1.00 0.05 0.2 6.1 4.25 6.1 0.4 A(1) Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 A1 b 0.30 c D(1) Dh E(1) Eh 4.10 e e1 e2 Lvw 0.05 y 0.05 y1 0.1 0.85 0.02 6.0 4.10 6.0 0.21 0.80 0.00 0.18 5.9 3.95 5.9 3.95 0.3 4.25 0.5 4.5 0.5 4.5 0.1 e e 1/2 e 1/2 e y terminal 1 index area A A1 c L Eh Dh b 11 20 40 31 30 21 10 1 D E terminal 1 index area 0 2.5 5 mm scale e1 AC C v B w y1 C C e2 X detail X B APN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 125 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 46. Package outline package version (TFBGA64) Outline References version European projection Issue date IEC JEDEC JEITA SOT1336-1 - - - sot1336-1_po 12-06-19 12-08-28 Unit mm max nom min 1.15 0.35 0.45 5.6 5.6 4.55 0.15 0.1 A Dimensions (mm are the original dimensions) TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls A1 A2 0.80 1.00 0.30 0.40 5.5 5.5 0.65 0.70 b DE ee1 4.55 0.90 0.25 0.35 5.4 5.4 0.65 e2 v w 0.08 y y1 0.1 SOT1336-1 C y1 C y 0 5 mm scale X A A2 A1 detail X ball A1 index area ball A1 index area A E D B e2 e A B C D E F G H 1 3 5 78 246 e1 e Ø v AC B Ø w C b 1/2 e 1/2 ePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 126 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 29. Abbreviations 30. Glossary Modulation index — Defined as the voltage ratio (Vmax  Vmin) / (Vmax + Vmin). Load modulation index — Defined as the voltage ratio for the card (Vmax  Vmin) / (Vmax + Vmin) measured at the card’s coil. Initiator — Generates RF field at 13.56 MHz and starts the NFCIP-1 communication. Target — Responds to command either using load modulation scheme (RF field generated by Initiator) or using modulation of self generated RF field (no RF field generated by initiator). 31. References [1] Application note — NFC Transmission Module Antenna and RF Design Guide Table 176. Abbreviations Acronym Description ADC Analog-to-Digital Converter ASK Amplitude Shift keying BPSK Binary Phase Shift Keying CRC Cyclic Redundancy Check CW Continuous Wave DAC Digital-to-Analog Converter EOF End of frame HBM Human Body Model I 2C Inter-integrated Circuit LSB Least Significant Bit MISO Master In Slave Out MM Machine Model MOSI Master Out Slave In MSB Most Significant Bit NSS Not Slave Select PCB Printed-Circuit Board PLL Phase-Locked Loop PRBS Pseudo-Random Bit Sequence RX Receiver SOF Start Of Frame SPI Serial Peripheral Interface TX Transmitter UART Universal Asynchronous Receiver TransmitterPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 127 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 32. Revision history Table 177. Revision history Document ID Release date Data sheet status Change notice Supersedes PN512 v.4.5 20131217 Product data sheet - PN512 v.4.4 Modifications: • Typo corrected PN512 v.4.4 20130730 Product data sheet - PN512 v.4.3 Modifications: • Value added in Table 166 “Limiting values” • Change of descriptive title PN512 v.4.3 20130507 Product data sheet - PN512 v.4.2 Modifications: • New type PN5120A0ET/C2 added • Table 72 “Description of MifNFCReg bits”: description of TxWait updated • Table 153 “Register and bit settings controlling the signal on pin TX1” and Table 153 “Register and bit settings controlling the signal on pin TX1”: updated • Table 166 “Limiting values”: VESD values added PN512 v.4.2 20120828 Product data sheet - PN512 v.4.1 Modifications: • Table 123 “AutoTestReg register (address 36h); reset value: 40h, 01000000b”: description of bits 4 and 5 corrected PN512 v.4.1 20120821 Product data sheet - PN512 v.4.0 Modifications: • Table 124 “Description of bits”: description of bits 4 and 5 corrected PN512 v.4.0 20120712 Product data sheet - PN512 v.3.9 Modifications: • Section 33.4 “Licenses”: updated PN512 v.3.9 20120201 Product data sheet - PN512 v.3.8 Modifications: • Adding information on the different version in General description. • Adding Section 21 “Errata sheet” on page 109 for explanation of differences between 1.0 and 2.0. • Adding ordering information for version 1.0 and industrial version in Table 2 “Ordering information” on page 5 • Adding the limitations and characteristics for the industrial version, see Table 1 “Quick reference data” on page 4, Table 166 “Limiting values” on page 111, Table 1 “Quick reference data” on page 4 • Referring to the Section 21 “Errata sheet” on page 109 within the following sections: Section 9.2.2.4 “RxModeReg” on page 39, Section 9.2.2.10 “DemodReg” on page 45, Section 9.2.2.15 “TypeBReg” on page 50, Section 9.2.3.10 “TMode Register, TPrescaler Register” on page 57, Section 9.2.4.7 “AutoTestReg” on page 64, Section 9.2.4.8 “VersionReg” on page 64, Section 9.1.1 “Register bit behavior” on page 23, Section 15 “Timer unit” on page 96, Section 20 “Testsignals” on page 107; • Update of command ‘Mem’ to ‘Configure’ and ‘RFU’ to ‘Autocoll’ in Table 158 “Command overview” on page 101. • Change of ‘Mem’ to ‘Configure’ in ‘Mem’ in Section 19.3.1.2 “Config command” on page 101 • Adding Autocoll in Section 19.3.1.9 “AutoColl” on page 103 PN512 v.3.8 20111025 Product data sheet - PN512 v.3.7 Modifications: • Table 168 “Characteristics”: unit of Pxtal corrected 111310 June 2005 Objective data sheet - Modifications: • Initial versionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 128 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 33. Legal information 33.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 33.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 129 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 33.4 Licenses 33.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I 2C-bus — logo is a trademark of NXP B.V. MIFARE — is a trademark of NXP B.V. 34. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron Technology Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 130 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 35. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5 Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . .10 Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . 11 Table 5. Pin description TFBGA64 . . . . . . . . . . . . . . . . .12 Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer . . . . .14 Table 7. Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 8. FeliCa framing and coding . . . . . . . . . . . . . . . .16 Table 9. Start value for the CRC Polynomial: (00h), (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 10. Communication overview for Active communication mode . . . . . . . . . . . . . . . . . . . .18 Table 11. Communication overview for Passive communication mode . . . . . . . . . . . . . . . . . . . .19 Table 12. Framing and coding overview. . . . . . . . . . . . . .20 Table 13. MIFARE Card operation mode . . . . . . . . . . . . .20 Table 14. FeliCa Card operation mode . . . . . . . . . . . . . .21 Table 15. PN512 registers overview . . . . . . . . . . . . . . . .21 Table 16. Behavior of register bits and its designation. . .23 Table 17. PageReg register (address 00h); reset value: 00h, 0000000b . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 18. Description of PageReg bits . . . . . . . . . . . . . . .24 Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .24 Table 20. Description of CommandReg bits. . . . . . . . . . .24 Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . .25 Table 22. Description of CommIEnReg bits . . . . . . . . . . .25 Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .26 Table 24. Description of DivIEnReg bits. . . . . . . . . . . . . .26 Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b . . . . . . . . . . . . . . . . . . .27 Table 26. Description of CommIRqReg bits . . . . . . . . . . .27 Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb . . . . . . . . . . . . . . . . . .28 Table 28. Description of DivIRqReg bits . . . . . . . . . . . . .28 Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .29 Table 30. Description of ErrorReg bits . . . . . . . . . . . . . . .29 Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb . . . . . . . . . . . . . . . . . .30 Table 32. Description of Status1Reg bits . . . . . . . . . . . . .30 Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .31 Table 34. Description of Status2Reg bits . . . . . . . . . . . . .31 Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . .32 Table 36. Description of FIFODataReg bits . . . . . . . . . . .32 Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .32 Table 38. Description of FIFOLevelReg bits. . . . . . . . . . .32 Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .33 Table 40. Description of WaterLevelReg bits. . . . . . . . . . 33 Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 33 Table 42. Description of ControlReg bits . . . . . . . . . . . . 33 Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 34 Table 44. Description of BitFramingReg bits . . . . . . . . . . 34 Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb . . . . . . . . . . . . . . . . . 35 Table 46. Description of CollReg bits. . . . . . . . . . . . . . . . 35 Table 47. PageReg register (address 10h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 36 Table 48. Description of PageReg bits . . . . . . . . . . . . . . 36 Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 50. Description of ModeReg bits . . . . . . . . . . . . . . 37 Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 38 Table 52. Description of TxModeReg bits . . . . . . . . . . . . 38 Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 39 Table 54. Description of RxModeReg bits . . . . . . . . . . . . 39 Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 40 Table 56. Description of TxControlReg bits . . . . . . . . . . . 40 Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 41 Table 58. Description of TxAutoReg bits . . . . . . . . . . . . . 41 Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b. . . . . . . . . . . . . . . . . . . . . . . . 42 Table 60. Description of TxSelReg bits . . . . . . . . . . . . . . 42 Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b. . . . . . . . . . . . . . . . . . . . . . . . 44 Table 62. Description of RxSelReg bits . . . . . . . . . . . . . . 44 Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b . . . . . . . . . . . . . . 44 Table 64. Description of RxThresholdReg bits . . . . . . . . 44 Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b . . . . . . . . . . . . . . . . . . 45 Table 66. Description of DemodReg bits . . . . . . . . . . . . . 45 Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 46 Table 68. Description of FelNFC1Reg bits . . . . . . . . . . . 46 Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 47 Table 70. Description of FelNFC2Reg bits . . . . . . . . . . . 47 Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b. . . . . . . . . . . . . . . . . . . 48 Table 72. Description of MifNFCReg bits. . . . . . . . . . . . . 48 Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b . . . . . . . . . . . . . . 49 Table 74. Description of ManualRCVReg bits . . . . . . . . . 49 Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 50 Table 76. Description of TypeBReg bits. . . . . . . . . . . . . . 50 Table 77. SerialSpeedReg register (address 1Fh); PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 131 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution reset value: EBh, 11101011b . . . . . . . . . . . . . .51 Table 78. Description of SerialSpeedReg bits . . . . . . . . .51 Table 79. PageReg register (address 20h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .52 Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52 Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 82. Description of CRCResultReg bits . . . . . . . . . .52 Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 84. Description of CRCResultReg bits . . . . . . . . . .52 Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .53 Table 86. Description of GsNOffReg bits . . . . . . . . . . . . .53 Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b . . . . . . . . . . . . . . . . . . .54 Table 88. Description of ModWidthReg bits . . . . . . . . . . .54 Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .54 Table 90. Description of TxBitPhaseReg bits . . . . . . . . . .54 Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b . . . . . . . . . . . . . . . . . . .55 Table 92. Description of RFCfgReg bits . . . . . . . . . . . . .55 Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .56 Table 94. Description of GsNOnReg bits . . . . . . . . . . . . .56 Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .56 Table 96. Description of CWGsPReg bits. . . . . . . . . . . . .56 Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .57 Table 98. Description of ModGsPReg bits . . . . . . . . . . . .57 Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .57 Table 100. Description of TModeReg bits . . . . . . . . . . . . .57 Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .58 Table 102. Description of TPrescalerReg bits . . . . . . . . . .58 Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b . . . . . . . . .59 Table 104. Description of the higher TReloadReg bits . . .59 Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b . . . . . . . . .59 Table 106. Description of lower TReloadReg bits . . . . . . .59 Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb . . . . . . .60 Table 108. Description of the higher TCounterValReg bits 60 Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .60 Table 110. Description of lower TCounterValReg bits . . . .60 Table 111. PageReg register (address 30h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .60 Table 112. Description of PageReg bits. . . . . . . . . . . . . . .61 Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62 Table 114. Description of TestSel1Reg bits . . . . . . . . . . . .62 Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62 Table 116. Description of TestSel2Reg bits. . . . . . . . . . . . 62 Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 63 Table 118. Description of TestPinEnReg bits . . . . . . . . . . 63 Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 63 Table 120. Description of TestPinValueReg bits . . . . . . . . 63 Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 64 Table 122. Description of TestBusReg bits . . . . . . . . . . . . 64 Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b . . . . . . . . . . . . . . . . . . 64 Table 124. Description of bits . . . . . . . . . . . . . . . . . . . . . . 64 Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 65 Table 126. Description of VersionReg bits . . . . . . . . . . . . 65 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 66 Table 128. Description of AnalogTestReg bits . . . . . . . . . 66 Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67 Table 130. Description of TestDAC1Reg bits . . . . . . . . . . 67 Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67 Table 132. Description ofTestDAC2Reg bits. . . . . . . . . . . 67 Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 67 Table 134. Description of TestADCReg bits . . . . . . . . . . . 67 Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 136. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 68 Table 138. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 140. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 141. Connection protocol for detecting different interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 142. Connection scheme for detecting the different interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 70 Table 144. MOSI and MISO byte order . . . . . . . . . . . . . . 71 Table 145. Address byte 0 register; address MOSI . . . . . 71 Table 146. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 72 Table 147. Selectable UART transfer speeds . . . . . . . . . 72 Table 148. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 149. Read data byte order . . . . . . . . . . . . . . . . . . . 73 Table 150. Write data byte order . . . . . . . . . . . . . . . . . . . 73 Table 151. Address byte 0 register; address MOSI . . . . . 75 Table 152. Supported interface types . . . . . . . . . . . . . . . . 82 Table 153. Register and bit settings controlling the signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . 84 Table 154. Register and bit settings controlling the signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . 85 Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) . . . 86 Table 156. CRC coprocessor parameters . . . . . . . . . . . . 93PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 132 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .95 Table 158. Command overview . . . . . . . . . . . . . . . . . . .101 Table 159. Testsignal routing (TestSel2Reg = 07h) . . . . .107 Table 160. Description of Testsignals . . . . . . . . . . . . . . .107 Table 161. Testsignal routing (TestSel2Reg = 0Dh) . . . .108 Table 162. Description of Testsignals . . . . . . . . . . . . . . .108 Table 163. Testsignal routing (TestSel2Reg = 19h) . . . . .108 Table 164. Description of Testsignals . . . . . . . . . . . . . . .108 Table 165. Testsignals description. . . . . . . . . . . . . . . . . .108 Table 166. Limiting values . . . . . . . . . . . . . . . . . . . . . . . 111 Table 167. Operating conditions . . . . . . . . . . . . . . . . . . . 111 Table 168. Thermal characteristics . . . . . . . . . . . . . . . . . 112 Table 169. Characteristics . . . . . . . . . . . . . . . . . . . . . . . 112 Table 170. SPI timing characteristics . . . . . . . . . . . . . . . 117 Table 171. I2C-bus timing in Fast mode . . . . . . . . . . . . . 117 Table 172. AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 173. Timing specification for separated Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . 119 Table 174. Timing specification for common Read/Write strobe. . . . . . . . . . . . . . . . . . . . . .120 Table 175. Package information . . . . . . . . . . . . . . . . . . .122 Table 176. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .126 Table 177. Revision history . . . . . . . . . . . . . . . . . . . . . . .127PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 133 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 36. Figures Fig 1. Simplified block diagram of the PN512 . . . . . . . . .6 Fig 2. Detailed block diagram of the PN512 . . . . . . . . . .7 Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .8 Fig 4. Pinning configuration HVQFN40 (SOT618-1) . . . .8 Fig 5. Pin configuration TFBGA64 (SOT1336-1) . . . . . . .9 Fig 6. PN512 Read/Write mode. . . . . . . . . . . . . . . . . . .14 Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram. . . . . . . . . . . . . . . . . . . .14 Fig 8. Data coding and framing according to ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . .15 Fig 9. FeliCa reader/writer communication diagram . . .16 Fig 10. NFCIP-1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . .17 Fig 11. Active communication mode . . . . . . . . . . . . . . . .18 Fig 12. Passive communication mode . . . . . . . . . . . . . . .19 Fig 13. SPI connection to host. . . . . . . . . . . . . . . . . . . . .70 Fig 14. UART connection to microcontrollers . . . . . . . . .71 Fig 15. UART read data timing diagram . . . . . . . . . . . . .73 Fig 16. UART write data timing diagram . . . . . . . . . . . . .74 Fig 17. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .75 Fig 18. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .76 Fig 19. START and STOP conditions . . . . . . . . . . . . . . .76 Fig 20. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .77 Fig 21. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .77 Fig 22. First byte following the START procedure . . . . . .78 Fig 23. Register read and write access . . . . . . . . . . . . . .79 Fig 24. I2C-bus HS mode protocol switch . . . . . . . . . . . .80 Fig 25. I2C-bus HS mode protocol frame. . . . . . . . . . . . .81 Fig 26. Connection to host controller with separated Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83 Fig 27. Connection to host controller with common Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83 Fig 28. Data mode detector . . . . . . . . . . . . . . . . . . . . . . .87 Fig 29. Serial data switch for TX1 and TX2 . . . . . . . . . . .88 Fig 30. Communication flows using the S2C interface. . .89 Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Fig 32. Signal shape for SIGIN in SAM mode . . . . . . . . .90 Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 35. Quartz crystal connection . . . . . . . . . . . . . . . . . .99 Fig 36. Oscillator start-up time. . . . . . . . . . . . . . . . . . . .100 Fig 37. Autocoll Command . . . . . . . . . . . . . . . . . . . . . .104 Fig 38. Typical circuit diagram . . . . . . . . . . . . . . . . . . . . 110 Fig 39. Pin RX input voltage range . . . . . . . . . . . . . . . . 116 Fig 40. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . 118 Fig 41. Timing for Fast and Standard mode devices on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Fig 42. Timing diagram for separated Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Fig 43. Timing diagram for common Read/Write strobe 121 Fig 44. Package outline package version (HVQFN32) .123 Fig 45. Package outline package version (HVQFN40) .124 Fig 46. Package outline package version (TFBGA64). .125PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 134 of 136 continued >> NXP Semiconductors PN512 Full NFC Forum compliant solution 37. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Different available versions. . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information. . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 14 8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . 14 8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . 15 8.3 FeliCa reader/writer functionality . . . . . . . . . . 16 8.3.1 FeliCa framing and coding . . . . . . . . . . . . . . . 16 8.4 NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4.1 Active communication mode . . . . . . . . . . . . . 18 8.4.2 Passive communication mode . . . . . . . . . . . . 19 8.4.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 20 8.4.4 NFCIP-1 protocol support. . . . . . . . . . . . . . . . 20 8.4.5 MIFARE Card operation mode . . . . . . . . . . . . 20 8.4.6 FeliCa Card operation mode . . . . . . . . . . . . . 21 9 PN512 register SET . . . . . . . . . . . . . . . . . . . . . 21 9.1 PN512 registers overview. . . . . . . . . . . . . . . . 21 9.1.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . 23 9.2 Register description . . . . . . . . . . . . . . . . . . . . 24 9.2.1 Page 0: Command and status . . . . . . . . . . . . 24 9.2.1.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1.2 CommandReg . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1.3 CommIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.1.4 DivIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.2.1.5 CommIRqReg. . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.1.6 DivIRqReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.1.7 ErrorReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.1.8 Status1Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.1.9 Status2Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.1.10 FIFODataReg . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1.11 FIFOLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1.12 WaterLevelReg. . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.1.13 ControlReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.1.14 BitFramingReg . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.1.15 CollReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2.2 Page 1: Communication . . . . . . . . . . . . . . . . . 36 9.2.2.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.2.2 ModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2.2.3 TxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2.2.4 RxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2.2.5 TxControlReg. . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.2.6 TxAutoReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2.7 TxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.2.8 RxSelReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.2.9 RxThresholdReg . . . . . . . . . . . . . . . . . . . . . . 44 9.2.2.10 DemodReg. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.2.11 FelNFC1Reg . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.2.12 FelNFC2Reg . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2.2.13 MifNFCReg . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.2.14 ManualRCVReg . . . . . . . . . . . . . . . . . . . . . . . 49 9.2.2.15 TypeBReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2.2.16 SerialSpeedReg. . . . . . . . . . . . . . . . . . . . . . . 50 9.2.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 52 9.2.3.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.3.2 CRCResultReg . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.3.3 GsNOffReg . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2.3.4 ModWidthReg . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3.5 TxBitPhaseReg . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3.6 RFCfgReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.3.7 GsNOnReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.8 CWGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.9 ModGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.3.10 TMode Register, TPrescaler Register . . . . . . 57 9.2.3.11 TReloadReg. . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2.3.12 TCounterValReg . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.2 TestSel1Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.3 TestSel2Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.4 TestPinEnReg . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.4.5 TestPinValueReg . . . . . . . . . . . . . . . . . . . . . . 63 9.2.4.6 TestBusReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.7 AutoTestReg . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.8 VersionReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.9 AnalogTestReg. . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.4.10 TestDAC1Reg . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.11 TestDAC2Reg . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.12 TestADCReg . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.13 RFTReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . 68 10.1 Automatic microcontroller interface detection 68 10.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 70 10.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.2 SPI write data. . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 71 10.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.1 Connection to a host . . . . . . . . . . . . . . . . . . . 71PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 135 of 136 continued >> NXP Semiconductors PN512 Full NFC Forum compliant solution 10.3.2 Selectable UART transfer speeds . . . . . . . . . 71 10.3.3 UART framing. . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 75 10.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4.2 START and STOP conditions . . . . . . . . . . . . . 76 10.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 78 10.4.6 Register write access . . . . . . . . . . . . . . . . . . . 78 10.4.7 Register read access . . . . . . . . . . . . . . . . . . . 79 10.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 80 10.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 80 10.4.10 Serial data transfer format in HS mode . . . . . 80 10.4.11 Switching between F/S mode and HS mode . 82 10.4.12 PN512 at lower speed modes . . . . . . . . . . . . 82 11 8-bit parallel interface . . . . . . . . . . . . . . . . . . . 82 11.1 Overview of supported host controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2 Separated Read/Write strobe . . . . . . . . . . . . . 83 11.3 Common Read/Write strobe . . . . . . . . . . . . . . 83 12 Analog interface and contactless UART . . . . 84 12.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.2 TX driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3 RF level detector . . . . . . . . . . . . . . . . . . . . . . 85 12.4 Data mode detector . . . . . . . . . . . . . . . . . . . . 86 12.5 Serial data switch . . . . . . . . . . . . . . . . . . . . . . 88 12.6 S2C interface support . . . . . . . . . . . . . . . . . . . 88 12.6.1 Signal shape for Felica S2C interface support 90 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support . . . . . . . . . . . . . . . . . . . 91 12.7 Hardware support for FeliCa and NFC polling 92 12.7.1 Polling sequence functionality for initiator. . . . 92 12.7.2 Polling sequence functionality for target. . . . . 92 12.7.3 Additional hardware support for FeliCa and NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.7.4 CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 93 13 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 94 13.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 94 13.3 FIFO buffer status information . . . . . . . . . . . . 94 14 Interrupt request system. . . . . . . . . . . . . . . . . 95 14.1 Interrupt sources overview . . . . . . . . . . . . . . . 95 15 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 16 Power reduction modes . . . . . . . . . . . . . . . . . 98 16.1 Hard power-down . . . . . . . . . . . . . . . . . . . . . . 98 16.2 Soft power-down mode. . . . . . . . . . . . . . . . . . 98 16.3 Transmitter power-down mode . . . . . . . . . . . . 98 17 Oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . 99 18 Reset and oscillator start-up time . . . . . . . . . 99 18.1 Reset timing requirements . . . . . . . . . . . . . . . 99 18.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 99 19 PN512 command set . . . . . . . . . . . . . . . . . . . 100 19.1 General description . . . . . . . . . . . . . . . . . . . 100 19.2 General behavior . . . . . . . . . . . . . . . . . . . . . 100 19.3 PN512 command overview . . . . . . . . . . . . . 101 19.3.1 PN512 command descriptions . . . . . . . . . . . 101 19.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 19.3.1.2 Config command . . . . . . . . . . . . . . . . . . . . . 101 19.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . 102 19.3.1.4 CalcCRC . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.6 NoCmdChange . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.7 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.8 Transceive . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.3.1.9 AutoColl . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.3.1.10 MFAuthent . . . . . . . . . . . . . . . . . . . . . . . . . . 105 19.3.1.11 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 20 Testsignals. . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.2 Testbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.3 Testsignals at pin AUX . . . . . . . . . . . . . . . . . 108 20.4 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 109 22 Application design-in information. . . . . . . . . 110 23 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 111 24 Recommended operating conditions . . . . . . 111 25 Thermal characteristics . . . . . . . . . . . . . . . . . 112 26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112 26.1 Timing characteristics . . . . . . . . . . . . . . . . . . 117 26.2 8-bit parallel interface timing . . . . . . . . . . . . . 119 26.2.1 AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119 26.2.2 AC operating specification . . . . . . . . . . . . . . . 119 26.2.2.1 Bus timing for separated Read/Write strobe . 119 26.2.2.2 Bus timing for common Read/Write strobe . 120 27 Package information. . . . . . . . . . . . . . . . . . . 122 28 Package outline. . . . . . . . . . . . . . . . . . . . . . . 123 29 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 126 30 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 31 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 126 32 Revision history . . . . . . . . . . . . . . . . . . . . . . 127 33 Legal information . . . . . . . . . . . . . . . . . . . . . 128 33.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 128 33.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 128 33.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 128 33.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 33.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 129NXP Semiconductors PN512 Full NFC Forum compliant solution © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 December 2013 111345 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 34 Contact information. . . . . . . . . . . . . . . . . . . . 129 35 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 36 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 37 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 1. Product profile 1.1 General description Unidirectional double ElectroStatic Discharge (ESD) protection diodes in a common cathode configuration, encapsulated in a SOT23 (TO-236AB) small Surface-Mounted Device (SMD) plastic package. The devices are designed for ESD and transient overvoltage protection of up to two signal lines. [1] All types available as /DG halogen-free version. 1.2 Features 1.3 Applications MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression Rev. 01 — 3 September 2008 Product data sheet Table 1. Product overview Type number[1] Package Configuration NXP JEDEC MMBZ12VDL SOT23 TO-236AB dual common cathode MMBZ15VDL MMBZ18VCL MMBZ20VCL MMBZ27VCL MMBZ33VCL ■ Unidirectional ESD protection of two lines ■ ESD protection up to 30 kV (contact discharge) ■ Bidirectional ESD protection of one line ■ IEC 61000-4-2; level 4 (ESD) ■ Low diode capacitance: Cd ≤ 140 pF ■ IEC 61643-321 ■ Rated peak pulse power: PPPM ≤ 40 W ■ AEC-Q101 qualified ■ Ultra low leakage current: IRM ≤ 5 nA ■ Computers and peripherals ■ Automotive electronic control units ■ Audio and video equipment ■ Portable electronics ■ Cellular handsets and accessoriesMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 2 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 1.4 Quick reference data 2. Pinning information Table 2. Quick reference data Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per diode VRWM reverse standoff voltage MMBZ12VDL MMBZ12VDL/DG - - 8.5 V MMBZ15VDL MMBZ15VDL/DG - - 12.8 V MMBZ18VCL MMBZ18VCL/DG - - 14.5 V MMBZ20VCL MMBZ20VCL/DG - - 17 V MMBZ27VCL MMBZ27VCL/DG - - 22 V MMBZ33VCL MMBZ33VCL/DG - - 26 V Cd diode capacitance f = 1 MHz; VR =0V MMBZ12VDL MMBZ12VDL/DG - 110 140 pF MMBZ15VDL MMBZ15VDL/DG - 85 105 pF MMBZ18VCL MMBZ18VCL/DG - 70 90 pF MMBZ20VCL MMBZ20VCL/DG - 65 80 pF MMBZ27VCL MMBZ27VCL/DG - 48 60 pF MMBZ33VCL MMBZ33VCL/DG - 45 55 pF Table 3. Pinning Pin Description Simplified outline Graphic symbol 1 anode (diode 1) 2 anode (diode 2) 3 common cathode 1 2 3 006aaa150 1 2 3MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 3 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China Table 4. Ordering information Type number Package Name Description Version MMBZ12VDL - plastic surface-mounted package; 3 leads SOT23 MMBZ15VDL MMBZ18VCL MMBZ20VCL MMBZ27VCL MMBZ33VCL MMBZ12VDL/DG - plastic surface-mounted package; 3 leads SOT23 MMBZ15VDL/DG MMBZ18VCL/DG MMBZ20VCL/DG MMBZ27VCL/DG MMBZ33VCL/DG Table 5. Marking codes Type number Marking code[1] Type number Marking code[1] MMBZ12VDL *MA MMBZ12VDL/DG TJ* MMBZ15VDL *MB MMBZ15VDL/DG TL* MMBZ18VCL *MC MMBZ18VCL/DG TN* MMBZ20VCL *MD MMBZ20VCL/DG TQ* MMBZ27VCL *ME MMBZ27VCL/DG TS* MMBZ33VCL *MF MMBZ33VCL/DG TU*MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 4 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 5. Limiting values [1] In accordance with IEC 61643-321 (10/1000 µs current waveform). [2] Measured from pin 1 or 2 to pin 3. [3] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. [1] Device stressed with ten non-repetitive ESD pulses. [2] Measured from pin 1 or 2 to pin 3. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per diode PPPM rated peak pulse power tp = 10/1000 µs [1][2] - 40 W IPPM rated peak pulse current tp = 10/1000 µs [1][2] MMBZ12VDL MMBZ12VDL/DG - 2.35 A MMBZ15VDL MMBZ15VDL/DG - 1.9 A MMBZ18VCL MMBZ18VCL/DG - 1.6 A MMBZ20VCL MMBZ20VCL/DG - 1.4 A MMBZ27VCL MMBZ27VCL/DG - 1A MMBZ33VCL MMBZ33VCL/DG - 0.87 A Per device Ptot total power dissipation Tamb ≤ 25 °C [3] - 350 mW [4] - 440 mW Tj junction temperature - 150 °C Tamb ambient temperature −55 +150 °C Tstg storage temperature −65 +150 °C Table 7. ESD maximum ratings Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Max Unit Per diode VESD electrostatic discharge voltage [1][2] IEC 61000-4-2 (contact discharge) - 30 kV machine model - 2 kVMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 5 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. [3] Soldering point at pin 3. Table 8. ESD standards compliance Standard Conditions Per diode IEC 61000-4-2; level 4 (ESD) > 15 kV (air); > 8 kV (contact) MIL-STD-883; class 3 (human body model) > 8 kV Fig 1. 10/1000 µs pulse waveform according to IEC 61643-321 Fig 2. ESD pulse waveform according to IEC 61000-4-2 tp (ms) 0 4.0 1.0 2.0 3.0 006aab319 50 100 150 IPP (%) 0 50 % IPP; 1000 µs 100 % IPP; 10 µs 001aaa631 IPP 100 % 90 % t 30 ns 60 ns 10 % tr = 0.7 ns to 1 ns Table 9. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per device Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 350 K/W [2] - - 280 K/W Rth(j-sp) thermal resistance from junction to solder point [3] - - 60 K/WMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 6 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 7. Characteristics Table 10. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per diode VF forward voltage MMBZ12VDL MMBZ12VDL/DG IF = 10 mA - - 0.9 V MMBZ15VDL MMBZ15VDL/DG IF = 10 mA - - 0.9 V MMBZ18VCL MMBZ18VCL/DG IF = 10 mA - - 0.9 V MMBZ20VCL MMBZ20VCL/DG IF = 10 mA - - 0.9 V MMBZ27VCL MMBZ27VCL/DG IF = 200 mA - - 1.1 V MMBZ33VCL MMBZ33VCL/DG IF = 10 mA - - 0.9 V VRWM reverse standoff voltage MMBZ12VDL MMBZ12VDL/DG - - 8.5 V MMBZ15VDL MMBZ15VDL/DG - - 12.8 V MMBZ18VCL MMBZ18VCL/DG - - 14.5 V MMBZ20VCL MMBZ20VCL/DG - - 17 V MMBZ27VCL MMBZ27VCL/DG - - 22 V MMBZ33VCL MMBZ33VCL/DG - - 26 V IRM reverse leakage current MMBZ12VDL MMBZ12VDL/DG VRWM = 8.5 V - 0.1 5 nA MMBZ15VDL MMBZ15VDL/DG VRWM = 12.8 V - 0.1 5 nA MMBZ18VCL MMBZ18VCL/DG VRWM = 14.5 V - 0.1 5 nA MMBZ20VCL MMBZ20VCL/DG VRWM = 17 V - 0.1 5 nA MMBZ27VCL MMBZ27VCL/DG VRWM = 22 V - 0.1 5 nA MMBZ33VCL MMBZ33VCL/DG VRWM = 26 V - 0.1 5 nAMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 7 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression VBR breakdown voltage IR = 1 mA MMBZ12VDL MMBZ12VDL/DG 11.4 12 12.6 V MMBZ15VDL MMBZ15VDL/DG 14.3 15 15.8 V MMBZ18VCL MMBZ18VCL/DG 17.1 18 18.9 V MMBZ20VCL MMBZ20VCL/DG 19 20 21 V MMBZ27VCL MMBZ27VCL/DG 25.65 27 28.35 V MMBZ33VCL MMBZ33VCL/DG 31.35 33 34.65 V Cd diode capacitance f = 1 MHz; VR =0V MMBZ12VDL MMBZ12VDL/DG - 110 140 pF MMBZ15VDL MMBZ15VDL/DG - 85 105 pF MMBZ18VCL MMBZ18VCL/DG - 70 90 pF MMBZ20VCL MMBZ20VCL/DG - 65 80 pF MMBZ27VCL MMBZ27VCL/DG - 48 60 pF MMBZ33VCL MMBZ33VCL/DG - 45 55 pF VCL clamping voltage [1][2] MMBZ12VDL MMBZ12VDL/DG IPPM = 2.35 A - - 17 V MMBZ15VDL MMBZ15VDL/DG IPPM = 1.9 A - - 21.2 V MMBZ18VCL MMBZ18VCL/DG IPPM = 1.6 A - - 25 V MMBZ20VCL MMBZ20VCL/DG IPPM = 1.4 A - - 28 V MMBZ27VCL MMBZ27VCL/DG IPPM = 1 A - - 38 V MMBZ33VCL MMBZ33VCL/DG IPPM = 0.87 A - - 46 V Table 10. Characteristics …continued Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max UnitMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 8 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression [1] In accordance with IEC 61643-321 (10/1000 µs current waveform). [2] Measured from pin 1 or 2 to pin 3. SZ temperature coefficient IZ = 1 mA MMBZ12VDL MMBZ12VDL/DG - 8.1 - mV/K MMBZ15VDL MMBZ15VDL/DG - 11 - mV/K MMBZ18VCL MMBZ18VCL/DG - 14 - mV/K MMBZ20VCL MMBZ20VCL/DG - 15.8 - mV/K MMBZ27VCL MMBZ27VCL/DG - 23 - mV/K MMBZ33VCL MMBZ33VCL/DG - 29.4 - mV/K Table 10. Characteristics …continued Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit MMBZ27VCL: unidirectional and bidirectional Tamb = 25 °C Fig 3. Rated peak pulse power as a function of exponential pulse duration (rectangular waveform); typical values Fig 4. Relative variation of rated peak pulse power as a function of junction temperature; typical values 006aab327 102 10 103 PPPM (W) 1 tp (ms) 10−2 103 102 10−1 1 10 Tj (°C) 0 200 50 100 150 006aab321 0.4 0.8 1.2 PPPM 0 PPPM(25°C)MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 9 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression f = 1 MHz; Tamb = 25 °C (1) MMBZ15VDL: unidirectional (2) MMBZ15VDL: bidirectional (3) MMBZ27VCL: unidirectional (4) MMBZ27VCL: bidirectional MMBZ27VCL: VRWM = 22 V Fig 5. Diode capacitance as a function of reverse voltage; typical values Fig 6. Reverse leakage current as a function of junction temperature; typical values Fig 7. V-I characteristics for a unidirectional ESD protection diode Fig 8. V-I characteristics for a bidirectional ESD protection diode VR (V) 0 25 5 10 15 20 006aab328 40 60 20 80 100 Cd (pF) 0 (1) (2) (3) (4) 006aab329 10−1 10−2 10 1 102 IRM (nA) 10−3 Tamb (°C) −75 175 −25 25 75 125 006aab324 −VCL −VBR −VRWM −IRM −IR −IPP V I P-N − + −IPPM 006aab325 −VCL −VBR −VRWM −IRM VRWM VBR VCL IRM −IR IR −IPP IPP − + IPPM −IPPMMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 10 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 8. Application information The MMBZxVCL series and the MMBZxVDL series are designed for the protection of up to two unidirectional data or signal lines from the damage caused by ESD and surge pulses. The devices may be used on lines where the signal polarities are either positive or negative with respect to ground. The devices provide a surge capability of 40 W per line for a 10/1000 µs waveform. Circuit board layout and protection device placement Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. Place the devices as close to the input terminal or connector as possible. 2. The path length between the device and the protected line should be minimized. 3. Keep parallel signal paths to a minimum. 4. Avoid running protected conductors in parallel with unprotected conductors. 5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops. 6. Minimize the length of the transient return path to ground. 7. Avoid using shared transient return paths to a common ground point. 8. Ground planes should be used whenever possible. For multilayer PCBs, use ground vias. 9. Test information 9.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. Fig 9. Typical application: ESD and transient voltage protection of data lines 006aab330 MMBZxVCL/VDL line 1 to be protected unidirectional protection of two lines bidirectional protection of one line line 2 to be protected GND MMBZxVCL/VDL line 1 to be protected GNDMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 11 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 10. Package outline 11. Packing information [1] For further information and the availability of packing methods, see Section 15. Fig 10. Package outline SOT23 (TO-236AB) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Table 11. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 MMBZ12VDL SOT23 4 mm pitch, 8 mm tape and reel -215 -235 MMBZ15VDL MMBZ18VCL MMBZ20VCL MMBZ27VCL MMBZ33VCL MMBZ12VDL/DG SOT23 4 mm pitch, 8 mm tape and reel -215 -235 MMBZ15VDL/DG MMBZ18VCL/DG MMBZ20VCL/DG MMBZ27VCL/DG MMBZ33VCL/DGMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 12 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 12. Soldering Fig 11. Reflow soldering footprint SOT23 (TO-236AB) Fig 12. Wave soldering footprint SOT23 (TO-236AB) solder lands solder resist occupied area solder paste sot023_fr 0.5 (3×) 0.6 (3×) 0.6 (3×) 0.7 (3×) 3 1 3.3 2.9 1.7 1.9 2 Dimensions in mm solder lands solder resist occupied area preferred transport direction during soldering sot023_fw 2.8 4.5 1.4 4.6 1.4 (2×) 1.2 (2×) 2.2 2.6 Dimensions in mmMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 13 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes MMBZXVCL_MMBZXVDL_SER_1 20080903 Product data sheet - -MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 3 September 2008 14 of 15 NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression 14. Legal information 14.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. ESD protection devices — These products are only intended for protection against ElectroStatic Discharge (ESD) pulses and are not intended for any other usage including, without limitation, voltage regulation applications. NXP Semiconductors accepts no liability for use in such applications and therefore such use is at the customer’s own risk. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors MMBZxVCL; MMBZxVDL series Double ESD protection diodes for transient overvoltage suppression © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 September 2008 Document identifier: MMBZXVCL_MMBZXVDL_SER_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 16. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Application information. . . . . . . . . . . . . . . . . . 10 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 9.1 Quality information . . . . . . . . . . . . . . . . . . . . . 10 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 11 Packing information. . . . . . . . . . . . . . . . . . . . . 11 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 Contact information. . . . . . . . . . . . . . . . . . . . . 14 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1. Product profile 1.1 General description The devices are 4-, 6- and 8-channel RC low-pass filter arrays which are designed to provide filtering of undesired RF signals on the I/O ports of portable communication or computing devices. In addition, the devices incorporate diodes to provide protection to downstream components from ElectroStatic Discharge (ESD) voltages as high as ±30 kV. The devices are fabricated using monolithic silicon technology and integrate up to eight resistors and sixteen diodes in a 0.4 mm pitch 8-, 12- or 16-pin ultra-thin leadless Quad Flat No-leads (QFN) plastic package with a height of 0.55 mm only. 1.2 Features and benefits „ Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen and antimony (Dark Green compliant) „ 4-, 6- and 8-channel integrated π-type RC filter network „ ESD protection to ±30 kV contact discharge according to IEC 61000-4-2 far exceeding level 4 „ QFN plastic package with 0.4 mm pitch and 0.55 mm height 1.3 Applications General-purpose ElectroMagnetic Interference (EMI) and Radio-Frequency Interference (RFI) filtering and downstream ESD protection for: „ Cellular phone and Personal Communication System (PCS) mobile handsets „ Cordless telephones „ Wireless data (WAN/LAN) systems „ Mobile Internet Devices (MID) „ Portable Media Players (PMP) IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network with ESD protection Rev. 2 — 5 May 2011 Product data sheetIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 2 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 1.4 Quick reference data [1] For the total channel. 2. Pinning information Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL Cch channel capacitance f = 100 kHz; Vbias(DC) = 2.5 V [1] - 10 - pF Rs(ch) channel series resistance 80 100 120 Ω IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL Cch channel capacitance f = 100 kHz; Vbias(DC) = 2.5 V [1] - 12 - pF Rs(ch) channel series resistance 32 40 48 Ω IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL Cch channel capacitance f = 100 kHz; Vbias(DC) = 2.5 V [1] - 30 - pF Rs(ch) channel series resistance 160 200 240 Ω IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL Cch channel capacitance f = 100 kHz; Vbias(DC) = 2.5 V [1] - 30 - pF Rs(ch) channel series resistance 80 100 120 Ω Table 2. Pinning Pin Description Simplified outline Graphic symbol IP4251CZ8-4-TTL; IP4252CZ8-4-TTL; IP4253CZ8-4-TTL; IP4254CZ8-4-TTL (SOT1166-1) 1 and 8 filter channel 1 2 and 7 filter channel 2 3 and 6 filter channel 3 4 and 5 filter channel 4 ground pad ground IP4251CZ12-6-TTL; IP4252CZ12-6-TTL; IP4253CZ12-6-TTL; IP4254CZ12-6-TTL (SOT1167-1) 1 and 12 filter channel 1 2 and 11 filter channel 2 3 and 10 filter channel 3 4 and 9 filter channel 4 5 and 8 filter channel 5 6 and 7 filter channel 6 ground pad ground Transparent top view 8 1 5 4 018aaa071 Rs(ch) Cch 1 to 4 5 to 8 GND 2 Cch 2 Transparent top view 12 1 7 6 018aaa072 Rs(ch) 1 to 6 7 to 12 GND Cch 2 Cch 2IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 3 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 3. Ordering information IP4251CZ16-8-TTL; IP4252CZ16-8-TTL; IP4253CZ16-8-TTL; IP4254CZ16-8-TTL (SOT1168-1) 1 and 16 filter channel 1 2 and 15 filter channel 2 3 and 14 filter channel 3 4 and 13 filter channel 4 5 and 12 filter channel 5 6 and 11 filter channel 6 7 and 10 filter channel 7 8 and 9 filter channel 8 ground pad ground Table 2. Pinning …continued Pin Description Simplified outline Graphic symbol Transparent top view 16 1 9 8 018aaa073 Rs(ch) 1 to 8 9 to 16 GND Cch 2 Cch 2 Table 3. Ordering information Type number Package Name Description Version IP4251CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads; 8 terminals; body 1.35 × 1.7 × 0.55 mm SOT1166-1 IP4251CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads; 12 terminals; body 1.35 × 2.5 × 0.55 mm SOT1167-1 IP4251CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads; 16 terminals; body 1.35 × 3.3 × 0.55 mm SOT1168-1 IP4252CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads; 8 terminals; body 1.35 × 1.7 × 0.55 mm SOT1166-1 IP4252CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads; 12 terminals; body 1.35 × 2.5 × 0.55 mm SOT1167-1 IP4252CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads; 16 terminals; body 1.35 × 3.3 × 0.55 mm SOT1168-1 IP4253CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads; 8 terminals; body 1.35 × 1.7 × 0.55 mm SOT1166-1 IP4253CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads; 12 terminals; body 1.35 × 2.5 × 0.55 mm SOT1167-1 IP4253CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads; 16 terminals; body 1.35 × 3.3 × 0.55 mm SOT1168-1 IP4254CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads; 8 terminals; body 1.35 × 1.7 × 0.55 mm SOT1166-1 IP4254CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads; 12 terminals; body 1.35 × 2.5 × 0.55 mm SOT1167-1 IP4254CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads; 16 terminals; body 1.35 × 3.3 × 0.55 mm SOT1168-1IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 4 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 4. Limiting values [1] Device tested with 1000 pulses of ±15 kV contact discharges, according to the IEC 61000-4-2 model, far exceeding IEC 61000-4-2 level 4 (8 kV contact discharge). [2] Device tested with 1000 pulses of ±30 kV contact discharges, according to the IEC 61000-4-2 model, far exceeding IEC 61000-4-2 level 4 (8 kV contact discharge). Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL VESD electrostatic discharge voltage all pins to ground; contact discharge [1] - ±15 kV IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL VESD electrostatic discharge voltage all pins to ground; contact discharge [1] - ±15 kV IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL VESD electrostatic discharge voltage all pins to ground [2] contact discharge - ±30 kV air discharge - ±30 kV IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL VESD electrostatic discharge voltage all pins to ground [2] contact discharge - ±30 kV air discharge - ±30 kV Per device VESD electrostatic discharge voltage IEC 61000-4-2, level 4; all pins to ground contact discharge - ±8 kV air discharge - ±15 kV VCC supply voltage −0.5 +5.6 V Pch channel power dissipation Tamb = 85 °C - 60 mW Ptot total power dissipation Tamb = 85 °C - 200 mW Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °CIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 5 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 5. Characteristics [1] For the total channel. [2] Guaranteed by design. Table 5. Channel characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL Cch channel capacitance f = 100 kHz [1] Vbias(DC) = 2.5 V - 10 - pF Vbias(DC) =0V [2] - 15 - pF Rs(ch) channel series resistance 80 100 120 Ω IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL Cch channel capacitance f = 100 kHz [1] Vbias(DC) = 2.5 V - 12 - pF Vbias(DC) =0V [2] - 18 - pF Rs(ch) channel series resistance 32 40 48 Ω IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL Cch channel capacitance f = 100 kHz [1] Vbias(DC) = 2.5 V - 30 - pF Vbias(DC) =0V [2] - 45 - pF Rs(ch) channel series resistance 160 200 240 Ω IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL Cch channel capacitance f = 100 kHz [1] Vbias(DC) = 2.5 V - 30 - pF Vbias(DC) =0V [2] - 45 - pF Rs(ch) channel series resistance 80 100 120 Ω Per device ILR reverse leakage current per channel; VI = 3.5 V - - 0.1 μA VBR breakdown voltage positive clamp; II = 1 mA 5.8 - 9 V VF forward voltage negative clamp; IF = 1 mA 0.4 - 1.5 VIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 6 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network Table 6. Frequency characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL αil insertion loss Rsource = 50 Ω; RL = 50 Ω 800 MHz < f < 3 GHz - 16 - dB f = 1 GHz - 20 - dB αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω; 800 MHz < f < 3 GHz - 30 - dB IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL αil insertion loss Rsource = 50 Ω; RL = 50 Ω 800 MHz < f < 3 GHz - 12 - dB f = 1 GHz - 14 - dB αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω; 800 MHz < f < 3 GHz - 40 - dB IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL αil insertion loss Rsource = 50 Ω; RL = 50 Ω 800 MHz < f < 3 GHz - 33 - dB f = 1 GHz 35 - - dB αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω; 800 MHz < f < 3 GHz - 30 - dB IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL αil insertion loss Rsource = 50 Ω; RL = 50 Ω 800 MHz < f < 3 GHz - 28 - dB f = 1 GHz 30 - - dB αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω; 800 MHz < f < 3 GHz - 30 - dBIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 7 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 6. Application information 6.1 Insertion loss The devices are designed as EMI/RFI filters for multichannel interfaces. The block schematic for measuring insertion loss in a 50 Ω system is shown in Figure 1. Typical measurements results are shown in Figure 2 to Figure 6 for the different devices. (1) IP4252CZ16-8-TTL - channel 1 to channel 16 (2) IP4251CZ16-8-TTL - channel 1 to channel 16 (3) IP4254CZ16-8-TTL - channel 1 to channel 16 (4) IP4253CZ16-8-TTL - channel 1 to channel 16 Fig 1. Frequency response setup Fig 2. Frequency response curves overview 018aaa074 50 Ω Vgen 50 Ω DUT IN OUT 001aaj308 −30 −20 −40 −10 0 S21 (dB) −50 f (MHz) 10−1 104 103 1 102 10 (1) (2) (3) (4)IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 8 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network Due to the optimized silicon dice and package design, all channels in a single package show a very good matching performance as the insertion loss for a channel at the package side (e.g. channel 1 to channel 16) is nearly identical with the center channels (e.g. channel 4 to channel 13). (1) Channel 1 to channel 16 (2) Channel 4 to channel 13 (1) Channel 1 to channel 16 (2) Channel 4 to channel 13 Fig 3. IP4251CZ16-8-TTL: frequency response curves Fig 4. IP4252CZ16-8-TTL: frequency response curves (1) Channel 1 to channel 16 (2) Channel 4 to channel 13 (1) Channel 4 to channel 13 (2) Channel 1 to channel 16 Fig 5. IP4253CZ16-8-TTL: frequency response curves Fig 6. IP4254CZ16-8-TTL: frequency response curves 001aaj608 −30 −20 −40 −10 0 S21 (dB) −50 f (MHz) 10−1 104 103 1 102 10 (1) (2) 001aaj609 −30 −20 −40 −10 0 S21 (dB) −50 f (MHz) 10−1 104 103 1 102 10 (1) (2) 001aaj610 −30 −20 −40 −10 0 S21 (dB) −50 f (MHz) 10−1 104 103 1 102 10 (1) (2) 001aaj611 −30 −20 −40 −10 0 S21 (dB) −50 f (MHz) 10−1 104 103 1 102 10 (1) (2)IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 9 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 6.2 Selection The selection of one of the filter devices has to be performed depending on the maximum clock frequency, driver strength, capacitive load of the sink, and also the maximum applicable rise and fall times. 6.2.1 SDHC and MMC memory interface The Secure Digital High Capacity (SDHC) memory card interface standard specification and the Multi Media Card (MMC) (JESD 84A43) standard specification recommend a rise and fall time of 25 % to 62.5 % (62.5 % to 25 % respectively) of 3 ns or less for the input signal of the receiving interface side. Assuming a typical capacitance of about 20 pF for the SDHC memory card itself, and approximately 4 pF to 7 pF for the Printed-Circuit Board (PCB) and the card holder, IP4252CZ12-6-TTL (6 channels, Rs(ch) = 40 Ω, Cch = 12 pF at Vbias(DC) = 2.5 V) is a matching selection to filter and protect all relevant interface pins such as CLK, CMD, and DAT0 to DAT3/CD. Please refer to Figure 7 for a general example of the implementation of the device in an SDHC card interface. In case additional channels such as write-protect or a mechanical card-detection switch are used, the IP4252CZ16-8-TTL (8 channels, Rs(ch) = 40 Ω, Cch = 12 pF at Vbias(DC) = 2.5 V) offers two additional channels.IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 10 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network The capacitance values specified for the signal channels of the MMC interface differ from the SDHC specification. The MMC card-side interface is specified to have an intrinsic capacitance of 12 pF to 18 pF and the total channel is limited according to the specification to 30 pF only. Therefore, any filter device capacitance is limited to a maximum of up to 18 pF, including the card holder and PCB traces. Please refer to Figure 8 for a general example of the implementation of the IP4252 in an MMC interface application. Fig 7. Example of IP4252 in an SDHC card interface 018aaa075 IP4252CZ12-6-TTL (IP4252CZ16-8-TTL) DAT1 pull-up resistors 10 kΩ − 100 kΩ 10 kΩ − 90 kΩ DAT3/CD pull-up 10 kΩ − 100 kΩ DAT3/CD pull-up >270 kΩ exact value depends on required logic levels DAT1 SD MEMORY CARD SET_CLR_ CARD_DETECT (ACMD42) to HOST INTERFACE DAT0 GND CLK VCC(VSD) VCC(VSD) DAT3/CD CMD DAT2 optional: 2-additional channels of IP4252CZ16-8-TTL optional: write protect switch optional: electrical card detect WP DAT0 CLK CMD DAT3/CD DAT2 CD WP optional: card detect switch CDIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 11 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network To generate SDHC and MMC-compliant digital signals, the driver strength should not significantly undercut 8 mA. 6.2.2 LCD interfaces, medium-speed interfaces For digital interfaces such as LCD interfaces running at clock speeds between 10 MHz and 25 MHz or more, IP4251, IP4252 or IP4254 can be used depending on the sink load, clock speed, driver strength and rise and fall time requirements. Also the minimum EMI filter requirements may be a decision-making factor. 6.2.3 Keypad, low-speed interfaces Especially for lower-speed interfaces such as keypads, low-speed serial interfaces (e.g. Recommended Standard (RS) 232) and low-speed control signals, IP4253 (Rs(ch) = 200 Ω, Cch = 30 pF at Vbias(DC) = 2.5 V) offers a very robust ESD protection and strong suppression of unwanted frequencies (EMI filtering). Fig 8. Example of IP4252 in an MMC interface 018aaa076 IP4252CZ12-6-TTL IP4252CZ8-4-TTL DAT1 pull-up resistors 50 kΩ - 100 kΩ CMD pull-up 4.7 kΩ - 100 kΩ DAT1 C8 e.g. RSMMC HOST INTERFACE DAT0 C7 DAT7 C13 VSS2 C6 DAT6 C12 CLK C5 VCC(VMMC) VCC(VMMC) C4 VSS1 C3 DAT5 C11 CMD C2 DAT4 C10 DAT3 C1 DAT2 CMD DAT4 DAT3 DAT2 C9 DAT0 DAT7 DAT6 CLK DAT5IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 12 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 7. Package outline Fig 9. Package outline SOT1166-1 (HUSON8) Outline References version European projection Issue date IEC JEDEC JEITA SOT1166-1 - - - - - - - - - sot1166-1_po 10-03-18 10-03-22 Unit(1) mm max nom min 0.55 0.05 0.00 0.25 0.20 0.15 1.8 1.7 1.6 1.3 1.2 1.1 1.45 1.35 1.25 0.4 1.2 0.30 0.25 0.20 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HUSON8: plastic, thermal enhanced ultra thin small outline package; no leads; 8 terminals; body 1.35 x 1.7 x 0.55 mm SOT1166-1 A1 c 0.127 b DDh E Eh 0.45 0.40 0.35 e e1 k 0.2 L v 0.1 w 0.05 y 0.05 y1 0 1 2 mm scale X C y1 C y tiebars are indicated on arbitrary location and size detail X A A1 c terminal 1 index area D B A E b terminal 1 index area e1 e v C A B w C L k Eh Dh 1 8 4 5IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 13 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network Fig 10. Package outline SOT1167-1 (HUSON12) Outline References version European projection Issue date IEC JEDEC JEITA SOT1167-1 - - - - - - - - - sot1167-1_po 10-03-18 10-03-22 Unit(1) mm max nom min 0.55 0.05 0.00 0.25 0.20 0.15 2.6 2.5 2.4 2.1 2.0 1.9 1.45 1.35 1.25 0.4 2.0 0.30 0.25 0.20 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HUSON12: plastic, thermal enhanced ultra thin small outline package; no leads; 12 terminals; body 1.35 x 2.5 x 0.55 mm SOT1167-1 A1 c 0.127 b DDh E Eh 0.45 0.40 0.35 e e1 k 0.2 L v 0.1 w 0.05 y 0.05 y1 0 1 2 mm scale X C y1 C y tiebars are indicated on arbitrary location and size detail X A A1 c terminal 1 index area D B A E b terminal 1 index area e1 e v C A B w C L k Eh Dh 1 12 6 7IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 14 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network Fig 11. Package outline SOT1168-1 (HUSON16) Outline References version European projection Issue date IEC JEDEC JEITA SOT1168-1 - - - - - - - - - sot1168-1_po 10-03-18 10-03-22 Unit(1) mm max nom min 0.55 0.05 0.00 0.25 0.20 0.15 3.4 3.3 3.2 2.9 2.8 2.7 1.45 1.35 1.25 0.4 2.8 0.30 0.25 0.20 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HUSON16: plastic, thermal enhanced ultra thin small outline package; no leads; 16 terminals; body 1.35 x 3.3 x 0.55 mm SOT1168-1 A1 c 0.127 b DDh E Eh 0.45 0.40 0.35 e e1 k 0.2 L v 0.1 w 0.05 y 0.05 y1 0 1 2 mm scale X C y1 C y tiebars are indicated on arbitrary location and size detail X A A1 c terminal 1 index area D B A E b terminal 1 index area e1 e v C A B w C L k Eh Dh 1 16 8 9IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 15 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes IP4251_52_53_54-TTL v.2 20110505 Product data sheet - IP4251_52_53_54-TTL v.1 Modifications: • Section 1 “Product profile”: updated. • Table 2 “Pinning”: updated. • Deleted section “Thermal characteristics”. IP4251_52_53_54-TTL v.1 20110131 Objective data sheet - -IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 16 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network 9. Legal information 9.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 May 2011 17 of 18 NXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors IP4251/52/53/54-TTL Integrated 4-, 6- and 8-channel passive filter network © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2011 Document identifier: IP4251_52_53_54-TTL Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 2 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Application information. . . . . . . . . . . . . . . . . . . 7 6.1 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2.1 SDHC and MMC memory interface . . . . . . . . . 9 6.2.2 LCD interfaces, medium-speed interfaces . . . 11 6.2.3 Keypad, low-speed interfaces. . . . . . . . . . . . . 11 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 Contact information. . . . . . . . . . . . . . . . . . . . . 17 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DATA SHEET Product data sheet Supersedes data of 2003 Nov 27 2004 Nov 04 DISCRETE SEMICONDUCTORS PBSS5320X 20 V, 3 A PNP low VCEsat (BISS) transistor dbook, halfpage M3D1092004 Nov 04 2 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X FEATURES • SOT89 (SC-62) package • Low collector-emitter saturation voltage VCEsat • High collector current capability: IC and ICM • Higher efficiency leading to less heat generation • Reduced printed-circuit board requirements. APPLICATIONS • Power management – DC/DC converters – Supply line switching – Battery charger – LCD backlighting. • Peripheral drivers – Driver in low supply voltage applications (e.g. lamps and LEDs) – Inductive load driver (e.g. relays, buzzers and motors). DESCRIPTION PNP low VCEsat transistor in a SOT89 plastic package. NPN complement: PBSS4320X. MARKING TYPE NUMBER MARKING CODE PBSS5320X S45 PINNING PIN DESCRIPTION 1 emitter 2 collector 3 base 321 sym079 1 2 3 Fig.1 Simplified outline (SOT89) and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER MAX. UNIT VCEO collector-emitter voltage −20 V IC collector current (DC) −3 A ICM peak collector current −5 A RCEsat equivalent on-resistance 105 mΩ ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION PBSS5320X SC-62 plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT892004 Nov 04 3 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Notes 1. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; standard footprint. 2. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 1 cm2. 3. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 6 cm2. 4. Device mounted on a ceramic printed-circuit board 7 cm2, single-sided copper, tin-plated. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCBO collector-base voltage open emitter − −20 V VCEO collector-emitter voltage open base − −20 V VEBO emitter-base voltage open collector − −5 V IC collector current (DC) note 4 − −3 A ICM peak collector current limited by Tj(max) − −5 A IB base current (DC) − −0.5 A Ptot total power dissipation Tamb ≤ 25 °C note 1 − 550 mW note 2 − 1 W note 3 − 1.4 W note 4 − 1.6 W Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb ambient temperature −65 +150 °C2004 Nov 04 4 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X handbook, halfpage 0 40 80 160 Ptot (W) (1) (2) (3) 2 0 1.6 120 1.2 0.8 0.4 MLE372 Tamb (°C) (4) Fig.2 Power derating curves. (1) Ceramic PCB; 7 cm2 mounting pad for collector. (2) FR4 PCB; 6 cm2 copper mounting pad for collector. (3) FR4 PCB; 1 cm2 copper mounting pad for collector. (4) Standard footprint.2004 Nov 04 5 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X THERMAL CHARACTERISTICS Notes 1. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; standard footprint. 2. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 1 cm2. 3. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 6 cm2. 4. Device mounted on a ceramic printed-circuit board 7 cm2, single-sided copper, tin-plated. SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-a) thermal resistance from junction to ambient in free air note 1 225 K/W note 2 125 K/W note 3 90 K/W note 4 80 K/W Rth(j-s) thermal resistance from junction to soldering point 16 K/W 006aaa243 10 1 102 103 Zth(j-a) (K/W) 10−1 10−5 10 10 −2 10−4 102 10−1 tp (s) 10−3 103 1 duty cycle = 1.00 0.75 0.50 0.33 0.20 0.10 0.05 0.02 0.01 0 Fig.3 Transient thermal impedance as a function of pulse time; typical values. Mounted on FR4 printed-circuit board; standard footprint.2004 Nov 04 6 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X 006aaa244 10 1 102 103 Zth(j-a) (K/W) 10−1 10−5 10 10 −2 10−4 102 10−1 tp (s) 10−3 103 1 duty cycle = 1.00 0.75 0.50 0.20 0.05 0.02 0.01 0 0.33 0.10 Fig.4 Transient thermal impedance as a function of pulse time; typical values. Mounted on FR4 printed-circuit board; mounting pad for collector 1 cm2. 006aaa245 10 1 102 103 Zth(j-a) (K/W) 10−1 10−5 10 10 −2 10−4 102 10−1 tp (s) 10−3 103 1 duty cycle = 1.00 0.75 0.50 0.20 0.05 0.02 0.01 0 0.33 0.10 Fig.5 Transient thermal impedance as a function of pulse time; typical values. Mounted on FR4 printed-circuit board; mounting pad for collector 6 cm2.2004 Nov 04 7 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X CHARACTERISTICS Tamb = 25 °C unless otherwise specified. Note 1. Pulse test: tp ≤ 300 μs; δ ≤ 0.02. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ICBO collector-base cut-off current VCB = −20 V; IE = 0 A − − −100 nA VCB = −20 V; IE = 0 A; Tj = 150 °C − − −50 μA ICES collector-emitter cut-off current VCE = −20 V; VBE = 0 V − − −100 nA IEBO emitter-base cut-off current VEB = −5 V; IC = 0 A − − −100 nA hFE DC current gain VCE = −2 V IC = −0.1 A 220 − − IC = −0.5 A 220 − − IC = −1 A; note 1 200 − − IC = −2 A; note 1 150 − − IC = −3 A; note 1 100 − − VCEsat collector-emitter saturation voltage IC = −0.5 A; IB = −50 mA − − −70 mV IC = −1 A; IB = −50 mA − − −130 mV IC = −2 A; IB = −100 mA − − −230 mV IC = −3 A; IB = −300 mA; note 1 − − −300 mV RCEsat equivalent on-resistance IC = −3 A; IB = −300 mA; note 1 − 90 105 mΩ VBEsat base-emitter saturation voltage IC = −2 A; IB = −100 mA − −1.1 − V IC = −3 A; IB = −300 mA; note 1 − − −1.2 V VBEon base-emitter turn-on voltage VCE = −2 V; IC = −1 A −1.1 − − V fT transition frequency IC = −100 mA; VCE = −5 V; f = 100 MHz 100 − − MHz Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 1 MHz − − 50 pF2004 Nov 04 8 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X 0 800 200 400 600 MLE374 −10−1 −1 I C (mA) hFE −10 −102 −103 −104 (2) (3) (1) Fig.6 DC current gain as a function of collector current; typical values. VCE = −2 V. (1) Tamb = 100 °C. (2) Tamb = 25 °C. (3) Tamb = −55 °C. handbook, halfpage MLE368 0 −1.2 −0.4 −0.8 −10−1 −1 −10 I C (mA) VBE (V) −102 −103 −104 (1) (3) (2) Fig.7 Base-emitter voltage as a function of collector current; typical values. VCE = −2 V. (1) Tamb = −55 °C. (2) Tamb = 25 °C. (3) Tamb = 100 °C. handbook, halfpage MLE370 −1 −10−1 −10−2 −10−3 −10−1 −1 −10 I C (mA) VCEsat (V) −102 −103 −104 (1) (3) (2) Fig.8 Collector-emitter saturation voltage as a function of collector current; typical values. IC/IB = 20. (1) Tamb = 100 °C. (2) Tamb = 25 °C. (3) Tamb = −55 °C. handbook, halfpage MLE371 −1 −10−1 −10−2 −10−3 −10−1 −1 −10 I C (mA) VCEsat (V) −102 −103 −104 (3) (1) (2) Fig.9 Collector-emitter saturation voltage as a function of collector current; typical values. Tamb = 25 °C. (1) IC/IB = 100. (2) IC/IB = 50. (3) IC/IB = 10.2004 Nov 04 9 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X handbook, halfpage −10 −1 −10−1 −1 −10 −102 −103 −104 −10−1 MLE369 I C (mA) VBEsat (V) (2) (3) (1) Fig.10 Base-emitter saturation voltage as a function of collector current; typical values. IC/IB = 20. (1) Tamb = −55 °C. (2) Tamb = 25 °C. (3) Tamb = 100 °C. handbook, halfpage 103 102 10 1 10−2 10−1 MLE376 −10−1 −1 −10 I C (mA) RCEsat (Ω) −103 −102 −104 (1) (3) (2) Fig.11 Equivalent on-resistance as a function of collector current; typical values. Tamb = 25 °C. (1) IC/IB = 100. (2) IC/IB = 50. (3) IC/IB = 10. handbook, halfpage MLE367 102 10 10−1 10−2 1 −10−1 −1 RCEsat (Ω) I C (mA) −10 −102 −103 −104 (2) (3) (1) Fig.12 Equivalent on-resistance as a function of collector current; typical values. IC/IB = 20. (1) Tamb = 100 °C. (2) Tamb = 25 °C. (3) Tamb = −55 °C. handbook, halfpage 0 −2 −5 0 −1 −2 −3 −4 −0.4 VCE (V) I C (A) −0.8 −1.2 −1.6 MLE375 (8) (5) (1) (2) (3) (4) (10) (7) (6) (9) Fig.13 Collector current as a function of collector-emitter voltage; typical values. (1) IB = −25 mA. (2) IB = −22.5 mA. (3) IB = −20 mA. (4) IB = −17.5 mA. (5) IB = −15 mA. (6) IB = −12.5 mA. (7) IB = −10 mA. (8) IB = −7.5 mA. (9) IB = −5 mA. (10) IB = −2.5 mA. Tamb = 25 °C.2004 Nov 04 10 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X PACKAGE OUTLINE REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA DIMENSIONS (mm are the original dimensions) SOT89 TO-243 SC-62 04-08-03 06-03-16 w M e1 e E HE B 0 2 4 mm scale bp3 bp2 bp1 c D Lp A Plastic surface-mounted package; collector pad for good heat transfer; 3 leads SOT89 1 23 UNIT A mm 1.6 1.4 0.48 0.35 c 0.44 0.23 D 4.6 4.4 E 2.6 2.4 HE Lp 4.25 3.75 e 3.0 w 0.13 e1 1.5 1.2 0.8 bp1 bp2 0.53 0.40 bp3 1.8 1.42004 Nov 04 11 NXP Semiconductors Product data sheet 20 V, 3 A PNP low VCEsat (BISS) transistor PBSS5320X DATA SHEET STATUS Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DISCLAIMERS General ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. 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Printed in The Netherlands R75/03/pp12 Date of release: 2004 Nov 04 Document order number: 9397 750 13887 Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz • Data and Non-volatile Program and Data Memories – 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles – 128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – USI – Universal Serial Interface – Full Duplex USART • Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF • Operating Voltages – 1.8 – 5.5V (ATtiny2313V) – 2.7 – 5.5V (ATtiny2313) • Speed Grades – ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V – ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V • Typical Power Consumption – Active Mode 1 MHz, 1.8V: 230 µA 32 kHz, 1.8V: 20 µA (including oscillator) – Power-down Mode < 0.1 µA at 1.8V 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny2313/V Preliminary Rev. 2543L–AVR–08/102 2543L–AVR–08/10 ATtiny2313 Pin Configurations Figure 1. Pinout ATtiny2313 Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (RESET/dW) PA2 (RXD) PD0 (TXD) PD1 (XTAL2) PA1 (XTAL1) PA0 (CKOUT/XCK/INT0) PD2 (INT1) PD3 (T0) PD4 (OC0B/T1) PD5 GND 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC PB7 (UCSK/SCL/PCINT7) PB6 (MISO/DO/PCINT6) PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PB0 (AIN0/PCINT0) PD6 (ICP) PDIP/SOIC 1 2 3 4 5 MLF 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (TXD) PD1 XTAL2) PA1 (XTAL1) PA0 (CKOUT/XCK/INT0) PD2 (INT1) PD3 (T0) PD4 (OC0B/T1) PD5 GND (ICP) PD6 (AIN0/PCINT0) PB0 PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PD0 (RXD) PA2 (RESET/dW) VCC PB7 (UCSK/SCK/PCINT7) PB6 (MISO/DO/PCINT6) NOTE: Bottom pad should be soldered to ground.3 2543L–AVR–08/10 ATtiny2313 Block Diagram Figure 2. Block Diagram PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER GND VCC INSTRUCTION DECODER CONTROL LINES STACK POINTER SRAM GENERAL PURPOSE REGISTER ALU STATUS REGISTER PROGRAMMING LOGIC SPI 8-BIT DATA BUS XTAL1 XTAL2 RESET INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTERS INTERRUPT UNIT EEPROM USI USART ANALOG COMPARATOR DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTA DATA DIR. REG. PORTA PORTB DRIVERS PB0 - PB7 PORTA DRIVERS PA0 - PA2 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD6 ON-CHIP DEBUGGER INTERNAL CALIBRATED OSCILLATOR4 2543L–AVR–08/10 ATtiny2313 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.5 2543L–AVR–08/10 ATtiny2313 Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313 as listed on page 53. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny2313 as listed on page 53. Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313 as listed on page 56. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1 is an alternate function for PA0. XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.6 2543L–AVR–08/10 ATtiny2313 General Information Resources A comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.atmel.com/avr. Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.7 2543L–AVR–08/10 ATtiny2313 AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n8 2543L–AVR–08/10 ATtiny2313 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.9 2543L–AVR–08/10 ATtiny2313 The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4 shows the structure of the 32 general purpose working registers in the CPU. Bit 7 6 5 4 3 2 1 0 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 010 2543L–AVR–08/10 ATtiny2313 Figure 4. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. The X-register, Yregister, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte 15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E)11 2543L–AVR–08/10 ATtiny2313 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6. The Parallel Instruction Fetches and Instruction Executions Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Bit 15 14 13 12 11 10 9 8 – – – – – – – – SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU12 2543L–AVR–08/10 ATtiny2313 Figure 7. Single Cycle ALU Operation Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. Refer to “Interrupts” on page 44 for more information. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU13 2543L–AVR–08/10 ATtiny2313 CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ... ... ... ... 46 2543L–AVR–08/10 ATtiny2313 I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 21. Refer to “Electrical Characteristics” on page 177 for a complete list of parameters. Figure 21. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 58. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 47. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 51. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Cpin Logic Rpu See Figure "General Digital I/O" for Details Pxn47 2543L–AVR–08/10 ATtiny2313 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 22. General Digital I/O(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O-Ports” on page 58, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. clk RPx RRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE clkI/O: I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q D Q Q Q D CLR PORTxn Q Q D CLR DDxn PINxn DATA BUS SLEEP SLEEP: SLEEP CONTROL Pxn I/O WPx 0 1 WRx WPx: WRITE PINx REGISTER48 2543L–AVR–08/10 ATtiny2313 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 22 summarizes the control signals for the pin value. Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 23. Synchronization when Reading an Externally Applied Pin value Table 22. Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up Comment 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK tpd, max tpd, min49 2543L–AVR–08/10 ATtiny2313 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 24. Synchronization when Reading a Software Assigned Pin Value out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd50 2543L–AVR–08/10 ATtiny2313 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: 1. For the assembly program, two temporary registers are used to minimize the time from pullups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Digital Input Enable and Sleep Modes As shown in Figure 22, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 51. If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 38 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 38. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling freTn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/O81 2543L–AVR–08/10 ATtiny2313 quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38. General Timer/Counter Control Register – GTCCR • Bits 7..1 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as zero. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. PSR10 Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 — – – – – – — PSR10 GTCCR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 082 2543L–AVR–08/10 ATtiny2313 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) Overview Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 104. Figure 40. 16-bit Timer/Counter Block Diagram(1) Note: 1. Refer to Figure 1 on page 2 for Timer/Counter1 pin placement and description. Clock Select Timer/Counter DATA BUS OCRnA OCRnB ICRn = = TCNTn Waveform Generation Waveform Generation OCnA OCnB Noise Canceler ICPn = Fixed TOP Values Edge Detector Control Logic = 0 TOP BOTTOM Count Clear Direction TOVn (Int.Req.) OCnA (Int.Req.) OCnB (Int.Req.) ICFn (Int.Req.) TCCRnA TCCRnB ( From Analog Comparator Ouput ) Tn Edge Detector ( From Prescaler ) clkTn83 2543L–AVR–08/10 ATtiny2313 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 84. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Output Compare Units” on page 90.. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 149.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. Definitions The following definitions are used extensively throughout the section: Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10. • PWM11 is changed to WGM11. • CTC1 is changed to WGM12. Table 42. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.84 2543L–AVR–08/10 ATtiny2313 The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16- bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.85 2543L–AVR–08/10 ATtiny2313 Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ...86 2543L–AVR–08/10 ATtiny2313 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example returns the TCNT1 value in the r17:r16 register pair. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; }87 2543L–AVR–08/10 ATtiny2313 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; }88 2543L–AVR–08/10 ATtiny2313 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 80. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 41 shows a block diagram of the counter and its surroundings. Figure 41. Counter Unit Block Diagram Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 94. TEMP (8-bit) DATA BUS (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) Control Logic Count Clear Direction TOVn (Int.Req.) Clock Select TOP BOTTOM Tn Edge Detector ( From Prescaler ) clkTn89 2543L–AVR–08/10 ATtiny2313 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 42. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 42. Input Capture Unit Block Diagram When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. ICFn (Int.Req.) Analog Comparator WRITE ICRn (16-bit Register) ICRnH (8-bit) Noise Canceler ICPn Edge Detector TEMP (8-bit) DATA BUS (8-bit) ICRnL (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) ACO* ACIC* ICNC ICES90 2543L–AVR–08/10 ATtiny2313 For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 84. Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 38 on page 80). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals91 2543L–AVR–08/10 ATtiny2313 are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 94.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 43 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 43. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. OCFnx (Int.Req.) = (16-bit Comparator ) OCRnx Buffer (16-bit Register) OCRnxH Buf. (8-bit) OCnx TEMP (8-bit) DATA BUS (8-bit) OCRnxL Buf. (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) WGMn3:0 COMnx1:0 OCRnx (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) Waveform Generator TOP BOTTOM92 2543L–AVR–08/10 ATtiny2313 For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 84. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled). Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately.93 2543L–AVR–08/10 ATtiny2313 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is reset to “0”. Figure 44. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 43, Table 44 and Table 45 for details. The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 104. The COM1x1:0 bits have no effect on the Input Capture unit. PORT DDR D Q D Q OCnx OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATA BUS FOCnx clkI/O94 2543L–AVR–08/10 ATtiny2313 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 43 on page 104. For fast PWM mode refer to Table 44 on page 104, and for phase correct and phase and frequency correct PWM refer to Table 45 on page 105. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 93.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102. Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 45 on page 95. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.95 2543L–AVR–08/10 ATtiny2313 Figure 45. CTC Mode, Timing Diagram An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OCFA output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OCF1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCF1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. TCNTn OCnA (Toggle) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 (COMnA1:0 = 1) f OCnA f clk_I/O 2 ⋅ ⋅ N ( ) 1 + OCRnA = --------------------------------------------------96 2543L–AVR–08/10 ATtiny2313 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting Compare Output mode output is cleared on compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 46. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 46. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. RFPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- TCNTn OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 5 6 7 8 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)97 2543L–AVR–08/10 ATtiny2313 Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 43 on page 104). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCF1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OCF1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. f OCnxPWM f clk_I/O N ⋅ ( ) 1 + TOP = -----------------------------------98 2543L–AVR–08/10 ATtiny2313 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 47. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 47. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer RPCPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)99 2543L–AVR–08/10 ATtiny2313 value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 47 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 44 on page 104). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. f OCnxPCPWM f clk_I/O 2 ⋅ ⋅ N TOP = ----------------------------100 2543L–AVR–08/10 ATtiny2313 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 47 and Figure 48). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 48. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram RPFCPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)101 2543L–AVR–08/10 ATtiny2313 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 48 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 45 on page 105). The actual OC1Fx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCF1x). The PWM waveform is generated by setting (or clearing) the OCF1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OCF1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. f OCnxPFCPWM f clk_I/O 2 ⋅ ⋅ N TOP = ----------------------------102 2543L–AVR–08/10 ATtiny2313 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing diagram for the setting of OCF1x. Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 50 shows the same timing data, but with the prescaler enabled. Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. clkTn (clkI/O/1) OCFnx clkI/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8)103 2543L–AVR–08/10 ATtiny2313 Figure 51. Timer/Counter Timing Diagram, no Prescaling Figure 52 shows the same timing data, but with the prescaler enabled. Figure 52. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkTn (clkI/O/1) clkI/O TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8)104 2543L–AVR–08/10 ATtiny2313 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 43 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 44 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 43. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match. 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level). 1 1 Set OC1A/OC1B on Compare Match (Set output to high level). Table 44. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP105 2543L–AVR–08/10 ATtiny2313 Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 96. for more details. Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 98. for more details. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 46. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 94.). Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match when upcounting. Set OC1A/OC1B on Compare Match when downcounting. 1 1 Set OC1A/OC1B on Compare Match when upcounting. Clear OC1A/OC1B on Compare Match when downcounting.106 2543L–AVR–08/10 ATtiny2313 Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 46. Waveform Generation Mode Bit Description(1) Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) Timer/Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICR1 TOP TOP 15 1 1 1 1 Fast PWM OCR1A TOP TOP107 2543L–AVR–08/10 ATtiny2313 Timer/Counter1 Control Register B – TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 49 and Figure 50. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 47. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge.108 2543L–AVR–08/10 ATtiny2313 Timer/Counter1 Control Register C – TCCR1C • Bit 7 – FOC1A: Force Output Compare for Channel A • Bit 6 – FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. Timer/Counter1 – TCNT1H and TCNT1L The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 84. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. Output Compare Register 1 A – OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B – – – – – – TCCR1C Read/Write W W R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0109 2543L–AVR–08/10 ATtiny2313 Output Compare Register 1 B - OCR1BH and OCR1BL The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16- bit registers. See “Accessing 16-bit Registers” on page 84. Input Capture Register 1 – ICR1H and ICR1L The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 84. Timer/Counter Interrupt Mask Register – TIMSK • Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the TOV1 flag, located in TIFR, is set. • Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1A flag, located in TIFR, is set. • Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1B flag, located in TIFR, is set. • Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A TIMSK Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0110 2543L–AVR–08/10 ATtiny2313 When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the ICF1 flag, located in TIFR, is set. Timer/Counter Interrupt Flag Register – TIFR • Bit 7 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to Table 46 on page 106 for the TOV1 flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. • Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. • Bit 3 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A TIFR Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0111 2543L–AVR–08/10 ATtiny2313 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode Overview A simplified block diagram of the USART Transmitter is shown in Figure 53. CPU accessible I/O Registers and I/O pins are shown in bold. Figure 53. USART Block Diagram(1) Note: 1. Refer to Figure 1 on page 2, Table 29 on page 57, and Table 26 on page 55 for USART pin placement. PARITY GENERATOR UBRR[H:L] UDR (Transmit) UCSRA UCSRB UCSRC BAUD RATE GENERATOR TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER RxD TxD PIN CONTROL UDR (Receive) PIN CONTROL XCK DATA RECOVERY CLOCK RECOVERY PIN CONTROL TX CONTROL RX CONTROL PARITY CHECKER DATA BUS OSC SYNC LOGIC Clock Generator Transmitter Receiver112 2543L–AVR–08/10 ATtiny2313 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost. • The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Figure 53) if the Buffer Registers are full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions. The following control bits have changed name, but have same functionality and register location: • CHR9 is changed to UCSZ2. • OR is changed to DOR. Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 54 shows a block diagram of the clock generation logic.113 2543L–AVR–08/10 ATtiny2313 Figure 54. Clock Generation Logic, Block Diagram Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 54. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table 48 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps) Prescaling Down-Counter /2 UBRR /4 /2 fosc UBRR+1 Sync Register OSC XCK Pin txclk U2X UMSEL DDR_XCK 0 1 0 1 xcki xcko DDR_XCK rxclk 0 1 1 0 Edge Detector UCPOL Table 48. Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRR Value Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode BAUD f OSC 16( ) UBRR + 1 = -------------------------------------- UBRR f OSC 16BAUD = ------------------------ – 1 BAUD f OSC 8( ) UBRR + 1 = ----------------------------------- UBRR f OSC 8BAUD = -------------------- – 1 BAUD f OSC 2( ) UBRR + 1 = ----------------------------------- UBRR f OSC 2BAUD = -------------------- – 1114 2543L–AVR–08/10 ATtiny2313 BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRR Contents of the UBRRH and UBRRL Registers, (0-4095) Some examples of UBRR values for some system clock frequencies are found in Table 56 (see page 134). Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 54 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 55. Synchronous Mode XCK Timing. The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 55 shows, when UCPOL is zero the data will be changed at risf XCK f OSC 4 < ----------- RxD / TxD XCK RxD / TxD UCPOL = 0 XCK UCPOL = 1 Sample Sample115 2543L–AVR–08/10 ATtiny2313 ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 56 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 56. Frame Formats St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: Peven Parity bit using even parity Podd Parity bit using odd parity (IDLE) St Sp1 [Sp2] 0 2 3 4 [5] [6] [7] [8] [P] 1 (St / IDLE) FRAME Peven dn – 1 … d3 d2 d1 d0 0 Podd ⊕⊕⊕⊕⊕⊕ dn – 1 … d3 d2 d1 d0 ⊕⊕⊕⊕⊕⊕ 1 = =116 2543L–AVR–08/10 ATtiny2313 dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC flag can be used to check that the Transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (before UDR is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); }123 2543L–AVR–08/10 ATtiny2313 Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete interrupt will be executed as long as the RXC flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 115 and “Parity Checker” on page 124.124 2543L–AVR–08/10 ATtiny2313 Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to check if the frame had a Parity Error. The UPE bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz t BVDV BS1 Valid to DATA valid 0 250 ns tOLDV OE Low to DATA Valid 250 ns tOHDZ OE High to DATA Tri-stated 250 ns Table 76. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter Min Typ Max Units VCC GND XTAL1 SCK MISO MOSI RESET +1.8 - 5.5V173 2543L–AVR–08/10 ATtiny2313 Serial Programming Algorithm When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See Figure 79, Figure 80 and Table 79 for timing details. To program and verify the ATtiny2313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 78 on page 174): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 77 on page 174.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 77 on page 174.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 5 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 77 on page 174). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off.174 2543L–AVR–08/10 ATtiny2313 Figure 79. Serial Programming Waveforms Table 77. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT Table 78. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. Load Program Memory Page 0100 H000 000x xxxx xxxx bbbb iiii iiii Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program Memory Page 0100 1100 0000 00aa bbbb xxxx xxxx xxxx Write Program Memory Page at address a:b. Read EEPROM Memory 1010 0000 000x xxxx xbbb bbbb oooo oooo Read data o from EEPROM memory at address b. Write EEPROM Memory 1100 0000 000x xxxx xbbb bbbb iiii iiii Write data i to EEPROM memory at address b. Load EEPROM Memory Page (page access) 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. Write EEPROM Memory Page (page access) 1100 0010 00xx xxxx xbbb bb00 xxxx xxxx Write EEPROM page at address b.175 2543L–AVR–08/10 ATtiny2313 Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 64 on page 158 for details. Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to program Lock bits. See Table 64 on page 158 for details. Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx xxxi Set bits = “0” to program, “1” to unprogram. Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1” = unprogrammed. Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed, “1” = unprogrammed. Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. Read Calibration Byte 0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte at address b. Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy. Wait until this bit returns to “0” before applying another command. Table 78. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation176 2543L–AVR–08/10 ATtiny2313 Serial Programming Characteristics Figure 80. Serial Programming Timing Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz Table 79. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 2.7V - 5.5V (Unless Otherwise Noted) Symbol Parameter Min Typ Max Units 1/tCLCL Oscillator Frequency (ATtiny2313L) 0 10 MHz tCLCL Oscillator Period (ATtiny2313L) 125 ns 1/tCLCL Oscillator Frequency (ATtiny2313, VCC = 4.5V - 5.5V) 0 20 MHz tCLCL Oscillator Period (ATtiny2313, VCC = 4.5V - 5.5V) 67 ns tSHSL SCK Pulse Width High 2 tCLCL* ns tSLSH SCK Pulse Width Low 2 tCLCL* ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid 100 ns MOSI MISO SCK t OVSH t SHSL t t SHOX SLSH t SLIV177 2543L–AVR–08/10 ATtiny2313 Electrical Characteristics Absolute Maximum Ratings* DC Characteristics Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins ................................ 200.0 mA TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) Symbol Parameter Condition Min. Typ.(2) Max. Units VIL Input Low Voltage except XTAL1 and RESET pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 0.2VCC(3) 0.3VCC(3) V VIH Input High-voltage except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(4) 0.6VCC(4) VCC +0.5 V VIL1 Input Low Voltage XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(3) V VIH1 Input High-voltage XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(4) 0.7VCC(4) VCC +0.5 V VIL2 Input Low Voltage RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC(3) V VIH2 Input High-voltage RESET pin VCC = 1.8V - 5.5V 0.9VCC(4) VCC +0.5 V VIL3 Input Low Voltage RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 0.2VCC(3) 0.3VCC(3) V VIH3 Input High-voltage RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(4) 0.6VCC(4) VCC +0.5 V VOL Output Low Voltage(5) (Port A, Port B, Port D) I OL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V 0.7 0.5 V V VOH Output High-voltage(6) (Port A, Port B, Port D) I OH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.2 2.5 V V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 µA IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 µA RRST Reset Pull-up Resistor 30 60 kΩ Rpu I/O Pin Pull-up Resistor 20 50 kΩ178 2543L–AVR–08/10 ATtiny2313 Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. 2. Typical values at +25°C. 3. “Max” means the highest value where the pin is guaranteed to be read as low. 4. “Min” means the lowest value where the pin is guaranteed to be read as high. 5. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 6. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. ICC Power Supply Current Active 1MHz, VCC = 2V 0.35 mA Active 4MHz, VCC = 3V 2 mA Active 8MHz, VCC = 5V 6 mA Idle 1MHz, VCC = 2V 0.08 0.2 mA Idle 4MHz, VCC = 3V 0.41 1 mA Idle 8MHz, VCC = 5V 1.6 3 mA Power-down mode WDT enabled, VCC = 3V < 3 6 µA WDT disabled, VCC = 3V < 0.5 2 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 < 10 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA t ACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V 750 500 ns TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued) Symbol Parameter Condition Min. Typ.(2) Max. Units179 2543L–AVR–08/10 ATtiny2313 External Clock Drive Waveforms Figure 81. External Clock Drive Waveforms External Clock Drive VIL1 VIH1 Table 80. External Clock Drive (Estimated Values) Symbol Parameter VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 0 4 0 10 0 20 MHz tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 μs tCHCL Fall Time 2.0 1.6 0.5 μs ΔtCLCL Change in period from one clock cycle to the next 2 2 2%180 2543L–AVR–08/10 ATtiny2313 Maximum Speed vs. VCC Maximum frequency is dependent on VCC. As shown in Figure 82 and Figure 83, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 82. Maximum Frequency vs. VCC, ATtiny2313V Figure 83. Maximum Frequency vs. VCC, ATtiny2313 10 MHz 4 MHz 1.8V 2.7V 5.5V Safe Operating Area 20 MHz 10 MHz 2.7V 4.5V 5.5V Safe Operating Area181 2543L–AVR–08/10 ATtiny2313 ATtiny2313 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 84. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA)182 2543L–AVR–08/10 ATtiny2313 Figure 85. Active Supply Current vs. Frequency (1 - 20 MHz) Figure 86. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 85 ˚C 25 ˚C -40 ˚C 0 1 2 3 4 5 6 7 8 9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA)183 2543L–AVR–08/10 ATtiny2313 Figure 87. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) Figure 88. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)184 2543L–AVR–08/10 ATtiny2313 Figure 89. Active Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz) Figure 90. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 0.5 MHz 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc (V) Icc (mA)185 2543L–AVR–08/10 ATtiny2313 Idle Supply Current Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) Figure 92. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Icc (m A) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Icc (mA)186 2543L–AVR–08/10 ATtiny2313 Figure 93. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Figure 94. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)187 2543L–AVR–08/10 ATtiny2313 Figure 95. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Figure 96. Idle Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 0.5 MHz 85 °C 25 °C -40 °C 0 0.05 0.1 0.15 0.2 0.25 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)188 2543L–AVR–08/10 ATtiny2313 Figure 97. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) Power-down Supply Current Figure 98. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (m A) POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C 0 0.25 0.5 0.75 1 1.25 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA)189 2543L–AVR–08/10 ATtiny2313 Figure 99. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) Standby Supply Current Figure 100. Standby Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 18 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA) STANDBY SUPPLY CURRENT vs. Vcc 455KHz Res 2MHz Xtal 2MHz Res 1MHz Res 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (m A)190 2543L–AVR–08/10 ATtiny2313 Pin Pull-up Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) IOP (uA ) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 VOP (V) IOP (uA)191 2543L–AVR–08/10 ATtiny2313 Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) IRESET (uA) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 85 °C -40 °C 25 °C 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 VRESET (V) IRESET (uA)192 2543L–AVR–08/10 ATtiny2313 Pin Driver Strength Figure 105. I/O Pin Source Current vs. Output Voltage (VCC = 5V) Figure 106. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 90 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 VOH (V) IOH (mA) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA)193 2543L–AVR–08/10 ATtiny2313 Figure 107. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) Figure 108. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 7 8 9 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) IOH (mA) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA)194 2543L–AVR–08/10 ATtiny2313 Figure 109. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) Figure 110. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL (V) IOL (mA)195 2543L–AVR–08/10 ATtiny2313 Figure 111. Reset I/O Pin Source Current vs. Output Voltage (VCC = 5V) Figure 112. Reset I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Current (mA) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 3 VOH (V) Current (m A)196 2543L–AVR–08/10 ATtiny2313 Figure 113. Reset I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 5V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Current (mA) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL (V) Current (mA)197 2543L–AVR–08/10 ATtiny2313 Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL (V) Current (mA) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL (V) Current (mA)198 2543L–AVR–08/10 ATtiny2313 Pin Thresholds and Hysteresis Figure 117. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) Figure 118. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V)199 2543L–AVR–08/10 ATtiny2313 Figure 119. Reset I/O Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) Figure 120. Reset I/O Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Threshold (V) RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Threshold (V)200 2543L–AVR–08/10 ATtiny2313 Figure 121. Reset I/O Input Pin Hysteresis vs. VCC Figure 122. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) RESET I/O INPUT PIN HYSTERESIS vs. Vcc 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (V) RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V)201 2543L–AVR–08/10 ATtiny2313 Figure 123. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) Figure 124. Reset Input Pin Hysteresis vs. VCC RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Threshold (V) RESET INPUT PIN HYSTERESIS vs. Vcc 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Input Hysteresis (V)202 2543L–AVR–08/10 ATtiny2313 BOD Thresholds and Analog Comparator Offset Figure 125. BOD Thresholds vs. Temperature (BOD Level is 4.3V) Figure 126. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.25 4.3 4.35 4.4 4.45 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Thres hol d (V ) Rising Vcc Falling Vcc BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.65 2.7 2.75 2.8 2.85 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Threshold (V) Rising Vcc Falling Vcc203 2543L–AVR–08/10 ATtiny2313 Figure 127. BOD Thresholds vs. Temperature (BOD Level is 1.8V) Internal Oscillator Speed Figure 128. Watchdog Oscillator Frequency vs. VCC BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V Rising Vcc Falling Vcc 1.78 1.8 1.82 1.84 1.86 1.88 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Threshold (V) WATCHDOG OSCILLATOR FREQUENCY vs. VCC 85 °C 25 °C -40 °C 0.095 0.096 0.097 0.098 0.099 0.1 0.101 0.102 0.103 0.104 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (M Hz)204 2543L–AVR–08/10 ATtiny2313 Figure 129. Watchdog Oscillator Frequency vs. Temperature Figure 130. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0.096 0.097 0.098 0.099 0.1 0.101 0.102 0.103 0.104 0.105 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) FRC (MHz) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) FRC (MHz )205 2543L–AVR–08/10 ATtiny2313 Figure 131. Calibrated 8 MHz RC Oscillator Frequency vs. VCC Figure 132. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc 85 °C 25 °C -40 °C 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 25 °C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 OSCCAL VALUE FRC (MHz)206 2543L–AVR–08/10 ATtiny2313 Figure 133. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature Figure 134. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 5.0 V 3.3 V 1.8 V 3.9 3.95 4 4.05 4.1 4.15 4.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) FRC (MHz) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc 85 °C 25 °C -40 °C 3.9 3.95 4 4.05 4.1 4.15 4.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz)207 2543L–AVR–08/10 ATtiny2313 Figure 135. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value Current Consumption of Peripheral Units Figure 136. Brownout Detector Current vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 25 °C 0 1 2 3 4 5 6 7 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 OSCCAL VALUE FRC (MHz ) BROWNOUT DETECTOR CURRENT vs. Vcc 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA)208 2543L–AVR–08/10 ATtiny2313 Figure 137. Analog Comparator Current vs. VCC Figure 138. Programming Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA) PROGRAMMING CURRENT vs. Vcc 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)209 2543L–AVR–08/10 ATtiny2313 Current Consumption in Reset and Reset Pulsewidth Figure 139. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Figure 140. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. Vcc 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Icc (mA) RESET SUPPLY CURRENT vs. Vcc 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Icc (mA)210 2543L–AVR–08/10 ATtiny2313 Figure 141. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. Vcc 85 °C 25 °C -40 °C 0 500 1000 1500 2000 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Pulsewidth (ns)211 2543L–AVR–08/10 ATtiny2313 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 8 0x3E (0x5E) Reserved – – – – – – – – 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 77 0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – – 60 0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – – 61 0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 78, 109 0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 78 0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN 155 0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 77 0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 53 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 37 0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 76 0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 77 0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 26 0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 73 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1BO – – WGM11 WGM10 104 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 107 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 108 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 108 0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 108 0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 108 0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 109 0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 109 0x27 (0x47) Reserved – – – – – – – – 0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 28 0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 109 0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 109 0x23 (0x43) GTCCR – – – – – – – PSR10 81 0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 108 0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 42 0x20 (0x40) PCMSK PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 61 0x1F (0x3F) Reserved – – – – – – – – 0x1E (0x3E) EEAR – EEPROM Address Register 16 0x1D (0x3D) EEDR EEPROM Data Register 17 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 17 0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 58 0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 58 0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 58 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 58 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 58 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 58 0x15 (0x35) GPIOR2 General Purpose I/O Register 2 21 0x14 (0x34) GPIOR1 General Purpose I/O Register 1 21 0x13 (0x33) GPIOR0 General Purpose I/O Register 0 21 0x12 (0x32) PORTD – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 58 0x11 (0x31) DDRD – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 58 0x10 (0x30) PIND – PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 58 0x0F (0x2F) USIDR USI Data Register 144 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 145 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 145 0x0C (0x2C) UDR UART Data Register (8-bit) 129 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 129 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 131 0x09 (0x29) UBRRL UBRRH[7:0] 133 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 149 0x07 (0x27) Reserved – – – – – – – – 0x06 (0x26) Reserved – – – – – – – – 0x05 (0x25) Reserved – – – – – – – – 0x04 (0x24) Reserved – – – – – – – – 0x03 (0x23) UCSRC – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 132 0x02 (0x22) UBRRH – – – – UBRRH[11:8] 133 0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 150 0x00 (0x20) Reserved – – – – – – – –212 2543L–AVR–08/10 ATtiny2313 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. 213 2543L–AVR–08/10 ATtiny2313 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1214 2543L–AVR–08/10 ATtiny2313 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1 V1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks215 2543L–AVR–08/10 ATtiny2313 Ordering Information Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 82 on page 180 and Figure 83 on page 180. 4. Code Indicators: – U: matte tin – R: tape & reel Speed (MHz)(3) Power Supply (V) Ordering Code(4) Package(2) Operation Range 10 1.8 - 5.5 ATtiny2313V-10PU ATtiny2313V-10SU ATtiny2313V-10SUR ATtiny2313V-10MU ATtiny2313V-10MUR 20P3 20S 20S 20M1 20M1 Industrial (-40°C to +85°C)(1) 20 2.7 - 5.5 ATtiny2313-20PU ATtiny2313-20SU ATtiny2313-20SUR ATtiny2313-20MU ATtiny2313-20MUR 20P3 20S 20S 20M1 20M1 Industrial (-40°C to +85°C)(1) Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)216 2543L–AVR–08/10 ATtiny2313 Packaging Information 20P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) 20P3 C 1/12/04 PIN 1 E1 A1 B E B1 C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 25.493 – 25.984 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 217 2543L–AVR–08/10 ATtiny2313 20S218 2543L–AVR–08/10 ATtiny2313 20M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 A 10/27/04 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 0.20 REF b 0.18 0.23 0.30 D 4.00 BSC D2 2.45 2.60 2.75 E 4.00 BSC E2 2.45 2.60 2.75 e 0.50 BSC L 0.35 0.40 0.55 SIDE VIEW Pin 1 ID Pin #1 Notch (0.20 R) BOTTOM VIEW TOP VIEW Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D E e A2 A1 A D2 E2 0.08 C L 1 2 3 b 1 2 3219 2543L–AVR–08/10 ATtiny2313 Errata The revision in this section refers to the revision of the ATtiny2313 device. ATtiny2313 Rev C No known errata ATtiny2313 Rev B • Wrong values read after Erase Only operation • Parallel Programming does not work • Watchdog Timer Interrupt disabled • EEPROM can not be written below 1.9 volts 1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. Parallel Programming does not work Parallel Programming is not functioning correctly. Because of this, reprogramming of the device is impossible if one of the following modes are selected: – In-System Programming disabled (SPIEN unprogrammed) – Reset Disabled (RSTDISBL programmed) Problem Fix/Workaround Serial Programming is still working correctly. By avoiding the two modes above, the device can be reprogrammed serially. 3. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. 4. EEPROM can not be written below 1.9 volts Writing the EEPROM at VCC below 1.9 volts might fail. Problem fix / Workaround Do not write the EEPROM when VCC is below 1.9 volts. ATtiny2313 Rev A Revision A has not been sampled.220 2543L–AVR–08/10 ATtiny2313 Datasheet Revision History Please note that the referring page numbers in this section refer to the complete document. Rev. 2543L - 8/10 Added tape and reel part numbers in “Ordering Information” on page 215. Removed text “Not recommended for new design” from cover page. Fixed literature number mismatch in Datasheet Revision History. Rev. 2543K - 03/10 Rev. 2543J - 11/09 Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06 Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05 1. Added device Rev C “No known errata” in “Errata” on page 219. 1. Updated template 2. Changed device status to “Not recommended for new designs.” 3. Updated “Stack Pointer” on page 11. 4. Updated Table “Sleep Mode Select” on page 30. 5. Updated “Calibration Byte” on page 160 (to one byte of calibration data) 1. Updated typos. 2. Updated Figure 1 on page 2. 3 Added “Resources” on page 6. 4. Updated “Default Clock Source” on page 23. 5. Updated “128 kHz Internal Oscillator” on page 28. 6. Updated “Power Management and Sleep Modes” on page 30 7. Updated Table 3 on page 23,Table 13 on page 30, Table 14 on page 31, Table 19 on page 42, Table 31 on page 60, Table 79 on page 176. 8. Updated “External Interrupts” on page 59. 9. Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page 61. 10. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 149. 11. Updated “Calibration Byte” on page 160. 12. Updated “DC Characteristics” on page 177. 13. Updated “Register Summary” on page 211. 14. Updated “Ordering Information” on page 215. 15. Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to OCF1x. 1. Updated Table 6 on page 25, Table 15 on page 34, Table 68 on page 160 and Table 80 on page 179. 2. Changed CKSEL default value in “Default Clock Source” on page 23 to 8 MHz.221 2543L–AVR–08/10 ATtiny2313 Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04 Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04 Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04 Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04 3. Updated “Programming the Flash” on page 165, “Programming the EEPROM” on page 167 and “Enter Programming Mode” on page 163. 4. Updated “DC Characteristics” on page 177. 5. MLF option updated to “Quad Flat No-Lead/Micro Lead Frame (QFN/MLF)” 1. Updated “Features” on page 1. 2. Updated “Pinout ATtiny2313” on page 2. 3. Updated “Ordering Information” on page 215. 4. Updated “Packaging Information” on page 216. 5. Updated “Errata” on page 219. 1. Updated “Features” on page 1. 2. Updated “Alternate Functions of Port B” on page 53. 3. Updated “Calibration Byte” on page 160. 4. Moved Table 69 on page 160 and Table 70 on page 160 to “Page Size” on page 160. 5. Updated “Enter Programming Mode” on page 163. 6. Updated “Serial Programming Algorithm” on page 173. 7. Updated Table 78 on page 174. 8. Updated “DC Characteristics” on page 177. 9. Updated “ATtiny2313 Typical Characteristics” on page 181. 10. Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and EEWE to EEPE in the document. 1. Speed Grades changed - 12MHz to 10MHz - 24MHz to 20MHz 2. Updated Figure 1 on page 2. 3. Updated “Ordering Information” on page 215. 4. Updated “Maximum Speed vs. VCC” on page 180. 5. Updated “ATtiny2313 Typical Characteristics” on page 181. 1. Updated Table 2 on page 23. 2. Replaced “Watchdog Timer” on page 39. 3. Added “Maximum Speed vs. VCC” on page 180. 4. “Serial Programming Algorithm” on page 173 updated. 5. Changed mA to µA in preliminary Figure 136 on page 207. 6. “Ordering Information” on page 215 updated. MLF package option removed222 2543L–AVR–08/10 ATtiny2313 Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03 Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03 7. Package drawing “20P3” on page 216 updated. 8. Updated C-code examples. 9. Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable. 1. Updated “Calibrated Internal RC Oscillator” on page 25. 1. Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in “Features” on page 1. 2. Updated “Pin Configurations” on page 2. 3. Updated Table 15 on page 34 and Table 80 on page 179. 4. Updated item 5 in “Serial Programming Algorithm” on page 173. 5. Updated “Electrical Characteristics” on page 177. 6. Updated Figure 82 on page 180 and added Figure 83 on page 180. 7. Changed SFIOR to GTCCR in “Register Summary” on page 211. 8. Updated “Ordering Information” on page 215. 9. Added new errata in “Errata” on page 219.i 2543L–AVR–08/10 ATtiny2313 Table of Contents Features 1 Pin Configurations 2 General Information 6 Resources 6 Code Examples 6 Disclaimer 6 AVR CPU Core 7 Introduction 7 Architectural Overview 7 ALU – Arithmetic Logic Unit 8 Status Register 8 General Purpose Register File 9 Instruction Execution Timing 11 Reset and Interrupt Handling 12 AVR ATtiny2313 Memories 14 In-System Reprogrammable Flash Program Memory 14 EEPROM Data Memory 16 I/O Memory 20 System Clock and Clock Options 22 Clock Systems and their Distribution 22 Clock Sources 23 Default Clock Source 23 Crystal Oscillator 23 Calibrated Internal RC Oscillator 25 System Clock Prescalar 28 Power Management and Sleep Modes 30 Idle Mode 30 Power-down Mode 31 Standby Mode 31 Minimizing Power Consumption 31 System Control and Reset 33 Interrupts 44 Interrupt Vectors in ATtiny2313 44 I/O-Ports 46 Introduction 46ii 2543L–AVR–08/10 ATtiny2313 Ports as General Digital I/O 47 Alternate Port Functions 51 External Interrupts 59 Pin Change Interrupt Timing 59 8-bit Timer/Counter0 with PWM 62 Overview 62 Timer/Counter Clock Sources 63 Counter Unit 63 Output Compare Unit 64 Compare Match Output Unit 65 Modes of Operation 66 Timer/Counter Timing Diagrams 71 Timer/Counter0 and Timer/Counter1 Prescalers 80 16-bit Timer/Counter1 82 Overview 82 Accessing 16-bit Registers 84 Counter Unit 88 Input Capture Unit 89 Output Compare Units 90 Modes of Operation 94 USART 111 Overview 111 Clock Generation 112 Frame Formats 115 USART Initialization 116 Asynchronous Data Reception 124 Universal Serial Interface – USI 138 Overview 138 Functional Descriptions 139 Alternative USI Usage 144 USI Register Descriptions 144 Analog Comparator 149 debugWIRE On-chip Debug System 151 Features 151 Overview 151 Physical Interface 151 Software Break Points 152 Limitations of debugWIRE 152iii 2543L–AVR–08/10 ATtiny2313 debugWIRE Related Register in I/O Memory 152 Self-Programming the Flash 153 Memory Programming 158 Program And Data Memory Lock Bits 158 Signature Bytes 160 Calibration Byte 160 Page Size 160 Parallel Programming Parameters, Pin Mapping, and Commands 161 Serial Programming Pin Mapping 163 Parallel Programming 163 Serial Downloading 172 External Clock Drive 179 ATtiny2313 Typical Characteristics 181 Errata 219 ATtiny2313 Rev C 219 ATtiny2313 Rev B 219 ATtiny2313 Rev A 219 Datasheet Revision History 220 Rev. 2543L - 8/10 220 Rev. 2543K - 03/10 220 Rev. 2543J - 11/09 220 Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06 220 Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05 220 Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04 221 Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04 221 Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04 221 Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04 221 Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03 222 Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03 2222543L–AVR–08/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. AVR172: Sensorless Commutation of Brushless DC Motor (BLDC) using ATmega32M1 and ATAVRMC320 Features • Robust sensorless commutation control • Ramp-up sequence References [1] ATmega32M1 Data sheet [2] AVR194: Brushless DC Motor Control using ATmega32M1 [3] AVR430: MC300 Hardware User Guide [4] AVR470: MC310 User Guide [5] AVR471: MC320 Getting Started Guide [6] AVR928: Sensorless methods to drive BLDC motors 1 Introduction This application note describes how to implement a sensorless commutation of BLDC motors with the ATAVRMC320 development kit. The ATmega32M1 is equipped with integrated peripherals that reduce the number of external components required in a BLDC application. The ATmega32M1 is suitable for sensorless commutation and for commutation with Hall sensors as well, but this application note focuses on the sensorless commutation. The AVR928 Application Note describes the theory of the sensorless control method and must be carefully read first. 8-bit Microcontrollers Application Note Rev. 8306B-AVR-05/10 2 AVR172 8306B-AVR-05/10 2 Hardware The hardware includes the ATAVRMC310 and ATAVRMC300 boards which are the two parts of the ATAVRMC320 Starter kit. Please refer to the ATAVRMC300 and ATAVRMC310 user guides : - AVR430: MC300 Hardware User Guide - AVR470: MC310 Hardware User Guide 2.1 MC310 jumpers setting The AVR172 firmware has been developed with the following jumper settings: Table 2-1.ATAVRMC310 jumpers setting for sensorless control Designator Setting Function J5 Vm connect PB4 to Vm’ (motor voltage measurement if necessary) J6 PFC OC Connect to overcurrent signal J7 none used by CAN applications J8 ShCo connect PC5 to ShCo for current measurement J9 GNDm connect PC4 to GNDm for current measurement J12 TxD connect PD3 to the RS232 driver MOSI A Connect PD3 to ISP connector (for ISP use) RxDUSB Connect PD3 to RxD1 (for USB interface use) J13 RxD connect PD4 to the RS232 driver SCK Connect PD3 to ISP connector (for ISP use) TxDUSB Connect PD3 to RxD1 (for USB interface use) J15 none used by CAN application to add a termination resistor J21 Cmp- connect ACMP0- to V+W bemf conditioning J22 Cmp+ connect ACMP0+ to U bemf conditioning J23 Cmp- connect ACMP1- to U+W bemf conditioning J24 Cmp+ connect ACMP1+ to V bemf conditioning J25 Cmp- connect ACMP2- to U+V bemf conditioning J26 Cmp+ connect ACMP2+ to W bemf conditioning J28 VCC supply the on board USB dongle from the board power supply See also following picture of MC310 Jumpers configurations : AVR172 3 8306B-AVR-05/10 Figure 1. MC310 Jumpers configuration 2.2 MC300 jumper settings Table 2-1. ATAVRMC300 jumpers setting for sensorless control Designator Setting Function J2 none provide +5V to supply the ATAVRMC310 board On ATAVRMC300, Vm and Vin connectors can be supplied from the same +12V/7A power supply. Nevertheless a separate +12V/1A can also be used to supply the Vin (processor supply voltage). 2.3 Power-supply This firmware example has been configured according to a power-supply Vm=12V. This power-supply must be able to provide up to 4A output current. 2.4 Motor The BLDC motor provided inside MC320 and MC300 Motor Control Kit has the following characteristics: Manufacturer : TECMOTION Number of phases : 3 Number of poles : 8 (4 pairs) Rated voltage : 24V Rated speed : 4000 rpm Rated torque : 62.5 Nm Torque constant : 35 Nm/A = k_tau4 AVR172 8306B-AVR-05/10 Line to Line Resistance : 1.8 ohm = R Back EMF : 3.66 V/Krpm = k_e Peak current : 5.4A As Vm=12V, the rated speed will be 2000 rpm. 2.5 ATmega32M1 Configuration ATmega32M1 must be programmed to run at 16MHz using PLL (set corresponding Fuse bits). The CKDIV8 fuse must be disabled. Extended/High/Low Fuses configurations are : FF/DF/F3 2.6 Technical Advices 2.6.1 Disconnecting the BLDC Motor The BLDC motor must not be disconnected while it is running or while its coils carry current. It is allowed to disconnect a BLDC motor if the PWM duty cycle is 0% and the rotor is at rest so that no current is driven through the coils. Be careful, when stopping the power supply or PWM, a BLDC motor with a high moment of inertia is able to run for a relatively long time. 2.6.2 Ground and Power Wirings One design its own board has to take care of the ground wiring and power wiring. The power supply of the processor and additional signal conditioning components (e.g. additional fast comparators, operational amplifiers, …) has to be decoupled from the motor power supply. The ground connection has to be of low resistance and low inductance to prevent against voltage drop and noise due to high currents. A ground plane within a multi layer PCB is recommended for proper operation. 3 Firmware The example firmware is based on the Sensorless method described in AVR928 Application Note. It is operating in sensorless mode using the ATmega32M1 internal comparators. Hall sensor wires of the BLDC motor of the kit can remain unconnected. The source file directory embeds an html documentation which can be opened through the readme.html file. The theory of the different tasks has been detailed in AVR928. The application to ATmega32M1 is detailed in following sections. 3.1 Main Flow chart The firmware main flowchart is described below : AVR172 5 8306B-AVR-05/10 Figure 2. Main flow chart The tasks are scheduled thanks to the g_tick produced each 1.024ms with Timer0. 6 AVR172 8306B-AVR-05/10 3.2 MS_ALIGN phase The ALIGN phase forces the motor at a specific position. The time of this phase is controlled with ALIGN_TIME constant which is the ru_period_counter initial value (200 for MC310 motor). 3.3 RAMP_UP phase The ramp-up charateristics (duty-cycles and times) are stored in two tables: • ramp_up_duty_table[] : which provides the duty_cycle of the step • ramp_up_time_table[] : which provides the length of the step (ru_step_length) These two tables are specific to the motor and the application. The scanning of the step sequences and the monitoring of the step length are achieved thanks to three independant counters : - ru_step_length_cntr : which counts the commutation time (up to ru_step_length variable) - ru_period_counter : which counts the step length (up to RAMP_UP_PERIOD constant) - ramp_up_index : which counts the step numbers (up to RAMP_UP_INDEX_MAX constant) The figure below provides a waveform of steps timing : Figure 3. Steps timing AVR172 7 8306B-AVR-05/10 3.3.1 Time of steps The step time is RAMP_UP_PERIOD = 50ms. 3.3.2 Number of steps The parameter : RAMP_UP_INDEX_MAX = 9, defines 10 steps ramp up. 3.3.3 Parameters tables In firmware example, the tables have been defined according to the characteristics of the motor provided in the kit (see parameters in 2.4 Motor section) : ramp_up_time_table[] = {26,23,20,17,14,11,8,5,3,2,2}; ramp_up_duty_table[] = {122,124,126,129,131,133,135,137,140,143,145}; 3.3.4 Sp1/pwm1 The usual parameters described in AVR928 Application Note are: • Pwm1 = 50% • Sp1 = Sp_max/60 The parameters defined with MC310 Tecmotion motor are: • Pwm1 = 48% (= 122/256) • Sp1 : Sp1 is defined thanks to the initialization value of ru_step_length : ru_step_length = RAMP_UP_STEP_MAX = 40 This variable determines one commutation each 40ms. So an electrical rotation time is 120ms. As the motor has 4 pairs of poles, the mechanical rotation time is 480ms. So the rotation speed is 60/0.48 = 125 rpm. So Sp1 = Sp_max/32. The second value of ru_step_length is 26 in the time table. It defines the following commutation time. 3.3.5 Sp2/pwm2 The theorical parameters described in AVR928 Application Note are: • Pwm2 = 60% • Sp2 = Sp_max/6 = Sp1 / 10 The parameters defined with Tecmotion motor are: • Pwm2 = 57% (= 145/256) • Sp2 : Sp2 is defined thanks to the last value of ru_step_length : 2 This variable determines one commutation each 4ms. So an electrical rotation time is 12ms. As the motor has 4 pairs of poles, the mechanical rotation time is 48ms. So the rotation speed is 60/0.048 = 1250 rpm. So Sp2 = Sp_max/3.2. 8 AVR172 8306B-AVR-05/10 This confirms also the usual ratio = 10 between Sp1 and Sp2 which is defined in AVR498 Application Note. 3.4 LAST_RAMP_UP phase To avoid a shorten last step, this phase monitors the last ramp-up step to guarantee it is ended properly before running in closed loop. 3.5 RUNNING Phase 3.5.1 Closed-loop block diagram The Running phase is a sensorless closed loop which block diagram is following : Figure 4. Closed-loop block diagram AVR172 9 8306B-AVR-05/10 3.5.2 Running flowchart The flowchart is following : Figure 5. Closed-loop flowchart • Motor_state is kept equal to MS_RUNNING mci_set_ref_speed() function updates the speed setpoint according to the potentiometer adjustment or the speed command received on serial transmission. In mc_regulation_loop() function, duty_cycle_reference is the duty_cycle variable which controls the PWM generator. This variable is the result of following functions : • In OPEN_LOOP: mci_set_ref_speed() function • In SPEED_LOOP: 10 AVR172 8306B-AVR-05/10 mc_control_speed(2*mci_get_ref_speed()) duty-cycle_reference is calculated from ref_speed and from monitored mci_get_measured_speed() measured_speed = (KSPEED * 4) / mci_measured_period with mci_measured_period calculated in the Interrupt vector of Analog Comparator 1. This interrupt uses Timer 0 to compute the period. • In CURRENT_LOOP : mc_control_current(mc_get_potentiometer_value() 3.5.3 Sensorless Detection and Commutation Management The analog comparators 0, 1 and 2 are used to detect the zero crossing of the U, V and W phases. The timer 1 is used to monitor the time between two consecutive zero crossings. This time corresponds to one sector of the electrical rotation of the motor. It equals 60° of the entire electrical period of the motor. When a zero crossing event occurs, the timer 1 value is stored. Then this value is divided by 2 (providing the 30° time) and loaded into the Compare A register of timer 1. Then this value is added to the half of itself to provide the 45° time and loaded into the Compare B register of timer 1. The timer 1 compare A event occurs 30° after the zero crossing. It activates the next commutation state and masks the zero crossing to avoid the discharge of the inductance (demagnetization) pulse generated at the end of a step when the active switches are released. Due to the inductance of the motor coils, a voltage equals to -Ldi/dt is generated, the demagnetization is done through the diodes of the power bridge. The timer 1 compare B event releases the zero crossing mask : enables the comparator n interrupt according to the motor_step variable. This Timer1 interrupt provides the demagnetization mask delay. AVR172 11 8306B-AVR-05/10 4 RS232 Communication with firmware 4.1 Connecting ATAVRMC310 to use the RS232 interface Connect PC com port to the ATAVRMC310 RS232 connector through a direct cable. The serial configuration is: • 38400 bauds, • 8 bit data bit, • 1 stop bit, • no handshake, 4.2 PC applications User can communicate with firmware through RS232 with usual PC serial communication applications (i.e. Hyperterminal) or the Atmel “Motor Control Center” application which can be downloaded from Atmel web at url : http://www.atmel.com 4.2.1 PC Terminal : RS232 Messages and Commands At power up the following welcome message is received on terminal : “ATMEL Motor Control Interface”. The following commands can be sent to the firmware: Table 2-1. List of commands Command Action ru Run motor st Stop Motor help Gives help fw Set direction to Forward bw Set direction to Backward ss Set Speed (followed with speed value) gi Get ID g0 Get Status 0 g1 Get Status 1 4.2.2 Motor Control Center The User Guide is available in Install directory at URL : C:\Program Files\Atmel\Motor Control Center\help\Overview.htm The AVR172 Target must be selected first to get the right configuration : To select a target, execute the File > Select Target command or click the button in the toolbar. The following dialog pops up: 12 AVR172 8306B-AVR-05/10 Figure 6. Motor Control Center Interface 5 USB communication Communication can be achieved from PC to USB connector of MC310 board. The AVR470, MC310 Hardware User Guide details the configuration to be achieved. Communication port becomes a Virtual Com port. Same tools as described in section 4 (RS232 Communication with firmware), can be used through this Virtual Com port. 8306B-AVR-05/10 Disclaimer Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Product Contact Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Web Site http://www.atmel.com/ Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Request www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel® , Atmel logo and combinations thereof, AVR® , AVR® logo and others, are the registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 1. Product profile 1.1 General description NPN/NPN general-purpose transistor pair in a small SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Low collector capacitance ■ Low collector-emitter saturation voltage ■ Closely matched current gain ■ Reduces number of components and board space ■ No mutual interference between the transistors ■ AEC-Q101 qualified 1.3 Applications ■ General-purpose switching and amplification 1.4 Quick reference data BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor Rev. 01 — 17 July 2009 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor VCEO collector-emitter voltage open base - - 65 V IC collector current - - 100 mA hFE DC current gain VCE = 5 V; IC = 2 mA 200 300 450BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 2 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 emitter TR1 2 base TR1 3 collector TR2 4 emitter TR2 5 base TR2 6 collector TR1 1 3 2 6 5 4 sym020 1 2 3 6 5 TR1 TR2 4 Table 3. Ordering information Type number Package Name Description Version BC846DS SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 Table 4. Marking codes Type number Marking code BC846DS ZK Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor VCBO collector-base voltage open emitter - 80 V VCEO collector-emitter voltage open base - 65 V VEBO emitter-base voltage open collector - 6 V IC collector current - 100 mA ICM peak collector current single pulse; tp ≤ 1 ms - 200 mA IBM peak base current single pulse; tp ≤ 1 ms - 200 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Per device Ptot total power dissipation Tamb ≤ 25 °C [1] - 380 mWBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 3 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Tj junction temperature - 150 °C Tamb ambient temperature −55 +150 °C Tstg storage temperature −65 +150 °C FR4 PCB, standard footprint Fig 1. Per device: Power derating curve SOT457 (SC-74) Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb (°C) −75 175 −25 25 75 125 006aab621 200 300 100 400 500 Ptot (mW) 0 Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/W Rth(j-sp) thermal resistance from junction to solder point - - 250 K/W Per device Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 328 K/WBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 4 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 7. Characteristics FR4 PCB, standard footprint Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab622 10−5 10 10 −2 10−4 102 10−1 tp (s) 10−3 103 1 102 10 103 Zth(j-a) (K/W) 1 δ = 1 0.75 0.50 0.33 0.10 0.05 0.02 0.01 0 0.20 Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor ICBO collector-base cut-off current VCB = 50 V; IE = 0 A - - 15 nA VCB = 30 V; IE = 0 A; Tj = 150 °C --5 µA IEBO emitter-base cut-off current VEB = 6 V; IC = 0 A - - 100 nA hFE DC current gain VCE =5V IC = 10 µA - 280 - IC = 2 mA 200 300 450 VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - 55 100 mV IC = 100 mA; IB = 5 mA - 200 300 mV VBEsat base-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - 755 850 mV IC = 100 mA; IB = 5 mA - 1000 - mV VBE base-emitter voltage VCE =5V IC = 2 mA 580 650 700 mV IC = 10 mA - - 770 mVBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 5 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - 1.9 - pF Ce emitter capacitance VEB = 0.5 V; IC = ic = 0 A; f = 1 MHz - 11 - pF fT transition frequency VCE = 5 V; IC = 10 mA; f = 100 MHz 100 - - MHz NF noise figure VCE = 5 V; IC = 0.2 mA; RS =2kΩ; f = 10 Hz to 15.7 kHz - 1.9 - dB VCE = 5 V; IC = 0.2 mA; RS =2kΩ; f = 1 kHz; B = 200 Hz - 3.1 - dB Table 7. Characteristics …continued Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCE =5V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 3. Per transistor: DC current gain as a function of collector current; typical values Fig 4. Per transistor: Collector current as a function of collector-emitter voltage; typical values 006aaa533 200 400 600 hFE 0 IC (mA) 10−2 103 102 10−1 1 10 (3) (1) (2) 006aaa532 VCE (V) 0 10 2 4 6 8 0.08 0.12 0.04 0.16 0.20 IC (A) 0 IB (mA) = 4.50 2.70 3.15 4.05 3.60 0.45 0.90 1.35 1.80 2.25BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 6 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor VCE = 5 V; Tamb = 25 °C IC/IB = 20 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 5. Per transistor: Base-emitter voltage as a function of collector current; typical values Fig 6. Per transistor: Base-emitter saturation voltage as a function of collector current; typical values IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C VCE = 5 V; Tamb = 25 °C Fig 7. Per transistor: Collector-emitter saturation voltage as a function of collector current; typical values Fig 8. Per transistor: Transition frequency as a function of collector current; typical values 006aaa536 0.6 0.8 1 VBE (V) 0.4 IC (mA) 10−1 103 102 1 10 006aaa534 IC (mA) 10−1 103 102 1 10 0.5 0.9 1.3 0.3 0.7 1.1 VBEsat (V) 0.1 (1) (2) (3) 006aaa535 1 10−1 10 VCEsat (V) 10−2 IC (mA) 10−1 103 102 1 10 (1) (2) (3) 006aaa537 IC (mA) 1 102 10 102 103 fT (MHz) 10BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 7 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor f = 1 MHz; Tamb = 25 °C f = 1 MHz; Tamb = 25 °C Fig 9. Per transistor: Collector capacitance as a function of collector-base voltage; typical values Fig 10. Per transistor: Emitter capacitance as a function of emitter-base voltage; typical values VCB (V) 0 10 2 4 6 8 006aab620 2 4 6 Cc (pF) 0 006aaa539 VEB (V) 0 6 2 4 9 11 7 13 15 Ce (pF) 5BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 8 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. [2] T1: normal taping [3] T2: reverse taping Fig 11. Package outline SOT457 (SC-74) Dimensions in mm 04-11-08 3.0 2.5 1.7 1.3 3.1 2.7 pin 1 index 1.9 0.26 0.10 0.40 0.25 0.95 1.1 0.9 0.6 0.2 1 3 2 6 5 4 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 BC846DS SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 9 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 11. Soldering Fig 12. Reflow soldering footprint SOT457 (SC-74) Fig 13. Wave soldering footprint SOT457 (SC-74) solder lands solder resist occupied area solder paste sot457_fr 3.45 1.95 3.3 2.825 0.45 (6×) 0.55 (6×) 0.7 (6×) 0.8 (6×) 2.4 0.95 0.95 Dimensions in mm sot457_fw 5.3 5.05 1.45 (6×) 0.45 (2×) 1.5 (4×) 2.85 1.475 1.475 solder lands solder resist occupied area preferred transport direction during soldering Dimensions in mmBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 10 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes BC846DS_1 20090717 Product data sheet - -BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 11 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 July 2009 Document identifier: BC846DS_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 8 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 Packing information. . . . . . . . . . . . . . . . . . . . . . 8 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Contact information. . . . . . . . . . . . . . . . . . . . . 11 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1. Product profile 1.1 General description Planar Maximum Efficiency General Application (MEGA) Schottky barrier rectifier with an integrated guard ring for stress protection, encapsulated in a SOD128 small and flat lead Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Average forward current: IF(AV) ≤ 1 A ■ Reverse voltage: VR ≤ 30 V ■ Low forward voltage ■ High power capability due to clip-bond technology ■ AEC-Q101 qualified ■ Small and flat lead SMD plastic package 1.3 Applications ■ Low voltage rectification ■ High efficiency DC-to-DC conversion ■ Switch Mode Power Supply (SMPS) ■ Reverse polarity protection ■ Low power consumption applications 1.4 Quick reference data [1] Device mounted on a ceramic Printed-Circuit Board (PCB), Al2O3, standard footprint. PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier Rev. 01 — 30 December 2008 Product data sheet Table 1. Quick reference data Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IF(AV) average forward current square wave; δ = 0.5; f = 20 kHz Tamb ≤ 130 °C [1] - - 1A Tsp ≤ 145 °C - - 1A VR reverse voltage - - 30 V VF forward voltage IF = 1 A - 320 360 mV IR reverse current VR = 30 V - 0.6 1.5 mAPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 2 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 2. Pinning information [1] The marking bar indicates the cathode. 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 cathode [1] 2 anode 1 2 sym001 1 2 Table 3. Ordering information Type number Package Name Description Version PMEG3010EP - plastic surface-mounted package; 2 leads SOD128 Table 4. Marking codes Type number Marking code PMEG3010EP A1 Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VR reverse voltage Tj = 25 °C - 30 V IF(AV) average forward current square wave; δ = 0.5; f = 20 kHz Tamb ≤ 130 °C [1] - 1A Tsp ≤ 145 °C - 1A IFSM non-repetitive peak forward current square wave; tp = 8 ms [2] - 50 A Ptot total power dissipation Tamb ≤ 25 °C [3][4] - 625 mW [3][5] - 1050 mW [3][1] - 2100 mWPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 3 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier [1] Device mounted on a ceramic PCB, Al2O3, standard footprint. [2] Tj = 25 °C prior to surge. [3] Reflow soldering is the only recommended soldering method. [4] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [5] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. 6. Thermal characteristics [1] For Schottky barrier diodes thermal runaway has to be considered, as in some applications the reverse power losses PR are a significant part of the total power losses. [2] Reflow soldering is the only recommended soldering method. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. [5] Device mounted on a ceramic PCB, Al2O3, standard footprint. [6] Soldering point of cathode tab. Tj junction temperature - 150 °C Tamb ambient temperature −55 +150 °C Tstg storage temperature −65 +150 °C Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1][2] [3] - - 200 K/W [4] - - 120 K/W [5] - - 60 K/W Rth(j-sp) thermal resistance from junction to solder point [6] - - 12 K/WPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 4 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier FR4 PCB, standard footprint Fig 1. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values FR4 PCB, mounting pad for cathode 1 cm2 Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab296 10 1 102 103 Zth(j-a) (K/W) 10−1 tp (s) 10−3 102 103 10 1 10 −2 10−1 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 0.1 0.05 0.02 0.01 0 006aab297 10 1 102 103 Zth(j-a) (K/W) 10−1 tp (s) 10−3 102 103 10 1 10 −2 10−1 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 0.1 0.05 0.02 0.01 0PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 5 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 7. Characteristics Ceramic PCB, Al2O3, standard footprint Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab298 10 1 102 103 Zth(j-a) (K/W) 10−1 tp (s) 10−3 102 103 10 1 10 −2 10−1 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 0.1 0.05 0.02 0.01 0 Table 7. Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VF forward voltage IF = 0.1 A - 230 260 mV IF = 0.5 A - 280 310 mV IF = 1 A - 320 360 mV IR reverse current VR = 5 V - 55 - µA VR = 30 V - 0.6 1.5 mA Cd diode capacitance f = 1 MHz VR = 1 V - 170 - pF VR = 10 V - 60 - pFPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 6 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier (1) Tj = 150 °C (2) Tj = 125 °C (3) Tj = 85 °C (4) Tj = 25 °C (5) Tj = −40 °C (1) Tj = 125 °C (2) Tj = 85 °C (3) Tj = 25 °C (4) Tj = −40 °C Fig 4. Forward current as a function of forward voltage; typical values Fig 5. Reverse current as a function of reverse voltage; typical values f = 1 MHz; Tamb = 25 °C Fig 6. Diode capacitance as a function of reverse voltage; typical values 006aab299 10−2 10−3 1 10−1 10 IF (A) 10−4 VF (V) 0 0.8 0.2 0.4 0.6 (1) (2) (3) (4) (5) 006aab300 VR (V) 0 30 10 20 1 10−1 10−2 10−3 10−4 10−5 10−6 IR (A) 10−7 (1) (2) (3) (4) VR (V) 0 30 10 20 006aab301 100 200 300 Cd (pF) 0PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 7 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier Tj = 150 °C (1) δ = 0.1 (2) δ = 0.2 (3) δ = 0.5 (4) δ = 1 Tj = 125 °C (1) δ = 1 (2) δ = 0.9 (3) δ = 0.8 (4) δ = 0.5 Fig 7. Average forward power dissipation as a function of average forward current; typical values Fig 8. Average reverse power dissipation as a function of reverse voltage; typical values FR4 PCB, standard footprint Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz FR4 PCB, mounting pad for cathode 1 cm2 Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz Fig 9. Average forward current as a function of ambient temperature; typical values Fig 10. Average forward current as a function of ambient temperature; typical values 006aab302 IF(AV) (A) 0 1.5 0.5 1 0.2 0.1 0.3 0.4 PF(AV) (W) 0 (1) (2) (3) (4) VR (V) 0 30 10 20 006aab303 3.5 PR(AV) (W) 0 0.5 1 1.5 2 2.5 3 (1) (2) (3) (4) Tamb (°C) 0 75 25 150 50 100 125 175 006aab304 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4) Tamb (°C) 0 75 25 150 50 100 125 175 006aab305 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4)PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 8 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier Ceramic PCB, Al2O3, standard footprint Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz Fig 11. Average forward current as a function of ambient temperature; typical values Fig 12. Average forward current as a function of solder point temperature; typical values Tamb (°C) 0 75 25 150 50 100 125 175 006aab306 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4) Tsp (°C) 0 75 25 150 50 100 125 175 006aab307 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4)PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 9 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 8. Test information The current ratings for the typical waveforms as shown in Figure 9, 10, 11 and 12 are calculated according to the equations: with IM defined as peak current, at DC, and with IRMS defined as RMS current. 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline Fig 13. Duty cycle definition t1 t2 P t 006aaa812 duty cycle δ = t1 t2 IF AV ( ) = IM × δ IRMS IF AV ( ) = IRMS = IM × δ Fig 14. Package outline SOD128 Dimensions in mm 07-09-12 1.1 0.9 0.22 0.10 0.6 0.3 5.0 4.4 4.0 3.6 1.9 1.6 2.7 2.3 1 2PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 10 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 10. Packing information [1] For further information and the availability of packing methods, see Section 14. 11. Soldering Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 PMEG3010EP SOD128 4 mm pitch, 12 mm tape and reel -115 Reflow soldering is the only recommended soldering method. Fig 15. Reflow soldering footprint SOD128 solder lands solder resist occupied area solder paste 3.4 2.5 2.1 (2×) 1.9 (2×) 4.4 4.2 6.2 1.2 (2×) 1.4 (2×) sod128_fr Dimensions in mmPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 11 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PMEG3010EP_1 20081230 Product data sheet - -PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 12 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 December 2008 Document identifier: PMEG3010EP_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 9 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Packing information. . . . . . . . . . . . . . . . . . . . . 10 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Contact information. . . . . . . . . . . . . . . . . . . . . 12 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1. Product profile 1.1 General description Planar Schottky barrier single diode with an integrated guard ring for stress protection, encapsulated in a SOD323F (SC-90) very small and flat lead Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Low forward voltage ■ Very small and flat lead SMD plastic package ■ Low capacitance ■ Flat leads: excellent coplanarity and improved thermal behavior 1.3 Applications ■ Voltage clamping ■ Line termination ■ Reverse polarity protection 1.4 Quick reference data [1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02. BAT54J Schottky barrier single diode Rev. 01 — 8 March 2007 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit IF forward current - - 200 mA VR reverse voltage - - 30 V VF forward voltage IF = 1 mA [1] - - 320 mVBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 2 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 2. Pinning information [1] The marking bar indicates the cathode. 3. Ordering information 4. Marking 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for cathode 1 cm2. Table 2. Pinning Pin Description Simplified outline Symbol 1 cathode [1] 2 anode 1 2 sym001 1 2 Table 3. Ordering information Type number Package Name Description Version BAT54J SC-90 plastic surface-mounted package; 2 leads SOD323F Table 4. Marking codes Type number Marking code BAT54J AP Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VR reverse voltage - 30 V IF forward current - 200 mA IFRM repetitive peak forward current tp ≤ 1 s; δ ≤ 0.5 - 300 mA IFSM non-repetitive peak forward current square wave; tp < 10 ms - 600 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 550 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °CBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 3 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. [2] Reflow soldering is the only recommended soldering method. [3] Soldering point of cathode tab. 7. Characteristics [1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02. Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1][2] - - 230 K/W Rth(j-sp) thermal resistance from junction to solder point [3] - - 55 K/W Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VF forward voltage [1] IF = 0.1 mA - - 240 mV IF = 1 mA - - 320 mV IF = 10 mA - - 400 mV IF = 30 mA - - 500 mV IF = 100 mA - - 800 mV IR reverse current VR = 25 V - - 2 µA Cd diode capacitance VR = 1 V; f = 1 MHz - - 10 pFBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 4 of 8 NXP Semiconductors BAT54J Schottky barrier single diode (1) Tamb = 125 °C (2) Tamb = 85 °C (3) Tamb = 25 °C (1) Tamb = 125 °C (2) Tamb = 85 °C (3) Tamb = 25 °C Fig 1. Forward current as a function of forward voltage; typical values Fig 2. Reverse current as a function of reverse voltage; typical values Tamb = 25 °C; f = 1 MHz Fig 3. Diode capacitance as a function of reverse voltage; typical values 103 102 10−1 IF (mA) VF (V) 10 1 0 0.4 0.8 1.2 msa892 (1) (2) (3) (1) (2) (3) 0 10 20 30 VR (V) 103 102 10−1 IR (µA) 10 1 (1) (2) (3) msa893 0 10 20 30 0 5 10 15 VR (V) Cd (pF) msa891BAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 5 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 8. Package outline 9. Packing information [1] For further information and the availability of packing methods, see Section 13. 10. Soldering Fig 4. Package outline SOD323F (SC-90) Dimensions in mm 04-09-13 0.80 0.65 0.25 0.10 0.5 0.3 2.7 2.3 1.8 1.6 0.40 0.25 1.35 1.15 1 2 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 BAT54J SOD323F 4 mm pitch, 8 mm tape and reel -115 -135 Reflow soldering is the only recommended soldering method. Dimensions in mm Fig 5. Reflow soldering footprint SOD323F (SC-90) 001aab169 1.65 0.50 (2×) 2.10 1.60 2.80 0.60 3.05 0.95 0.50 solder lands solder resist occupied area solder pasteBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 6 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 11. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes BAT54J_1 20070308 Product data sheet - -BAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 7 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 12. Legal information 12.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 12.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BAT54J Schottky barrier single diode © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 March 2007 Document identifier: BAT54J_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 14. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Packing information. . . . . . . . . . . . . . . . . . . . . . 5 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 7 12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 7 12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Contact information. . . . . . . . . . . . . . . . . . . . . . 7 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FUJITSU SEMICONDUCTOR DATA SHEET Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.2 Memory FRAM 128K (16 K × 8) Bit SPI MB85RS128B ■ DESCRIPTION MB85RS128B is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 16,384 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS128B adopts the Serial Peripheral Interface (SPI). The MB85RS128B is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS128B can be used for 1012 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS128B does not take long time to write data like Flash memories or E2PROM, and MB85RS128B takes no wait time. ■ FEATURES • Bit configuration : 16,384 words × 8 bits • Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) • Operating frequency : All commands except READ 33 MHz (Max) READ command 25 MHz (Max) • High endurance : 1012 times / byte • Data retention : 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) • Operating power supply voltage : 2.7 V to 3.6 V • Low power consumption : Operating power supply current 6 mA (Typ @33 MHz) Standby current 9 μA (Typ) • Operation ambient temperature range : − 40 °C to + 85 °C • Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant DS501-00020-2v0-EMB85RS128B 2 DS501-00020-2v0-E ■ PIN ASSIGNMENT ■ PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description 1 CS Chip Select pin This is an input pin to make chips select. When CS is the “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When CS is the “L” level, device is in select (active) status. CS has to be the “L” level before inputting op-code. 3 WP Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “■STATUS REGISTER”) is protected in related with WP and WPEN. See “■WRITING PROTECT” for detail. 7 HOLD Hold pin This pin is used to interrupt serial input/output without making chips deselect. When HOLD is the “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care. While the hold operation, CS has to be retained the “L” level. 6 SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin GND SI SO VDD WP SCK CS HOLD 8 7 6 4 5 3 2 1 (TOP VIEW) (FPT-8P-M02)MB85RS128B DS501-00020-2v0-E 3 ■ BLOCK DIAGRAM SCK SO SI Serial-Parallel Converter FRAM Cell Array 16,384 ✕ 8 Column Decoder/Sense Amp/ Write Amp FRAM Status Register Data Register Parallel-Serial Converter Control Circuit Address Counter Ro w Decoder CS WP HOLDMB85RS128B 4 DS501-00020-2v0-E ■ SPI MODE MB85RS128B corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) . SCK SI CS SCK SI CS 76543210 76543210 MSB LSB MSB LSB SPI Mode 0 SPI Mode 3MB85RS128B DS501-00020-2v0-E 5 ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85RS128B works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK SS1 HOLD1 MOSI MISO SS2 HOLD2 SCK CS HOLD SISO SCK CS HOLD SISO MB85RS128B MB85RS128B SCK CS HOLD SISO MB85RS128B SPI Microcontroller MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port System Configuration without SPI Port MicrocontrollerMB85RS128B 6 DS501-00020-2v0-E ■ STATUS REGISTER ■ OP-CODE MB85RS128B accepts 8 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Bit No. Bit Name Function 7 WPEN Status Register Write Protect This is a bit composed of nonvolatile memories (FRAM). WPEN protects writing to a status register (refer to “■ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR command are possible. 6 to 4 ⎯ Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR command is possible, and “000” is written before shipment. These bits are not used but they are read with the RDSR command. 3 BP1 Block Protect This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (refer to “■ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible. 2 BP0 1 WEL Write Enable Latch This indicates an FRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR command. WEL is reset after the following operations. After power ON. After WRDI command recognition. The rising edge of CS after WRSR command recognition. The rising edge of CS after WRITE command recognition. 0 0 This is a bit fixed to “0”. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B RDID Read Device ID 1001 1111B FSTRD Fast Read Memory Code 0000 1011BMB85RS128B DS501-00020-2v0-E 7 ■ COMMAND • WREN The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . WREN command is applicable to “Up to 33 MHz operation”. • WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR command) are not performed when WEL is reset. WRDI command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00000110 High-Z 210 3 7654 Invalid Invalid SO SCK SI CS 00000100 High-Z 210 3 7654 Invalid InvalidMB85RS128B 8 DS501-00020-2v0-E • RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. RDSR command is applicable to “Up to 33 MHz operation”. • WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. The WP signal level shall be fixed before performing the WRSR command, and do not change the WP signal level until the end of command sequence. WRSR command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00000101 High-Z 210 3 7654 Invalid MSB 210 3 7654 Data Out LSB Invalid SO SCK SI CS 00000001 210 3 7654 Data In MSB 210 3 7654 High-Z LSB 7654 3 210 InstructionMB85RS128B DS501-00020-2v0-E 9 • READ The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to SI. The 2-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. READ command is applicable to “Up to 25 MHz operation”. • WRITE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to SI. The 2-bit upper address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued infinitely. WRITE command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00 0 0 X 1 12 10 MSB 76543210 MSB Data Out High-Z LSB 420 1 Invalid 8 131211109 8 252423222120191 2726 8 3130292 OP-CODE 0 0 1 11 X 3 13 5 16-bit Address Invalid LSB 6 4 57 2 0 13 SO SCK SI CS 00 0 0 X 1 12 10 MSB 76543210 Data In MSB High-Z LSB 420 1 8 131211109 8 252423222120191 2726 8 3130292 OP-CODE 0 0 0 11 X 3 13 5 16-bit Address LSB 6 4 57 2 0 13MB85RS128B 10 DS501-00020-2v0-E • FSTRD The FSTRD command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of FSTRD are input to SI followed by 8 bits dummy. The 2-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. FSTRD command is applicable to “Up to 33 MHz operation”. • RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit after 32-bit Device ID output by continuously sending SCK clock before CS is risen. RDID command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00 0 1 X 1 13 76543210 MSB High-Z XX 8 11109 33323130 37363534 8 393 0 0 1 12 X Invalid LSB 6 4 57 2 0 13 1 XX 02 24 25232221 Invalid MSB Data Out LSB OP-CODE 16-bit Address 8-bit Dummy SO SCK SI CS MSB 76543210 Data Out Data Out High-Z LSB 8 11109 333231 37363534 8 393 Invalid 30 2 2931 8 10011111 8 6 4 57 2 0 13 bit 7 6 5 4 3 2 1 0 Hex Manufacturer ID 0 0 0 0 0 1 0 0 04H Fujitsu Continuation code 0 1 1 1 1 1 1 1 7FH Proprietary use Density Hex Product ID (1st Byte) 0 0 0 0 0 1 0 0 04H Density: 00100B = 128kbit Proprietary use Hex Product ID (2nd Byte) 0 0 0 0 1 0 0 1 09HMB85RS128B DS501-00020-2v0-E 11 ■ BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care. And, SO becomes High-Z while reading command (RDSR, READ) . If CS is rising during hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the value before transition to HOLD status. BP1 BP0 Protected Block 0 0 None 0 1 3000H to 3FFFH (upper 1/4) 1 0 2000H to 3FFFH (upper 1/2) 1 1 0000H to 3FFFH (all) WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected SCK CS Hold Condition HOLD Hold ConditionMB85RS128B 12 DS501-00020-2v0-E ■ ABSOLUTE MAXIMUM RATINGS *:These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS *:These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage* VDD − 0.5 + 4.0 V Input voltage* VIN − 0.5 VDD + 0.5 V Output voltage* VOUT − 0.5 VDD + 0.5 V Operation ambient temperature TA − 40 + 85 °C Storage temperature Tstg − 55 + 125 °C Parameter Symbol Value Unit Min Typ Max Power supply voltage* VDD 2.7 3.3 3.6 V Input high voltage* VIH VDD × 0.8 ⎯ VDD + 0.5 V Input low voltage* VIL − 0.5 ⎯ + 0.6 V Operation ambient temperature TA − 40 ⎯ + 85 °CMB85RS128B DS501-00020-2v0-E 13 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1 : Applicable pin : CS, WP, HOLD, SCK, SI *2 : Applicable pin : SO Parameter Symbol Condition Value Unit Min Typ Max Input leakage current*1 |ILI| VIN = 0 V to VDD ⎯ ⎯ 10 μA Output leakage current*2 |ILO| VOUT = 0 V to VDD ⎯ ⎯ 10 μA Operating power supply current IDD SCK = 25 MHz ⎯ 4 5 mA SCK = 33 MHz ⎯ 5 6 mA Standby current ISB All inputs VSS or SCK = SI = CS = VDD ⎯ 9 50 μA Output high voltage VOH IOH = −2 mA VDD × 0.8 ⎯ ⎯ V Output low voltage VOL IOL = 2 mA ⎯ ⎯ 0.4 VMB85RS128B 14 DS501-00020-2v0-E 2. AC Characteristics * : All commands except READ are applicable to “Up to 33 MHz operation”. READ command is applicable to “Up to 25MHz operation”. AC Test Condition Power supply voltage : 2.7 V to 3.6 V Operation ambient temperature : − 40 °C to + 85 °C Input voltage magnitude : 0.3 V to 2.7 V Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 Parameter Symbol Value Up to 25MHz Operation Up to 33MHz Operation* Unit Min Max Min Max SCK clock frequency fCK 0 25033 MHz Clock high time tCH 20 ⎯ 15 ⎯ ns Clock low time tCL 20 ⎯ 15 ⎯ ns Chip select set up time tCSU 10 ⎯ 10 ⎯ ns Chip select hold time tCSH 10 ⎯ 10 ⎯ ns Output disable time tOD ⎯ 20 ⎯ 20 ns Output data valid time tODV ⎯ 18 ⎯ 13 ns Output hold time tOH 0 ⎯ 0 ⎯ ns Deselect time tD 60 ⎯ 40 ⎯ ns Data in rising time tR ⎯ 50 - 50 ns Data falling time tF ⎯ 50 - 50 ns Data set up time tSU 5 ⎯ 5 ⎯ ns Data hold time tH 5 ⎯ 5 ⎯ ns HOLD set up time tHS 10 ⎯ 10 ⎯ ns HOLD hold time tHH 10 ⎯ 10 ⎯ ns HOLD output floating time tHZ ⎯ 20 ⎯ 20 ns HOLD output active time tLZ ⎯ 20 ⎯ 20 nsMB85RS128B DS501-00020-2v0-E 15 AC Load Equivalent Circuit 3. Pin Capacitance Parameter Symbol Conditions Value Unit Min Max Output capacitance CO VDD = VIN = VOUT = 0 V, f = 1 MHz, TA = + 25 °C ⎯ 10 pF Input capacitance CI ⎯ 10 pF 30 pF Output 3.3 V 1.2 k 0.95 kMB85RS128B 16 DS501-00020-2v0-E ■ TIMING DIAGRAM • Serial Data Timing • Hold Timing SCK CS SI Valid in SO High-Z : H or L tCSU tCH tCL tCH tSU tH tODV tOH tOD tCSH tD High-Z SCK CS SO tHS tHS tHH tHH tHH tHH tHZ tLZ tHZ tLZ tHS tHS HOLD High-Z High-ZMB85RS128B DS501-00020-2v0-E 17 ■ POWER ON/OFF SEQUENCE If VDD falls down below 2.0 V, VDD is required to be started from 1.0 V or less to prevent malfunctions when the power is turned on again (see the figure below). If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. ■ FRAM CHARACTERISTICS *1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates with destructive readout mechanism. *2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. ■ NOTE ON USE Data written before performing IR reflow is not guaranteed after IR reflow. Parameter Symbol Value Unit Min Max CS level hold time at power OFF tpd 200 ⎯ ns CS level hold time at power ON tpu 85 ⎯ ns Power supply rising time tr 0.05 200 ms Item Min Max Unit Parameter Read/Write Endurance*1 1012 ⎯ Times/byte Operation Ambient Temperature TA = + 85 °C Data Retention*2 10 ⎯ Years Operation Ambient Temperature TA = + 85 °C 95 ⎯ Operation Ambient Temperature TA = + 55 °C ≥ 200 ⎯ Operation Ambient Temperature TA = + 35 °C GND CS >VDD × 0.8* tpd tr tpu VIL (Max) 1.0 V VIH (Min) 3.0 V VDD CS : don't care CS >VDD × 0.8* CS CS GND VIL (Max) 1.0 V VIH (Min) 3.0 V VDD * : CS (Max) < VDD + 0.5 VMB85RS128B 18 DS501-00020-2v0-E ■ ESD AND LATCH-UP • Current method of Latch-Up Resistance Test Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN = ± 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant MB85RS128BPNF-G-JNE1 ≥ |2000 V| ESD MM (Machine Model) JESD22-A115 compliant ≥ |200 V| ESD CDM (Charged Device Model) JESD22-C101 compliant ⎯ Latch-Up (I-test) JESD78 compliant ⎯ Latch-Up (Vsupply overvoltage test) JESD78 compliant ⎯ Latch-Up (Current Method) Proprietary method ⎯ Latch-Up (C-V Method) Proprietary method ⎯ A VDD VSS DUT V IIN VIN + - Test terminal Protection Resistance VDD (Max.Rating) Reference terminalMB85RS128B DS501-00020-2v0-E 19 • C-V method of Latch-Up Resistance Test Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5times, this test must be stopped immediately. VDD VSS DUT VIN + - SW 1 2 C 200pF V A Test terminal Protection Resistance VDD (Max.Rating) Reference terminalMB85RS128B 20 DS501-00020-2v0-E ■ REFLOW CONDITIONS AND FLOOR LIFE Reflow Profile Item Condition Method IR (infrared reflow) , Convection Times 2 Floor life Before unpacking Please use within 2 years after production. From unpacking to 2nd reflow Within 8 days In case over period of floor life Baking with 125 °C+/-3 °C for 24hrs+2hrs/-0hrs is required. Then please use within 8 days. (Please remember baking is up to 2 times) Floor life condition Between 5 °C and 30 °C and also below 70%RH required. (It is preferred lower humidity in the required temp range.) 260°C (e) (d') (d) 255°C 170 °C 190 °C RT (b) (a) (c) to Note : Temperature on the top of the package body is measured. (a) Average ramp-up rate : 1 °C/s to 4 °C/s (b) Preheat & Soak : 170 °C to 190 °C, 60 s to 180 s (c) Average ramp-up rate : 1 °C/s to 4 °C/s (d) Peak temperature : Temperature 260 °C Max; 255 °C within 10 s (d’) Liquidous temperature : Up to 230 °C within 40 s or Up to 225 °C within 60 s or Up to 220 °C within 80 s (e) Cooling : Natural cooling or forced cooling Liquidous TemperatureMB85RS128B DS501-00020-2v0-E 21 ■ RESTRICTED SUBSTANCES This product complies with the regulations below (Based on current knowledge as of November 2011). • EU RoHS Directive (2002/95/EC) • China RoHS (Administration on the Control of Pollution Caused by Electronic Information Products ( )) • Vietnam RoHS (30/2011/TT-BCT) Restricted substances in each regulation are as follows. * : The mark of “❍” shows below a threshold value. Substances Threshold Contain status* Lead and its compounds 1,000 ppm ❍ Mercury and its compounds 1,000 ppm ❍ Cadmium and its compounds 100 ppm ❍ Hexavalent chromium compound 1,000 ppm ❍ Polybrominated biphenyls (PBB) 1,000 ppm ❍ Polybrominated diphenyl ethers (PBDE) 1,000 ppm ❍MB85RS128B 22 DS501-00020-2v0-E ■ ORDERING INFORMATION Part number Package Shipping form Minimum shipping quantity MB85RS128BPNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) Tube 1 MB85RS128BPNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) Embossed Carrier tape 1500MB85RS128B DS501-00020-2v0-E 23 ■ PACKAGE DIMENSION Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 8-pin plastic SOP Lead pitch 1.27 mm Package width × package length 3.9 mm × 5.05 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g 8-pin plastic SOP (FPT-8P-M02) (FPT-8P-M02) C 1.27(.050) 3.90±0.30 6.00±0.20 .199 –.008 +.010 –0.20 +0.25 5.05 0.13(.005) M (.154±.012) (.236±.008) 0.10(.004) 1 4 8 5 0.44±0.08 (.017±.003) –0.07 +0.03 0.22 .009 +.001 –.003 45° 0.40(.016) "A" 0~8° 0.25(.010) (Mounting height) Details of "A" part 1.55±0.20 (.061±.008) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) *1 *2 2002-2012 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-5-10 Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) 1 : These dimensions include resin protrusion. Note 2) 2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. * *MB85RS128B 24 DS501-00020-2v0-E ■ MARKING RS128B E11150 300 [MB85RS128BPNF-G-JNE1] [MB85RS128BPNF-G-JNERE1] [FPT-8P-M02]MB85RS128B DS501-00020-2v0-E 25 ■ PACKING INFORMATION 1. Tube 1.1 Tube Dimensions • Tube/stopper shape Tube cross-sections and Maximum quantity Package form Package code Maximum quantity pcs/ tube pcs/inner box pcs/outer box SOP, 8, plastic (2) t = 0.5 Transparent polyethylene terephthalate FPT-8P-M02 95 7600 30400 (Dimensions in mm) (treated to antistatic) Tube length: 520 mm (treated to antistatic) Stopper Tube Transparent polyethylene terephthalate 4.4 6.4 7.4 1.8 C 2006 FUJITSU LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-1 2.6 ©2006-2010 FUJITSU SEMICONDUCTOR LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-3MB85RS128B 26 DS501-00020-2v0-E 1.2 Tube Dry pack packing specifications *1: For a product of witch part number is suffixed with “E1”, a “ ” marks is display to the moisture barrier bag and the inner boxes. *2: The space in the outer box will be filled with empty inner boxes, or cushions, etc. *3: Please refer to an attached sheet about the indication label. Note: The packing specifications may not be applied when the product is delivered via a distributer. Tube Dry pack Inner box Outer box For SOP Stopper Aluminum Iaminated bag Index mark Desiccant Label I *1*3 Heat seal Aluminum Iaminated bag (tubes inside) Cushioning material Inner box Label I *1*3 Cushioning material Humidity indicater Outer box*2 Label II-A *3 Label II-B *3 IC Use adhesive tapes. G PbMB85RS128B DS501-00020-2v0-E 27 1.3 Product label indicators Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)] Label II-A: Label on Outer box [D Label] (100mm × 100mm) Label II-B: Outer boxes product indicate Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed. (Customer part number or FJ part number) (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Customer part number or FJ part number bar code) (Part number and quantity) (FJ control number) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX (Customer part number or FJ part number) XXXXXXXXXXXXXX (Comment) XXXXXXXXXX (FJ control number ) (LEAD FREE mark) C-3 Label Supplemental Label Perforated line XXXXXXXXXXXXX (Customer Name) (CUST.) XXX (FJ control number) XXX (FJ control number) XXX (FJ control number) XXXXXXXXXXXXXX (Part number) (FJ control number + Product quantity) (FJ control number + Product quantity bar code) (Part number + Product quantity bar code) XXXXXXXXX (Delivery Address) (DELIVERY POINT) XXXXXXXXXXXXXX (TRANS.NO.) (FJ control number) XXXXXXXXXXXXXX (PART NO.) (Customer part number or FJ part number) XXX/XXX (Q’TY/TOTAL Q’TY) XX (UNIT) (CUSTOMER'S REMARKS) XXXXXXXXXXXXXXXXXXXX (PACKAGE COUNT) XXX/XXX (PART NAME) XXXXXXXXXXXXXX (Part number) (3N)3 XXXXXXXXXXXXXX XXX (3N)4 XXXXXXXXXXXXXX XXX (Part number + Product quantity) (FJ control number) (FJ control number bar code) (3N)5 XXXXXXXXXX D Label XXXXXXXXXXXXXX (Part number) (Lot Number) XXXX-XXX XXXX-XXX (Count) (Quantity) X XXX X XXX XXXMB85RS128B 28 DS501-00020-2v0-E 1.4 Dimensions for Containers (1) Dimensions for inner box (2) Dimensions for outer box LWH 540 125 75 (Dimensions in mm) LWH 565 270 180 (Dimensions in mm) L W H L W HMB85RS128B DS501-00020-2v0-E 29 2. Emboss Tape 2.1 Tape Dimensions PKG code Reel No Maximum storage capacity pcs/reel pcs/inner box pcs/outer box FPT-8P-M02 3 1500 1500 10500 (Dimensions in mm) Material : Conductive polystyrene Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. C 2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1 8±0.1 6.4±0.1 3.9±0.2 4±0.1 5.5±0.05 5.5±0.1 2.1±0.1 0.4 1.75±0.1 0.3±0.05 2±0.05 +0.1 ø1.5 –0 +0.1 ø1.5 –0 +0.3 –0.1 12 B A B A SEC.A-A SEC.B-BMB85RS128B 30 DS501-00020-2v0-E 2.2 IC orientation 2.3 Reel dimensions Dimensions in mm Reel No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tape width Symbol 8 12 16 24 32 44 56 12 16 24 A 254 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 330 ± 2 B 100 100 150 100 150 100 100 ± 2 C 13 ± 0.2 13 D 21 ± 0.8 20.5 E 2 ± 0.5 W1 8.4 12.4 16.4 24.4 32.4 44.4 56.4 12.4 16.4 24.4 W2 less than 14.4 less than 18.4 less than 22.4 less than 30.4 less than 38.4 less than 50.4 less than 62.4 less than 18.4 less than 22.4 less than 30.4 W3 7.9 ~ 10.9 11.9 ~ 15.4 15.9 ~ 19.4 23.9 ~ 27.4 31.9 ~ 35.4 43.9 ~ 47.4 55.9 ~ 59.4 12.4 ~ 14.4 16.4 ~ 18.4 24.4 ~ 26.4 r 1.0 (User Direction of Feed) (User Direction of Feed) • ER type Index mark (Reel side) ∗ ∗: Hub unit width dimensions Reel cutout dimensions W1 W2 r E W3 B A C D +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +0.5 -0.2 +1 -0.2 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +1 -0 +1 -0 +0.1 -0MB85RS128B DS501-00020-2v0-E 31 2.4 Taping (φ330mm Reel) Dry Pack Packing Specifications *1: For a product of witch part number is suffixed with “E1”, a “ ” marks is display to the moisture barrier bag and the inner boxes. *2: The size of the outer box may be changed depending on the quantity of inner boxes. *3: The space in the outer box will be filled with empty inner boxes, or cushions, etc. *4: Please refer to an attached sheet about the indication label. Note: The packing specifications may not be applied when the product is delivered via a distributer. Embossed tapes Dry pack Inner box Outer box Outside diameter: 330mm reel Heat seal Label I *1, *4 Label II-B Label II-A *4 *4 Label I *1, *4 Label I *1, *4 Taping Use adhesive tapes. Outer box *2, *3 φ Inner box Label I *1, *4 Desiccant Humidity indicator Aluminum laminated bag G PbMB85RS128B 32 DS501-00020-2v0-E 2.5 Product label indicators Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)] Label II-A: Label on Outer box [D Label] (100mm × 100mm) Label II-B: Outer boxes product indicate Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed. (Customer part number or FJ part number) (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Customer part number or FJ part number bar code) (Part number and quantity) (FJ control number) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX (Customer part number or FJ part number) XXXXXXXXXXXXXX (Comment) XXXXXXXXXX (FJ control number ) (LEAD FREE mark) C-3 Label Supplemental Label Perforated line XXXXXXXXXXXXX (Customer Name) (CUST.) XXX (FJ control number) XXX (FJ control number) XXX (FJ control number) XXXXXXXXXXXXXX (Part number) (FJ control number + Product quantity) (FJ control number + Product quantity bar code) (Part number + Product quantity bar code) XXXXXXXXX (Delivery Address) (DELIVERY POINT) XXXXXXXXXXXXXX (TRANS.NO.) (FJ control number) XXXXXXXXXXXXXX (PART NO.) (Customer part number or FJ part number) XXX/XXX (Q’TY/TOTAL Q’TY) XX (UNIT) (CUSTOMER'S REMARKS) XXXXXXXXXXXXXXXXXXXX (PACKAGE COUNT) XXX/XXX (PART NAME) XXXXXXXXXXXXXX (Part number) (3N)3 XXXXXXXXXXXXXX XXX (3N)4 XXXXXXXXXXXXXX XXX (Part number + Product quantity) (FJ control number) (FJ control number bar code) (3N)5 XXXXXXXXXX D Label XXXXXXXXXXXXXX (Part number) (Lot Number) XXXX-XXX XXXX-XXX (Count) (Quantity) X XXX X XXX XXXMB85RS128B DS501-00020-2v0-E 33 2.6 Dimensions for Containers (1) Dimensions for inner box (2) Dimensions for outer box Tape width L W H 12, 16 365 345 40 24, 32 50 44 65 56 75 (Dimensions in mm) LWH 415 400 315 (Dimensions in mm) L W H L W HMB85RS128B 34 DS501-00020-2v0-E ■ MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results 1 ■ FEATURES Revised the Data retention 10 years ( + 85 °C) →10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) 17 ■ POWER ON/OFF SEQUENCE Revised the following description: “VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may cause malfunctions, when the power is turned on.” → “If VDD falls down below 2.0 V, VDD is required to be started from 1.0 V or less to prevent malfunctions when the power is turned on again (see the figure below).” Moved the following description under the table: “If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed.” ■ FRAM CHARACTERISTICS Revised the table and NoteMB85RS128B DS501-00020-2v0-E 35 MEMOMB85RS128B FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits „ Advanced TrenchMOS provides low RDSon and low gate charge „ High efficiency gains in switching power converters „ Improved mechanical and thermal characteristics „ LFPAK provides maximum power density in a Power SO8 package 1.3 Applications „ DC-to-DC converters „ Lithium-ion battery protection „ Load switching „ Motor control „ Server power supplies 1.4 Quick reference data PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Rev. 02 — 28 October 2010 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 67 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 117 W Tj junction temperature -55 - 175 °C Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 12 - - 18 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12; see Figure 13 - 8.6 11 mΩPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 2 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 2. Pinning information 3. Ordering information Dynamic characteristics QGD gate-drain charge VGS = 10 V; ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 11 - nC QG(tot) total gate charge - 45 - nC Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 67 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped - - 121 mJ Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source SOT669 (LFPAK) 2 S source 3 S source 4 G gate mb D mounting base; connected to drain mb 1234 S D G mbb076 Table 3. Ordering information Type number Package Name Description Version PSMN011-80YS LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 3 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 80 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 100 °C; see Figure 1 - 47 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 67 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 266 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 117 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb = 25 °C - 67 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 266 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 67 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped - 121 mJ Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aad341 0 20 40 60 80 0 50 100 150 200 Tmb (°C) ID (A) Tmb (°C) 0 200 50 100 150 03aa16 40 80 120 Pder (%) 0PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 4 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003aad343 10-1 1 10 102 103 1 10 102 103 VDS (V) ID (A) DC 100 ms 10 ms 1 ms 100 μs 10 μs Limit RDSon = VDS / IDPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 5 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.5 1.3 K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration; typical values 003aad342 single shot 0.2 0.1 0.05 0.02 10−3 10−2 10−1 1 1−6 10−5 10−4 10−3 10−2 10−1 1 tp (s) Zth (j-mb) (K/W) δ = 0.5PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 6 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 73 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 1- - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 4.6 V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11; see Figure 10 234V IDSS drain leakage current VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 80 V; VGS = 0 V; Tj = 125 °C - - 100 µA IGSS gate leakage current VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 12 - 19 26 mΩ VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 12 - - 18 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12; see Figure 13 - 8.6 11 mΩ RG internal gate resistance (AC) f = 1 MHz - 0.7 - Ω Dynamic characteristics QG(tot) total gate charge ID = 0 A; VDS = 0 V; VGS = 10 V - 38 - nC ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - 45 - nC QGS gate-source charge - 13 - nC QGS(th) pre-threshold gate-source charge ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14 - 8 - nC QGS(th-pl) post-threshold gate-source charge - 5 - nC QGD gate-drain charge ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - 11 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 4.9 - V Ciss input capacitance VDS = 40 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 2800 - pF Coss output capacitance - 270 - pF Crss reverse transfer capacitance - 146 - pF td(on) turn-on delay time VDS = 40 V; RL = 1.6 Ω; VGS = 10 V; RG(ext) = 4.7 Ω - 23 - ns tr rise time - 20 - ns td(off) turn-off delay time - 40 - ns tf fall time - 12 - nsPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 7 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.8 1.2 V trr reverse recovery time IS = 40 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 40 V - 54 - ns Qr recovered charge - 98 - nC Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 7. Forward transconductance as a function of drain current; typical values Fig 8. Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aad311 0 20 40 60 80 100 0123 VDS (V) ID (A) 8 10 20 5.5 5 6 VGS (V) = 4.5 003aad333 0 20 40 60 80 100 0246 VGS (V) ID (A) Tj = 175 °C Tj = 25 °C 003aad338 0 20 40 60 80 100 0 20 40 60 80 100 ID (A) gfs (S) 003aad337 1000 1500 2000 2500 3000 3500 4000 0 5 10 15 20 25 VGS (V) C (pF) Ciss CrssPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 8 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 9. Drain-source on-state resistance as a function of gate-source voltage; typical values Fig 10. Gate-source threshold voltage as a function of junction temperature Fig 11. Sub-threshold drain current as a function of gate-source voltage Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aad339 5 10 15 20 25 30 4 8 12 16 20 VGS (V) RDSon (mΩ) Tj (°C) −60 180 0 60 120 003aad280 2 3 1 4 5 VGS(th) (V) 0 max typ min 03aa35 VGS (V) 0 6 2 4 10−4 10−5 10−2 10−3 10−1 ID (A) 10−6 min typ max 003aae090 0 0.6 1.2 1.8 2.4 3 -60 0 60 120 180 Tj (°C) aPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 9 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 13. Drain-source on-state resistance as a function of drain current; typical values Fig 14. Gate charge waveform definitions Fig 15. Gate-source voltage as a function of gate charge; typical values Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aad312 5 8 11 14 17 20 0 20 40 60 80 100 ID (A) RDSon (mΩ) 8 5.5 20 6 10 VGS (V) = 5 003aaa508 VGS VGS(th) QGS1 QGS2 QGD VDS QG(tot) ID QGS VGS(pl) 003aad335 0 2 4 6 8 10 0 10 20 30 40 50 QG (nC) VGS (V) VDS = 40V 64V 16V 003aad336 102 103 104 10-1 1 10 102 VDS (V) C (pF) Ciss Crss CossPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 10 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values 003aad334 0 20 40 60 80 100 0 0.3 0.6 0.9 1.2 VSD (V) IS (A) Tj = 25 °C Tj = 175 °CPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 11 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 7. Package outline Fig 18. Package outline SOT669 (LFPAK) REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT669 MO-235 04-10-13 06-03-16 0 2.5 5 mm scale e E1 b c2 A2 UNIT A A2 b c e DIMENSIONS (mm are the original dimensions) mm 1.10 0.95 A1 A3 0.15 0.00 1.20 1.01 0.50 0.35 b2 4.41 3.62 b3 2.2 2.0 b4 0.9 0.7 0.25 0.19 c2 0.30 0.24 4.10 3.80 6.2 5.8 H 1.3 0.8 L2 0.85 0.40 L 1.3 0.8 L1 8° 0° D w y (1) 5.0 4.8 E(1) 3.3 3.1 E1 D1 (1) (1) max 0.25 4.20 1.27 0.25 0.1 1 2 34 mounting base D1 c Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E b2 b3 b4 H D L2 L1 A w M A C C X 1/2 e y C θ θ (A ) 3 L A A1 detail X Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 12 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN011-80YS v.2 20101028 Product data sheet - PSMN011-80YS v.1 Modifications: • Status changed from objective to product. • Various changes to content. PSMN011-80YS v.1 20100226 Objective data sheet - -PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 13 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 9. Legal information 9.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 14 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 October 2010 Document identifier: PSMN011-80YS Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 General description . . . . . . . . . . . . . . . . . . . . . .1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 5 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11 8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 10 Contact information. . . . . . . . . . . . . . . . . . . . . .14 1. Product profile 1.1 General description Femtofarad bidirectional ElectroStatic Discharge (ESD) protection diode in a leadless ultra small SOD882 Surface-Mounted Device (SMD) plastic package designed to protect one signal line from the damage caused by ESD and other transients. The combination of extremely low capacitance, high ESD maximum rating and ultra small package makes the device ideal for high-speed data line protection and antenna protection applications. 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data PESD5V0F1BL Femtofarad bidirectional ESD protection diode Rev. 3 — 24 October 2011 Product data sheet  Bidirectional ESD protection of one line  ESD protection up to 10 kV  Femtofarad capacitance: Cd = 400 fF  IEC 61000-4-2; level 4 (ESD)  Low ESD clamping voltage: 30 V at 30 ns and  8 kV  AEC-Q101 qualified  Very low leakage current: IRM < 1 nA  10/100/1000 Mbit/s Ethernet  Portable electronics  FireWire  Communication systems  High-speed data lines  Computers and peripherals  Subscriber Identity Module (SIM) card protection  Audio and video equipment  Cellular handsets and accessories  Antenna protection Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per device VRWM reverse standoff voltage - - 5.5 V Cd diode capacitance f = 1 MHz; VR = 0 V - 0.4 0.55 pFPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 2 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values [1] Non-repetitive current pulse 8/20 s exponential decay waveform according to IEC 61000-4-5. Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 cathode (diode 1) 2 cathode (diode 2) 21 Transparent top view sym045 1 2 Table 3. Ordering information Type number Package Name Description Version PESD5V0F1BL - leadless ultra small plastic package; 2 terminals; body 1.0  0.6  0.5 mm SOD882 Table 4. Marking codes Type number Marking code PESD5V0F1BL ZZ Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per device IPP peak pulse current tp = 8/20 s [1] - 2.5 A Tj junction temperature - 125 C Tamb ambient temperature 40 +125 C Tstg storage temperature 55 +125 CPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 3 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode [1] Device stressed with ten non-repetitive ESD pulses. Table 6. ESD maximum ratings Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Max Unit Per device VESD electrostatic discharge voltage IEC 61000-4-2 (contact discharge) [1] - 10 kV MIL-STD-883 (human body model) - 10 kV Table 7. ESD standards compliance Standard Conditions Per device IEC 61000-4-2; level 4 (ESD) > 8 kV (contact) MIL-STD-883; class 3 (human body model) > 4 kV Fig 1. 8/20 s pulse waveform according to IEC 61000-4-5 Fig 2. ESD pulse waveform according to IEC 61000-4-2 t (μs) 0 40 10 20 30 001aaa630 40 80 120 IPP (%) 0 e−t 100 % IPP; 8 μs 50 % IPP; 20 μs 001aaa631 IPP 100 % 90 % t 30 ns 60 ns 10 % tr = 0.7 ns to 1 nsPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 4 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 6. Characteristics [1] Non-repetitive current pulse 8/20 s exponential decay waveform according to IEC 61000-4-5. Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per device VRWM reverse standoff voltage - - 5.5 V IRM reverse leakage current VRWM = 5 V - 1 100 nA VBR breakdown voltage IR = 1 mA 6 8 10 V Cd diode capacitance f = 1 MHz; VR = 0 V - 0.4 0.55 pF VCL clamping voltage [1] IPP =1A - - 11 V IPP = 2.5 A - - 15 V rdif differential resistance IR = 20 mA - - 30  f = 1 MHz; Tamb = 25 C Fig 3. Diode capacitance as a function of reverse voltage; typical values Fig 4. V-I characteristics for a bidirectional ESD protection diode VR (V) −6.0 −2.0 2.0 6.0 006aab598 0.3 0.4 0.5 Cd (pF) 0.2 006aaa676 −VCL −VBR −VRWM −IRM VRWM VBR VCL IRM −IR IR −IPP IPP − +PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 5 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode Fig 5. ESD clamping test setup and waveforms 006aab599 50 Ω RZ CZ DUT (DEVICE UNDER TEST) GND GND 450 Ω RG 223/U 50 Ω coax ESD TESTER IEC 61000-4-2 network CZ = 150 pF; RZ = 330 Ω 4 GHz DIGITAL OSCILLOSCOPE 10× ATTENUATOR GND GND unclamped +8 kV ESD pulse waveform (IEC 61000-4-2 network) clamped +8 kV ESD pulse waveform (IEC 61000-4-2 network) pin 1 to 2 unclamped −8 kV ESD pulse waveform (IEC 61000-4-2 network) clamped −8 kV ESD pulse waveform (IEC 61000-4-2 network) pin 1 to 2 vertical scale = 2 kV/div horizontal scale = 15 ns/div vertical scale = 2 kV/div horizontal scale = 15 ns/div vertical scale = 50 V/div horizontal scale = 15 ns/div vertical scale = 50 V/div horizontal scale = 15 ns/divPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 6 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 7. Application information PESD5V0F1BL is designed for the protection of one bidirectional data or signal line from the damage caused by ESD and surge pulses. The device may be used on lines where the signal polarities are both, positive and negative with respect to ground. Circuit board layout and protection device placement Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. Place the device as close to the input terminal or connector as possible. 2. The path length between the device and the protected line should be minimized. 3. Keep parallel signal paths to a minimum. 4. Avoid running protected conductors in parallel with unprotected conductors. 5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops. 6. Minimize the length of the transient return path to ground. 7. Avoid using shared transient return paths to a common ground point. 8. Ground planes should be used whenever possible. For multilayer PCBs, use ground vias. 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. Fig 6. Application diagram 006aab600 PESD5V0F1BL GND GPS ANTENNAPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 7 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. This is a generic drawing for SOD882 package. This product has no cathode marking. Fig 7. Package outline PESD5V0F1BL (SOD882) Dimensions in mm 03-04-17 0.55 0.47 0.65 0.62 0.55 0.50 0.46 cathode marking on top side 1.02 0.95 0.30 0.22 0.30 0.22 2 1 Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 10000 PESD5V0F1BL SOD882 2 mm pitch, 8 mm tape and reel -315PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 8 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 11. Soldering Reflow soldering is the only recommended soldering method. Fig 8. Reflow soldering footprint PESD5V0F1BL (SOD882) solder lands solder resist occupied area solder paste sod882_fr 0.9 0.3 (2×) R0.05 (8×) 0.6 (2×) 0.7 (2×) 0.4 (2×) 1.3 0.5 (2×) 0.8 (2×) 0.7 Dimensions in mmPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 9 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PESD5V0F1BL v.3 20111024 Product data sheet - PESD5V0F1BL v.2 Modifications: • Figure 7 “Package outline PESD5V0F1BL (SOD882)”: updated. • Section 13 “Legal information”: updated. PESD5V0F1BL v.2 20110323 Product data sheet - PESD5V0F1BL v.1 PESD5V0F1BL v.1 20091001 Product data sheet - -PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 10 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 11 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 October 2011 Document identifier: PESD5V0F1BL Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Application information. . . . . . . . . . . . . . . . . . . 6 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 6 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Packing information . . . . . . . . . . . . . . . . . . . . . 7 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Contact information. . . . . . . . . . . . . . . . . . . . . 11 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1. Product profile 1.1 General description 500 mA PNP Resistor-Equipped Transistor (RET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package. NPN complement: PDTD123TT. 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data PDTB123TT PNP 500 mA, 50 V resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open Rev. 4 — 8 November 2010 Product data sheet „ 500 mA output current capability „ Reduces component count „ Built-in bias resistor „ Reduces pick and place costs „ Simplifies circuit design „ AEC-Q101 qualified „ Digital application in automotive and industrial segments „ Cost-saving alternative for BC807 series in digital applications „ Control of IC inputs „ Switching loads Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −50 V IO output current - - −500 mA R1 bias resistor 1 (input) 1.54 2.2 2.86 kΩPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 2 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 2. Pinning information 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 input (base) 2 GND (emitter) 3 output (collector) 006aaa144 1 2 3 sym009 3 2 1 R1 Table 3. Ordering information Type number Package Name Description Version PDTB123TT - plastic surface-mounted package; 3 leads SOT23 Table 4. Marking codes Type number Marking code[1] PDTB123TT *1UPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 3 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −50 V VCEO collector-emitter voltage open base - −50 V VEBO emitter-base voltage open collector - −5 V VI input voltage positive - +5 V negative - −12 V IO output current - −500 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/WPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 4 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 7. Characteristics Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = −40 V; IE =0A - - −100 nA VCB = −50 V; IE =0A - - −100 nA ICEO collector-emitter cut-off current VCE = −50 V; IB =0A - - −0.5 μA IEBO emitter-base cut-off current VEB = −5 V; IC =0A - - −100 nA hFE DC current gain VCE = −5 V; IC = −50 mA 100 250 - VCEsat collector-emitter saturation voltage IC = −50 mA; IB = −2.5 mA - - −0.3 V R1 bias resistor 1 (input) 1.54 2.2 2.86 kΩ Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 100 MHz - 11 - pF VCE = −5 V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C Fig 1. DC current gain as a function of collector current; typical values Fig 2. Collector-emitter saturation voltage as a function of collector current; typical values 006aaa455 IC (mA) −10−1 −103 −102 −1 −10 103 hFE 102 (2) (3) (1) 006aaa456 IC (mA) −10−1 −102 −1 −10 −10−1 VCEsat (V) −10−2 (2) (3) (1)PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 5 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. Fig 3. Package outline SOT23 (TO-236AB) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 PDTB123TT SOT23 4 mm pitch, 8 mm tape and reel -215 -235PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 6 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 11. Soldering Fig 4. Reflow soldering footprint SOT23 (TO-236AB) Fig 5. Wave soldering footprint SOT23 (TO-236AB) solder lands solder resist occupied area solder paste sot023_fr 0.5 (3×) 0.6 (3×) 0.6 (3×) 0.7 (3×) 3 1 3.3 2.9 1.7 1.9 2 Dimensions in mm solder lands solder resist occupied area preferred transport direction during soldering sot023_fw 2.8 4.5 1.4 4.6 1.4 (2×) 1.2 (2×) 2.2 2.6 Dimensions in mmPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 7 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PDTB123TT v.4 20101108 Product data sheet - PDTB123T_SER_3 Modifications: • Type numbers PDTB123TK and PDTB123TS deleted. • Table 7 “Characteristics”: unit for VCEsat changed from mV to V. • Section 8 “Test information”: added. • Section 11 “Soldering”: added. • Section 13 “Legal information”: updated. PDTB123T_SER_3 20091116 Product data sheet - PDTB123T_SER_2 PDTB123T_SER_2 20050804 Product data sheet - PDTB123TK_1 PDTB123TK_1 20050519 Product data sheet - -PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 8 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 9 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 November 2010 Document identifier: PDTB123TT Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 5 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 Packing information . . . . . . . . . . . . . . . . . . . . . 5 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 8 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 8 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Contact information. . . . . . . . . . . . . . . . . . . . . . 9 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 http://www.farnell.com/datasheets/1754399.pdf http://www.farnell.com/datasheets/1754399.pdf 1. Product profile 1.1 General description PNP switching transistor in a SOT23 (TO-236AB) small Surface-Mounted Device (SMD) plastic package. NPN complement: PMBT3904. 1.2 Features and benefits „ Collector-emitter voltage VCEO = −40 V „ Collector current capability IC = −200 mA 1.3 Applications „ General amplification and switching 1.4 Quick reference data 2. Pinning information PMBT3906 PNP switching transistor Rev. 06 — 2 March 2010 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −40 V IC collector current - - −200 mA Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 base 2 emitter 3 collector 1 2 3 006aab259 2 1 3PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 2 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB). Table 3. Ordering information Type number Package Name Description Version PMBT3906 - plastic surface-mounted package; 3 leads SOT23 Table 4. Marking codes Type number Marking code[1] PMBT3906 *2A Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −40 V VCEO collector-emitter voltage open base - −40 V VEBO emitter-base voltage open collector - −6 V IC collector current - −200 mA ICM peak collector current - −200 mA IBM peak base current - −100 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °CPMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 3 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 6. Thermal characteristics [1] Device mounted on an FR4 PCB. 7. Characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/W Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = −30 V; IE =0A - - −50 nA IEBO emitter-base cut-off current VEB = −6 V; IC =0A - - −50 nA hFE DC current gain VCE = −1 V IC = −0.1 mA 60 - - IC = −1 mA 80 - - IC = −10 mA 100 - 300 IC = −50 mA 60 - - IC = −100 mA 30 - - VCEsat collector-emitter saturation voltage IC = −10 mA; IB = −1 mA - - −250 mV IC = −50 mA; IB = −5 mA - - −400 mV VBEsat base-emitter saturation voltage IC = −10 mA; IB = −1 mA - - −850 mV IC = −50 mA; IB = −5 mA - - −950 mV td delay time ICon = −10 mA; IBon = −1 mA; IBoff = 1 mA - - 35 ns tr rise time - - 35 ns ton turn-on time - - 70 ns ts storage time - - 225 ns tf fall time - - 75 ns toff turn-off time - - 300 ns fT transition frequency VCE = −20 V; IC = −10 mA; f = 100 MHz 250 - - MHz Cc collector capacitance VCB = −5 V; IE = ie = 0 A; f = 1 MHz - - 4.5 pF Ce emitter capacitance VEB = −500 mV; IC = ic = 0 A; f = 1 MHz - - 10 pF NF noise figure IC = −100 μA; VCE = −5 V; RS =1kΩ; f = 10 Hz to 15.7 kHz - - 4 dBPMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 4 of 11 NXP Semiconductors PMBT3906 PNP switching transistor VCE = −1 V (1) Tamb = 150 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 1. DC current gain as a function of collector current; typical values Fig 2. Collector current as a function of collector-emitter voltage; typical values VCE = −1 V (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 150 °C IC/IB = 10 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 150 °C Fig 3. Base-emitter voltage as a function of collector current; typical values Fig 4. Base-emitter saturation voltage as a function of collector current; typical values 0 400 600 200 mhc459 −10−1 −1 −10 IC (mA) hFE −102 −103 (1) (3) (2) 0 −10 −250 0 −50 −100 −150 −200 −2 VCE (V) IC (mA) −4 −6 −8 006aab845 IB (mA) = −1.5 −1.05 −0.75 −0.45 −0.15 −0.3 −0.6 −0.9 −1.2 −1.35 mhc461 −600 −800 −400 −1000 −1200 VBE (mV) −200 IC (mA) −10−1 −103 −102 −1 −10 (1) (2) (3) mhc462 −600 −800 −400 −1000 −1200 VBEsat (mV) −200 IC (mA) −10−1 −103 −102 −1 −10 (1) (2) (3)PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 5 of 11 NXP Semiconductors PMBT3906 PNP switching transistor IC/IB = 10 (1) Tamb = 150 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 5. Collector-emitter saturation voltage as a function of collector current; typical values −103 −102 −10 mhc463 −10−1 −1 −10 IC (mA) VCEsat (mV) −102 −103 (1) (2) (3)PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 6 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 8. Test information Fig 6. BISS transistor switching time definition VI = 5 V; T = 500 μs; tp = 10 μs; tr = tf ≤ 3 ns R1 = 56 Ω; R2 = 2.5 kΩ; RB = 3.9 kΩ; RC = 270 Ω VBB = 1.9 V; VCC = −3 V Oscilloscope: input impedance Zi = 50 Ω Fig 7. Test circuit for switching times 006aaa266 −IBon (100 %) −IB input pulse (idealized waveform) −IBoff 90 % 10 % −IC (100 %) −IC td ton 90 % 10 % tr output pulse (idealized waveform) tf t ts toff RC R2 R1 DUT mgd624 Vo RB (probe) 450 Ω (probe) 450 Ω oscilloscope oscilloscope VBB VI VCCPMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 7 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 13. Fig 8. Package outline SOT23 (TO-236AB) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 PMBT3906 SOT23 4 mm pitch, 8 mm tape and reel -215 -235PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 8 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 11. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PMBT3906_6 20100302 Product data sheet - PMBT3906_N_5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 4 “Marking”: amended • Table 7 “Characteristics”: F redefined to NF noise figure • Section 8 “Test information”: added • Figure 6: added • Figure 8: superseded by minimized package outline drawing • Section 10 “Packing information”: added • Section 12 “Legal information”: updated PMBT3906_N_5 20071004 Product data sheet - PMBT3906_4 PMBT3906_4 20040121 Product specification - PMBT3906_3 PMBT3906_3 19990427 Product specification - PMBT3906_CNV_2 PMBT3906_CNV_2 19970505 Product specification - -PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 9 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 12. Legal information 12.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 10 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 13. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PMBT3906 PNP switching transistor © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 March 2010 Document identifier: PMBT3906_6 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 14. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Packing information . . . . . . . . . . . . . . . . . . . . . 7 11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9 12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9 12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Contact information. . . . . . . . . . . . . . . . . . . . . 10 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SG2525A SG3525A REGULATING PULSE WIDTH MODULATORS ..8 TO 35 V OPERATION .5.1 V REFERENCE TRIMMED TO ± 1 % .100 Hz TO 500 KHz OSCILLATOR RANGE .SEPARATE OSCILLATOR SYNC TERMINAL .ADJUSTABLE DEADTIME CONTROL .INTERNAL SOFT-START .PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH .HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE .PULSES DUAL SOURCE/SINK OUTPUT DRIVERS DESCRIPTION The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time ad- justment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525A output stage features NOR logic, giving a LOW output for an OFF state. DIP16 16(Narrow) Type Plastic DIP SO16 SG2525A SG2525AN SG2525AP SG3525A SG3525AN SG3525AP PIN CONNECTIONS AND ORDERING NUMBERS (top view) ® June 2000 1/12 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vi Supply Voltage 40 V VC Collector Supply Voltage 40 V IOSC Oscillator Charging Current 5 mA Io Output Current, Source or Sink 500 mA IR Reference Output Current 50 mA IT Current through CT Terminal Logic Inputs Analog Inputs 5 – 0.3 to + 5.5 – 0.3 to Vi mA V V Ptot Total Power Dissipation at Tamb = 70 °C 1000 mW Tj Junction Temperature Range – 55 to 150 °C Tstg Storage Temperature Range – 65 to 150 °C Top Operating Ambient Temperature : SG2525A SG3525A – 25 to 85 0 to 70 °C °C THERMAL DATA Symbol Parameter SO16 DIP16 Unit Rth j-pins Rth j-amb Rth j-alumina Thermal Resistance Junction-pins Max Thermal Resistance Junction-ambient Max Thermal Resistance Junction-alumina (*) Max 50 50 80 °C/W °C/W °C/W * Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 ´ 20 mm ; 0.65 mm thickness with infinite heatsink. BLOCK DIAGRAM SG2525A-SG3525A 2/12 ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified) Symbol Parameter Test Conditions SG2525A SG3525A Unit Min. Typ. Max. Min. Typ. Max. REFERENCE SECTION VREF Output Voltage Tj = 25 °C 5.05 5.1 5.15 5 5.1 5.2 V DVREF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV DVREF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV DVREF/DT* Temp. Stability Over Operating Range 20 50 20 50 mV * Total Output Variation Line, Load and Temperature 5 5.2 4.95 5.25 V Short Circuit Current VREF = 0 Tj = 25 °C 80 100 80 100 mA * Output Noise Voltage 10 Hz £f £ 10 kHz, Tj = 25 °C 40 200 40 200 mVrms DVREF* Long Term Stability Tj = 125 °C, 1000 hrs 20 50 20 50 mV OSCILLATOR SECTION * * *, · Initial Accuracy Tj = 25 °C ± 2 ± 6 ± 2 ± 6 % *, · Voltage Stability Vi = 8 to 35 V ± 0.3 ± 1 ± 1 ± 2 % Df/DT* Temperature Stability Over Operating Range ± 3 ± 6 ± 3 ± 6 % fMIN Minimum Frequency RT = 200 KW CT = 0.1 mF 120 120 Hz fMAX Maximum Frequency RT = 2 KW CT = 470 pF 400 400 KHz Current Mirror IRT = 2 mA 1.7 2 2.2 1.7 2 2.2 mA *, · Clock Amplitude 3 3.5 3 3.5 V *, · Clock Width Tj = 25 °C 0.3 0.5 1 0.3 0.5 1 ms Sync Threshold 1.2 2 2.8 1.2 2 2.8 V Sync Input Current Sync Voltage = 3.5 V 1 2.5 1 2.5 mA ERROR AMPLIFIER SECTION (VCM = 5.1 V) VOS Input Offset Voltage 0.5 5 2 10 mV Ib Input Bias Current 1 10 1 10 mA Ios Input Offset Current 1 1 mA DC Open Loop Gain RL ³ 10 MW 60 75 60 75 dB * Gain Bandwidth Product Gv = 0 dB Tj = 25 °C 1 2 1 2 MHz *, z DC Transconduct. 30 KW £ RL £ 1 MW Tj = 25 °C 1.1 1.5 1.1 1.5 ms Output Low Level 0.2 0.5 0.2 0.5 V Output High Level 3.8 5.6 3.8 5.6 V CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB PSR Supply Voltage Rejection Vi = 8 to 35 V 50 60 50 60 dB SG2525A-SG3525A 3/12 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions SG2525A SG3525A Unit Min. Typ. Max. Min. Typ. Max. PWM COMPARATOR Minimum Duty-cycle 0 0 % · Maximum Duty-cycle 45 49 45 49 % · Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V Maximum Duty-cycle 3.3 3.6 3.3 3.6 V * Input Bias Current 0.05 1 0.05 1 mA SHUTDOWN SECTION Soft Start Current VSD = 0 V, VSS = 0 V 25 50 80 25 50 80 mA Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V Shutdown Threshold To outputs, VSS = 5.1 V Tj = 25 °C 0.6 0.8 1 0.6 0.8 1 V Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 mA * Shutdown Delay VSD = 2.5 V Tj = 25 °C 0.2 0.5 0.2 0.5 ms OUTPUT DRIVERS (each output) (VC = 20 V) Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V Isink = 100 mA 1 2 1 2 V Output High Level Isource = 20 mA 18 19 18 19 V Isource = 100 mA 17 18 17 18 V Under-Voltage Lockout Vcomp and Vss = High 6 7 8 6 7 8 V IC Collector Leakage VC = 35 V 200 200 mA tr* Rise Time CL = 1 nF, Tj = 25 °C 100 600 100 600 ns tf* Fall Time CL = 1 nF, Tj = 25 °C 50 300 50 300 ns TOTAL STANDBY CURRENT Is Supply Current Vi = 35 V 14 20 14 20 mA * These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production. · Tested at fosc = 40 KHz (RT = 3.6 KW, CT = 10nF, RD = 0 W). Approximate oscillator frequency is defined by : f = 1 CT (0.7 RT + 3 RD) .DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded. SG2525A-SG3525A 4/12 TEST CIRCUIT SG2525A-SG3525A 5/12 Figure 1 : Oscillator Charge Time vs. RT and CT. Figure 2 : Oscillator Discharge Time vs. RD and CT. RECOMMENDED OPERATING CONDITIONS (·) Parameter Value Input Voltage (Vi) 8 to 35 V Collector Supply Voltage (VC) 4.5 to 35 V Sink/Source Load Current (steady state) 0 to 100 mA Sink/Source Load Current (peak) 0 to 400 mA Reference Load Current 0 to 20 mA Oscillator Frequency Range 100 Hz to 400 KHz Oscillator Timing Resistor 2 KW to 150 KW Oscillator Timing Capacitor 0.001 mF to 0.1 mF Dead Time Resistor Range 0 to 500 W · (×) Range over which the device is functional and parameter limits are guaranteed. Figure 3 : Output Saturation Characteristics. Figure 4 : Error Amplifier Voltage Gain and Phase vs. Frequency. SG2525A-SG3525A 6/12 SHUTDOWN OPTIONS (see Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 mA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immediately set providing the fastest turn-off signal to the outputs ; and a 150 mA current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. Figure 5 : Error Amplifier. PRINCIPLES OF OPERATION SG2525A-SG3525A 7/12 Figure 7 : Output Circuit (1/2 circuit shown). Figure 6 : Oscillator Schematic. SG2525A-SG3525A 8/12 Figure 10. Figure 11. For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. The low source impedance of the output drivers provides rapid charging of Power Mos input capacitance while minimizing external components. Low power transformers can be driven directly. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. Figure 8. Figure 9. SG2525A-SG3525A 9/12 DIP16 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 OUTLINE AND MECHANICAL DATA SG2525A-SG3525A 10/12 SO16 Narrow DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M 0.62 0.024 S (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). OUTLINE AND MECHANICAL DATA 8°(max.) SG2525A-SG3525A 11/12 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com SG2525A-SG3525A 12/12 AN2794 Application note 1 kW dual stage DC-AC converter based on the STP160N75F3 Introduction This application note provides design guidelines and performance characterization of the STEVAL-ISV001V1 demonstration board. This board implements a 1 kW dual stage DC-AC converter, suitable for use in batterypowered uninterruptible power supplies (UPS) or photovoltaic (PV) standalone systems. The converter is fed by a low DC input voltage varying from 20 V to 28 V, and is capable of supplying up to 1 kW of output power on a single-phase AC load. These features are possible thanks to a dual stage conversion topology that includes an efficient step-up pushpull DC-DC converter, which produces a regulated high-voltage DC bus and a sinusoidal HBridge PWM inverter to generate a 50 Hz, 230 Vrms output sine wave. Other key features of the system proposed are high power density, high switching frequency and efficiency greater than 90% over a wide output load range Figure 1. 1 kW DC-AC converter prototype www.st.com Contents AN2794 2/39 Doc ID 14827 Rev 2 Contents 1 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 Schematic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Appendix A Component list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Appendix B Product technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AN2794 List of tables Doc ID 14827 Rev 2 3/39 List of tables Table 1. System specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Push-pull converter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. HF transformer design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Output inductor design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Bill of material (BOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 List of figures AN2794 4/39 Doc ID 14827 Rev 2 List of figures Figure 1. 1 kW DC-AC converter prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Block diagram of an offline UPS system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Possible use of a DC-AC converter in standalone PV conversion . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Block diagram of the proposed conversion scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Push-pull converter typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Distribution of converter losses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Distribution of losses with 3 STP160N75F3s paralleled . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 12. Characteristic waveforms (measured at 24 V input voltage and 280 W resistive load) . . . 26 Figure 13. Characteristic waveforms (measured at 28 V input voltage and 1000 W resistive load) . . 26 Figure 14. MOSFET voltage (ch4) and current (ch3) without RC snubber . . . . . . . . . . . . . . . . . . . . . 27 Figure 15. MOSFET voltage (ch4) and current (ch3) with RC snubber . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Rectifier diode current (ch3) and voltage (ch4) without RDC snubber . . . . . . . . . . . . . . . . 27 Figure 17. Rectifier diode current (ch3) and voltage (ch4) with RDC snubber. . . . . . . . . . . . . . . . . . . 27 Figure 18. Ch1, ch3 MOSFETs drain current, ch2, ch4 MOSFET drain-source voltage . . . . . . . . . . . 28 Figure 19. Startup, ch2, ch3 inverter voltage and current, ch4 DC bus voltage . . . . . . . . . . . . . . . . . 28 Figure 20. DC-DC converter efficiency with 20 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 21. DC-DC converter efficiency with 22 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 22. DC-DC converter efficiency with 24 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 23. DC-DC converter efficiency with 26 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 24. DC-DC converter efficiency with 28 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 25. Converter efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 26. Technical specification for 1.5 mH 2.5 A inductor L4 (produced by MAGNETICA) . . . . . . 35 Figure 27. Technical specification for 1 kW, 100 kHz switch mode power transformer TX1 (produced by MAGNETICA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 28. Dimensional drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AN2794 System description Doc ID 14827 Rev 2 5/39 1 System description In a UPS system, as shown in Figure 2, a DC-AC converter is always used to convert the DC power from the batteries to AC power used to supply the load. The basic scheme also includes a battery pack, a battery charger which converts AC power from the grid into DC power, and a transfer switch to supply the load from the mains or from the energy storage elements if a line voltage drop or failure occurs. Figure 2. Block diagram of an offline UPS system Another application where a DC-AC converter is always required is shown in the block diagram of Figure 3. In this case, the converter is part of a conversion scheme commonly used in standalone photovoltaic systems. An additional DC-DC converter operates as a battery charger while performing a maximum power point tracking algorithm (MPPT), which is necessary to maximize the energy yield from the PV array. The battery pack is always present to store energy when solar radiation is available and release it at night or during hours of low insolation. Figure 3. Possible use of a DC-AC converter in standalone PV conversion A possible implementation of an isolated DC-AC converter, which can be successfully used in both the above mentioned applications, is given in the block diagram of Figure 4. It consists of three main sections: 1. The DC-DC converter 2. The DC-AC converter 3. The power supply section Battery AC/DC DC/AC SWITCH Battery Charger + MPPT Batteries LC Filter DC/DC DC/AC Load System description AN2794 6/39 Doc ID 14827 Rev 2 Figure 4. Block diagram of the proposed conversion scheme The DC-DC section is a critical part of the converter design. In fact, the need for high overall efficiency (close to 90% or higher) together with the specifications for continuous power rating, low input voltage range leading to high input current, and the need for high switching frequency to minimize weight and size of passive components, makes it a quite challenging design. Due to the constraints given by the specifications given in Table 1, few topology solutions are suitable to meet the efficiency target. Actually, since the input voltage of the DC-AC converter must be at least equal to 350 V, it is not feasible to use non-isolated DC-DC converters. Moreover, the output power rating prevents the use of single switch topologies such as the flyback and the forward. Among the remaining isolated topologies, the half bridge and full bridge are more suitable for high DC input voltage applications and also characterized by the added complexity of gate drive circuitry of the high side switches. Due to such considerations, the push-pull represents the most suitable choice. This topology features two transistors on the primary side and a center tapped high frequency transformer, as shown in the step-up section in Figure 4. It is quite efficient at low input voltage making it widely used in battery powered UPS applications. Both power devices are ground referenced with consequent simple gate drive circuits. They are alternatively turned Table 1. System specifications Specification Value Nominal input voltage 24 V Output voltage 230 Vrms, 50 Hz Output power 1kW Efficiency 90% Switching frequency 100 kHz (DC-DC); 16 kHz (DC-AC) 􀀳􀁔􀁅􀁐􀀍􀁕􀁐􀀀􀁓􀁔􀁁􀁇􀁅􀀀􀀈􀀰􀁕􀁓􀁈􀀍􀀰􀁕􀁌􀁌􀀉􀀀 􀀳􀀧􀀓􀀕􀀒􀀕 􀀋 􀀳􀀴􀀰􀀑􀀖􀀐􀀮􀀗􀀕􀀦􀀓􀀀 􀀳􀀴􀀴􀀨􀀘􀀲􀀐􀀖 􀀬􀀖􀀓􀀘􀀖􀀀 􀀳􀀴􀀗􀀦􀁌􀁉􀁔􀁅􀀓􀀙 􀀳􀀴􀀧􀀷􀀑􀀙􀀮􀀣􀀖􀀐􀀷􀀤􀀀 􀀋 􀀿 􀀩􀁎􀁖􀁅􀁒􀁔􀁅􀁒􀀀􀀳􀁔􀁁􀁇􀁅􀀀􀀈􀀨􀀍􀀢􀁒􀁉􀁄􀁇􀁅􀀉􀀀 􀀋 􀀋􀀑􀀕􀀶 􀀬􀀗􀀘􀀐􀀕 􀀀􀀀􀀋􀀕􀀶􀀀 􀀀􀀀􀀬􀀕􀀙􀀗􀀓􀀤􀀀 􀀑􀀮􀀕􀀘􀀒􀀑 􀀳􀀴􀀮􀀔􀀮􀀦􀀐􀀓􀀬 􀀰􀁏􀁗􀁅􀁒 􀀳􀁕􀁐􀁐􀁌􀁙􀀀 􀀳􀁅􀁃􀁔􀁉􀁏􀁎􀀀 􀀋 􀀬􀀖􀀓􀀘􀀖 􀀋 􀀿 􀀭􀀑 􀀭􀀒 􀀴􀀸􀀀 􀀬 􀀣 􀀤􀀑 􀀤􀀒 􀀤􀀓􀀀 􀀤􀀔 􀀺􀀑􀀀 􀀺􀀒􀀀 􀀺􀀔􀀀 􀀺􀀓􀀀 􀀶􀁉􀁎 􀀶􀁏􀁕􀁔 􀀡􀀭􀀐􀀐􀀖􀀕􀀘􀁖􀀑 AN2794 System description Doc ID 14827 Rev 2 7/39 on and off in order to transfer power to each primary of the center tapped transformer. Contemporary conduction of both devices must be avoided by limiting the duty cycle value of the constant frequency PWM modulator to less than 0.5. The PWM modulator should also prevent unequal ON times for the driving signals since this would result in transformer saturation caused by the "Flux Walking" phenomenon. The basic operation is similar to a forward converter. In fact, when a primary switch is active, the current flows through the rectifier diodes, charging the output inductor, while when both the switches are off, the output inductor discharges. It is important to point out that the operating frequency of the output inductor is twice the switching frequency. A transformer reset circuit is not needed thanks to the bipolar flux operation, which also means better transformer core utilization with respect to single-ended topologies. The main disadvantage of the push-pull converter is the breakdown voltage of primary power devices which has to be higher than twice the input voltage. In fact, when voltage is applied to one of the two transformer primary windings by the conduction of a transistor, the reflected voltage across the other primary winding puts the drain of the off state transistor at twice the input voltage with respect to ground. This is the reason why push-pull converters are not suitable for high input voltage applications. For the above mentioned reasons, the voltage fed push-pull converter, shown in Figure 4, is chosen to boost the input voltage from 24 V to a regulated 350 V, suitable for optimal inverter operation. The high voltage conversion ratio can be achieved by proper transformer turns ratio design, taking into account that the input to output voltage transfer function is given by: Equation 1 The duty cycle is set by a voltage mode PWM regulator (SG3525) to keep a constant output DC bus voltage. This voltage is then converted into AC using a standard H-bridge converter implemented with four ultrafast switching IGBTs in PowerMESH™ technology, switching at 16 kHz. The switching strategy, based on PWM sinusoidal modulation, is implemented on an 8-bit ST7lite39 microcontroller unit. This allows the use of a simple LC circuit to obtain a high quality sine wave in terms of harmonic content. The power supply section consists of a buck-boost converter to produce a regulated 15 V from a minimum input voltage of 4 V. The circuit can be simply implemented by means of a L5973 device, characterized by an internal P-channel DMOS transistor and few external components. In this way, it is possible to supply all the driving circuits and the PWM modulator. A standard linear regulator, L7805, provides 5 V supply to the microcontroller unit. in 1 2 out DV N N V = 2 Design considerations AN2794 8/39 Doc ID 14827 Rev 2 2 Design considerations The basic operation of a voltage fed push-pull converter is shown in Figure 5, where theoretical converter waveforms are highlighted. In practice, significant overvoltages across devices M1, M2 and across the four rectifier diodes are observed in most cases due to the leakage inductance of the high frequency transformer. As a consequence, the breakdown voltage of primary devices must be greater than twice the input voltage, and the use of snubbing and/or clamping circuits is often helpful. Special attention has to be paid to transformer design, due to the difficulties in minimizing the leakage inductance and implementing low-voltage high-current terminations. Moreover, imbalance in the two primary inductance values must be avoided both by symmetrical windings and proper printed circuit board (PCB) layout. While transformer construction techniques guarantee good symmetry and low leakage inductance values, asymmetrical layout due to inappropriate component placement can be the source of different PCB trace inductances. Whatever the cause of a difference in peak current through the switching elements, transformer saturation in voltage mode push-pull converters can occur in a few switching cycles with catastrophic consequences. Figure 5. Push-pull converter typical waveforms AN2794 Design considerations Doc ID 14827 Rev 2 9/39 Starting from the specifications in Table 2, a step-by-step design procedure and some design hints to obtain a symmetrical layout are given below. A switching frequency of f = 100 kHz was chosen to minimize passive components size and weight, then the following step-by-step calculation was done: ● Switching period: Equation 2 ● Maximum duty cycle The theoretical maximum on time for each phase of the push-pull converter is: Equation 3 Since deadtime has to be provided in order to avoid simultaneous device conduction, it is better to choose the maximum duty cycle of each phase as: Equation 4 This means a total deadtime of 1μs at maximum duty cycle, occurring for minimum input voltage operation. ● Input power Assuming 90% efficiency the input power is: Equation 5 Table 2. Push-pull converter specifications Specification Symbol Value Nominal input voltage Vin 24 V Maximum input voltage Vinmax 28 V Minimum input voltage Vinmin 20 V Nominal output power Pout 1000 W Nominal output voltage Vout 350 V Target efficiency η > 90% Switching frequency f 100 kHz 10 s 10 1 f 1 T 5 = = = μ t on 0.5T 5 s * = = μ 0.45 T t D 0.9 on * max = = 1111W 0.9 P P out in = = Design considerations AN2794 10/39 Doc ID 14827 Rev 2 ● Maximum average input current: Equation 6 ● Maximum equivalent flat topped input current: Equation 7 ● Maximum input RMS current: Equation 8 ● Maximum MOSFET RMS current: Equation 9 ● Minimum MOSFET breakdown voltage: Equation 10 ● Transformer turns ratio: Equation 11 ● Minimum duty cycle value: Equation 12 ● Duty cycle at nominal input voltage: Equation 13 ● Maximum average output current: Equation 14 55.55 A 20 1111 V P I inmin in in = = = 61.72 A 0.9 55.55 2D I I max in pft = = = Iin Ipft 2Dmax 58.55A RMS = = IMosRMS = Ipft Dmax = 41.4A VBrk 1.3 2 VinMax 72.8 V Mos = • • = 19 2V D V N N N in max out 1 2 min = = = 0.32 2NV V D inmax out min = = 0.38 2NV V D in out min = = 2.86A V P I out out out = = AN2794 Design considerations Doc ID 14827 Rev 2 11/39 ● Secondary maximum RMS current Assuming that the secondary top flat current value is equal to the average output value the rms secondary current is: Equation 15 ● Rectifier diode voltage: Equation 16 ● Output filter inductor value: Equation 17 Assuming a ripple current value ΔI= 15% Iout = 0.43A, the minimum value for the output filter inductance is: Equation 18 With this value of inductance continuous current mode (CCM) operation is guaranteed for a minimum output current of: Equation 19 which means a minimum load of 75 W is required for CCM operation. The chosen value for this design is L=1.5 mH. ● Output filter capacitor value: Equation 20 Considering a maximum output ripple value equal to: Equation 21 Isec Iout Dmax 1.91A RMS = = Vdiode = NVinMax = 532 V in 1 2 min V N N L ≥ ( - I t V ) onMax out Δ Lmin = 1.109 mH 0.215A 2 I I outMin = Δ = s 0 L T V I 8 1 C Δ Δ = ΔV0 = 0.1%Vout = 0.35 V Design considerations AN2794 12/39 Doc ID 14827 Rev 2 the minimum value of capacitance is: Equation 22 and the equivalent series resistance (ESR) has to be lower than: Equation 23 ● Input capacitor: Equation 24 where Icrms is the RMS capacitor current value given by: Equation 25 and Equation 26 then Equation 27 Cmin = 1.53 μF = Ω Δ Δ = 0.81 I V ESR L 0 max in onMax in Crms V T C I Δ Δ = I I I2 19A in 2 Crms InRms = - = V 0.1%V 0.028V in inMax Δ = = 3053 F V T C I in onMax in Crms = μ Δ Δ = AN2794 Design considerations Doc ID 14827 Rev 2 13/39 ● HF transformer design The design method is based on the Kg core geometry approach. The design can be done according to the specifications in Table 3. The first step is to compute the transformer apparent power given by: Equation 28 The second step is the electrical condition parameter calculation Ke: Equation 29 where Kf=4 is the waveform coefficient (for square waves). Equation 30 The next step is to calculate the core geometry parameter: Equation 31 Table 3. HF transformer design parameters Specification Symbol Value Nominal input voltage Vin 24 V Maximum input voltage Vinmax 28 V Minimum input voltage Vinmin 20 V RMS input current Iin 41.4 A Nominal output voltage Vout 350 V Output current Iout 2.86 A Switching frequency f 100 kHz Efficiency η 98% Regulation α 0.05% Max operating flux density Bm 0.05T Window utilization Ku 0.3 Duty cycle Dmax 0.45 Temperature rise Tr 30 °C 1)V I 2021 W 1 P ( P P 0 0 0 0 t + = η + = η = ( ) 4 2m 2 2f Ke 0.145 K f B 10= • • • - K 0.145(4)2 (100.000)2 (0.05)2 (10 4 ) 5800 e = = - 5 e t g 0.348 cm 2K P K = α = Design considerations AN2794 14/39 Doc ID 14827 Rev 2 The Kg constant is related to the core geometrical parameters by the following equation: Equation 32 where Wa is the core window area, Ac is the core cross sectional area and MLT is the mean length per turn. For example, choosing an E55/28/21 core with N27 ferrite, having ● Wa= 2.8 cm2 ● Ac= 3.5 cm2 ● MLT= 11.3 cm the resulting Kg factor is: ● Kg= 0.91 cm2 which is then suitable for this application. Once the core has been chosen, it is possible to calculate the number of primary turns as follows: Equation 33 The primary inductance value is: Equation 34 and the number of secondary turns is: Equation 35 At this point wires must be selected in order to implement primary and secondary windings. At 100 kHz the current penetration depth is: Equation 36 Then, the wire diameter can be selected as follows: Equation 37 MLT W A K K u 2c a g = 2 turns BA V D T N c in max 1 min = Δ = L N AL 4 5800 nH 23.2 H 2 p = = • = μ N2 = N • N1 = 38 turns 0.0209 cm f 6.62 δ = = d = 2δ = 0.0418cm AN2794 Design considerations Doc ID 14827 Rev 2 15/39 and the conductor section is: Equation 38 Checking the wire table we notice that AWG26, having a wire area of AWAWG26 = 0.00128 cm2, can be used in this design. Considering a current density J = 500 A/cm2 the number of primary wires is given by: Equation 39 where: Equation 40 Since the AWG26 has a resistance of 1345 μΩ/cm, the primary resistance is: Equation 41 and so the value of resistance for the primary winding is: Equation 42 Using the same procedure, the secondary winding is: Equation 43 Equation 44 Equation 45 Equation 46 2 2 W 0.00137cm 4 d A = π = 62 A A S wAWG26 wp np = = in 2 wp 0.08 cm J I A = = 21.69 / cm 62 1345 / cm rp = μΩ μΩ = Rp = N1 •MLT • rp = 490.1 μΩ out 2 ws 0.00572 cm J I A = = 5 A A S wAWG26 ws ns = = 269 / cm 5 1345 / cm rs = μΩ μΩ = Rs = N2 • MLT • rs = 115 .5mΩ Design considerations AN2794 16/39 Doc ID 14827 Rev 2 The total copper losses are: Equation 47 And transformer regulation is: Equation 48 From the core loss curve of N27 material, at 55 °C, 50mT and 100 kHz, the selected core has the following losses: Equation 49 Where Ve= 43900 mm3 is the core volume. The transformer temperature rise is: Equation 50 with Equation 51 ● Output inductor The output filter inductor can be made using powder cores to minimize eddy current losses and introduce a distributed air gap into the core. The design parameters are shown in Table 4: Table 4. Output inductor design parameters Specification Symbol Value Minimum inductance value Lmin 1.5 mH DC current I0 2.86 A AC current ΔI 0.41 A Output power P0 1000 W Ripple frequency fr 200 kHz Operating flux density Bm 0.3 T Core material Kool μ Window utilization K u 0.4 Temperature rise Tr 25 °C W 78 . 1 I R I R P P P 2s in s 2 Cu = p + s = p + = 100 0.178% P P out α = cu = V 1.23W m kW PV = 28.1 3 • e = T R (P P ) 33 oC r = th • Cu + V = W C R 11 o th = AN2794 Design considerations Doc ID 14827 Rev 2 17/39 The peak current value across the inductor is: Equation 52 To select a proper core we must compute the LI2 pk value: Equation 53 Knowing this parameter, from Magnetics’ core chart, a 46.7 mm x 28.7 mm x 12.2 mm Kool μ toroid, with μ=60 permeability and AL = 0.086 nH/turn can be selected. The required number of turns is then: Equation 54 The resulting magnetizing force (DC bias) is: Equation 55 The initial value of turns has to be increased by dividing it by 0.8 (as shown in the data catalog) to take into account the reduction of initial permeability (μe = 39 at full load) at nominal current value. Then, the adjusted number of turns is: Equation 56 The wire table shows that at 3 A the AWG20 can be used. With this choice, the maximum number of turns per layer, for the selected core, is Nlayer= 96 and the resistance per single layer is rlayer= 0.166Ω. The total winding resistance is then: Equation 57 and the copper losses are: Equation 58 The core losses can be evaluated as follows: 3.06A 2 I Ipk I0 = Δ = + LI2 10.3mH A pk = • 132 turns A L N L = = 84.2 oersteds L NI H 0.4 e = π = N = 165 turns = r = 0.38Ω N N R layer layer W 1 . 3 RI P 2o cu = = Design considerations AN2794 18/39 Doc ID 14827 Rev 2 Equation 59 Equation 60 where MPL=11.8 cm is the magnetic path length. Since the core weight is 95.8 g, the core losses are: Equation 61 ● Analysis of the converter losses Once the transformer has been designed, the next step in performing the loss analysis is to choose the power devices both for the input and output stage of the push-pull converter. According to the calculations given above the following components have been selected: MOSFET and diode losses can be separated into conduction and switching losses which can be estimated, in the worst case operating condition (junction temperature of 100 °C), with the following equations: Equation 62 Equation 63 Equation 64 Table 5. Power MOSFET Device Type RDS(on) tr+tf Vbr Id at 100 °C STP160N75F3 Power MOSFET 4.5 mΩ 70 ns+15 ns 75 V 96 A Table 6. Diode Device Type VF at 175 °C trrMax VRRM IF at 100 °C STTH8R06 Ultrafast diode 1.4 V 25 ns 600 V 8 A P kB2.12f1.23 2.047mW/ g L = ac = ( ) 0.0137T MPL 10 2 I 0.4 N B 4 e ac = μ Δ π = - PL = 0.2W P 1.6R I 12.5W ON RMS Mos 2 cond = ds = Pgate = QgVgsf = 0.165W 8.5W T V I (t t ) 2 1 P Off mos r f sw(ON OFF) = + = + AN2794 Design considerations Doc ID 14827 Rev 2 19/39 Equation 65 Equation 66 Note: Assuming: tB= trr/2, VRM= 350 V Converter losses are distributed according to the graphic in Figure 6, where PCB trace losses and control losses are not considered. What is important to note is that primary switch conduction accounts for 36% of total DC-DC converter losses. This contribution can be reduced by paralleling either two or three power devices. For example, by paralleling three STP160N75F3s, a reduction in MOSFET conduction losses of 33% is achieved. Thus MOSFET conduction losses account for 16% of total DC-DC converter losses, resulting in a 1.8% efficiency improvement. Figure 6. Distribution of converter losses P V I 2.67W condDiode F secRMS = = Pdiode VRMIRRtbf 2.4W SW = = 36% 25% 16% 14% 4% 5% MOSFET cond. Losses MOSFET sw. Losses Diode cond. Losses Diode sw. Losses Transformer Losses Inductor Losses AM00627v1 Design considerations AN2794 20/39 Doc ID 14827 Rev 2 Figure 7. Distribution of losses with 3 STP160N75F3s paralleled 2.1 Layout considerations Because of the high power level involved with this design, the parasitic elements must be reduced as much as possible. Proper operation of the push-pull converter can be assured through geometrical symmetry of the PCB board. In fact, geometrical symmetry leads to electrical symmetry, preventing a difference in the current values across the two primary windings of the transformer which can be the cause of core saturation. The output stage of the converter has also to be routed with a certain degree of symmetry even if in this case the impact of unwanted parasitic elements is lower because of lower current values with respect to the input stage. In Figure 8, Figure 9 and Figure 10, a symmetrical layout designed for the application is shown. 16% 33% 21% 18% 6% 6% MOSFET cond. Losses MOSFET sw. Losses Diode cond. Losses Diode sw. Losses Transformer Losses Inductor Losses AM00628v1 AN2794 Design considerations Doc ID 14827 Rev 2 21/39 Figure 8. Component placement Figure 9. Top layer AM00629v1 AM00630v1 Design considerations AN2794 22/39 Doc ID 14827 Rev 2 Figure 10. Bottom layer To obtain geometrical symmetry the HF transformer has been placed at the center of the board, which has been developed using double-sided, 140 μm FR-4 substrate with 135 x 185 mm size. In addition, this placement of the transformer is the most suitable since it is the bulkiest part of the board. Both the primary and secondary AC current loops are placed very close to the transformer in order to reduce their area and consequently their parasitic inductances. For this reason the MOSFET and rectifier diodes lie at the edges of the PCB. Input loop PCB traces show identical shapes to guarantee the same values of resistance and parasitic inductance. Also the IGBTs of the inverter stage lie at one edge of the board. This gives the advantage of using a single heat sink for each group of power components. The output filter is placed on the right side of the transformer, between the bridge rectifier and the inverter stage. The power supply section lies on the left side of the transformer, simplifying the routing of the 15 V bus dedicated to supply all the control circuitry. AM00631v1 AN2794 Schematic description Doc ID 14827 Rev 2 23/39 3 Schematic description The schematic of the converter is shown in Figure 11. Three MOSFETs are paralleled in order to transfer power to each primary winding of the transformer. Both RC and RCD networks can be connected between the drain and source of the MOSFETs to reduce the overvoltages and voltage ringing caused by unclamped leakage inductance. The output of the transformer is rectified by a full bridge of ultrafast soft-recovery diodes. An RCD network is connected across the rectifier output to clamp the diode voltage to its steady state value and recover the reverse recovery energy stored in the leakage inductance. This energy is first transferred to the clamp capacitor and then partially diverted to the output through a resistor. The IGBT full bridge is connected to the output of the push-pull stage. Their control signals are generated by an SG3525 voltage mode PWM modulator. Its internal clock, necessary to generate the 100 kHz modulation, is set by an external RC network. The PWM output stage is capable of sourcing or sinking up to 100 mA which can be enough to directly drive the gate of the MOSFETs devices. The PWM controller power dissipation, given by the sum of its own power consumption and the power needed to drive six STP160N75F3s at 100 kHz, can be evaluated with the following equation: Equation 67 where Vs and Is are the supply voltage and current. Since this power dissipation would result in a high operating temperature of the IC, a totem pole driving circuit has been used to handle the power losses and peak currents, achieving a more favorable operating condition. This circuit was implemented by means of an NPNPNP complementary pair of BJT transistors. The control and driver stage schematic is shown in Figure 11. PContoller tot = 6QgfVdrive + VsIs = 1.3W Schematic description AN2794 24/39 Doc ID 14827 Rev 2 Figure 11. Schematic 􀀶􀁉􀁎􀀝􀀑􀀒􀀶􀀏􀀒􀀔􀀶 􀀹􀁒􀀠􀀔􀀘􀀹 􀀯􀀱􀁐􀀔􀀠􀀒􀀔􀀱􀀚􀀕􀁘􀀠􀀫􀀔􀀛 􀀖􀀤 􀀹􀀲􀀸􀀷 􀀪􀀤􀀷􀀨􀀃􀀤 􀀪􀀤􀀷􀀨􀀃􀀥 􀀹􀀲􀀸􀀷 􀀳􀀺􀀰􀀃􀀥 􀀳􀀺􀀰􀀃􀀤 􀀳􀀺􀀰􀀃􀀤 􀀪􀀤􀀷􀀨􀀃􀀤 􀀳􀀺􀀰􀀃􀀥 􀀪􀀤􀀷􀀨􀀃􀀥 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀧􀀵􀀤􀀬􀀱􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀧􀀵􀀤􀀬􀀱􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀔􀀒􀀫􀀬􀀪􀀫􀀕 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀕􀀒􀀫􀀬􀀪􀀫􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀹􀁌􀁑 􀀎􀀔􀀘􀀹 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀔􀀒􀀫􀀬􀀪􀀫􀀕 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀕􀀒􀀫􀀬􀀪􀀫􀀔 􀀵􀀨􀀶􀀨􀀷 􀀳􀀤􀀘 􀀳􀀤􀀙 􀀳􀀤􀀘 􀀳􀀤􀀙 􀀵􀀨􀀶􀀨􀀷 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀓 􀀓 􀀹􀁕􀁈􀁉 􀀓 􀀓 􀀎􀀔􀀘􀀹 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀹􀁌􀁑 􀀎􀀔􀀘􀀹 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀓 􀀘􀀹 􀀓 􀀘􀀹 􀀓 􀀓 􀀘􀀹 􀀓 􀀓 􀀓 􀀦􀀔􀀜 􀀕􀀕􀁘􀀃􀀕􀀘􀀹 􀀰􀀖 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀵􀀜􀀖 􀀔􀀑􀀘􀁎 􀀬􀀦􀀕 􀀯􀀙􀀖􀀛􀀙􀀧 􀀶􀀧 􀀕 􀀹􀀦􀀦 􀀗 􀀯􀀬􀀱 􀀔 􀀫􀀹􀀪 􀀔􀀖 􀀪􀀱􀀧 􀀛 􀀫􀀬􀀱 􀀖 􀀦􀀬􀀱 􀀙 􀀧􀀬􀀤􀀪 􀀘 􀀱􀀦 􀀔􀀓 􀀶􀀪􀀱􀀧 􀀚 􀀯􀀹􀀪 􀀜 􀀲􀀸􀀷 􀀔􀀕 􀀱􀀦􀀔 􀀔􀀔 􀀹􀀥􀀲􀀲􀀷 􀀔􀀗 􀀹􀀬􀀱 􀀦􀀲􀀱􀀔 􀀔 􀀹􀀲􀀸􀀷􀀃􀀤􀀦􀀃􀀔 􀀦􀀲􀀱􀀔 􀀔 􀀦􀀘􀀜 􀀔􀀓􀀓􀁑 􀀵􀀜􀀗 􀀘􀀓􀀓􀀏􀀃􀀕􀀓􀀺 􀀵􀀔􀀓􀀖 􀀔􀀓 􀀦􀀘􀀖 􀀕􀀑􀀕􀁘􀀏􀀃􀀗􀀘􀀓􀀹 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀔􀀓􀀓 􀀯􀀗 􀀔􀀑􀀘􀁐􀀫 􀀔 􀀕 􀀦􀀖􀀜 􀀔􀀘􀀓􀁘􀀩􀀃􀀖􀀘􀀹􀀃􀀏􀀃􀁈􀁏􀁈􀁆􀀑 􀀵􀀕􀀗 􀀔􀀓 􀀦􀀕􀀙 􀀕􀀑􀀕􀁘􀀃􀀕􀀘􀀹 􀀵􀀜􀀓 􀀔􀀓􀁎 􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀴􀀛 􀀶􀀷􀀱􀀗􀀱􀀩􀀓􀀖􀀯 􀀦􀁖􀀕 􀀔􀀓􀀓􀁑􀀃􀀙􀀖􀀓􀀹 􀀪􀀱􀀧 􀀦􀀲􀀱􀀔 􀀔 􀀴􀀔􀀔 􀀕􀀶􀀥􀀚􀀚􀀕 􀀦􀀔􀀓 􀀗􀀚􀁘􀀃􀀏􀀃􀀖􀀘􀀹􀀃􀀨􀀯􀀨􀀦 􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀸􀀕􀀓 􀀯􀀚􀀛􀀓􀀘􀀒􀀧􀁁􀀕􀀳􀁄􀁎 􀀹􀀬􀀱 􀀔 􀀪􀀱􀀧 􀀕 􀀹􀀲􀀸􀀷 􀀖 􀀧􀀛 􀀥􀀤􀀷􀀃􀀗􀀙 􀀕 􀀔 􀀧􀀔􀀖 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀧􀀔􀀓 􀀶􀀷􀀷􀀫􀀔􀀯􀀓􀀙 􀀔 􀀕 􀀬􀀦􀀔 􀀯􀀙􀀖􀀛􀀙􀀧 􀀶􀀧 􀀕 􀀹􀀦􀀦 􀀗 􀀯􀀬􀀱 􀀔 􀀫􀀹􀀪 􀀔􀀖 􀀪􀀱􀀧 􀀛 􀀫􀀬􀀱 􀀖 􀀦􀀬􀀱 􀀙 􀀧􀀬􀀤􀀪 􀀘 􀀱􀀦 􀀔􀀓 􀀶􀀪􀀱􀀧 􀀚 􀀯􀀹􀀪 􀀜 􀀲􀀸􀀷 􀀔􀀕 􀀱􀀦􀀔 􀀔􀀔 􀀹􀀥􀀲􀀲􀀷 􀀔􀀗 􀀵􀀕􀀔 􀀔􀀕􀀒􀀓􀀑􀀕􀀘􀀺 􀀰􀀘 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀦􀀖􀀖 􀀗􀀚􀀓􀁑􀀃􀀕􀀘􀀹 􀀦􀀗􀀓 􀀕􀀕􀁑􀀩 􀀦􀀔􀀙 􀀔􀀓􀀓􀁓 􀀵􀀜􀀔 􀀔􀀓􀁎 􀀦􀀔 􀀔􀀓􀀓􀁑 􀀵􀀜􀀘 􀀘􀀓􀀓􀀏􀀃􀀕􀀓􀀺 􀀹􀀲􀀸􀀷􀀃􀀤􀀦􀀃􀀕 􀀦􀀲􀀱􀀔 􀀔 􀀴􀀔􀀕 􀀕􀀶􀀥􀀚􀀚􀀕 􀀸􀀔 􀀶􀀪􀀖􀀘􀀕􀀘 􀀬􀀱􀀐 􀀔 􀀲􀀶􀀦 􀀗 􀀦􀀷 􀀘 􀀧􀀬􀀶􀀦􀀫􀀤􀀵 􀀚 􀀶􀀶 􀀛 􀀶􀀑􀀧􀀲􀀺􀀱 􀀔􀀓 􀀲􀀸􀀷􀀤 􀀔􀀔 􀀪􀀱􀀧 􀀔􀀕 􀀹􀀦 􀀔􀀖 􀀲􀀸􀀷􀀥 􀀔􀀗 􀀵􀀷 􀀙 􀀦􀀲􀀰􀀳 􀀜 􀀶􀀼􀀱􀀦 􀀖 􀀎􀀹􀀬 􀀔􀀘 􀀬􀀱􀀎 􀀕 􀀹􀀵􀀨􀀩 􀀔􀀙 􀀧􀀚 􀀕 􀀔 􀀥􀀤􀀷􀀗􀀙 􀀎 􀀦􀀗􀀕 􀀔􀀓􀀓􀁘􀀩􀀃􀀕􀀘􀀹 􀀧􀀜 􀀶􀀷􀀷􀀫􀀔􀀯􀀓􀀙 􀀔 􀀕 􀀦􀁖􀀔 􀀔􀀓􀀓􀁑􀀃􀀙􀀖􀀓􀀹 􀀵􀀛􀀜 􀀔􀀓􀁎 􀀦􀀘􀀛 􀀓􀀑􀀖􀀖􀁘 􀀭􀀔 􀀦􀀲􀀱􀀔􀀓 􀀔 􀀕􀀖􀀗􀀘􀀙􀀚 􀀛 􀀜 􀀔􀀓 􀀦􀀘􀀘 􀀗􀀑􀀚􀁑􀀏􀀃􀀔􀀓􀀓􀀹 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀔􀀓􀀓 􀀹􀀲􀀸􀀷􀀃􀀐 􀀦􀀲􀀱􀀔 􀀔 􀀵􀀚 􀀖􀀜􀀓􀀮􀀏􀀃􀀓􀀑􀀕􀀘􀀺􀀃􀀔􀀈 􀀎 􀀦􀀘􀀔 􀀔􀀓􀀓􀁘􀀩􀀃􀀕􀀘􀀹 􀀦􀀘􀀗 􀀗􀀑􀀚􀁑􀀏􀀃􀀔􀀓􀀓􀀹 􀀧􀀔􀀕 􀀔􀀱􀀘􀀛􀀕􀀔 􀀔 􀀕 􀀦􀀖􀀛 􀀖􀀜􀀓􀀓􀁘􀀏􀀃􀀖􀀘􀀹 􀀔 􀀕 􀀵􀀕􀀘 􀀔􀀓 􀀵􀀔􀀓􀀔 􀀔􀀓 􀀦􀀕 􀀔􀀓􀀓􀁑 􀀦􀀔􀀚 􀀙􀀛􀀓􀁑 􀀧􀀔 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀯􀀖 􀀔􀀘􀀓􀁘􀀫􀀃􀀖􀀤 􀀵􀀕􀀕 􀀔􀀓 􀀵􀀛􀀔 􀀕􀀕􀁎 􀀵􀀜􀀕 􀀔􀀓􀁎 􀀦􀀖􀀚 􀀖􀀜􀀓􀀓􀁘􀀏􀀃􀀖􀀘􀀹 􀀔 􀀕 􀀦􀀖􀀔 􀀕􀀑􀀕􀁘􀀃􀀕􀀘􀀹 􀀧􀀔􀀔 􀀔􀀱􀀘􀀛􀀕􀀔 􀀔 􀀕 􀀵􀀜􀀙 􀀔􀀓􀀃􀀏􀀃􀀕􀀺 􀀰􀀔 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀵􀀜􀀛 􀀗􀀚􀁎 􀀦􀀔􀀔 􀀗􀀑􀀚􀁑 􀀦􀀘􀀙 􀀗􀀚􀀓􀁑 􀀦􀀖􀀗 􀀖􀀖􀁘􀀩􀀃􀀗􀀘􀀓􀀹 􀀔 􀀕 􀀵􀀜􀀚 􀀔􀀓􀀃􀀏􀀃􀀕􀀺 􀀵􀀛􀀛 􀀔􀀓􀁎 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀔􀀓􀀓 􀀧􀀗 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀦􀀕􀀛 􀀗􀀚􀀓􀁑􀀃􀀕􀀘􀀹 􀀦􀀔􀀛 􀀕􀀕􀁘􀀃􀀕􀀘􀀹􀀃 􀀴􀀜 􀀕􀀶􀀧􀀛􀀛􀀕 􀀦􀀔􀀕 􀀔􀀓􀀓􀁘 􀀵􀀕􀀖 􀀔􀀓 􀀕 􀀧􀀘 􀀔 􀀥􀀤􀀷􀀃􀀗􀀙 􀀦􀀙􀀓 􀀔􀀘􀀓􀁑 􀀵􀀛􀀕 􀀖􀀑􀀖􀁎 􀀵􀀜 􀀘􀀑􀀙􀀮􀀏􀀃􀀔􀀈 􀀰􀀗 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀧􀀕 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀯􀁓􀀕 􀀯􀁓􀀔 􀀯􀁖 􀀷􀀻􀀔 􀀷􀀵􀀤􀀩􀀲􀀃􀀰􀀤􀀪􀀱􀀨􀀷􀀬􀀦􀀤 􀀹􀀲􀀸􀀷􀀃􀀎 􀀦􀀲􀀱􀀔 􀀔 􀀸􀀔􀀚 􀀶􀀷􀀚􀀩􀀯􀀬􀀷􀀨􀀖􀀜􀁂􀀶􀀲􀀬􀀦􀁂􀀕􀀓􀀳 􀀹􀀶􀀶 􀀔 􀀹􀀧􀀧 􀀕 􀀵􀀨􀀶􀀨􀀷 􀀖 􀀲􀀶􀀦􀀔􀀒􀀦􀀯􀀮􀀬􀀱 􀀕􀀓 􀀲􀀶􀀦􀀕 􀀔􀀜 􀀳􀀤􀀓􀀒􀀯􀀷􀀬􀀦 􀀔􀀛 􀀳􀀤􀀔􀀒􀀤􀀷􀀬􀀦 􀀔􀀚 􀀳􀀤􀀕􀀒􀀤􀀷􀀳􀀺􀀰􀀓 􀀔􀀙 􀀳􀀤􀀖􀀒􀀤􀀷􀀳􀀺􀀰􀀔 􀀔􀀘 􀀳􀀤􀀗􀀒􀀤􀀷􀀳􀀺􀀰􀀕 􀀔􀀗 􀀳􀀤􀀘􀀒􀀤􀀷􀀳􀀺􀀰􀀖􀀒􀀬􀀦􀀦􀀧􀀤􀀷􀀤 􀀔􀀖 􀀳􀀤􀀙􀀒􀀰􀀦􀀲􀀒􀀬􀀦􀀦􀀦􀀯􀀮􀀒􀀥􀀵􀀨􀀤􀀮 􀀔􀀕 􀀳􀀤􀀚 􀀔􀀔 􀀳􀀥􀀓􀀒􀀶􀀶􀀒􀀤􀀬􀀱􀀓 􀀗 􀀳􀀥􀀔􀀒􀀶􀀦􀀮􀀒􀀤􀀬􀀱􀀔 􀀘 􀀳􀀥􀀕􀀒􀀰􀀬􀀶􀀲􀀒􀀤􀀬􀀱􀀕 􀀙 􀀳􀀥􀀖􀀒􀀰􀀲􀀶􀀬􀀒􀀤􀀬􀀱􀀖 􀀚 􀀳􀀥􀀗􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀤􀀬􀀱􀀗 􀀛 􀀳􀀥􀀘􀀒􀀤􀀬􀀱􀀘 􀀜 􀀳􀀥􀀙􀀒􀀤􀀬􀀱􀀙 􀀔􀀓 􀀵􀀕􀀓 􀀔􀀕􀀃􀀒􀀓􀀑􀀕􀀘􀀺 􀀵􀀔􀀓􀀓 􀀔􀀓 􀀸􀀔􀀙 􀀯􀀘􀀜􀀚􀀖􀀧 􀀲􀀸􀀷 􀀔 􀀶􀀼􀀱􀀦 􀀕 􀀬􀀱􀀫 􀀖 􀀦􀀲􀀰􀀳 􀀗 􀀩􀀥 􀀘 􀀹􀀵􀀨􀀩 􀀙 􀀪􀀱􀀧 􀀚 􀀹􀀦􀀦 􀀛 􀀦􀀔􀀗 􀀗􀀚􀁘􀀩􀀃􀀏􀀖􀀘􀀃􀀹􀀃􀀨􀀯􀀨􀀦 􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀵􀀜􀀜 􀀔􀀓 􀀎 􀀦􀀘􀀕 􀀔􀀓􀀓􀁘􀀩􀀃􀀕􀀘􀀹 􀀦􀀖􀀘 􀀖􀀖􀁘􀀩 􀀔 􀀕 􀀴􀀔􀀓 􀀕􀀶􀀧􀀛􀀛􀀕 􀀵􀀛􀀚 􀀔􀀓􀁎 􀀰􀀙 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀦􀀗􀀔 􀀔􀀓􀀓􀁓 􀀦􀀘􀀚 􀀔􀀓􀀓􀁑 􀀵􀀔􀀓􀀗 􀀔􀀓 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀔􀀓􀀓 􀀕 􀀧􀀙 􀀔 􀀥􀀤􀀷􀀃􀀗􀀙 􀀵􀀔􀀓􀀕 􀀔􀀓 􀀰􀀕 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀵􀀛􀀖 􀀖􀀜􀁎 􀀧􀀖 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀡􀀭􀀑􀀑􀀑􀀑􀀖􀁖􀀑 AN2794 Schematic description Doc ID 14827 Rev 2 25/39 The PWM modulation of the H-bridge inverter is implemented on an ST7lite39 microcontroller connected to the gate drive circuit composed of two L6386, as shown in the schematic in Figure 11. The auxiliary power supply section consists of an L5973D and an L7805, used to implement a buck-boost converter to decrease the battery voltage from 24 V to 15 V and from 15 V to 5 V respectively. Experimental results AN2794 26/39 Doc ID 14827 Rev 2 4 Experimental results Typical voltage and current waveforms of the DC-AC converter and the efficiency curves of the push-pull DC-DC stage, measured at different input voltages, are shown below. In particular, Figure 12 and Figure 13 show both input and output characteristic waveforms of the DC-DC converter both in light load and full load condition. The HF transformer leakage inductance, which is about 1% of the magnetizing inductance, is the cause of severe ringing across the input and the output power devices. MOSFETs voltage and current waveforms with and without the connection of a snubber network are shown in Figure 14 and 15, while Figure 16 and 17 show the effect of the RCD clamp circuit connected across the rectifier bridge output. In Figure 18 the current and the voltage across one of the three parallel-connected MOSFETs, powering each of the two windings of the transformer are shown, while in Figure 19 it is possible to observe the variation of the inverter output voltage and current together with the DC-DC converter bus voltage. In Figure 20, 21, 22, 23 and 24, the efficiency curves of the push-pull converter measured with an RL load are given. A maximum efficiency above 93% has been measured at nominal input voltage and 640 W output power. The minimum value of efficiency has been tested under low load and maximum input voltage. In Figure 25, the efficiency of the whole board is shown. The efficiency tests have been carried out connecting an RL load at the inverter output connectors, with 3 mH output inductor. Figure 12. Characteristic waveforms (measured at 24 V input voltage and 280 W resistive load) Figure 13. Characteristic waveforms (measured at 28 V input voltage and 1000 W resistive load) Ch1 and Ch2: MOSFETs drain source voltage; Ch4: HF transformer output voltage; Ch3: filter inductor current Ch1 and Ch2: MOSFETs drain source voltage; Ch3: filter inductor current AN2794 Experimental results Doc ID 14827 Rev 2 27/39 Figure 14. MOSFET voltage (ch4) and current (ch3) without RC snubber Figure 15. MOSFET voltage (ch4) and current (ch3) with RC snubber Figure 16. Rectifier diode current (ch3) and voltage (ch4) without RDC snubber Figure 17. Rectifier diode current (ch3) and voltage (ch4) with RDC snubber Experimental results AN2794 28/39 Doc ID 14827 Rev 2 Figure 18. Ch1, ch3 MOSFETs drain current, ch2, ch4 MOSFET drain-source voltage Figure 19. Startup, ch2, ch3 inverter voltage and current, ch4 DC bus voltage Figure 20. DC-DC converter efficiency with 20 V input Figure 21. DC-DC converter efficiency with 22 V input Figure 22. DC-DC converter efficiency with 24 V input Figure 23. DC-DC converter efficiency with 26 V input 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00636v1 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00637v1 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00638v1 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00639v1 AN2794 Experimental results Doc ID 14827 Rev 2 29/39 Figure 24. DC-DC converter efficiency with 28 V input Figure 25. Converter efficiency 0.75 0.8 0.85 0.9 0.95 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00640v1 87 88 89 90 91 92 93 0 200 400 600 800 1000 Output Power [W] Effciency % AM00641v1 Conclusion AN2794 30/39 Doc ID 14827 Rev 2 5 Conclusion The theoretical analysis, design and implementation of a DC-AC converter, consisting of a push-pull DC-DC stage and a full-bridge inverter circuit, have been evaluated. Due to the use of the parallel connection of three STP160N75F3 MOSFETs the converter shows good performance in terms of efficiency. Moreover the use of an ST7lite39 8-bit microcontroller allows achieving simple control of the IGBTs used to implement the DC-AC stage. Any additional feature, such as regulation of the AC output voltage or protection requirements, can simply be achieved with firmware development. 6 Bibliography 1. Power Electronics: Converters, Applications and Design 2. Transformer and Inductor Design Handbook, Second Edition 3. Magnetic Core Selection for Transformers and Inductors, Second Edition 4. Switching Power Supply Design. New York. AN2794 Component list Doc ID 14827 Rev 2 31/39 Appendix A Component list Table 7. Bill of material (BOM) Component Part value Description Supplier Cs1 100 nF, 630 V Polip. cap., MKP series EPCOS Cs2 100 nF, 630 V Polip. cap., MKP series EPCOS C1 100 nF, 50 V X7R ceramic cap.., B37987 series EPCOS C2 100 nF, 50 V X7R ceramic cap., B37987 series EPCOS C57 100 nF, 50 V X7R ceramic cap., B37987 series EPCOS C59 100 nF, 50 V X7R ceramic cap., B37987 series EPCOS C10 47 μF, 35 V SMD tantalum capacitor TAJ series AVX C11 4.7 nF, 25 V SMD multilayer ceramic capacitor muRata C12 100 μF, 25 V SMD X7R ceramic cap. C3225 series; size 1210 TDK C14 47 μF, 35 V SMD tantalum capacitor TAJ series AVX C16 100 pF, 25 V SMD multilayer ceramic capacitor muRata C41 100 pF, 50 V General purpose ceramic cap., radial AVX C17 680 nF, 25 V SMD multilayer ceramic capacitor muRata C18 22 μF, 25 V Electrolytic cap FC series Panasonic C19 22 μF, 25 V Electrolytic cap. FC series Panasonic C26 2.2 μF, 25 V X7R ceramic cap., B37984 series EPCOS C31 2.2 μF, 25 V X7R ceramic cap., B37984 series EPCOS C28 470 nF, 25 V X7R ceramic cap., B37984 series EPCOS C33 470 nF, 25 V X7R ceramic cap., B37984 series EPCOS C34 33 μF, 450 V Electrolytic cap. B43821 series EPCOS C35 33 μF, 450 V Electrolytic cap. B43821 series EPCOS C37 3900 μF, 35 V Elec. capacitor 0.012 Ω, YXH series Rubycon C38 3900 μF, 35 V Elec. capacitor 0.012 Ω, YXH series Rubycon C39 150 μF, 35 V Electrolytic cap. fc series Panasonic C40 22 nF, 50 V General purpose ceramic cap., radial AVX C42 100 μF, 25 V Electrolytic cap. fc series Panasonic C51 100 μF, 25 V Electrolytic cap.fc series Panasonic C52 100 μF, 25 V Electrolytic cap.fc series Panasonic C53 2.2 μF, 450 V Elcrolytic capactor B43851 series EPCOS C54 4.7 nF, 100 V Polip. cap., MKT series EPCOS C55 4.7 nF, 100 V Polip. cap., MKT series EPCOS C56 470 nF, 50 V X7R ceramic cap., B37984 series EPCOS Component list AN2794 32/39 Doc ID 14827 Rev 2 C58 0.33 μF, 50 V X7R ceramic cap., B37984 series EPCOS C60 150 nF, 50 V SMD multilayer ceramic capacitor muRata D1 STTH8R06D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D2 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D3 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D4 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D13 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D5 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D6 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D8 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D7 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D9 STTH1L06 Ultrafast high voltage rectifier; DO-41 STMicroelectronics D10 STTH1L06 Ultrafast high voltage rectifier; DO-41 STMicroelectronics D11 1N5821 Schottky rectifier; DO-221AD STMicroelectronics D12 1N5821 Schottky rectifier; DO-221AD STMicroelectronics VOUT AC 1 CON1 FASTON RS components VOUT AC 2 CON1 FASTON RS components VOUT - CON1 FASTON RS components VOUT + CON1 FASTON RS components VIN CON1 FASTON RS components GND CON1 FASTON RS components IC1 L6386D High-voltage high and low side driver; dip-14 STMicroelectronics IC2 L6386D High-voltage high and low side driver; dip-14 STMicroelectronics IGBT LOW 1 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics IGBT HIGH 1 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics IGBT LOW 2 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics IGBT HIGH 2 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics J1 CON10 10-way idc connector commercial box header series Tyco Electronics L3 150 μH, 3 A Power use SMD inductor; SLF12575T series TDK L4(1) 1174.0018 ST04 1.5 mH, filter inductor MAGNETICA M1 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M2 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M3 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics Table 7. Bill of material (BOM) (continued) Component Part value Description Supplier AN2794 Component list Doc ID 14827 Rev 2 33/39 M4 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M5 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M6 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics Q8 STN4NF03L N-channel 30 V , 6.5 A SOT-223 STripFET™ II Power MOSFET STMicroelectronics Q9 2SD882 NPN Power BJT 30 V, 3 A transistor- SOT-32 STMicroelectronics Q10 2SD882 NPN Power BJT 30 V, 3 A transistor- SOT-32 STMicroelectronics Q11 2SB772 NPN Power BJT 30 V, 3 A transistor - SOT-32 STMicroelectronics Q12 2SB772 NPN Power BJT 30 V, 3 A transistor - SOT-32 STMicroelectronics RGATE IGBT LOW 1 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components RGATE IGBT HIGH 1 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components RGATE IGBT LOW 2 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components RGATE IGBT HIGH 2 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R7 390 kΩ SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R9 5.6 kΩ SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R20 12 Ω SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R21 R22 10 Ω SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R23 R24 R25 R99 R100 R101 R102 R103 R104 R81 22 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm R82 3.3 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm R83 39 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm R87 10 kΩ SMD standard film res - 1/8 W - 1% - 100ppm/°C BC components Table 7. Bill of material (BOM) (continued) Component Part value Description Supplier Component list AN2794 34/39 Doc ID 14827 Rev 2 R88 10 kΩ SMD standard film res - 1/8 W - 1% - 100ppm/°C BC components R89 R90 R91 R92 R93 1.5 kΩ SMD standard film res - 1/8 W – 1% - 100ppm/°C BC components R94 470 Ω High voltage 17 W ceramic resistor sbcv type Meggit CGS R95 470 Ω High voltage 17 W ceramic resistor sbcv type Meggit CGS R96 10 Ω Standard film res – 2 W 5%, axial 05 T-Ohm R97 R98 47 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm TX1(2) 1356.0004 rev.01 Power transformer MAGNETICA U1 SG3525 Pulse width modulator SO-16 (narrow) STMicroelectronics U16 L5973D 2.5 A switch step down regulator; HSOP8 STMicroelectronics U17 ST7FLITE39F2 8-bit microcontroller; SO-20 STMicroelectronics U20 L7805 Positive voltage regulator; D2PAK STMicroelectronics 124 HEAT SINK Part n. 78185, S562 cooled package TO-220; thermal res. 7.52 °C/W at length 70 mm width 40 mm height 57 mm Aavid Thermalloy 125 HEAT SINK Part n. 78350, SA36 cooled package TO-220; thermal res. 1.2°C/W at length 135 mm width 49.5 mm height 85.5 mm Aavid Thermalloy 126 1. The technical specification for this component is provided in Figure 26. 2. The technical specification for this component is provided in Figure 27. Table 7. Bill of material (BOM) (continued) Component Part value Description Supplier AN2794 Product technical specification Doc ID 14827 Rev 2 35/39 Appendix B Product technical specification Figure 26. Technical specification for 1.5 mH 2.5 A inductor L4 (produced by MAGNETICA) TYPICAL APPLICATION INDUCTOR FOR DC/DC CONVERTERS AS BUCK, BOOST E BUCK-BOOST CONVERTERS. ALSO SUITABLE IN HALFBRIDGE, PUSH-PULL AND FULL-BRIDGE APPLICATIONS TECHNICAL DATA INDUCTANCE 1.5mH ±15% (MEASURE 1KHZ, TA 20°C) RESISTANCE 0.52 max (MEASURE DC, TA 20°C) OPERATING VOLTAGE 800 VP MAX (F 100K HZ, IR 2.5A, TA 20°C) OPERATING VOLTAGE 2.5 A MAX (MEASURE DC 800 VP, TA 20°C) SATURATION CURRENT 4.5 A NOM (MEASURE DC, L 50%NOM, TA 20°C) SELF-RESONANT FREQUENY 1MHZ NOM (TA 20°C) OPERATING TEMPERATURE RANGE -10°C÷+45°C (IR 2.5 A MAX) DIMENSIONS 45X20 H46mm WEIGHT 78g CIRCA SCHEMATIC INDUCTANCE VS CURRENT INDUCTANCE VS FREQUENCY DIMENSIONAL DRAWING DIMENSIONS IN MM, DRAWING NOT IN SCALE 1 3 10% 100% 0 1 2 3 4 5 6 L I [A] 0% 50% 100% 150% 200% 250% 0 200 400 600 800 1000 L/L(1kHz) f [kHz] 1 2 2 3 3 min 1 45 max 46 max 20 max 0.8 (X4), RECOMMENDED PCB HOLE 1.2 (X4) 2 3 4 BOTTOM VIEW (PIN SIDE) 12.7 10.16 30.48 Product technical specification AN2794 36/39 Doc ID 14827 Rev 2 Figure 27. Technical specification for 1 kW, 100 kHz switch mode power transformer TX1 (produced by MAGNETICA) TYPICAL APPLICATION TRANSFORMER TO POWER APPLICATIONS WITH HALF - BRIDGE , PUSH -PULL E FULL -BRIDGE TYPOLOGY . TECHNICAL DATA INDUCTANCE (MEASURE 1KHZ, TA 20°C) PIN 1,2 – 3,4,5 17.2 uH MIN PIN 3,4,5 – 6,7 17.2 uH MIN PIN 9 – 13 (10-12 IN CC ) 5.7 mH MIN R ESISTANCE (MEASURE D .C, TA 20°C) PIN 1,2 – 3,4,5 6 mΩ MAX PIN 3,4,5 – 6,7 6 mΩ MAX PIN 9 – 13 (10-12 IN CC ) 90 mΩ MAX TRANSFORMER RATIO (MEASURE 10KHZ, 10-12 IN CC , TA 20°C) PIN 13 – 9 ⇔ 1,2 – 3,4,5 18 ± 5% PIN 13 – 9 ⇔ 3,4,5 – 6,7 18 ± 5% L EAKAGE INDUCTANCE 0.11 % NOM (MEASURE 9-13, 1-2-3-4-5-6-7 AND 10-12 IN C .C, F 10KHZ, TA 20°C) OPERATING VOLTAGE 800 VP MAX (MEASURE 13-9, 10-12 IN CC , F 100KHZ , DUTY CYCLE 0.8,T A 20°C) OPERATING CURRENT 2.5 A MAX (MEASURE 13-9 WITH 1-2-3-4-5-6-7 IN CC , PMAX 1KW ,F 100 KHZ, TA 20°C) OPERATING FREQUENCY 100KHZ NOM (P MAX 1KW , TA 20°C) OPERATING TEMPERATURE RANGE -10°C ÷+45°C (P MAX 1KW, F 100KHZ ) INSULATION CLASS I ( PMAX 1KW, TA 20°C ) P RIMARY TO SECONDARY INSULATION 2500V (F 50H Z,DURATION TEST 2”, TA 20°C) MAXIMUM DIMENSIONS 57X57H45 mm WEIGHT 292g CIRCA SCHEMATIC PRODUCT PICTURE PIN DESCRIPTION PIN (*) FUNCTION PIN (*) FUNCTION 1A P RIMARY DRAIN A 8 NOT USED 2A P RIMARY DRAIN A 9 SECONDARY GROUND 3B PRIMARY +VB 24V 10D INTERMEDIARY S ECONDARY ACCESS 4B 11 MISSING , REFERENCE TO PCB ASSEMBLING 5B 12D INTERMEDIARY S ECONDARY ACCESS 6C P RIMARY DRAIN B 13 S ECONDARY 400V 2.5A 7C P RIMARY DRAIN B 14 NOT USED (*)P IN WITH THE SAME SUBSCRIPT MU ST BE CONNECTED TOGETHER ON PCB 13 12 1 2 3 4 5 6 7 10 9 AN2794 Product technical specification Doc ID 14827 Rev 2 37/39 Figure 28. Dimensional drawing 7 8 55.5 max 3 min ı 1.0, Recommended PCB hole ı 1.4 56.5 max 14 13 12 4 10 9 8 1356.0004 SMT 1kW 100kHz MAGNETICA 08149 BOTTOM VIEW (PIN SIDE ) 40 5 1 7 8 14 MISSING PIN REFERENCE AS PCB ASSEMBLING Revision history AN2794 38/39 Doc ID 14827 Rev 2 7 Revision history Table 8. Document revision history Date Revision Changes 16-Feb-2009 1 Initial release 13-Jan-2012 2 – Introduction modified – Section 3 modified AN2794 Doc ID 14827 Rev 2 39/39 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com STEVAL-TDR027V1 Portable UHF 2-way radio demonstration board based on the PD84008L-E Features ■ Excellent thermal stability ■ Frequency: 380 - 512 MHz ■ Supply voltage: 7.2 V ■ Output power: > 6 W ■ Power gain: 11.7 ± 0.5 dB ■ Efficiency: 46% - 71% ■ Load mismatch: 20:1 all phases ■ BeO-free amplifier Description The STEVAL-TDR027V1 demonstration board is a portable UHF 2-way radio designed as a platform for evaluating the performance of the PD84008L-E LDMOS RF power transistor. Table 1. Device summary Part number STEVAL-TDR027V1 Mechanical specification: L = 60 mm, W = 30 mm www.st.com Contents STEVAL-TDR027V1 2/11 Doc ID 18109 Rev 1 Contents 1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Circuit photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STEVAL-TDR027V1 Electrical characteristics Doc ID 18109 Rev 1 3/11 1 Electrical characteristics TA = +25 oC, VDD = 7.2 V, Idq = 200 mA Table 2. Electrical specification Symbol Test conditions Min Typ Max Unit Freq Frequency range 380 512 MHz POUT @ PIN = 27 dBm 6 W Gain @ PIN = 27 dBm 11.7 ± 0.5 dB ND @ PIN = 27 dB 46 - 71 % H2 2nd harmonic @ PIN = 27 dB -38 / -70 dBc H3 3rd harmonic @ PIN = 27 dB -60 / -70 dBc VSWR Load mismatch all phases @ POUT = 6 W 20:1 Impedance STEVAL-TDR027V1 4/11 Doc ID 18109 Rev 1 2 Impedance Figure 1. Impedance diagram Table 3. Impedance data F (MHz) ZGS ZDL 380 3,3 + j6,2 2,2 - j0,7 390 3,6 + j6,7 2,2 - j0,4 400 4,1 + j7,1 2,2 - j0,1 410 4,6 + j7,4 2,2 + j0,2 420 5,3 + j7,5 2,2 + j0,5 430 6,2 + j7,3 2,3 + j0,8 440 6,8 + j6,6 2,4 + j1,0 450 7,0 + j5,4 2,4 + j1,3 460 6,4 + j4,2 2,6 + j1,5 470 5,2 + j3,6 2,7 + j1,6 480 3,9 + j3,7 2,8 + j1,7 490 2,8 + j4,2 2,9 + j1,8 500 2,1 + j4,9 3,0 + j1,9 510 1,6 + j5,6 3,1 + j1,8 520 1,3 + j6,3 3,2 + j1,7 STEVAL-TDR027V1 Typical performance Doc ID 18109 Rev 1 5/11 3 Typical performance Figure 2. Output power and efficiency vs. frequency (pin=27 dBm) Figure 3. Output power and efficiency vs. frequency (pin=28 dBm) Figure 4. Gain vs. frequency Figure 5. Gain vs. Pout Fig Typical performance STEVAL-TDR027V1 6/11 Doc ID 18109 Rev 1 Figure 8. Harmonics vs. frequency 􀀫􀀕 􀀫􀀖 􀀡􀀭􀀐􀀖􀀐􀀑􀀖􀁖􀀑 STEVAL-TDR027V1 Test circuit Doc ID 18109 Rev 1 7/11 4 Test circuit Figure 9. Test circuit schematic diagram + TL5 TL6 C12 C13 RFout C11 L4 C10 L3 C9 C6 RFin TL1 TL2 C8 PD84008L-E LDMOS R2 R1 R3 C7 L2 L1 C2 C1 Vcc 2 - 1 + B2 C3 C4 C5 TL4 TL3 D1 FR4 H=60 mil MSub B1 Table 4. Component list Component ID Description Value Case size Manufacturer Part code B1 Ferrite bead Panasonic EXCELDRC35C B2 Panasonic EXCELDRC35C C1, C2 Capacitor 120 pF 1206 MURATA GRM42-6 COG 121J 50_ C3 1 nF 1206 MURATA GRM42-6 COG 102J 50 C4 100 nF 1206 MURATA GRM42-6_X7R 104K 50_ C5 10 uF SMT Panasonic EEVHB1V100P C6, C13 33 pF 100B ATC ATC 100B 330JW C7 22 pF 100B ATC ATC 100B 220JW C8 47 pF 100B ATC ATC 100B 470JW C9 39 pF 100B ATC ATC 100B 390JW C10 15 pF 100B ATC ATC 100B 150JW C11 6.8 pF 100B ATC ATC 100B 6R8BW C12 2.2 pF 100B ATC ATC 100B 2R2BW D1 Zener diode 5.1 V SOD110 Philips BZX284C5V1 L1 Inductor 18.5 nH Coilcraft A05T L2 5 nH Coilcraft A02T L3, L4 2.5 nH Coilcraft A01T R1 Resistor 1 kΩ 1206 Tyco Electronics 01623440-1 Test circuit STEVAL-TDR027V1 8/11 Doc ID 18109 Rev 1 R2 Potentiometer 10 kΩ Bourns Electronics 3214W-1-103E R3 Resistor 560 Ω 1206 Bourns Electronics TL1 Transmission line W=2.87 mm L=7.4 mm TL2 W=2.87 mm L=5.0 mm TL3 W=4.98 mm L=4.8 mm TL4 W=4.98 mm L=4.0 mm TL5 W=2.87 mm L=1.5 mm TL6 W=2.87 mm L=6.1 mm PD84008L LDMOS STMicroelectronics PD84008L-E Board FR-4 THk=0.060" 2OZ Cu both sides Table 4. Component list (continued) Component ID Description Value Case size Manufacturer Part code STEVAL-TDR027V1 Board photo Doc ID 18109 Rev 1 9/11 5 Board photo Figure 10. STEVAL-TDR027V1 demonstration board Revision history STEVAL-TDR027V1 10/11 Doc ID 18109 Rev 1 6 Revision history Updated Table 5. Document revision history Date Revision Changes 18-Oct-2010 1 Initial release. STEVAL-TDR027V1 Doc ID 18109 Rev 1 11/11 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com L6384E High voltage half-bridge driver Datasheet - production data Features  High voltage rail up to 600 V  dV/dt immunity ± 50 V/nsec in full temperature range  Driver current capability – 400 mA source – 650 mA sink  Switching times 50/30 nsec rise/fall with 1 nF load  CMOS/TTL Schmitt trigger inputs with hysteresis and pull-down  Shutdown input  Deadtime setting  Undervoltage lockout  Integrated bootstrap diode  Clamping on VCC  Available in DIP-8/SO-8 packages Applications  Home appliances  Induction heating  HVAC  Industrial applications and drives  Motor drivers – DC, AC, PMDC and PMAC motors  Lighting applications  Factory automation  Power supply systems Description The L6384E is a high voltage gate driver, manufactured with the BCD™ “offline” technology, and able to drive a half-bridge of power MOS or IGBT devices. The high-side (floating) section is enabled to work with voltage rail up to 600 V. Both device outputs can sink and source 650 mA and 400 mA respectively and cannot be simultaneously driven high thanks to an integrated interlocking function. Further prevention from outputs cross conduction is guaranteed by the deadtime function, tunable by the user through an external resistor connected to the DT/SD pin. The L6384E device has one input pin, one enable pin (DT/SD) and two output pins, and guarantees matched delays between low-side and high-side sections, thus simplifying device's high frequency operation. The logic inputs are CMOS/TTL compatible to ease the interfacing with controlling devices. The bootstrap diode is integrated inside the device, allowing a more compact and reliable solution. The L6384E features the UVLO protection and a voltage clamp on the VCC supply voltage. The voltage clamp is typically around 15.6 V and is useful in order to ensure a correct device functioning in cases where VCC supply voltage is ramped up too slowly or is subject to voltage drops. The device is available in a DIP-8 tube and SO-8 tube and tape and reel packaging options. DIP-8 SO-8 Table 1. Device summary Part number Package Packaging L6384E DIP-8 Tube L6384ED SO-8 Tube L6384ED013TR SO-8 Tape and reel www.st.com Contents L6384E 2/15 DocID13862 Rev 2 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DocID13862 Rev 2 3/15 L6384E Block diagram 15 1 Block diagram Figure 1. Block diagram LOGIC UV DETECTION LEVEL SHIFTER R S VCC LVG DRIVER VCC IN DT/SD VBOOT HVG DRIVER HVG H.V. LOAD OUT LVG GND D97IN518A DEAD TIME VCC Idt Vthi BOOTSTRAP DRIVER CBOOT 4 3 5 6 7 8 1 2 Electrical data L6384E 4/15 DocID13862 Rev 2 2 Electrical data 2.1 Absolute maximum ratings 2.2 Thermal data 2.3 Recommended operating conditions Table 2. Absolute maximum ratings Symbol Parameter Value Unit Vout Output voltage -3 to Vboot -18 V Vcc Supply voltage(1) 1. The device has an internal clamping Zener between GND and the Vcc pin, It must not be supplied by a low impedance voltage source. - 0.3 to 14.6 V Is Supply current(1) 25 mA Vboot Floating supply voltage -1 to 618 V Vhvg High-side gate output voltage -1 to Vboot V Vlvg Low-side gate output voltage -0.3 to Vcc +0.3 V Vi Logic input voltage -0.3 to Vcc +0.3 V Vsd Shutdown/deadtime voltage -0.3 to Vcc +0.3 V dVout/dt Allowed output slew rate 50 V/ns Ptot Total power dissipation (Tj = 85 °C) 750 mW TJ Junction temperature 150 °C Ts Storage temperature -50 to 150 °C Table 3. Thermal data Symbol Parameter SO-8 DIP-8 Unit Rth(JA) Thermal resistance junction to ambient 150 100 °C/W Table 4. Recommended operating conditions Symbol Pin Parameter Test condition Min. Typ. Max. Unit Vout 6 Output voltage (1) 1. If the condition Vboot - Vout < 18 V is guaranteed, Vout can range from -3 to 580 V. 580 V VBS (2) 2. VBS = Vboot - Vout. 8 Floating supply voltage (1) 17 V fsw Switching frequency HVG, LVG load CL = 1 nF 400 kHz Vcc 2 Supply voltage Vclamp V Tj Junction temperature -45 125 °C DocID13862 Rev 2 5/15 L6384E Pin connection 15 3 Pin connection Figure 2. Pin connection (top view) IN VCC DT/SD GND 1 3 2 4 LVG VOUT HVG 8 VBOOT 7 6 5 D97IN519 Table 5. Pin description No. Pin Type Function 1 IN I Logic input: it is in phase with HVG and in opposition of phase with LVG. It is compatible to VCC voltage. (Vil Max = 1.5 V, Vih Min = 3.6 V). 2 VCC P Supply input voltage: there is an internal clamp [typ. 15.6 V]. 3 DT/SD I High impedance pin with two functionalities. When pulled lower than Vdt (typ. 0.5 V), the device is shut down. A voltage higher than Vdt sets the deadtime between the high-side gate driver and low-side gate driver. The deadtime value can be set forcing a certain voltage level on the pin or connecting a resistor between the pin 3 and ground. Care must be taken to avoid below threshold spikes on the pin 3 that can cause undesired shutdown of the IC. For this reason the connection of the components between the pin 3 and ground has to be as short as possible. This pin can not be left floating for the same reason. The pin has not be pulled through a low impedance to VCC, because of the drop on the current source that feeds Rdt. The operative range is: Vdt … 270 K Idt, that allows a dt range of 0.4 - 3.1 s. 4 GND P Ground 5 LVG O Low-side driver output: the output stage can deliver 400 mA source and 650 mA sink (typ. values). The circuit guarantees 0.3 V max. on the pin (at Isink = 10 mA) with VCC > 3 V and lower than the turn-on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 6 Vout P High-side driver floating reference: layout care has to be taken to avoid below ground spikes on this pin. 7 HVG O High-side driver output: the output stage can deliver 400 mA source and 650 mA sink (typ. values). The circuit guarantees 0.3 V max. between this pin and Vout (at Isink = 10 mA) with VCC > 3 V and lower than the turn-on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 8 Vboot P Bootstrap supply voltage: it is the high-side driver floating supply. The bootstrap capacitor connected between this pin and the pin 6 can be fed by an internal structure named “bootstrap driver” (a patented structure). This structure can replace the external bootstrap diode. Electrical characteristics L6384E 6/15 DocID13862 Rev 2 4 Electrical characteristics 4.1 AC operation 4.2 DC operation Table 6. AC operation electrical characteristics (VCC = 14.4V; TJ = 25°C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit ton 1 vs. 5, 7 High/low-side driver turn-on propagation delay Vout = 0 V Rdt= 47 k 200+ dt ns tonsd 3 vs. 5, 7 Shutdown input propagation delay 220 280 ns toff 1 vs. 5, 7 High/low-side driver turn-off propagation delay Vout = 0 V Rdt = 47 k 250 300 ns Vout = 0 V Rdt = 146 k 200 250 ns Vout = 0 V Rdt = 270 k 170 200 ns tr 5, 7 Rise time CL = 1000 pF 50 ns tf 5, 7 Fall time CL = 1000 pF 30 ns Table 7. DC operation electrical characteristics (VCC = 14.4 V; TJ = 25 °C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Supply voltage section Vclamp 2 Supply voltage clamping Is = 5 mA 14.6 15.6 16.6 V Vccth1 2 VCC UV turn-on threshold 11.5 12 12.5 V Vccth2 2 VCC UV turn-off threshold 9.5 10 10.5 V Vcchys VCC UV hysteresis 2 V Iqccu Undervoltage quiescent supply current Vcc 11 V 150 A Iqcc Quiescent current Vin = 0 380 500 A Bootstrapped supply voltage section Vboot 8 Bootstrap supply voltage 17 V IQBS Quiescent current IN = HIGH 100 A ILK High voltage leakage current Vhvg = Vout = Vboot = 600 V 10 A Rdson Bootstrap driver on-resistance(1) Vcc 12.5 V; IN = LOW 125  High/low-side driver Iso 5, 7 Source short-circuit current VIN = Vih (tp < 10 s) 300 400 mA Isi Sink short-circuit current VIN = Vil (tp < 10 s) 500 650 mA DocID13862 Rev 2 7/15 L6384E Electrical characteristics 15 4.3 Timing diagram Figure 3. Input/output timing diagram Symbol Pin Parameter Test condition Min. Typ. Max. Unit Logic inputs Vil 1, 3 Low level logic threshold voltage 1.5 V Vih High level logic threshold voltage 3.6 V Iih High level logic input current VIN = 15 V 50 70 A Iil Low level logic input current VIN = 0 V 1 A Iref 3 Deadtime setting current 28 A dt 3 vs. 5, 7 Deadtime setting range(2) Rdt = 47 k Rdt = 146 k Rdt = 270 k 0.4 0.5 1.5 2.7 3.1 s s s Vdt 3 Shutdown threshold 0.5 V 1. RDS(on) is tested in the following way: Where I1 is the pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 2. The pin 3 is a high impedance pin. Therefore dt can be set also forcing a certain voltage V3 on this pin. The deadtime is the same obtained with an Rdt if it is: Rdt × Iref = V3. Table 7. DC operation electrical characteristics (continued)(VCC = 14.4 V; TJ = 25 °C) RDSON VCC – VCBOOT1 – VCC – VCBOOT2 = I--1------V----C----C---,--V-----C---B----O----O----T---1-------–----I--2-----V-----C---C----,--V----C----B----O----O----T---2---- IN SD HVG LVG D99IN1017 Bootstrap driver L6384E 8/15 DocID13862 Rev 2 5 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6384E device a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn-on. CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. E.g.: HVG steady state consumption is lower than 100 A, so if HVG TON is 5 ms, CBOOT has to supply 0.5 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 0.5 V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has a great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 2 where Qgate is the gate charge of the external power MOS, Rdson is the on-resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. CEXT Qgate Vgate = -------------- Vdrop Ich argeRdson  Vdrop Qgate Tch arge = = -------------------Rdson DocID13862 Rev 2 9/15 L6384E Bootstrap driver 15 For example: using a power MOS with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact: Equation 3 Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 4. Bootstrap driver Vdrop 30nC 5s = --------------  125  0.8V TO LOAD D99IN1067 H.V. HVG a b LVG HVG LVG CBOOT TO LOAD H.V. CBOOT DBOOT VS VBOOT VS VOUT VBOOT VOUT Typical characteristic L6384E 10/15 DocID13862 Rev 2 6 Typical characteristic Figure 5. Typical rise and fall times vs. load capacitance Figure 6. Quiescent current vs. supply voltage Figure 7. Deadtime vs. resistance Figure 8. Driver propagation delay vs. temperature Figure 9. Deadtime vs. temperature Figure 10. Shutdown threshold vs. temperature For both high and low side buffers @25°C Tamb 0 1 2 3 4 5 C (nF) 0 50 100 150 200 250 time (nsec) Tr D99IN1015 Tf 0 2 4 6 8 10 12 14 VS(V) 10 102 103 104 Iq (μA) D99IN1016 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 dt (s) Rdt (k) Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 0 100 200 300 400 Ton,Toff (ns) @ Rdt = 47kOhm @ Rdt = 146kOhm @ Rdt = 270kOhm Tj (°C) Typ. Typ. Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 Tj (°C) 0 0.5 1 1.5 2 2.5 3 dt (s) R=47K R=146K Typ. R=270K Typ. Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 Vdt (V) Tj (°C) Typ. @ Vcc = 14.4V DocID13862 Rev 2 11/15 L6384E Typical characteristic 15 Figure 11. VCC UV turn-on vs. temperature Figure 12. Output source current vs. temperature Figure 13. VCC UV turn-off vs. temperature Figure 14. Output sink current vs. temperature -45 -25 0 25 50 75 100 125 10 11 12 13 14 15 Vccth1 (V) Tj (°C) Typ. -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 Current (mA) Tj (°C) Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 8 9 10 11 12 13 Vccth2 (V) Tj (°C) Typ. -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 Current (mA) Tj (°C) Typ. @ Vcc = 14.4V Package information L6384E 12/15 DocID13862 Rev 2 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 15. DIP-8 package outline Table 8. DIP-8 package mechanical data Symbol Dimensions (mm) Dimensions (inch) Min. Typ. Max. Min. Typ. Max. A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 0.125 0.150 Z 1.52 0.060 DocID13862 Rev 2 13/15 L6384E Package information 15 Figure 16. SO-8 package outline Table 9. SO-8 package mechanical data Symbol Dimensions (mm) Dimensions (inch) Min. Typ. Max. Min. Typ. Max. A 1.750 0.0689 A1 0.100 0.250 0.0039 0.0098 A2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 D(1) 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides). 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(2) 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. 3.800 3.900 4.000 0.1496 0.1535 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 L 0.400 1.270 0.0157 0.0500 L1 1.040 0.0409 k 0° 8° 0° 8° ccc 0.100 0.0039 􀀤􀀰􀀔􀀔􀀚􀀘􀀚􀁙􀀔 Revision history L6384E 14/15 DocID13862 Rev 2 8 Revision history Table 10. Document revision history Date Revision Changes 12-Oct-2007 1 First release 20-Jun-2014 2 Added Section : Applications on page 1. Updated Section : Description on page 1 (replaced by new description). Updated Table 1: Device summary on page 1 (moved from page 15 to page 1, updated title). Updated Figure 1: Block diagram on page 3 (moved from page 1 to page 3, numbered and added title to Section 1: Block diagram on page 3). Updated Section 2.1: Absolute maximum ratings on page 4 (removed note below Table 2: Absolute maximum ratings). Updated Table 5: Pin description on page 5 (updated “Type” of several pins). Updated Table 7 on page 6 (updated “Max.” value of IQBS symbol). Updated Section : CBOOT selection and charging on page 8 (updated values of “E.g.: HVG”). Numbered Equation 1 on page 8, Equation 2 on page 8 and Equation 3 on page 9. Updated Section 7: Package information on page 12 [updated/added titles, updated ECOPACK text, reversed order of Figure 15 and Table 8, Figure 16 and Table 9 (numbered tables), removed 3D package figures, minor modifications]. Minor modifications throughout document. DocID13862 Rev 2 15/15 L6384E 15 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com ULQ2001 ULQ2003 - ULQ2004 Seven Darlington array Features ■ Seven Darlington per package ■ Extended temperature range: -40 to 105 °C ■ Output current 500 mA per driver (600 mA peak) ■ Output voltage 50 V ■ Automotive Grade product in SO16 package ■ Integrated suppression diodes for inductive loads ■ Outputs can be paralleled for higher current ■ TTL/CMOS/PMOS/DTL compatible inputs ■ Inputs pinned opposite outputs to simplify layout Description The ULQ2001, ULQ2003 and ULQ2004 are high voltage, high current Darlington arrays each containing seven open collector Darlington pairs with common emitters. Each channel rated at 500 mA and can withstand peak currents of 600 mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The versions interface to all common logic families. These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal print-heads and high power buffers. The ULQ2001A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package (SO16) as ULQ2003D1/2004D1. The ULQ2003 is available as Automotive Grade in SO16 package. The commercial part numbers is shown in the order codes. This device is qualified according to the specification AEC-Q100 of the Automotive market, in the temperature range -40 °C to 125 °C and the statistical tests PAT, SYL, SBL are performed. DIP-16 SO16 (Narrow) Table 1. Device summary Part numbers Order codes Description Packages ULQ2001 ULQ2001A General purpose, DTL, TTL, PMOS, CMOS DIP-16 ULQ2003 ULQ2003A 5 V TTL, CMOS DIP-16 ULQ2004 ULQ2004A 6–15 V CMOS, PMOS DIP-16 ULQ2003 ULQ2003D1013TR SO16 in tape and reel ULQ2003 ULQ2003D1013TRY (1) SO16 in tape and reel ULQ2004 ULQ2004D1013TR SO16 in tape and reel 1. Automotive Grade products. www.st.com Contents ULQ2001, ULQ2003, ULQ2004 2/14 Doc ID 1537 Rev 6 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ULQ2001, ULQ2003, ULQ2004 Diagram Doc ID 1537 Rev 6 3/14 1 Diagram Figure 1. Schematic diagram ULQ2001 (each driver) ULQ2003 (each driver) ULQ2004 (each driver) Pin configuration ULQ2001, ULQ2003, ULQ2004 4/14 Doc ID 1537 Rev 6 2 Pin configuration Figure 2. Pin connections (top view) ULQ2001, ULQ2003, ULQ2004 Maximum ratings Doc ID 1537 Rev 6 5/14 3 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VO Output voltage 50 V VIN Input voltage (for ULQ2003A/D1 - 2004A/D1) 30 V IC Continuous collector current 500 mA IB Continuous base current 25 mA TA Operating ambient temperature range -40 to 105 °C TSTG Storage temperature range -55 to 150 °C TJ Junction temperature 150 °C Table 3. Thermal data Symbol Parameter DIP-16 SO16 Unit RthJA Thermal resistance junction-ambient, max. 70 120 °C/W Electrical characteristics ULQ2001, ULQ2003, ULQ2004 6/14 Doc ID 1537 Rev 6 4 Electrical characteristics TJ = -40 to 105 °C for DIP16 unless otherwise specified, TJ = -25 to 105 °C for SO16 unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit ICEX Output leakage current VCE = 50V, (Figure 3) 50 μA TJ = 105°C, VCE= 50V (Figure 3) 100 TJ = 105°C for ULQ2004, VCE= 50V, VI = 1V (Figure 4) 500 VCE(SAT) Collector-emitter saturation voltage (Figure 5) IC = 100mA, IB = 250μA 0.9 1.1 IC = 200mA, IB= 350μA 1.1 1.3 V IC = 350mA, IB= 500μA 1.3 1.6 II(ON) Input current (Figure 6) for ULQ2003, VI = 3.85V 0.93 1.35 for ULQ2004, VI = 5V 0.35 0.5 mA for ULQ2004, VI = 12V 1 1.45 II(OFF) Input current (Figure 7) TJ = 105°C, IC = 500μA 50 65 μA VI(ON) Input voltage (Figure 8) for ULQ2003 VCE= 2V, IC = 200mA VCE= 2V, IC = 250mA VCE= 2V, IC = 300mA for ULQ2004 VCE= 2V, IC = 125mA VCE= 2V, IC = 200mA VCE= 2V, IC = 275mA VCE= 2V, IC = 350mA 2.4 2.7 3 5 6 7 8 V hFE DC forward current gain (Figure 5) for ULQ2001, VCE = 2V, IC = 350mA 1000 CI Input capacitance 15 25 (1) pF tPLH Turn-on delay time 0.5 VI to 0.5VO 0.25 1 (1) μs tPHL Turn-off delay time 0.5 VI to 0.5VO 0.25 1 (1) μs IR Clamp diode leakage current (Figure 9) VR = 50V 50 μA TJ = 105°C, VR = 50V 100 VF Clamp diode forward voltage (Figure 10) IF = 350mA 1.7 2 V 1. Guaranteed by design. ULQ2001, ULQ2003, ULQ2004 Electrical characteristics Doc ID 1537 Rev 6 7/14 TJ = -40 to 125 °C for SO16 unless otherwise specified. Table 5. Electrical characteristics for ULQ2003D1013TRY (Automotive Grade) Symbol Parameter Test conditions Min. Typ. Max. Unit ICEX Output leakage current (Figure 3) VCE = 50V 50 μA VCE(SAT) Collector-emitter saturation voltage (Figure 5) IC = 100mA, IB = 250μA 0.9 1.1 IC = 200mA, IB= 350μA 1.1 1.3 V IC = 350mA, IB= 500μA 1.3 1.6 II(ON) Input current (Figure 6) VI = 3.85V 0.93 1.35 mA II(OFF) Input current (Figure 7) IC = 500μA 50 65 μA VI(ON) Input voltage (Figure 8) VCE = 2V, IC = 200mA VCE = 2V, IC = 250mA VCE = 2V,IC = 300mA 2.4 2.7 3 V CI Input capacitance 15 25 pF tPLH Turn-on delay time 0.5 VI to 0.5VO 0.25 1 μs tPHL Turn-off delay time 0.5 VI to 0.5VO 0.25 1 μs IR Clamp diode leakage current (Figure 9) VR = 50V 50 μA VF Clamp diode forward voltage (Figure 10) IF = 350mA 1.7 2 V Test circuits ULQ2001, ULQ2003, ULQ2004 8/14 Doc ID 1537 Rev 6 5 Test circuits Figure 3. Output leakage current Figure 4. Output leakage current (for ULN2002 only) Figure 5. Collector-emitter saturation voltage Figure 6. Input current (ON) Figure 7. Input current (OFF) Figure 8. Input voltage ULQ2001, ULQ2003, ULQ2004 Test circuits Doc ID 1537 Rev 6 9/14 Figure 9. Clamp diode leakage current Figure 10. Clamp diode forward voltage Package mechanical data ULQ2001, ULQ2003, ULQ2004 10/14 Doc ID 1537 Rev 6 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. ULQ2001, ULQ2003, ULQ2004 Package mechanical data Doc ID 1537 Rev 6 11/14 Dim. mm. inch. Min. Typ. Max. Min. Typ. Max. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 Plastic DIP-16 (0.25) mechanical data P001C Package mechanical data ULQ2001, ULQ2003, ULQ2004 12/14 Doc ID 1537 Rev 6 OUTLINE AND MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D(1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F(1) 3.8 4.0 0.150 0.157 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M 0.62 0.024 S 8° (max.) (1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.) SO16 (Narrow) 0016020 D ULQ2001, ULQ2003, ULQ2004 Revision history Doc ID 1537 Rev 6 13/14 7 Revision history Table 6. Document revision history Date Revision Changes 05-Dec-2006 2 Order codes updated. 23-May-2007 3 Order codes updated. 17-Apr-2008 4 Added new order codes for Automotive grade products see Table 1 on page 1. 25-Aug-2008 5 Modified: Table 4 on page 6 and Table 5 on page 7. 11-Feb-2011 6 Modified: TJ = -25 to 105 °C Table 4 on page 6. ULQ2001, ULQ2003, ULQ2004 14/14 Doc ID 1537 Rev 6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com ULN2001, ULN2002 ULN2003, ULN2004 Seven Darlington array Datasheet − production data Features ■ Seven Darlingtons per package ■ Output current 500 mA per driver (600 mA peak) ■ Output voltage 50 V ■ Integrated suppression diodes for inductive loads ■ Outputs can be paralleled for higher current ■ TTL/CMOS/PMOS/DTL compatible inputs ■ Inputs pinned opposite outputs to simplify layout Description The ULN2001, ULN2002, ULN2003 and ULN 2004 are high voltage, high current Darlington arrays each containing seven open collector Darlington pairs with common emitters. Each channel rated at 500 mA and can withstand peak currents of 600 mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The versions interface to all common logic families: – ULN2001 (general purpose, DTL, TTL, PMOS, CMOS) – ULN2002 (14 - 25 V PMOS) – ULN2003 (5 V TTL, CMOS) – ULN2004 (6 - 15 V CMOS, PMOS) These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal printheads and high power buffers. The ULN2001A/2002A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package (SO-16) as ULN2001D1/2002D1/2003D1/ 2004D1 DIP-16 SO-16 (Narrow) Table 1. Device summary Order codes ULN2001A ULN2001D1013TR ULN2002A ULN2002D1013TR ULN2003A ULN2003D1013TR ULN2004A ULN2004D1013TR www.st.com Contents ULN2001, ULN2002, ULN2003, ULN2004 2/16 Doc ID 5279 Rev 8 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ULN2001, ULN2002, ULN2003, ULN2004 Diagram Doc ID 5279 Rev 8 3/16 1 Diagram Figure 1. Schematic diagram ULN2001 (each driver) ULN2002 (each driver) ULN2003 (each driver) ULN2004 (each driver) Pin configuration ULN2001, ULN2002, ULN2003, ULN2004 4/16 Doc ID 5279 Rev 8 2 Pin configuration Figure 2. Pin connections (top view) ULN2001, ULN2002, ULN2003, ULN2004 Maximum ratings Doc ID 5279 Rev 8 5/16 3 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VO Output voltage 50 V VI Input voltage (for ULN2002A/D - 2003A/D - 2004A/D) 30 V IC Continuous collector current 500 mA IB Continuous base current 25 mA TA Operating ambient temperature range - 40 to 85 °C TSTG Storage temperature range - 55 to 150 °C TJ Junction temperature 150 °C Table 3. Thermal data Symbol Parameter DIP-16 SO-16 Unit RthJA Thermal resistance junction-ambient, Max. 70 120 °C/W Electrical characteristics ULN2001, ULN2002, ULN2003, ULN2004 6/16 Doc ID 5279 Rev 8 4 Electrical characteristics TA = 25 °C unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit ICEX Output leakage current VCE = 50 V, (Figure 3.) 50 μA TA = 85°C, VCE = 50 V (Figure 3.) 100 TA = 85°C for ULN2002, VCE = 50 V, VI = 6 V (Figure 4.) 500 TA = 85°C for ULN2002, VCE = 50 V, VI = 1V (Figure 4.) 500 VCE(SAT) Collector-emitter saturation voltage (Figure 5.) IC = 100 mA, IB = 250 μA 0.9 1.1 IC = 200 mA, IB= 350 μA 1.1 1.3 V IC = 350 mA, IB= 500 μA 1.3 1.6 II(ON) Input current (Figure 6.) for ULN2002, VI = 17 V 0.82 1.25 mA for ULN2003, VI = 3.85 V 0.93 1.35 for ULN2004, VI = 5 V 0.35 0.5 VI = 12 V 1 1.45 II(OFF) Input current (Figure 7.) TA = 85°C, IC = 500 μA 50 65 μA VI(ON) Input voltage (Figure 8.) VCE= 2 V, for ULN2002 IC = 300 mA for ULN2003 IC = 200 mA IC = 250 mA IC = 300 mA for ULN2004 IC = 125 mA IC = 200 mA IC = 275 mA IC = 350 mA 13 2.4 2.7 3 5 6 7 8 V hFE DC Forward current gain (Figure 5.) for ULN2001, VCE = 2 V, IC = 350 mA 1000 CI Input capacitance 15 25 pF tPLH Turn-on delay time 0.5 VI to 0.5 VO 0.25 1 μs tPHL Turn-off delay time 0.5 VI to 0.5 VO 0.25 1 μs IR Clamp diode leakage current (Figure 9.) VR = 50 V 50 μA TA = 85°C, VR = 50 V 100 VF Clamp diode forward voltage (Figure 10.) IF = 350 mA 1.7 2 V ULN2001, ULN2002, ULN2003, ULN2004 Test circuits Doc ID 5279 Rev 8 7/16 5 Test circuits Figure 3. Output leakage current Figure 4. Output leakage current (for ULN2002 only) Figure 5. Collector-emitter saturation voltage Figure 6. Input current (ON) Figure 7. Input current (OFF) Figure 8. Input voltage Test circuits ULN2001, ULN2002, ULN2003, ULN2004 8/16 Doc ID 5279 Rev 8 Figure 9. Clamp diode leakage current Figure 10. Clamp diode forward voltage ULN2001, ULN2002, ULN2003, ULN2004 Typical performance characteristics Doc ID 5279 Rev 8 9/16 6 Typical performance characteristics Figure 11. Collector current vs. saturation voltage (TJ = 25°C) Figure 12. Collector current vs. saturation voltage Figure 13. Input current vs. input voltage Figure 14. Input current vs. input voltage (Ta = 25°C) Figure 15. Collector current vs. input current Figure 16. hFE vs. output current IOUT [mA] 85°C 25°C -30°C VCESAT [V] IIN = 500 μA ULN2003A Typ Max Min ULN2003A Ta = 25°C Iout=100mA Iout=200mA Iout=300mA IIN [μA] I OUT [mA] -30°C 85°C 25°C VCE = 2 V 1 10 100 1000 10000 1 10 100 1000 DC Current Transfer Ratio (hFE) Output current IOUT [mA] 85 °C -40 °C 25 °C VCE = 2 V Typical performance characteristics ULN2001, ULN2002, ULN2003, ULN2004 10/16 Doc ID 5279 Rev 8 Figure 17. Peak collector current vs. duty cycle (DIP-16) Figure 18. Peak collector current vs. duty cycle (SO-16) 0 20 40 60 80 DC 0 100 200 300 400 500 Ic peak (mA) Tamb=70°C (DIP16) 7 6 5 4 3 2 NUMBER OF ACTIVE OUTPUT D96IN451 0 20 40 60 80 100 DC 0 100 200 300 400 500 Ic peak (mA) D96IN452A 7 5 3 2 NUMBER OF ACTIVE OUTPUT Tamb=70°C (SO16) ULN2001, ULN2002, ULN2003, ULN2004 Package mechanical data Doc ID 5279 Rev 8 11/16 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 5. DIP-16L mechanical data Dim. mm. Min. Typ. Max. A 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 18067 19.18 19.69 E 7.62 7.87 8.26 E1 6.10 6.35 7.11 e 2.54 e1 17.78 eA 7.62 eB 10.92 L 2.92 3.30 3.81 Package mechanical data ULN2001, ULN2002, ULN2003, ULN2004 12/16 Doc ID 5279 Rev 8 Figure 19. DIP-16L package dimensions 0015895_E ULN2001, ULN2002, ULN2003, ULN2004 Package mechanical data Doc ID 5279 Rev 8 13/16 Table 6. SO-16 narrow mechanical data Dim. mm. inch. Min. Typ. Max. Min. Typ. Max. A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D(1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F(1) 3.8 4.0 0.150 0.157 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M 0.62 0.024 S 8° (max.) Figure 20. SO-16 package dimensions Order codes ULN2001, ULN2002, ULN2003, ULN2004 14/16 Doc ID 5279 Rev 8 8 Order codes Table 7. Order codes Part numbers Packages ULN2001A DIP-16 ULN2002A DIP-16 ULN2003A DIP-16 ULN2004A DIP-16 ULN2001D1013TR SO-16 in tape and reel ULN2002D1013TR SO-16 in tape and reel ULN2003D1013TR SO-16 in tape and reel ULN2004D1013TR SO-16 in tape and reel ULN2001, ULN2002, ULN2003, ULN2004 Revision history Doc ID 5279 Rev 8 15/16 9 Revision history Table 8. Revision history Date Revision Changes 05-Dec-2006 5 Order code updated and document reformatted. 28-Aug-2007 6 Added Table 1 in cover page. 07-May-2012 7 Modified: Figure 12 on page 9. Added: Figure 13, 14, 15 and Figure 16 on page 9. 01-Jun-2012 8 Updated: DIP-16L package mechanical data Table 5 on page 11 and Figure 19 on page 12. ULN2001, ULN2002, ULN2003, ULN2004 16/16 Doc ID 5279 Rev 8 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Smart street lighting solutions GPRS/3G network Data flow Contents Goals and design of street lighting Smart street lighting From incandescent lamps to HID and LED: today’s highest luminous performances The advantages of electronic ballasts for HID lamps: ST’s solutions Using LEDs in street lighting: ST’s solutions Smart communication system: wireless and wired Real-time lamppost fall detection using MEMS A complete solution for smart street lighting Goals and design of street lighting Goals Design principles Ensure maximum visual safety for drivers and pedestrians Improve visibility of people and objects Provide the best light quality and the highest color rendering Make residential areas surer Enhance street furniture appearance Energy efficient Reliable and safe Technically advanced Cost effective Convenient for maintenance What is smart street lighting?  Enables smart cities with highly-efficient street light driving, advanced monitoring and remote control GPRS/3G network Data flow Lamp controller with connectivity PDA with RF connectivity District data concentrator Services center Reduced maintenance costs Reduced energy consumption Performance and energy-consumption data at your fingertips Reduced greenhouse gas emissions Greater citizen satisfaction Why smart street lighting? From incandescent lamps to HID, LED Inefficient light sources such as incandescent lamps will be phased out LED technology will push the lighting market HID and HB LED offer outstanding luminous efficiency Source: U.S Department of energy 2004, Philips Lighting 2005 HID, LED: highest performances Ignition at very high voltage Warm-up phase is required Steady-state phase with lamp power control is needed Different performances according to the metals and filler materials High pressure sodium (up to 150 lm/W) Metal halide (up to 110 lm/W) Mercury vapor (up to 60 lm/W) A LED is activated when a DC voltage is applied The luminous flux and dominant wavelength are controlled by average current The ripple current has to be kept at acceptable levels Dimming can be implemented through digital or analog control  Best LED efficiency: 150 lm/W High intensity discharge (HID) Light emitting diode (LED) Source: OSRAM Electronic ballasts for HID lamps Increased lamp life Enhanced lumen constancy with life 10-15% lower energy consumption than magnetic ballasts More reliable lamp operation (end of life protection) Electronic ballasts are smaller than electromagnetic ballasts Electronics allow smart communication Lamp controller with connectivity Source: Philips Lighting Input: 185 to 265 VAC, 50 Hz Load: 150 W MH or HPS lamp PF = 0.99, THD = 2.8% Dimmable Average efficiency: 90% EN55015 compliant Remote control interfacing by PLM 150 W electronic ballast for HID lamps ESICOM order code: STEVAL-ILH005V2* Description and purpose Key features 2-stage electronic ballast for 150 W HID (high-intensity discharge) lamp, including a boost converter (PFC) working in transition mode (TM), and a full bridge inverter to drive a lamp with a low-frequency square wave Key products STF10NM60ND; STGF10NC60SD; STTH1L06; STTH1R06; VIPer16L; L6562A; L6388E; TS272; ST7FLITE39F2 * Available in Q1/2012 Wide input voltage range High power factor (up to 0.998) and very low THD (5%) PFC boost working in TM Half bridge based on power MOSFETs Controls the igniter circuit Implements buck converter in TM Provides alternate low frequency square wave current Overvoltage and short-circuit protection Suitable for HPS and MH lamps 70 W electronic ballast for HID lamps ESICOM order code: STEVAL-ILH004V1* Description and purpose Key features Fully digital ballast to drive 70 W HID lamps, based on two ICs, the digital combo driver L6382D5 and a low-cost 8-bit microcontroller, able to manage the PFC and the half bridge stage Key products L6382D5; STF8NM60ND; STTH1L06; VIPer16L; ST7LITE49K2; LIC01. * Available in Q1/2012 Source of graphic: RUUD lighting LED HID Using LEDs in street lighting The green way to lowering energy costs Low power consumption Long lumen constancy Long and predictable lifetime Light emission can be easily redirected Reliability (robust against shock and vibration) Environment friendly (CO2 saving and mercury free) Quick turn on/off and dimming 100 W and above 130 W LED driver based on L6562AT and L6599AT Input mains range: 85 to 305 VAC SMPS output voltage: 48 V at 2.7 A Long life time, electrolytic capacitors are not used Mains harmonics: meet EN61000-3-2 Class-C Efficiency at full load: > 93% EMI: meets EN55022-Class-B, EN55015 Digital dimming ESICOM order code: EVL130W-STRLIG, EVL130W-SL-EU, EVL6562A-LED Description and purpose Key features The system is composed of three stages: a front-end PFC an LLC resonant converter an inverse buck converter The key benefits are very high efficiency, long term reliability and small form factor Key products L6562AT, L6599AT, STF21NM60N, STD10NM60N, SEA05, STTH3L06U, STPS1L60A, STPS2H100A, STN3NF06 Wide input voltage range: 88 to 265 VAC LED current set to 350 mA, 700 mA and 1 A High efficiency (~90%) and high power factor Universal PWM input for dimming (ext. board required) Non-isolated SMPS Brightness regulation between 0% and 100% EMI filter implemented EN55015 and EN61000-3-2 compliant 80 W and above 80 W offline LED driver with dimming based on L6562A ESICOM order code: STEVAL-ILL013V1 Description and purpose Key features An innovative non-isolated solution for driving LEDs where high power factor, high efficiency and individual LED brightness regulation is required PFC boost, inverse buck converter Key products L6562A, STTH1L06A, STF10NM50N, STP8NM50N , STPSC806D, BUX87 Input voltage range: 185 to 265 VAC Able to drive single LED String Provides 350 mA to 0.5 A constant current for LED Max output voltage: 130 VDC No input electrolytic capacitor Efficiency: from 91% to 92.5% PF > 0.95 Maximum 2fLINE output ripple: 1.0% Up to 75 W ESICOM order code: STEVAL-ILL042V1* Description and purpose Key features Key products L6562AT; STP7N95K3; TSM101; 1.5KE350A; STTH1L06; STTH2L06 Single-stage isolated solution based on L6562AT and TSM101, offering high performance with a simple and reliable design for LED street lighting High power factor flyback 60 W offline LED driver for single LED string based on L6562AT * Available in Q1/2012 Digital constant-current controller for multi-string LED driving based on STM8S Input DC bus voltage: 48 V Independent LED string average current control Inverse buck topology System power: 120 W Switching frequency: 100 kHz Ripple current <10% Global dimming from 0% to 100% at 225 Hz (PWM dimming) Independent analog dimming on 4 channels Short-circuit protection Innovative multi-string LED driving ESICOM order code: STEVAL-ILL031V1 Description and purpose Key features Key products STM8S208RB; STPS1L60; STN3NF06 Complete platform (HW/SW) for LED multi-string constant-current control based on an innovative methodology Each LED string can be dimmed and brightened independently System can be interfaced with ZigBee or PLM modules for remote control Smart communication GPRS/3G network Data flow Dimming level, adjust on/off timing, lamp failure, consumed energy, lamp-burning hours, lamppost tilt, etc. Highway: simple linear topology City centre: complex topology Wireless network solution STM32W108xx: 32-bit MCU ARM Cortex-M3 ZigBee system on chip SPZB32W1x2.1: ZigBee PRO modules based on the STM32W chipset M24LR64-R: 64-Kbit Dual Interface EEPROM (I²C and ISO 15693 RF protocol at 13.56 MHz) IEEE 802.15.4 - ZigBee® network A mesh topology is used to reach the data concentrator A network for each district is identified by its PANID Lamppost’s node configuration using RFID EEPROM which can be written/read during both manufacturing process and installation procedure by the PDA C R1 R2 N2 R3 N4 N3 N1 Data concentrator/ network coordinator Router lamppost End node lamppost STM32W or SPZB32W1x2.1 M24LR64-R Lamppost communication mode PLC wired network solution STM32F103xx: 32-bit MCU ARM Cortex-M3 microcontroller M24LR64-R: 64-Kbit Dual Interface EEPROM (I²C and ISO 15693 RF protocol at 13.56 MHz) ST7570: IEC 61334-5-1 compliant PLM ST7540: FSK stripped down power line transceiver IEC 61334-5-1 power line communication network (ST7570) or proprietary protocol (ST7540) Configured to work in CENELEC band B or C to avoid interference with AMR network Data repeaters are used to reach the data concentrator  A network for each district identified by unique identification  Node configuration using RFID EEPROM which can be written/read during both manufacturing process and installation procedure by the PDA C R1 R2 N2 R3 N4 N3 N1 Data concentrator/ network initiator Repeater lamppost End node lamppost STM32F ST7570 or ST7540 Lamppost communication mode M24LR64-R Data concentrator STM32F107xx: 32-bit MCU ARM Cortex-M3 microcontroller with Ethernet M24LR64-R: 64-Kbit Dual Interface EEPROM (I²C and ISO 15693 RF protocol at 13.56 MHz) ST7570: IEC 61334-5-1 compliant PLM ST7540: FSK stripped down power line transceiver STM32W108xx: 32-bit MCU ARM Cortex-M3 ZigBee system on chip SPZB32W1x2.1: ZigBee PRO modules based on the STM32W chipset M24128-Bxx: 128-Kbit EEPROM One concentrator for each district STM32F ST7570 or ST7540 M24LR64-R STM32W or SPZB32W1x2.1 GPRS module M24128-Bxx PLM option ZigBee® option Real-time lamppost fall detection STM32F LIS331DLH STM32W or SPZB32W1x2.1 One low-g 3-axis accelerometer for each lamppost Tilt angle measurement Lamppost fall detection Key application benefits Road safety Reduced maintenance cost 150 W HID lamp ballast + ST7540-based communication for networked street lighting Solutions for smart street lighting Lamp driver and controller 150 W high-efficiency HID lamp ballast High reliability (up to 85°C ambient temperature) Dimmable and EN55015 compliant Suitable for HPS and MH lamps Communication section Remote control on power line Routing policies to cover long distances without dedicated hardware resources Allows remote turn-on/off, dimming, lamp and ballast status monitoring Description and purpose Key features Innovative networked street lighting system with remote control and monitoring based on PLM, including a dedicated PC GUI * Available in Q1/2012 ESICOM order code: STEVAL-ILH005V2* STEVAL-IHP003V1 Thank you For more information, visit our website: www.st.com Or follow the links below: LED and general lighting HID lighting LED lighting Evaluation boards LM350 Three-terminal 3 A adjustable voltage regulators Features ■ Guaranteed 3 A output current ■ Adjustable output down to 1.2 V ■ Line regulation typically 0.005 %/V ■ Load regulation typically 0.1 % ■ Guaranteed thermal regulation ■ Current limit constant with temperature ■ Standard 3-lead transistor package TO-3 Table 1. Device summary Order codes TO-3 Temperature range LM350K 0 to 125 °C www.st.com Contents LM350 2/14 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Protection diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LM350 Diagram 3/14 1 Diagram Figure 1. Schematic diagram Pin configuration LM350 4/14 2 Pin configuration Figure 2. Pin connections (bottom view) LM350 Maximum ratings 5/14 3 Maximum ratings Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied Table 2. Absolute maximum ratings Symbol Parameter Value Unit PD Power dissipation Internally limited VI - VO Input-output voltage differential 35 V TSTG Storage temperature range -65 to 150 °C TLEAD lead temperature (Soldering, 10 seconds) 300 °C TOP Operating junction temperature range 0 to 125 °C Table 3. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junction-case 1.5 °C/W RthJA Thermal resistance junction-ambient 35 °C/W Electrical characteristics LM350 6/14 4 Electrical characteristics Table 4. Electrical characteristics (VI -VO = 5V, IO = 1.5 A. Although power dissipation is internally limited, these specifications apply to power dissipation up to 30 W, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit KVI Line regulation (1) 1. Regulation is measured at constant junction temperature. Changes in output voltage due to heating effects are taken into account separately by thermal rejection. Ta = 25°C, VI - VO = 3 to 35 V 0.005 0.03 %/V KVO Load regulation (1) Ta = 25°C IO = 10 mA to 3 A VO ≤ 5 V 5 25 mV VO ≥ 5 V 0.1 0.5 % Thermal regulation Pulse = 20 ms 0.002 0.02 %/W IADJ Adjustment pin current 50 100 μA ΔIADJ Adjustment pin current change IL = 10 mA to 3 A, VI - VO = 3 to 35 V 0.2 5 μA VREF Reference voltage VI - VO = 3 to 35 V, IO = 10 mA to 3 A P ≤ 30 W 1.19 1.24 1.29 V KVI Line regulation (1) VI - VO = 3 to 35 V 0.02 0.05 %/V KVO Load regulation (1) IO = 10 mA to 3 A VO ≤ 5 V 20 70 mV VO ≥ 5 V 0.3 1.5 % KVT Temperature stability TJ = TMIN to TMAX 1 % IO(MIN) Minimum load current VI - VO ≤ 35 V 3.5 10 mA IO(MAX) Current limit VI - VO ≤ 10 V DC 3 4.5 A VI - VO = 30 V 1 VNO RMS output noise (% of VO) Ta = 25°C, f = 10 Hz to 10 kHz 0.001 % RVF Ripple rejection ratio VO = 10 V, f = 120 Hz 65 dB CADJ = 10 μF 66 86 KVH Long term stability Ta = 125°C 0.3 1 % LM350 Typical performance 7/14 5 Typical performance Δ Needed if device is far from filter capacitors. * Optional-improves transient response. Output capacitors in the range of 1 μF to 100 μF of aluminium or tantalum electrolytic are commonly used to provide improved output impedance and rejection of transients ** VO = 1.25 V (1 + R2/R1) Figure 3. 1.2 V to 25 V adjustable regulator Application hints LM350 8/14 6 Application hints In operation, the LM350 develops a nominal 1.25 V reference voltage, V(REF), between the output and adjustment terminal. The reference voltage is impressed across program resistor R1 and, since the voltage is constant, a constant current I1 then flows through the output set resistor R2, giving an output voltage of: VO = V(REF) (1+ R2 / R1) + IADJ x R2. Since the 50 μA current from the adjustment terminal represents an error term, the LM350 was designed to minimize IADJ and make it very constant with line and load changes. To do this, all quiescent operating current is returned to the output establishing a minimum load current requirement. If there is insufficient load on the output, the output will rise. 6.1 External capacitors An input bypass capacitor is recommended. A 0.1 μF disc or 1 μF solid tantalum on the input is suitable input by passing for almost all applications. The device is more sensitive to the absence of input bypassing when adjustment or output capacitors are used by the above values will eliminate the possibility of problems. The adjustment terminal can be bypassed to ground on the LM350 to improve ripple rejection. This bypass capacitor prevents ripple form being amplified as the output voltage is increased. With a 10 μF bypass capacitor 75 dB ripple rejection is obtainable at any output level. Increases over 20 μF do not appreciably improve the ripple rejection at frequencies above 120 Hz. If the bypass capacitor is used, it is sometimes necessary to include protection diodes to prevent the capacitor from discharging through internal low current paths and damaging the device. In general, the best type of capacitors to use are solid tantalum. Solid tantalum capacitors have low impedance even at high frequencies. Depending upon capacitor construction, it takes about 25 μF in aluminium electrolytic to equal 1 μF solid tantalum at high frequencies. Ceramic capacitors are also good at high frequencies, but some types have a large Figure 4. Circuit LM350 Application hints 9/14 decrease in capacitance at frequencies around 0.5 MHz. For this reason, 0.01 μF disc may seem to work better than a 0.1 μF disc as a bypass. Although the LM350 is stable with no output capacitors, like any feedback circuit, certain values of external capacitance can cause excessive ringing. This occurs with values between 500 pF and 5000 pF. A 1 μF solid tantalum (or 25 μF aluminium electrolytic) on the output swamps this effect and insures stability. 6.2 Load regulation The LM350 is capable of providing extremely good load regulation but a few precautions are needed to obtain maximum performance. The current set resistor connected between the adjustment terminal and the output terminal (usually 240 Ω) should be tied directly to the output of the regulator rather than near the load. This eliminates line drops from appearing effectively in series with the reference and degrading regulation. For example, a 15 V regulator with 0.05 Ω resistance between the regulator and load will have a load regulation due to line resistance of 0.05 Ω x IL. If the set resistor is connected near the load the effective line resistance will be 0.05 Ω (1 + R2/R1) or in this case, 11.5 times worse. Figure 5 shows the effect of resistance between the regulator and 140 Ω set resistor. With the TO-3 package, it is easy to minimize the resistance from the case to the set resistor, by using 2 separate leads to the case. The ground of R2 can be returned near the ground of the load to provide remote ground sensing and improve load regulation. 6.3 Protection diodes When external capacitors are used with any IC regulator it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Most 20 μF capacitors have low enough internal series resistance to deliver 20 A spikes when shorted. Although the surge is short, there is enough energy to damage parts of the IC. When an output capacitor is connected to a regulator and the input is shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage of the regulator, and the rate of decrease of VI. In the LM350 this discharge path is through a large junction that is able to sustain 25 A surge with no problem. This is not true of other types of positive regulators. For output capacitors of 100 μF or less at output of 15 V or less, there is no need to use diodes. The bypass capacitor on the adjustment terminal can discharge through a low current junction. Discharge occurs when either the input or output is shorted. Internal to the LM350 is a 50 Ω resistor which limits the peak discharge current. No protection is needed for output voltages of 25 V or less and 10 μF capacitance. Figure 6 shows an LM350 with protection diodes included for use with outputs greater than 25 V and high values of output capacitance. Application circuits LM350 10/14 7 Application circuits Figure 5. Regulator with line resistance in output lead Figure 6. Regulator with protection diodes LM350 Package mechanical data 11/14 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Package mechanical data LM350 12/14 Dim. mm. inch. Min. Typ. Max. Min. Typ. Max. A 11.85 0.466 B 0.96 1.05 1.10 0.037 0.041 0.043 C 1.70 0.066 D 8.7 0.342 E 20.0 0.787 G 10.9 0.429 N 16.9 0.665 P 26.2 1.031 R 3.88 4.09 0.152 0.161 U 39.5 1.555 V 30.10 1.185 TO-3 mechanical data P003C/C E B R C P A D G N V U O LM350 Revision history 13/14 9 Revision history Table 5. Document revision history Date Revision Changes 29-Sep-2006 1 11-Feb-2008 2 Added: Table 1 on page 1. LM350 14/14 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com VND920P-E Double channel high-side driver Features ■ ECOPACK®: lead free and RoHS compliant ■ Automotive Grade: compliance with AEC guidelines ■ Very low standby current ■ CMOS compatible input ■ Proportional load current sense ■ Current sense disable ■ Thermal shutdown protection and diagnosis ■ Undervoltage shutdown ■ Overvoltage clamp ■ Load current limitation Description The VND920P-E is a double chip device designed in STMicroelectronics™ VIPower ™ M0-3 technology. The VND920P-E is intended for driving any type of load with one side connected to ground. The active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device integrates an analog current sense output which delivers a current proportional to the load current. The device automatically turns off in the case where the ground pin becomes disconnected. Type RDS(on) IOUT VCC VND920P-E 16 mΩ 35 A(1) 1. Per channel with all the output pins connected to the PCB. 36 V SO-28 (double island) Table 1. Device summary Package Order codes Tube Tape and reel SO-28 VND920P-E VND920PTR-E www.st.com Contents VND920P-E 2/26 Doc ID 10898 Rev 5 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 19 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 VND920P-E List of tables Doc ID 10898 Rev 5 3/26 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Switching (VCC=13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. VCC output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9. Current sense (9 V <= VCC <=16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 13. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 15. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 List of figures VND920P-E 4/26 Doc ID 10898 Rev 5 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 17. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 20. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 23. SO-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 24. Thermal fitting model of a double channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 25. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 26. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 27. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VND920P-E Block diagram and pin description Doc ID 10898 Rev 5 5/26 1 Block diagram and pin description Figure 1. Block diagram UNDERVOLTAGE OVERTEMPERATURE VCC 1 GND 1 INPUT 1 OUTPUT 1 OVERVOLTAGE CURRENT LIMITER LOGIC DRIVER Power CLAMP VCC CLAMP VDS LIMITER DETECTION DETECTION DETECTION K IOUT CURRENT SENSE 1 UNDERVOLTAGE OVERTEMPERATURE VCC 2 GND 2 INPUT 2 OUTPUT 2 OVERVOLTAGE CURRENT LIMITER LOGIC DRIVER Power CLAMP VCC CLAMP VDS LIMITER DETECTION DETECTION DETECTION K IOUT CURRENT SENSE 2 Block diagram and pin description VND920P-E 6/26 Doc ID 10898 Rev 5 Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins Connection / pin Current Sense N.C. Output Input Floating X X X To ground Through 1KΩ resistor X Through 10 KΩ resistor VCC 1 GND 1 INPUT 1 CURRENT SENSE 1 NC VCC 1 VCC 2 GND 2 INPUT 2 CURRENT SENSE 2 VCC 2 VCC 2 OUTPUT 2 OUTPUT 2 OUTPUT 2 OUTPUT 2 OUTPUT 1 OUTPUT 1 OUTPUT 1 OUTPUT 1 VCC1 OUTPUT 2 OUTPUT 2 OUTPUT 1 OUTPUT 1 NC NC NC 1 14 15 28 VND920P-E Electrical specifications Doc ID 10898 Rev 5 7/26 2 Electrical specifications Figure 3. Current and voltage conventions Note: VFn = VCCn - VOUTn during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document. IS2 IGND2 OUTPUT2 VCC2 IOUT2 VCC2 VSENSE2 CURRENT SENSE 1 ISENSE1 VOUT2 OUTPUT1 IOUT1 CURRENT SENSE 2 ISENSE2 VSENSE1 VOUT1 INPUT2 IIN2 INPUT1 IIN1 VIN2 VIN1 GROUND2 IS1 VCC1 VCC1 IGND1 GROUND1 VF1 (*) Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V - VCC Reverse DC supply voltage - 0.3 V - Ignd DC reverse ground pin current - 200 mA IOUT DC output current Internally limited A - IOUT Reverse DC output current - 21 A IIN DC input current +/- 10 mA VCSENSE Current Sense maximum voltage - 3 + 15 V V VESD Electrostatic discharge (human body model: R = 1.5 KΩ; C = 100pF) INPUT CURRENT SENSE OUTPUT VCC 4000 2000 5000 5000 V V V V Electrical specifications VND920P-E 8/26 Doc ID 10898 Rev 5 2.2 Thermal data Symbol Parameter Value Unit EMAX Maximum switching energy (L = 0.25 mH; RL= 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; IL = 45 A) 355 mJ Ptot Power dissipation TC ≤ 25°C 6.25 W Tj Junction operating temperature Internally limited °C Tc Case operating temperature - 40 to 150 °C Tstg Storage temperature - 55 to 150 °C Table 3. Absolute maximum ratings (continued) Table 4. Thermal data (per island) Symbol Parameter Value Unit Rthj-lead Thermal resistance junction-lead 15 °C/W Rthj-amb Thermal resistance junction-ambient (one chip ON) 55(1) 1. When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35 μm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 45(2) 2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 μm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. °C/W Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 32(2) °C/W VND920P-E Electrical specifications Doc ID 10898 Rev 5 9/26 2.3 Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless otherwise stated. Note: VCLAMP and VOV are correlated. Typical difference is 5 V. Table 5. Power Symbol Parameter Test conditions Min. Typ. Max. Unit VCC Operating supply voltage 5.5 13 36 V VUSD Undervoltage shutdown 3 4 5.5 V VOV Overvoltage shutdown 36 V RON On-state resistance IOUT = 10 A; Tj = 25 °C; IOUT = 10 A; IOUT = 3 A; VCC = 6 V 16 32 55 mΩ mΩ mΩ VCLAMP Clamp voltage ICC = 20 mA 41 48 55 V IS Supply current Off-state; VCC = 13 V; VIN = VOUT = 0V Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25 °C On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A; RSENSE = 3.9 kΩ 10 10 25 20 5 μA μA mA IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 μA IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 μA IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 °C 5 μA IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 °C 3 μA Table 6. Switching (VCC=13 V) Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 1.3 Ω (see Figure 4.) 50 μs td(off) Turn-off delay time RL = 1.3 Ω (see Figure 4.) 50 μs dVOUT/dt(on) Turn-on voltage slope RL = 1.3 Ω (see Figure 4.) See Figure 10. V/μs dVOUT/dt(off) Turn-off voltage slope RL = 1.3 Ω (see Figure 4.) See Figure 12. V/μs Table 7. VCC output diode Symbol Parameter Test conditions Min. Typ. Max. Unit VF Forward on voltage - IOUT = 5 A; Tj = 150 °C - - 0.6 V Electrical specifications VND920P-E 10/26 Doc ID 10898 Rev 5 Table 8. Logic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit VIL Input low level voltage 1.25 V IIL Low level input current VIN = 1.25 V 1 μA VIH Input high level voltage 3.25 V IIH High level input current VIN = 3.25 V 10 μA VI(hyst) Input hysteresis voltage 0.5 V VICL Input clamp voltage IIN = 1 mA IIN = - 1 mA 6 6.8 - 0.7 8 V V Table 9. Current sense (9 V <= VCC <=16 V) Symbol Parameter Test conditions Min. Typ. Max. Unit K1 IOUT/ISENSE IOUT = 1 A; VSENSE = 0.5 V; Tj = -40 °C...150 °C 3300 4400 6000 dK1/K1 Current sense ratio drift IOUT = 1 A; VSENSE = 0.5 V; Tj= - 40 °C...150 °C -10 +10 % K2 IOUT/ISENSE IOUT = 10 A; VSENSE = 4 V; Tj = - 40 °C Tj= 25 °C...150 °C 4200 4400 4900 4900 6000 5750 dK2/K2 Current sense ratio drift IOUT = 10 A; VSENSE = 4 V; Tj = -40 °C...150 °C -8 +8 % K3 IOUT/ISENSE IOUT = 30 A; VSENSE = 4 V; Tj = -40 °C Tj = 25 °C...150 °C 4200 4400 4900 4900 5500 5250 dK3/K3 Current sense ratio drift IOUT = 30 A; VSENSE = 4 V; Tj = -40 °C...150 °C -6 +6 % ISENSE0 Analog sense current VCC = 6...16V; IOUT = 0A; VSENSE = 0V; Tj = -40°C...150°C 0 10 μA VSENSE Max analog sense output voltage VCC = 5.5 V; IOUT = 5 A; RSENSE = 10 kΩ VCC > 8 V, IOUT = 10 A; RSENSE = 10 kΩ 2 4 V V VSENSEH Sense voltage in overtemperature condition VCC = 13 V; RSENSE = 3.9 kΩ 5.5 V RVSENSEH Analog sense output impedance in overtemperature condition VCC = 13 V; Tj > TTSD; output open 400 Ω tDSENSE Current sense delay response To 90 % ISENSE (1) 1. Current sense signal delay after positive input slope. 500 μs VND920P-E Electrical specifications Doc ID 10898 Rev 5 11/26 Table 10. Protections(1) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles. Symbol Parameter Test conditions Min. Typ. Max. Unit TTSD Shutdown temperature 150 175 200 °C TR Reset temperature 135 °C Thyst Thermal hysteresis 7 15 °C Ilim Current limitation VCC = 13 V 5 V < VCC < 36 V 30 45 75 75 A A Vdemag Turn-off output clamp voltage IOUT = 2 A; VIN = 0 V; L = 6 mH VCC - 41 VCC - 48 VCC - 55 V VON Output voltage drop limitation IOUT = 1 A; Tj = -40 °C...150 °C 50 mV Table 11. Truth table Conditions Input Output Sense Normal operation L H L H 0 Nominal Overtemperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Overvoltage L H L L 0 0 Short circuit to GND L H H L L L 0 (TjTTSD) VSENSEH Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Electrical specifications VND920P-E 12/26 Doc ID 10898 Rev 5 Figure 4. Switching characteristics Table 12. Electrical transient requirements ISO T/R 7637/1 Test pulse Test level I II III IV Delays and impedance 1 - 25 V(1) 1. All functions of the device are performed as designed after exposure to disturbance. - 50 V(1) - 75 V(1) - 100 V(1) 2 ms, 10 Ω 2 + 25 V(1) + 50 V(1) + 75 V(1) + 100 V(1) 0.2 ms, 10 Ω 3a - 25 V(1) - 50 V(1) - 100 V(1) - 150 V(1) 0.1 μs, 50 Ω 3b + 25 V(1) + 50 V(1) + 75 V(1) + 100 V(1) 0.1 μs, 50 Ω 4 - 4 V(1) - 5 V(1) - 6 V(1) - 7 V(1) 100 ms, 0.01 Ω 5 + 26.5 V(1) + 46.5 V(2) 2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. + 66.5 V(2) + 86.5 V(2) 400 ms, 2 Ω VOUT dVOUT/dt(on) tr 80% 10% tf dVOUT/dt(off) ISENSE t t 90% td(off) INPUT t 90% td(on) tDSENSE VND920P-E Electrical specifications Doc ID 10898 Rev 5 13/26 Figure 5. IOUT/ISENSE versus IOUT 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3000 3500 4000 4500 5000 5500 6000 6500 min.Tj=-40°C max.Tj=-40°C min.Tj=25...150°C max.Tj=25...150°C typical value IOUT (A) IOUT/ISENSE 6500 6000 5500 5000 4500 4000 3500 3000 Electrical specifications VND920P-E 14/26 Doc ID 10898 Rev 5 Figure 6. Waveforms SENSE INPUT NORMAL OPERATION UNDERVOLTAGE VCC VUSD VUSDhyst INPUT OVERVOLTAGE VCC SENSE INPUT SENSE LOAD CURRENT LOAD CURRENT LOAD CURRENT VOV VCC > VUSD VOVhyst SHORT TO GROUND INPUT LOAD CURRENT SENSE LOAD VOLTAGE INPUT LOAD VOLTAGE SENSE LOAD CURRENT VI = 11.4 to 23 V test conditon value Line regulation Table 6 on page 12. 10-May-2012 29 Added: order codes L7806ACV-DG, L7808ACV-DG, L7815ACV-DG, L7824ABV-DG and L7824ACV-DG Table 26 on page 55. 19-Sep-2012 30 Modified load regulation units from V to mV in Table 3 to Table 9. 12-Mar-2013 31 Modified: VO output voltage at 25 °C min. value 14.4 V Table 16 on page 22. 04-Mar-2014 32 Part numbers L78xx, L78xxC, L78xxAB, L78xxAC changed to L78. Removed TO-3 package. Updated the description in cover page, Section 2: Pin configuration, Section 3: Maximum ratings, Section 4: Test circuits, Section 5: Electrical characteristics, Section 6: Application information, Section 8: Package mechanical data and Table 26: Order codes. Added Section 9: Packaging mechanical data. Minor text changes. Positive voltage regulator ICs 58/58 DocID2143 Rev 32 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com LM2904, LM2904A Low-power dual operational amplifier Datasheet - production data Features  Internally frequency-compensated  Large DC voltage gain: 100 dB  Wide bandwidth (unity gain): 1.1 MHz (temperature compensated)  Very low supply current/amplifier, essentially independent of supply voltage  Low input bias current: 20 nA (temperature compensated)  Low input offset current: 2 nA  Input common-mode voltage range includes negative rail  Differential input voltage range equal to the power supply voltage  Large output voltage swing 0 V to (VCC+ -1.5 V) Related products:  See LM2904W for enhanced ESD performances Description This circuit consists of two independent, high gain, internally frequency-compensated operational amplifiers designed specifically for automotive and industrial control systems. It operates from a single power supply over a wide range of voltages. The low power supply drain is independent of the magnitude of the power supply voltage. Application areas include transducer amplifiers, DC gain blocks and all the conventional op-amp circuits which can now be more easily implemented in single power supply systems. For example, these circuits can be directly supplied from the standard +5 V which is used in logic systems and easily provides the required interface electronics without requiring any additional power supply. In the linear mode, the input common-mode voltage range includes ground and the output voltage can also swing to ground, even though operated from a single power supply. D P S MiniSO-8 Q2 DFN8 2 x 2 mm (Plastic micropackage) SO-8 (Plastic micropackage) TSSOP8 (Thin shrink small outline package) www.st.com Contents LM2904, LM2904A 2/24 DocID2471 Rev 15 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Typical single-supply applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 DFN8 2 x 2 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID2471 Rev 15 3/24 LM2904, LM2904A Schematic diagram 24 1 Schematic diagram Figure 1. Schematic diagram (1/2 LM2904) 6 􀁍A 4 􀁍A 100􀁍A Q2 Q3 Q1 Q4 Inverting input Non-inverting input Q8 Q9 Q10 Q11 Q12 50 mA Q13 Output Q7 Q6 Q5 RSC VCC CC GND Package pin connections LM2904, LM2904A 4/24 DocID2471 Rev 15 2 Package pin connections Figure 2. DFN8 pin connections (top view) 1. The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating. Figure 3. MiniSO8, TSSOP8 and SO8 package pin connections (top view) 􀀹􀀦􀀦􀀎 􀀹􀀦􀀦􀀐 􀀲􀀸􀀷􀀔 􀀬􀀱􀀔􀀐 􀀬􀀱􀀔􀀎 􀀲􀀸􀀷􀀕 􀀬􀀱􀀕􀀐 􀀬􀀱􀀕􀀎 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀱􀀦􀀋􀀔􀀌 􀀹􀀦􀀦􀀎 􀀹􀀦􀀦􀀐 􀀲􀀸􀀷􀀔 􀀬􀀱􀀔􀀐 􀀬􀀱􀀔􀀎 􀀲􀀸􀀷􀀕 􀀬􀀱􀀕􀀐 􀀬􀀱􀀕􀀎 DocID2471 Rev 15 5/24 LM2904, LM2904A Absolute maximum ratings and operating conditions 24 3 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage (1) 1. All voltage values, except differential voltage are with respect to network ground terminal. ±16 or 32 V Vid Differential input voltage(2) 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. ±32 V Vin Input voltage -0.3 to 32 V Output short-circuit duration (3) 3. Short-circuits from the output to VCC can cause excessive heating if Vcc+ > 15 V. The maximum output current is approximately 40 mA, independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short-circuits on all amplifiers. Infinite s Iin Input current (4): Vin driven negative Input current (5): Vin driven positive above AMR value 4. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward-biased and thereby acting as input diode clamp. In addition to this diode action, there is NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the Opamps to go to the VCC voltage level (or to ground for a large overdrive) for the time during which an input is driven negative. This is not destructive and normal output is restored for input voltages above -0.3 V. 5. The junction base/substrate of the input PNP transistor polarized in reverse must be protected by a resistor in series with the inputs to limit the input current to 400 μA max (R = (Vin-32 V)/400 μA). 5 mA in DC or 50 mA in AC (duty cycle = 10%, T = 1s) 0.4 mA Toper Operating free-air temperature range -40 to +125 °C Tstg Storage temperature range -65 to +150 °C Tj Maximum junction temperature 150 °C Rthja Thermal resistance junction to ambient(6) SO-8 TSSOP8 MiniSO-8 DFN8 2x2 6. Short-circuits can cause excessive heating and destructive dissipation. Values are typical. 125 120 190 57 °C/W Rthjc Thermal resistance junction to case(6) SO-8 TSSOP8 MiniSO-8 40 37 39 °C/W ESD HBM: human body model(7) 7. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kW resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 300 V MM: machine model(8) 8. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 W). This is done for all couples of connected pin combinations while the other pins are floating. 200 V CDM: charged device model(9) 9. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. 1.5 kV Absolute maximum ratings and operating conditions LM2904, LM2904A 6/24 DocID2471 Rev 15 Table 2. Operating conditions Symbol Parameter Value Unit VCC Supply voltage 3 to 30 V Vicm Common mode input voltage range 0 to VCC+ - 1.5 V Toper Operating free-air temperature range -40 to +125 °C DocID2471 Rev 15 7/24 LM2904, LM2904A Electrical characteristics 24 4 Electrical characteristics Table 3. VCC+ = 5 V, VCC- = ground, VO = 1.4 V, Tamb = 25° C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Vio Input offset voltage (1) Tamb = 25° C LM2904 Tamb = 25° C LM2904A Tmin  Tamb  Tmax LM2904 Tmin  Tamb  Tmax LM2904A 2 1 7 29 4 mV Vio/T Input offset voltage drift 7 30 μV/°C Iio Input offset current Tamb = 25° C Tmin  Tamb  Tmax 2 30 40 nA IioT Input offset current drift 10 300 pA/°C Iib Input bias current (2) Tamb = 25° C Tmin  Tamb  Tmax 20 150 200 nA Avd Large signal voltage gain VCC+ = +15 V, RL = 2 k, Vo = 1.4 V to 11.4 V Tamb = 25° C Tmin  Tamb  Tmax 50 25 100 V/mV SVR Supply voltage rejection ratio (RS 10 k) Tamb = 25° C Tmin  Tamb  Tmax 65 65 100 dB ICC Supply current, all amp, no load Tamb = 25°C, VCC+ = +5 V Tmin  Tamb  Tmax, VCC+ = +30 V 0.7 1.2 2 mA Vicm Input common mode voltage range (VCC+= +30 V) (3) Tamb = 25° C Tmin  Tamb  Tmax 00 VCC+ -1.5 VCC+ -2 V CMR Common-mode rejection ratio (RS 10 k) Tamb = 25° C Tmin  Tamb  Tmax 70 60 85 dB Isource Output short-circuit current VCC+ = +15 V, Vo = +2 V, Vid = +1 V 20 40 60 mA Isink Output sink current VO = 2 V, VCC+ = +5 V VO = +0.2 V, VCC+ = +15 V 10 12 20 50 mA μA VOH High level output voltage (VCC+ = + 30 V) Tamb = +25° C, RL 2 k Tmin  Tamb  Tmax Tamb = +25° C, RL 10 k Tmin  Tamb  Tmax 26 26 27 27 27 28 V Electrical characteristics LM2904, LM2904A 8/24 DocID2471 Rev 15 VOL Low level output voltage (RL 10 k) Tamb = +25° C Tmin  Tamb  Tmax 5 20 20 SR Slew rate VCC+ = 15 V, Vin = 0.5 to 3 V, RL 2 k, CL =100 pF, unity gain Tmin  Tamb  Tmax 0.3 0.2 0.6 GBP Gain bandwidth product f = 100 kHz VCC+ = 30 V, Vin = 10 mV, RL 2 k, CL = 100 pF 0.7 1.1 MHz THD Total harmonic distortion f = 1 kHz, AV = 20 dB, RL = 2 k, Vo = 2 Vpp, CL = 100 pF, VCC+ = 30 V 0.02 % en Equivalent input noise voltage f = 1 kHz, RS = 100 , VCC+ = 30 V 55 nV/Hz VO1/VO2 Channel separation (4) 1 kHz  f  20 kHz 120 dB 1. VO = 1.4 V, RS = 0 W, 5 V < VCC+ < 30 V, 0 V < Vic < VCC+ - 1.5 V. 2. The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output, so there is no change in the loading charge on the input lines. 3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is VCC+ –1.5 V, but either or both inputs can go to +32 V without damage. 4. Due to the proximity of external components, ensure that the stray capacitance does not cause coupling between these external parts. This can typically be detected at higher frequencies because this type of capacitance increases. Table 3. VCC+ = 5 V, VCC- = ground, VO = 1.4 V, Tamb = 25° C (unless otherwise specified) (continued) Symbol Parameter Min. Typ. Max. Unit DocID2471 Rev 15 9/24 LM2904, LM2904A Electrical characteristics 24 Figure 4. Open-loop frequency response Figure 5. Large signal frequency response VOLTAGE GAIN (dB) 1.0 10 100 1k 10k 100k 1M 10M VCC = +10 to + 15V & FREQUENCY (Hz) 10MΩ VI VCC/2 VCC = 30V & 0.1μF VCC VO - + -55°C Tamb +125°C 140 120 100 80 60 40 20 0 -55°C Tamb +125°C FREQUENCY (Hz) 1k 10k 100k 1M OUTPUT SWING (Vpp) +7V 2kΩ 1kΩ 100kΩ +15V VO - + VI 20 15 10 5 0 Figure 6. Voltage follower large signal response Figure 7. Current sinking output characteristics INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) VOLAGE FOLLOWER PULSE RESPONSE 0 10 20 30 40 TIME (μ s) RL 2 kΩ VCC = +15V 4 3 2 1 0 3 2 1 OUTPUT CHARACTERISTICS OUTPUT SINK CURRENT (mA) 0,001 0,01 0,1 1 10 100 OUTPUT VOLTAGE(V) VCC = +5V VCC = +15V VCC = +30V - IO VO Tamb = +25°C vcc/2 vcc + 10 1 0.1 0.01 Figure 8. Voltage follower small signal response Figure 9. Current sourcing output characteristics Electrical characteristics LM2904, LM2904A 10/24 DocID2471 Rev 15 Figure 10. Input current versus temperature Figure 11. Current limiting Figure 12. Input voltage range Figure 13. Supply current Figure 14. Voltage gain Figure 15. Input current versus supply voltage 0 10 20 30 40 POSITIVE SUPPLY VOLTAGE (V) VOLTAGE GAIN (dB) 160 120 80 40 R L = 20kΩ R L = 2kΩ DocID2471 Rev 15 11/24 LM2904, LM2904A Electrical characteristics 24 Figure 16. Gain bandwidth product Figure 17. Power supply rejection ratio Figure 18. Common-mode rejection ratio Figure 19. Phase margin vs capacitive load Phase Margin at Vcc=15V and Vicm=7.5V Vs. Iout and Capacitive load value Electrical characteristics LM2904, LM2904A 12/24 DocID2471 Rev 15 4.1 Typical single-supply applications Figure 20. AC coupled inverting amplifier Figure 21. AC coupled non-inverting amplifier 1/2 LM2904 ~ 0 2VPP R 10 kΩ L Co eo R 6.2 kΩ B R 100 kΩ f R1 CI 10 kΩ eI VCC R2 100 kΩ C1 10 μF R3 100 kΩ A =- R V R1 f (as shown AV = -10) 1/2 LM2904 ~ 0 2VPP R 10 kΩ L Co eo R 6.2 kΩ B C1 0.1 μF eI VCC (as shown AV = 11) A =1+R2 V R1 R1 100 kΩ R2 1 MΩ CI R3 1 MΩ R4 100 kΩ R5 100 kΩ C2 10 μF Figure 22. Non-inverting DC gain Figure 23. DC summing amplifier R1 10 kΩ R2 1 MΩ 1/2 LM2904 10 kΩ eI eO +5V eO (V) (mV) 0 AV= 1 + R2 R1 (As shown AV = 101) 1/2 LM2904 eO e 4 e 3 e 2 e 1 100 kΩ 100 kΩ 100 kΩ 100 kΩ 100 kΩ 100 kΩ eo = e1 + e2 - e3 - e4 where (e1 + e2) (e3 + e4) to keep eo 0V ≥ ≥ Figure 24. High input Z, DC differential amplifier Figure 25. Using symmetrical amplifiers to reduce input current + 1/2 LM2904 R1 100 kΩ R2 100 kΩ R4 100 kΩ R3 100 kΩ +V2 V1 Vo 1/2 LM2904 If R1 = R5 and R3 = R4 = R6 = R7 eo = [ 1 + ] (e2 - e1) As shown eo = 101 (e2 - e1) 2R1 R2 IB 2N 929 0.001 μF IB 3 MΩ IB I eo I e I IB IB Input current compensation 1.5 MΩ 1/2 LM2904 1/2 LM2904 DocID2471 Rev 15 13/24 LM2904, LM2904A Electrical characteristics 24 Table 4. Low drift peak detector Table 5. Active bandpass filter 1/2 LM2904 IB 2N 929 0.001 μF IB 3R 3 MΩ IB Input current compensation eo IB e I Zo ZI C 1 μF 2IB R 1 MΩ 2IB 1/2 LM2904 1/2 LM2904 1/2 LM2904 R8 100 kΩ C3 10 μF R7 100 kΩ R5 470 kΩ C1 330 pF Vo VCC R6 470 kΩ C2 330 pF R4 10 MΩ R1 100 kΩ R2 100 kΩ +V1 R3 100 kΩ 1/2 LM2904 1/2 LM2904 Fo = 1 kHz Q = 50 Av = 100 (40 dB) Macromodel LM2904, LM2904A 14/24 DocID2471 Rev 15 5 Macromodel An accurate macromodel of the LM2904 is available on STMicroelectronics’ web site at www.st.com. This model is a trade-off between accuracy and complexity (that is, time simulation) of the LM2904 operational amplifier. It emulates the nominal performances of a typical device within the specified operating conditions mentioned in the datasheet. It also helps to validate a design approach and to select the right operational amplifier, but it does not replace on-board measurements. DocID2471 Rev 15 15/24 LM2904, LM2904A Package information 24 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Package information LM2904, LM2904A 16/24 DocID2471 Rev 15 6.1 SO-8 package information Figure 26. SO-8 package mechanical drawing Table 6. SO-8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.75 0.069 A1 0.10 0.25 0.004 0.010 A2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 1.04 0.040 k 1° 8° 1° 8° ccc 0.10 0.004 DocID2471 Rev 15 17/24 LM2904, LM2904A Package information 24 6.2 DFN8 2 x 2 mm package mechanical data Figure 27. DFN8 2 x 2 mm package mechanical drawing Table 7. DFN8 2 x 2 mm package mechanical data (pitch 0.5 mm) Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.51 0.55 0.60 0.020 0.022 0.024 A1 0.05 0.002 A3 0.15 0.006 b 0.18 0.25 0.30 0.007 0.010 0.012 D 1.85 2.00 2.15 0.073 0.079 0.085 D2 1.45 1.60 1.70 0.057 0.063 0.067 E 1.85 2.00 2.15 0.073 0.079 0.085 E2 0.75 0.90 1.00 0.030 0.035 0.039 e 0.50 0.020 L 0.50 0.020 ddd 0.08 0.003 Package information LM2904, LM2904A 18/24 DocID2471 Rev 15 Figure 28. DFN8 2 x 2 mm footprint recommendation 2.80 mm 0.30 mm 0.50 mm 0.45 mm 1.60 mm 0.75 mm DocID2471 Rev 15 19/24 LM2904, LM2904A Package information 24 6.3 TSSOP8 package information Figure 29. TSSOP8 package mechanical drawing Figure 30. TSSOP8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 2.90 3.00 3.10 0.114 0.118 0.122 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.177 e 0.65 0.0256 k 0° 8° 0° 8° L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1 0.039 aaa 0.10 0.004 Package information LM2904, LM2904A 20/24 DocID2471 Rev 15 6.4 MiniSO-8 package information Figure 31. MiniSO-8 package mechanical drawing Table 8. MiniSO-8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.1 0.043 A1 0 0.15 0 0.006 A2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e 0.65 0.026 L 0.40 0.60 0.80 0.016 0.024 0.031 L1 0.95 0.037 L2 0.25 0.010 k 0° 8° 0° 8° ccc 0.10 0.004 DocID2471 Rev 15 21/24 LM2904, LM2904A Ordering information 24 7 Ordering information Table 9. Order codes Order code Temperature range Package Packing Marking LM2904D/DT -40° C to +125° C SO-8 Tube or tape & reel 2904 LM2904PT TSSOP8 (thin shrink outline package) Tape & reel LM2904ST MiniSO-8 Tape & reel K403 LM2904Q2T DFN8 2 x 2 Tape & reel K1Y LM2904YDT(1) SO-8 (automotive grade level) Tape & reel 2904Y LM2904AYDT(1) 2904AY LM2904YPT(2) TSSOP8 (automotive grade level) Tape & reel 2904Y LM2904AYPT(2) 904AY LM2904YST(1) MiniSO-8 (automotive grade level) Tape & reel K409 1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent. 2. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are on-going. Revision history LM2904, LM2904A 22/24 DocID2471 Rev 15 8 Revision history Table 10. Document revision history Date Revision Changes 02-Jan-2002 1 Initial release. 20-Jun-2005 2 PPAP references inserted in the datasheet, see Table 9 on page 21. ESD protection inserted in Table 1 on page 5. 10-Oct-2005 3 PPAP part numbers added in table Table 9 on page 21. 12-Dec-2005 4 Pin connections identification added on cover page figure. Thermal resistance junction to case information added see Table 1 on page 5. 01-Feb-2006 5 Maximum junction temperature parameter added in Table 1 on page 5. 02-May-2006 6 Minimum slew rate parameter in temperature Table 3 on page 7. 13-Jul-2006 7 Modified ESD values and added explanation on VCC, Vid in Table 1 on page 5. Added macromodel information. 28-Feb-2007 8 Modified ESD/HBM values in Table 1 on page 5. Updated MiniSO-8 package information. Added note relative to automotive grade level part numbers in Table 9 on page 21. 18-Jun-2007 9 Power dissipation value corrected in Table 1: Absolute maximum ratings. Table 2: Operating conditions added. Equivalent input noise voltage parameter added in Table 3. Electrical characteristics curves updated. Figure 19: Phase margin vs capacitive load added. Section 6: Package information updated. 18-Dec-2007 10 Removed power dissipation parameter from Table 1: Absolute maximum ratings. Removed Vopp from electrical characteristics in Table 3. Corrected MiniSO-8 package mechanical data in Section 6.4: MiniSO-8 package information. 08-Apr-2008 11 Added table of contents. Corrected the scale of Figure 7 (mA not μA). Corrected SO-8 package information. 02-Jun-2009 12 Added input current information in Table 1: Absolute maximum ratings. Added L1 parameters in Table 6: SO-8 package mechanical data. Added new order codes, LM2904AYD/DT, LM2904AYPT and LM2904AYST in Table 9: Order codes. 13-Apr-2010 13 Added LM2904A on cover page. Corrected footnote (5) in Table 1: Absolute maximum ratings. Removed order code LM2904AYST from Table 9: Order codes. DocID2471 Rev 15 23/24 LM2904, LM2904A Revision history 24 24-Jan-2012 14 Removed macromodel from Chapter 5 (now available on www.st.com). Added DFN8 2 x 2 mm package information in Chapter 6 and related order codes in Chapter 7. Removed LM2904YD and LM2904AYD order codes from Table 9. Changed note for LM2904YST order code in Table 9. 24-Jan-2014 15 Updated: marking info for LM2904AYPT, package silhouette drawings in the cover page, Vio/T and IioT symbols in Table 3 on page 7 Added: ESD info in Features section and Section 2: Package pin connections Removed: LM2904N from Table 9: Order codes. Table 10. Document revision history (continued) Date Revision Changes LM2904, LM2904A 24/24 DocID2471 Rev 15 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com LM217, LM317 1.2 V to 37 V adjustable voltage regulators Datasheet - production data Features • Output voltage range: 1.2 to 37 V • Output current in excess of 1.5 A • 0.1 % line and load regulation • Floating operation for high voltages • Complete series of protections: current limiting, thermal shutdown and SOA control Description The LM217, LM317 are monolithic integrated circuits in TO-220, TO-220FP and D²PAK packages intended for use as positive adjustable voltage regulators. They are designed to supply more than 1.5 A of load current with an output voltage adjustable over a 1.2 to 37 V range. The nominal output voltage is selected by means of a resistive divider, making the device exceptionally easy to use and eliminating the stocking of many fixed regulators. TO-220 TO-220FP D²PAK Table 1. Device summary Order codes TO-220 (single gauge) TO-220 (double gauge) D²PAK (tape and reel) TO-220FP LM217T LM217T-DG LM217D2T-TR LM317T LM317T-DG LM317D2T-TR LM317P LM317BT www.st.com Contents LM217, LM317 2/25 DocID2154 Rev 19 Contents 1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DocID2154 Rev 19 3/25 LM217, LM317 Pin configuration 25 1 Pin configuration Figure 1. Pin connections (top view) 􀀷􀀲􀀐􀀕􀀕􀀓 􀀷􀀲􀀐􀀕􀀕􀀓􀀩􀀳 􀀧􀃰􀀳􀀤􀀮􀀃 Maximum ratings LM217, LM317 4/25 DocID2154 Rev 19 2 Maximum ratings Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 2. Absolute maximum ratings Symbol Parameter Value Unit VI - VO Input-reference differential voltage 40 V IO Output current Internally limited A TOP Operating junction temperature for: LM217 - 25 to 150 °C LM317 0 to 125 LM317B -40 to 125 PD Power dissipation Internally limited TSTG Storage temperature - 65 to 150 °C Table 3. Thermal data Symbol Parameter D²PAK TO-220 TO-220FP Unit RthJC Thermal resistance junction-case 3 5 5 °C/W RthJA Thermal resistance junction-ambient 62.5 50 60 °C/W DocID2154 Rev 19 5/25 LM217, LM317 Diagram 25 3 Diagram Figure 2. Schematic diagram Electrical characteristics LM217, LM317 6/25 DocID2154 Rev 19 4 Electrical characteristics VI - VO = 5 V, IO = 500 mA, IMAX = 1.5 A and PMAX = 20 W, TJ = - 55 to 150 °C, unless otherwise specified. Table 4. Electrical characteristics for LM217 Symbol Parameter Test conditions Min. Typ. Max. Unit ΔVO Line regulation VI - VO = 3 to 40 V TJ = 25°C 0.01 0.02 %/V 0.02 0.05 ΔVO Load regulation VO ≤5 V IO = 10 mA to IMAX TJ = 25°C 5 15 mV 20 50 VO ≥5 V, IO = 10 mA to IMAX TJ = 25°C 0.1 0.3 % 0.3 1 IADJ Adjustment pin current 50 100 μA ΔIADJ Adjustment pin current VI - VO = 2.5 to 40V IO = 10 mA to IMAX 0.2 5 μA VREF Reference voltage VI - VO = 2.5 to 40V IO= 10 mA to IMAX PD ≤ PMAX 1.2 1.25 1.3 V ΔVO/VO Output voltage temperature stability 1 % IO(min) Minimum load current VI - VO = 40 V 3.5 5 mA IO(max) Maximum load current VI - VO ≤ 15 V, PD < PMAX 1.5 2.2 A VI - VO = 40 V, PD < PMAX, TJ = 25°C 0.4 eN Output noise voltage (percentage of VO) B = 10Hz to 100kHz, TJ = 25°C 0.003 % SVR Supply voltage rejection (1) TJ = 25°C, f = 120Hz CADJ=0 65 dB CADJ=10μF 66 80 1. CADJ is connected between adjust pin and ground. DocID2154 Rev 19 7/25 LM217, LM317 Electrical characteristics 25 VI - VO = 5 V, IO = 500 mA, IMAX = 1.5 A and PMAX = 20 W, TJ = 0 to 125 °C, unless otherwise specified. Table 5. Electrical characteristics for LM317 Symbol Parameter Test conditions Min. Typ. Max. Unit ΔVO Line regulation VI - VO = 3 to 40 V TJ = 25°C 0.01 0.04 %/V 0.02 0.07 ΔVO Load regulation VO ≤ 5 V IO = 10 mA to IMAX TJ = 25°C 5 25 mV 20 70 VO ≥5 V, IO = 10 mA to IMAX TJ = 25°C 0.1 0.5 % 0.3 1.5 IADJ Adjustment pin current 50 100 μA ΔIADJ Adjustment pin current VI - VO = 2.5 to 40V, IO = 10 mA to 500mA 0.2 5 μA VREF Reference voltage (between pin 3 and pin 1) VI - VO = 2.5 to 40V IO = 10 mA to 500mA PD ≤ PMAX 1.2 1.25 1.3 V ΔVO/VO Output voltage temperature stability 1 % IO(min) Minimum load current VI - VO = 40 V 3.5 10 mA IO(max) Maximum load current VI - VO ≤ 15 V, PD < PMAX 1.5 2.2 A VI - VO = 40 V, PD < PMAX, TJ = 25°C 0.4 eN Output noise voltage (percentage of VO) B = 10Hz to 100kHz, TJ = 25°C 0.003 % SVR Supply voltage rejection (1) TJ = 25°C, f = 120Hz CADJ=0 65 dB CADJ=10μF 66 80 1. CADJ is connected between adjust pin and ground. Electrical characteristics LM217, LM317 8/25 DocID2154 Rev 19 VI - VO = 5 V, IO = 500 mA, IMAX = 1.5 A and PMAX = 20 W, TJ = - 40 to 125 °C, unless otherwise specified. Table 6. Electrical characteristics for LM317B Symbol Parameter Test conditions Min. Typ. Max. Unit ΔVO Line regulation VI - VO = 3 to 40 V TJ = 25°C 0.01 0.04 %/V 0.02 0.07 ΔVO Load regulation VO ≤ 5 V IO = 10 mA to IMAX TJ = 25°C 5 25 mV 20 70 VO ≥5 V, IO = 10 mA to IMAX TJ = 25°C 0.1 0.5 % 0.3 1.5 IADJ Adjustment pin current 50 100 μA ΔIADJ Adjustment pin current VI - VO = 2.5 to 40V, IO = 10 mA to 500mA 0.2 5 μA VREF Reference voltage (between pin 3 and pin 1) VI - VO = 2.5 to 40V IO = 10 mA to 500mA PD ≤ PMAX 1.2 1.25 1.3 V ΔVO/VO Output voltage temperature stability 1 % IO(min) Minimum load current VI - VO = 40 V 3.5 10 mA IO(max) Maximum load current VI - VO ≤ 15 V, PD < PMAX 1.5 2.2 A VI - VO = 40 V, PD < PMAX, TJ = 25°C 0.4 eN Output noise voltage (percentage of VO) B = 10Hz to 100kHz, TJ = 25°C 0.003 % SVR Supply voltage rejection (1) TJ = 25°C, f = 120Hz CADJ=0 65 dB CADJ=10μF 66 80 1. CADJ is connected between adjust pin and ground. DocID2154 Rev 19 9/25 LM217, LM317 Typical characteristics 25 5 Typical characteristics Figure 3. Output current vs. input-output differential voltage Figure 4. Dropout voltage vs. junction temperature Figure 5. Reference voltage vs. junction Figure 6. Basic adjustable regulator 􀀬􀀬􀁑􀁑􀁓􀁓􀁘􀁘􀁗􀁗 􀀲􀀲􀁘􀁘􀁗􀁗􀁓􀁓􀁘􀁘􀁗􀁗 􀀤􀀤􀁇􀁇􀁍􀁍 Application information LM217, LM317 10/25 DocID2154 Rev 19 6 Application information The LM217, LM317 provides an internal reference voltage of 1.25 V between the output and adjustments terminals. This is used to set a constant current flow across an external resistor divider (see Figure 6), giving an output voltage VO of: VO = VREF (1 + R2/R1) + IADJ R2 The device was designed to minimize the term IADJ (100 μA max) and to maintain it very constant with line and load changes. Usually, the error term IADJ × R2 can be neglected. To obtain the previous requirement, all the regulator quiescent current is returned to the output terminal, imposing a minimum load current condition. If the load is insufficient, the output voltage will rise. Since the LM217, LM317 is a floating regulator and "sees" only the input-tooutput differential voltage, supplies of very high voltage with respect to ground can be regulated as long as the maximum input-to-output differential is not exceeded. Furthermore, programmable regulators are easily obtainable and, by connecting a fixed resistor between the adjustment and output, the device can be used as a precision current regulator. In order to optimize the load regulation, the current set resistor R1 (see Figure 6) should be tied as close as possible to the regulator, while the ground terminal of R2 should be near the ground of the load to provide remote ground sensing. Performance may be improved with added capacitance as follow: • An input bypass capacitor of 0.1 μF • An adjustment terminal to ground 10 μF capacitor to improve the ripple rejection of about 15 dB (CADJ). • An 1 μF tantalum (or 25 μF Aluminium electrolytic) capacitor on the output to improve transient response. In addition to external capacitors, it is good practice to add protection diodes, as shown in Figure 7 D1 protect the device against input short circuit, while D2 protect against output short circuit for capacitance discharging. Note: D1 protect the device against input short circuit, while D2 protects against output short circuit for capacitors discharging. Figure 7. Voltage regulator with protection diodes 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 DocID2154 Rev 19 11/25 LM217, LM317 Application information 25 IO = (VREF / R1) + IADJ = 1.25 V / R1 Figure 8. Slow turn-on 15 V regulator 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 Figure 9. Current regulator 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 Figure 10. 5 V electronic shut-down regulator 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 Application information LM217, LM317 12/25 DocID2154 Rev 19 (R2 sets maximum VO) * RS sets output impedance of charger ZO = RS (1 + R2/R1). Use of RS allows low charging rates whit fully charged battery. Figure 11. Digitally selected outputs 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 Figure 12. Battery charger (12 V) 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 DocID2154 Rev 19 13/25 LM217, LM317 Application information 25 * R3 sets peak current (0.6 A for 1 0). ** C1 recommended to filter out input transients. Figure 13. Current limited 6 V charger 􀀪􀀪􀁏􀁏􀁑􀁑􀁖􀁖􀁕􀁕 􀀰􀁖􀁖􀁕􀁕􀁑􀁑􀁖􀁖􀁕􀁕 􀀢􀁅􀁅􀁋􀁋􀁖􀁖􀁔􀁔􀁕􀁕 Package mechanical data LM217, LM317 14/25 DocID2154 Rev 19 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14. TO-220 (single gauge) drawing 􀀛􀀔􀀚􀀗􀀙􀀕􀀚􀁂􀁕􀁈􀁙􀀧 DocID2154 Rev 19 15/25 LM217, LM317 Package mechanical data 25 Table 7. TO-220 (single gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 0.51 0.60 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 Package mechanical data LM217, LM317 16/25 DocID2154 Rev 19 Figure 15. TO-220 (dual gauge) drawing 􀀓􀀓􀀔􀀘􀀜􀀛􀀛􀁂􀁗􀁜􀁓􀁈􀀤􀁂􀀵􀁈􀁙􀁂􀀷 DocID2154 Rev 19 17/25 LM217, LM317 Package mechanical data 25 Table 8. TO-220 (dual gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 Package mechanical data LM217, LM317 18/25 DocID2154 Rev 19 Figure 16. TO-220FP drawing 7012510_Rev_K A B H Dia L7 D E L6 L5 L2 L3 L4 F1 F2 F G G1 DocID2154 Rev 19 19/25 LM217, LM317 Package mechanical data 25 Table 9. TO-220FP mechanical data Dim. mm Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 Package mechanical data LM217, LM317 20/25 DocID2154 Rev 19 Figure 17. D²PAK drawing 0079457_T DocID2154 Rev 19 21/25 LM217, LM317 Package mechanical data 25 Table 10. D²PAK mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R 0.4 V2 0° 8° Packaging mechanical data LM217, LM317 22/25 DocID2154 Rev 19 8 Packaging mechanical data Figure 18. Tape for D²PAK A0 P1 D1 P0 F W E D B0 K0 T User direction of feed P2 10 pitches cumulative tolerance on tape +/- 0.2 mm User direction of feed R Bending radius B1 For machine ref. only including draft and radii concentric around B0 AM08852v1 Top cover tape DocID2154 Rev 19 23/25 LM217, LM317 Packaging mechanical data 25 Figure 19. Reel for D²PAK Table 11. D²PAK tape and reel mechanical data Tape Reel Dim. mm Dim. mm Min. Max. Min. Max. A0 10.5 10.7 A 330 B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 13.2 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 26.4 F 11.4 11.6 N 100 K0 4.8 5.0 T 30.4 P0 3.9 4.1 P1 11.9 12.1 Base qty 1000 P2 1.9 2.1 Bulk qty 1000 R 50 T 0.25 0.35 W 23.7 24.3 A D B Full radius G measured at hub C N REEL DIMENSIONS 40mm min. Access hole At sl ot location T Tape slot in core for tape start 25 mm min. width AM08851v2 Revision history LM217, LM317 24/25 DocID2154 Rev 19 9 Revision history Table 12. Document revision history Date Revision Changes 01-Sep-2004 10 Mistake VREF ==> VO, tables 1, 4 and 5. 19-Jan-2007 11 D²PAK mechanical data has been updated, add footprint data and the document has been reformatted. 13-Jun-2007 12 Change values ΔIADJ and VREF test condition of IO = 10 mA to IMAX ==> IO = 10 mA to 500 mA on Table 5. 23-Nov-2007 13 Added Table 1. 06-Feb-2008 14 Added: TO-220 mechanical data Figure 14 on page 14 and Table 6 on page 13. 02-Mar-2010 15 Added: notes Figure 14 on page 14, Figure 15 on page 15, Figure 16 and Figure 17 on page 16. 17-Nov-2010 16 Modified: RthJC value for TO-220 Table 3 on page 4. 18-Nov-2011 17 Added: order code LM317T-DG Table 1 on page 1. 13-Feb-2012 18 Added: order code LM217T-DG Table 1 on page 1. 12-Mar-2014 19 The part number LM117 has been moved to a separate datasheet. Removed TO-3 package. Updated the description in cover page Modified Table 1: Device summary, Table 3: Thermal data, Figure 1: Pin connections (top view), Section 4: Electrical characteristics, Section 5: Typical characteristics, Section 6: Application information, Section 7: Package mechanical data. Added Section 8: Packaging mechanical data. Minor text changes. DocID2154 Rev 19 25/25 LM217, LM317 25 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com STP80NF55L-08 STB80NF55L-08 - STB80NF55L-08-1 N-CHANNEL 55V - 0.0065Ω - 80A - TO-220/D2PAK/I2PAK STripFET™ II POWER MOSFET (1) Current Limited by Package (2) ISD ≤ 80A, di/dt ≤ 500A/μs, VDD= 40V Tj ≤ TJMAX. (3) Starting Tj= 25°C, ID= 40A, VDD= 40V  TYPICAL RDS(on) = 0.0065Ω  LOW THRESHOLD DRIVE  LOGIC LEVEL DEVICE DESCRIPTION This Power Mosfet is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalance characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS  HIGH CURRENT SWITCHING APPLICATION ABSOLUTE MAXIMUM RATINGS () Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STP80NF55L-08 STB80NF55L-08 STB80NF55L-08-1 55 V 55 V 55 V 0.008Ω 0.008Ω 0.008Ω 80 A 80 A 80 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 55 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 55 V VGS Gate- source Voltage ± 16 V ID (1) Drain Current (continuous) at TC = 25°C 80 A ID (1) Drain Current (continuous) at TC = 100°C 80 A IDM () Drain Current (pulsed) 320 A PTOT Total Dissipation at TC = 25°C 300 W Derating Factor 2 W/°C dv/dt (2) Peak Diode Recovery voltage slope 15 V/ns EAS(3) Single Pulse Avalanche Energy 870 mJ Tstg Storage Temperature –55 to 175 °C Tj Max. Operating Junction Temperature 175 °C TO-220 1 2 3 1 3 D2PAK 1 2 3 I2PAK INTERNAL SCHEMATIC DIAGRAM STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 2/9 THERMAL DATA ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 0.5 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 μA, VGS = 0 55 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 μA VDS = Max Rating, TC = 125 °C 10 μA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250μA 1 1.6 2.5 V RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 40 A VGS = 5 V, ID = 40 A 0.0065 0.008 0.008 0.01 ΩΩ Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs Forward Transconductance VDS =15V , ID =40 A 150 S Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 4350 pF Coss Output Capacitance 800 pF Crss Reverse Transfer Capacitance 260 pF 3/9 STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1. Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 27V, ID = 40A RG = 4.7Ω VGS = 4.5V (see test circuit, Figure 3) 35 ns tr Rise Time 145 ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 27.5 V, ID = 80A, VGS = 4.5V 75 20 30 100 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off-Delay Time Fall Time VDD = 27V, ID = 40A, RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 3) 85 65 ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 80 A ISDM (2) Source-drain Current (pulsed) 320 A VSD (2) Forward On Voltage ISD = 80A, VGS = 0 1.5 V trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80A, di/dt = 100A/μs, VDD = 20V, Tj = 150°C (see test circuit, Figure 5) 85 280 6.5 ns nC A STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 4/9 Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. Fig. 1: Unclamped Inductive Load Test Circuit 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load 5/9 STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 0.645 L30 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 TO-220 MECHANICAL DATA STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 6/9 1 DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 D1 8 0.315 E 10 10.4 0.393 E1 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R 0.4 0.015 V2 0º 4º D2PAK MECHANICAL DATA 3 7/9 STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 A1 2.40 2.72 0.094 0.107 b 0.61 0.88 0.024 0.034 b1 1.14 1.70 0.044 0.066 c 0.49 0.70 0.019 0.027 c2 1.23 1.32 0.048 0.052 D 8.95 9.35 0.352 0.368 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 E 10 10.40 0.393 0.410 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L2 1.27 1.40 0.050 0.055 TO-262 (I2PAK) MECHANICAL DATA STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 8/9 TAPE AND REEL SHIPMENT (suffix ”T4”)* D2PAK FOOTPRINT TUBE SHIPMENT (no suffix)* * on sales type DIM. mm inch MIN. MAX. MIN. MAX. A 330 12.992 B 1.5 0.059 C 12.8 13.2 0.504 0.520 D 20.2 0795 G 24.4 26.4 0.960 1.039 N 100 3.937 T 30.4 1.197 BASE QTY BULK QTY 1000 1000 REEL MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. MAX. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0.075 0.082 R 50 1.574 T 0.25 0.35 0.0098 0.0137 W 23.7 24.3 0.933 0.956 TAPE MECHANICAL DATA 9/9 STP80NF55L-08 - STB80NF55L-08 - STB80NF55L-08-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland STP16NF06L STP16NF06LFP N-CHANNEL 60V - 0.07 Ω - 16A TO-220/TO-220FP STripFET™ II POWER MOSFET ■ TYPICAL RDS(on) = 0.07Ω ■ EXCEPTIONAL dv/dt CAPABILITY ■ LOW GATE CHARGE AT 100 oC ■ LOW THRESHOLD DRIVE DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" stripbased process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ DC-DC & DC-AC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT TYPE VDSS RDS(on) ID STP16NF06L STP60NF06LFP 60 V 60 V <0.09 Ω <0.09 Ω 16 A 11 A 1 2 3 1 2 3 TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS (•) Pulse width limited by safe operating area. (*) Current Limited by package’s thermal resistance (1) ISD ≤ 16A, di/dt ≤ 210A/μs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. (2) Starting Tj = 25 oC, ID = 8A, VDD = 30V Symbol Parameter Value Unit STP16NF06L STP16NF06LFP VDS Drain-source Voltage (VGS = 0) 60 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 60 V VGS Gate- source Voltage ± 16 V ID Drain Current (continuous) at TC = 25°C 16 11(*) A ID Drain Current (continuous) at TC = 100°C 11 7.5(*) A IDM(•) Drain Current (pulsed) 64 44(*) A Ptot Total Dissipation at TC = 25°C 45 25 W Derating Factor 0.3 0.17 W/°C dv/dt (1) Peak Diode Recovery voltage slope 23 V/ns EAS (2) Single Pulse Avalanche Energy 127 mJ VISO Insulation Withstand Voltage (DC) -------- 2500 V Tstg Storage Temperature -55 to 175 °C Tj Operating Junction Temperature STP16NF06L/FP 2/9 THERMAL DATA ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF ON (1) DYNAMIC TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max 3.33 6 °C/W Rthj-amb Tl Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max 62.5 300 °C/W °C Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 μA, VGS = 0 60 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C 1 10 μA μA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 μA 1 2.5 V RDS(on) Static Drain-source On Resistance VGS = 5 V ID = 8 A VGS = 10 V ID = 8 A 0.08 0.07 0.10 0.09 ΩΩ Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (*) Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 8 A 17 S Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 345 72 29 pF pF pF 3/9 STP16NF06L/FP SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE (*)Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 30 V ID = 8 A RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 3) 10 37 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 48 V ID = 16 A VGS= 5V 7.3 2.1 3.1 10 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time VDD = 30 V ID = 8 A RG = 4.7Ω, VGS = 4.5 V (Resistive Load, Figure 3) 20 12.5 ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) 16 64 AA VSD (*) Forward On Voltage ISD = 16 A VGS = 0 1.3 V trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 16 A di/dt = 100A/μs VDD = 16 V Tj = 150°C (see test circuit, Figure 5) 50 67.5 2.7 ns nC A ELECTRICAL CHARACTERISTICS (continued) Safe Operating Area for TO-220 Safe Operating Area for TO-220FP STP16NF06L/FP 4/9 Thermal Impedance Thermal Impedance for TO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 5/9 STP16NF06L/FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics STP16NF06L/FP 6/9 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 7/9 STP16NF06L/FP DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 L6 A C D E D1 F G L7 L2 Dia. F1 L5 L4 H2 L9 F2 G1 TO-220 MECHANICAL DATA P011C STP16NF06L/FP 8/9 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 L2 A B D E H G L6 ¯ F L3 G1 1 2 3 F2 F1 L7 L4 TO-220FP MECHANICAL DATA 9/9 STP16NF06L/FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com STM32F205xx STM32F207xx ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM 32-bit Cortex™-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™ allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1) • Memories – Up to 1 Mbyte of Flash memory – 512 bytes of OTP memory – Up to 128 + 4 Kbytes of SRAM – Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – From 1.8 to 3.6 V application supply+I/Os – POR, PDR, PVD and BOR – 4 to 26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20 × 32 bit backup registers, and optional 4 KB backup SRAM • 3 × 12-bit, 0.5 μs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode • 2 × 12-bit D/A converters • General-purpose DMA: 16-stream controller with centralized FIFOs and burst support • Up to 17 timers – Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode: Serial wire debug (SWD), JTAG, and Cortex-M3 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability: – Up to 136 fast I/Os up to 60 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs and 2 UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem ctrl) – Up to 3 SPIs (30 Mbit/s), 2 with muxed I2S to achieve audio class accuracy via audio PLL or external PLL – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface (48 Mbyte/s max.) – • CRC calculation unit • 96-bit unique ID Table 1. Device summary Reference Part number STM32F205xx STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG, STM32F205VB, STM32F205VC, STM32F205VE, STM32F205VF STM32F205VG, STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG STM32F207xx STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG, STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG, STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm) UFBGA176 (10 × 10 mm) WLCSP64+2 (0.400 mm pitch) 􀀦􀀢􀀧􀀡 www.st.com Contents STM32F20xxx 2/178 DocID15818 Rev 11 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . . 18 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 19 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 28 3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID15818 Rev 11 3/178 STM32F20xxx Contents 5 3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.25 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 34 3.27 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.28 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 35 3.29 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 35 3.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.32 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.33 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.34 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.35 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Contents STM32F20xxx 4/178 DocID15818 Rev 11 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 73 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 73 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 74 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 95 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 100 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 148 6.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 148 6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 DocID15818 Rev 11 5/178 STM32F20xxx Contents 5 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 List of tables STM32F20xxx 6/178 DocID15818 Rev 11 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F205xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. STM32F207xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 8. STM32F20x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 9. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 10. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 71 Table 16. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 73 Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 73 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 76 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 83 Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 83 Table 26. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 28. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 29. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 30. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 32. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 33. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 34. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 35. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 36. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 37. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 38. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 39. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 40. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DocID15818 Rev 11 7/178 STM32F20xxx List of tables 7 Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 50. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 51. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 52. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 53. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 55. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 56. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 57. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 58. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 59. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 60. Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 61. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 62. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 63. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 64. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 65. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 67. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 68. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 69. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 71. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 130 Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 131 Table 74. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 75. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 76. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 77. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 78. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 79. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 80. Switching characteristics for PC Card/CF read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 145 Table 82. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 83. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 84. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 85. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 86. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 151 Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . 153 Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 155 Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data. . . . . . . . 157 Table 91. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . 162 Table 93. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 94. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 95. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 List of figures STM32F20xxx 8/178 DocID15818 Rev 11 List of figures Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. STM32F20x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7. Regulator OFF/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 9. Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10. STM32F20x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. STM32F20x WLCSP64+2 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. STM32F20x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13. STM32F20x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 14. STM32F20x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 15. STM32F20x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 16. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 17. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 18. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 19. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 20. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 21. Number of wait states versus fCPU and VDD range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 22. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 25. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON. . . . . . . . . . . . . . . 79 Figure 26. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 79 Figure 27. Typical current consumption vs temperature in Sleep mode, peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 28. Typical current consumption vs temperature in Sleep mode, peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 29. Typical current consumption vs temperature in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 34. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 35. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 36. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 37. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DocID15818 Rev 11 9/178 STM32F20xxx List of figures 9 Figure 38. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 39. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 40. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 41. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 42. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 43. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 44. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 45. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 46. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 117 Figure 47. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 48. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 49. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 50. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 51. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 52. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 125 Figure 54. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 125 Figure 55. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 130 Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 131 Figure 58. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 59. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 60. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 61. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 62. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 138 Figure 63. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Figure 64. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 141 Figure 65. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 141 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 67. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 68. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 143 Figure 69. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 144 Figure 70. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 71. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 72. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 147 Figure 73. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 147 Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 75. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 151 Figure 77. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 78. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . 153 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 155 Figure 80. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 82. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline . . . . . . . . 159 Figure 84. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 85. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Introduction STM32F20xxx 10/178 DocID15818 Rev 11 1 Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document. For information on programming, erasing and protection of the internal Flash memory, please refer to the STM32F20x/STM32F21x Flash programming manual (PM0059). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. DocID15818 Rev 11 11/178 STM32F20xxx Description 177 2 Description The STM32F20x family is based on the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices also feature an adaptive real-time memory accelerator (ART Accelerator™) which allows to achieve a performance equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. This performance has been validated using the CoreMark benchmark. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true number random generator (RNG). They also feature standard and advanced communication interfaces. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), and a camera interface for CMOS sensors. The devices also feature standard peripherals. • Up to three I2Cs • Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external PLL to allow synchronization. • 4 USARTs and 2 UARTs • A USB OTG high-speed with full-speed capability (with the ULPI) • A second USB OTG (full-speed) • Two CANs • An SDIO interface • Ethernet and camera interface available on STM32F207xx devices only. Note: The STM32F205xx and STM32F207xx devices operate in the –40 to +105 °C temperature range from a 1.8 V to 3.6 V power supply. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). A comprehensive set of power-saving modes allow the design of low-power applications. STM32F205xx and STM32F207xx devices are offered in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.These features make the STM32F205xx and STM32F207xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Figure 4 shows the general block diagram of the device family. Description STM32F20xxx 12/178 DocID15818 Rev 11 Table 2. STM32F205xx features and peripheral counts Peripherals STM32F205Rx STM32F205Vx STM32F205Zx Flash memory in Kbytes 128 256 512 768 1024 128 256 512 768 1024 256 512 768 1024 SRAM in Kbytes System (SRAM1+SRAM2) 64 (48+16) 96 (80+16) 128 (112+16) 64 (48+16) 96 (80+16) 128 (112+16) 96 (80+16) 128 (112+16) Backup 4 4 4 FSMC memory controller No Yes(1) Ethernet No Timers General-purpose 10 Advanced-control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Comm. interfaces SPI/(I2S) 3 (2)(2) I2C 3 USART UART 42 USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface No GPIOs 51 82 114 SDIO Yes 12-bit ADC Number of channels 3 16 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 120 MHz Operating voltage 1.8 V to 3.6 V(3) STM32F20xxx Description DocID15818 Rev 11 13/178 Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Package LQFP64 LQFP64 WLCSP64 +2 LQFP6 4 LQFP64 WLCSP6 4+2 LQFP100 LQFP144 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). Table 2. STM32F205xx features and peripheral counts (continued) Peripherals STM32F205Rx STM32F205Vx STM32F205Zx Table 3. STM32F207xx features and peripheral counts Peripherals STM32F207Vx STM32F207Zx STM32F207Ix Flash memory in Kbytes 256 512 768 1024 256 512 768 1024 256 512 768 1024 SRAM in Kbytes System (SRAM1+SRAM2) 128 (112+16) Backup 4 FSMC memory controller Yes(1) Ethernet Yes Timers General-purpose 10 Advanced-control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Description STM32F20xxx 14/178 DocID15818 Rev 11 Comm. interfaces SPI/(I2S) 3 (2)(2) I2C 3 USART UART 42 USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface Yes GPIOs 82 114 140 SDIO Yes 12-bit ADC Number of channels 3 16 24 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 120 MHz Operating voltage 1.8 V to 3.6 V(3) Operating temperatures Ambient temperatures: –40 to +85 °C/–40 to +105 °C Junction temperature: –40 to + 125 °C Package LQFP100 LQFP144 LQFP176/ UFBGA176 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). Table 3. STM32F207xx features and peripheral counts (continued) Peripherals STM32F207Vx STM32F207Zx STM32F207Ix DocID15818 Rev 11 15/178 STM32F20xxx Description 177 2.1 Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F205xx and STM32F207xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F205xx and STM32F207xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F20x family remains simple as only a few pins are impacted. Figure 3 and Figure 1 provide compatible board designs between the STM32F20x and the STM32F10xxx family. Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package 31 1 16 17 32 48 33 64 49 47 VSS VSS VSS VSS 0  resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration ai15962b Description STM32F20xxx 16/178 DocID15818 Rev 11 Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package Figure 3. Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package 1. RFU = reserved for future use. ai15961c 20 49 1 25 26 50 75 51 100 76 73 19 VSS VSS VDD VSS VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the 99 (RFU) STM32F2xx configuration VDD VSS VSS for STM32F10xx VDD for STM32F2xx Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VDD, VSS, or NC for the STM32F2xx ai15960c 31 71 1 36 37 72 108 73 144 109 VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration 106 VSS 30 Two 0 Ω resistors connected to: VDD VSS VSS VSS 143 (RFU) VDD VSS - VSS for the STM32F10xx - VDD, VSS, or NC for the STM32F2xx DocID15818 Rev 11 17/178 STM32F20xxx Description 177 Figure 4. STM32F20x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 60 MHz. 2. The camera interface and Ethernet are available only in STM32F207xx devices. GPIO PORT A AHB/APB2 140 AF EXT IT. WKUP PA[15:0] PB[15:0] GPIO PORT B TIM1 / PWM 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF TIM8 / PWM PC[15:0] GPIO PORT C RX, TX, CK, USART 1 CTS, RTS as AF PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E GPIO PORT F PF[15:0] GPIO PORT G PG[15:0] MOSI, MISO SPI1 SCK, NSS as AF APB2 60MHz APB1 30MHz 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 VDDREF_ADC 8 analog inputs to ADC3 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels USART2 RX, TX, CK, USART3 RX, TX, CK UART4 RX, TX as AF UART5 RX, TX as AF SPI2/I2S2 MOSI/DOUT, MISO/DIN, SCK/CK NSS/WS, MCK as AF SPI3/I2S3 MOSI/DOUT, MISO/DIN, SCK/CK NSS/WS, MCK as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF bxCAN1 TX, RX bxCAN2 TX, RX DAC1_OUT as AF DAC2_OUT as AF ITF WWDG 4 KB BKSPRAM RTC_AF1 OSC32_IN OSC_IN OSC_OUT OSC32_OUT NRST VDDA, VSSA VCAP1, VCAP2 RX, TX, CK, USART 6 CTS, RTS as AF smcard irDA smcard irDA smcard irDA smcard irDA 16b 16b 32b 16b 16b 32b 16b 16b CTS, RTS as AF CTS, RTS as AF SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA1 AHB/APB1 DMA2 I2C3/SMBUS SCL, SDA, SMBA as AF PH[15:0] GPIO PORT H PI[11:0] GPIO PORT I JTAG & SW D-BUS S-BUS I-BUS ETM NVIC MPU NJTRST, JTDI, JTDO/SWD JTDO/TRACESWO TRACECLK TRACED[3:0] JTCK/SWCLK MII or RMII as AF Ethernet MAC DMA/ MDIO as AF 10/100 FIFO USB DMA/ OTG HS FIFO DP, DM ULPI: CK, D(7:0), DIR, STP, NXT DMA2 8 Streams FIFO DMA1 8 Streams FIFO ACCEL/ CACHE SRAM 112 KB SRAM 16 KB CLK, NE [3:0], A[23:0] D[31:0], OEN, WEN, NBL[3:0], NL, NREG NWAIT/IORDY, CD NIORD, IOWR, INT[2:3] INTN, NIIS16 as AF SCL, SDA, INTN, ID, VBUS, SOF Camera interface HSYNC, VSYNC PIXCLK, D[13:0] USB PHY OTG FS DP DM FIFO FIFO AHB1 120 MHz PHY FIFO TUeSmApReTra 2tuMreB pssensor ADC1 ADC2 ADC 3 IIFF @VDDA @VDDA POR/PDR/ Supply @VDDA supervision PVD Reset Int POR XTAL OSC 4-26 MHz XTAL 32 kHz HCLKx MANAGT RTC RC HS FCLK RC LS PWR IWDG @VBAT @VDDA @VDD AWU Reset & clock control PLL1&2 PCLKx interface VDD = 1.8 to 3.6 V VSS Voltage regulator 3.3 V to 1.2 V VDD12 Power managmt @VDD Backup register RTC_AF1 SCL/SDA, INTN, ID, VBUS, SOF AHB bus-matrix 8S7M APB2 60MHz AHB2 120 MHz LS LS 2 channels as AF 1 channel as AF TIM14 1 channel as AF 16b 16b 16b 2 channels as AF TIM9 1 channel as AF TIM10 16b 16b 1 channel as AF TIM11 16b BOR DAC1 DAC2 Flash 1 Mbyte SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash External memory controller (FSMC) TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 ai17614c 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF FIFO RNG ARM Cortex-M3 120 MHz ART accelerator APB1 30MHz AHB3 Functional overview STM32F20xxx 18/178 DocID15818 Rev 11 3 Functional overview 3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, the STM32F20x family is compatible with all ARM tools and software. Figure 4 shows the general block diagram of the STM32F20x family. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M3 processors. It balances the inherent performance advantage of the ARM Cortex-M3 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full 150 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DocID15818 Rev 11 19/178 STM32F20xxx Functional overview 177 3.4 Embedded Flash memory The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All STM32F20x products embed: • Up to 128 Kbytes of system SRAM accessed (read/write) at CPU clock speed with 0 wait states • 4 Kbytes of backup SRAM. The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Functional overview STM32F20xxx 20/178 DocID15818 Rev 11 Figure 5. Multi-AHB matrix 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. ARM Cortex-M3 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S S0 S1 S2 S3 S4 S5 S6 S7 ICODE DCODE ART ACCEL. Flash memory SRAM 112 Kbyte SRAM 16 Kbyte AHB1 periph AHB2 periph FSMC Static MemCtl M0 M1 M2 M3 M4 M5 M6 I-bus D-bus S-bus DMA_P1 DMA_MEM1 DMA_MEM2 DMA_P2 ETHERNET_M USB_HS_M ai15963c APB1 APB2 DocID15818 Rev 11 21/178 STM32F20xxx Functional overview 177 The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART and UART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. 3.9 Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Code execution from external memory except for NAND Flash and PC Card • Maximum frequency (fHCLK) for external access is 60 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 Nested vectored interrupt controller (NVIC) The STM32F20x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M3. The NVIC main features are the following: • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. Functional overview STM32F20xxx 22/178 DocID15818 Rev 11 3.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 3.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the system clock. Several prescalers and PLLs allow the configuration of the three AHB buses, the highspeed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is 60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz. The devices embed a dedicate PLL (PLLI2S) which allow to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 3.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates DocID15818 Rev 11 23/178 STM32F20xxx Functional overview 177 in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 19: Power supply scheme for more details. 3.15 Power supply supervisor The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. On devices in WLCSP64+2 package, the BOR, POR and PDR features can be disabled by setting IRROFF pin to VDD. In this mode an external power supply supervisor is required (see Section 3.16). The devices also feature an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.16 Voltage regulator The regulator has five operating modes: • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down • Regulator OFF – Regulator OFF/internal reset ON – Regulator OFF/internal reset OFF 3.16.1 Regulator ON The regulator ON modes are activated by default on LQFP packages.On WLCSP64+2 package, they are activated by connecting both REGOFF and IRROFF pins to VSS, while only REGOFF must be connected to VSS on UFBGA176 package (IRROFF is not available). VDD minimum value is 1.8 V. Functional overview STM32F20xxx 24/178 DocID15818 Rev 11 There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode • LPR is used in Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost). Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to Figure 19: Power supply scheme and Table 16: VCAP1/VCAP2 operating conditions. All packages have the regulator ON feature. 3.16.2 Regulator OFF This feature is available only on packages featuring the REGOFF pin. The regulator is disabled by holding REGOFF high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 19: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used at power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection at reset or pre-reset is required. Regulator OFF/internal reset ON On WLCSP64+2 package, this mode is activated by connecting REGOFF pin to VDD and IRROFF pin to VSS. On UFBGA176 package, only REGOFF must be connected to VDD (IRROFF not available). In this mode, VDD/VDDA minimum value is 1.8 V. The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. DocID15818 Rev 11 25/178 STM32F20xxx Functional overview 177 Figure 6. Regulator OFF/internal reset ON The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 8). • Otherwise, If the time for VCAP_1 and VCAP_2 to reach 1.08 V is slower than the time for VDD to reach 1.8 V, then PA0 should be asserted low externally (see Figure 9). • If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. Regulator OFF/internal reset OFF On WLCSP64+2 package, this mode activated by connecting REGOFF to VSS and IRROFF to VDD. IRROFF cannot be activated in conjunction with REGOFF. This mode is available only on the WLCSP64+2 package. It allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins. In this mode, the integrated power-on reset (POR)/ powerdown reset (PDR) circuitry is disabled. An external power supply supervisor should monitor both the external 1.2 V and the external VDD supply voltage, and should maintain the device in reset mode as long as they remain below a specified threshold. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V. This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving modes allows to design low-power applications. ai18476b REGOFF VCAP_1 VCAP_2 PA0 1.2 V VDD (1.8 to 3.6 V) Power-down reset risen before VCAP_1/VCAP_2 stabilization NRST IRROFF VDD Application reset signal (optional) External VCAP_1/2 power supply supervisor Ext. reset controller active when VCAP_1/2 < 1.08 V Functional overview STM32F20xxx 26/178 DocID15818 Rev 11 Figure 7. Regulator OFF/internal reset OFF The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains (see Figure 8). • PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V, and until VDD reaches 1.7 V. • NRST should be controlled by an external reset controller to keep the device under reset when VDD is below 1.7 V (see Figure 9). In this mode, when the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry is disabled. • The embedded programmable voltage detector (PVD) is disabled. • VBAT functionality is no more available and VBAT pin should be connected to VDD. REGOFF VCAP_1 ai18477b VCAP_2 NRST 1.2 V IRROFF VDD VDD 1.2 V External VDD/VCAP_1/2 power supply supervisor Ext. reset controller active when VDD<1.7V and VCAP_1/2 < 1.08 V PA0 DocID15818 Rev 11 27/178 STM32F20xxx Functional overview 177 Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD time 1.08 V PDR=1.8 V VCAP_1/V 1.2 V CAP_2 time PA0 tied to NRST NRST VDD time 1.08 V PDR=1.8 V VCAP_1/VCAP_2 1.2 V time PA0 asserted externally NRST Functional overview STM32F20xxx 28/178 DocID15818 Rev 11 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability 3.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F20x devices includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the following: • Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 day of the month. • Programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. • It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal lowpower RC oscillator or the high-speed external clock divided by 128. The internal lowspeed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. • Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 μs to every 36 hours. • A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which need to be retained in VBAT and standby mode.This memory area is disabled to minimize power consumption (see Section 3.18: Low-power modes). It can be enabled by software. Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON/internal reset ON Regulator OFF/internal reset ON Regulator OFF/internal reset OFF LQFP64 LQFP100 LQFP144 LQFP176 Yes No No WLCSP 64+2 Yes REGOFF and IRROFF set to VSS Yes REGOFF set to VDD and IRROFF set to VSS Yes REGOFF set to VSS and IRROFF set to VDD UFBGA176 Yes REGOFF set to VSS Yes REGOFF set to VDD No DocID15818 Rev 11 29/178 STM32F20xxx Functional overview 177 The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin. 3.18 Low-power modes The STM32F20x family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped when the device enters the Stop or Standby mode. 3.19 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery or an external supercapacitor. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When using WLCSP64+2 package, if IRROFF pin is connected to VDD, the VBAT functionality is no more available and VBAT pin should be connected to VDD. Functional overview STM32F20xxx 30/178 DocID15818 Rev 11 3.20 Timers and watchdogs The STM32F20x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. 3.20.1 Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output Table 5. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary output Max interface clock Max timer clock Advancedcontrol TIM1, TIM8 16-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 Yes 60 MHz 120 MHz General purpose TIM2, TIM5 32-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 No 30 MHz 60 MHz TIM3, TIM4 16-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 No 30 MHz 60 MHz Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 30 MHz 60 MHz General purpose TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 60 MHz 120 MHz TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 60 MHz 120 MHz TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 30 MHz 60 MHz TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 30 MHz 60 MHz DocID15818 Rev 11 31/178 STM32F20xxx Functional overview 177 If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control timer features are shared with those of the standard TIMx timers which have the same architecture. The advanced-control timer can therefore work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 3.20.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F20x devices (see Table 5 for differences). TIM2, TIM3, TIM4, TIM5 The STM32F20x include 4 full-featured general-purpose timers. TIM2 and TIM5 are 32-bit timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are based on a 32- bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. The counters of TIM2, TIM3, TIM4, TIM5 can be frozen in debug mode. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 halleffect sensors. TIM10, TIM11 and TIM9 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. TIM12, TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.20.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. Functional overview STM32F20xxx 32/178 DocID15818 Rev 11 3.20.4 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.20.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source 3.21 Inter-integrated circuit interface (I²C) Up to three I2C bus interfaces can operate in multimaster and slave modes. They can support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 3.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) The STM32F20x devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at up to 3.75 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. DocID15818 Rev 11 33/178 STM32F20xxx Functional overview 177 3.23 Serial peripheral interface (SPI) The STM32F20x devices feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 30 Mbits/s, while SPI2 and SPI3 can communicate at up to 15 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 3.24 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, in half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx interfaces can be served by the DMA controller. 3.25 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. Table 6. USART feature comparison USART name Standard features Modem (RTS/CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s (oversampling by 16) Max. baud rate in Mbit/s (oversampling by 8) APB mapping USART1 X X X X X X 1.87 7.5 APB2 (max. 60 MHz) USART2 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) USART3 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) UART4 X - X - X - 1.87 3.75 APB1 (max. 30 MHz) UART5 X - X - X - 3.75 3.75 APB1 (max. 30 MHz) USART6 X X X X X X 3.75 7.5 APB2 (max. 60 MHz) Functional overview STM32F20xxx 34/178 DocID15818 Rev 11 The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F207xx devices. The STM32F207xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F207xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F207xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F207xx. The STM32F207xx includes the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F20x and STM32F21x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time 3.27 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one DocID15818 Rev 11 35/178 STM32F20xxx Functional overview 177 CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral. 3.28 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected • Internal FS OTG PHY support 3.29 Universal serial bus on-the-go high-speed (OTG_HS) The STM32F20x devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Functional overview STM32F20xxx 36/178 DocID15818 Rev 11 3.30 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 3.31 Digital camera interface (DCMI) The camera interface is not available in STM32F205xx devices. STM32F207xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image 3.32 True random number generator (RNG) All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers produced by an integrated analog circuit. 3.33 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to 120 MHz that leads to a maximum I/O toggling speed of 60 MHz. DocID15818 Rev 11 37/178 STM32F20xxx Functional overview 177 3.34 ADCs (analog-to-digital converters) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 3.35 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. Functional overview STM32F20xxx 38/178 DocID15818 Rev 11 3.37 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.38 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F20x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID15818 Rev 11 39/178 STM32F20xxx Pinouts and pin description 177 4 Pinouts and pin description Figure 10. STM32F20x LQFP64 pinout 1. The above figure shows the package top view. Figure 11. STM32F20x WLCSP64+2 ballout 1. The above figure shows the package top view. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14-OSC32_IN PC15-OSC32_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai15969c PC13-RTC_AF1 PH0-OSC_IN PH1-OSC_OUT VDD VSS 1 2 3 8 A PA14 PA15 PC12 PB3 PB5 PB7 PB9 VDD B PA13 PC10 PB4 PB6 BOOT0 PB8 PC13 C PA12 VCAP_2 PC11 PD2 IRROFF D PC9 PA11 PA10 PC2 E PA8 PA9 F PC7 PC8 G PB15 PC6 PC5 PA3 PC3 H PB14 PB13 PB10 PC4 J PB12 PB1 1 VCAP_1 PB2 PB0 PA7 PA4 ai18470c 4 5 6 7 9 VBAT VSS PC14 PC15 VSS VDD VDD PA0 NRST PH0- OSC_IN VSS VREF+ PC1 PH1- OSC_OUT PC0 PA6 PA5 REGOFF PA1 VSS_5 PB1 PA2 Pinouts and pin description STM32F20xxx 40/178 DocID15818 Rev 11 Figure 12. STM32F20x LQFP100 pinout 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 PE3 PE4 PE5 PE6 VBAT PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0-WKUP PA1 PA2 VDD VSS VCAP_2 PA13 PA 12 PA11 PA10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD RFU VDD PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai15970e LQFP100 PC13-RTC_AF1 PH1-OSC_OUT DocID15818 Rev 11 41/178 STM32F20xxx Pinouts and pin description 177 Figure 13. STM32F20x LQFP144 pinout 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. RFU VDD PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 VDD PE3 VSS PE4 PE5 PA13 PE6 PA12 VBAT PA11 PC13-RTC_AF1 PA10 PC14-OSC32_IN PA9 PC15-OSC32_OUT PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 VDD PF5 VSS VSS PG8 VDD PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0-OSC_IN PD15 PH1-OSC_OUT PD14 NRST VDD PC0 VSS PC1 PD13 PC2 PD12 PC3 PD11 VSSA VDD PD10 PD9 VREF+ PD8 VDDA PB15 PA0-WKUP PB14 PA1 PB13 PA2 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 LQFP144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai15971e VCAP_2 Pinouts and pin description STM32F20xxx 42/178 DocID15818 Rev 11 Figure 14. STM32F20x LQFP176 pinout 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. PDR_ON VDD PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PI7 PI6 PE2 VDD PE3 VSS PE4 PE5 PA13 PE6 PA12 VBAT PA11 PI8-RTC_AF2 PA10 PC14-OSC32_IN PA9 PC15-OSC32_OUT PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 VDD PF5 VSS VSS PG8 VDD PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0-OSC_IN PD15 PH1-OSC_OUT PD14 NRST VDD PC0 VSS PC1 PD13 PC2 PD12 PC3 PD11 VSSA PD10 VDD PD9 VREF+ PD8 VDDA PB15 PA0-WKUP PB14 PA1 PB13 PA2 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 LQFP176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 ai15972e VCAP_2 PI4 PA15 PA14 VDD VSS PI3 PI2 PI5 140 139 138 137 136 135 134 133 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 88 81 82 83 84 85 86 87 PI1 PI0 PH15 PH14 PH13 VDD VSS PH12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 PC13-RTC_AF1 PI9 PI10 PI11 VSS VDD PH2 PH3 DocID15818 Rev 11 43/178 STM32F20xxx Pinouts and pin description 177 Figure 15. STM32F20x UFBGA176 ballout 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. 1 2 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD RFU VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13- TAMP1 PI8- TAMP2 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14- OSC32_IN PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15- OSC32_OUT VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8 G PH0- OSC_IN VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1- OSC_OUT PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 REGOFF PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0- WKUP PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 ai17293c VSS 3 4 5 6 7 8 Table 7. Legend/abbreviations used in the pinout table Name Abbreviation Definition Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I/O Input/ output pin I/O structure FT 5 V tolerant I/O TTa 3.3 V tolerant I/O B Dedicated BOOT0 pin NRST Bidirectional reset pin with embedded weak pull-up resistor Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Pinouts and pin description STM32F20xxx 44/178 DocID15818 Rev 11 Table 8. STM32F20x pin and ball definitions Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 - - 1 1 1 A2 PE2 I/O FT TRACECLK, FSMC_A23, ETH_MII_TXD3, EVENTOUT - - 2 2 2 A1 PE3 I/O FT TRACED0,FSMC_A19, EVENTOUT - - 3 3 3 B1 PE4 I/O FT TRACED1,FSMC_A20, DCMI_D4, EVENTOUT - - 4 4 4 B2 PE5 I/O FT TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6, EVENTOUT - - 5 5 5 B3 PE6 I/O FT TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7, EVENTOUT 1 A9 6 6 6 C1 VBAT S - - - - 7 D2 PI8 I/O FT (2)(3) EVENTOUT RTC_AF2 2 B8 7 7 8 D1 PC13 I/O FT (2)(3) EVENTOUT RTC_AF1 3 B9 8 8 9 E1 PC14/OSC32_IN (PC14) I/O FT (2)(3) EVENTOUT OSC32_IN(4) 4 C9 9 9 10 F1 PC15-OSC32_OUT (PC15) I/O FT (2)(3) EVENTOUT OSC32_OUT(4) - - - - 11 D3 PI9 I/O FT CAN1_RX,EVENTOUT - - - - 12 E3 PI10 I/O FT ETH_MII_RX_ER, EVENTOUT - - - - 13 E4 PI11 I/O FT OTG_HS_ULPI_DIR, EVENTOUT - - - - 14 F2 VSS S - - - - 15 F3 VDD S - - - 10 16 E2 PF0 I/O FT FSMC_A0, I2C2_SDA, EVENTOUT - - - 11 17 H3 PF1 I/O FT FSMC_A1, I2C2_SCL, EVENTOUT - - - 12 18 H2 PF2 I/O FT FSMC_A2, I2C2_SMBA, EVENTOUT - - - 13 19 J2 PF3 I/O FT (4) FSMC_A3, EVENTOUT ADC3_IN9 DocID15818 Rev 11 45/178 STM32F20xxx Pinouts and pin description 177 - - - 14 20 J3 PF4 I/O FT (4) FSMC_A4, EVENTOUT ADC3_IN14 - - - 15 21 K3 PF5 I/O FT (4) FSMC_A5, EVENTOUT ADC3_IN15 - H9 10 16 22 G2 VSS S - - 11 17 23 G3 VDD S - - - 18 24 K2 PF6 I/O FT (4) TIM10_CH1, FSMC_NIORD, EVENTOUT ADC3_IN4 - - - 19 25 K1 PF7 I/O FT (4) TIM11_CH1,FSMC_NREG, EVENTOUT ADC3_IN5 - - - 20 26 L3 PF8 I/O FT (4) TIM13_CH1, FSMC_NIOWR, EVENTOUT ADC3_IN6 - - - 21 27 L2 PF9 I/O FT (4) TIM14_CH1, FSMC_CD, EVENTOUT ADC3_IN7 - - - 22 28 L1 PF10 I/O FT (4) FSMC_INTR, EVENTOUT ADC3_IN8 5 E9 12 23 29 G1 PH0/OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 F9 13 24 30 H1 PH1/OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 E8 14 25 31 J1 NRST I/O 8 G9 15 26 32 M2 PC0 I/O FT (4) OTG_HS_ULPI_STP, EVENTOUT ADC123_ IN10 9 F8 16 27 33 M3 PC1 I/O FT (4) ETH_MDC, EVENTOUT ADC123_ IN11 10 D7 17 28 34 M4 PC2 I/O FT (4) SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, EVENTOUT ADC123_ IN12 11 G8 18 29 35 M5 PC3 I/O FT (4) SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, EVENTOUT ADC123_ IN13 - - 19 30 36 - VDD S 12 - 20 31 37 M1 VSSA S - - - - - N1 VREF- S - F7 21 32 38 P1 VREF+ S Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Pinouts and pin description STM32F20xxx 46/178 DocID15818 Rev 11 13 - 22 33 39 R1 VDDA S 14 E7 23 34 40 N3 PA0-WKUP (PA0) I/O FT (4)(5) USART2_CTS, UART4_TX, ETH_MII_CRS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, EVENTOUT ADC123_IN0, WKUP 15 H8 24 35 41 N2 PA1 I/O FT (4) USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2, EVENTOUT ADC123_IN1 16 J9 25 36 42 P2 PA2 I/O FT (4) USART2_TX,TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO, EVENTOUT ADC123_IN2 - - - - 43 F4 PH2 I/O FT ETH_MII_CRS, EVENTOUT - - - - 44 G4 PH3 I/O FT ETH_MII_COL, EVENTOUT - - - - 45 H4 PH4 I/O FT I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT - - - - 46 J4 PH5 I/O FT I2C2_SDA, EVENTOUT 17 G7 26 37 47 R2 PA3 I/O FT (4) USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL, EVENTOUT ADC123_IN3 18 F1 27 38 48 - VSS S H7 L4 REGOFF I/O 19 E1 28 39 49 K4 VDD S 20 J8 29 40 50 N4 PA4 I/O TTa (4) SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF, I2S3_WS, EVENTOUT ADC12_IN4, DAC_OUT1 21 H6 30 41 51 P4 PA5 I/O TTa (4) SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N, EVENTOUT ADC12_IN5, DAC_OUT2 Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 DocID15818 Rev 11 47/178 STM32F20xxx Pinouts and pin description 177 22 H5 31 42 52 P3 PA6 I/O FT (4) SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN, EVENTOUT ADC12_IN6 23 J7 32 43 53 R3 PA7 I/O FT (4) SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N, ETH_RMII_CRS_DV, EVENTOUT ADC12_IN7 24 H4 33 44 54 N5 PC4 I/O FT (4) ETH_RMII_RXD0, ETH_MII_RXD0, EVENTOUT ADC12_IN14 25 G3 34 45 55 P5 PC5 I/O FT (4) ETH_RMII_RXD1, ETH_MII_RXD1, EVENTOUT ADC12_IN15 26 J6 35 46 56 R5 PB0 I/O FT (4) TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N, EVENTOUT ADC12_IN8 27 J5 36 47 57 R4 PB1 I/O FT (4) TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N, EVENTOUT ADC12_IN9 28 J4 37 48 58 M6 PB2/BOOT1 (PB2) I/O FT EVENTOUT - - - 49 59 R6 PF11 I/O FT DCMI_D12, EVENTOUT - - - 50 60 P6 PF12 I/O FT FSMC_A6, EVENTOUT - - - 51 61 M8 VSS S - - - 52 62 N8 VDD S - - - 53 63 N6 PF13 I/O FT FSMC_A7, EVENTOUT - - - 54 64 R7 PF14 I/O FT FSMC_A8, EVENTOUT - - - 55 65 P7 PF15 I/O FT FSMC_A9, EVENTOUT - - - 56 66 N7 PG0 I/O FT FSMC_A10, EVENTOUT - - - 57 67 M7 PG1 I/O FT FSMC_A11, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Pinouts and pin description STM32F20xxx 48/178 DocID15818 Rev 11 - - 38 58 68 R8 PE7 I/O FT FSMC_D4,TIM1_ETR, EVENTOUT - - 39 59 69 P8 PE8 I/O FT FSMC_D5,TIM1_CH1N, EVENTOUT - - 40 60 70 P9 PE9 I/O FT FSMC_D6,TIM1_CH1, EVENTOUT - - - 61 71 M9 VSS S - - - 62 72 N9 VDD S - - 41 63 73 R9 PE10 I/O FT FSMC_D7,TIM1_CH2N, EVENTOUT - - 42 64 74 P10 PE11 I/O FT FSMC_D8,TIM1_CH2, EVENTOUT - - 43 65 75 R10 PE12 I/O FT FSMC_D9,TIM1_CH3N, EVENTOUT - - 44 66 76 N11 PE13 I/O FT FSMC_D10,TIM1_CH3, EVENTOUT - - 45 67 77 P11 PE14 I/O FT FSMC_D11,TIM1_CH4, EVENTOUT - - 46 68 78 R11 PE15 I/O FT FSMC_D12,TIM1_BKIN, EVENTOUT 29 H3 47 69 79 R12 PB10 I/O FT SPI2_SCK, I2S2_SCK, I2C2_SCL,USART3_TX,OT G_HS_ULPI_D3,ETH_MII_R X_ER,TIM2_CH3, EVENTOUT 30 J2 48 70 80 R13 PB11 I/O FT I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN, ETH_MII_TX_EN, TIM2_CH4, EVENTOUT 31 J3 49 71 81 M10 VCAP_1 S 32 - 50 72 82 N10 VDD S - - - - 83 M11 PH6 I/O FT I2C2_SMBA, TIM12_CH1, ETH_MII_RXD2, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 DocID15818 Rev 11 49/178 STM32F20xxx Pinouts and pin description 177 - - - - 84 N12 PH7 I/O FT I2C3_SCL, ETH_MII_RXD3, EVENTOUT - - - - 85 M12 PH8 I/O FT I2C3_SDA, DCMI_HSYNC, EVENTOUT - - - - 86 M13 PH9 I/O FT I2C3_SMBA, TIM12_CH2, DCMI_D0, EVENTOUT - - - - 87 L13 PH10 I/O FT TIM5_CH1, DCMI_D1, EVENTOUT - - - - 88 L12 PH11 I/O FT TIM5_CH2, DCMI_D2, EVENTOUT - - - - 89 K12 PH12 I/O FT TIM5_CH3, DCMI_D3, EVENTOUT - - - - 90 H12 VSS S - - - - 91 J12 VDD S 33 J1 51 73 92 P12 PB12 I/O FT SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0, ETH_MII_TXD0, OTG_HS_ID, EVENTOUT 34 H2 52 74 93 P13 PB13 I/O FT SPI2_SCK, I2S2_SCK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6, ETH_RMII_TXD1, ETH_MII_TXD1, EVENTOUT OTG_HS_ VBUS 35 H1 53 75 94 R14 PB14 I/O FT SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM USART3_RTS, TIM8_CH2N, EVENTOUT 36 G1 54 76 95 R15 PB15 I/O FT SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP, RTC_50Hz, EVENTOUT - - 55 77 96 P15 PD8 I/O FT FSMC_D13, USART3_TX, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Pinouts and pin description STM32F20xxx 50/178 DocID15818 Rev 11 - - 56 78 97 P14 PD9 I/O FT FSMC_D14, USART3_RX, EVENTOUT - - 57 79 98 N15 PD10 I/O FT FSMC_D15, USART3_CK, EVENTOUT - - 58 80 99 N14 PD11 I/O FT FSMC_A16,USART3_CTS, EVENTOUT - - 59 81 100 N13 PD12 I/O FT FSMC_A17,TIM4_CH1, USART3_RTS, EVENTOUT - - 60 82 101 M15 PD13 I/O FT FSMC_A18,TIM4_CH2, EVENTOUT - - - 83102 - VSS S - - - 84103J13 VDD S - - 61 85 104 M14 PD14 I/O FT FSMC_D0,TIM4_CH3, EVENTOUT - - 62 86 105 L14 PD15 I/O FT FSMC_D1,TIM4_CH4, EVENTOUT - - - 87 106 L15 PG2 I/O FT FSMC_A12, EVENTOUT - - - 88 107 K15 PG3 I/O FT FSMC_A13, EVENTOUT - - - 89 108 K14 PG4 I/O FT FSMC_A14, EVENTOUT - - - 90 109 K13 PG5 I/O FT FSMC_A15, EVENTOUT - - - 91 110 J15 PG6 I/O FT FSMC_INT2, EVENTOUT - - - 92 111 J14 PG7 I/O FT FSMC_INT3 ,USART6_CK, EVENTOUT - - - 93 112 H14 PG8 I/O FT USART6_RTS, ETH_PPS_OUT, EVENTOUT - - - 94 113G12 VSS S - - - 95 114H13 VDD S 37 G2 63 96 115 H15 PC6 I/O FT I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 DocID15818 Rev 11 51/178 STM32F20xxx Pinouts and pin description 177 38 F2 64 97 116 G15 PC7 I/O FT I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2, EVENTOUT 39 F3 65 98 117 G14 PC8 I/O FT TIM8_CH3,SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2, EVENTOUT 40 D1 66 99 118 F14 PC9 I/O FT I2S2_CKIN, I2S3_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4, EVENTOUT 41 E2 67 100 119 F15 PA8 I/O FT MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF, EVENTOUT 42 E3 68 101 120 E15 PA9 I/O FT USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0, EVENTOUT OTG_FS_ VBUS 43 D3 69 102 121 D15 PA10 I/O FT USART1_RX, TIM1_CH3, OTG_FS_ID,DCMI_D1, EVENTOUT 44 D2 70 103 122 C15 PA11 I/O FT USART1_CTS, CAN1_RX, TIM1_CH4,OTG_FS_DM, EVENTOUT 45 C1 71 104 123 B15 PA12 I/O FT USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP, EVENTOUT 46 B2 72 105 124 A15 PA13 (JTMS-SWDIO) I/O FT JTMS-SWDIO, EVENTOUT 47 C2 73 106 125 F13 VCAP_2 S - B1 74 107 126 F12 VSS S 48 A8 75 108 127 G13 VDD S - - - - 128 E12 PH13 I/O FT TIM8_CH1N, CAN1_TX, EVENTOUT - - - - 129 E13 PH14 I/O FT TIM8_CH2N, DCMI_D4, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Pinouts and pin description STM32F20xxx 52/178 DocID15818 Rev 11 - - - - 130 D13 PH15 I/O FT TIM8_CH3N, DCMI_D11, EVENTOUT - - - - 131E14 PI0 I/O FT TIM5_CH4, SPI2_NSS, I2S2_WS, DCMI_D13, EVENTOUT - - - - 132D14 PI1 I/O FT SPI2_SCK, I2S2_SCK, DCMI_D8, EVENTOUT - - - - 133C14 PI2 I/O FT TIM8_CH4 ,SPI2_MISO, DCMI_D9, EVENTOUT - - - - 134C13 PI3 I/O FT TIM8_ETR, SPI2_MOSI, I2S2_SD, DCMI_D10, EVENTOUT - - - - 135 D9 VSS S - - - - 136 C9 VDD S 49 A1 76 109 137 A14 PA14 (JTCK-SWCLK) I/O FT JTCK-SWCLK, EVENTOUT 50 A2 77 110 138 A13 PA15 (JTDI) I/O FT JTDI, SPI3_NSS, I2S3_WS,TIM2_CH1_ETR, SPI1_NSS, EVENTOUT 51 B3 78 111 139 B14 PC10 I/O FT SPI3_SCK, I2S3_SCK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX, EVENTOUT 52 C3 79 112 140 B13 PC11 I/O FT UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4,USART3_RX, EVENTOUT 53 A3 80 113 141 A12 PC12 I/O FT UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD, USART3_CK, EVENTOUT - - 81 114142B12 PD0 I/O FT FSMC_D2,CAN1_RX, EVENTOUT - - 82 115 143 C12 PD1 I/O FT FSMC_D3, CAN1_TX, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 DocID15818 Rev 11 53/178 STM32F20xxx Pinouts and pin description 177 54 C7 83 116 144 D12 PD2 I/O FT TIM3_ETR,UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT - - 84 117 145 D11 PD3 I/O FT FSMC_CLK,USART2_CTS, EVENTOUT - - 85 118 146 D10 PD4 I/O FT FSMC_NOE, USART2_RTS, EVENTOUT - - 86 119 147 C11 PD5 I/O FT FSMC_NWE,USART2_TX, EVENTOUT - - - 120 148 D8 VSS S - - - 121 149 C8 VDD S - - 87 122 150 B11 PD6 I/O FT FSMC_NWAIT, USART2_RX, EVENTOUT - - 88 123 151 A11 PD7 I/O FT USART2_CK,FSMC_NE1, FSMC_NCE2, EVENTOUT - - - 124 152 C10 PG9 I/O FT USART6_RX, FSMC_NE2,FSMC_NCE3, EVENTOUT - - - 125 153 B10 PG10 I/O FT FSMC_NCE4_1, FSMC_NE3, EVENTOUT - - - 126 154 B9 PG11 I/O FT FSMC_NCE4_2, ETH_MII_TX_EN , ETH _RMII_TX_EN, EVENTOUT - - - 127 155 B8 PG12 I/O FT FSMC_NE4, USART6_RTS, EVENTOUT - - - 128 156 A8 PG13 I/O FT FSMC_A24, USART6_CTS, ETH_MII_TXD0, ETH_RMII_TXD0, EVENTOUT - - - 129 157 A7 PG14 I/O FT FSMC_A25, USART6_TX, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT - - - 130 158 D7 VSS S Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Pinouts and pin description STM32F20xxx 54/178 DocID15818 Rev 11 - - - 131 159 C7 VDD S - - - 132 160 B7 PG15 I/O FT USART6_CTS, DCMI_D13, EVENTOUT 55 A4 89 133 161 A10 PB3 (JTDO/TRACESWO) I/O FT JTDO/ TRACESWO, SPI3_SCK, I2S3_SCK, TIM2_CH2, SPI1_SCK, EVENTOUT 56 B4 90 134 162 A9 PB4 I/O FT NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO, EVENTOUT 57 A5 91 135 163 A6 PB5 I/O FT I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10, I2S3_SD, EVENTOUT 58 B5 92 136 164 B6 PB6 I/O FT I2C1_SCL,, TIM4_CH1, CAN2_TX, DCMI_D5,USART1_TX, EVENTOUT 59 A6 93 137 165 B5 PB7 I/O FT I2C1_SDA, FSMC_NL(6), DCMI_VSYNC, USART1_RX, TIM4_CH2, EVENTOUT 60 B6 94 138 166 D6 BOOT0 I B VPP 61 B7 95 139 167 A5 PB8 I/O FT TIM4_CH3,SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX, EVENTOUT 62 A7 96 140 168 B4 PB9 I/O FT SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX, EVENTOUT - - 97 141 169 A4 PE0 I/O FT TIM4_ETR, FSMC_NBL0, DCMI_D2, EVENTOUT Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 DocID15818 Rev 11 55/178 STM32F20xxx Pinouts and pin description 177 - - 98 142 170 A3 PE1 I/O FT FSMC_NBL1, DCMI_D3, EVENTOUT - - - - - D5 VSS S 63 D8 - - - - VSS S - - 99 143 171 C6 RFU (7) 64 D9 100 144 172 C5 VDD S - - - - 173 D4 PI4 I/O FT TIM8_BKIN, DCMI_D5, EVENTOUT - - - - 174 C4 PI5 I/O FT TIM8_CH1, DCMI_VSYNC, EVENTOUT - - - - 175 C3 PI6 I/O FT TIM8_CH2, DCMI_D6, EVENTOUT - - - - 176 C2 PI7 I/O FT TIM8_CH3, DCMI_D7, EVENTOUT - C8 - - - - IRROFF I/O 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is used as an internal Reset (active low). 6. FSMC_NL pin is also named FSMC_NADV on memory devices. 7. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. Table 8. STM32F20x pin and ball definitions (continued) Pins Pin name (function after reset)(1) Pin type I/O structure Note Alternate functions Additional functions LQFP64 WLCSP64+2 LQFP100 LQFP144 LQFP176 UFBGA176 Table 9. FSMC pin definition Pins FSMC LQFP100 CF NOR/PSRAM/S RAM NOR/PSRAM Mux NAND 16 bit PE2 A23 A23 Yes PE3 A19 A19 Yes Pinouts and pin description STM32F20xxx 56/178 DocID15818 Rev 11 PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 - PF1 A1 A1 - PF2 A2 A2 - PF3 A3 A3 - PF4 A4 A4 - PF5 A5 A5 - PF6 NIORD - PF7 NREG - PF8 NIOWR - PF9 CD - PF10 INTR - PF12 A6 A6 - PF13 A7 A7 - PF14 A8 A8 - PF15 A9 A9 - PG0 A10 A10 - PG1 A11 - PE7 D4 D4 DA4 D4 Yes PE8 D5 D5 DA5 D5 Yes PE9 D6 D6 DA6 D6 Yes PE10 D7 D7 DA7 D7 Yes PE11 D8 D8 DA8 D8 Yes PE12 D9 D9 DA9 D9 Yes PE13 D10 D10 DA10 D10 Yes PE14 D11 D11 DA11 D11 Yes PE15 D12 D12 DA12 D12 Yes PD8 D13 D13 DA13 D13 Yes PD9 D14 D14 DA14 D14 Yes PD10 D15 D15 DA15 D15 Yes PD11 A16 A16 CLE Yes Table 9. FSMC pin definition (continued) Pins FSMC LQFP100 CF NOR/PSRAM/S RAM NOR/PSRAM Mux NAND 16 bit DocID15818 Rev 11 57/178 STM32F20xxx Pinouts and pin description 177 PD12 A17 A17 ALE Yes PD13 A18 A18 Yes PD14 D0 D0 DA0 D0 Yes PD15 D1 D1 DA1 D1 Yes PG2 A12 - PG3 A13 - PG4 A14 - PG5 A15 - PG6 INT2 - PG7 INT3 - PD0 D2 D2 DA2 D2 Yes PD1 D3 D3 DA3 D3 Yes PD3 CLK CLK Yes PD4 NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes PD7 NE1 NE1 NCE2 Yes PG9 NE2 NE2 NCE3 - PG10 NCE4_1 NE3 NE3 - PG11 NCE4_2 - PG12 NE4 NE4 - PG13 A24 A24 - PG14 A25 A25 - PB7 NADV NADV Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes Table 9. FSMC pin definition (continued) Pins FSMC LQFP100 CF NOR/PSRAM/S RAM NOR/PSRAM Mux NAND 16 bit Pinouts and pin description STM32F20xxx 58/178 DocID15818 Rev 11 Table 10. Alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS DCMI Port A PA0-WKUP TIM2_CH1_ETR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII _REF_CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_D0 ETH _MII_COL EVENTOUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK OTG_HS_SOF DCMI_HSYNC EVENTOUT PA5 TIM2_CH1_ETR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_C K EVENTOUT PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT PA9 TIM1_CH2 I2C3_SMBA USART1_TX DCMI_D0 EVENTOUT PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMSSWDIO EVENTOUT PA14 JTCKSWCLK EVENTOUT PA15 JTDI TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS I2S3_WS EVENTOUT STM32F20xxx Pinouts and pin description DocID15818 Rev 11 59/178 Port B PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 EVENTOUT PB2 EVENTOUT PB3 JTDO/ TRACESWO TIM2_CH2 SPI1_SCK SPI3_SCK I2S3_SCK EVENTOUT PB4 JTRST TIM3_CH1 SPI1_MISO SPI3_MISO EVENTOUT PB5 TIM3_CH2 I2C1_SMBA SPI1_MOSI SPI3_MOSI I2S3_SD CAN2_RX OTG_HS_ULPI_D7 ETH _PPS_OUT DCMI_D10 EVENTOUT PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYNC EVENTOUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS I2S2_WS CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT PB10 TIM2_CH3 I2C2_SCL SPI2_SCK I2S2_SCK USART3_TX OTG_HS_ULPI_D3 ETH_ MII_RX_ER EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_D4 ETH _MII_TX_EN ETH _RMII_TX_EN EVENTOUT PB12 TIM1_BKIN I2C2_SMBA SPI2_NSS I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_D5 ETH _MII_TXD0 ETH _RMII_TXD0 OTG_HS_ID EVENTOUT PB13 TIM1_CH1N SPI2_SCK I2S2_SCK USART3_CTS CAN2_TX OTG_HS_ULPI_D6 ETH _MII_TXD1 ETH _RMII_TXD1 EVENTOUT PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N SPI2_MOSI I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT Table 10. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS DCMI Pinouts and pin description STM32F20xxx 60/178 DocID15818 Rev 11 Port C PC0 OTG_HS_ULPI_ STP EVENTOUT PC1 ETH_MDC EVENTOUT PC2 SPI2_MISO OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT PC3 SPI2_MOSI OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN I2S3_CKIN SDIO_D1 DCMI_D3 EVENTOUT PC10 SPI3_SCK I2S3_SCK USART3_TX UART4_TX SDIO_D2 DCMI_D8 EVENTOUT PC11 SPI3_MISO USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT PC12 SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 EVENTOUT PC14- OSC32_IN EVENTOUT PC15- OSC32_OU T EVENTOUT Table 10. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS DCMI STM32F20xxx Pinouts and pin description DocID15818 Rev 11 61/178 Port D PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT Port E PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT PE1 FSMC_NBL1 DCMI_D3 EVENTOUT PE2 TRACECLK ETH _MII_TXD3 FSMC_A23 EVENTOUT PE3 TRACED0 FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT Table 10. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS DCMI Pinouts and pin description STM32F20xxx 62/178 DocID15818 Rev 11 Port F PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT PF8 TIM13_CH1 FSMC_NIOWR EVENTOUT PF9 TIM14_CH1 FSMC_CD EVENTOUT PF10 FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT Port G PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT PG7 USART6_CK FSMC_INT3 EVENTOUT PG8 USART6_RTS ETH _PPS_OUT EVENTOUT PG9 USART6_RX FSMC_NE2/ FSMC_NCE3 EVENTOUT PG10 FSMC_NCE4_1/ FSMC_NE3 EVENTOUT PG11 ETH _MII_TX_EN ETH _RMII_TX_EN FSMC_NCE4_2 EVENTOUT PG12 USART6_RTS FSMC_NE4 EVENTOUT PG13 UART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 FSMC_A24 EVENTOUT PG14 USART6_TX ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A25 EVENTOUT PG15 USART6_CTS DCMI_D13 EVENTOUT Table 10. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS DCMI STM32F20xxx Pinouts and pin description DocID15818 Rev 11 63/178 Port H PH0 - OSC_IN EVENTOUT PH1 - OSC_OUT EVENTOUT PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT PH4 I2C2_SCL OTG_HS_ULPI_N XT EVENTOUT PH5 I2C2_SDA EVENTOUT PH6 I2C2_SMBA TIM12_CH1 ETH _MII_RXD2 EVENTOUT PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT PH8 I2C3_SDA DCMI_HSYNC EVENTOUT PH9 I2C3_SMBA TIM12_CH2 DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TIM8_CH1N CAN1_TX EVENTOUT PH14 TIM8_CH2N DCMI_D4 EVENTOUT PH15 TIM8_CH3N DCMI_D11 EVENTOUT Port I PI0 TIM5_CH4 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT PI1 SPI2_SCK I2S2_SCK DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO DCMI_D9 EVENTOUT PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT PI8 EVENTOUT PI9 CAN1_RX EVENTOUT PI10 ETH _MII_RX_ER EVENTOUT PI11 OTG_HS_ULPI_ DIR EVENTOUT Table 10. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 CAN1/CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_HS DCMI Memory mapping STM32F20xxx 64/178 DocID15818 Rev 11 5 Memory mapping The memory map is shown in Figure 16. DocID15818 Rev 11 65/178 STM32F20xxx Memory mapping 177 Figure 16. Memory map 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 512-Mbyte block 5 FSMC registers 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 512-Mbyte block 1 SRAM 0x0000 0000 0x1FFF FFFF 0x2000 0000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 0x6000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xFFFF FFFF 512-Mbyte block 0 Code Flash 0x0810 0000 - 0x0FFF FFFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1FFF C000 - 0x1FFF C007 0x0800 0000 - 0x080F FFFF 0x0001 C000 - 0x07FF FFFF 0x0000 0000 - 0x000F FFFF System memory + OTP Reserved Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins SRAM (16 KB aliased by bit-banding) Reserved 0x2000 0000 - 0x2001 BFFF 0x2001 C000 - 0x2001 FFFF 0x2002 0000 - 0x3FFF FFFF TIM2 TIM3 0x4000 0000 - 0x4000 03FF TIM4 TIM5 TIM6 TIM7 Reserved 0x4000 0400 - 0x4000 07FF 0x4000 0800 - 0x4000 0BFF 0x4000 0C00 - 0x4000 0FFF 0x4000 1000 - 0x4000 13FF 0x4000 2000 - 0x4000 23FF 0x4000 2400 - 0x4000 27FF RTC & BKP registers 0x4000 2800 - 0x4000 2BFF WWDG 0x4000 2C00 - 0x4000 2FFF IWDG 0x4000 3000 - 0x4000 33FF Reserved 0x4000 3400 - 0x4000 37FF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI3/I2S3 0x4000 3C00 - 0x4000 3FFF Reserved 0x4000 4000 - 0x4000 43FF USART2 0x4000 4400 - 0x4000 47FF USART3 0x4000 4800 - 0x4000 4BFF UART4 0x4000 4C00 - 0x4000 4FFF UART5 0x4000 5000 - 0x4000 53FF I2C1 0x4000 5400 - 0x4000 57FF I2C2 0x4000 5800 - 0x4000 5BFF Reserved 0x4000 6C00 - 0x4000 6FFF PWR 0x4000 7000 - 0x4000 73FF DAC1/DAC2 0x4000 7400 - 0x4000 77FF 0x4000 7800 - 0x4000 FFFF TIM1 / PWM1 0x4001 0000 - 0x4001 03FF TIM8 / PWM2 0x4001 0400 - 0x4001 07FF Port A USART1 0x4001 1000 - 0x4001 13FF 0x4001 1400 - 0x4001 17FF Port B 0x4001 1800 - 0x4001 1FFF Port C 0x4001 2000 - 0x4001 23FF Port D 0x4001 2400 - 0x4001 27FF Port E 0x4001 2800 - 0x4001 2BFF Port F 0x4001 2C00 - 0x4001 2FFF Port G 0x4001 3000 - 0x4001 33FF Reserved 0x4001 3400 - 0x4001 37FF 0x4001 3800 - 0x4001 3BFF 0x4001 4000 - 0x4001 43FF 0x4001 4400 - 0x4001 47FF USART6 0x4001 4800 - 0x4001 4BFF 0x4002 0000 - 0x4002 03FF 0x4002 0C00 - 0x4002 0FFF 0x4002 1000 - 0x4002 13FF 0x4002 1400 - 0x4002 17FF Reset clock controller (RCC) 0x4002 1800 - 0x4002 1BFF Port H 0x4002 1C00 - 0x4002 1FFF Flash interface 0x4002 2000 - 0x4002 23FF Reserved 0x4002 2400 - 0x4002 2FFF CRC 0x4002 3000 - 0x4002 33FF FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF FSMC bank4 PC Card 0x9000 0000 - 0x9FFF FFFF FSMC control register 0xA000 0000 - 0xA000 0FFF 0xA000 1000 - 0xBFFF FFFF ai17615c Option Bytes TIM10 SYSCFG 0x4002 0400 - 0x4002 07FF 0x4002 0800 - 0x4002 0BFF SDIO Reserved Reserved 0x4001 4C00 - 0x4001 FFFF EXTI 0x4001 3C00 - 0x4001 3FFF Reserved BxCAN2 0x4000 6000 - 0x4000 63FF 0x4000 6400 - 0x4000 67FF 0x4000 6800 - 0x4000 6BFF Reserved 0x5006 1000 - 0x5FFF FFFF DCMI 0x5005 0000 - 0x5005 03FF Reserved 0x5004 0000 - 0x5004 0FFF USB OTG FS 0x5000 0000 - 0x5003 FFFF Reserved 0x4002 9400 - 0x4FFF FFFF USB OTG HS 0x4004 0000 - 0x4007 FFFF Reserved 0x4002 9400 - 0x4003 FFFF ETHERNET 0x4002 8000 - 0x4002 93FF Reserved 0x4002 6800 - 0x4002 7FFF 0x4002 6400 - 0x4002 67FF 0x4002 6000 - 0x4002 63FF DMA2 DMA1 Reserved 0x4002 5000 - 0x4002 5FFF BKPSRAM 0x4002 4000 - 0x4002 4FFF 0x4002 3C00 - 0x4002 3FFF 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Port I TIM11 TIM9 SPI1 ADC1 - ADC2 - ADC3 Reserved BxCAN1 I2C3 0x4000 5C00 - 0x4000 5FFF Reserved TIM12 TIM13 TIM14 0x4000 1C00 - 0x4000 1FFF 0x4000 1800 - 0x4000 1BFF 0x4000 1400 - 0x4000 17FF SRAM (112 KB aliased by bit-banding) Reserved 0x1FFF C008 - 0x1FFF FFFF Reserved 0x1FFF 7A10 - 0x1FFF 7FFF Reserved RNG 0x5006 0800 - 0x5006 0FFF Reserved 0x5005 0400 - 0x5006 7FFF 0x4001 0800 - 0x4001 0FFF Reserved Reserved Electrical characteristics STM32F20xxx 66/178 DocID15818 Rev 11 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 17. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 18. Figure 17. Pin loading conditions Figure 18. Pin input voltage MS19011V2 C = 50 pF MCU pin MS19010V2 MCU pin VIN DocID15818 Rev 11 67/178 STM32F20xxx Electrical characteristics 177 6.1.6 Power supply scheme Figure 19. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect REGOFF and IRROFF pins, refer to Section 3.16: Voltage regulator. 3. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 μF ceramic capacitor must be connected to one of the VDD pin. ai17527e VDD 1/2/...14/15 VBAT GP I/Os OUT IN Kernel logic (CPU, digital & RAM) Backup circuitry (OSC32K,RTC, Backup registers, backup RAM) Wakeup logic 15 × 100 nF + 1 × 4.7 μF 1.8-3.6 V VSS 1/2/...14/15 VDDA VREF+ VREFVSSA ADC Level shifter IO Logic VDD 100 nF + 1 μF VREF 100 nF + 1 μF VDD Flash memory VVCAP_1 2 × 2.2 μF CAP_2 REGOFF IRROFF Power switch Analog RCs, PLL, ... Voltage regulator Electrical characteristics STM32F20xxx 68/178 DocID15818 Rev 11 6.1.7 Current consumption measurement Figure 20. Current consumption measurement scheme 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 VBAT VDD VDDA IDD_VBAT IDD Table 11. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA, VDD)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V VIN Input voltage on five-volt tolerant pin(2) 2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current. VSS–0.3 VDD+4 Input voltage on any other pin VSS–0.3 4.0 |ΔVDDx| Variations between different VDD power pins - 50 mV |VSSX − VSS| Variations between all the different ground pins - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 6.3.14: Absolute maximum ratings (electrical sensitivity) DocID15818 Rev 11 69/178 STM32F20xxx Electrical characteristics 177 6.3 Operating conditions 6.3.1 General operating conditions Table 12. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 120 mA IVSS Total current out of VSS ground lines (sink)(1) 120 IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IINJ(PIN) (2) 2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics. Injected current on five-volt tolerant I/O(3) 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. In this case HCLK = system clock/2. DocID15818 Rev 11 77/178 STM32F20xxx Electrical characteristics 177 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Symbol Parameter Conditions fHCLK Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Run mode External clock(2), all peripherals enabled(3) 120 MHz 61 81 93 mA 90 MHz 48 68 80 60 MHz 33 53 65 30 MHz 18 38 50 25 MHz 14 34 46 16 MHz(4) 10 30 42 8 MHz 6 26 38 4 MHz 4 24 36 2 MHz 3 23 35 External clock(2), all peripherals disabled 120 MHz 33 54 66 90 MHz 27 47 59 60 MHz 19 39 51 30 MHz 11 31 43 25 MHz 8 28 41 16 MHz(4) 6 26 38 8 MHz 4 24 36 4 MHz 3 23 35 2 MHz 2 23 34 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 4. In this case HCLK = system clock/2. Electrical characteristics STM32F20xxx 78/178 DocID15818 Rev 11 Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF MS19014V1 0 10 20 30 40 50 60 0 20 40 60 80 100 120 CPU frequnecy (MHz) 105°C 85°C 70°C 55°C 30°C 0°C -45°C IDD(RUN) (mA) MS19015V1 0 5 10 15 20 25 30 0 20 40 60 80 100 120 CPU Frequency (MHz) 105°C 85°C 70°C 55°C 30°C 0°C -45°C IDD(RUN) (mA) DocID15818 Rev 11 79/178 STM32F20xxx Electrical characteristics 177 Figure 25. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON Figure 26. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF MS19016V1 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 0 20 40 60 80 100 120 105 85 30°C -45°C IDD(RUN) (mA) CPU frequnecy (MHz) MS19017V1 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 CPU Frequency (MHz) 105 85 30°C -45°C I DD(RUN) (mA) Electrical characteristics STM32F20xxx 80/178 DocID15818 Rev 11 Table 22. Typical and maximum current consumption in Sleep mode Symbol Parameter Conditions fHCLK Typ Max(1) T Unit A = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Sleep mode External clock(2), all peripherals enabled(3) 120 MHz 38 51 61 mA 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 25 35 25 MHz 8 21 31 16 MHz 6 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 2 MHz 1.9 14.9 24.7 External clock(2), all peripherals disabled 120 MHz 8 21 31 90 MHz 7 20 30 60 MHz 5 18 28 30 MHz 3.5 16.0 26.0 25 MHz 2.5 16.0 25.0 16 MHz 2.1 15.1 25.0 8 MHz 1.7 15.0 25.0 4 MHz 1.5 14.6 24.6 2 MHz 1.4 14.2 24.3 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). DocID15818 Rev 11 81/178 STM32F20xxx Electrical characteristics 177 Figure 27. Typical current consumption vs temperature in Sleep mode, peripherals ON Figure 28. Typical current consumption vs temperature in Sleep mode, peripherals OFF MS19018V1 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 105°C 85°C 70°C 55°C 30°C 0°C -45°C IDD(SLEEP) (mA) CPU Frequency (MHz) MS19019V1 0 2 4 6 8 10 12 14 16 0 20 40 60 80 100 120 105°C 85°C 70°C 55°C 30°C 0°C -45°C CPU Frequency (MHz) IDD(SLEEP) (mA) Electrical characteristics STM32F20xxx 82/178 DocID15818 Rev 11 Figure 29. Typical current consumption vs temperature in Stop mode 1. All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes Table 23. Typical and maximum current consumptions in Stop mode(1) Symbol Parameter Conditions Typ Max T Unit A = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_STOP Supply current in Stop mode with main regulator in Run mode Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.55 1.2 11.00 20.00 mA Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.50 1.2 11.00 20.00 Supply current in Stop mode with main regulator in Low Power mode Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.35 1.1 8.00 15.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.30 1.1 8.00 15.00 1. All typical and maximum values will be further reduced by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes. MS19020V1 0.01 0.1 1 10 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Idd_stop_mr_flhstop Idd_stop_mr_flhdeep Idd_stop_lp_flhstop Idd_stop_lp_flhdeep IDD(STOP) (mA) DocID15818 Rev 11 83/178 STM32F20xxx Electrical characteristics 177 Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C TA = 85 °C TA = 105 °C Unit VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V VDD = 3.6 V IDD_STBY Supply current in Standby mode Backup SRAM ON, low-speed oscillator and RTC ON 3.0 3.4 4.0 15.1 25.8 μA Backup SRAM OFF, lowspeed oscillator and RTC ON 2.4 2.7 3.3 12.4 20.5 Backup SRAM ON, RTC OFF 2.4 2.6 3.0 12.5 24.8 Backup SRAM OFF, RTC OFF 1.7 1.9 2.2 9.8 19.2 1. Based on characterization, not tested in production. Table 25. Typical and maximum current consumptions in VBAT mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C TA = 85 °C Unit TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V VDD = 3.6 V IDD_VBAT Backup domain supply current Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 12 19 μA Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 8 10 Backup SRAM ON, RTC OFF 0.79 0.81 0.86 9 16 Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 5 7 1. Based on characterization, not tested in production. Electrical characteristics STM32F20xxx 84/178 DocID15818 Rev 11 On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 26. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog inputs by firmware. • All peripherals are disabled unless otherwise mentioned • The given value is calculated by measuring the current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) • The code is running from Flash memory and the Flash memory access time is equal to 3 wait states at 120 MHz • Prefetch and Cache ON • When the peripherals are enabled, HCLK = 120MHz, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2 • The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. Table 26. Peripheral current consumption Peripheral(1) Typical consumption at 25 °C Unit AHB1 GPIO A 0.45 mA GPIO B 0.43 GPIO C 0.46 GPIO D 0.44 GPIO E 0.44 GPIO F 0.42 GPIO G 0.44 GPIO H 0.42 GPIO I 0.43 OTG_HS + ULPI 3.64 CRC 1.17 BKPSRAM 0.21 DMA1 2.76 DMA2 2.85 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 2.99 AHB2 OTG_FS 3.16 DCMI 0.60 AHB3 FSMC 1.74 DocID15818 Rev 11 85/178 STM32F20xxx Electrical characteristics 177 APB1 TIM2 0.61 mA TIM3 0.49 TIM4 0.54 TIM5 0.62 TIM6 0.20 TIM7 0.20 TIM12 0.36 TIM13 0.28 TIM14 0.25 USART2 0.25 USART3 0.25 UART4 0.25 UART5 0.26 I2C1 0.25 I2C2 0.25 I2C3 0.25 SPI2 0.20/0.10 SPI3 0.18/0.09 CAN1 0.31 CAN2 0.30 DAC channel 1(2) 1.11 DAC channel 1(3) 1.11 PWR 0.15 WWDG 0.15 Table 26. Peripheral current consumption (continued) Peripheral(1) Typical consumption at 25 °C Unit Electrical characteristics STM32F20xxx 86/178 DocID15818 Rev 11 6.3.7 Wakeup time from low-power mode The wakeup times given in Table 27 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. APB2 SDIO 0.69 mA TIM1 1.06 TIM8 1.03 TIM9 0.58 TIM10 0.37 TIM11 0.39 ADC1(4) 2.13 ADC2(4) 2.04 ADC3(4) 2.12 SPI1 1.20 USART1 0.38 USART6 0.37 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR register. 4. fADC = fPCLK2/2, ADON bit set in ADC_CR2 register. Table 26. Peripheral current consumption (continued) Peripheral(1) Typical consumption at 25 °C Unit Table 27. Low-power mode wakeup timings Symbol Parameter Min(1) Typ(1) Max(1) Unit tWUSLEEP (2) Wakeup from Sleep mode - 1 - μs tWUSTOP (2) Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 μs Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - tWUSTDBY (2)(3) Wakeup from Standby mode 260 375 480 μs 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. DocID15818 Rev 11 87/178 STM32F20xxx Electrical characteristics 177 6.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 28 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Low-speed external user clock generated from an external source The characteristics given in Table 29 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 28. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext External user clock source frequency(1) 1 - 26 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD V VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 1. Guaranteed by design, not tested in production. 5 - - ns tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 20 Cin(HSE) OSC_IN input capacitance(1) - 5 - pF DuCy(HSE) Duty cycle 45 - 55 % IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA Table 29. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User External clock source frequency(1) 1. Guaranteed by design, not tested in production. - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD V VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - ns tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) OSC32_IN input capacitance(1) - 5 - pF DuCy(LSE) Duty cycle 30 - 70 % IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA Electrical characteristics STM32F20xxx 88/178 DocID15818 Rev 11 Figure 30. High-speed external clock source AC timing diagram Figure 31. Low-speed external clock source AC timing diagram High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 30. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai17528 OSC_IN External STM32F clock source VHSEH tf(HSE) tW(HSE) IL 90% 10% THSE tr(HSE) tW(HSE) t fHSE_ext VHSEL ai17529 External OSC32_IN STM32F clock source VLSEH tf(LSE) tW(LSE) IL 90% 10% TLSE tr(LSE) tW(LSE) t fLSE_ext VLSEL DocID15818 Rev 11 89/178 STM32F20xxx Electrical characteristics 177 For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 32. Typical application with an 8 MHz crystal 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 31. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 30. HSE 4-26 MHz oscillator characteristics(1) (2) 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - kΩ IDD HSE current consumption VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - μA VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - gm Oscillator transconductance Startup 5 - - mA/V tSU(HSE (3) 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Startup time VDD is stabilized - 2 - ms ai17530 OSC_OUT OSC_IN fHSE CL1 RF STM32F 8 MHz resonator Resonator with integrated capacitors Bias controlled gain CL2 REXT(1) Electrical characteristics STM32F20xxx 90/178 DocID15818 Rev 11 Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 33. Typical application with a 32.768 kHz crystal 6.3.9 Internal clock source characteristics The parameters given in Table 32 and Table 33 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) 1. Guaranteed by design, not tested in production. Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 μA gm Oscillator Transconductance 2.8 - - μA/V tSU(LSE) (2) 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time VDD is stabilized - 2 - s ai17531 OSC32_OUT OSC32_IN fLSE CL1 RF STM32F 32.768 kHz resonator Resonator with integrated capacitors Bias controlled gain CL2 Table 32. HSI oscillator characteristics (1) 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency - 16 - MHz ACCHSI Accuracy of the HSI oscillator User-trimmed with the RCC_CR register(2) - - 1 % Factorycalibrated TA = –40 to 105 °C –8 - 4.5 % TA = –10 to 85 °C –4 - 4 % TA = 25 °C –1 - 1 % tsu(HSI) (3) HSI oscillator startup time - 2.2 4 μs IDD(HSI) HSI oscillator power consumption - 60 80 μA DocID15818 Rev 11 91/178 STM32F20xxx Electrical characteristics 177 Figure 34. ACCHSI versus temperature Low-speed internal (LSI) RC oscillator 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. Table 33. LSI oscillator characteristics (1) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. Symbol Parameter Min Typ Max Unit fLSI (2) 2. Based on characterization, not tested in production. Frequency 17 32 47 kHz tsu(LSI) (3) 3. Guaranteed by design, not tested in production. LSI oscillator startup time - 15 40 μs IDD(LSI) (3) LSI oscillator power consumption - 0.4 0.6 μA MS19012V2 -8 -6 -4 -2 0 2 4 6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Normalized deviation (%) Temperature (°C) max avg min Electrical characteristics STM32F20xxx 92/178 DocID15818 Rev 11 Figure 35. ACCLSI versus temperature 6.3.10 PLL characteristics The parameters given in Table 34 and Table 35 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. MS19013V1 -40 -30 -20 -10 0 10 20 30 40 50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Normalized deviati on (%) Temperature (°C) max avg min Table 34. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) 0.95 (2) 1 2.10(2) MHz fPLL_OUT PLL multiplier output clock 24 - 120 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 MHz fVCO_OUT PLL VCO output 192 - 432 MHz tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 DocID15818 Rev 11 93/178 STM32F20xxx Electrical characteristics 177 Jitter(3) Cycle-to-cycle jitter System clock 120 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL) (4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL) (4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 34. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 35. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 1 2.10(2) MHz fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz fVCO_OUT PLLI2S VCO output 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Electrical characteristics STM32F20xxx 94/178 DocID15818 Rev 11 Jitter(3) Master I2S clock jitter Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N=432, R=5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S) (4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S) (4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. Table 35. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit DocID15818 Rev 11 95/178 STM32F20xxx Electrical characteristics 177 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 42: EMI characteristics). It is available only on the main PLL. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: As a result: Table 36. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - 215−1 - 1. Guaranteed by design, not tested in production. MODEPER = round[fPLL_IN ⁄ (4 × fMod)] MODEPER round 106 4 10 3 = [ ⁄ ( × )] = 250 INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)] INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)% mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN) mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.0002%(peak) Electrical characteristics STM32F20xxx 96/178 DocID15818 Rev 11 Figure 36 and Figure 37 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 36. PLL output clock waveforms in center spread mode Figure 37. PLL output clock waveforms in down spread mode 6.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Frequency (PLL_OUT) Time F0 tmode 2xtmode md ai17291 md Frequency (PLL_OUT) Time F0 tmode 2xtmode 2xmd ai17292 DocID15818 Rev 11 97/178 STM32F20xxx Electrical characteristics 177 Table 37. Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit IDD Supply current Write / Erase 8-bit mode VDD = 1.8 V - 5 - Write / Erase 16-bit mode mA VDD = 2.1 V - 8 - Write / Erase 32-bit mode VDD = 3.3 V - 12 - Table 38. Flash memory programming Symbol Parameter Conditions Min(1) Typ Max(1) 1. Based on characterization, not tested in production. Unit tprog Word programming time Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) 2. The maximum programming time is measured after 100K erase operations. μs tERASE16KB Sector (16 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism ms (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 tERASE64KB Sector (64 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism ms (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 tERASE128KB Sector (128 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism s (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 tME Mass erase time Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism s (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 Vprog Programming voltage 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V Electrical characteristics STM32F20xxx 98/178 DocID15818 Rev 11 Table 40. Flash memory endurance and data retention 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. Table 39. Flash memory programming with VPP Symbol Parameter Conditions Min(1) Typ Max(1) 1. Guaranteed by design, not tested in production. Unit tprog Double word programming TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V - 16 100(2) 2. The maximum programming time is measured after 100K erase operations. μs tERASE16KB Sector (16 KB) erase time - 230 - tERASE64KB Sector (64 KB) erase time - 490 - ms tERASE128KB Sector (128 KB) erase time - 875 - tME Mass erase time - 6.9 - s Vprog Programming voltage 2.7 - 3.6 V VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA tVPP (3) 3. VPP should only be connected during programming/erasing. Cumulative time during which VPP is applied - - 1 hour Symbol Parameter Conditions Value Unit Min(1) 1. Based on characterization, not tested in production. NEND Endurance TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 kcycles tRET Data retention 1 kcycle(2) at TA = 85 °C 2. Cycling performed over the whole temperature range. 30 1 kcycle(2) at TA = 105 °C 10 Years 10 kcycles(2) at TA = 55 °C 20 DocID15818 Rev 11 99/178 STM32F20xxx Electrical characteristics 177 The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 41. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 120 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 120 MHz, conforms to IEC 61000-4-2 4A Electrical characteristics STM32F20xxx 100/178 DocID15818 Rev 11 Electromagnetic Interference (EMI)g The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. 6.3.14 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 42. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 25/120 MHz SEMI Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled, peripheral clock disabled 0.1 to 30 MHz 30 to 130 MHz 25 dBμV 130 MHz to 1GHz SAE EMI Level 4 - VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled, PLL spread spectrum enabled, peripheral clock disabled 0.1 to 30 MHz 28 30 to 130 MHz 26 dBμV 130 MHz to 1GHz 22 SAE EMI level 4 - Table 43. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to JESD22-A114 2 2000(2) V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-C101 II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. DocID15818 Rev 11 101/178 STM32F20xxx Electrical characteristics 177 Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. 6.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 45. Table 44. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A Table 45. I/O current injection susceptibility Symbol Description Functional susceptibility Negative Unit injection Positive injection IINJ Injected current on all FT pins –5 +0 mA Injected current on any other pin –5 +5 Electrical characteristics STM32F20xxx 102/178 DocID15818 Rev 11 6.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 14: General operating conditions. All I/Os are CMOS and TTL compliant except for BOOT0 and BOOT1. Table 46. I/O static characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VIL Low level input voltage TTa, FT and NRST I/Os 1.6 V ≤ VDD ≤ 3.6 V - - 0.35VDD–0.04(2) V BOOT0 - - TBD(2) I/O input low level voltage except BOOT0 - - 0.3VDD (3) VIH High level input voltage TTa, FT and NRST I/Os(4) 0.45VDD+0.3(2) - - BOOT0 TBD(2) - - I/O input low level voltage except BOOT0 0.7VDD (3) - - Vhys Schmitt trigger hysteresis TTa, FT and NRST I/Os 10% VDDIO (2)(5) - - mV BOOT0 TBD(2) - - Ilkg I/O input leakage current (6) VSS ≤ VIN ≤ VDD - - ±1 μA I/O FT input leakage current (5) VIN = 5 V - - 3 RPU Weak pull-up equivalent resistor(7) All pins except for PA10 and PB12 VIN = VSS 30 40 50 kΩ PA10 and PB12 8 11 15 RPD Weak pulldown equivalent resistor All pins except for PA10 and PB12 VIN = VDD 30 40 50 PA10 and PB12 8 11 15 CIO (2) I/O pin capacitance 5 pF 1. TBD stands for “to be defined”. 2. Data based on design simulation only. Not tested in production. 3. Tested in production. 4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. 5. With a minimum of 200 mV. 6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). DocID15818 Rev 11 103/178 STM32F20xxx Electrical characteristics 177 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics(1) 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Symbol Parameter Conditions Min Max Unit VOL (2) 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS ports IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL ports IIO =+ 8mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 - VOL (2)(4) 4. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 2.7 V < VDD < 3.6 V - 1.3 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–1.3 - VOL (2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 2 V < VDD < 2.7 V - 0.4 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - Electrical characteristics STM32F20xxx 104/178 DocID15818 Rev 11 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 38 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 48. I/O AC characteristics(1) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit 00 fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD > 2.70 V - - 4 MHz CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - 8 CL = 10 pF, VDD > 1.8 V - - 4 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 50 pF, VDD = 1.8 V to 3.6 V - - 100 ns 01 fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD > 2.70 V - - 25 MHz CL = 50 pF, VDD > 1.8 V - - 12.5 CL = 10 pF, VDD > 2.70 V - - 50(3) CL = 10 pF, VDD > 1.8 V - - 20 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 50 pF, VDD >2.7 V - - 10 ns CL = 50 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 6 CL = 10 pF, VDD > 1.8 V - - 10 10 fmax(IO)out Maximum frequency(2) CL = 40 pF, VDD > 2.70 V - - 25 MHz CL = 40 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 100(3) CL = 10 pF, VDD > 1.8 V - - 50(3) tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 40 pF, VDD > 2.70 V - - 6 ns CL = 40 pF, VDD > 1.8 V - - 10 CL = 10 pF, VDD > 2.70 V - 4 CL = 10 pF, VDD > 1.8 V - 6 DocID15818 Rev 11 105/178 STM32F20xxx Electrical characteristics 177 Figure 38. I/O AC characteristics definition 11 fmax(IO)out Maximum frequency(2) CL = 30 pF, VDD > 2.70 V - - 100(3) MHz CL = 30 pF, VDD > 1.8 V - - 50(3) CL = 10 pF, VDD > 2.70 V - - 180(3) CL = 10 pF, VDD > 1.8 V - - 100(3) tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 30 pF, VDD > 2.70 V - - 4 ns CL = 30 pF, VDD > 1.8 V - - 6 CL = 10 pF, VDD > 2.70 V - - 2.5 CL = 10 pF, VDD > 1.8 V - - 4 - tEXTIpw Pulse width of external signals detected by the EXTI controller 10 - - ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 2. The maximum frequency is defined in Figure 38. 3. For maximum frequencies above 50 MHz, the compensation cell should be used. Table 48. I/O AC characteristics(1) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit ai14131c 10% 90% 50% tr(IO)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T tf(IO)out Electrical characteristics STM32F20xxx 106/178 DocID15818 Rev 11 6.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49). Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Figure 39. Recommended NRST pin protection 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset is not taken into account by the device. Table 49. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) (1) NRST input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8V VIH(NRST) (1) NRST input high level voltage 2 - - VIL(NRST) (1) NRST input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - - 0.3VDD V VIH(NRST) (1) NRST input high level voltage 0.7VDD - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ VF(NRST) (1) NRST Input filtered pulse - - 100 ns VNF(NRST) (1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - μs 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). ai14132c STM32Fxxx NRST(2) RPU VDD Filter Internal Reset 0.1 μF External reset circuit(1) DocID15818 Rev 11 107/178 STM32F20xxx Electrical characteristics 177 6.3.18 TIM timer characteristics The parameters given in Table 50 and Table 51 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. Characteristics of TIMx connected to the APB1 domain(1) 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB1 prescaler distinct from 1, fTIMxCLK = 60 MHz 1 - tTIMxCLK 16.7 - ns AHB/APB1 prescaler = 1, fTIMxCLK = 30 MHz 1 - tTIMxCLK 33.3 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 60 MHz APB1= 30 MHz 0 fTIMxCLK/2 MHz 0 30 MHz ResTIM Timer resolution - 16/32 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 0.0167 1092 μs 32-bit counter clock period when internal clock is selected 1 - tTIMxCLK 0.0167 71582788 μs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 71.6 s Electrical characteristics STM32F20xxx 108/178 DocID15818 Rev 11 6.3.19 Communications interfaces I2C interface characteristics STM32F205xx and STM32F207xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 52. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 51. Characteristics of TIMx connected to the APB2 domain(1) 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 120 MHz 1 - tTIMxCLK 8.3 - ns AHB/APB2 prescaler = 1, fTIMxCLK = 60 MHz 1 - tTIMxCLK 16.7 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 120 MHz APB2 = 60 MHz 0 fTIMxCLK/2 MHz 0 60 MHz ResTIM Timer resolution - 16 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 0.0083 546 μs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 35.79 s DocID15818 Rev 11 109/178 STM32F20xxx Electrical characteristics 177 Table 52. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) 1. Guaranteed by design, not tested in production. Fast mode I2C(1)(2) 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - μs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time - 3450(3) - 900(3) 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal. tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - μs tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of the spikes that are suppressed by the analog filter 0 50(4) 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). 0 50 ns Electrical characteristics STM32F20xxx 110/178 DocID15818 Rev 11 Figure 40. I2C bus AC waveforms and measurement circuit 1. RS= series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 53. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V)(1)(2) 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. fSCL (kHz) I2C_CCR value RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE ai14979c S TAR T SD A RP I²C bus VDD_I2C STM32Fxx SDA SCL tf(SDA) tr(SDA) SCL th(STA) tw(SCLH) tw(SCLL) tsu(SDA) tr(SCL) tf(SCL) th(SDA) S TAR T REPEATED t S TAR T su(STA) tsu(STO) S TOP tw(STO:STA) VDD_I2C RP RS RS DocID15818 Rev 11 111/178 STM32F20xxx Electrical characteristics 177 I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 54 for SPI or in Table 55 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 54. SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency SPI1 master/slave mode - 30 MHz SPI2/SPI3 master/slave mode - 15 tr(SCL) tf(SCL) SPI clock rise and fall time Capacitive load: C = 30 pF, fPCLK = 30 MHz - 8 ns DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 % tsu(NSS) (1) 1. Based on characterization, not tested in production. NSS setup time Slave mode 4tPCLK - ns th(NSS) (1) NSS hold time Slave mode 2tPCLK - tw(SCLH) (1) tw(SCLL) (1) SCK high and low time Master mode, fPCLK = 30 MHz, presc = 2 tPCLK-3 tPCLK+3 tsu(MI) (1) tsu(SI) (1) Data input setup time Master mode 5 - Slave mode 5 - th(MI) (1) th(SI) (1) Data input hold time Master mode 5 - Slave mode 4 - ta(SO) (1)(2) 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Data output access time Slave mode, fPCLK = 30 MHz 0 3tPCLK tdis(SO) (1)(3) 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Data output disable time Slave mode 2 10 tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO) (1) Data output valid time Master mode (after enable edge) - 5 th(SO) (1) Data output hold time Slave mode (after enable edge) 15 - th(MO) (1) Master mode (after enable edge) 2 - Electrical characteristics STM32F20xxx 112/178 DocID15818 Rev 11 Figure 41. SPI timing diagram - slave mode and CPHA = 0 Figure 42. SPI timing diagram - slave mode and CPHA = 1 ai14134c SCK Input CPHA=0 MOSI INPUT MISO OUT PUT CPHA=0 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN NSS input tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) ai14135 SCK Input CPHA=1 MOSI INPUT MISO OUT PUT CPHA=1 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) NSS input DocID15818 Rev 11 113/178 STM32F20xxx Electrical characteristics 177 Figure 43. SPI timing diagram - master mode ai14136V2 SCK Output CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 MSBIN MSB OUT BIT6 IN LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High SCK Output CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) Electrical characteristics STM32F20xxx 114/178 DocID15818 Rev 11 Table 55. I2S characteristics Symbol Parameter Conditions Min Max Unit fCK 1/tc(CK) I2S clock frequency Master, 16-bit data, audio frequency = 48 kHz, main clock disabled 1.23 1.24 MHz Slave 0 64FS (1) tr(CK) tf(CK) I2S clock rise and fall time capacitive load CL = 50 pF - (2) ns tv(WS) (3) WS valid time Master 0.3 - th(WS) (3) WS hold time Master 0 - tsu(WS) (3) WS setup time Slave 3 - th(WS) (3) WS hold time Slave 0 - tw(CKH) (3) tw(CKL) (3) CK high and low time Master fPCLK= 30 MHz 396 - tsu(SD_MR) (3) tsu(SD_SR) (3) Data input setup time Master receiver Slave receiver 45 0 - th(SD_MR) (3)(4) th(SD_SR) (3)(4) Data input hold time Master receiver: fPCLK= 30 MHz, Slave receiver: fPCLK= 30 MHz 13 0 - tv(SD_ST) (3)(4) Data output valid time Slave transmitter (after enable edge) - 30 th(SD_ST) (3) Data output hold time Slave transmitter (after enable edge) 10 - tv(SD_MT) (3)(4) Data output valid time Master transmitter (after enable edge) - 6 th(SD_MT) (3) Data output hold time Master transmitter (after enable edge) 0 - 1. FS is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. fCK values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of (I2SDIV+ODD)/(2*I2SDIV+ODD) and FS maximum values for each mode/condition. 2. Refer to Table 48: I/O AC characteristics. 3. Based on design simulation and/or characterization results, not tested in production. 4. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. DocID15818 Rev 11 115/178 STM32F20xxx Electrical characteristics 177 Figure 44. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 45. I2S master timing diagram (Philips protocol)(1) 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. CK Input CPOL = 0 CPOL = 1 tc(CK) WS input SDtransmit SDreceive tw(CKH) tw(CKL) tsu(WS) tv(SD_ST) th(SD_ST) th(WS) tsu(SD_SR) th(SD_SR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14881b LSB receive(2) LSB transmit(2) CK output CPOL = 0 CPOL = 1 tc(CK) WS output SDreceive SDtransmit tw(CKH) tw(CKL) tsu(SD_MR) tv(SD_MT) th(SD_MT) th(WS) th(SD_MR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14884b tf(CK) tr(CK) tv(WS) LSB receive(2) LSB transmit(2) Electrical characteristics STM32F20xxx 116/178 DocID15818 Rev 11 USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 56. USB OTG FS startup time Symbol Parameter Max Unit tSTARTUP (1) 1. Guaranteed by design, not tested in production. USB OTG FS transceiver startup time 1 μs Table 57. USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min.(1) 1. All the voltages are measured from the local ground potential. Typ. Max.(1) Unit Input levels VDD USB OTG FS operating voltage 3.0(2) 2. The STM32F205xx and STM32F207xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. - 3.6 V VDI (3) 3. Guaranteed by design, not tested in production. Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM V (3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE (3) Single ended receiver threshold 1.3 - 2.0 Output levels VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) 4. RL is the load connected on the USB OTG FS drivers - - 0.3 V VOH Static output level high RL of 15 kΩ to VSS (4) 2.8 - 3.6 RPD PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) VIN = VDD 17 21 24 kΩ PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) 0.65 1.1 2.0 RPU PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 DocID15818 Rev 11 117/178 STM32F20xxx Electrical characteristics 177 Figure 46. USB OTG FS timings: definition of data signal rise and fall time USB HS characteristics Table 59 shows the USB HS operating voltage. Table 58. USB OTG FS electrical characteristics(1) 1. Guaranteed by design, not tested in production. Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). CL = 50 pF 4 20 ns tf Fall time(2) CL = 50 pF 4 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V Table 59. USB HS DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD USB OTG HS operating voltage 2.7 3.6 V Table 60. Clock timing parameters Parameter(1) 1. Guaranteed by design, not tested in production. Symbol Min Nominal Max Unit Frequency (first transition) 8-bit ±10% FSTART_8BIT 54 60 66 MHz Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 % Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 % Time to reach the steady state frequency and duty cycle after the first transition TSTEADY - - 1.4 ms Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 ms Host TSTART_HOST - - - PHY preparation time after the first transition of the input clock TPREP - - - μs ai14137 tf Differen tial Data L ines VSS VCRS tr Crossover points Electrical characteristics STM32F20xxx 118/178 DocID15818 Rev 11 Figure 47. ULPI timing diagram Ethernet characteristics Table 62 shows the Ethernet operating voltage. Table 63 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 48 shows the corresponding timing diagram. Table 61. ULPI timing Symbol Parameter Value(1) 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Unit Min. Max. tSC Control in (ULPI_DIR) setup time - 2.0 ns Control in (ULPI_NXT) setup time - 1.5 tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0 - tSD Data in setup time - 2.0 tHD Data in hold time 0 - tDC Control out (ULPI_STP) setup time and hold time - 9.2 tDD Data out available from clock rising edge - 10.7 Table 62. Ethernet DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD Ethernet operating voltage 2.7 3.6 V Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tSD tHD tSC tHC ai17361c tDC DocID15818 Rev 11 119/178 STM32F20xxx Electrical characteristics 177 Figure 48. Ethernet SMI timing diagram Table 64 gives the list of Ethernet MAC signals for the RMII and Figure 49 shows the corresponding timing diagram. Figure 49. Ethernet RMII timing diagram Table 63. Dynamics characteristics: Ethernet MAC signals for SMI Symbol Rating Min Typ Max Unit tMDC MDC cycle time (2.38 MHz) 411 420 425 ns td(MDIO) MDIO write data valid time 6 10 13 ns tsu(MDIO) Read data setup time 12 - - ns th(MDIO) Read data hold time 0 - - ns Table 64. Dynamics characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 1 - - ns tih(RXD) Receive data hold time 1.5 - - tsu(CRS) Carrier sense set-up time 0 - - tih(CRS) Carrier sense hold time 2 - - td(TXEN) Transmit enable valid delay time 9 11 13 td(TXD) Transmit data valid delay time 9 11.5 14 ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO) ai15666d RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) ai15667 Electrical characteristics STM32F20xxx 120/178 DocID15818 Rev 11 Table 65 gives the list of Ethernet MAC signals for MII and Figure 49 shows the corresponding timing diagram. Figure 50. Ethernet MII timing diagram CAN (controller area network) interface Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). Table 65. Dynamics characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 7.5 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(DV) Data valid setup time 4 - - ns tih(DV) Data valid hold time 0 - - ns tsu(ER) Error setup time 3.5 - - ns tih(ER) Error hold time 0 - - ns td(TXEN) Transmit enable valid delay time - 11 14 ns td(TXD) Transmit data valid delay time - 11 14 ns MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER td(TXEN) td(TXD) tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) ai15668 MII_TX_CLK MII_TX_EN MII_TXD[3:0] DocID15818 Rev 11 121/178 STM32F20xxx Electrical characteristics 177 6.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 66. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1.8(1) - 3.6 V VREF+ Positive reference voltage 1.8(1)(2) - VDDA V fADC ADC clock frequency VDDA = 1.8(1) to 2.4 V 0.6 - 15 MHz VDDA = 2.4 to 3.6 V 0.6 - 30 MHz fTRIG (3) External trigger frequency fADC = 30 MHz with 12-bit resolution - - 1764 kHz - - 17 1/fADC VAIN Conversion voltage range(4) 0 (VSSA or VREFtied to ground) - VREF+ V RAIN (3) External input impedance See Equation 1 for details - - 50 kΩ RADC (3)(5) Sampling switch resistance 1.5 - 6 kΩ CADC (3) Internal sample and hold capacitor - 4 - pF tlat (3) Injection trigger conversion latency fADC = 30 MHz - - 0.100 μs - - 3(6) 1/fADC tlatr (3) Regular trigger conversion latency fADC = 30 MHz - - 0.067 μs - - 2(6) 1/fADC tS (3) Sampling time fADC = 30 MHz 0.100 - 16 μs 3 - 480 1/fADC tSTAB (3) Power-up time - 2 3 μs tCONV (3) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.5 - 16.40 μs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 μs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 μs fADC = 30 MHz 6-bit resolution 0.3 - 16.20 μs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC Electrical characteristics STM32F20xxx 122/178 DocID15818 Rev 11 Equation 1: RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion fS (3) Sampling rate (fADC = 30 MHz) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+ (3) ADC VREF DC current consumption in conversion mode - 300 500 μA IVDDA (3) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. Based on characterization, not tested in production. 4. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 5. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 6. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 66. Table 66. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 67. ADC accuracy (1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Based on characterization, not tested in production. Unit ET Total unadjusted error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V 3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 RAIN (k – 0.5) fADC CADC 2N + 2 × × ln( ) = -------------------------------------------------------------- – RADC DocID15818 Rev 11 123/178 STM32F20xxx Electrical characteristics 177 being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.16 does not affect the ADC accuracy. Figure 51. ADC accuracy characteristics 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 52. Typical connection diagram using the ADC 1. Refer to Table 66 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the ai14395c EO EG 1L SBIDEAL 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VSSA VDDA VREF+ 4096 (or depending on package)] VDDA 4096 [1LSB IDEAL = ai17534 VDD STM32F AINx IL±1 μA 0.6 V VT RAIN (1) Cparasitic VAIN 0.6 V VT RADC (1) CADC(1) 12-bit converter Sample and hold ADC converter Electrical characteristics STM32F20xxx 124/178 DocID15818 Rev 11 pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DocID15818 Rev 11 125/178 STM32F20xxx Electrical characteristics 177 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 53 or Figure 54, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 54. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. VREF+ STM32F VDDA VSSA/V REF- 1 μF // 10 nF 1 μF // 10 nF ai17535 (See note 1) (See note 1) VREF+/VDDA STM32F 1 μF // 10 nF VREF–/VSSA ai17536 (See note 1) (See note 1) Electrical characteristics STM32F20xxx 126/178 DocID15818 Rev 11 6.3.21 DAC electrical characteristics Table 68. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VREF+ ≤ VDDA VSSA Ground 0 - 0 V RLOAD (2) Resistive load with buffer ON 5 - - kΩ RO (2) Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD (2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON 0.2 - - V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V DAC_OUT min(2) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV It gives the maximum output DAC_OUT excursion of the DAC. max(2) Higher DAC_OUT voltage with buffer OFF - - VREF+ – 1LSB V IVREF+ (4) DAC DC VREF current consumption in quiescent mode (Standby mode) - 170 240 μA With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs IDDA (4) DAC DC VDDA current consumption in quiescent mode(3) - 280 380 μA With no load, middle code (0x800) on the inputs - 475 625 μA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(4) Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSBGiven for the DAC in 10-bit configuration. - - ±2 LSBGiven for the DAC in 12-bit configuration. DocID15818 Rev 11 127/178 STM32F20xxx Electrical characteristics 177 INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - ±1 LSBGiven for the DAC in 10-bit configuration. - - ±4 LSBGiven for the DAC in 12-bit configuration. Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±10 mV - - ±3 LSBGiven for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSBGiven for the DAC in 12-bit at VREF+ = 3.6 V Gain error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration tSETTLING (4) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±4LSB - 3 6 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP (4) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Table 68. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Electrical characteristics STM32F20xxx 128/178 DocID15818 Rev 11 Figure 55. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.22 Temperature sensor characteristics 6.3.23 VBAT monitoring characteristics RLOAD CLOAD Buffered/Non-buffered DAC DAC_OUTx Buffer(1) 12-bit digital to analog converter ai17157V2 Table 69. TS characteristics Symbol Parameter Min Typ Max Unit TL (1) 1. Based on characterization, not tested in production. VSENSE linearity with temperature - ±1 ±2 °C Avg_Slope(1) Average slope - 2.5 mV/°C V25 (1) Voltage at 25 °C - 0.76 V tSTART (2) 2. Guaranteed by design, not tested in production. Startup time - 6 10 μs TS_temp (3)(2) 3. Shortest sampling time can be determined in the application by multiple iterations. ADC sampling time when reading the temperature 1°C accuracy 10 - - μs Table 70. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 2 - Er(1) 1. Guaranteed by design, not tested in production. Error on Q –1 - +1 % TS_vbat (2)(2) 2. Shortest sampling time can be determined in the application by multiple iterations. ADC sampling time when reading the VBAT 1mV accuracy 5 - - μs DocID15818 Rev 11 129/178 STM32F20xxx Electrical characteristics 177 6.3.24 Embedded reference voltage The parameters given in Table 71 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. 6.3.25 FSMC characteristics Asynchronous waveforms and timings Figure 56 through Figure 59 represent asynchronous waveforms and Table 72 through Table 75 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 1 • DataSetupTime = 1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Table 71. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V TS_vrefint (1) 1. Shortest sampling time can be determined in the application by multiple iterations. ADC sampling time when reading the internal reference voltage 10 - - μs VRERINT_s (2) 2. Guaranteed by design, not tested in production. Internal reference voltage spread over the temperature range VDD = 3 V - 3 5 mV TCoeff (2) Temperature coefficient - 30 50 ppm/°C tSTART (2) Startup time - 6 10 μs Electrical characteristics STM32F20xxx 130/178 DocID15818 Rev 11 Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 2THCLK– 0.5 2THCLK+0.5 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 2.5 ns tw(NOE) FSMC_NOE low time 2THCLK- 1 2THCLK+ 0.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 4 ns th(A_NOE) Address hold time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 0.5 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+ 2.5 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2.5 ns tw(NADV) FSMC_NADV low time - THCLK– 0.5 ns Data FSMC_NE FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) t h(Data_NE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) FSMC_NWE tsu(Data_NE) tw(NE) ai14991c tv(NOE_NE) t w(NOE) t h(NE_NOE) th(Data_NOE) t h(A_NOE) t h(BL_NOE) tsu(Data_NOE) FSMC_NADV(1) t v(NADV_NE) tw(NADV) DocID15818 Rev 11 131/178 STM32F20xxx Electrical characteristics 177 Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK 3THCLK+ 4 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK– 0.5 THCLK+ 0.5 ns tw(NWE) FSMC_NWE low time THCLK– 0.5 THCLK+ 3 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns th(A_NWE) Address hold time after FSMC_NWE high THCLK- 3 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK– 1 - ns tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+ 5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK+0.5 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK+ 1.5 ns NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) tv(Data_NE) tw(NE) ai14990 FSMC_NADV(1) t v(NADV_NE) tw(NADV) Electrical characteristics STM32F20xxx 132/178 DocID15818 Rev 11 Figure 58. Asynchronous multiplexed PSRAM/NOR read waveforms 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK-1 3THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2THCLK 2THCLK+0.5 ns tw(NOE) FSMC_NOE low time THCLK-1 THCLK+1 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 2 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2.5 ns tw(NADV) FSMC_NADV low time THCLK– 1.5 THCLK ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 2 - ns NBL Data FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NE) FSMC_A[25:16] Address tv(A_NE) FSMC_NWE t v(A_NE) ai14892b Address FSMC_NADV t v(NADV_NE) tw(NADV) tsu(Data_NE) th(AD_NADV) FSMC_NE FSMC_NOE tw(NE) t w(NOE) tv(NOE_NE) t h(NE_NOE) th(A_NOE) th(BL_NOE) tsu(Data_NOE) th(Data_NOE) DocID15818 Rev 11 133/178 STM32F20xxx Electrical characteristics 177 tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+ 3 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) Symbol Parameter Min Max Unit Electrical characteristics STM32F20xxx 134/178 DocID15818 Rev 11 Figure 59. Asynchronous multiplexed PSRAM/NOR write waveforms Table 75. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 4THCLK-1 4THCLK+1 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK- 1 THCLK ns tw(NWE) FSMC_NWE low tim e 2THCLK 2THCLK+1 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK- 1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+ 2 ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK– 0.5 - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK- 1 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK+2 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK– 0.5 - ns NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:16] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) t v(A_NE) tw(NE) ai14891B Address FSMC_NADV t v(NADV_NE) tw(NADV) t v(Data_NADV) th(AD_NADV) DocID15818 Rev 11 135/178 STM32F20xxx Electrical characteristics 177 Synchronous waveforms and timings Figure 60 through Figure 63 represent synchronous waveforms and Table 77 through Table 79 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period. Figure 60. Synchronous multiplexed NOR/PSRAM read timings FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NOE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKH-NOEL) td(CLKL-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893h Electrical characteristics STM32F20xxx 136/178 DocID15818 Rev 11 Table 76. Synchronous multiplexed NOR/PSRAM read timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1.5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 5 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns DocID15818 Rev 11 137/178 STM32F20xxx Electrical characteristics 177 Figure 61. Synchronous multiplexed PSRAM write timings Table 77. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK- 1 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 7 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NWE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-NBLH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14992g td(CLKL-Data) FSMC_NBL Electrical characteristics STM32F20xxx 138/178 DocID15818 Rev 11 Figure 62. Synchronous non-multiplexed NOR/PSRAM read timings 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2.5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 4 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 3 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 8 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 0 - ns FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKH-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894g FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) DocID15818 Rev 11 139/178 STM32F20xxx Electrical characteristics 177 Figure 63. Synchronous non-multiplexed PSRAM write timings 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 79. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK- 1 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKLNADVL) FSMC_CLK low to FSMC_NADV low - 5 ns td(CLKLNADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14993g FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-Data) FSMC_NBL td(CLKL-NBLH) Electrical characteristics STM32F20xxx 140/178 DocID15818 Rev 11 PC Card/CompactFlash controller waveforms and timings Figure 64 through Figure 69 represent synchronous waveforms together with Table 80 and Table 81 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 2 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 79. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit DocID15818 Rev 11 141/178 STM32F20xxx Electrical characteristics 177 Figure 64. PC Card/CompactFlash controller waveforms for common memory read access 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 65. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NWE tw(NOE) FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2(1) FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NOE) tsu(D-NOE) th(NOE-D) tv(NCEx-A) td(NREG-NCEx) td(NIORD-NCEx) th(NCEx-AI) th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) ai14895b td(NCE4_1-NWE) tw(NWE) th(NWE-D) tv(NCE4_1-A) td(NREG-NCE4_1) td(NIORD-NCE4_1) th(NCE4_1-AI) MEMxHIZ =1 tv(NWE-D) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) ai14896b FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) td(D-NWE) FSMC_NCE4_2 High Electrical characteristics STM32F20xxx 142/178 DocID15818 Rev 11 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory read access 1. Only data bits 0...7 are read (bits 8...15 are disregarded). td(NCE4_1-NOE) tw(NOE) tsu(D-NOE) th(NOE-D) tv(NCE4_1-A) th(NCE4_1-AI) td(NREG-NCE4_1) th(NCE4_1-NREG) ai14897b FSMC_NWE FSMC_NOE FSMC_D[15:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NOE-NCE4_1) High DocID15818 Rev 11 143/178 STM32F20xxx Electrical characteristics 177 Figure 67. PC Card/CompactFlash controller waveforms for attribute memory write access 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 68. PC Card/CompactFlash controller waveforms for I/O space read access tw(NWE) tv(NCE4_1-A) td(NREG-NCE4_1) th(NCE4_1-AI) th(NCE4_1-NREG) tv(NWE-D) ai14898b FSMC_NWE FSMC_NOE FSMC_D[7:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) High td(NCE4_1-NWE) td(NIORD-NCE4_1) tw(NIORD) tsu(D-NIORD) td(NIORD-D) tv(NCEx-A) th(NCE4_1-AI) ai14899B FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD Electrical characteristics STM32F20xxx 144/178 DocID15818 Rev 11 Figure 69. PC Card/CompactFlash controller waveforms for I/O space write access td(NCE4_1-NIOWR) tw(NIOWR) tv(NCEx-A) th(NCE4_1-AI) th(NIOWR-D) ATTxHIZ =1 tv(NIOWR-D) ai14900c FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD Table 80. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+ 4 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK ns tw(NOE) FSMC_NOE low width 8THCLK– 0.5 8THCLK+ 1 ns td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high 5THCLK+ 2.5 - ns tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4 - ns th (N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 2 - ns tw(NWE) FSMC_NWE low width 8THCLK- 1 8THCLK+ 4 ns td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high 5THCLK+ 1.5 ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5HCLK+ 1 ns tv (NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8 THCLK - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. DocID15818 Rev 11 145/178 STM32F20xxx Electrical characteristics 177 NAND controller waveforms and timings Figure 70 through Figure 73 represent synchronous waveforms, together with Table 82 and Table 83 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter Min Max Unit tw(NIOWR) FSMC_NIOWR low width 8THCLK - 0.5 - ns tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid - 5THCLK- 1 ns th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 8THCLK- 3 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.5 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 1 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 0.5 - ns tw(NIORD) FSMC_NIORD low width 8THCLK+ 1 - ns tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9.5 ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Electrical characteristics STM32F20xxx 146/178 DocID15818 Rev 11 Figure 70. NAND controller waveforms for read access Figure 71. NAND controller waveforms for write access FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] tsu(D-NOE) th(NOE-D) ai14901c ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) tv(NWE-D) th(NWE-D) ai14902c FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NWE) th(NWE-ALE) DocID15818 Rev 11 147/178 STM32F20xxx Electrical characteristics 177 Figure 72. NAND controller waveforms for common memory read access Figure 73. NAND controller waveforms for common memory write access Table 82. Switching characteristics for NAND Flash read cycles(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(N0E) FSMC_NOE low width 4THCLK- 1 4THCLK+ 2 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 9 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 3 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK+ 2 - ns FSMC_NWE FSMC_NOE FSMC_D[15:0] tw(NOE) tsu(D-NOE) th(NOE-D) ai14912c ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) tw(NWE) tv(NWE-D) th(NWE-D) ai14913c FSMC_NWE FSMC_NOE FSMC_D[15:0] td(D-NWE) ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) Electrical characteristics STM32F20xxx 148/178 DocID15818 Rev 11 6.3.26 Camera interface (DCMI) timing specifications 6.3.27 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 85 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 74. SDIO high-speed mode Table 83. Switching characteristics for NAND Flash write cycles(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(NWE) FSMC_NWE low width 4THCLK- 1 4THCLK+ 3 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid - 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low - 3THCLK+ 2 ns th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK- 2 - ns Table 84. DCMI characteristics Symbol Parameter Conditions Min Max - Frequency ratio DCMI_PIXCLK/fHCLK DCMI_PIXCLK= 48 MHz 0.4 tW(CKH) CK D, CMD (output) D, CMD (input) tC tW(CKL) tOV tOH tISU tIH tf tr ai14887 DocID15818 Rev 11 149/178 STM32F20xxx Electrical characteristics 177 Figure 75. SD default mode 6.3.28 RTC characteristics Table 85. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 ns tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31 tr Clock rise time CL ≤ 30 pF 3.5 tf Clock fall time CL ≤ 30 pF 5 CMD, D inputs (referenced to CK) tISU Input setup time CL ≤ 30 pF 2 ns tIH Input hold time CL ≤ 30 pF 0 CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL ≤ 30 pF 6 ns tOH Output hold time CL ≤ 30 pF 0.3 CMD, D outputs (referenced to CK) in SD default mode(1) 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. tOVD Output valid default time CL ≤ 30 pF 7 ns tOHD Output hold default time CL ≤ 30 pF 0.5 ai14888 CK D, CMD (output) tOVD tOHD Table 86. RTC characteristics Symbol Parameter Conditions Min Max - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 - Package characteristics STM32F20xxx 150/178 DocID15818 Rev 11 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID15818 Rev 11 151/178 STM32F20xxx Package characteristics 177 Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline 1. Drawing is not to scale. A1 A2 A SEATING PLANE ccc C b C c A1 L L1 K GAUGE PLANE 0.25 mm IDENTIFICATION PIN 1 D D1 D3 e 1 16 17 32 48 33 49 64 E3 E1 E 5W_ME_V2 Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3937 0.3937 0.4016 D3 - 7.500 - - 0.2953 - Package characteristics STM32F20xxx 152/178 DocID15818 Rev 11 Figure 77. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3937 0.3937 0.4016 E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) Symbol millimeters inches(1) Min Typ Max Min Typ Max 48 49 32 64 17 1 16 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909c DocID15818 Rev 11 153/178 STM32F20xxx Package characteristics 177 Figure 78. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline 1. Drawing is not to scale. Side view Bump side Detail A Wafer back side A1 ball location A1 Detail A rotated by 90 °C eee D A0FX_ME Seating plane A2 A b E e e1 e G F e1 Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data Symbol millimeters inches Min Typ Max Min Typ Max A 0.520 0.570 0.600 0.0205 0.0224 0.0236 A1 0.170 0.190 0.210 0.0067 0.0075 0.0083 A2 0.350 0.380 0.410 0.0138 0.0150 0.0161 b 0.245 0.270 0.295 0.0096 0.0106 0.0116 D 3.619 3.639 3.659 0.1425 0.1433 0.1441 E 3.951 3.971 3.991 0.1556 0.1563 0.1571 e - 0.400 - - 0.0157 - e1 - 3.218 - - 0.1267 - F - 0.220 - - 0.0087 - Package characteristics STM32F20xxx 154/178 DocID15818 Rev 11 G - 0.386 - - 0.0152 - eee - - 0.050 - - 0.0020 Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data (continued) Symbol millimeters inches Min Typ Max Min Typ Max DocID15818 Rev 11 155/178 STM32F20xxx Package characteristics 177 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. Drawing is not to scale. IDENTIFICATION e PIN 1 GAUGE PLANE 0.25 mm SEATING PLANE D D1 D3 E3 E1 E K ccc C C 1 25 100 26 76 75 51 50 1L_ME_V4 A2 A A1 L1 L c b A1 Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 Package characteristics STM32F20xxx 156/178 DocID15818 Rev 11 Figure 80. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max 75 51 76 50 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 DocID15818 Rev 11 157/178 STM32F20xxx Package characteristics 177 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. Drawing is not to scale. e IDENTIFICATION PIN 1 GAUGE PLANE 0.25 mm SEATING PLANE D D1 D3 E3 E1 E K ccc C C 1 36 37 144 109 108 73 72 1A_ME_V3 A2 A A1 L1 L c b A1 Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 Package characteristics STM32F20xxx 158/178 DocID15818 Rev 11 Figure 82. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) Symbol millimeters inches(1) Min Typ Max Min Typ Max ai14905c 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 1 36 37 72 108 73 109 144 DocID15818 Rev 11 159/178 STM32F20xxx Package characteristics 177 Figure 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline 1. Drawing is not to scale. Table 91. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - HD 25.900 - 26.100 1.0197 - 1.0276 1T_ME_V2 A2 A e E HE D HD ZD ZE b 0.25 mm gauge plane A1 L L1 k c IDENTIFICATION PIN 1 C Seating plane A1 Package characteristics STM32F20xxx 160/178 DocID15818 Rev 11 HE 25.900 26.100 1.0197 1.0276 L(2) 0.450 0.750 0.0177 0.0295 L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 k 0° 7° 0° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. Table 91. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data (continued) Symbol millimeters inches(1) Min Typ Max Min Typ Max DocID15818 Rev 11 161/178 STM32F20xxx Package characteristics 177 Figure 84. LQFP176 recommended footprint 1. Dimensions are expressed in millimeters. 1T_FP_V1 133 132 1.2 0.3 0.5 89 88 1.2 44 45 21.8 26.7 1 176 26.7 21.8 Package characteristics STM32F20xxx 162/178 DocID15818 Rev 11 Figure 85. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline 1. Drawing is not to scale. A0E7_ME_V5 Seating plane A2 ddd C A1 A e F F e R A 15 1 BOTTOM VIEW E D TOP VIEW Øb (176 + 25 balls) B A Ø eee M B Ø fff M C C A C A1 ball identifier A1 ball index area b Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3917 0.3937 0.3957 E 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID15818 Rev 11 163/178 STM32F20xxx Package characteristics 177 7.2 Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Table 93. Package thermal characteristics Symbol Parameter Value Unit ΘJA Thermal resistance junction-ambient LQFP 64 - 10 × 10 mm / 0.5 mm pitch 45 °C/W Thermal resistance junction-ambient WLCSP64+2 - 0.400 mm pitch 51 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 × 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10× 10 mm / 0.5 mm pitch 39 Part numbering STM32F20xxx 164/178 DocID15818 Rev 11 8 Part numbering For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 94. Ordering information scheme Example: STM32 F 205 R E T 6 Vxxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 205 = STM32F20x, connectivity 207= STM32F20x, connectivity, camera interface, Ethernet Pin count R = 64 pins or 66 pins(1) V = 100 pins Z = 144 pins I = 176 pins Flash memory size B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory E = 512 Kbytes of Flash memory F = 768 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Software option Internal code or Blank Options xxx = programmed parts TR = tape and reel 1. The 66 pins is available on WLCSP package only. DocID15818 Rev 11 165/178 STM32F20xxx Revision history 177 9 Revision history Table 95. Document revision history Date Revision Changes 05-Jun-2009 1 Initial release. 09-Oct-2009 2 Document status promoted from Target specification to Preliminary data. In Table 8: STM32F20x pin and ball definitions: – Note 4 updated – VDD_SA and VDD_3 pins inverted (Figure 12: STM32F20x LQFP100 pinout, Figure 13: STM32F20x LQFP144 pinout and Figure 14: STM32F20x LQFP176 pinout corrected accordingly). Section 7.1: Package mechanical data changed to LQFP with no exposed pad. 01-Feb-2010 3 LFBGA144 package removed. STM32F203xx part numbers removed. Part numbers with 128 and 256 Kbyte Flash densities added. Encryption features removed. PC13-TAMPER-RTC renamed to PC13-RTC_AF1 and PI8-TAMPERRTC renamed to PI8-RTC_AF2. 13-Jul-2010 4 Renamed high-speed SRAM, system SRAM. Removed combination: 128 KBytes Flash memory in LQFP144. Added UFBGA176 package. Added note 1 related to LQFP176 package in Table 2, Figure 14, and Table 94. Added information on ART accelerator and audio PLL (PLLI2S). Added Table 6: USART feature comparison. Several updates on Table 8: STM32F20x pin and ball definitions and Table 10: Alternate function mapping. ADC, DAC, oscillator, RTC_AF, WKUP and VBUS signals removed from alternate functions and moved to the “other functions” column in Table 8: STM32F20x pin and ball definitions. TRACESWO added in Figure 4: STM32F20x block diagram, Table 8: STM32F20x pin and ball definitions, and Table 10: Alternate function mapping. XTAL oscillator frequency updated on cover page, in Figure 4: STM32F20x block diagram and in Section 3.11: External interrupt/event controller (EXTI). Updated list of peripherals used for boot mode in Section 3.13: Boot modes. Added Regulator bypass mode in Section 3.16: Voltage regulator, and Section 6.3.4: Operating conditions at power-up / power-down (regulator OFF). Updated Section 3.17: Real-time clock (RTC), backup SRAM and backup registers. Added Note Note: in Section 3.18: Low-power modes. Added SPI TI protocol in Section 3.23: Serial peripheral interface (SPI). Revision history STM32F20xxx 166/178 DocID15818 Rev 11 13-Jul-2010 4 (continued) Added USB OTG_FS features in Section 3.28: Universal serial bus onthe- go full-speed (OTG_FS). Updated VCAP_1 and VCAP_2 capacitor value to 2.2 μF in Figure 19: Power supply scheme. Removed DAC, modified ADC limitations, and updated I/O compensation for 1.8 to 2.1 V range in Table 15: Limitations depending on the operating power supply range. Added VBORL, VBORM, VBORH and IRUSH in Table 19: Embedded reset and power control block characteristics. Removed table Typical current consumption in Sleep mode with Flash memory in Deep power down mode. Merged typical and maximum current consumption sections and added Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM, Table 22: Typical and maximum current consumption in Sleep mode, Table 23: Typical and maximum current consumptions in Stop mode, Table 24: Typical and maximum current consumptions in Standby mode, and Table 25: Typical and maximum current consumptions in VBAT mode. Update Table 34: Main PLL characteristics and added Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Added Note 8 for CIO in Table 48: I/O AC characteristics. Updated Section 6.3.18: TIM timer characteristics. Added TNRST_OUT in Table 49: NRST pin characteristics. Updated Table 52: I2C characteristics. Removed 8-bit data in and data out waveforms from Figure 47: ULPI timing diagram. Removed note related to ADC calibration in Table 67. Section 6.3.20: 12-bit ADC characteristics: ADC characteristics tables merged into one single table; tables ADC conversion time and ADC accuracy removed. Updated Table 68: DAC characteristics. Updated Section 6.3.22: Temperature sensor characteristics and Section 6.3.23: VBAT monitoring characteristics. Update Section 6.3.26: Camera interface (DCMI) timing specifications. Added Section 6.3.27: SD/SDIO MMC card host interface (SDIO) characteristics, and Section 6.3.28: RTC characteristics. Added Section 7.2: Thermal characteristics. Updated Table 91: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data and Figure 83: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline. Changed tape and reel code to TX in Table 94: Ordering information scheme. Added Table 101: Main applications versus package for STM32F2xxx microcontrollers. Updated figures in Appendix A.2: USB OTG full speed (FS) interface solutions and A.3: USB OTG high speed (HS) interface solutions. Updated Figure 94: Audio player solution using PLL, PLLI2S, USB and 1 crystal and Figure 95: Audio PLL (PLLI2S) providing accurate I2S clock. Table 95. Document revision history (continued) Date Revision Changes DocID15818 Rev 11 167/178 STM32F20xxx Revision history 177 25-Nov-2010 5 Update I/Os in Section : Features. Added WLCSP64+2 package. Added note 1 related to LQFP176 on cover page. Added trademark for ART accelerator. Updated Section 3.2: Adaptive real-time memory accelerator (ART Accelerator™). Updated Figure 5: Multi-AHB matrix. Added case of BOR inactivation using IRROFF on WLCSP devices in Section 3.15: Power supply supervisor. Reworked Section 3.16: Voltage regulator to clarify regulator off modes. Renamed PDROFF, IRROFF in the whole document. Added Section 3.19: VBAT operation. Updated LIN and IrDA features for UART4/5 in Table 6: USART feature comparison. Table 8: STM32F20x pin and ball definitions: Modified VDD_3 pin, and added note related to the FSMC_NL pin; renamed BYPASS-REG REGOFF, and add IRROFF pin; renamed USART4/5 UART4/5. USART4 pins renamed UART4. Changed VSS_SA to VSS, and VDD_SA pin reserved for future use. Updated maximum HSE crystal frequency to 26 MHz. Section 6.2: Absolute maximum ratings: Updated VIN minimum and maximum values and note related to five-volt tolerant inputs in Table 11: Voltage characteristics. Updated IINJ(PIN) maximum values and related notes in Table 12: Current characteristics. Updated VDDA minimum value in Table 14: General operating conditions. Added Note 2 and updated Maximum CPU frequency in Table 15: Limitations depending on the operating power supply range, and added Figure 21: Number of wait states versus fCPU and VDD range. Added brownout level 1, 2, and 3 thresholds in Table 19: Embedded reset and power control block characteristics. Changed fOSC_IN maximum value in Table 30: HSE 4-26 MHz oscillator characteristics. Changed fPLL_IN maximum value in Table 34: Main PLL characteristics, and updated jitter parameters in Table 35: PLLI2S (audio PLL) characteristics. Section 6.3.16: I/O port characteristics: updated VIH and VIL in Table 48: I/O AC characteristics. Added Note 1 below Table 47: Output voltage characteristics. Updated RPD and RPU parameter description in Table 57: USB OTG FS DC electrical characteristics. Updated VREF+ minimum value in Table 66: ADC characteristics. Updated Table 71: Embedded internal reference voltage. Removed Ethernet and USB2 for 64-pin devices in Table 101: Main applications versus package for STM32F2xxx microcontrollers. Added A.2: USB OTG full speed (FS) interface solutions, removed “OTG FS connection with external PHY” figure, updated Figure 87, Figure 88, and Figure 90 to add STULPI01B. Table 95. Document revision history (continued) Date Revision Changes Revision history STM32F20xxx 168/178 DocID15818 Rev 11 22-Apr-2011 6 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability of WLCSP64+2 package limited to 512 Kbyte and 1 Mbyte devices. Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package and Figure 2: Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package. Added camera interface for STM32F207Vx devices in Table 2: STM32F205xx features and peripheral counts. Removed 16 MHz internal RC oscillator accuracy in Section 3.12: Clocks and startup. Updated Section 3.16: Voltage regulator. Modified I2S sampling frequency range in Section 3.12: Clocks and startup, Section 3.24: Inter-integrated sound (I2S), and Section 3.30: Audio PLL (PLLI2S). Updated Section 3.17: Real-time clock (RTC), backup SRAM and backup registers and description of TIM2 and TIM5 in Section 3.20.2: General-purpose timers (TIMx). Modified maximum baud rate (oversampling by 16) for USART1 in Table 6: USART feature comparison. Updated note related to RFU pin below Figure 12: STM32F20x LQFP100 pinout, Figure 13: STM32F20x LQFP144 pinout, Figure 14: STM32F20x LQFP176 pinout, Figure 15: STM32F20x UFBGA176 ballout, and Table 8: STM32F20x pin and ball definitions. In Table 8: STM32F20x pin and ball definitions,:changed I2S2_CK and I2S3_CK to I2S2_SCK and I2S3_SCK, respectively; added PA15 and TT (3.6 V tolerant I/O). Added RTC_50Hz as PB15 alternate function in Table 8: STM32F20x pin and ball definitions and Table 10: Alternate function mapping. Removed ETH _RMII_TX_CLK for PC3/AF11 in Table 10: Alternate function mapping. Updated Table 11: Voltage characteristics and Table 12: Current characteristics. TSTG updated to –65 to +150 in Table 13: Thermal characteristics. Added CEXT, ESL, and ESR in Table 14: General operating conditions as well as Section 6.3.2: VCAP1/VCAP2 external capacitor. Modified Note 4 in Table 15: Limitations depending on the operating power supply range. Updated Table 17: Operating conditions at power-up / power-down (regulator ON), and Table 18: Operating conditions at power-up / power-down (regulator OFF). Added OSC_OUT pin in Figure 17: Pin loading conditions. and Figure 18: Pin input voltage. Updated Figure 19: Power supply scheme to add IRROFF and REGOFF pins and modified notes. Updated VPVD, VBOR1, VBOR2, VBOR3, TRSTTEMPO typical value, and IRUSH, added ERUSH and Note 2 in Table 19: Embedded reset and power control block characteristics. Table 95. Document revision history (continued) Date Revision Changes DocID15818 Rev 11 169/178 STM32F20xxx Revision history 177 22-Apr-2011 6 (continued) Updated Typical and maximum current consumption conditions, as well as Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure 23, Figure 24, Figure 25, and Figure 26. Updated Table 22: Typical and maximum current consumption in Sleep mode, and added Figure 27 and Figure 28. Updated Table 23: Typical and maximum current consumptions in Stop mode. Added Figure 29: Typical current consumption vs temperature in Stop mode. Updated Table 24: Typical and maximum current consumptions in Standby mode and Table 25: Typical and maximum current consumptions in VBAT mode. Updated On-chip peripheral current consumption conditions and Table 26: Peripheral current consumption. Updated tWUSTDBY and tWUSTOP, and added Note 3 in Table 27: Lowpower mode wakeup timings. Maximum fHSE_ext and minimum tw(HSE) values updated in Table 28: High-speed external user clock characteristics. Updated C and gm in Table 30: HSE 4-26 MHz oscillator characteristics. Updated RF, I2, gm, and tsu(LSE) in Table 31: LSE oscillator characteristics (fLSE = 32.768 kHz). Added Note 1 and updated ACCHSI, IDD(HSI, and tsu(HSI) in Table 32: HSI oscillator characteristics. Added Figure 34: ACCHSI versus temperature. Updated fLSI, tsu(LSI) and IDD(LSI) in Table 33: LSI oscillator characteristics. Added Figure 35: ACCLSI versus temperature Table 34: Main PLL characteristics: removed note 1, updated tLOCK, jitter, IDD(PLL) and IDDA(PLL), added Note 2 for fPLL_IN minimum and maximum values. Table 35: PLLI2S (audio PLL) characteristics: removed note 1, updated tLOCK, jitter, IDD(PLLI2S) and IDDA(PLLI2S), added Note 2 for fPLLI2S_IN minimum and maximum values. Added Note 1 in Table 36: SSCG parameters constraint. Updated Table 37: Flash memory characteristics. Modified Table 38: Flash memory programming and added Note 2 for tprog. Updated tprog and added Note 1 in Table 39: Flash memory programming with VPP. Modified Figure 39: Recommended NRST pin protection. Updated Table 42: EMI characteristics and EMI monitoring conditions in Section : Electromagnetic Interference (EMI)g. Added Note 2 related to VESD(HBM)in Table 43: ESD absolute maximum ratings. Updated Table 48: I/O AC characteristics. Added Section 6.3.15: I/O current injection characteristics. Modified maximum frequency values and conditions in Table 48: I/O AC characteristics. Updated tres(TIM) in Table 50: Characteristics of TIMx connected to the APB1 domain. Modified tres(TIM) and fEXT Table 51: Characteristics of TIMx connected to the APB2 domain. Table 95. Document revision history (continued) Date Revision Changes Revision history STM32F20xxx 170/178 DocID15818 Rev 11 22-Apr-2011 6 (continued) Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and tf(SCK) to tf(SCL) in Table 52: I2C characteristics and in Figure 40: I2C bus AC waveforms and measurement circuit. Added Table 57: USB OTG FS DC electrical characteristics and updated Table 58: USB OTG FS electrical characteristics. Updated VDD minimum value in Table 62: Ethernet DC electrical characteristics. Updated Table 66: ADC characteristics and RAIN equation. Updated RAIN equation. Updated Table 68: DAC characteristics. Updated tSTART in Table 69: TS characteristics. Updated R typical value in Table 70: VBAT monitoring characteristics. Updated Table 71: Embedded internal reference voltage. Modified FSMC_NOE waveform in Figure 56: Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKLAIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKLNWEH), and updated data latency from 1 to 0 in Figure 60: Synchronous multiplexed NOR/PSRAM read timings, Figure 61: Synchronous multiplexed PSRAM write timings, Figure 62: Synchronous non-multiplexed NOR/PSRAM read timings, and Figure 63: Synchronous non-multiplexed PSRAM write timings, Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV), td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and modified tw(CLK) minimum value in Table 76, Table 77, Table 78, and Table 79. Updated note 2 in Table 72, Table 73, Table 74, Table 75, Table 76, Table 77, Table 78, and Table 79. Modified th(NIOWR-D) in Figure 69: PC Card/CompactFlash controller waveforms for I/O space write access. Modified FSMC_NCEx signal in Figure 70: NAND controller waveforms for read access, Figure 71: NAND controller waveforms for write access, Figure 72: NAND controller waveforms for common memory read access, and Figure 73: NAND controller waveforms for common memory write access Specified Full speed (FS) mode for Figure 89: USB OTG HS peripheral-only connection in FS mode and Figure 90: USB OTG HS host-only connection in FS mode. Table 95. Document revision history (continued) Date Revision Changes DocID15818 Rev 11 171/178 STM32F20xxx Revision history 177 14-Jun-2011 7 Added SDIO in Table 2: STM32F205xx features and peripheral counts. Updated VIN for 5V tolerant pins in Table 11: Voltage characteristics. Updated jitter parameters description in Table 34: Main PLL characteristics. Remove jitter values for system clock in Table 35: PLLI2S (audio PLL) characteristics. Updated Table 42: EMI characteristics. Update Note 2 in Table 52: I2C characteristics. Updated Avg_Slope typical value and TS_temp minimum value in Table 69: TS characteristics. Updated TS_vbat minimum value in Table 70: VBAT monitoring characteristics. Updated TS_vrefint mimimum value in Table 71: Embedded internal reference voltage. Added Software option in Section 8: Part numbering. In Table 101: Main applications versus package for STM32F2xxx microcontrollers, renamed USB1 and USB2, USB OTG FS and USB OTG HS, respectively; and removed USB OTG FS and camera interface for 64-pin package; added USB OTG HS on 64-pin package; added Note 1 and Note 2. 20-Dec-2011 8 Updated SDIO register addresses in Figure 16: Memory map. Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package, Figure 2: Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package, Figure 1: Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package, and added Figure 4: Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Section 3.3: Memory protection unit. Updated Section 3.6: Embedded SRAM. Updated Section 3.28: Universal serial bus on-the-go full-speed (OTG_FS) to remove external FS OTG PHY support. In Table 8: STM32F20x pin and ball definitions: changed SPI2_MCK and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added ETH _RMII_TX_EN atlternate function to PG11. Added EVENTOUT in the list of alternate functions for I/O pin/balls. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. In Table 10: Alternate function mapping: changed I2S3_SCK to I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3 for PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. Changed I2S3_SCK into I2S3_MCK for PC7/AF6. Updated peripherals corresponding to AF12. Removed CEXT and ESR from Table 14: General operating conditions. Table 95. Document revision history (continued) Date Revision Changes Revision history STM32F20xxx 172/178 DocID15818 Rev 11 20-Dec-2011 8 (continued) Added maximum power consumption at TA=25 °C in Table 23: Typical and maximum current consumptions in Stop mode. Updated md minimum value in Table 36: SSCG parameters constraint. Added examples in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 54: SPI characteristics and Table 55: I2S characteristics. Updated Figure 47: ULPI timing diagram and Table 61: ULPI timing. Updated Table 63: Dynamics characteristics: Ethernet MAC signals for SMI, Table 64: Dynamics characteristics: Ethernet MAC signals for RMII, and Table 65: Dynamics characteristics: Ethernet MAC signals for MII. Section 6.3.25: FSMC characteristics: updated Table 72 toTable 83, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 61: Synchronous multiplexed PSRAM write timings. UpdatedTable 84: DCMI characteristics. Updated Table 92: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data. Updated Table 94: Ordering information scheme. Appendix A.2: USB OTG full speed (FS) interface solutions: updated Figure 87: USB OTG FS (full speed) host-only connection and added Note 2, updated Figure 88: OTG FS (full speed) connection dual-role with internal PHY and added Note 3 and Note 4, modified Figure 89: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY and added Note 2. Appendix A.3: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode,updated Figure 89: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY. Added Appendix A.4: Ethernet interface solutions. Updated disclaimer on last page. 24-Apr-2012 9 Updated VDD minimum value in Section 2: Description. Updated number of USB OTG HS and FS, modified packages for STM32F207Ix part numbers, added Note 1 related to FSMC and Note 2 related to SPI/I2S, and updated Note 3 in Table 2: STM32F205xx features and peripheral counts and Table 3: STM32F207xx features and peripheral counts. Added Note 2 and update TIM5 in Figure 4: STM32F20x block diagram. Updated maximum number of maskable interrupts in Section 3.10: Nested vectored interrupt controller (NVIC). Updated VDD minimum value in Section 3.14: Power supply schemes. Updated Note a in Section 3.16.1: Regulator ON. Removed STM32F205xx in Section 3.28: Universal serial bus on-thego full-speed (OTG_FS). Table 95. Document revision history (continued) Date Revision Changes DocID15818 Rev 11 173/178 STM32F20xxx Revision history 177 24-Apr-2012 9 (continued) Removed support of I2C for OTG PHY in Section 3.29: Universal serial bus on-the-go high-speed (OTG_HS). Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 8: STM32F20x pin and ball definitions and Table 10: Alternate function mapping. Renamed PH10 alternate function into TIM5_CH1 in Table 10: Alternate function mapping. Added Table 9: FSMC pin definition. Updated Note 2 in Table 14: General operating conditions, Note 2 in Table 15: Limitations depending on the operating power supply range, and Note 1 below Figure 21: Number of wait states versus fCPU and VDD range. Updated VPOR/PDR in Table 19: Embedded reset and power control block characteristics. Updated typical values in Table 24: Typical and maximum current consumptions in Standby mode and Table 25: Typical and maximum current consumptions in VBAT mode. Updated Table 30: HSE 4-26 MHz oscillator characteristics and Table 31: LSE oscillator characteristics (fLSE = 32.768 kHz). Updated Table 37: Flash memory characteristics, Table 38: Flash memory programming, and Table 39: Flash memory programming with VPP. Updated Section : Output driving current. Updated Note 3 and removed note related to minimum hold time value in Table 52: I2C characteristics. Updated Table 64: Dynamics characteristics: Ethernet MAC signals for RMII. Updated Note 1, CADC, IVREF+, and IVDDA in Table 66: ADC characteristics. Updated Note 3 and note concerning ADC accuracy vs. negative injection current in Table 67: ADC accuracy. Updated Note 1 in Table 68: DAC characteristics. Updated Section Figure 85.: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. Appendix A.1: Main applications versus package: removed number of address lines for FSMC/NAND in Table 101: Main applications versus package for STM32F2xxx microcontrollers. Appendix A.4: Ethernet interface solutions: updated Figure 92: Complete audio player solution 1 and Figure 93: Complete audio player solution 2. Table 95. Document revision history (continued) Date Revision Changes Revision history STM32F20xxx 174/178 DocID15818 Rev 11 29-Oct-2012 10 Changed minimum supply voltage from 1.65 to 1.8 V. Updated number of AHB buses in Section 2: Description and Section 3.12: Clocks and startup. Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Note 2 below Figure 4: STM32F20x block diagram. Changed System memory to System memory + OTP in Figure 16: Memory map. Added Note 1 below Table 16: VCAP1/VCAP2 operating conditions. Updated VDDA and VREF+ decouping capacitor in Figure 19: Power supply scheme and updated Note 3. Changed simplex mode into half-duplex mode in Section 3.24: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively.Changed TIM2_CH1/TIM2_ETR into TIM2_CH1_ETR for PA0 and PA5 in Table 10: Alternate function mapping. Updated note applying to IDD (external clock and all peripheral disabled) in Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled). Updated Note 3 below Table 22: Typical and maximum current consumption in Sleep mode. Removed fHSE_ext typical value in Table 28: High-speed external user clock characteristics. Updated master I2S clock jitter conditions and vlaues in Table 35: PLLI2S (audio PLL) characteristics. Updated equations in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Swapped TTL and CMOS port conditions for VOL and VOH in Table 47: Output voltage characteristics. Updated VIL(NRST) and VIH(NRST) in Table 49: NRST pin characteristics. Updated Table 54: SPI characteristics and Table 55: I2S characteristics. Removed note 1 related to measurement points below Figure 42: SPI timing diagram - slave mode and CPHA = 1, Figure 43: SPI timing diagram - master mode, and Figure 44: I2S slave timing diagram (Philips protocol)(1). Updated tHC in Table 61: ULPI timing. Updated Figure 48: Ethernet SMI timing diagram, Table 63: Dynamics characteristics: Ethernet MAC signals for SMI and Table 65: Dynamics characteristics: Ethernet MAC signals for MII. Update fTRIG in Table 66: ADC characteristics. Updated IDDA description in Table 68: DAC characteristics. Updated note below Figure 53: Power supply and reference decoupling (VREF+ not connected to VDDA) and Figure 54: Power supply and reference decoupling (VREF+ connected to VDDA). Table 95. Document revision history (continued) Date Revision Changes DocID15818 Rev 11 175/178 STM32F20xxx Revision history 177 29-Oct-2012 10 (continued) Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 76: Synchronous multiplexed NOR/PSRAM read timings, Table 78: Synchronous nonmultiplexed NOR/PSRAM read timings, Figure 60: Synchronous multiplexed NOR/PSRAM read timings and Figure 62: Synchronous non-multiplexed NOR/PSRAM read timings. Added Figure 84: LQFP176 recommended footprint. Added Note 2 below Figure 86: Regulator OFF/internal reset ON. Updated device subfamily in Table 94: Ordering information scheme. Remove reference to note 2 for USB IOTG FS in Table 101: Main applications versus package for STM32F2xxx microcontrollers. Table 95. Document revision history (continued) Date Revision Changes Revision history STM32F20xxx 176/178 DocID15818 Rev 11 04-Nov-2013 11 In the whole document, updated notes related to WLCSP64+2 usage with IRROFF set to VDD. Updated Section 3.14: Power supply schemes, Section 3.15: Power supply supervisor, Section 3.16.1: Regulator ON and Section 3.16.2: Regulator OFF. Added Section 3.16.3: Regulator ON/OFF and internal reset ON/OFF availability. Added note related to WLCSP64+2 package. Restructured RTC features and added reference clock detection in Section 3.17: Real-time clock (RTC), backup SRAM and backup registers. Added note indicating the package view below Figure 10: STM32F20x LQFP64 pinout, Figure 12: STM32F20x LQFP100 pinout, Figure 13: STM32F20x LQFP144 pinout, and Figure 14: STM32F20x LQFP176 pinout. Added Table 7: Legend/abbreviations used in the pinout table. Table 8: STM32F20x pin and ball definitions: content reformatted; removed indeces on VSS and VDD; updated PA4, PA5, PA6, PC4, BOOT0; replaced DCMI_12 by DCMI_D12, TIM8_CHIN by TIM8_CH1N, ETH_MII_RX_D0 by ETH_MII_RXD0, ETH_MII_RX_D1 by ETH_MII_RXD1, ETH_RMII_RX_D0 by ETH_RMII_RXD0, ETH_RMII_RX_D1 by ETH_RMII_RXD1, and RMII_CRS_DV by ETH_RMII_CRS_DV. Table 10: Alternate function mapping: replaced FSMC_BLN1 by FSMC_NBL1, added EVENTOUT as AF15 alternated fucntion for PC13, PC14, PC15, PH0, PH1, and PI8. Updated Figure 17: Pin loading conditions and Figure 18: Pin input voltage. Added VIN in Table 14: General operating conditions. Removed note applying to VPOR/PDR minimum value in Table 19: Embedded reset and power control block characteristics. Updated notes related to CL1 and CL2 in Section : Low-speed external clock generated from a crystal/ceramic resonator. Updated conditions in Table 41: EMS characteristics. Updated Table 42: EMI characteristics. Updated VIL, VIH and VHys in Table 46: I/O static characteristics. Added Figure : Output driving current and updated Figure 38: I/O AC characteristics definition. Updated VIL(NRST) and VIH(NRST) in Table 49: NRST pin characteristics, updated Figure 38: I/O AC characteristics definition. Removed tests conditions in Section : I2C interface characteristics. Updated Table 52: I2C characteristics and Figure 40: I2C bus AC waveforms and measurement circuit. Updated IVREF+ and IVDDA in Table 66: ADC characteristics. Updated Offset comments in Table 68: DAC characteristics. Updated minimum th(CLKH-DV) value in Table 78: Synchronous nonmultiplexed NOR/PSRAM read timings. Table 95. Document revision history (continued) Date Revision Changes DocID15818 Rev 11 177/178 STM32F20xxx Revision history 177 04-Nov-2013 11 (continued) Removed Appendix A Application block diagrams. Updated Figure 76: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table 87: LQFP64 – 10 x 10 mm 64 pin lowprofile quad flat package mechanical data. Updated Figure 79: LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline, Figure 81: LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline, Figure 83: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline. Updated Figure 85: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline and Figure 85: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. Table 95. Document revision history (continued) Date Revision Changes STM32F20xxx 178/178 DocID15818 Rev 11 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of Flash memory – Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM – Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) FBGA UFBGA176 (10 × 10 mm) LQFP176 (24 × 24 mm) WLCSP90 Table 1. Device summary Reference Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE www.st.com Contents STM32F405xx, STM32F407xx 2/185 DocID022152 Rev 4 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 28 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 33 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID022152 Rev 4 3/185 STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 80 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 80 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 80 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 102 Contents STM32F405xx, STM32F407xx 4/185 DocID022152 Rev 4 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 155 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 156 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 171 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 173 A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID022152 Rev 4 5/185 STM32F405xx, STM32F407xx List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 Table 3. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 7. STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 10. STM32F40x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 79 Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 80 Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 83 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 88 Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 89 Table 26. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 31. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 33. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 35. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 36. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 37. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 39. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 40. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 41. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 42. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 43. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 44. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 45. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 46. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 List of tables STM32F405xx, STM32F407xx 6/185 DocID022152 Rev 4 Table 47. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 48. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 49. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 50. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 51. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 52. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 53. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 55. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 56. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 57. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 58. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 59. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 61. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 62. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 63. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 64. Dynamic characteristics: Ehternet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 65. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 66. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 70. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 71. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 72. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 73. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 74. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 138 Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 139 Table 77. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 78. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 80. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 85. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 86. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 87. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 88. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 89. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 159 Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 160 Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 162 Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 164 Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 167 DocID022152 Rev 4 7/185 STM32F405xx, STM32F407xx List of tables Table 96. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 97. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 98. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 List of figures STM32F405xx, STM32F407xx 8/185 DocID022152 Rev 4 List of figures Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64. . . . . . . . . . . . 15 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. STM32F40x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24 Figure 8. PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12. STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 13. STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15. STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 16. STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 17. STM32F40x WLCSP90 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18. STM32F40x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 85 Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 85 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 86 Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 86 Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 89 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 90 Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 39. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DocID022152 Rev 4 9/185 STM32F405xx, STM32F407xx List of figures Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 44. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 124 Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 133 Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 133 Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138 Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 139 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 148 Figure 64. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 148 Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 150 Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 151 Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 154 Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154 Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 75. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 159 Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 160 Figure 78. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 162 Figure 80. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 164 Figure 82. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 167 Figure 85. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 87. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 171 List of figures STM32F405xx, STM32F407xx 10/185 DocID022152 Rev 4 Figure 88. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172 Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 90. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 91. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 92. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DocID022152 Rev 4 11/185 STM32F405xx, STM32F407xx Introduction 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming manual (PM0214) available from www.st.com. Description STM32F405xx, STM32F407xx 12/185 DocID022152 Rev 4 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. • Up to three I2Cs • Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus two UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • An SDIO/MMC interface • Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances STM32F405xx, STM32F407xx Description DocID022152 Rev 4 13/185 Figure 5 shows the general block diagram of the device family. Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix Flash memory in Kbytes 1024 512 512 1024 512 1024 512 1024 SRAM in Kbytes System 192(112+16+64) Backup 4 FSMC memory controller No Yes(1) Ethernet No Yes Timers Generalpurpose 10 Advanced -control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Description STM32F405xx, STM32F407xx 14/185 DocID022152 Rev 4 Communi cation interfaces SPI / I2S 3/2 (full duplex)(2) I2C 3 USART/ UART 4/2 USB OTG FS Yes USB OTG HS Yes CAN 2 SDIO Yes Camera interface No Yes GPIOs 51 72 82 114 72 82 114 140 12-bit ADC Number of channels 3 16 13 16 24 13 16 24 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz Operating voltage 1.8 to 3.6 V(3) Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Package LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix DocID022152 Rev 4 15/185 STM32F405xx, STM32F407xx Description 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto- pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 31 1 16 17 32 48 33 64 49 47 VSS VSS VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration ai18489 Description STM32F405xx, STM32F407xx 16/185 DocID022152 Rev 4 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 20 49 1 25 26 50 75 51 100 76 73 19 VSS VSS VDD VSS VSS VSS 0 ΩΩ resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration ai18488c 99 (VSS) VDD VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VSS for the STM32F4xx VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx ai18487d 31 71 1 36 37 72 108 73 144 109 VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 106 VSS 30 Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VDD or signal from external power supply supervisor for the STM32F4xx VDD VSS VSS VSS 143 (PDR_ON) VDD VSS VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx Signal from external power supply supervisor DocID022152 Rev 4 17/185 STM32F405xx, STM32F407xx Description Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages MS19919V3 1 44 45 88 132 89 176 133 Two 0 Ω resistors connected to: - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx 171 (PDR_ON) VDDVSS Signal from external power supply supervisor Description STM32F405xx, STM32F407xx 18/185 DocID022152 Rev 4 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The camera interface and ethernet are available only on STM32F407xx devices. MS19920V3 GPIO PORT A AHB/APB2 140 AF PA[15:0] TIM1 / PWM 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF RX, TX, CK, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF APB 1 30M Hz 8 analog inputs common to the 3 ADCs VDDREF_ADC MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX DAC1_OUT as AF ITF WWDG 4 KB BKPSRAM RTC_AF1 OSC32_IN OSC32_OUT VDDA, VSSA NRST 16b SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA2 SCL, SDA, SMBA as AF JTAG & SW ARM Cortex-M4 168 MHz ETM NVIC MPU TRACECLK TRACED[3:0] Ethernet MAC 10/100 DMA/ FIFO MII or RMII as AF MDIO as AF USB OTG HS DP, DM ULPI:CK, D[7:0], DIR, STP, NXT ID, VBUS, SOF DMA2 8 Streams FIFO ART ACCEL/ CACHE SRAM 112 KB CLK, NE [3:0], A[23:0], D[31:0], OEN, WEN, NBL[3:0], NL, NREG, NWAIT/IORDY, CD INTN, NIIS16 as AF RNG Camera interface HSYNC, VSYNC PUIXCLK, D[13:0] PHY USB OTG FS DP DM ID, VBUS, SOF FIFO AHB1 168 MHz PHY FIFO @VDDA @VDDA POR/PDR BOR Supply supervision @VDDA PVD Int POR reset XTAL 32 kHz MAN AGT RTC RC HS FCLK RC LS PWR interface IWDG @VBAT AWU Reset & clock control P L L1&2 PCLKx VDD = 1.8 to 3.6 V VSS VCAP1, VCPA2 Voltage regulator 3.3 to 1.2 V VDD Power managmt Backup register RTC_AF1 AHB bus-matrix 8S7M LS 2 channels as AF DAC1 DAC2 Flash up to 1 MB SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash External memory controller (FSMC) TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 SP3/I2S3 I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS bxCAN1 bxCAN2 SPI1 EXT IT. WKUP D-BUS FIFO FPU APB142 MHz (max) SRAM 16 KB CCM data RAM 64 KB AHB3 AHB2 168 MHz NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO I-BUS S-BUS DMA/ FIFO DMA1 8 Streams FIFO PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I TIM8 / PWM 16b 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 DAC2_OUT as AF 16b 16b SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX RX, TX as AF RX, TX as AF RX, TX as AF CTS, RTS as AF RX, TX as AF CTS, RTS as AF 1 channel as AF smcard irDA smcard irDA 16b 16b 16b 1 channel as AF 2 channels as AF 32b 16b 16b 32b 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF DMA1 AHB/APB1 LS OSC_IN OSC_OUT HCLKx XTAL OSC 4- 16MHz FIFO SP2/I2S2 NIORD, IOWR, INT[2:3] ADC3 ADC2 ADC1 Temperature sensor IF TIM9 16b TIM10 16b TIM11 16b smcard irDA USART1 irDA smcard USART6 APB2 84 MHz @VDD @VDD @VDDA DocID022152 Rev 4 19/185 STM32F405xx, STM32F407xx Description 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. Note: Cortex-M4F is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. Description STM32F405xx, STM32F407xx 20/185 DocID022152 Rev 4 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40x products embed: • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DocID022152 Rev 4 21/185 STM32F405xx, STM32F407xx Description Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S S0 S1 S2 S3 S4 S5 S6 S7 ICODE DCODE ACCEL Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB1 peripherals AHB2 FSMC Static MemCtl M0 M1 M2 M3 M4 M5 M6 I-bus D-bus S-bus DMA_PI DMA_MEM1 DMA_MEM2 DMA_P2 ETHERNET_M USB_HS_M ai18490c CCM data RAM 64-Kbyte APB1 APB2 peripherals Description STM32F405xx, STM32F407xx 22/185 DocID022152 Rev 4 2.2.9 Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL DocID022152 Rev 4 23/185 STM32F405xx, STM32F407xx Description clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 21: Power supply scheme for more details. Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Refer to Table 2 in order to identify the packages supporting this option. 2.2.15 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. Description STM32F405xx, STM32F407xx 24/185 DocID022152 Rev 4 The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. Figure 7. Power supply supervisor interconnection with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal. MS31383V3 NRST VDD PDR_ON External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V or 1.8 V (1) VDD Application reset signal (optional) DocID022152 Rev 4 25/185 STM32F405xx, STM32F407xx Description Figure 8. PDR_ON and NRST control with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.16 Voltage regulator The regulator has four operating modes: • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down • Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost) MS19009V6 VDD time PDR = 1.7 V or 1.8 V (1) time NRST PDR_ON PDR_ON Reset by other source than power supply supervisor Description STM32F405xx, STM32F407xx 26/185 DocID022152 Rev 4 Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 21: Power supply scheme When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. Figure 9. Regulator OFF ai18498V4 External VCAP_1/2 power supply supervisor Ext. reset controller active when VCAP_1/2 < Min V12 V12 VCAP_1 VCAP_2 BYPASS_REG VDD PA0 NRST Application reset signal (optional) VDD V12 DocID022152 Rev 4 27/185 STM32F405xx, STM32F407xx Description The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 14: General operating conditions). Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or OFFoff). 2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges. ai18491e VDD time Min V12 PDR = 1.7 V or 1.8 V (2) VCAP_1/VCAP_2 V12 NRST time Description STM32F405xx, STM32F407xx 28/185 DocID022152 Rev 4 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or offOFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability 2.2.18 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC VDD time Min V12 VCAP_1/VCAP_2 V12 PA0 asserted externally NRST time ai18492d PDR = 1.7 V or 1.8 V (2) Table 3. Regulator ON/OFF and internal reset ON/OFF availability Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP64 LQFP100 Yes No Yes No LQFP144 LQFP176 Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor WLCSP90 UFBGA176 Yes BYPASS_REG set to VSS Yes BYPASS_REG set to VDD DocID022152 Rev 4 29/185 STM32F405xx, STM32F407xx Description has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 μs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 2.2.19 Low-power modes The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V12 domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Description STM32F405xx, STM32F407xx 30/185 DocID022152 Rev 4 Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.20 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 2.2.21 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Advanced -control TIM1, TIM8 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 Yes 84 168 DocID022152 Rev 4 31/185 STM32F405xx, STM32F407xx Description Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. General purpose TIM2, TIM5 32-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM3, TIM4 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 84 168 TIM10 , TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 84 168 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 42 84 TIM13 , TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 42 84 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 42 84 Table 4. Timer feature comparison (continued) Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Description STM32F405xx, STM32F407xx 32/185 DocID022152 Rev 4 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. DocID022152 Rev 4 33/185 STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. 2.2.22 Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Description STM32F405xx, STM32F407xx 34/185 DocID022152 Rev 4 2.2.24 Serial peripheral interface (SPI) The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.25 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.2.26 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. Table 5. USART feature comparison USART name Standard features Modem (RTS/ CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s (oversampling by 16) Max. baud rate in Mbit/s (oversampling by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) USART6 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) DocID022152 Rev 4 35/185 STM32F405xx, STM32F407xx Description The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.27 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F407xx devices. The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx. The STM32F407xx includes the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time Description STM32F405xx, STM32F407xx 36/185 DocID022152 Rev 4 2.2.29 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID022152 Rev 4 37/185 STM32F405xx, STM32F407xx Description 2.2.32 Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image 2.2.33 Random number generator (RNG) All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. 2.2.35 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally Description STM32F405xx, STM32F407xx 38/185 DocID022152 Rev 4 connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.37 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.39 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40x through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID022152 Rev 4 39/185 STM32F405xx, STM32F407xx Pinouts and pin description 3 Pinouts and pin description Figure 12. STM32F40x LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14 PC15 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai18493b PC13 PH0 PH1 VSS Pinouts and pin description STM32F405xx, STM32F407xx 40/185 DocID022152 Rev 4 Figure 13. STM32F40x LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 PE3 PE4 PE5 PE6 VBAT PC14 PC15 VSS VDD PH0 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 VDD VSS VCAP_2 PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai18495c LQFP100 PC13 PH1 DocID022152 Rev 4 41/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 14. STM32F40x LQFP144 pinout VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 VDD PE3 VSS PE4 PE5 PA13 PE6 PA12 VBAT PA11 PC13 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 VDD PF5 VSS VSS PG8 VDD PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST VDD PC0 VSS PC1 PD13 PC2 PD12 PC3 PD11 VSSA VDD PD10 PD9 VREF+ PD8 VDDA PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 LQFP144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai18496b VCAP_2 VSS Pinouts and pin description STM32F405xx, STM32F407xx 42/185 DocID022152 Rev 4 Figure 15. STM32F40x LQFP176 pinout MS19916V3 PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PI7 PI6 PE2 PE3 PE4 PE5 PA13 PE6 PA12 VBAT PA11 PI8 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 PF5 PG8 PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST V PC0 V PC1 PD13 PC2 PD12 PC3 PD11 PD10 PD9 VREF+ PD8 PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 LQFP176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 PI4 PA15 PA14 PI3 PI2 PI5 140 139 138 137 136 135 134 133 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 88 81 82 83 84 85 86 87 PI1 PI0 PH15 PH14 PH13 PH12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 PC13 PI9 PI10 PI11 VSS PH2 PH3 VDD VSS VDD VDDA VSSA VDDA BYPASS_REG VDD VDD VSS VDD VCAP_1 VDD VSS VDD VCAP_2 VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD DocID022152 Rev 4 43/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 16. STM32F40x UFBGA176 ballout 1. This figure shows the package top view. ai18497b 1 2 3 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 VSS 4 5 6 7 8 Pinouts and pin description STM32F405xx, STM32F407xx 44/185 DocID022152 Rev 4 Figure 17. STM32F40x WLCSP90 ballout 1. This figure shows the package bump view. A VBAT PC13 PDR_ON PB4 PD7 PD4 PC12 B PC15 VDD PB7 PB3 PD6 PD2 PA15 C PA0 VSS PB6 PD5 PD1 PC11 PI0 D PC2 PB8 PA13 E PC3 VSS F PH1 PA1 G NRST H VSSA J PA2 PA 4 PA7 PB2 PE11 PB11 PB12 MS30402V1 1 PA14 PI1 PA12 PA10 PA9 PC0 PC9 PC8 PH0 PB13 PC6 PD14 PD12 PE8 PE12 BYPASS_ REG PD9 PD8 PE9 PB14 10 9 8 7 6 5 4 3 2 VDD PC14 VCAP_2 PA11 PB5 PD0 PC10 PA8 VSS VDD VSS VDD PC7 VDD PE10 PE14 VCAP_1 PD15 PE13 PE15 PD10 PD11 PA3 PA6 PB1 PB10 PB15 PB9 BOOT0 VDDA PA5 PB0 PE7 Table 6. Legend/abbreviations used in the pinout table Name Abbreviation Definition Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I/O Input / output pin I/O structure FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DocID022152 Rev 4 45/185 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 - - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 A10 6 6 C1 6 VBAT S - - - - D2 7 PI8 I/O FT (2)( 3) EVENTOUT RTC_TAMP1, RTC_TAMP2, RTC_TS 2 A9 7 7 D1 8 PC13 I/O FT (2) (3) EVENTOUT RTC_OUT, RTC_TAMP1, RTC_TS 3 B10 8 8 E1 9 PC14/OSC32_IN (PC14) I/O FT (2)( 3) EVENTOUT OSC32_IN(4) 4 B9 9 9 F1 10 PC15/ OSC32_OUT (PC15) I/O FT (2)( 3) EVENTOUT OSC32_OUT(4) - - - - D3 11 PI9 I/O FT CAN1_RX / EVENTOUT - - - - E3 12 PI10 I/O FT ETH_MII_RX_ER / EVENTOUT - - - - E4 13 PI11 I/O FT OTG_HS_ULPI_DIR / EVENTOUT - - - - F2 14 VSS S - - - - F3 15 VDD S - - - 10 E2 16 PF0 I/O FT FSMC_A0 / I2C2_SDA / EVENTOUT Pinouts and pin description STM32F405xx, STM32F407xx 46/185 DocID022152 Rev 4 - - - 11 H3 17 PF1 I/O FT FSMC_A1 / I2C2_SCL / EVENTOUT - - - 12 H2 18 PF2 I/O FT FSMC_A2 / I2C2_SMBA / EVENTOUT - - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9 - - - 14 J3 20 PF4 I/O FT (4) FSMC_A4/EVENTOUT ADC3_IN14 - - - 15 K3 21 PF5 I/O FT (4) FSMC_A5/EVENTOUT ADC3_IN15 - C9 10 16 G2 22 VSS S - B8 11 17 G3 23 VDD S - - - 18 K2 24 PF6 I/O FT (4) TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG / EVENTOUT ADC3_IN5 - - - 20 L3 26 PF8 I/O FT (4) TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8 5 F10 12 23 G1 29 PH0/OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 F9 13 24 H1 30 PH1/OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 G10 14 25 J1 31 NRST I/O RS T 8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/ EVENTOUT ADC123_IN10 9 - 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11 10 D10 17 28 M4 34 PC2 I/O FT (4) SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT ADC123_IN12 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 47/185 STM32F405xx, STM32F407xx Pinouts and pin description 11 E9 18 29 M5 35 PC3 I/O FT (4) SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_IN13 - - 19 30 G3 36 VDD S 12 H10 20 31 M1 37 VSSA S - - - - N1 - VREF– S - - 21 32 P1 38 VREF+ S 13 G9 22 33 R1 39 VDDA S 14 C10 23 34 N3 40 PA0/WKUP (PA0) I/O FT (5) USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT ADC123_IN0/WKUP(4 ) 15 F8 24 35 N2 41 PA1 I/O FT (4) USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT ADC123_IN1 16 J10 25 36 P2 42 PA2 I/O FT (4) USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT ADC123_IN2 - - - - F4 43 PH2 I/O FT ETH_MII_CRS/EVENTOU T - - - - G4 44 PH3 I/O FT ETH_MII_COL/EVENTOU T - - - - H4 45 PH4 I/O FT I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - - J4 46 PH5 I/O FT I2C2_SDA/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 48/185 DocID022152 Rev 4 17 H9 26 37 R2 47 PA3 I/O FT (4) USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 18 E5 27 38 - - VSS S D9 L4 48 BYPASS_REG I FT 19 E4 28 39 K4 49 VDD S 20 J9 29 40 N4 50 PA4 I/O TTa (4) SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC_OUT1 21 G8 30 41 P4 51 PA5 I/O TTa (4) SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CH1N/ EVENTOUT ADC12_IN5/DAC_OU T2 22 H8 31 42 P3 52 PA6 I/O FT (4) SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 23 J8 32 43 R3 53 PA7 I/O FT (4) SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT ADC12_IN7 24 - 33 44 N5 54 PC4 I/O FT (4) ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 - 34 45 P5 55 PC5 I/O FT (4) ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT ADC12_IN15 26 G7 35 46 R5 56 PB0 I/O FT (4) TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 49/185 STM32F405xx, STM32F407xx Pinouts and pin description 27 H7 36 47 R4 57 PB1 I/O FT (4) TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT ADC12_IN9 28 J7 37 48 M6 58 PB2/BOOT1 (PB2) I/O FT EVENTOUT - - - 49 R6 59 PF11 I/O FT DCMI_D12/ EVENTOUT - - - 50 P6 60 PF12 I/O FT FSMC_A6/ EVENTOUT - - - 51 M8 61 VSS S - - - 52 N8 62 VDD S - - - 53 N6 63 PF13 I/O FT FSMC_A7/ EVENTOUT - - - 54 R7 64 PF14 I/O FT FSMC_A8/ EVENTOUT - - - 55 P7 65 PF15 I/O FT FSMC_A9/ EVENTOUT - - - 56 N7 66 PG0 I/O FT FSMC_A10/ EVENTOUT - - - 57 M7 67 PG1 I/O FT FSMC_A11/ EVENTOUT - G6 38 58 R8 68 PE7 I/O FT FSMC_D4/TIM1_ETR/ EVENTOUT - H6 39 59 P8 69 PE8 I/O FT FSMC_D5/ TIM1_CH1N/ EVENTOUT - J6 40 60 P9 70 PE9 I/O FT FSMC_D6/TIM1_CH1/ EVENTOUT - - - 61 M9 71 VSS S - - - 62 N9 72 VDD S - F6 41 63 R9 73 PE10 I/O FT FSMC_D7/TIM1_CH2N/ EVENTOUT - J5 42 64 P10 74 PE11 I/O FT FSMC_D8/TIM1_CH2/ EVENTOUT - H5 43 65 R10 75 PE12 I/O FT FSMC_D9/TIM1_CH3N/ EVENTOUT - G5 44 66 N11 76 PE13 I/O FT FSMC_D10/TIM1_CH3/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 50/185 DocID022152 Rev 4 - F5 45 67 P11 77 PE14 I/O FT FSMC_D11/TIM1_CH4/ EVENTOUT - G4 46 68 R11 78 PE15 I/O FT FSMC_D12/TIM1_BKIN/ EVENTOUT 29 H4 47 69 R12 79 PB10 I/O FT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT 30 J4 48 70 R13 80 PB11 I/O FT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT 31 F4 49 71 M10 81 VCAP_1 S 32 - 50 72 N10 82 VDD S - - - - M11 83 PH6 I/O FT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - - N12 84 PH7 I/O FT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - - M12 85 PH8 I/O FT I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - - M13 86 PH9 I/O FT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - - L13 87 PH10 I/O FT TIM5_CH1 / DCMI_D1/ EVENTOUT - - - - L12 88 PH11 I/O FT TIM5_CH2 / DCMI_D2/ EVENTOUT - - - - K12 89 PH12 I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT - - - - H12 90 VSS S - - - - J12 91 VDD S Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 51/185 STM32F405xx, STM32F407xx Pinouts and pin description 33 J3 51 73 P12 92 PB12 I/O FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT 34 J1 52 74 P13 93 PB13 I/O FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT OTG_HS_VBUS 35 J2 53 75 R14 94 PB14 I/O FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT 36 H1 54 76 R15 95 PB15 I/O FT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT RTC_REFIN - H2 55 77 P15 96 PD8 I/O FT FSMC_D13 / USART3_TX/ EVENTOUT - H3 56 78 P14 97 PD9 I/O FT FSMC_D14 / USART3_RX/ EVENTOUT - G3 57 79 N15 98 PD10 I/O FT FSMC_D15 / USART3_CK/ EVENTOUT - G1 58 80 N14 99 PD11 I/O FT FSMC_CLE / FSMC_A16/USART3_CT S/ EVENTOUT - G2 59 81 N13 100 PD12 I/O FT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 52/185 DocID022152 Rev 4 - - 60 82 M15 101 PD13 I/O FT FSMC_A18/TIM4_CH2/ EVENTOUT - - - 83 - 102 VSS S - - - 84 J13 103 VDD S - F2 61 85 M14 104 PD14 I/O FT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT - F1 62 86 L14 105 PD15 I/O FT FSMC_D1/TIM4_CH4/ EVENTOUT - - - 87 L15 106 PG2 I/O FT FSMC_A12/ EVENTOUT - - - 88 K15 107 PG3 I/O FT FSMC_A13/ EVENTOUT - - - 89 K14 108 PG4 I/O FT FSMC_A14/ EVENTOUT - - - 90 K13 109 PG5 I/O FT FSMC_A15/ EVENTOUT - - - 91 J15 110 PG6 I/O FT FSMC_INT2/ EVENTOUT - - - 92 J14 111 PG7 I/O FT FSMC_INT3 /USART6_CK/ EVENTOUT - - - 93 H14 112 PG8 I/O FT USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - - 94 G12 113 VSS S - - - 95 H13 114 VDD S 37 F3 63 96 H15 115 PC6 I/O FT I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT 38 E1 64 97 G15 116 PC7 I/O FT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 E2 65 98 G14 117 PC8 I/O FT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 53/185 STM32F405xx, STM32F407xx Pinouts and pin description 40 E3 66 99 F14 118 PC9 I/O FT I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 41 D1 67 100 F15 119 PA8 I/O FT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 D2 68 101 E15 120 PA9 I/O FT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT OTG_FS_VBUS 43 D3 69 102 D15 121 PA10 I/O FT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT 44 C1 70 103 C15 122 PA11 I/O FT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 45 C2 71 104 B15 123 PA12 I/O FT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 D4 72 105 A15 124 PA13 (JTMS-SWDIO) I/O FT JTMS-SWDIO/ EVENTOUT 47 B1 73 106 F13 125 VCAP_2 S - E7 74 107 F12 126 VSS S 48 E6 75 108 G13 127 VDD S - - - - E12 128 PH13 I/O FT TIM8_CH1N / CAN1_TX/ EVENTOUT - - - - E13 129 PH14 I/O FT TIM8_CH2N / DCMI_D4/ EVENTOUT - - - - D13 130 PH15 I/O FT TIM8_CH3N / DCMI_D11/ EVENTOUT - C3 - - E14 131 PI0 I/O FT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 54/185 DocID022152 Rev 4 - B2 - - D14 132 PI1 I/O FT SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT - - - - C14 133 PI2 I/O FT TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT - - - - C13 134 PI3 I/O FT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - - D9 135 VSS S - - - - C9 136 VDD S 49 A2 76 109 A14 137 PA14 (JTCK/SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 50 B3 77 110 A13 138 PA15 (JTDI) I/O FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ET R / SPI1_NSS / EVENTOUT 51 D5 78 111 B14 139 PC10 I/O FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT 52 C4 79 112 B13 140 PC11 I/O FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT 53 A3 80 113 A12 141 PC12 I/O FT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT - D6 81 114 B12 142 PD0 I/O FT FSMC_D2/CAN1_RX/ EVENTOUT - C5 82 115 C12 143 PD1 I/O FT FSMC_D3 / CAN1_TX/ EVENTOUT 54 B4 83 116 D12 144 PD2 I/O FT TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 55/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 84 117 D11 145 PD3 I/O FT FSMC_CLK/ USART2_CTS/ EVENTOUT - A4 85 118 D10 146 PD4 I/O FT FSMC_NOE/ USART2_RTS/ EVENTOUT - C6 86 119 C11 147 PD5 I/O FT FSMC_NWE/USART2_TX / EVENTOUT - - - 120 D8 148 VSS S - - - 121 C8 149 VDD S - B5 87 122 B11 150 PD6 I/O FT FSMC_NWAIT/ USART2_RX/ EVENTOUT - A5 88 123 A11 151 PD7 I/O FT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT - - - 124 C10 152 PG9 I/O FT USART6_RX / FSMC_NE2/FSMC_NCE3 / EVENTOUT - - - 125 B10 153 PG10 I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT - - - 126 B9 154 PG11 I/O FT FSMC_NCE4_2 / ETH_MII_TX_EN/ ETH _RMII_TX_EN/ EVENTOUT - - - 127 B8 155 PG12 I/O FT FSMC_NE4 / USART6_RTS/ EVENTOUT - - - 128 A8 156 PG13 I/O FT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT - - - 129 A7 157 PG14 I/O FT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 56/185 DocID022152 Rev 4 - E8 - 130 D7 158 VSS S - F7 - 131 C7 159 VDD S - - - 132 B7 160 PG15 I/O FT USART6_CTS / DCMI_D13/ EVENTOUT 55 B6 89 133 A10 161 PB3 (JTDO/ TRACESWO) I/O FT JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT 56 A6 90 134 A9 162 PB4 (NJTRST) I/O FT NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT 57 D7 91 135 A6 163 PB5 I/O FT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH 2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT 58 C7 92 136 B6 164 PB6 I/O FT I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT 59 B7 93 137 B5 165 PB7 I/O FT I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT 60 A7 94 138 D6 166 BOOT0 I B VPP 61 D8 95 139 A5 167 PB8 I/O FT TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT 62 C8 96 140 B4 168 PB9 I/O FT SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 57/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 97 141 A4 169 PE0 I/O FT TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - - 98 142 A3 170 PE1 I/O FT FSMC_NBL1 / DCMI_D3/ EVENTOUT 63 - 99 - D5 - VSS S - A8 - 143 C6 171 PDR_ON I FT 64 A1 10 0 144 C5 172 VDD S - - - - D4 173 PI4 I/O FT TIM8_BKIN / DCMI_D5/ EVENTOUT - - - - C4 174 PI5 I/O FT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - - C3 175 PI6 I/O FT TIM8_CH2 / DCMI_D6/ EVENTOUT - - - - C2 176 PI7 I/O FT TIM8_CH3 / DCMI_D7/ EVENTOUT 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Table 8. FSMC pin definition Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PE2 A23 A23 Yes PE3 A19 A19 Yes Pinouts and pin description STM32F405xx, STM32F407xx 58/185 DocID022152 Rev 4 PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 - - PF1 A1 A1 - - PF2 A2 A2 - - PF3 A3 A3 - - PF4 A4 A4 - - PF5 A5 A5 - - PF6 NIORD - - PF7 NREG - - PF8 NIOWR - - PF9 CD - - PF10 INTR - - PF12 A6 A6 - - PF13 A7 A7 - - PF14 A8 A8 - - PF15 A9 A9 - - PG0 A10 A10 - - PG1 A11 - - PE7 D4 D4 DA4 D4 Yes Yes PE8 D5 D5 DA5 D5 Yes Yes PE9 D6 D6 DA6 D6 Yes Yes PE10 D7 D7 DA7 D7 Yes Yes PE11 D8 D8 DA8 D8 Yes Yes PE12 D9 D9 DA9 D9 Yes Yes PE13 D10 D10 DA10 D10 Yes Yes PE14 D11 D11 DA11 D11 Yes Yes PE15 D12 D12 DA12 D12 Yes Yes PD8 D13 D13 DA13 D13 Yes Yes PD9 D14 D14 DA14 D14 Yes Yes PD10 D15 D15 DA15 D15 Yes Yes PD11 A16 A16 CLE Yes Yes Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit DocID022152 Rev 4 59/185 STM32F405xx, STM32F407xx Pinouts and pin description PD12 A17 A17 ALE Yes Yes PD13 A18 A18 Yes PD14 D0 D0 DA0 D0 Yes Yes PD15 D1 D1 DA1 D1 Yes Yes PG2 A12 - - PG3 A13 - - PG4 A14 - - PG5 A15 - - PG6 INT2 - - PG7 INT3 - - PD0 D2 D2 DA2 D2 Yes Yes PD1 D3 D3 DA3 D3 Yes Yes PD3 CLK CLK Yes PD4 NOE NOE NOE NOE Yes Yes PD5 NWE NWE NWE NWE Yes Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes Yes PD7 NE1 NE1 NCE2 Yes Yes PG9 NE2 NE2 NCE3 - - PG10 NCE4_1 NE3 NE3 - - PG11 NCE4_2 - - PG12 NE4 NE4 - - PG13 A24 A24 - - PG14 A25 A25 - - PB7 NADV NADV Yes Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column. 2. Ports F and G are not available in devices delivered in 100-pin packages. Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit Pinouts and pin description STM32F405xx, STM32F407xx 60/185 DocID022152 Rev 4 Table 9. Alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port A PA0 TIM2_CH1_E TR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII__REF _CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_ D0 ETH _MII_COL EVENTOUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK OTG_HS_SO F DCMI_HSYN C EVENTOUT PA5 TIM2_CH1_E TR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_ CK EVENTOUT PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT PA9 TIM1_CH2 I2C3_SMB A USART1_TX DCMI_D0 EVENTOUT PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMSSWDIO EVENTOUT PA14 JTCKSWCLK EVENTOUT PA15 JTDI TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS/ I2S3_WS EVENTOUT STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 61/185 Port B PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_ D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_ D2 ETH _MII_RXD3 EVENTOUT PB2 EVENTOUT PB3 JTDO/ TRACES WO TIM2_CH2 SPI1_SCK SPI3_SCK I2S3_CK EVENTOUT PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO I2S3ext_SD EVENTOUT PB5 TIM3_CH2 I2C1_SMB A SPI1_MOSI SPI3_MOSI I2S3_SD CAN2_RX OTG_HS_ULPI_ D7 ETH _PPS_OUT DCMI_D10 EVENTOUT PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYN C EVENTOUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS I2S2_WS CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT PB10 TIM2_CH3 I2C2_SCL SPI2_SCK I2S2_CK USART3_TX OTG_HS_ULPI_ D3 ETH_ MII_RX_ER EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_ D4 ETH _MII_TX_EN ETH _RMII_TX_EN EVENTOUT PB12 TIM1_BKIN I2C2_SMB A SPI2_NSS I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_ D5 ETH _MII_TXD0 ETH _RMII_TXD0 OTG_HS_ID EVENTOUT PB13 TIM1_CH1N SPI2_SCK I2S2_CK USART3_CTS CAN2_TX OTG_HS_ULPI_ D6 ETH _MII_TXD1 ETH _RMII_TXD1 EVENTOUT PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO I2S2ext_SD USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT PB15 RTC_ REFIN TIM1_CH3N TIM8_CH3N SPI2_MOSI I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 62/185 DocID022152 Rev 4 Port C PC0 OTG_HS_ULPI_ STP EVENTOUT PC1 ETH_MDC EVENTOUT PC2 SPI2_MISO I2S2ext_SD OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT PC3 SPI2_MOSI I2S2_SD OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN SDIO_D1 DCMI_D3 EVENTOUT PC10 SPI3_SCK/ I2S3_CK USART3_TX/ UART4_TX SDIO_D2 DCMI_D8 EVENTOUT PC11 I2S3ext_SD SPI3_MISO/ USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT PC12 SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 63/185 Port D PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 64/185 DocID022152 Rev 4 Port E PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT PE1 FSMC_NBL1 DCMI_D3 EVENTOUT PE2 TRACECL K ETH _MII_TXD3 FSMC_A23 EVENTOUT PE3 TRACED0 FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 65/185 Port F PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_ SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT PF8 TIM13_CH1 FSMC_ NIOWR EVENTOUT PF9 TIM14_CH1 FSMC_CD EVENTOUT PF10 FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 66/185 DocID022152 Rev 4 Port G PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT PG7 USART6_CK FSMC_INT3 EVENTOUT PG8 USART6_ RTS ETH _PPS_OUT EVENTOUT PG9 USART6_RX FSMC_NE2/ FSMC_NCE3 EVENTOUT PG10 FSMC_ NCE4_1/ FSMC_NE3 EVENTOUT PG11 ETH _MII_TX_EN ETH _RMII_ TX_EN FSMC_NCE4_ 2 EVENTOUT PG12 USART6_ RTS FSMC_NE4 EVENTOUT PG13 UART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 FSMC_A24 EVENTOUT PG14 USART6_TX ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A25 EVENTOUT PG15 USART6_ CTS DCMI_D13 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 67/185 Port H PH0 EVENTOUT PH1 EVENTOUT PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT PH4 I2C2_SCL OTG_HS_ULPI_ NXT EVENTOUT PH5 I2C2_SDA EVENTOUT PH6 I2C2_SMB A TIM12_CH1 ETH _MII_RXD2 EVENTOUT PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT PH8 I2C3_SDA DCMI_HSYN C EVENTOUT PH9 I2C3_SMB A TIM12_CH2 DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TIM8_CH1N CAN1_TX EVENTOUT PH14 TIM8_CH2N DCMI_D4 EVENTOUT PH15 TIM8_CH3N DCMI_D11 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 68/185 DocID022152 Rev 4 Port I PI0 TIM5_CH4 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT PI1 SPI2_SCK I2S2_CK DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO I2S2ext_SD DCMI_D9 EVENTOUT PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_ VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT PI8 EVENTOUT PI9 CAN1_RX EVENTOUT PI10 ETH _MII_RX_ER EVENTOUT PI11 OTG_HS_ULPI_ DIR EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI DocID022152 Rev 4 69/185 STM32F405xx, STM32F407xx Memory mapping 4 Memory mapping The memory map is shown in Figure 18. Figure 18. STM32F40x memory map 512-Mbyte block 7 Cortex-M4's internal peripherals 512-Mbyte block 6 Not used 512-Mbyte block 5 FSMC registers 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 512-Mbyte block 1 SRAM 0x0000 0000 0x1FFF FFFF 0x2000 0000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 0x6000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xFFFF FFFF 512-Mbyte block 0 Code Flash 0x0810 0000 - 0x0FFF FFFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1FFF C000 - 0x1FFF C007 0x0800 0000 - 0x080F FFFF 0x0010 0000 - 0x07FF FFFF 0x0000 0000 - 0x000F FFFF System memory + OTP Reserved Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins SRAM (16 KB aliased by bit-banding) Reserved 0x2000 0000 - 0x2001 BFFF 0x2001 C000 - 0x2001 FFFF 0x2002 0000 - 0x3FFF FFFF 0x4000 0000 Reserved 0x4000 7FFF 0x4000 7800 - 0x4000 FFFF 0x4001 0000 0x4001 57FF 0x4002 000 Reserved 0x5006 0C00 - 0x5FFF FFFF 0x6000 0000 AHB3 0xA000 0FFF 0xA000 1000 - 0xDFFF FFFF ai18513f Option Bytes Reserved 0x4001 5800 - 0x4001 FFFF 0x5006 0BFF AHB2 0x5000 0000 Reserved 0x4008 0000 - 0x4FFF FFFF AHB1 SRAM (112 KB aliased by bit-banding) Reserved 0x1FFF C008 - 0x1FFF FFFF Reserved 0x1FFF 7A10 - 0x1FFF 7FFF CCM data RAM (64 KB data SRAM) 0x1000 0000 - 0x1000 FFFF Reserved 0x1001 0000 - 0x1FFE FFFF Reserved APB2 0x4007 FFFF APB1 CORTEX-M4 internal peripherals 0xE000 0000 - 0xE00F FFFF Reserved 0xE010 0000 - 0xFFFF FFFF Memory mapping STM32F405xx, STM32F407xx 70/185 DocID022152 Rev 4 Table 10. STM32F40x register boundary addresses Bus Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 1000 - 0xDFFF FFFF Reserved AHB3 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF FSMC bank 4 0x8000 0000 - 0x8FFF FFFF FSMC bank 3 0x7000 0000 - 0x7FFF FFFF FSMC bank 2 0x6000 0000 - 0x6FFF FFFF FSMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved AHB2 0x5006 0800 - 0x5006 0BFF RNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4008 0000- 0x4FFF FFFF Reserved DocID022152 Rev 4 71/185 STM32F405xx, STM32F407xx Memory mapping AHB1 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 9400 - 0x4003 FFFF Reserved 0x4002 9000 - 0x4002 93FF ETHERNET MAC 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 0x4001 5800- 0x4001 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Memory mapping STM32F405xx, STM32F407xx 72/185 DocID022152 Rev 4 APB2 0x4001 4C00 - 0x4001 57FF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7800- 0x4000 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral DocID022152 Rev 4 73/185 STM32F405xx, STM32F407xx Memory mapping APB1 0x4000 7800 - 0x4000 7FFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Electrical characteristics STM32F405xx, STM32F407xx 74/185 DocID022152 Rev 4 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Pin input voltage MS19011V1 C = 50 pF STM32F pin OSC_OUT (Hi-Z when using HSE or LSE) MS19010V1 STM32F pin VIN OSC_OUT (Hi-Z when using HSE or LSE) DocID022152 Rev 4 75/185 STM32F405xx, STM32F407xx Electrical characteristics 5.1.6 Power supply scheme Figure 21. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15: Power supply supervisor. 3. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 μF ceramic capacitor must be connected to one of the VDD pin. 5. VDDA=VDD and VSSA=VSS. MS19911V2 Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Kernel logic (CPU, digital & RAM) Analog: RCs, PLL,.. Power switch VBAT GPIOs OUT IN 15 × 100 nF + 1 × 4.7 μF VBAT = 1.65 to 3.6V Voltage regulator VDDA ADC Level shifter IO Logic VDD 100 nF + 1 μF Flash memory VCAP_1 2 × 2.2 μF VCAP_2 BYPASS_REG PDR_ON Reset controller VDD 1/2/...14/15 VSS 1/2/...14/15 VDD VREF+ VREFVSSA VREF 100 nF + 1 μF Electrical characteristics STM32F405xx, STM32F407xx 76/185 DocID022152 Rev 4 5.1.7 Current consumption measurement Figure 22. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 VBAT VDD VDDA IDD_VBAT IDD Table 11. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA, VDD)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V VIN Input voltage on five-volt tolerant pin(2) 2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current. VSS–0.3 VDD+4 Input voltage on any other pin VSS–0.3 4.0 |ΔVDDx| Variations between different VDD power pins - 50 mV |VSSX − VSS| Variations between all the different ground pins - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) DocID022152 Rev 4 77/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 12. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 150 mA IVSS Total current out of VSS ground lines (sink)(1) 150 IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IINJ(PIN) (2) 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. Injected current on five-volt tolerant I/O(3) 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 6. In this case HCLK = system clock/2. Electrical characteristics STM32F405xx, STM32F407xx 84/185 DocID022152 Rev 4 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Symbol Parameter Conditions fHCLK Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Run mode External clock(2), all peripherals enabled(3)(4) 168 MHz 93 109 117 mA 144 MHz 76 89 96 120 MHz 67 79 86 90 MHz 53 65 73 60 MHz 37 49 56 30 MHz 20 32 39 25 MHz 16 27 35 16 MHz 11 23 30 8 MHz 6 18 25 4 MHz 4 16 23 2 MHz 3 15 22 External clock(2), all peripherals disabled(3)(4) 168 MHz 46 61 69 144 MHz 40 52 60 120 MHz 37 48 56 90 MHz 30 42 50 60 MHz 22 33 41 30 MHz 12 24 31 25 MHz 10 21 29 16 MHz 7 19 26 8 MHz 4 16 23 4 MHz 3 15 22 2 MHz 2 14 21 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. DocID022152 Rev 4 85/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON MS19974V1 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45 °C 0 °C 25 °C 55 °C 85 °C 105 °C MS19975V1 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C Electrical characteristics STM32F405xx, STM32F407xx 86/185 DocID022152 Rev 4 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON MS19976V1 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C MS19977V1 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C DocID022152 Rev 4 87/185 STM32F405xx, STM32F407xx Electrical characteristics Table 22. Typical and maximum current consumption in Sleep mode Symbol Parameter Conditions fHCLK Typ Max(1) T Unit A = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Sleep mode External clock(2), all peripherals enabled(3) 168 MHz 59 77 84 mA 144 MHz 46 61 67 120 MHz 38 53 60 90 MHz 30 44 51 60 MHz 20 34 41 30 MHz 11 24 31 25 MHz 8 21 28 16 MHz 6 18 25 8 MHz 3 16 23 4 MHz 2 15 22 2 MHz 2 14 21 External clock(2), all peripherals disabled 168 MHz 12 27 35 144 MHz 9 22 29 120 MHz 8 20 28 90 MHz 7 19 26 60 MHz 5 17 24 30 MHz 3 16 23 25 MHz 2 15 22 16 MHz 2 14 21 8 MHz 1 14 21 4 MHz 1 13 21 2 MHz 1 13 21 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). Electrical characteristics STM32F405xx, STM32F407xx 88/185 DocID022152 Rev 4 Table 23. Typical and maximum current consumptions in Stop mode Symbol Parameter Conditions Typ Max T Unit A = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_STOP Supply current in Stop mode with main regulator in Run mode Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.45 1.5 11.00 20.00 mA Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.40 1.5 11.00 20.00 Supply current in Stop mode with main regulator in Low Power mode Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.31 1.1 8.00 15.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.28 1.1 8.00 15.00 Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C Unit TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V VDD = 3.6 V IDD_STBY Supply current in Standby mode Backup SRAM ON, lowspeed oscillator and RTC ON 3.0 3.4 4.0 20 36 μA Backup SRAM OFF, lowspeed oscillator and RTC ON 2.4 2.7 3.3 16 32 Backup SRAM ON, RTC OFF 2.4 2.6 3.0 12.5 24.8 Backup SRAM OFF, RTC OFF 1.7 1.9 2.2 9.8 19.2 1. Based on characterization, not tested in production. DocID022152 Rev 4 89/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) Table 25. Typical and maximum current consumptions in VBAT mode Symbol Parameter Conditions Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C VBAT = 1.8 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V IDD_VBA T Backup domain supply current Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 6 11 μA Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 3 5 Backup SRAM ON, RTC OFF 0.79 0.81 0.86 5 10 Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 2 4 1. Based on characterization, not tested in production. MS19990V1 0 0.5 1 1.5 2 2.5 3 3.5 0 10 20 30 40 50 60 70 80 90 100 IVBAT in (μA) Temperature in (°C) 1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V Electrical characteristics STM32F405xx, STM32F407xx 90/185 DocID022152 Rev 4 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 47: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 27: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU MS19991V1 0 1 2 3 4 5 6 0 10 20 30 40 50 60 70 80 90 100 IVBAT in (μA) Temperature in (°C) 1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V DocID022152 Rev 4 91/185 STM32F405xx, STM32F407xx Electrical characteristics supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. ISW = VDD × fSW × C Electrical characteristics STM32F405xx, STM32F407xx 92/185 DocID022152 Rev 4 Table 26. Switching output I/O current consumption Symbol Parameter Conditions(1) I/O toggling frequency (fSW) Typ Unit IDDIO I/O switching current VDD = 3.3 V(2) C = CINT 2 MHz 0.02 mA 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.82 60 MHz -(3) 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 2. This test is performed by cutting the LQFP package pin (pad removal). 3. At 60 MHz, C maximum load is specified 30 pF. DocID022152 Rev 4 93/185 STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned • The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz. • The code is running from Flash memory and the Flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2. • ART accelerator and Cache off. • The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) • When the peripherals are enabled: HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. • The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. Table 27. Peripheral current consumption Peripheral(1) 168 MHz 144 MHz Unit AHB1 GPIO A 0.49 0.36 mA GPIO B 0.45 0.33 GPIO C 0.45 0.34 GPIO D 0.45 0.34 GPIO E 0.47 0.35 GPIO F 0.45 0.33 GPIO G 0.44 0.33 GPIO H 0.45 0.34 GPIO I 0.44 0.33 OTG_HS + ULPI 4.57 3.55 CRC 0.07 0.06 BKPSRAM 0.11 0.08 DMA1 6.15 4.75 DMA2 6.24 4.8 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 3.28 2.54 AHB2 OTG_FS 4.59 3.69 mA DCMI 1.04 0.80 Electrical characteristics STM32F405xx, STM32F407xx 94/185 DocID022152 Rev 4 AHB3 FSMC 2.18 1.67 mA APB1 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 I2C3 0.18 0.13 SPI2/I2S2(2) 0.17/0.16 0.13/0.12 SPI3/I2S3(2) 0.16/0.14 0.12/0.12 CAN1 0.27 0.21 CAN2 0.26 0.20 DAC 0.14 0.10 DAC channel 1(3) 0.91 0.89 DAC channel 2(4) 0.91 0.89 DAC channel 1 and 2(3)(4) 1.69 1.68 WWDG 0.04 0.04 Table 27. Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz Unit DocID022152 Rev 4 95/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 28 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. APB2 SDIO 0.64 0.54 mA TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 ADC1(5) 2.20 2.10 ADC2(5) 2.04 1.93 ADC3(5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 1. HSE oscillator with 4 MHz crystal and PLL are ON. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 bit is set in DAC_CR register. 4. EN2 bit is set in DAC_CR register. 5. ADON bit set in ADC_CR2 register. Table 27. Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz Unit Table 28. Low-power mode wakeup timings Symbol Parameter Min(1) Typ(1) Max(1) Unit tWUSLEEP (2) Wakeup from Sleep mode - 1 - μs tWUSTOP (2) Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 μs Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - tWUSTDBY (2)(3) Wakeup from Standby mode 260 375 480 μs 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. Electrical characteristics STM32F405xx, STM32F407xx 96/185 DocID022152 Rev 4 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 29 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Low-speed external user clock generated from an external source The characteristics given in Table 30 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 29. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext External user clock source frequency(1) 1 - 50 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD V VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 1. Guaranteed by design, not tested in production. 5 - - ns tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 10 Cin(HSE) OSC_IN input capacitance(1) - 5 - pF DuCy(HSE) Duty cycle 45 - 55 % IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA Table 30. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User External clock source frequency(1) - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD V VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - ns tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) OSC32_IN input capacitance(1) - 5 - pF DuCy(LSE) Duty cycle 30 - 70 % IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA 1. Guaranteed by design, not tested in production. DocID022152 Rev 4 97/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 30. High-speed external clock source AC timing diagram Figure 31. Low-speed external clock source AC timing diagram High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 31. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai17528 OSC_IN External STM32F clock source VHSEH tf(HSE) tW(HSE) IL 90% 10% THSE tr(HSE) tW(HSE) t fHSE_ext VHSEL ai17529 External OSC32_IN STM32F clock source VLSEH tf(LSE) tW(LSE) IL 90% 10% TLSE tr(LSE) tW(LSE) t fLSE_ext VLSEL Electrical characteristics STM32F405xx, STM32F407xx 98/185 DocID022152 Rev 4 For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 32. Typical application with an 8 MHz crystal 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 31. HSE 4-26 MHz oscillator characteristics(1) (2) 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - kΩ IDD HSE current consumption VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - μA VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - gm Oscillator transconductance Startup 5 - - mA/V tSU(HSE (3) 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Startup time VDD is stabilized - 2 - ms ai17530 OSC_OUT OSC_IN fHSE CL1 RF STM32F 8 MHz resonator Resonator with integrated capacitors Bias controlled gain CL2 REXT(1) DocID022152 Rev 4 99/185 STM32F405xx, STM32F407xx Electrical characteristics Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 33. Typical application with a 32.768 kHz crystal 5.3.9 Internal clock source characteristics The parameters given in Table 33 and Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) 1. Guaranteed by design, not tested in production. Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 μA gm Oscillator Transconductance 2.8 - - μA/V tSU(LSE) (2) 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time VDD is stabilized - 2 - s ai17531 OSC32_OUT OSC32_IN fLSE CL1 RF STM32F 32.768 kHz resonator Resonator with integrated capacitors Bias controlled gain CL2 Table 33. HSI oscillator characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency - 16 - MHz ACCHSI Accuracy of the HSI oscillator User-trimmed with the RCC_CR register - - 1 % Factorycalibrated TA = –40 to 105 °C(2) –8 - 4.5 % TA = –10 to 85 °C(2) –4 - 4 % TA = 25 °C –1 - 1 % tsu(HSI) (3) HSI oscillator startup time - 2.2 4 μs IDD(HSI) HSI oscillator power consumption - 60 80 μA Electrical characteristics STM32F405xx, STM32F407xx 100/185 DocID022152 Rev 4 Low-speed internal (LSI) RC oscillator Figure 34. ACCLSI versus temperature 5.3.10 PLL characteristics The parameters given in Table 35 and Table 36 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Table 34. LSI oscillator characteristics (1) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. Symbol Parameter Min Typ Max Unit fLSI (2) 2. Based on characterization, not tested in production. Frequency 17 32 47 kHz tsu(LSI) (3) 3. Guaranteed by design, not tested in production. LSI oscillator startup time - 15 40 μs IDD(LSI) (3) LSI oscillator power consumption - 0.4 0.6 μA MS19013V1 -40 -30 -20 -10 0 10 20 30 40 50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Normalized deviati on (%) Temperature (°C) max avg min DocID022152 Rev 4 101/185 STM32F405xx, STM32F407xx Electrical characteristics Table 35. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) 0.95(2) 1 2.10 MHz fPLL_OUT PLL multiplier output clock 24 - 168 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - 48 75 MHz fVCO_OUT PLL VCO output 192 - 432 MHz tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 120 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL) (4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL) (4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 1 2.10 MHz fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz fVCO_OUT PLLI2S VCO output 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Electrical characteristics STM32F405xx, STM32F407xx 102/185 DocID022152 Rev 4 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 43: EMI characteristics). It is available only on the main PLL. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: Jitter(3) Master I2S clock jitter Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S) (4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S) (4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 37. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - 215−1 - 1. Guaranteed by design, not tested in production. MODEPER = round[fPLL_IN ⁄ (4 × fMod)] MODEPER round 106 4 10 3 = [ ⁄ ( × )] = 250 DocID022152 Rev 4 103/185 STM32F405xx, STM32F407xx Electrical characteristics Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: As a result: Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 35. PLL output clock waveforms in center spread mode INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)] INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)% mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN) mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak) Frequency (PLL_OUT) Time F0 tmode md ai17291 md 2 x tmode Electrical characteristics STM32F405xx, STM32F407xx 104/185 DocID022152 Rev 4 Figure 36. PLL output clock waveforms in down spread mode 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Time ai17292 Frequency (PLL_OUT) F0 2 x md tmode 2 x tmode Table 38. Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit IDD Supply current Write / Erase 8-bit mode, VDD = 1.8 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - mA Write / Erase 32-bit mode, VDD = 3.3 V - 12 - Table 39. Flash memory programming Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog Word programming time Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) μs tERASE16KB Sector (16 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism ms (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 DocID022152 Rev 4 105/185 STM32F405xx, STM32F407xx Electrical characteristics tERASE64KB Sector (64 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism ms (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 tERASE128KB Sector (128 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism s (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 tME Mass erase time Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism s (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 Vprog Programming voltage 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V 1. Based on characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. Table 39. Flash memory programming (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit Electrical characteristics STM32F405xx, STM32F407xx 106/185 DocID022152 Rev 4 5.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. Table 40. Flash memory programming with VPP Symbol Parameter Conditions Min(1) Typ Max(1) 1. Guaranteed by design, not tested in production. Unit tprog Double word programming TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V - 16 100(2) 2. The maximum programming time is measured after 100K erase operations. μs tERASE16KB Sector (16 KB) erase time - 230 - tERASE64KB Sector (64 KB) erase time - 490 - ms tERASE128KB Sector (128 KB) erase time - 875 - tME Mass erase time - 6.9 - s Vprog Programming voltage 2.7 - 3.6 V VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA tVPP (3) 3. VPP should only be connected during programming/erasing. Cumulative time during which VPP is applied - - 1 hour Table 41. Flash memory endurance and data retention Symbol Parameter Conditions Value Unit Min(1) 1. Based on characterization, not tested in production. NEND Endurance TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 kcycles tRET Data retention 1 kcycle(2) at TA = 85 °C 2. Cycling performed over the whole temperature range. 30 1 kcycle(2) at TA = 105 °C 10 Years 10 kcycles(2) at TA = 55 °C 20 DocID022152 Rev 4 107/185 STM32F405xx, STM32F407xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 42. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 4A Electrical characteristics STM32F405xx, STM32F407xx 108/185 DocID022152 Rev 4 5.3.14 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 43. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 25/168 MHz SEMI Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator enabled 0.1 to 30 MHz 32 30 to 130 MHz 25 dBμV 130 MHz to 1GHz 29 SAE EMI Level 4 - VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator and PLL spread spectrum enabled 0.1 to 30 MHz 19 30 to 130 MHz 16 dBμV 130 MHz to 1GHz 18 SAE EMI level 3.5 - Table 44. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to JESD22-A114 2 2000(2) V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-C101 II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. DocID022152 Rev 4 109/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 uA/+0 uA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 46. 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 45. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A Table 46. I/O current injection susceptibility Symbol Description Functional susceptibility Negative Unit injection Positive injection IINJ (1) 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Injected current on all FT pins –5 +0 mA Injected current on any other pin –5 +5 Electrical characteristics STM32F405xx, STM32F407xx 110/185 DocID022152 Rev 4 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. Table 47. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 V VIH (1) Input high level voltage 2.0 - - VIL Input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - - 0.3VDD VIH (1) Input high level voltage 0.7VDD - - - - Vhys I/O Schmitt trigger voltage hysteresis(2) - 200 - IO FT Schmitt trigger voltage mV hysteresis(2) 5% VDD (3) - - Ilkg I/O input leakage current (4) VSS ≤ VIN ≤ VDD - - ±1 μA I/O FT input leakage current (4) VIN = 5 V - - 3 RPU Weak pull-up equivalent resistor(5) All pins except for PA10 and PB12 VIN = VSS 30 40 50 kΩ PA10 and PB12 8 11 15 RPD Weak pull-down equivalent resistor All pins except for PA10 and PB12 VIN = VDD 30 40 50 PA10 and PB12 8 11 15 CIO (6) I/O pin capacitance 5 pF 1. Tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 6. Guaranteed by design, not tested in production. DocID022152 Rev 4 111/185 STM32F405xx, STM32F407xx Electrical characteristics In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 49, respectively. Table 48. Output voltage characteristics(1) 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Symbol Parameter Conditions Min Max Unit VOL (2) 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port IIO =+ 8mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 - VOL (2)(4) 4. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 2.7 V < VDD < 3.6 V - 1.3 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–1.3 - VOL (2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 2 V < VDD < 2.7 V - 0.4 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - Electrical characteristics STM32F405xx, STM32F407xx 112/185 DocID022152 Rev 4 Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 49. I/O AC characteristics(1)(2)(3) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit 00 fmax(IO)out Maximum frequency(4) CL = 50 pF, VDD > 2.70 V - - 2 MHz CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - TBD CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 1.8 V to 3.6 V - - TBD ns tr(IO)out Output low to high level rise time - - TBD 01 fmax(IO)out Maximum frequency(4) CL = 50 pF, VDD > 2.70 V - - 25 MHz CL = 50 pF, VDD > 1.8 V - - 12.5(5) CL = 10 pF, VDD > 2.70 V - - 50(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, VDD < 2.7 V - - TBD ns CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 50 pF, VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 fmax(IO)out Maximum frequency(4) CL = 40 pF, VDD > 2.70 V - - 50(5) MHz CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD ns tr(IO)out Output low to high level rise time CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD DocID022152 Rev 4 113/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 37. I/O AC characteristics definition 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 47). Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. 11 Fmax(IO)ou t Maximum frequency(4) CL = 30 pF, VDD > 2.70 V - - 100(5) MHz CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.70 V - - 200(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD ns CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD - tEXTIpw Pulse width of external signals detected by the EXTI controller 10 - - ns 1. Based on characterization data, not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. TBD stands for “to be defined”. 4. The maximum frequency is defined in Figure 37. 5. For maximum frequencies above 50 MHz, the compensation cell should be used. Table 49. I/O AC characteristics(1)(2)(3) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit ai14131 10% 90% 50% tr(IO)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T tr(IO)out Electrical characteristics STM32F405xx, STM32F407xx 114/185 DocID022152 Rev 4 Figure 38. Recommended NRST pin protection 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 50. Otherwise the reset is not taken into account by the device. 5.3.18 TIM timer characteristics The parameters given in Table 51 and Table 52 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) (1) 1. Guaranteed by design, not tested in production. NRST Input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 V VIH(NRST) (1) NRST Input high level voltage 2 - - VIL(NRST) (1) NRST Input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - 0.3VDD VIH(NRST) (1) NRST Input high level voltage 0.7VDD - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV RPU Weak pull-up equivalent resistor(2) 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). VIN = VSS 30 40 50 kΩ VF(NRST) (1) NRST Input filtered pulse - - 100 ns VNF(NRST) (1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - μs ai14132c STM32Fxxx NRST(2) RPU VDD Filter Internal Reset 0.1 μF External reset circuit(1) DocID022152 Rev 4 115/185 STM32F405xx, STM32F407xx Electrical characteristics Table 51. Characteristics of TIMx connected to the APB1 domain(1) 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz 1 - tTIMxCLK 11.9 - ns AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz 1 - tTIMxCLK 23.8 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 84 MHz APB1= 42 MHz 0 fTIMxCLK/2 MHz 0 42 MHz ResTIM Timer resolution - 16/32 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 0.0119 780 μs 32-bit counter clock period when internal clock is selected 1 - tTIMxCLK 0.0119 51130563 μs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 51.1 s Electrical characteristics STM32F405xx, STM32F407xx 116/185 DocID022152 Rev 4 5.3.19 Communications interfaces I2C interface characteristics The STM32F405xx and STM32F407xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 52. Characteristics of TIMx connected to the APB2 domain(1) 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz 1 - tTIMxCLK 5.95 - ns AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz 1 - tTIMxCLK 11.9 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 168 MHz APB2 = 84 MHz 0 fTIMxCLK/2 MHz 0 84 MHz ResTIM Timer resolution - 16 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK tMAX_COUNT Maximum possible count - 32768 tTIMxCLK Table 53. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - μs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) - 0 900(4) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 DocID022152 Rev 4 117/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 39. I2C bus AC waveforms and measurement circuit 1. Rs= series protection resistor. 2. Rp = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. th(STA) Start condition hold time 4.0 - 0.6 - μs tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. Table 53. I2C characteristics (continued) Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max ai14979c S TAR T SD A RP I²C bus VDD_I2C STM32Fxx SDA SCL tf(SDA) tr(SDA) SCL th(STA) tw(SCLH) tw(SCLL) tsu(SDA) tr(SCL) tf(SCL) th(SDA) S TAR T REPEATED t S TAR T su(STA) tsu(STO) S TOP tw(STO:STA) VDD_I2C RP RS RS Electrical characteristics STM32F405xx, STM32F407xx 118/185 DocID022152 Rev 4 SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. fSCL (kHz) I2C_CCR value RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE Table 55. SPI dynamic characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SPI clock frequency Master mode, SPI1, 2.7V < VDD < 3.6V - - 42 MHz Slave mode, SPI1, 2.7V < VDD < 3.6V 42 1/tc(SCK) Master mode, SPI1/2/3, 1.7V < VDD < 3.6V - - 21 Slave mode, SPI1/2/3, 1.7V < VDD < 3.6V 21 Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % DocID022152 Rev 4 119/185 STM32F405xx, STM32F407xx Electrical characteristics tw(SCKH) SCK high and low time Master mode, SPI presc = 2, 2.7V < VDD < 3.6V TPCLK-0.5 TPCLK TPCLK+0.5 ns tw(SCKL) Master mode, SPI presc = 2, 1.7V < VDD < 3.6V TPCLK-2 TPCLK TPCLK+2 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4 x TPCLK - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2 x TPCLK tsu(MI) Data input setup time Master mode 6.5 - - tsu(SI) Slave mode 2.5 - - th(MI) Data input hold time Master mode 2.5 - - th(SI) Slave mode 4 - - ta(SO) (2) Data output access time Slave mode, SPI presc = 2 0 - 4 x TPCLK tdis(SO) (3) Data output disable time Slave mode, SPI1, 2.7V < VDD < 3.6V 0 - 7.5 Slave mode, SPI1/2/3 1.7V < VDD < 3.6V 0 - 16.5 tv(SO) th(SO) Data output valid/hold time Slave mode (after enable edge), SPI1, 2.7V < VDD < 3.6V - 11 13 Slave mode (after enable edge), SPI2/3, 2.7V < VDD < 3.6V - 12 16.5 Slave mode (after enable edge), SPI1, 1.7V < VDD < 3.6V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7V < VDD < 3.6V - 18 20.5 tv(MO) Data output valid time Master mode (after enable edge), SPI1 , 2.7V < VDD < 3.6V - - 2.5 Master mode (after enable edge), SPI1/2/3 , 1.7V < VDD < 3.6V - - 4.5 th(MO) Data output hold time Master mode (after enable edge) 0 - - 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Electrical characteristics STM32F405xx, STM32F407xx 120/185 DocID022152 Rev 4 Figure 40. SPI timing diagram - slave mode and CPHA = 0 Figure 41. SPI timing diagram - slave mode and CPHA = 1 ai14134c SCK Input CPHA=0 MOSI INPUT MISO OUT PUT CPHA=0 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN NSS input tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) ai14135 SCK Input CPHA=1 MOSI INPUT MISO OUT PUT CPHA=1 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) NSS input DocID022152 Rev 4 121/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 42. SPI timing diagram - master mode ai14136 SCK Input CPHA=0 MOSI OUTUT MISO INPUT CPHA=0 MSBIN MSB OUT BIT6 IN LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High SCK Input CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) Electrical characteristics STM32F405xx, STM32F407xx 122/185 DocID022152 Rev 4 I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). FS maximum value is supported for each mode/condition. Table 56. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S main clock output - 256 x 8K 256 x FS (2) MHz fCK I2S clock frequency Master data: 32 bits - 64 x FS MHz Slave data: 32 bits - 64 x FS DCK I2S clock frequency duty cycle Slave receiver 30 70 % tv(WS) WS valid time Master mode 0 6 ns th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 7.5 - tsu(SD_SR) Slave receiver 2 - th(SD_MR) Data input hold time Master receiver 0 - th(SD_SR) Slave receiver 0 - tv(SD_ST) th(SD_ST) Data output valid time Slave transmitter (after enable edge) - 27 tv(SD_MT) Master transmitter (after enable edge) - 20 th(SD_MT) Data output hold time Master transmitter (after enable edge) 2.5 - 1. Data based on characterization results, not tested in production. 2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency). DocID022152 Rev 4 123/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 43. I2S slave timing diagram (Philips protocol) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. CK Input CPOL = 0 CPOL = 1 tc(CK) WS input SDtransmit SDreceive tw(CKH) tw(CKL) tsu(WS) tv(SD_ST) th(SD_ST) th(WS) tsu(SD_SR) th(SD_SR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14881b LSB receive(2) LSB transmit(2) CK output CPOL = 0 CPOL = 1 tc(CK) WS output SDreceive SDtransmit tw(CKH) tw(CKL) tsu(SD_MR) tv(SD_MT) th(SD_MT) th(WS) th(SD_MR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14884b tf(CK) tr(CK) tv(WS) LSB receive(2) LSB transmit(2) Electrical characteristics STM32F405xx, STM32F407xx 124/185 DocID022152 Rev 4 Figure 45. USB OTG FS timings: definition of data signal rise and fall time Table 57. USB OTG FS startup time Symbol Parameter Max Unit tSTARTUP (1) 1. Guaranteed by design, not tested in production. USB OTG FS transceiver startup time 1 μs Table 58. USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min.(1) 1. All the voltages are measured from the local ground potential. Typ. Max.(1) Unit Input levels VDD USB OTG FS operating voltage 3.0(2) 2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. - 3.6 V VDI (3) 3. Guaranteed by design, not tested in production. Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM V (3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE (3) Single ended receiver threshold 1.3 - 2.0 Output levels VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) 4. RL is the load connected on the USB OTG FS drivers - - 0.3 V VOH Static output level high RL of 15 kΩ to VSS (4) 2.8 - 3.6 RPD PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) VIN = VDD 17 21 24 kΩ PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) 0.65 1.1 2.0 RPU PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 ai14137 tf Differen tial Data L ines VSS VCRS tr Crossover points DocID022152 Rev 4 125/185 STM32F405xx, STM32F407xx Electrical characteristics USB HS characteristics Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 61 and VDD supply voltage conditions summarized in Table 60, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/outputcharacteristics. Table 59. USB OTG FS electrical characteristics(1) 1. Guaranteed by design, not tested in production. Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). CL = 50 pF 4 20 ns tf Fall time(2) CL = 50 pF 4 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V Table 60. USB HS DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD USB OTG HS operating voltage 2.7 3.6 V Table 61. USB HS clock timing parameters(1) Parameter Symbol Min Nominal Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 MHz Frequency (first transition) 8-bit ±10% FSTART_8BIT 54 60 66 MHz Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 % Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 % Time to reach the steady state frequency and duty cycle after the first transition TSTEADY - - 1.4 ms Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 ms Host TSTART_HOST - - - PHY preparation time after the first transition of the input clock TPREP - - - μs Electrical characteristics STM32F405xx, STM32F407xx 126/185 DocID022152 Rev 4 Figure 46. ULPI timing diagram Ethernet characteristics Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. 1. Guaranteed by design, not tested in production. Table 62. ULPI timing Parameter Symbol Value(1) 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Unit Min. Max. Control in (ULPI_DIR) setup time tSC - 2.0 ns Control in (ULPI_NXT) setup time - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0 - Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tSD tHD tSC tHC ai17361c tDC DocID022152 Rev 4 127/185 STM32F405xx, STM32F407xx Electrical characteristics Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet SMI timing diagram Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram Table 63. Ethernet DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD Ethernet operating voltage 2.7 3.6 V Table 64. Dynamic characteristics: Ehternet MAC signals for SMI(1) 1. Data based on characterization results, not tested in production. Symbol Parameter Min Typ Max Unit tMDC MDC cycle time( 2.38 MHz) 411 420 425 ns Td(MDIO) Write data valid time 6 10 13 tsu(MDIO) Read data setup time 12 - - th(MDIO) Read data hold time 0 - - MS31384V1 ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO) RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) ai15667 Electrical characteristics STM32F405xx, STM32F407xx 128/185 DocID022152 Rev 4 Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. Figure 49. Ethernet MII timing diagram Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.5 ns Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) 1. Data based on characterization results, not tested in production. Symbol Parameter Min Typ Max Unit tsu(RXD) Receive data setup time 9 - ns tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER td(TXEN) td(TXD) tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) ai15668 MII_TX_CLK MII_TX_EN MII_TXD[3:0] DocID022152 Rev 4 129/185 STM32F405xx, STM32F407xx Electrical characteristics CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 67. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1.8(1) - 3.6 V VREF+ Positive reference voltage 1.8(1)(2)(3) - VDDA V fADC ADC clock frequency VDDA = 1.8(1)(3) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V(3) 0.6 30 36 MHz fTRIG (4) External trigger frequency fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - 17 1/fADC VAIN Conversion voltage range(5) 0 (VSSA or VREFtied to ground) - VREF+ V RAIN (4) External input impedance See Equation 1 for details - - 50 κΩ RADC (4)(6) Sampling switch resistance - - 6 κΩ CADC (4) Internal sample and hold capacitor - 4 - pF tlat (4) Injection trigger conversion latency fADC = 30 MHz - - 0.100 μs - - 3(7) 1/fADC tlatr (4) Regular trigger conversion latency fADC = 30 MHz - - 0.067 μs - - 2(7) 1/fADC tS (4) Sampling time fADC = 30 MHz 0.100 - 16 μs 3 - 480 1/fADC tSTAB (4) Power-up time - 2 3 μs Electrical characteristics STM32F405xx, STM32F407xx 130/185 DocID022152 Rev 4 Equation 1: RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. tCONV (4) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.50 - 16.40 μs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 μs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 μs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 μs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC fS (4) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+ (4) ADC VREF DC current consumption in conversion mode - 300 500 μA IVDDA (4) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. VDDA -VREF+ < 1.2 V. 4. Based on characterization, not tested in production. 5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit RAIN (k – 0.5) fADC CADC 2N + 2 × × ln( ) = -------------------------------------------------------------- – RADC DocID022152 Rev 4 131/185 STM32F405xx, STM32F407xx Electrical characteristics a Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Figure 50. ADC accuracy characteristics 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. Table 68. ADC accuracy at fADC = 30 MHz(1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Based on characterization, not tested in production. Unit ET Total unadjusted error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 ai14395c EO EG 1L SBIDEAL 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VSSA VDDA VREF+ 4096 (or depending on package)] VDDA 4096 [1LSB IDEAL = Electrical characteristics STM32F405xx, STM32F407xx 132/185 DocID022152 Rev 4 EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. ai17534 VDD STM32F AINx IL±1 μA 0.6 V VT RAIN (1) Cparasitic VAIN 0.6 V VT RADC (1) CADC(1) 12-bit converter Sample and hold ADC converter DocID022152 Rev 4 133/185 STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. VREF+ STM32F VDDA VSSA/V REF- 1 μF // 10 nF 1 μF // 10 nF ai17535 (See note 1) (See note 1) VREF+/VDDA STM32F 1 μF // 10 nF VREF–/VSSA ai17536 (See note 1) (See note 1) Electrical characteristics STM32F405xx, STM32F407xx 134/185 DocID022152 Rev 4 5.3.21 Temperature sensor characteristics 5.3.22 VBAT monitoring characteristics Table 69. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit TL (1) VSENSE linearity with temperature - ±1 ±2 °C Avg_Slope(1) Average slope - 2.5 mV/°C V25 (1) Voltage at 25 °C - 0.76 V tSTART (2) Startup time - 6 10 μs TS_temp (3)(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - μs 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Table 70. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F Table 71. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 2 - Er(1) Error on Q –1 - +1 % TS_vbat (2)(2) ADC sampling time when reading the VBAT 1 mV accuracy 5 - - μs 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. DocID022152 Rev 4 135/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.23 Embedded reference voltage The parameters given in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. 5.3.24 DAC electrical characteristics Table 72. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V TS_vrefint (1) ADC sampling time when reading the internal reference voltage 10 - - μs VRERINT_s (2) Internal reference voltage spread over the temperature range VDD = 3 V - 3 5 mV TCoeff (2) Temperature coefficient - 30 50 ppm/°C tSTART (2) Startup time - 6 10 μs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. Table 73. Internal reference voltage calibration values Symbol Parameter Memory address VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B Table 74. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VREF+ ≤ VDDA VSSA Ground 0 - 0 V RLOAD (2) Resistive load with buffer ON 5 - - kΩ RO (2) Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD (2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON 0.2 - - V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V Electrical characteristics STM32F405xx, STM32F407xx 136/185 DocID022152 Rev 4 DAC_OUT min(2) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV It gives the maximum output DAC_OUT excursion of the DAC. max(2) Higher DAC_OUT voltage with buffer OFF - - VREF+ – 1LSB V IVREF+ (4) DAC DC VREF current consumption in quiescent mode (Standby mode) - 170 240 μA With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs IDDA (4) DAC DC VDDA current consumption in quiescent mode(3) - 280 380 μA With no load, middle code (0x800) on the inputs - 475 625 μA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(4) Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±10 mV Given for the DAC in 12-bit configuration - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration tSETTLING (4) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±4LSB - 3 6 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments DocID022152 Rev 4 137/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 54. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.25 FSMC characteristics Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP (4) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments RLOAD CLOAD Buffered/Non-buffered DAC DACx_OUT Buffer(1) 12-bit digital to analog converter ai17157 Electrical characteristics STM32F405xx, STM32F407xx 138/185 DocID022152 Rev 4 Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 2THCLK–0.5 2 THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 3 ns tw(NOE) FSMC_NOE low time 2THCLK–2 2THCLK+ 2 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 4.5 ns th(A_NOE) Address hold time after FSMC_NOE high 4 - ns Data FSMC_NE FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) t h(Data_NE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) FSMC_NWE tsu(Data_NE) tw(NE) ai14991c tv(NOE_NE) t w(NOE) t h(NE_NOE) th(Data_NOE) t h(A_NOE) t h(BL_NOE) tsu(Data_NOE) FSMC_NADV(1) t v(NADV_NE) tw(NADV) DocID022152 Rev 4 139/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+4 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK 3THCLK+ 4 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK+0.5 ns tw(NWE) FSMC_NWE low time THCLK–1 THCLK+2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK–1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) tv(Data_NE) tw(NE) ai14990 FSMC_NADV(1) t v(NADV_NE) tw(NADV) Electrical characteristics STM32F405xx, STM32F407xx 140/185 DocID022152 Rev 4 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms th(A_NWE) Address hold time after FSMC_NWE high THCLK– 2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK– 1 - ns tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK–1 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK+0.5 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK–1 3THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2THCLK–0.5 2THCLK+0.5 ns tw(NOE) FSMC_NOE low time THCLK–1 THCLK+1 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 3 ns Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) NBL Data FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NE) FSMC_A[25:16] Address tv(A_NE) FSMC_NWE t v(A_NE) ai14892b Address FSMC_NADV t v(NADV_NE) tw(NADV) tsu(Data_NE) th(AD_NADV) FSMC_NE FSMC_NOE tw(NE) t w(NOE) tv(NOE_NE) t h(NE_NOE) th(A_NOE) th(BL_NOE) tsu(Data_NOE) th(Data_NOE) DocID022152 Rev 4 141/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+1 ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK–1 - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 2 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+4 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 4THCLK–0.5 4THCLK+3 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK -0.5 ns tw(NWE) FSMC_NWE low tim e 2THCLK–0.5 2THCLK+3 ns Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:16] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) t v(A_NE) tw(NE) ai14891B Address FSMC_NADV t v(NADV_NE) tw(NADV) t v(Data_NADV) th(AD_NADV) Electrical characteristics STM32F405xx, STM32F407xx 142/185 DocID022152 Rev 4 Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+ 1 ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) THCLK–2 - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK–2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK–0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) DocID022152 Rev 4 143/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NOE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893g Electrical characteristics STM32F405xx, STM32F407xx 144/185 DocID022152 Rev 4 Figure 60. Synchronous multiplexed PSRAM write timings th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 80. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NWE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-NBLH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14992g td(CLKL-Data) FSMC_NBL DocID022152 Rev 4 145/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK –0.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns Table 80. Synchronous multiplexed PSRAM write timings(1)(2) FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894f FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) Electrical characteristics STM32F405xx, STM32F407xx 146/185 DocID022152 Rev 4 Figure 62. Synchronous non-multiplexed PSRAM write timings td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14993g FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-Data) FSMC_NBL td(CLKL-NBLH) DocID022152 Rev 4 147/185 STM32F405xx, STM32F407xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns Electrical characteristics STM32F405xx, STM32F407xx 148/185 DocID022152 Rev 4 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NWE tw(NOE) FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2(1) FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NOE) tsu(D-NOE) th(NOE-D) tv(NCEx-A) td(NREG-NCEx) td(NIORD-NCEx) th(NCEx-AI) th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) ai14895b td(NCE4_1-NWE) tw(NWE) th(NWE-D) tv(NCE4_1-A) td(NREG-NCE4_1) td(NIORD-NCE4_1) th(NCE4_1-AI) MEMxHIZ =1 tv(NWE-D) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) ai14896b FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) td(D-NWE) FSMC_NCE4_2 High DocID022152 Rev 4 149/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access 1. Only data bits 0...7 are read (bits 8...15 are disregarded). td(NCE4_1-NOE) tw(NOE) tsu(D-NOE) th(NOE-D) tv(NCE4_1-A) th(NCE4_1-AI) td(NREG-NCE4_1) th(NCE4_1-NREG) ai14897b FSMC_NWE FSMC_NOE FSMC_D[15:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NOE-NCE4_1) High Electrical characteristics STM32F405xx, STM32F407xx 150/185 DocID022152 Rev 4 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access tw(NWE) tv(NCE4_1-A) td(NREG-NCE4_1) th(NCE4_1-AI) th(NCE4_1-NREG) tv(NWE-D) ai14898b FSMC_NWE FSMC_NOE FSMC_D[7:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) High td(NCE4_1-NWE) td(NIORD-NCE4_1) tw(NIORD) tsu(D-NIORD) td(NIORD-D) tv(NCEx-A) th(NCE4_1-AI) ai14899B FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD DocID022152 Rev 4 151/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access td(NCE4_1-NIOWR) tw(NIOWR) tv(NCEx-A) th(NCE4_1-AI) th(NIOWR-D) ATTxHIZ =1 tv(NIOWR-D) ai14900c FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+4 - ns